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1 | #include <linux/init.h> | |
2 | #include <linux/bitops.h> | |
3 | #include <linux/mm.h> | |
4 | ||
5 | #include <linux/io.h> | |
6 | #include <asm/processor.h> | |
7 | #include <asm/apic.h> | |
8 | #include <asm/cpu.h> | |
9 | #include <asm/pci-direct.h> | |
10 | ||
11 | #ifdef CONFIG_X86_64 | |
12 | # include <asm/numa_64.h> | |
13 | # include <asm/mmconfig.h> | |
14 | # include <asm/cacheflush.h> | |
15 | #endif | |
16 | ||
17 | #include "cpu.h" | |
18 | ||
19 | #ifdef CONFIG_X86_32 | |
20 | /* | |
21 | * B step AMD K6 before B 9730xxxx have hardware bugs that can cause | |
22 | * misexecution of code under Linux. Owners of such processors should | |
23 | * contact AMD for precise details and a CPU swap. | |
24 | * | |
25 | * See http://www.multimania.com/poulot/k6bug.html | |
26 | * http://www.amd.com/K6/k6docs/revgd.html | |
27 | * | |
28 | * The following test is erm.. interesting. AMD neglected to up | |
29 | * the chip setting when fixing the bug but they also tweaked some | |
30 | * performance at the same time.. | |
31 | */ | |
32 | ||
33 | extern void vide(void); | |
34 | __asm__(".align 4\nvide: ret"); | |
35 | ||
36 | static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c) | |
37 | { | |
38 | /* | |
39 | * General Systems BIOSen alias the cpu frequency registers | |
40 | * of the Elan at 0x000df000. Unfortuantly, one of the Linux | |
41 | * drivers subsequently pokes it, and changes the CPU speed. | |
42 | * Workaround : Remove the unneeded alias. | |
43 | */ | |
44 | #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ | |
45 | #define CBAR_ENB (0x80000000) | |
46 | #define CBAR_KEY (0X000000CB) | |
47 | if (c->x86_model == 9 || c->x86_model == 10) { | |
48 | if (inl(CBAR) & CBAR_ENB) | |
49 | outl(0 | CBAR_KEY, CBAR); | |
50 | } | |
51 | } | |
52 | ||
53 | ||
54 | static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c) | |
55 | { | |
56 | u32 l, h; | |
57 | int mbytes = num_physpages >> (20-PAGE_SHIFT); | |
58 | ||
59 | if (c->x86_model < 6) { | |
60 | /* Based on AMD doc 20734R - June 2000 */ | |
61 | if (c->x86_model == 0) { | |
62 | clear_cpu_cap(c, X86_FEATURE_APIC); | |
63 | set_cpu_cap(c, X86_FEATURE_PGE); | |
64 | } | |
65 | return; | |
66 | } | |
67 | ||
68 | if (c->x86_model == 6 && c->x86_mask == 1) { | |
69 | const int K6_BUG_LOOP = 1000000; | |
70 | int n; | |
71 | void (*f_vide)(void); | |
72 | unsigned long d, d2; | |
73 | ||
74 | printk(KERN_INFO "AMD K6 stepping B detected - "); | |
75 | ||
76 | /* | |
77 | * It looks like AMD fixed the 2.6.2 bug and improved indirect | |
78 | * calls at the same time. | |
79 | */ | |
80 | ||
81 | n = K6_BUG_LOOP; | |
82 | f_vide = vide; | |
83 | rdtscl(d); | |
84 | while (n--) | |
85 | f_vide(); | |
86 | rdtscl(d2); | |
87 | d = d2-d; | |
88 | ||
89 | if (d > 20*K6_BUG_LOOP) | |
90 | printk(KERN_CONT | |
91 | "system stability may be impaired when more than 32 MB are used.\n"); | |
92 | else | |
93 | printk(KERN_CONT "probably OK (after B9730xxxx).\n"); | |
94 | printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n"); | |
95 | } | |
96 | ||
97 | /* K6 with old style WHCR */ | |
98 | if (c->x86_model < 8 || | |
99 | (c->x86_model == 8 && c->x86_mask < 8)) { | |
100 | /* We can only write allocate on the low 508Mb */ | |
101 | if (mbytes > 508) | |
102 | mbytes = 508; | |
103 | ||
104 | rdmsr(MSR_K6_WHCR, l, h); | |
105 | if ((l&0x0000FFFF) == 0) { | |
106 | unsigned long flags; | |
107 | l = (1<<0)|((mbytes/4)<<1); | |
108 | local_irq_save(flags); | |
109 | wbinvd(); | |
110 | wrmsr(MSR_K6_WHCR, l, h); | |
111 | local_irq_restore(flags); | |
112 | printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n", | |
113 | mbytes); | |
114 | } | |
115 | return; | |
116 | } | |
117 | ||
118 | if ((c->x86_model == 8 && c->x86_mask > 7) || | |
119 | c->x86_model == 9 || c->x86_model == 13) { | |
120 | /* The more serious chips .. */ | |
121 | ||
122 | if (mbytes > 4092) | |
123 | mbytes = 4092; | |
124 | ||
125 | rdmsr(MSR_K6_WHCR, l, h); | |
126 | if ((l&0xFFFF0000) == 0) { | |
127 | unsigned long flags; | |
128 | l = ((mbytes>>2)<<22)|(1<<16); | |
129 | local_irq_save(flags); | |
130 | wbinvd(); | |
131 | wrmsr(MSR_K6_WHCR, l, h); | |
132 | local_irq_restore(flags); | |
133 | printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n", | |
134 | mbytes); | |
135 | } | |
136 | ||
137 | return; | |
138 | } | |
139 | ||
140 | if (c->x86_model == 10) { | |
141 | /* AMD Geode LX is model 10 */ | |
142 | /* placeholder for any needed mods */ | |
143 | return; | |
144 | } | |
145 | } | |
146 | ||
147 | static void __cpuinit amd_k7_smp_check(struct cpuinfo_x86 *c) | |
148 | { | |
149 | #ifdef CONFIG_SMP | |
150 | /* calling is from identify_secondary_cpu() ? */ | |
151 | if (!c->cpu_index) | |
152 | return; | |
153 | ||
154 | /* | |
155 | * Certain Athlons might work (for various values of 'work') in SMP | |
156 | * but they are not certified as MP capable. | |
157 | */ | |
158 | /* Athlon 660/661 is valid. */ | |
159 | if ((c->x86_model == 6) && ((c->x86_mask == 0) || | |
160 | (c->x86_mask == 1))) | |
161 | goto valid_k7; | |
162 | ||
163 | /* Duron 670 is valid */ | |
164 | if ((c->x86_model == 7) && (c->x86_mask == 0)) | |
165 | goto valid_k7; | |
166 | ||
167 | /* | |
168 | * Athlon 662, Duron 671, and Athlon >model 7 have capability | |
169 | * bit. It's worth noting that the A5 stepping (662) of some | |
170 | * Athlon XP's have the MP bit set. | |
171 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for | |
172 | * more. | |
173 | */ | |
174 | if (((c->x86_model == 6) && (c->x86_mask >= 2)) || | |
175 | ((c->x86_model == 7) && (c->x86_mask >= 1)) || | |
176 | (c->x86_model > 7)) | |
177 | if (cpu_has_mp) | |
178 | goto valid_k7; | |
179 | ||
180 | /* If we get here, not a certified SMP capable AMD system. */ | |
181 | ||
182 | /* | |
183 | * Don't taint if we are running SMP kernel on a single non-MP | |
184 | * approved Athlon | |
185 | */ | |
186 | WARN_ONCE(1, "WARNING: This combination of AMD" | |
187 | " processors is not suitable for SMP.\n"); | |
188 | if (!test_taint(TAINT_UNSAFE_SMP)) | |
189 | add_taint(TAINT_UNSAFE_SMP); | |
190 | ||
191 | valid_k7: | |
192 | ; | |
193 | #endif | |
194 | } | |
195 | ||
196 | static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c) | |
197 | { | |
198 | u32 l, h; | |
199 | ||
200 | /* | |
201 | * Bit 15 of Athlon specific MSR 15, needs to be 0 | |
202 | * to enable SSE on Palomino/Morgan/Barton CPU's. | |
203 | * If the BIOS didn't enable it already, enable it here. | |
204 | */ | |
205 | if (c->x86_model >= 6 && c->x86_model <= 10) { | |
206 | if (!cpu_has(c, X86_FEATURE_XMM)) { | |
207 | printk(KERN_INFO "Enabling disabled K7/SSE Support.\n"); | |
208 | rdmsr(MSR_K7_HWCR, l, h); | |
209 | l &= ~0x00008000; | |
210 | wrmsr(MSR_K7_HWCR, l, h); | |
211 | set_cpu_cap(c, X86_FEATURE_XMM); | |
212 | } | |
213 | } | |
214 | ||
215 | /* | |
216 | * It's been determined by AMD that Athlons since model 8 stepping 1 | |
217 | * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx | |
218 | * As per AMD technical note 27212 0.2 | |
219 | */ | |
220 | if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { | |
221 | rdmsr(MSR_K7_CLK_CTL, l, h); | |
222 | if ((l & 0xfff00000) != 0x20000000) { | |
223 | printk(KERN_INFO | |
224 | "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", | |
225 | l, ((l & 0x000fffff)|0x20000000)); | |
226 | wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); | |
227 | } | |
228 | } | |
229 | ||
230 | set_cpu_cap(c, X86_FEATURE_K7); | |
231 | ||
232 | amd_k7_smp_check(c); | |
233 | } | |
234 | #endif | |
235 | ||
236 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
237 | static int __cpuinit nearby_node(int apicid) | |
238 | { | |
239 | int i, node; | |
240 | ||
241 | for (i = apicid - 1; i >= 0; i--) { | |
242 | node = apicid_to_node[i]; | |
243 | if (node != NUMA_NO_NODE && node_online(node)) | |
244 | return node; | |
245 | } | |
246 | for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { | |
247 | node = apicid_to_node[i]; | |
248 | if (node != NUMA_NO_NODE && node_online(node)) | |
249 | return node; | |
250 | } | |
251 | return first_node(node_online_map); /* Shouldn't happen */ | |
252 | } | |
253 | #endif | |
254 | ||
255 | /* | |
256 | * Fixup core topology information for | |
257 | * (1) AMD multi-node processors | |
258 | * Assumption: Number of cores in each internal node is the same. | |
259 | * (2) AMD processors supporting compute units | |
260 | */ | |
261 | #ifdef CONFIG_X86_HT | |
262 | static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) | |
263 | { | |
264 | u32 nodes, cores_per_cu; | |
265 | u8 node_id; | |
266 | int cpu = smp_processor_id(); | |
267 | ||
268 | /* get information required for multi-node processors */ | |
269 | if (cpu_has(c, X86_FEATURE_TOPOEXT)) { | |
270 | u32 eax, ebx, ecx, edx; | |
271 | ||
272 | cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); | |
273 | nodes = ((ecx >> 8) & 7) + 1; | |
274 | node_id = ecx & 7; | |
275 | ||
276 | /* get compute unit information */ | |
277 | smp_num_siblings = ((ebx >> 8) & 3) + 1; | |
278 | c->compute_unit_id = ebx & 0xff; | |
279 | cores_per_cu = ((ebx >> 8) & 3) + 1; | |
280 | } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { | |
281 | u64 value; | |
282 | ||
283 | rdmsrl(MSR_FAM10H_NODE_ID, value); | |
284 | nodes = ((value >> 3) & 7) + 1; | |
285 | node_id = value & 7; | |
286 | } else | |
287 | return; | |
288 | ||
289 | /* fixup multi-node processor information */ | |
290 | if (nodes > 1) { | |
291 | u32 cores_per_node; | |
292 | u32 cus_per_node; | |
293 | ||
294 | set_cpu_cap(c, X86_FEATURE_AMD_DCM); | |
295 | cores_per_node = c->x86_max_cores / nodes; | |
296 | cus_per_node = cores_per_node / cores_per_cu; | |
297 | ||
298 | /* store NodeID, use llc_shared_map to store sibling info */ | |
299 | per_cpu(cpu_llc_id, cpu) = node_id; | |
300 | ||
301 | /* core id to be in range from 0 to (cores_per_node - 1) */ | |
302 | c->cpu_core_id %= cores_per_node; | |
303 | c->compute_unit_id %= cus_per_node; | |
304 | } | |
305 | } | |
306 | #endif | |
307 | ||
308 | /* | |
309 | * On a AMD dual core setup the lower bits of the APIC id distingush the cores. | |
310 | * Assumes number of cores is a power of two. | |
311 | */ | |
312 | static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c) | |
313 | { | |
314 | #ifdef CONFIG_X86_HT | |
315 | unsigned bits; | |
316 | int cpu = smp_processor_id(); | |
317 | ||
318 | bits = c->x86_coreid_bits; | |
319 | /* Low order bits define the core id (index of core in socket) */ | |
320 | c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); | |
321 | /* Convert the initial APIC ID into the socket ID */ | |
322 | c->phys_proc_id = c->initial_apicid >> bits; | |
323 | /* use socket ID also for last level cache */ | |
324 | per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; | |
325 | amd_get_topology(c); | |
326 | #endif | |
327 | } | |
328 | ||
329 | int amd_get_nb_id(int cpu) | |
330 | { | |
331 | int id = 0; | |
332 | #ifdef CONFIG_SMP | |
333 | id = per_cpu(cpu_llc_id, cpu); | |
334 | #endif | |
335 | return id; | |
336 | } | |
337 | EXPORT_SYMBOL_GPL(amd_get_nb_id); | |
338 | ||
339 | static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c) | |
340 | { | |
341 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
342 | int cpu = smp_processor_id(); | |
343 | int node; | |
344 | unsigned apicid = c->apicid; | |
345 | ||
346 | node = per_cpu(cpu_llc_id, cpu); | |
347 | ||
348 | if (apicid_to_node[apicid] != NUMA_NO_NODE) | |
349 | node = apicid_to_node[apicid]; | |
350 | if (!node_online(node)) { | |
351 | /* Two possibilities here: | |
352 | - The CPU is missing memory and no node was created. | |
353 | In that case try picking one from a nearby CPU | |
354 | - The APIC IDs differ from the HyperTransport node IDs | |
355 | which the K8 northbridge parsing fills in. | |
356 | Assume they are all increased by a constant offset, | |
357 | but in the same order as the HT nodeids. | |
358 | If that doesn't result in a usable node fall back to the | |
359 | path for the previous case. */ | |
360 | ||
361 | int ht_nodeid = c->initial_apicid; | |
362 | ||
363 | if (ht_nodeid >= 0 && | |
364 | apicid_to_node[ht_nodeid] != NUMA_NO_NODE) | |
365 | node = apicid_to_node[ht_nodeid]; | |
366 | /* Pick a nearby node */ | |
367 | if (!node_online(node)) | |
368 | node = nearby_node(apicid); | |
369 | } | |
370 | numa_set_node(cpu, node); | |
371 | #endif | |
372 | } | |
373 | ||
374 | static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c) | |
375 | { | |
376 | #ifdef CONFIG_X86_HT | |
377 | unsigned bits, ecx; | |
378 | ||
379 | /* Multi core CPU? */ | |
380 | if (c->extended_cpuid_level < 0x80000008) | |
381 | return; | |
382 | ||
383 | ecx = cpuid_ecx(0x80000008); | |
384 | ||
385 | c->x86_max_cores = (ecx & 0xff) + 1; | |
386 | ||
387 | /* CPU telling us the core id bits shift? */ | |
388 | bits = (ecx >> 12) & 0xF; | |
389 | ||
390 | /* Otherwise recompute */ | |
391 | if (bits == 0) { | |
392 | while ((1 << bits) < c->x86_max_cores) | |
393 | bits++; | |
394 | } | |
395 | ||
396 | c->x86_coreid_bits = bits; | |
397 | #endif | |
398 | } | |
399 | ||
400 | static void __cpuinit early_init_amd(struct cpuinfo_x86 *c) | |
401 | { | |
402 | early_init_amd_mc(c); | |
403 | ||
404 | /* | |
405 | * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate | |
406 | * with P/T states and does not stop in deep C-states | |
407 | */ | |
408 | if (c->x86_power & (1 << 8)) { | |
409 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); | |
410 | set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); | |
411 | } | |
412 | ||
413 | #ifdef CONFIG_X86_64 | |
414 | set_cpu_cap(c, X86_FEATURE_SYSCALL32); | |
415 | #else | |
416 | /* Set MTRR capability flag if appropriate */ | |
417 | if (c->x86 == 5) | |
418 | if (c->x86_model == 13 || c->x86_model == 9 || | |
419 | (c->x86_model == 8 && c->x86_mask >= 8)) | |
420 | set_cpu_cap(c, X86_FEATURE_K6_MTRR); | |
421 | #endif | |
422 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) | |
423 | /* check CPU config space for extended APIC ID */ | |
424 | if (cpu_has_apic && c->x86 >= 0xf) { | |
425 | unsigned int val; | |
426 | val = read_pci_config(0, 24, 0, 0x68); | |
427 | if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18))) | |
428 | set_cpu_cap(c, X86_FEATURE_EXTD_APICID); | |
429 | } | |
430 | #endif | |
431 | ||
432 | /* We need to do the following only once */ | |
433 | if (c != &boot_cpu_data) | |
434 | return; | |
435 | ||
436 | if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { | |
437 | ||
438 | if (c->x86 > 0x10 || | |
439 | (c->x86 == 0x10 && c->x86_model >= 0x2)) { | |
440 | u64 val; | |
441 | ||
442 | rdmsrl(MSR_K7_HWCR, val); | |
443 | if (!(val & BIT(24))) | |
444 | printk(KERN_WARNING FW_BUG "TSC doesn't count " | |
445 | "with P0 frequency!\n"); | |
446 | } | |
447 | } | |
448 | } | |
449 | ||
450 | static void __cpuinit init_amd(struct cpuinfo_x86 *c) | |
451 | { | |
452 | #ifdef CONFIG_SMP | |
453 | unsigned long long value; | |
454 | ||
455 | /* | |
456 | * Disable TLB flush filter by setting HWCR.FFDIS on K8 | |
457 | * bit 6 of msr C001_0015 | |
458 | * | |
459 | * Errata 63 for SH-B3 steppings | |
460 | * Errata 122 for all steppings (F+ have it disabled by default) | |
461 | */ | |
462 | if (c->x86 == 0xf) { | |
463 | rdmsrl(MSR_K7_HWCR, value); | |
464 | value |= 1 << 6; | |
465 | wrmsrl(MSR_K7_HWCR, value); | |
466 | } | |
467 | #endif | |
468 | ||
469 | early_init_amd(c); | |
470 | ||
471 | /* | |
472 | * Bit 31 in normal CPUID used for nonstandard 3DNow ID; | |
473 | * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway | |
474 | */ | |
475 | clear_cpu_cap(c, 0*32+31); | |
476 | ||
477 | #ifdef CONFIG_X86_64 | |
478 | /* On C+ stepping K8 rep microcode works well for copy/memset */ | |
479 | if (c->x86 == 0xf) { | |
480 | u32 level; | |
481 | ||
482 | level = cpuid_eax(1); | |
483 | if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) | |
484 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); | |
485 | ||
486 | /* | |
487 | * Some BIOSes incorrectly force this feature, but only K8 | |
488 | * revision D (model = 0x14) and later actually support it. | |
489 | * (AMD Erratum #110, docId: 25759). | |
490 | */ | |
491 | if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { | |
492 | u64 val; | |
493 | ||
494 | clear_cpu_cap(c, X86_FEATURE_LAHF_LM); | |
495 | if (!rdmsrl_amd_safe(0xc001100d, &val)) { | |
496 | val &= ~(1ULL << 32); | |
497 | wrmsrl_amd_safe(0xc001100d, val); | |
498 | } | |
499 | } | |
500 | ||
501 | } | |
502 | if (c->x86 >= 0x10) | |
503 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); | |
504 | ||
505 | /* get apicid instead of initial apic id from cpuid */ | |
506 | c->apicid = hard_smp_processor_id(); | |
507 | #else | |
508 | ||
509 | /* | |
510 | * FIXME: We should handle the K5 here. Set up the write | |
511 | * range and also turn on MSR 83 bits 4 and 31 (write alloc, | |
512 | * no bus pipeline) | |
513 | */ | |
514 | ||
515 | switch (c->x86) { | |
516 | case 4: | |
517 | init_amd_k5(c); | |
518 | break; | |
519 | case 5: | |
520 | init_amd_k6(c); | |
521 | break; | |
522 | case 6: /* An Athlon/Duron */ | |
523 | init_amd_k7(c); | |
524 | break; | |
525 | } | |
526 | ||
527 | /* K6s reports MCEs but don't actually have all the MSRs */ | |
528 | if (c->x86 < 6) | |
529 | clear_cpu_cap(c, X86_FEATURE_MCE); | |
530 | #endif | |
531 | ||
532 | /* Enable workaround for FXSAVE leak */ | |
533 | if (c->x86 >= 6) | |
534 | set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK); | |
535 | ||
536 | if (!c->x86_model_id[0]) { | |
537 | switch (c->x86) { | |
538 | case 0xf: | |
539 | /* Should distinguish Models here, but this is only | |
540 | a fallback anyways. */ | |
541 | strcpy(c->x86_model_id, "Hammer"); | |
542 | break; | |
543 | } | |
544 | } | |
545 | ||
546 | cpu_detect_cache_sizes(c); | |
547 | ||
548 | /* Multi core CPU? */ | |
549 | if (c->extended_cpuid_level >= 0x80000008) { | |
550 | amd_detect_cmp(c); | |
551 | srat_detect_node(c); | |
552 | } | |
553 | ||
554 | #ifdef CONFIG_X86_32 | |
555 | detect_ht(c); | |
556 | #endif | |
557 | ||
558 | if (c->extended_cpuid_level >= 0x80000006) { | |
559 | if (cpuid_edx(0x80000006) & 0xf000) | |
560 | num_cache_leaves = 4; | |
561 | else | |
562 | num_cache_leaves = 3; | |
563 | } | |
564 | ||
565 | if (c->x86 >= 0xf) | |
566 | set_cpu_cap(c, X86_FEATURE_K8); | |
567 | ||
568 | if (cpu_has_xmm2) { | |
569 | /* MFENCE stops RDTSC speculation */ | |
570 | set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); | |
571 | } | |
572 | ||
573 | #ifdef CONFIG_X86_64 | |
574 | if (c->x86 == 0x10) { | |
575 | /* do this for boot cpu */ | |
576 | if (c == &boot_cpu_data) | |
577 | check_enable_amd_mmconf_dmi(); | |
578 | ||
579 | fam10h_check_enable_mmcfg(); | |
580 | } | |
581 | ||
582 | if (c == &boot_cpu_data && c->x86 >= 0xf) { | |
583 | unsigned long long tseg; | |
584 | ||
585 | /* | |
586 | * Split up direct mapping around the TSEG SMM area. | |
587 | * Don't do it for gbpages because there seems very little | |
588 | * benefit in doing so. | |
589 | */ | |
590 | if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { | |
591 | printk(KERN_DEBUG "tseg: %010llx\n", tseg); | |
592 | if ((tseg>>PMD_SHIFT) < | |
593 | (max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) || | |
594 | ((tseg>>PMD_SHIFT) < | |
595 | (max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) && | |
596 | (tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT)))) | |
597 | set_memory_4k((unsigned long)__va(tseg), 1); | |
598 | } | |
599 | } | |
600 | #endif | |
601 | } | |
602 | ||
603 | #ifdef CONFIG_X86_32 | |
604 | static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, | |
605 | unsigned int size) | |
606 | { | |
607 | /* AMD errata T13 (order #21922) */ | |
608 | if ((c->x86 == 6)) { | |
609 | /* Duron Rev A0 */ | |
610 | if (c->x86_model == 3 && c->x86_mask == 0) | |
611 | size = 64; | |
612 | /* Tbird rev A1/A2 */ | |
613 | if (c->x86_model == 4 && | |
614 | (c->x86_mask == 0 || c->x86_mask == 1)) | |
615 | size = 256; | |
616 | } | |
617 | return size; | |
618 | } | |
619 | #endif | |
620 | ||
621 | static const struct cpu_dev __cpuinitconst amd_cpu_dev = { | |
622 | .c_vendor = "AMD", | |
623 | .c_ident = { "AuthenticAMD" }, | |
624 | #ifdef CONFIG_X86_32 | |
625 | .c_models = { | |
626 | { .vendor = X86_VENDOR_AMD, .family = 4, .model_names = | |
627 | { | |
628 | [3] = "486 DX/2", | |
629 | [7] = "486 DX/2-WB", | |
630 | [8] = "486 DX/4", | |
631 | [9] = "486 DX/4-WB", | |
632 | [14] = "Am5x86-WT", | |
633 | [15] = "Am5x86-WB" | |
634 | } | |
635 | }, | |
636 | }, | |
637 | .c_size_cache = amd_size_cache, | |
638 | #endif | |
639 | .c_early_init = early_init_amd, | |
640 | .c_init = init_amd, | |
641 | .c_x86_vendor = X86_VENDOR_AMD, | |
642 | }; | |
643 | ||
644 | cpu_dev_register(amd_cpu_dev); | |
645 | ||
646 | /* | |
647 | * AMD errata checking | |
648 | * | |
649 | * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or | |
650 | * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that | |
651 | * have an OSVW id assigned, which it takes as first argument. Both take a | |
652 | * variable number of family-specific model-stepping ranges created by | |
653 | * AMD_MODEL_RANGE(). Each erratum also has to be declared as extern const | |
654 | * int[] in arch/x86/include/asm/processor.h. | |
655 | * | |
656 | * Example: | |
657 | * | |
658 | * const int amd_erratum_319[] = | |
659 | * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), | |
660 | * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), | |
661 | * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); | |
662 | */ | |
663 | ||
664 | const int amd_erratum_400[] = | |
665 | AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), | |
666 | AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); | |
667 | EXPORT_SYMBOL_GPL(amd_erratum_400); | |
668 | ||
669 | const int amd_erratum_383[] = | |
670 | AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); | |
671 | EXPORT_SYMBOL_GPL(amd_erratum_383); | |
672 | ||
673 | bool cpu_has_amd_erratum(const int *erratum) | |
674 | { | |
675 | struct cpuinfo_x86 *cpu = __this_cpu_ptr(&cpu_info); | |
676 | int osvw_id = *erratum++; | |
677 | u32 range; | |
678 | u32 ms; | |
679 | ||
680 | /* | |
681 | * If called early enough that current_cpu_data hasn't been initialized | |
682 | * yet, fall back to boot_cpu_data. | |
683 | */ | |
684 | if (cpu->x86 == 0) | |
685 | cpu = &boot_cpu_data; | |
686 | ||
687 | if (cpu->x86_vendor != X86_VENDOR_AMD) | |
688 | return false; | |
689 | ||
690 | if (osvw_id >= 0 && osvw_id < 65536 && | |
691 | cpu_has(cpu, X86_FEATURE_OSVW)) { | |
692 | u64 osvw_len; | |
693 | ||
694 | rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); | |
695 | if (osvw_id < osvw_len) { | |
696 | u64 osvw_bits; | |
697 | ||
698 | rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), | |
699 | osvw_bits); | |
700 | return osvw_bits & (1ULL << (osvw_id & 0x3f)); | |
701 | } | |
702 | } | |
703 | ||
704 | /* OSVW unavailable or ID unknown, match family-model-stepping range */ | |
705 | ms = (cpu->x86_model << 4) | cpu->x86_mask; | |
706 | while ((range = *erratum++)) | |
707 | if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && | |
708 | (ms >= AMD_MODEL_RANGE_START(range)) && | |
709 | (ms <= AMD_MODEL_RANGE_END(range))) | |
710 | return true; | |
711 | ||
712 | return false; | |
713 | } | |
714 | ||
715 | EXPORT_SYMBOL_GPL(cpu_has_amd_erratum); |