]>
Commit | Line | Data |
---|---|---|
1 | #include <linux/export.h> | |
2 | #include <linux/bitops.h> | |
3 | #include <linux/elf.h> | |
4 | #include <linux/mm.h> | |
5 | ||
6 | #include <linux/io.h> | |
7 | #include <linux/sched.h> | |
8 | #include <linux/sched/clock.h> | |
9 | #include <linux/random.h> | |
10 | #include <asm/processor.h> | |
11 | #include <asm/apic.h> | |
12 | #include <asm/cpu.h> | |
13 | #include <asm/smp.h> | |
14 | #include <asm/pci-direct.h> | |
15 | #include <asm/delay.h> | |
16 | ||
17 | #ifdef CONFIG_X86_64 | |
18 | # include <asm/mmconfig.h> | |
19 | # include <asm/set_memory.h> | |
20 | #endif | |
21 | ||
22 | #include "cpu.h" | |
23 | ||
24 | static const int amd_erratum_383[]; | |
25 | static const int amd_erratum_400[]; | |
26 | static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); | |
27 | ||
28 | /* | |
29 | * nodes_per_socket: Stores the number of nodes per socket. | |
30 | * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX | |
31 | * Node Identifiers[10:8] | |
32 | */ | |
33 | static u32 nodes_per_socket = 1; | |
34 | ||
35 | static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) | |
36 | { | |
37 | u32 gprs[8] = { 0 }; | |
38 | int err; | |
39 | ||
40 | WARN_ONCE((boot_cpu_data.x86 != 0xf), | |
41 | "%s should only be used on K8!\n", __func__); | |
42 | ||
43 | gprs[1] = msr; | |
44 | gprs[7] = 0x9c5a203a; | |
45 | ||
46 | err = rdmsr_safe_regs(gprs); | |
47 | ||
48 | *p = gprs[0] | ((u64)gprs[2] << 32); | |
49 | ||
50 | return err; | |
51 | } | |
52 | ||
53 | static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) | |
54 | { | |
55 | u32 gprs[8] = { 0 }; | |
56 | ||
57 | WARN_ONCE((boot_cpu_data.x86 != 0xf), | |
58 | "%s should only be used on K8!\n", __func__); | |
59 | ||
60 | gprs[0] = (u32)val; | |
61 | gprs[1] = msr; | |
62 | gprs[2] = val >> 32; | |
63 | gprs[7] = 0x9c5a203a; | |
64 | ||
65 | return wrmsr_safe_regs(gprs); | |
66 | } | |
67 | ||
68 | /* | |
69 | * B step AMD K6 before B 9730xxxx have hardware bugs that can cause | |
70 | * misexecution of code under Linux. Owners of such processors should | |
71 | * contact AMD for precise details and a CPU swap. | |
72 | * | |
73 | * See http://www.multimania.com/poulot/k6bug.html | |
74 | * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" | |
75 | * (Publication # 21266 Issue Date: August 1998) | |
76 | * | |
77 | * The following test is erm.. interesting. AMD neglected to up | |
78 | * the chip setting when fixing the bug but they also tweaked some | |
79 | * performance at the same time.. | |
80 | */ | |
81 | ||
82 | extern __visible void vide(void); | |
83 | __asm__(".globl vide\n" | |
84 | ".type vide, @function\n" | |
85 | ".align 4\n" | |
86 | "vide: ret\n"); | |
87 | ||
88 | static void init_amd_k5(struct cpuinfo_x86 *c) | |
89 | { | |
90 | #ifdef CONFIG_X86_32 | |
91 | /* | |
92 | * General Systems BIOSen alias the cpu frequency registers | |
93 | * of the Elan at 0x000df000. Unfortunately, one of the Linux | |
94 | * drivers subsequently pokes it, and changes the CPU speed. | |
95 | * Workaround : Remove the unneeded alias. | |
96 | */ | |
97 | #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ | |
98 | #define CBAR_ENB (0x80000000) | |
99 | #define CBAR_KEY (0X000000CB) | |
100 | if (c->x86_model == 9 || c->x86_model == 10) { | |
101 | if (inl(CBAR) & CBAR_ENB) | |
102 | outl(0 | CBAR_KEY, CBAR); | |
103 | } | |
104 | #endif | |
105 | } | |
106 | ||
107 | static void init_amd_k6(struct cpuinfo_x86 *c) | |
108 | { | |
109 | #ifdef CONFIG_X86_32 | |
110 | u32 l, h; | |
111 | int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); | |
112 | ||
113 | if (c->x86_model < 6) { | |
114 | /* Based on AMD doc 20734R - June 2000 */ | |
115 | if (c->x86_model == 0) { | |
116 | clear_cpu_cap(c, X86_FEATURE_APIC); | |
117 | set_cpu_cap(c, X86_FEATURE_PGE); | |
118 | } | |
119 | return; | |
120 | } | |
121 | ||
122 | if (c->x86_model == 6 && c->x86_mask == 1) { | |
123 | const int K6_BUG_LOOP = 1000000; | |
124 | int n; | |
125 | void (*f_vide)(void); | |
126 | u64 d, d2; | |
127 | ||
128 | pr_info("AMD K6 stepping B detected - "); | |
129 | ||
130 | /* | |
131 | * It looks like AMD fixed the 2.6.2 bug and improved indirect | |
132 | * calls at the same time. | |
133 | */ | |
134 | ||
135 | n = K6_BUG_LOOP; | |
136 | f_vide = vide; | |
137 | OPTIMIZER_HIDE_VAR(f_vide); | |
138 | d = rdtsc(); | |
139 | while (n--) | |
140 | f_vide(); | |
141 | d2 = rdtsc(); | |
142 | d = d2-d; | |
143 | ||
144 | if (d > 20*K6_BUG_LOOP) | |
145 | pr_cont("system stability may be impaired when more than 32 MB are used.\n"); | |
146 | else | |
147 | pr_cont("probably OK (after B9730xxxx).\n"); | |
148 | } | |
149 | ||
150 | /* K6 with old style WHCR */ | |
151 | if (c->x86_model < 8 || | |
152 | (c->x86_model == 8 && c->x86_mask < 8)) { | |
153 | /* We can only write allocate on the low 508Mb */ | |
154 | if (mbytes > 508) | |
155 | mbytes = 508; | |
156 | ||
157 | rdmsr(MSR_K6_WHCR, l, h); | |
158 | if ((l&0x0000FFFF) == 0) { | |
159 | unsigned long flags; | |
160 | l = (1<<0)|((mbytes/4)<<1); | |
161 | local_irq_save(flags); | |
162 | wbinvd(); | |
163 | wrmsr(MSR_K6_WHCR, l, h); | |
164 | local_irq_restore(flags); | |
165 | pr_info("Enabling old style K6 write allocation for %d Mb\n", | |
166 | mbytes); | |
167 | } | |
168 | return; | |
169 | } | |
170 | ||
171 | if ((c->x86_model == 8 && c->x86_mask > 7) || | |
172 | c->x86_model == 9 || c->x86_model == 13) { | |
173 | /* The more serious chips .. */ | |
174 | ||
175 | if (mbytes > 4092) | |
176 | mbytes = 4092; | |
177 | ||
178 | rdmsr(MSR_K6_WHCR, l, h); | |
179 | if ((l&0xFFFF0000) == 0) { | |
180 | unsigned long flags; | |
181 | l = ((mbytes>>2)<<22)|(1<<16); | |
182 | local_irq_save(flags); | |
183 | wbinvd(); | |
184 | wrmsr(MSR_K6_WHCR, l, h); | |
185 | local_irq_restore(flags); | |
186 | pr_info("Enabling new style K6 write allocation for %d Mb\n", | |
187 | mbytes); | |
188 | } | |
189 | ||
190 | return; | |
191 | } | |
192 | ||
193 | if (c->x86_model == 10) { | |
194 | /* AMD Geode LX is model 10 */ | |
195 | /* placeholder for any needed mods */ | |
196 | return; | |
197 | } | |
198 | #endif | |
199 | } | |
200 | ||
201 | static void init_amd_k7(struct cpuinfo_x86 *c) | |
202 | { | |
203 | #ifdef CONFIG_X86_32 | |
204 | u32 l, h; | |
205 | ||
206 | /* | |
207 | * Bit 15 of Athlon specific MSR 15, needs to be 0 | |
208 | * to enable SSE on Palomino/Morgan/Barton CPU's. | |
209 | * If the BIOS didn't enable it already, enable it here. | |
210 | */ | |
211 | if (c->x86_model >= 6 && c->x86_model <= 10) { | |
212 | if (!cpu_has(c, X86_FEATURE_XMM)) { | |
213 | pr_info("Enabling disabled K7/SSE Support.\n"); | |
214 | msr_clear_bit(MSR_K7_HWCR, 15); | |
215 | set_cpu_cap(c, X86_FEATURE_XMM); | |
216 | } | |
217 | } | |
218 | ||
219 | /* | |
220 | * It's been determined by AMD that Athlons since model 8 stepping 1 | |
221 | * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx | |
222 | * As per AMD technical note 27212 0.2 | |
223 | */ | |
224 | if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { | |
225 | rdmsr(MSR_K7_CLK_CTL, l, h); | |
226 | if ((l & 0xfff00000) != 0x20000000) { | |
227 | pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", | |
228 | l, ((l & 0x000fffff)|0x20000000)); | |
229 | wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); | |
230 | } | |
231 | } | |
232 | ||
233 | set_cpu_cap(c, X86_FEATURE_K7); | |
234 | ||
235 | /* calling is from identify_secondary_cpu() ? */ | |
236 | if (!c->cpu_index) | |
237 | return; | |
238 | ||
239 | /* | |
240 | * Certain Athlons might work (for various values of 'work') in SMP | |
241 | * but they are not certified as MP capable. | |
242 | */ | |
243 | /* Athlon 660/661 is valid. */ | |
244 | if ((c->x86_model == 6) && ((c->x86_mask == 0) || | |
245 | (c->x86_mask == 1))) | |
246 | return; | |
247 | ||
248 | /* Duron 670 is valid */ | |
249 | if ((c->x86_model == 7) && (c->x86_mask == 0)) | |
250 | return; | |
251 | ||
252 | /* | |
253 | * Athlon 662, Duron 671, and Athlon >model 7 have capability | |
254 | * bit. It's worth noting that the A5 stepping (662) of some | |
255 | * Athlon XP's have the MP bit set. | |
256 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for | |
257 | * more. | |
258 | */ | |
259 | if (((c->x86_model == 6) && (c->x86_mask >= 2)) || | |
260 | ((c->x86_model == 7) && (c->x86_mask >= 1)) || | |
261 | (c->x86_model > 7)) | |
262 | if (cpu_has(c, X86_FEATURE_MP)) | |
263 | return; | |
264 | ||
265 | /* If we get here, not a certified SMP capable AMD system. */ | |
266 | ||
267 | /* | |
268 | * Don't taint if we are running SMP kernel on a single non-MP | |
269 | * approved Athlon | |
270 | */ | |
271 | WARN_ONCE(1, "WARNING: This combination of AMD" | |
272 | " processors is not suitable for SMP.\n"); | |
273 | add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); | |
274 | #endif | |
275 | } | |
276 | ||
277 | #ifdef CONFIG_NUMA | |
278 | /* | |
279 | * To workaround broken NUMA config. Read the comment in | |
280 | * srat_detect_node(). | |
281 | */ | |
282 | static int nearby_node(int apicid) | |
283 | { | |
284 | int i, node; | |
285 | ||
286 | for (i = apicid - 1; i >= 0; i--) { | |
287 | node = __apicid_to_node[i]; | |
288 | if (node != NUMA_NO_NODE && node_online(node)) | |
289 | return node; | |
290 | } | |
291 | for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { | |
292 | node = __apicid_to_node[i]; | |
293 | if (node != NUMA_NO_NODE && node_online(node)) | |
294 | return node; | |
295 | } | |
296 | return first_node(node_online_map); /* Shouldn't happen */ | |
297 | } | |
298 | #endif | |
299 | ||
300 | /* | |
301 | * Fixup core topology information for | |
302 | * (1) AMD multi-node processors | |
303 | * Assumption: Number of cores in each internal node is the same. | |
304 | * (2) AMD processors supporting compute units | |
305 | */ | |
306 | #ifdef CONFIG_SMP | |
307 | static void amd_get_topology(struct cpuinfo_x86 *c) | |
308 | { | |
309 | u8 node_id; | |
310 | int cpu = smp_processor_id(); | |
311 | ||
312 | /* get information required for multi-node processors */ | |
313 | if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { | |
314 | u32 eax, ebx, ecx, edx; | |
315 | ||
316 | cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); | |
317 | ||
318 | node_id = ecx & 0xff; | |
319 | smp_num_siblings = ((ebx >> 8) & 0xff) + 1; | |
320 | ||
321 | if (c->x86 == 0x15) | |
322 | c->cu_id = ebx & 0xff; | |
323 | ||
324 | if (c->x86 >= 0x17) { | |
325 | c->cpu_core_id = ebx & 0xff; | |
326 | ||
327 | if (smp_num_siblings > 1) | |
328 | c->x86_max_cores /= smp_num_siblings; | |
329 | } | |
330 | ||
331 | /* | |
332 | * We may have multiple LLCs if L3 caches exist, so check if we | |
333 | * have an L3 cache by looking at the L3 cache CPUID leaf. | |
334 | */ | |
335 | if (cpuid_edx(0x80000006)) { | |
336 | if (c->x86 == 0x17) { | |
337 | /* | |
338 | * LLC is at the core complex level. | |
339 | * Core complex id is ApicId[3]. | |
340 | */ | |
341 | per_cpu(cpu_llc_id, cpu) = c->apicid >> 3; | |
342 | } else { | |
343 | /* LLC is at the node level. */ | |
344 | per_cpu(cpu_llc_id, cpu) = node_id; | |
345 | } | |
346 | } | |
347 | } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { | |
348 | u64 value; | |
349 | ||
350 | rdmsrl(MSR_FAM10H_NODE_ID, value); | |
351 | node_id = value & 7; | |
352 | ||
353 | per_cpu(cpu_llc_id, cpu) = node_id; | |
354 | } else | |
355 | return; | |
356 | ||
357 | /* fixup multi-node processor information */ | |
358 | if (nodes_per_socket > 1) { | |
359 | u32 cus_per_node; | |
360 | ||
361 | set_cpu_cap(c, X86_FEATURE_AMD_DCM); | |
362 | cus_per_node = c->x86_max_cores / nodes_per_socket; | |
363 | ||
364 | /* core id has to be in the [0 .. cores_per_node - 1] range */ | |
365 | c->cpu_core_id %= cus_per_node; | |
366 | } | |
367 | } | |
368 | #endif | |
369 | ||
370 | /* | |
371 | * On a AMD dual core setup the lower bits of the APIC id distinguish the cores. | |
372 | * Assumes number of cores is a power of two. | |
373 | */ | |
374 | static void amd_detect_cmp(struct cpuinfo_x86 *c) | |
375 | { | |
376 | #ifdef CONFIG_SMP | |
377 | unsigned bits; | |
378 | int cpu = smp_processor_id(); | |
379 | ||
380 | bits = c->x86_coreid_bits; | |
381 | /* Low order bits define the core id (index of core in socket) */ | |
382 | c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); | |
383 | /* Convert the initial APIC ID into the socket ID */ | |
384 | c->phys_proc_id = c->initial_apicid >> bits; | |
385 | /* use socket ID also for last level cache */ | |
386 | per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; | |
387 | amd_get_topology(c); | |
388 | #endif | |
389 | } | |
390 | ||
391 | u16 amd_get_nb_id(int cpu) | |
392 | { | |
393 | u16 id = 0; | |
394 | #ifdef CONFIG_SMP | |
395 | id = per_cpu(cpu_llc_id, cpu); | |
396 | #endif | |
397 | return id; | |
398 | } | |
399 | EXPORT_SYMBOL_GPL(amd_get_nb_id); | |
400 | ||
401 | u32 amd_get_nodes_per_socket(void) | |
402 | { | |
403 | return nodes_per_socket; | |
404 | } | |
405 | EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket); | |
406 | ||
407 | static void srat_detect_node(struct cpuinfo_x86 *c) | |
408 | { | |
409 | #ifdef CONFIG_NUMA | |
410 | int cpu = smp_processor_id(); | |
411 | int node; | |
412 | unsigned apicid = c->apicid; | |
413 | ||
414 | node = numa_cpu_node(cpu); | |
415 | if (node == NUMA_NO_NODE) | |
416 | node = per_cpu(cpu_llc_id, cpu); | |
417 | ||
418 | /* | |
419 | * On multi-fabric platform (e.g. Numascale NumaChip) a | |
420 | * platform-specific handler needs to be called to fixup some | |
421 | * IDs of the CPU. | |
422 | */ | |
423 | if (x86_cpuinit.fixup_cpu_id) | |
424 | x86_cpuinit.fixup_cpu_id(c, node); | |
425 | ||
426 | if (!node_online(node)) { | |
427 | /* | |
428 | * Two possibilities here: | |
429 | * | |
430 | * - The CPU is missing memory and no node was created. In | |
431 | * that case try picking one from a nearby CPU. | |
432 | * | |
433 | * - The APIC IDs differ from the HyperTransport node IDs | |
434 | * which the K8 northbridge parsing fills in. Assume | |
435 | * they are all increased by a constant offset, but in | |
436 | * the same order as the HT nodeids. If that doesn't | |
437 | * result in a usable node fall back to the path for the | |
438 | * previous case. | |
439 | * | |
440 | * This workaround operates directly on the mapping between | |
441 | * APIC ID and NUMA node, assuming certain relationship | |
442 | * between APIC ID, HT node ID and NUMA topology. As going | |
443 | * through CPU mapping may alter the outcome, directly | |
444 | * access __apicid_to_node[]. | |
445 | */ | |
446 | int ht_nodeid = c->initial_apicid; | |
447 | ||
448 | if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) | |
449 | node = __apicid_to_node[ht_nodeid]; | |
450 | /* Pick a nearby node */ | |
451 | if (!node_online(node)) | |
452 | node = nearby_node(apicid); | |
453 | } | |
454 | numa_set_node(cpu, node); | |
455 | #endif | |
456 | } | |
457 | ||
458 | static void early_init_amd_mc(struct cpuinfo_x86 *c) | |
459 | { | |
460 | #ifdef CONFIG_SMP | |
461 | unsigned bits, ecx; | |
462 | ||
463 | /* Multi core CPU? */ | |
464 | if (c->extended_cpuid_level < 0x80000008) | |
465 | return; | |
466 | ||
467 | ecx = cpuid_ecx(0x80000008); | |
468 | ||
469 | c->x86_max_cores = (ecx & 0xff) + 1; | |
470 | ||
471 | /* CPU telling us the core id bits shift? */ | |
472 | bits = (ecx >> 12) & 0xF; | |
473 | ||
474 | /* Otherwise recompute */ | |
475 | if (bits == 0) { | |
476 | while ((1 << bits) < c->x86_max_cores) | |
477 | bits++; | |
478 | } | |
479 | ||
480 | c->x86_coreid_bits = bits; | |
481 | #endif | |
482 | } | |
483 | ||
484 | static void bsp_init_amd(struct cpuinfo_x86 *c) | |
485 | { | |
486 | ||
487 | #ifdef CONFIG_X86_64 | |
488 | if (c->x86 >= 0xf) { | |
489 | unsigned long long tseg; | |
490 | ||
491 | /* | |
492 | * Split up direct mapping around the TSEG SMM area. | |
493 | * Don't do it for gbpages because there seems very little | |
494 | * benefit in doing so. | |
495 | */ | |
496 | if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { | |
497 | unsigned long pfn = tseg >> PAGE_SHIFT; | |
498 | ||
499 | pr_debug("tseg: %010llx\n", tseg); | |
500 | if (pfn_range_is_mapped(pfn, pfn + 1)) | |
501 | set_memory_4k((unsigned long)__va(tseg), 1); | |
502 | } | |
503 | } | |
504 | #endif | |
505 | ||
506 | if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { | |
507 | ||
508 | if (c->x86 > 0x10 || | |
509 | (c->x86 == 0x10 && c->x86_model >= 0x2)) { | |
510 | u64 val; | |
511 | ||
512 | rdmsrl(MSR_K7_HWCR, val); | |
513 | if (!(val & BIT(24))) | |
514 | pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); | |
515 | } | |
516 | } | |
517 | ||
518 | if (c->x86 == 0x15) { | |
519 | unsigned long upperbit; | |
520 | u32 cpuid, assoc; | |
521 | ||
522 | cpuid = cpuid_edx(0x80000005); | |
523 | assoc = cpuid >> 16 & 0xff; | |
524 | upperbit = ((cpuid >> 24) << 10) / assoc; | |
525 | ||
526 | va_align.mask = (upperbit - 1) & PAGE_MASK; | |
527 | va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; | |
528 | ||
529 | /* A random value per boot for bit slice [12:upper_bit) */ | |
530 | va_align.bits = get_random_int() & va_align.mask; | |
531 | } | |
532 | ||
533 | if (cpu_has(c, X86_FEATURE_MWAITX)) | |
534 | use_mwaitx_delay(); | |
535 | ||
536 | if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { | |
537 | u32 ecx; | |
538 | ||
539 | ecx = cpuid_ecx(0x8000001e); | |
540 | nodes_per_socket = ((ecx >> 8) & 7) + 1; | |
541 | } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { | |
542 | u64 value; | |
543 | ||
544 | rdmsrl(MSR_FAM10H_NODE_ID, value); | |
545 | nodes_per_socket = ((value >> 3) & 7) + 1; | |
546 | } | |
547 | } | |
548 | ||
549 | static void early_init_amd(struct cpuinfo_x86 *c) | |
550 | { | |
551 | early_init_amd_mc(c); | |
552 | ||
553 | /* | |
554 | * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate | |
555 | * with P/T states and does not stop in deep C-states | |
556 | */ | |
557 | if (c->x86_power & (1 << 8)) { | |
558 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); | |
559 | set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); | |
560 | } | |
561 | ||
562 | /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ | |
563 | if (c->x86_power & BIT(12)) | |
564 | set_cpu_cap(c, X86_FEATURE_ACC_POWER); | |
565 | ||
566 | #ifdef CONFIG_X86_64 | |
567 | set_cpu_cap(c, X86_FEATURE_SYSCALL32); | |
568 | #else | |
569 | /* Set MTRR capability flag if appropriate */ | |
570 | if (c->x86 == 5) | |
571 | if (c->x86_model == 13 || c->x86_model == 9 || | |
572 | (c->x86_model == 8 && c->x86_mask >= 8)) | |
573 | set_cpu_cap(c, X86_FEATURE_K6_MTRR); | |
574 | #endif | |
575 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) | |
576 | /* | |
577 | * ApicID can always be treated as an 8-bit value for AMD APIC versions | |
578 | * >= 0x10, but even old K8s came out of reset with version 0x10. So, we | |
579 | * can safely set X86_FEATURE_EXTD_APICID unconditionally for families | |
580 | * after 16h. | |
581 | */ | |
582 | if (boot_cpu_has(X86_FEATURE_APIC)) { | |
583 | if (c->x86 > 0x16) | |
584 | set_cpu_cap(c, X86_FEATURE_EXTD_APICID); | |
585 | else if (c->x86 >= 0xf) { | |
586 | /* check CPU config space for extended APIC ID */ | |
587 | unsigned int val; | |
588 | ||
589 | val = read_pci_config(0, 24, 0, 0x68); | |
590 | if ((val >> 17 & 0x3) == 0x3) | |
591 | set_cpu_cap(c, X86_FEATURE_EXTD_APICID); | |
592 | } | |
593 | } | |
594 | #endif | |
595 | ||
596 | /* | |
597 | * This is only needed to tell the kernel whether to use VMCALL | |
598 | * and VMMCALL. VMMCALL is never executed except under virt, so | |
599 | * we can set it unconditionally. | |
600 | */ | |
601 | set_cpu_cap(c, X86_FEATURE_VMMCALL); | |
602 | ||
603 | /* F16h erratum 793, CVE-2013-6885 */ | |
604 | if (c->x86 == 0x16 && c->x86_model <= 0xf) | |
605 | msr_set_bit(MSR_AMD64_LS_CFG, 15); | |
606 | ||
607 | /* | |
608 | * Check whether the machine is affected by erratum 400. This is | |
609 | * used to select the proper idle routine and to enable the check | |
610 | * whether the machine is affected in arch_post_acpi_init(), which | |
611 | * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. | |
612 | */ | |
613 | if (cpu_has_amd_erratum(c, amd_erratum_400)) | |
614 | set_cpu_bug(c, X86_BUG_AMD_E400); | |
615 | } | |
616 | ||
617 | static void init_amd_k8(struct cpuinfo_x86 *c) | |
618 | { | |
619 | u32 level; | |
620 | u64 value; | |
621 | ||
622 | /* On C+ stepping K8 rep microcode works well for copy/memset */ | |
623 | level = cpuid_eax(1); | |
624 | if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) | |
625 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); | |
626 | ||
627 | /* | |
628 | * Some BIOSes incorrectly force this feature, but only K8 revision D | |
629 | * (model = 0x14) and later actually support it. | |
630 | * (AMD Erratum #110, docId: 25759). | |
631 | */ | |
632 | if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { | |
633 | clear_cpu_cap(c, X86_FEATURE_LAHF_LM); | |
634 | if (!rdmsrl_amd_safe(0xc001100d, &value)) { | |
635 | value &= ~BIT_64(32); | |
636 | wrmsrl_amd_safe(0xc001100d, value); | |
637 | } | |
638 | } | |
639 | ||
640 | if (!c->x86_model_id[0]) | |
641 | strcpy(c->x86_model_id, "Hammer"); | |
642 | ||
643 | #ifdef CONFIG_SMP | |
644 | /* | |
645 | * Disable TLB flush filter by setting HWCR.FFDIS on K8 | |
646 | * bit 6 of msr C001_0015 | |
647 | * | |
648 | * Errata 63 for SH-B3 steppings | |
649 | * Errata 122 for all steppings (F+ have it disabled by default) | |
650 | */ | |
651 | msr_set_bit(MSR_K7_HWCR, 6); | |
652 | #endif | |
653 | set_cpu_bug(c, X86_BUG_SWAPGS_FENCE); | |
654 | } | |
655 | ||
656 | static void init_amd_gh(struct cpuinfo_x86 *c) | |
657 | { | |
658 | #ifdef CONFIG_X86_64 | |
659 | /* do this for boot cpu */ | |
660 | if (c == &boot_cpu_data) | |
661 | check_enable_amd_mmconf_dmi(); | |
662 | ||
663 | fam10h_check_enable_mmcfg(); | |
664 | #endif | |
665 | ||
666 | /* | |
667 | * Disable GART TLB Walk Errors on Fam10h. We do this here because this | |
668 | * is always needed when GART is enabled, even in a kernel which has no | |
669 | * MCE support built in. BIOS should disable GartTlbWlk Errors already. | |
670 | * If it doesn't, we do it here as suggested by the BKDG. | |
671 | * | |
672 | * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 | |
673 | */ | |
674 | msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); | |
675 | ||
676 | /* | |
677 | * On family 10h BIOS may not have properly enabled WC+ support, causing | |
678 | * it to be converted to CD memtype. This may result in performance | |
679 | * degradation for certain nested-paging guests. Prevent this conversion | |
680 | * by clearing bit 24 in MSR_AMD64_BU_CFG2. | |
681 | * | |
682 | * NOTE: we want to use the _safe accessors so as not to #GP kvm | |
683 | * guests on older kvm hosts. | |
684 | */ | |
685 | msr_clear_bit(MSR_AMD64_BU_CFG2, 24); | |
686 | ||
687 | if (cpu_has_amd_erratum(c, amd_erratum_383)) | |
688 | set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); | |
689 | } | |
690 | ||
691 | #define MSR_AMD64_DE_CFG 0xC0011029 | |
692 | ||
693 | static void init_amd_ln(struct cpuinfo_x86 *c) | |
694 | { | |
695 | /* | |
696 | * Apply erratum 665 fix unconditionally so machines without a BIOS | |
697 | * fix work. | |
698 | */ | |
699 | msr_set_bit(MSR_AMD64_DE_CFG, 31); | |
700 | } | |
701 | ||
702 | static void init_amd_bd(struct cpuinfo_x86 *c) | |
703 | { | |
704 | u64 value; | |
705 | ||
706 | /* re-enable TopologyExtensions if switched off by BIOS */ | |
707 | if ((c->x86_model >= 0x10) && (c->x86_model <= 0x6f) && | |
708 | !cpu_has(c, X86_FEATURE_TOPOEXT)) { | |
709 | ||
710 | if (msr_set_bit(0xc0011005, 54) > 0) { | |
711 | rdmsrl(0xc0011005, value); | |
712 | if (value & BIT_64(54)) { | |
713 | set_cpu_cap(c, X86_FEATURE_TOPOEXT); | |
714 | pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n"); | |
715 | } | |
716 | } | |
717 | } | |
718 | ||
719 | /* | |
720 | * The way access filter has a performance penalty on some workloads. | |
721 | * Disable it on the affected CPUs. | |
722 | */ | |
723 | if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { | |
724 | if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { | |
725 | value |= 0x1E; | |
726 | wrmsrl_safe(MSR_F15H_IC_CFG, value); | |
727 | } | |
728 | } | |
729 | } | |
730 | ||
731 | static void init_amd(struct cpuinfo_x86 *c) | |
732 | { | |
733 | u32 dummy; | |
734 | ||
735 | early_init_amd(c); | |
736 | ||
737 | /* | |
738 | * Bit 31 in normal CPUID used for nonstandard 3DNow ID; | |
739 | * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway | |
740 | */ | |
741 | clear_cpu_cap(c, 0*32+31); | |
742 | ||
743 | if (c->x86 >= 0x10) | |
744 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); | |
745 | ||
746 | /* get apicid instead of initial apic id from cpuid */ | |
747 | c->apicid = hard_smp_processor_id(); | |
748 | ||
749 | /* K6s reports MCEs but don't actually have all the MSRs */ | |
750 | if (c->x86 < 6) | |
751 | clear_cpu_cap(c, X86_FEATURE_MCE); | |
752 | ||
753 | switch (c->x86) { | |
754 | case 4: init_amd_k5(c); break; | |
755 | case 5: init_amd_k6(c); break; | |
756 | case 6: init_amd_k7(c); break; | |
757 | case 0xf: init_amd_k8(c); break; | |
758 | case 0x10: init_amd_gh(c); break; | |
759 | case 0x12: init_amd_ln(c); break; | |
760 | case 0x15: init_amd_bd(c); break; | |
761 | } | |
762 | ||
763 | /* | |
764 | * Enable workaround for FXSAVE leak on CPUs | |
765 | * without a XSaveErPtr feature | |
766 | */ | |
767 | if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR))) | |
768 | set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); | |
769 | ||
770 | cpu_detect_cache_sizes(c); | |
771 | ||
772 | /* Multi core CPU? */ | |
773 | if (c->extended_cpuid_level >= 0x80000008) { | |
774 | amd_detect_cmp(c); | |
775 | srat_detect_node(c); | |
776 | } | |
777 | ||
778 | #ifdef CONFIG_X86_32 | |
779 | detect_ht(c); | |
780 | #endif | |
781 | ||
782 | init_amd_cacheinfo(c); | |
783 | ||
784 | if (c->x86 >= 0xf) | |
785 | set_cpu_cap(c, X86_FEATURE_K8); | |
786 | ||
787 | if (cpu_has(c, X86_FEATURE_XMM2)) { | |
788 | /* MFENCE stops RDTSC speculation */ | |
789 | set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); | |
790 | } | |
791 | ||
792 | /* | |
793 | * Family 0x12 and above processors have APIC timer | |
794 | * running in deep C states. | |
795 | */ | |
796 | if (c->x86 > 0x11) | |
797 | set_cpu_cap(c, X86_FEATURE_ARAT); | |
798 | ||
799 | rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); | |
800 | ||
801 | /* 3DNow or LM implies PREFETCHW */ | |
802 | if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) | |
803 | if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) | |
804 | set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); | |
805 | ||
806 | /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */ | |
807 | if (!cpu_has(c, X86_FEATURE_XENPV)) | |
808 | set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); | |
809 | } | |
810 | ||
811 | #ifdef CONFIG_X86_32 | |
812 | static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) | |
813 | { | |
814 | /* AMD errata T13 (order #21922) */ | |
815 | if ((c->x86 == 6)) { | |
816 | /* Duron Rev A0 */ | |
817 | if (c->x86_model == 3 && c->x86_mask == 0) | |
818 | size = 64; | |
819 | /* Tbird rev A1/A2 */ | |
820 | if (c->x86_model == 4 && | |
821 | (c->x86_mask == 0 || c->x86_mask == 1)) | |
822 | size = 256; | |
823 | } | |
824 | return size; | |
825 | } | |
826 | #endif | |
827 | ||
828 | static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) | |
829 | { | |
830 | u32 ebx, eax, ecx, edx; | |
831 | u16 mask = 0xfff; | |
832 | ||
833 | if (c->x86 < 0xf) | |
834 | return; | |
835 | ||
836 | if (c->extended_cpuid_level < 0x80000006) | |
837 | return; | |
838 | ||
839 | cpuid(0x80000006, &eax, &ebx, &ecx, &edx); | |
840 | ||
841 | tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; | |
842 | tlb_lli_4k[ENTRIES] = ebx & mask; | |
843 | ||
844 | /* | |
845 | * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB | |
846 | * characteristics from the CPUID function 0x80000005 instead. | |
847 | */ | |
848 | if (c->x86 == 0xf) { | |
849 | cpuid(0x80000005, &eax, &ebx, &ecx, &edx); | |
850 | mask = 0xff; | |
851 | } | |
852 | ||
853 | /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ | |
854 | if (!((eax >> 16) & mask)) | |
855 | tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff; | |
856 | else | |
857 | tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; | |
858 | ||
859 | /* a 4M entry uses two 2M entries */ | |
860 | tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; | |
861 | ||
862 | /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ | |
863 | if (!(eax & mask)) { | |
864 | /* Erratum 658 */ | |
865 | if (c->x86 == 0x15 && c->x86_model <= 0x1f) { | |
866 | tlb_lli_2m[ENTRIES] = 1024; | |
867 | } else { | |
868 | cpuid(0x80000005, &eax, &ebx, &ecx, &edx); | |
869 | tlb_lli_2m[ENTRIES] = eax & 0xff; | |
870 | } | |
871 | } else | |
872 | tlb_lli_2m[ENTRIES] = eax & mask; | |
873 | ||
874 | tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; | |
875 | } | |
876 | ||
877 | static const struct cpu_dev amd_cpu_dev = { | |
878 | .c_vendor = "AMD", | |
879 | .c_ident = { "AuthenticAMD" }, | |
880 | #ifdef CONFIG_X86_32 | |
881 | .legacy_models = { | |
882 | { .family = 4, .model_names = | |
883 | { | |
884 | [3] = "486 DX/2", | |
885 | [7] = "486 DX/2-WB", | |
886 | [8] = "486 DX/4", | |
887 | [9] = "486 DX/4-WB", | |
888 | [14] = "Am5x86-WT", | |
889 | [15] = "Am5x86-WB" | |
890 | } | |
891 | }, | |
892 | }, | |
893 | .legacy_cache_size = amd_size_cache, | |
894 | #endif | |
895 | .c_early_init = early_init_amd, | |
896 | .c_detect_tlb = cpu_detect_tlb_amd, | |
897 | .c_bsp_init = bsp_init_amd, | |
898 | .c_init = init_amd, | |
899 | .c_x86_vendor = X86_VENDOR_AMD, | |
900 | }; | |
901 | ||
902 | cpu_dev_register(amd_cpu_dev); | |
903 | ||
904 | /* | |
905 | * AMD errata checking | |
906 | * | |
907 | * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or | |
908 | * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that | |
909 | * have an OSVW id assigned, which it takes as first argument. Both take a | |
910 | * variable number of family-specific model-stepping ranges created by | |
911 | * AMD_MODEL_RANGE(). | |
912 | * | |
913 | * Example: | |
914 | * | |
915 | * const int amd_erratum_319[] = | |
916 | * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), | |
917 | * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), | |
918 | * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); | |
919 | */ | |
920 | ||
921 | #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } | |
922 | #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } | |
923 | #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ | |
924 | ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) | |
925 | #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) | |
926 | #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) | |
927 | #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) | |
928 | ||
929 | static const int amd_erratum_400[] = | |
930 | AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), | |
931 | AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); | |
932 | ||
933 | static const int amd_erratum_383[] = | |
934 | AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); | |
935 | ||
936 | ||
937 | static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) | |
938 | { | |
939 | int osvw_id = *erratum++; | |
940 | u32 range; | |
941 | u32 ms; | |
942 | ||
943 | if (osvw_id >= 0 && osvw_id < 65536 && | |
944 | cpu_has(cpu, X86_FEATURE_OSVW)) { | |
945 | u64 osvw_len; | |
946 | ||
947 | rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); | |
948 | if (osvw_id < osvw_len) { | |
949 | u64 osvw_bits; | |
950 | ||
951 | rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), | |
952 | osvw_bits); | |
953 | return osvw_bits & (1ULL << (osvw_id & 0x3f)); | |
954 | } | |
955 | } | |
956 | ||
957 | /* OSVW unavailable or ID unknown, match family-model-stepping range */ | |
958 | ms = (cpu->x86_model << 4) | cpu->x86_mask; | |
959 | while ((range = *erratum++)) | |
960 | if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && | |
961 | (ms >= AMD_MODEL_RANGE_START(range)) && | |
962 | (ms <= AMD_MODEL_RANGE_END(range))) | |
963 | return true; | |
964 | ||
965 | return false; | |
966 | } | |
967 | ||
968 | void set_dr_addr_mask(unsigned long mask, int dr) | |
969 | { | |
970 | if (!boot_cpu_has(X86_FEATURE_BPEXT)) | |
971 | return; | |
972 | ||
973 | switch (dr) { | |
974 | case 0: | |
975 | wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0); | |
976 | break; | |
977 | case 1: | |
978 | case 2: | |
979 | case 3: | |
980 | wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); | |
981 | break; | |
982 | default: | |
983 | break; | |
984 | } | |
985 | } |