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1 | #include <linux/bootmem.h> | |
2 | #include <linux/linkage.h> | |
3 | #include <linux/bitops.h> | |
4 | #include <linux/kernel.h> | |
5 | #include <linux/module.h> | |
6 | #include <linux/percpu.h> | |
7 | #include <linux/string.h> | |
8 | #include <linux/ctype.h> | |
9 | #include <linux/delay.h> | |
10 | #include <linux/sched.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/kprobes.h> | |
13 | #include <linux/kgdb.h> | |
14 | #include <linux/smp.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/syscore_ops.h> | |
17 | ||
18 | #include <asm/stackprotector.h> | |
19 | #include <asm/perf_event.h> | |
20 | #include <asm/mmu_context.h> | |
21 | #include <asm/archrandom.h> | |
22 | #include <asm/hypervisor.h> | |
23 | #include <asm/processor.h> | |
24 | #include <asm/tlbflush.h> | |
25 | #include <asm/debugreg.h> | |
26 | #include <asm/sections.h> | |
27 | #include <asm/vsyscall.h> | |
28 | #include <linux/topology.h> | |
29 | #include <linux/cpumask.h> | |
30 | #include <asm/pgtable.h> | |
31 | #include <linux/atomic.h> | |
32 | #include <asm/proto.h> | |
33 | #include <asm/setup.h> | |
34 | #include <asm/apic.h> | |
35 | #include <asm/desc.h> | |
36 | #include <asm/fpu/internal.h> | |
37 | #include <asm/mtrr.h> | |
38 | #include <linux/numa.h> | |
39 | #include <asm/asm.h> | |
40 | #include <asm/cpu.h> | |
41 | #include <asm/mce.h> | |
42 | #include <asm/msr.h> | |
43 | #include <asm/pat.h> | |
44 | #include <asm/microcode.h> | |
45 | #include <asm/microcode_intel.h> | |
46 | ||
47 | #ifdef CONFIG_X86_LOCAL_APIC | |
48 | #include <asm/uv/uv.h> | |
49 | #endif | |
50 | ||
51 | #include "cpu.h" | |
52 | ||
53 | /* all of these masks are initialized in setup_cpu_local_masks() */ | |
54 | cpumask_var_t cpu_initialized_mask; | |
55 | cpumask_var_t cpu_callout_mask; | |
56 | cpumask_var_t cpu_callin_mask; | |
57 | ||
58 | /* representing cpus for which sibling maps can be computed */ | |
59 | cpumask_var_t cpu_sibling_setup_mask; | |
60 | ||
61 | /* correctly size the local cpu masks */ | |
62 | void __init setup_cpu_local_masks(void) | |
63 | { | |
64 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
65 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
66 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
67 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
68 | } | |
69 | ||
70 | static void default_init(struct cpuinfo_x86 *c) | |
71 | { | |
72 | #ifdef CONFIG_X86_64 | |
73 | cpu_detect_cache_sizes(c); | |
74 | #else | |
75 | /* Not much we can do here... */ | |
76 | /* Check if at least it has cpuid */ | |
77 | if (c->cpuid_level == -1) { | |
78 | /* No cpuid. It must be an ancient CPU */ | |
79 | if (c->x86 == 4) | |
80 | strcpy(c->x86_model_id, "486"); | |
81 | else if (c->x86 == 3) | |
82 | strcpy(c->x86_model_id, "386"); | |
83 | } | |
84 | #endif | |
85 | } | |
86 | ||
87 | static const struct cpu_dev default_cpu = { | |
88 | .c_init = default_init, | |
89 | .c_vendor = "Unknown", | |
90 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
91 | }; | |
92 | ||
93 | static const struct cpu_dev *this_cpu = &default_cpu; | |
94 | ||
95 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { | |
96 | #ifdef CONFIG_X86_64 | |
97 | /* | |
98 | * We need valid kernel segments for data and code in long mode too | |
99 | * IRET will check the segment types kkeil 2000/10/28 | |
100 | * Also sysret mandates a special GDT layout | |
101 | * | |
102 | * TLS descriptors are currently at a different place compared to i386. | |
103 | * Hopefully nobody expects them at a fixed place (Wine?) | |
104 | */ | |
105 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), | |
106 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
107 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
108 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
109 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
110 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
111 | #else | |
112 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), | |
113 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
114 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
115 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
116 | /* | |
117 | * Segments used for calling PnP BIOS have byte granularity. | |
118 | * They code segments and data segments have fixed 64k limits, | |
119 | * the transfer segment sizes are set at run time. | |
120 | */ | |
121 | /* 32-bit code */ | |
122 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), | |
123 | /* 16-bit code */ | |
124 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), | |
125 | /* 16-bit data */ | |
126 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), | |
127 | /* 16-bit data */ | |
128 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), | |
129 | /* 16-bit data */ | |
130 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), | |
131 | /* | |
132 | * The APM segments have byte granularity and their bases | |
133 | * are set at run time. All have 64k limits. | |
134 | */ | |
135 | /* 32-bit code */ | |
136 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), | |
137 | /* 16-bit code */ | |
138 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), | |
139 | /* data */ | |
140 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), | |
141 | ||
142 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
143 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
144 | GDT_STACK_CANARY_INIT | |
145 | #endif | |
146 | } }; | |
147 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); | |
148 | ||
149 | static int __init x86_mpx_setup(char *s) | |
150 | { | |
151 | /* require an exact match without trailing characters */ | |
152 | if (strlen(s)) | |
153 | return 0; | |
154 | ||
155 | /* do not emit a message if the feature is not present */ | |
156 | if (!boot_cpu_has(X86_FEATURE_MPX)) | |
157 | return 1; | |
158 | ||
159 | setup_clear_cpu_cap(X86_FEATURE_MPX); | |
160 | pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); | |
161 | return 1; | |
162 | } | |
163 | __setup("nompx", x86_mpx_setup); | |
164 | ||
165 | #ifdef CONFIG_X86_32 | |
166 | static int cachesize_override = -1; | |
167 | static int disable_x86_serial_nr = 1; | |
168 | ||
169 | static int __init cachesize_setup(char *str) | |
170 | { | |
171 | get_option(&str, &cachesize_override); | |
172 | return 1; | |
173 | } | |
174 | __setup("cachesize=", cachesize_setup); | |
175 | ||
176 | static int __init x86_sep_setup(char *s) | |
177 | { | |
178 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
179 | return 1; | |
180 | } | |
181 | __setup("nosep", x86_sep_setup); | |
182 | ||
183 | /* Standard macro to see if a specific flag is changeable */ | |
184 | static inline int flag_is_changeable_p(u32 flag) | |
185 | { | |
186 | u32 f1, f2; | |
187 | ||
188 | /* | |
189 | * Cyrix and IDT cpus allow disabling of CPUID | |
190 | * so the code below may return different results | |
191 | * when it is executed before and after enabling | |
192 | * the CPUID. Add "volatile" to not allow gcc to | |
193 | * optimize the subsequent calls to this function. | |
194 | */ | |
195 | asm volatile ("pushfl \n\t" | |
196 | "pushfl \n\t" | |
197 | "popl %0 \n\t" | |
198 | "movl %0, %1 \n\t" | |
199 | "xorl %2, %0 \n\t" | |
200 | "pushl %0 \n\t" | |
201 | "popfl \n\t" | |
202 | "pushfl \n\t" | |
203 | "popl %0 \n\t" | |
204 | "popfl \n\t" | |
205 | ||
206 | : "=&r" (f1), "=&r" (f2) | |
207 | : "ir" (flag)); | |
208 | ||
209 | return ((f1^f2) & flag) != 0; | |
210 | } | |
211 | ||
212 | /* Probe for the CPUID instruction */ | |
213 | int have_cpuid_p(void) | |
214 | { | |
215 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
216 | } | |
217 | ||
218 | static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
219 | { | |
220 | unsigned long lo, hi; | |
221 | ||
222 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
223 | return; | |
224 | ||
225 | /* Disable processor serial number: */ | |
226 | ||
227 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
228 | lo |= 0x200000; | |
229 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
230 | ||
231 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
232 | clear_cpu_cap(c, X86_FEATURE_PN); | |
233 | ||
234 | /* Disabling the serial number may affect the cpuid level */ | |
235 | c->cpuid_level = cpuid_eax(0); | |
236 | } | |
237 | ||
238 | static int __init x86_serial_nr_setup(char *s) | |
239 | { | |
240 | disable_x86_serial_nr = 0; | |
241 | return 1; | |
242 | } | |
243 | __setup("serialnumber", x86_serial_nr_setup); | |
244 | #else | |
245 | static inline int flag_is_changeable_p(u32 flag) | |
246 | { | |
247 | return 1; | |
248 | } | |
249 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
250 | { | |
251 | } | |
252 | #endif | |
253 | ||
254 | static __init int setup_disable_smep(char *arg) | |
255 | { | |
256 | setup_clear_cpu_cap(X86_FEATURE_SMEP); | |
257 | return 1; | |
258 | } | |
259 | __setup("nosmep", setup_disable_smep); | |
260 | ||
261 | static __always_inline void setup_smep(struct cpuinfo_x86 *c) | |
262 | { | |
263 | if (cpu_has(c, X86_FEATURE_SMEP)) | |
264 | cr4_set_bits(X86_CR4_SMEP); | |
265 | } | |
266 | ||
267 | static __init int setup_disable_smap(char *arg) | |
268 | { | |
269 | setup_clear_cpu_cap(X86_FEATURE_SMAP); | |
270 | return 1; | |
271 | } | |
272 | __setup("nosmap", setup_disable_smap); | |
273 | ||
274 | static __always_inline void setup_smap(struct cpuinfo_x86 *c) | |
275 | { | |
276 | unsigned long eflags = native_save_fl(); | |
277 | ||
278 | /* This should have been cleared long ago */ | |
279 | BUG_ON(eflags & X86_EFLAGS_AC); | |
280 | ||
281 | if (cpu_has(c, X86_FEATURE_SMAP)) { | |
282 | #ifdef CONFIG_X86_SMAP | |
283 | cr4_set_bits(X86_CR4_SMAP); | |
284 | #else | |
285 | cr4_clear_bits(X86_CR4_SMAP); | |
286 | #endif | |
287 | } | |
288 | } | |
289 | ||
290 | /* | |
291 | * Some CPU features depend on higher CPUID levels, which may not always | |
292 | * be available due to CPUID level capping or broken virtualization | |
293 | * software. Add those features to this table to auto-disable them. | |
294 | */ | |
295 | struct cpuid_dependent_feature { | |
296 | u32 feature; | |
297 | u32 level; | |
298 | }; | |
299 | ||
300 | static const struct cpuid_dependent_feature | |
301 | cpuid_dependent_features[] = { | |
302 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
303 | { X86_FEATURE_DCA, 0x00000009 }, | |
304 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
305 | { 0, 0 } | |
306 | }; | |
307 | ||
308 | static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) | |
309 | { | |
310 | const struct cpuid_dependent_feature *df; | |
311 | ||
312 | for (df = cpuid_dependent_features; df->feature; df++) { | |
313 | ||
314 | if (!cpu_has(c, df->feature)) | |
315 | continue; | |
316 | /* | |
317 | * Note: cpuid_level is set to -1 if unavailable, but | |
318 | * extended_extended_level is set to 0 if unavailable | |
319 | * and the legitimate extended levels are all negative | |
320 | * when signed; hence the weird messing around with | |
321 | * signs here... | |
322 | */ | |
323 | if (!((s32)df->level < 0 ? | |
324 | (u32)df->level > (u32)c->extended_cpuid_level : | |
325 | (s32)df->level > (s32)c->cpuid_level)) | |
326 | continue; | |
327 | ||
328 | clear_cpu_cap(c, df->feature); | |
329 | if (!warn) | |
330 | continue; | |
331 | ||
332 | printk(KERN_WARNING | |
333 | "CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", | |
334 | x86_cap_flag(df->feature), df->level); | |
335 | } | |
336 | } | |
337 | ||
338 | /* | |
339 | * Naming convention should be: <Name> [(<Codename>)] | |
340 | * This table only is used unless init_<vendor>() below doesn't set it; | |
341 | * in particular, if CPUID levels 0x80000002..4 are supported, this | |
342 | * isn't used | |
343 | */ | |
344 | ||
345 | /* Look up CPU names by table lookup. */ | |
346 | static const char *table_lookup_model(struct cpuinfo_x86 *c) | |
347 | { | |
348 | #ifdef CONFIG_X86_32 | |
349 | const struct legacy_cpu_model_info *info; | |
350 | ||
351 | if (c->x86_model >= 16) | |
352 | return NULL; /* Range check */ | |
353 | ||
354 | if (!this_cpu) | |
355 | return NULL; | |
356 | ||
357 | info = this_cpu->legacy_models; | |
358 | ||
359 | while (info->family) { | |
360 | if (info->family == c->x86) | |
361 | return info->model_names[c->x86_model]; | |
362 | info++; | |
363 | } | |
364 | #endif | |
365 | return NULL; /* Not found */ | |
366 | } | |
367 | ||
368 | __u32 cpu_caps_cleared[NCAPINTS]; | |
369 | __u32 cpu_caps_set[NCAPINTS]; | |
370 | ||
371 | void load_percpu_segment(int cpu) | |
372 | { | |
373 | #ifdef CONFIG_X86_32 | |
374 | loadsegment(fs, __KERNEL_PERCPU); | |
375 | #else | |
376 | loadsegment(gs, 0); | |
377 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); | |
378 | #endif | |
379 | load_stack_canary_segment(); | |
380 | } | |
381 | ||
382 | /* | |
383 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
384 | * it's on the real one. | |
385 | */ | |
386 | void switch_to_new_gdt(int cpu) | |
387 | { | |
388 | struct desc_ptr gdt_descr; | |
389 | ||
390 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); | |
391 | gdt_descr.size = GDT_SIZE - 1; | |
392 | load_gdt(&gdt_descr); | |
393 | /* Reload the per-cpu base */ | |
394 | ||
395 | load_percpu_segment(cpu); | |
396 | } | |
397 | ||
398 | static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; | |
399 | ||
400 | static void get_model_name(struct cpuinfo_x86 *c) | |
401 | { | |
402 | unsigned int *v; | |
403 | char *p, *q, *s; | |
404 | ||
405 | if (c->extended_cpuid_level < 0x80000004) | |
406 | return; | |
407 | ||
408 | v = (unsigned int *)c->x86_model_id; | |
409 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
410 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
411 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
412 | c->x86_model_id[48] = 0; | |
413 | ||
414 | /* Trim whitespace */ | |
415 | p = q = s = &c->x86_model_id[0]; | |
416 | ||
417 | while (*p == ' ') | |
418 | p++; | |
419 | ||
420 | while (*p) { | |
421 | /* Note the last non-whitespace index */ | |
422 | if (!isspace(*p)) | |
423 | s = q; | |
424 | ||
425 | *q++ = *p++; | |
426 | } | |
427 | ||
428 | *(s + 1) = '\0'; | |
429 | } | |
430 | ||
431 | void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) | |
432 | { | |
433 | unsigned int n, dummy, ebx, ecx, edx, l2size; | |
434 | ||
435 | n = c->extended_cpuid_level; | |
436 | ||
437 | if (n >= 0x80000005) { | |
438 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); | |
439 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
440 | #ifdef CONFIG_X86_64 | |
441 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
442 | c->x86_tlbsize = 0; | |
443 | #endif | |
444 | } | |
445 | ||
446 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
447 | return; | |
448 | ||
449 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); | |
450 | l2size = ecx >> 16; | |
451 | ||
452 | #ifdef CONFIG_X86_64 | |
453 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
454 | #else | |
455 | /* do processor-specific cache resizing */ | |
456 | if (this_cpu->legacy_cache_size) | |
457 | l2size = this_cpu->legacy_cache_size(c, l2size); | |
458 | ||
459 | /* Allow user to override all this if necessary. */ | |
460 | if (cachesize_override != -1) | |
461 | l2size = cachesize_override; | |
462 | ||
463 | if (l2size == 0) | |
464 | return; /* Again, no L2 cache is possible */ | |
465 | #endif | |
466 | ||
467 | c->x86_cache_size = l2size; | |
468 | } | |
469 | ||
470 | u16 __read_mostly tlb_lli_4k[NR_INFO]; | |
471 | u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
472 | u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
473 | u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
474 | u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
475 | u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
476 | u16 __read_mostly tlb_lld_1g[NR_INFO]; | |
477 | ||
478 | static void cpu_detect_tlb(struct cpuinfo_x86 *c) | |
479 | { | |
480 | if (this_cpu->c_detect_tlb) | |
481 | this_cpu->c_detect_tlb(c); | |
482 | ||
483 | pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", | |
484 | tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], | |
485 | tlb_lli_4m[ENTRIES]); | |
486 | ||
487 | pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", | |
488 | tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], | |
489 | tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); | |
490 | } | |
491 | ||
492 | void detect_ht(struct cpuinfo_x86 *c) | |
493 | { | |
494 | #ifdef CONFIG_SMP | |
495 | u32 eax, ebx, ecx, edx; | |
496 | int index_msb, core_bits; | |
497 | static bool printed; | |
498 | ||
499 | if (!cpu_has(c, X86_FEATURE_HT)) | |
500 | return; | |
501 | ||
502 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) | |
503 | goto out; | |
504 | ||
505 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) | |
506 | return; | |
507 | ||
508 | cpuid(1, &eax, &ebx, &ecx, &edx); | |
509 | ||
510 | smp_num_siblings = (ebx & 0xff0000) >> 16; | |
511 | ||
512 | if (smp_num_siblings == 1) { | |
513 | printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n"); | |
514 | goto out; | |
515 | } | |
516 | ||
517 | if (smp_num_siblings <= 1) | |
518 | goto out; | |
519 | ||
520 | index_msb = get_count_order(smp_num_siblings); | |
521 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
522 | ||
523 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
524 | ||
525 | index_msb = get_count_order(smp_num_siblings); | |
526 | ||
527 | core_bits = get_count_order(c->x86_max_cores); | |
528 | ||
529 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & | |
530 | ((1 << core_bits) - 1); | |
531 | ||
532 | out: | |
533 | if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { | |
534 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
535 | c->phys_proc_id); | |
536 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
537 | c->cpu_core_id); | |
538 | printed = 1; | |
539 | } | |
540 | #endif | |
541 | } | |
542 | ||
543 | static void get_cpu_vendor(struct cpuinfo_x86 *c) | |
544 | { | |
545 | char *v = c->x86_vendor_id; | |
546 | int i; | |
547 | ||
548 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
549 | if (!cpu_devs[i]) | |
550 | break; | |
551 | ||
552 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
553 | (cpu_devs[i]->c_ident[1] && | |
554 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
555 | ||
556 | this_cpu = cpu_devs[i]; | |
557 | c->x86_vendor = this_cpu->c_x86_vendor; | |
558 | return; | |
559 | } | |
560 | } | |
561 | ||
562 | printk_once(KERN_ERR | |
563 | "CPU: vendor_id '%s' unknown, using generic init.\n" \ | |
564 | "CPU: Your system may be unstable.\n", v); | |
565 | ||
566 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
567 | this_cpu = &default_cpu; | |
568 | } | |
569 | ||
570 | void cpu_detect(struct cpuinfo_x86 *c) | |
571 | { | |
572 | /* Get vendor name */ | |
573 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, | |
574 | (unsigned int *)&c->x86_vendor_id[0], | |
575 | (unsigned int *)&c->x86_vendor_id[8], | |
576 | (unsigned int *)&c->x86_vendor_id[4]); | |
577 | ||
578 | c->x86 = 4; | |
579 | /* Intel-defined flags: level 0x00000001 */ | |
580 | if (c->cpuid_level >= 0x00000001) { | |
581 | u32 junk, tfms, cap0, misc; | |
582 | ||
583 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
584 | c->x86 = (tfms >> 8) & 0xf; | |
585 | c->x86_model = (tfms >> 4) & 0xf; | |
586 | c->x86_mask = tfms & 0xf; | |
587 | ||
588 | if (c->x86 == 0xf) | |
589 | c->x86 += (tfms >> 20) & 0xff; | |
590 | if (c->x86 >= 0x6) | |
591 | c->x86_model += ((tfms >> 16) & 0xf) << 4; | |
592 | ||
593 | if (cap0 & (1<<19)) { | |
594 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; | |
595 | c->x86_cache_alignment = c->x86_clflush_size; | |
596 | } | |
597 | } | |
598 | } | |
599 | ||
600 | void get_cpu_cap(struct cpuinfo_x86 *c) | |
601 | { | |
602 | u32 tfms, xlvl; | |
603 | u32 ebx; | |
604 | ||
605 | /* Intel-defined flags: level 0x00000001 */ | |
606 | if (c->cpuid_level >= 0x00000001) { | |
607 | u32 capability, excap; | |
608 | ||
609 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
610 | c->x86_capability[0] = capability; | |
611 | c->x86_capability[4] = excap; | |
612 | } | |
613 | ||
614 | /* Additional Intel-defined flags: level 0x00000007 */ | |
615 | if (c->cpuid_level >= 0x00000007) { | |
616 | u32 eax, ebx, ecx, edx; | |
617 | ||
618 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); | |
619 | ||
620 | c->x86_capability[9] = ebx; | |
621 | } | |
622 | ||
623 | /* Extended state features: level 0x0000000d */ | |
624 | if (c->cpuid_level >= 0x0000000d) { | |
625 | u32 eax, ebx, ecx, edx; | |
626 | ||
627 | cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); | |
628 | ||
629 | c->x86_capability[10] = eax; | |
630 | } | |
631 | ||
632 | /* Additional Intel-defined flags: level 0x0000000F */ | |
633 | if (c->cpuid_level >= 0x0000000F) { | |
634 | u32 eax, ebx, ecx, edx; | |
635 | ||
636 | /* QoS sub-leaf, EAX=0Fh, ECX=0 */ | |
637 | cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); | |
638 | c->x86_capability[11] = edx; | |
639 | if (cpu_has(c, X86_FEATURE_CQM_LLC)) { | |
640 | /* will be overridden if occupancy monitoring exists */ | |
641 | c->x86_cache_max_rmid = ebx; | |
642 | ||
643 | /* QoS sub-leaf, EAX=0Fh, ECX=1 */ | |
644 | cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); | |
645 | c->x86_capability[12] = edx; | |
646 | if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) { | |
647 | c->x86_cache_max_rmid = ecx; | |
648 | c->x86_cache_occ_scale = ebx; | |
649 | } | |
650 | } else { | |
651 | c->x86_cache_max_rmid = -1; | |
652 | c->x86_cache_occ_scale = -1; | |
653 | } | |
654 | } | |
655 | ||
656 | /* AMD-defined flags: level 0x80000001 */ | |
657 | xlvl = cpuid_eax(0x80000000); | |
658 | c->extended_cpuid_level = xlvl; | |
659 | ||
660 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
661 | if (xlvl >= 0x80000001) { | |
662 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
663 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
664 | } | |
665 | } | |
666 | ||
667 | if (c->extended_cpuid_level >= 0x80000008) { | |
668 | u32 eax = cpuid_eax(0x80000008); | |
669 | ||
670 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
671 | c->x86_phys_bits = eax & 0xff; | |
672 | c->x86_capability[13] = cpuid_ebx(0x80000008); | |
673 | } | |
674 | #ifdef CONFIG_X86_32 | |
675 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
676 | c->x86_phys_bits = 36; | |
677 | #endif | |
678 | ||
679 | if (c->extended_cpuid_level >= 0x80000007) | |
680 | c->x86_power = cpuid_edx(0x80000007); | |
681 | ||
682 | init_scattered_cpuid_features(c); | |
683 | } | |
684 | ||
685 | static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) | |
686 | { | |
687 | #ifdef CONFIG_X86_32 | |
688 | int i; | |
689 | ||
690 | /* | |
691 | * First of all, decide if this is a 486 or higher | |
692 | * It's a 486 if we can modify the AC flag | |
693 | */ | |
694 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
695 | c->x86 = 4; | |
696 | else | |
697 | c->x86 = 3; | |
698 | ||
699 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
700 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
701 | c->x86_vendor_id[0] = 0; | |
702 | cpu_devs[i]->c_identify(c); | |
703 | if (c->x86_vendor_id[0]) { | |
704 | get_cpu_vendor(c); | |
705 | break; | |
706 | } | |
707 | } | |
708 | #endif | |
709 | } | |
710 | ||
711 | /* | |
712 | * Do minimum CPU detection early. | |
713 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
714 | * cache alignment. | |
715 | * The others are not touched to avoid unwanted side effects. | |
716 | * | |
717 | * WARNING: this function is only called on the BP. Don't add code here | |
718 | * that is supposed to run on all CPUs. | |
719 | */ | |
720 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) | |
721 | { | |
722 | #ifdef CONFIG_X86_64 | |
723 | c->x86_clflush_size = 64; | |
724 | c->x86_phys_bits = 36; | |
725 | c->x86_virt_bits = 48; | |
726 | #else | |
727 | c->x86_clflush_size = 32; | |
728 | c->x86_phys_bits = 32; | |
729 | c->x86_virt_bits = 32; | |
730 | #endif | |
731 | c->x86_cache_alignment = c->x86_clflush_size; | |
732 | ||
733 | memset(&c->x86_capability, 0, sizeof c->x86_capability); | |
734 | c->extended_cpuid_level = 0; | |
735 | ||
736 | if (!have_cpuid_p()) | |
737 | identify_cpu_without_cpuid(c); | |
738 | ||
739 | /* cyrix could have cpuid enabled via c_identify()*/ | |
740 | if (!have_cpuid_p()) | |
741 | return; | |
742 | ||
743 | cpu_detect(c); | |
744 | get_cpu_vendor(c); | |
745 | get_cpu_cap(c); | |
746 | ||
747 | if (this_cpu->c_early_init) | |
748 | this_cpu->c_early_init(c); | |
749 | ||
750 | c->cpu_index = 0; | |
751 | filter_cpuid_features(c, false); | |
752 | ||
753 | if (this_cpu->c_bsp_init) | |
754 | this_cpu->c_bsp_init(c); | |
755 | ||
756 | setup_force_cpu_cap(X86_FEATURE_ALWAYS); | |
757 | fpu__init_system(c); | |
758 | } | |
759 | ||
760 | void __init early_cpu_init(void) | |
761 | { | |
762 | const struct cpu_dev *const *cdev; | |
763 | int count = 0; | |
764 | ||
765 | #ifdef CONFIG_PROCESSOR_SELECT | |
766 | printk(KERN_INFO "KERNEL supported cpus:\n"); | |
767 | #endif | |
768 | ||
769 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { | |
770 | const struct cpu_dev *cpudev = *cdev; | |
771 | ||
772 | if (count >= X86_VENDOR_NUM) | |
773 | break; | |
774 | cpu_devs[count] = cpudev; | |
775 | count++; | |
776 | ||
777 | #ifdef CONFIG_PROCESSOR_SELECT | |
778 | { | |
779 | unsigned int j; | |
780 | ||
781 | for (j = 0; j < 2; j++) { | |
782 | if (!cpudev->c_ident[j]) | |
783 | continue; | |
784 | printk(KERN_INFO " %s %s\n", cpudev->c_vendor, | |
785 | cpudev->c_ident[j]); | |
786 | } | |
787 | } | |
788 | #endif | |
789 | } | |
790 | early_identify_cpu(&boot_cpu_data); | |
791 | } | |
792 | ||
793 | /* | |
794 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; | |
795 | * unfortunately, that's not true in practice because of early VIA | |
796 | * chips and (more importantly) broken virtualizers that are not easy | |
797 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
798 | * probing for it doesn't even work. Disable it completely on 32-bit | |
799 | * unless we can find a reliable way to detect all the broken cases. | |
800 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). | |
801 | */ | |
802 | static void detect_nopl(struct cpuinfo_x86 *c) | |
803 | { | |
804 | #ifdef CONFIG_X86_32 | |
805 | clear_cpu_cap(c, X86_FEATURE_NOPL); | |
806 | #else | |
807 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
808 | #endif | |
809 | } | |
810 | ||
811 | static void generic_identify(struct cpuinfo_x86 *c) | |
812 | { | |
813 | c->extended_cpuid_level = 0; | |
814 | ||
815 | if (!have_cpuid_p()) | |
816 | identify_cpu_without_cpuid(c); | |
817 | ||
818 | /* cyrix could have cpuid enabled via c_identify()*/ | |
819 | if (!have_cpuid_p()) | |
820 | return; | |
821 | ||
822 | cpu_detect(c); | |
823 | ||
824 | get_cpu_vendor(c); | |
825 | ||
826 | get_cpu_cap(c); | |
827 | ||
828 | if (c->cpuid_level >= 0x00000001) { | |
829 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
830 | #ifdef CONFIG_X86_32 | |
831 | # ifdef CONFIG_SMP | |
832 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); | |
833 | # else | |
834 | c->apicid = c->initial_apicid; | |
835 | # endif | |
836 | #endif | |
837 | c->phys_proc_id = c->initial_apicid; | |
838 | } | |
839 | ||
840 | get_model_name(c); /* Default name */ | |
841 | ||
842 | detect_nopl(c); | |
843 | } | |
844 | ||
845 | static void x86_init_cache_qos(struct cpuinfo_x86 *c) | |
846 | { | |
847 | /* | |
848 | * The heavy lifting of max_rmid and cache_occ_scale are handled | |
849 | * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu | |
850 | * in case CQM bits really aren't there in this CPU. | |
851 | */ | |
852 | if (c != &boot_cpu_data) { | |
853 | boot_cpu_data.x86_cache_max_rmid = | |
854 | min(boot_cpu_data.x86_cache_max_rmid, | |
855 | c->x86_cache_max_rmid); | |
856 | } | |
857 | } | |
858 | ||
859 | /* | |
860 | * This does the hard work of actually picking apart the CPU stuff... | |
861 | */ | |
862 | static void identify_cpu(struct cpuinfo_x86 *c) | |
863 | { | |
864 | int i; | |
865 | ||
866 | c->loops_per_jiffy = loops_per_jiffy; | |
867 | c->x86_cache_size = -1; | |
868 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
869 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ | |
870 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
871 | c->x86_model_id[0] = '\0'; /* Unset */ | |
872 | c->x86_max_cores = 1; | |
873 | c->x86_coreid_bits = 0; | |
874 | #ifdef CONFIG_X86_64 | |
875 | c->x86_clflush_size = 64; | |
876 | c->x86_phys_bits = 36; | |
877 | c->x86_virt_bits = 48; | |
878 | #else | |
879 | c->cpuid_level = -1; /* CPUID not detected */ | |
880 | c->x86_clflush_size = 32; | |
881 | c->x86_phys_bits = 32; | |
882 | c->x86_virt_bits = 32; | |
883 | #endif | |
884 | c->x86_cache_alignment = c->x86_clflush_size; | |
885 | memset(&c->x86_capability, 0, sizeof c->x86_capability); | |
886 | ||
887 | generic_identify(c); | |
888 | ||
889 | if (this_cpu->c_identify) | |
890 | this_cpu->c_identify(c); | |
891 | ||
892 | /* Clear/Set all flags overriden by options, after probe */ | |
893 | for (i = 0; i < NCAPINTS; i++) { | |
894 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
895 | c->x86_capability[i] |= cpu_caps_set[i]; | |
896 | } | |
897 | ||
898 | #ifdef CONFIG_X86_64 | |
899 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); | |
900 | #endif | |
901 | ||
902 | /* | |
903 | * Vendor-specific initialization. In this section we | |
904 | * canonicalize the feature flags, meaning if there are | |
905 | * features a certain CPU supports which CPUID doesn't | |
906 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
907 | * we handle them here. | |
908 | * | |
909 | * At the end of this section, c->x86_capability better | |
910 | * indicate the features this CPU genuinely supports! | |
911 | */ | |
912 | if (this_cpu->c_init) | |
913 | this_cpu->c_init(c); | |
914 | ||
915 | /* Disable the PN if appropriate */ | |
916 | squash_the_stupid_serial_number(c); | |
917 | ||
918 | /* Set up SMEP/SMAP */ | |
919 | setup_smep(c); | |
920 | setup_smap(c); | |
921 | ||
922 | /* | |
923 | * The vendor-specific functions might have changed features. | |
924 | * Now we do "generic changes." | |
925 | */ | |
926 | ||
927 | /* Filter out anything that depends on CPUID levels we don't have */ | |
928 | filter_cpuid_features(c, true); | |
929 | ||
930 | /* If the model name is still unset, do table lookup. */ | |
931 | if (!c->x86_model_id[0]) { | |
932 | const char *p; | |
933 | p = table_lookup_model(c); | |
934 | if (p) | |
935 | strcpy(c->x86_model_id, p); | |
936 | else | |
937 | /* Last resort... */ | |
938 | sprintf(c->x86_model_id, "%02x/%02x", | |
939 | c->x86, c->x86_model); | |
940 | } | |
941 | ||
942 | #ifdef CONFIG_X86_64 | |
943 | detect_ht(c); | |
944 | #endif | |
945 | ||
946 | init_hypervisor(c); | |
947 | x86_init_rdrand(c); | |
948 | x86_init_cache_qos(c); | |
949 | ||
950 | /* | |
951 | * Clear/Set all flags overriden by options, need do it | |
952 | * before following smp all cpus cap AND. | |
953 | */ | |
954 | for (i = 0; i < NCAPINTS; i++) { | |
955 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
956 | c->x86_capability[i] |= cpu_caps_set[i]; | |
957 | } | |
958 | ||
959 | /* | |
960 | * On SMP, boot_cpu_data holds the common feature set between | |
961 | * all CPUs; so make sure that we indicate which features are | |
962 | * common between the CPUs. The first time this routine gets | |
963 | * executed, c == &boot_cpu_data. | |
964 | */ | |
965 | if (c != &boot_cpu_data) { | |
966 | /* AND the already accumulated flags with these */ | |
967 | for (i = 0; i < NCAPINTS; i++) | |
968 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; | |
969 | ||
970 | /* OR, i.e. replicate the bug flags */ | |
971 | for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) | |
972 | c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; | |
973 | } | |
974 | ||
975 | /* Init Machine Check Exception if available. */ | |
976 | mcheck_cpu_init(c); | |
977 | ||
978 | select_idle_routine(c); | |
979 | ||
980 | #ifdef CONFIG_NUMA | |
981 | numa_add_cpu(smp_processor_id()); | |
982 | #endif | |
983 | } | |
984 | ||
985 | /* | |
986 | * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions | |
987 | * on 32-bit kernels: | |
988 | */ | |
989 | #ifdef CONFIG_X86_32 | |
990 | void enable_sep_cpu(void) | |
991 | { | |
992 | struct tss_struct *tss; | |
993 | int cpu; | |
994 | ||
995 | cpu = get_cpu(); | |
996 | tss = &per_cpu(cpu_tss, cpu); | |
997 | ||
998 | if (!boot_cpu_has(X86_FEATURE_SEP)) | |
999 | goto out; | |
1000 | ||
1001 | /* | |
1002 | * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- | |
1003 | * see the big comment in struct x86_hw_tss's definition. | |
1004 | */ | |
1005 | ||
1006 | tss->x86_tss.ss1 = __KERNEL_CS; | |
1007 | wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); | |
1008 | ||
1009 | wrmsr(MSR_IA32_SYSENTER_ESP, | |
1010 | (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack), | |
1011 | 0); | |
1012 | ||
1013 | wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); | |
1014 | ||
1015 | out: | |
1016 | put_cpu(); | |
1017 | } | |
1018 | #endif | |
1019 | ||
1020 | void __init identify_boot_cpu(void) | |
1021 | { | |
1022 | identify_cpu(&boot_cpu_data); | |
1023 | init_amd_e400_c1e_mask(); | |
1024 | #ifdef CONFIG_X86_32 | |
1025 | sysenter_setup(); | |
1026 | enable_sep_cpu(); | |
1027 | #endif | |
1028 | cpu_detect_tlb(&boot_cpu_data); | |
1029 | } | |
1030 | ||
1031 | void identify_secondary_cpu(struct cpuinfo_x86 *c) | |
1032 | { | |
1033 | BUG_ON(c == &boot_cpu_data); | |
1034 | identify_cpu(c); | |
1035 | #ifdef CONFIG_X86_32 | |
1036 | enable_sep_cpu(); | |
1037 | #endif | |
1038 | mtrr_ap_init(); | |
1039 | } | |
1040 | ||
1041 | struct msr_range { | |
1042 | unsigned min; | |
1043 | unsigned max; | |
1044 | }; | |
1045 | ||
1046 | static const struct msr_range msr_range_array[] = { | |
1047 | { 0x00000000, 0x00000418}, | |
1048 | { 0xc0000000, 0xc000040b}, | |
1049 | { 0xc0010000, 0xc0010142}, | |
1050 | { 0xc0011000, 0xc001103b}, | |
1051 | }; | |
1052 | ||
1053 | static void __print_cpu_msr(void) | |
1054 | { | |
1055 | unsigned index_min, index_max; | |
1056 | unsigned index; | |
1057 | u64 val; | |
1058 | int i; | |
1059 | ||
1060 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
1061 | index_min = msr_range_array[i].min; | |
1062 | index_max = msr_range_array[i].max; | |
1063 | ||
1064 | for (index = index_min; index < index_max; index++) { | |
1065 | if (rdmsrl_safe(index, &val)) | |
1066 | continue; | |
1067 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1068 | } | |
1069 | } | |
1070 | } | |
1071 | ||
1072 | static int show_msr; | |
1073 | ||
1074 | static __init int setup_show_msr(char *arg) | |
1075 | { | |
1076 | int num; | |
1077 | ||
1078 | get_option(&arg, &num); | |
1079 | ||
1080 | if (num > 0) | |
1081 | show_msr = num; | |
1082 | return 1; | |
1083 | } | |
1084 | __setup("show_msr=", setup_show_msr); | |
1085 | ||
1086 | static __init int setup_noclflush(char *arg) | |
1087 | { | |
1088 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); | |
1089 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); | |
1090 | return 1; | |
1091 | } | |
1092 | __setup("noclflush", setup_noclflush); | |
1093 | ||
1094 | void print_cpu_info(struct cpuinfo_x86 *c) | |
1095 | { | |
1096 | const char *vendor = NULL; | |
1097 | ||
1098 | if (c->x86_vendor < X86_VENDOR_NUM) { | |
1099 | vendor = this_cpu->c_vendor; | |
1100 | } else { | |
1101 | if (c->cpuid_level >= 0) | |
1102 | vendor = c->x86_vendor_id; | |
1103 | } | |
1104 | ||
1105 | if (vendor && !strstr(c->x86_model_id, vendor)) | |
1106 | printk(KERN_CONT "%s ", vendor); | |
1107 | ||
1108 | if (c->x86_model_id[0]) | |
1109 | printk(KERN_CONT "%s", c->x86_model_id); | |
1110 | else | |
1111 | printk(KERN_CONT "%d86", c->x86); | |
1112 | ||
1113 | printk(KERN_CONT " (family: 0x%x, model: 0x%x", c->x86, c->x86_model); | |
1114 | ||
1115 | if (c->x86_mask || c->cpuid_level >= 0) | |
1116 | printk(KERN_CONT ", stepping: 0x%x)\n", c->x86_mask); | |
1117 | else | |
1118 | printk(KERN_CONT ")\n"); | |
1119 | ||
1120 | print_cpu_msr(c); | |
1121 | } | |
1122 | ||
1123 | void print_cpu_msr(struct cpuinfo_x86 *c) | |
1124 | { | |
1125 | if (c->cpu_index < show_msr) | |
1126 | __print_cpu_msr(); | |
1127 | } | |
1128 | ||
1129 | static __init int setup_disablecpuid(char *arg) | |
1130 | { | |
1131 | int bit; | |
1132 | ||
1133 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
1134 | setup_clear_cpu_cap(bit); | |
1135 | else | |
1136 | return 0; | |
1137 | ||
1138 | return 1; | |
1139 | } | |
1140 | __setup("clearcpuid=", setup_disablecpuid); | |
1141 | ||
1142 | #ifdef CONFIG_X86_64 | |
1143 | struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; | |
1144 | struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1, | |
1145 | (unsigned long) debug_idt_table }; | |
1146 | ||
1147 | DEFINE_PER_CPU_FIRST(union irq_stack_union, | |
1148 | irq_stack_union) __aligned(PAGE_SIZE) __visible; | |
1149 | ||
1150 | /* | |
1151 | * The following percpu variables are hot. Align current_task to | |
1152 | * cacheline size such that they fall in the same cacheline. | |
1153 | */ | |
1154 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1155 | &init_task; | |
1156 | EXPORT_PER_CPU_SYMBOL(current_task); | |
1157 | ||
1158 | DEFINE_PER_CPU(char *, irq_stack_ptr) = | |
1159 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; | |
1160 | ||
1161 | DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; | |
1162 | ||
1163 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; | |
1164 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
1165 | ||
1166 | /* | |
1167 | * Special IST stacks which the CPU switches to when it calls | |
1168 | * an IST-marked descriptor entry. Up to 7 stacks (hardware | |
1169 | * limit), all of them are 4K, except the debug stack which | |
1170 | * is 8K. | |
1171 | */ | |
1172 | static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { | |
1173 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
1174 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
1175 | }; | |
1176 | ||
1177 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks | |
1178 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); | |
1179 | ||
1180 | /* May not be marked __init: used by software suspend */ | |
1181 | void syscall_init(void) | |
1182 | { | |
1183 | /* | |
1184 | * LSTAR and STAR live in a bit strange symbiosis. | |
1185 | * They both write to the same internal register. STAR allows to | |
1186 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
1187 | */ | |
1188 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
1189 | wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); | |
1190 | ||
1191 | #ifdef CONFIG_IA32_EMULATION | |
1192 | wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); | |
1193 | /* | |
1194 | * This only works on Intel CPUs. | |
1195 | * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. | |
1196 | * This does not cause SYSENTER to jump to the wrong location, because | |
1197 | * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). | |
1198 | */ | |
1199 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); | |
1200 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); | |
1201 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); | |
1202 | #else | |
1203 | wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); | |
1204 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); | |
1205 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); | |
1206 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); | |
1207 | #endif | |
1208 | ||
1209 | /* Flags to clear on syscall */ | |
1210 | wrmsrl(MSR_SYSCALL_MASK, | |
1211 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| | |
1212 | X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); | |
1213 | } | |
1214 | ||
1215 | /* | |
1216 | * Copies of the original ist values from the tss are only accessed during | |
1217 | * debugging, no special alignment required. | |
1218 | */ | |
1219 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
1220 | ||
1221 | static DEFINE_PER_CPU(unsigned long, debug_stack_addr); | |
1222 | DEFINE_PER_CPU(int, debug_stack_usage); | |
1223 | ||
1224 | int is_debug_stack(unsigned long addr) | |
1225 | { | |
1226 | return __this_cpu_read(debug_stack_usage) || | |
1227 | (addr <= __this_cpu_read(debug_stack_addr) && | |
1228 | addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); | |
1229 | } | |
1230 | NOKPROBE_SYMBOL(is_debug_stack); | |
1231 | ||
1232 | DEFINE_PER_CPU(u32, debug_idt_ctr); | |
1233 | ||
1234 | void debug_stack_set_zero(void) | |
1235 | { | |
1236 | this_cpu_inc(debug_idt_ctr); | |
1237 | load_current_idt(); | |
1238 | } | |
1239 | NOKPROBE_SYMBOL(debug_stack_set_zero); | |
1240 | ||
1241 | void debug_stack_reset(void) | |
1242 | { | |
1243 | if (WARN_ON(!this_cpu_read(debug_idt_ctr))) | |
1244 | return; | |
1245 | if (this_cpu_dec_return(debug_idt_ctr) == 0) | |
1246 | load_current_idt(); | |
1247 | } | |
1248 | NOKPROBE_SYMBOL(debug_stack_reset); | |
1249 | ||
1250 | #else /* CONFIG_X86_64 */ | |
1251 | ||
1252 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; | |
1253 | EXPORT_PER_CPU_SYMBOL(current_task); | |
1254 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; | |
1255 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
1256 | ||
1257 | /* | |
1258 | * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find | |
1259 | * the top of the kernel stack. Use an extra percpu variable to track the | |
1260 | * top of the kernel stack directly. | |
1261 | */ | |
1262 | DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = | |
1263 | (unsigned long)&init_thread_union + THREAD_SIZE; | |
1264 | EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); | |
1265 | ||
1266 | #ifdef CONFIG_CC_STACKPROTECTOR | |
1267 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); | |
1268 | #endif | |
1269 | ||
1270 | #endif /* CONFIG_X86_64 */ | |
1271 | ||
1272 | /* | |
1273 | * Clear all 6 debug registers: | |
1274 | */ | |
1275 | static void clear_all_debug_regs(void) | |
1276 | { | |
1277 | int i; | |
1278 | ||
1279 | for (i = 0; i < 8; i++) { | |
1280 | /* Ignore db4, db5 */ | |
1281 | if ((i == 4) || (i == 5)) | |
1282 | continue; | |
1283 | ||
1284 | set_debugreg(0, i); | |
1285 | } | |
1286 | } | |
1287 | ||
1288 | #ifdef CONFIG_KGDB | |
1289 | /* | |
1290 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1291 | * connection established. | |
1292 | */ | |
1293 | static void dbg_restore_debug_regs(void) | |
1294 | { | |
1295 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1296 | arch_kgdb_ops.correct_hw_break(); | |
1297 | } | |
1298 | #else /* ! CONFIG_KGDB */ | |
1299 | #define dbg_restore_debug_regs() | |
1300 | #endif /* ! CONFIG_KGDB */ | |
1301 | ||
1302 | static void wait_for_master_cpu(int cpu) | |
1303 | { | |
1304 | #ifdef CONFIG_SMP | |
1305 | /* | |
1306 | * wait for ACK from master CPU before continuing | |
1307 | * with AP initialization | |
1308 | */ | |
1309 | WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); | |
1310 | while (!cpumask_test_cpu(cpu, cpu_callout_mask)) | |
1311 | cpu_relax(); | |
1312 | #endif | |
1313 | } | |
1314 | ||
1315 | /* | |
1316 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1317 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1318 | * and IDT. We reload them nevertheless, this function acts as a | |
1319 | * 'CPU state barrier', nothing should get across. | |
1320 | * A lot of state is already set up in PDA init for 64 bit | |
1321 | */ | |
1322 | #ifdef CONFIG_X86_64 | |
1323 | ||
1324 | void cpu_init(void) | |
1325 | { | |
1326 | struct orig_ist *oist; | |
1327 | struct task_struct *me; | |
1328 | struct tss_struct *t; | |
1329 | unsigned long v; | |
1330 | int cpu = stack_smp_processor_id(); | |
1331 | int i; | |
1332 | ||
1333 | wait_for_master_cpu(cpu); | |
1334 | ||
1335 | /* | |
1336 | * Initialize the CR4 shadow before doing anything that could | |
1337 | * try to read it. | |
1338 | */ | |
1339 | cr4_init_shadow(); | |
1340 | ||
1341 | /* | |
1342 | * Load microcode on this cpu if a valid microcode is available. | |
1343 | * This is early microcode loading procedure. | |
1344 | */ | |
1345 | load_ucode_ap(); | |
1346 | ||
1347 | t = &per_cpu(cpu_tss, cpu); | |
1348 | oist = &per_cpu(orig_ist, cpu); | |
1349 | ||
1350 | #ifdef CONFIG_NUMA | |
1351 | if (this_cpu_read(numa_node) == 0 && | |
1352 | early_cpu_to_node(cpu) != NUMA_NO_NODE) | |
1353 | set_numa_node(early_cpu_to_node(cpu)); | |
1354 | #endif | |
1355 | ||
1356 | me = current; | |
1357 | ||
1358 | pr_debug("Initializing CPU#%d\n", cpu); | |
1359 | ||
1360 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1361 | ||
1362 | /* | |
1363 | * Initialize the per-CPU GDT with the boot GDT, | |
1364 | * and set up the GDT descriptor: | |
1365 | */ | |
1366 | ||
1367 | switch_to_new_gdt(cpu); | |
1368 | loadsegment(fs, 0); | |
1369 | ||
1370 | load_current_idt(); | |
1371 | ||
1372 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1373 | syscall_init(); | |
1374 | ||
1375 | wrmsrl(MSR_FS_BASE, 0); | |
1376 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1377 | barrier(); | |
1378 | ||
1379 | x86_configure_nx(); | |
1380 | x2apic_setup(); | |
1381 | ||
1382 | /* | |
1383 | * set up and load the per-CPU TSS | |
1384 | */ | |
1385 | if (!oist->ist[0]) { | |
1386 | char *estacks = per_cpu(exception_stacks, cpu); | |
1387 | ||
1388 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { | |
1389 | estacks += exception_stack_sizes[v]; | |
1390 | oist->ist[v] = t->x86_tss.ist[v] = | |
1391 | (unsigned long)estacks; | |
1392 | if (v == DEBUG_STACK-1) | |
1393 | per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; | |
1394 | } | |
1395 | } | |
1396 | ||
1397 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
1398 | ||
1399 | /* | |
1400 | * <= is required because the CPU will access up to | |
1401 | * 8 bits beyond the end of the IO permission bitmap. | |
1402 | */ | |
1403 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1404 | t->io_bitmap[i] = ~0UL; | |
1405 | ||
1406 | atomic_inc(&init_mm.mm_count); | |
1407 | me->active_mm = &init_mm; | |
1408 | BUG_ON(me->mm); | |
1409 | enter_lazy_tlb(&init_mm, me); | |
1410 | ||
1411 | load_sp0(t, ¤t->thread); | |
1412 | set_tss_desc(cpu, t); | |
1413 | load_TR_desc(); | |
1414 | load_mm_ldt(&init_mm); | |
1415 | ||
1416 | clear_all_debug_regs(); | |
1417 | dbg_restore_debug_regs(); | |
1418 | ||
1419 | fpu__init_cpu(); | |
1420 | ||
1421 | if (is_uv_system()) | |
1422 | uv_cpu_init(); | |
1423 | } | |
1424 | ||
1425 | #else | |
1426 | ||
1427 | void cpu_init(void) | |
1428 | { | |
1429 | int cpu = smp_processor_id(); | |
1430 | struct task_struct *curr = current; | |
1431 | struct tss_struct *t = &per_cpu(cpu_tss, cpu); | |
1432 | struct thread_struct *thread = &curr->thread; | |
1433 | ||
1434 | wait_for_master_cpu(cpu); | |
1435 | ||
1436 | /* | |
1437 | * Initialize the CR4 shadow before doing anything that could | |
1438 | * try to read it. | |
1439 | */ | |
1440 | cr4_init_shadow(); | |
1441 | ||
1442 | show_ucode_info_early(); | |
1443 | ||
1444 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1445 | ||
1446 | if (cpu_feature_enabled(X86_FEATURE_VME) || cpu_has_tsc || cpu_has_de) | |
1447 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1448 | ||
1449 | load_current_idt(); | |
1450 | switch_to_new_gdt(cpu); | |
1451 | ||
1452 | /* | |
1453 | * Set up and load the per-CPU TSS and LDT | |
1454 | */ | |
1455 | atomic_inc(&init_mm.mm_count); | |
1456 | curr->active_mm = &init_mm; | |
1457 | BUG_ON(curr->mm); | |
1458 | enter_lazy_tlb(&init_mm, curr); | |
1459 | ||
1460 | load_sp0(t, thread); | |
1461 | set_tss_desc(cpu, t); | |
1462 | load_TR_desc(); | |
1463 | load_mm_ldt(&init_mm); | |
1464 | ||
1465 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
1466 | ||
1467 | #ifdef CONFIG_DOUBLEFAULT | |
1468 | /* Set up doublefault TSS pointer in the GDT */ | |
1469 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
1470 | #endif | |
1471 | ||
1472 | clear_all_debug_regs(); | |
1473 | dbg_restore_debug_regs(); | |
1474 | ||
1475 | fpu__init_cpu(); | |
1476 | } | |
1477 | #endif | |
1478 | ||
1479 | #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS | |
1480 | void warn_pre_alternatives(void) | |
1481 | { | |
1482 | WARN(1, "You're using static_cpu_has before alternatives have run!\n"); | |
1483 | } | |
1484 | EXPORT_SYMBOL_GPL(warn_pre_alternatives); | |
1485 | #endif | |
1486 | ||
1487 | inline bool __static_cpu_has_safe(u16 bit) | |
1488 | { | |
1489 | return boot_cpu_has(bit); | |
1490 | } | |
1491 | EXPORT_SYMBOL_GPL(__static_cpu_has_safe); | |
1492 | ||
1493 | static void bsp_resume(void) | |
1494 | { | |
1495 | if (this_cpu->c_bsp_resume) | |
1496 | this_cpu->c_bsp_resume(&boot_cpu_data); | |
1497 | } | |
1498 | ||
1499 | static struct syscore_ops cpu_syscore_ops = { | |
1500 | .resume = bsp_resume, | |
1501 | }; | |
1502 | ||
1503 | static int __init init_cpu_syscore(void) | |
1504 | { | |
1505 | register_syscore_ops(&cpu_syscore_ops); | |
1506 | return 0; | |
1507 | } | |
1508 | core_initcall(init_cpu_syscore); |