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1 | /* cpu_feature_enabled() cannot be used this early */ | |
2 | #define USE_EARLY_PGTABLE_L5 | |
3 | ||
4 | #include <linux/bootmem.h> | |
5 | #include <linux/linkage.h> | |
6 | #include <linux/bitops.h> | |
7 | #include <linux/kernel.h> | |
8 | #include <linux/export.h> | |
9 | #include <linux/percpu.h> | |
10 | #include <linux/string.h> | |
11 | #include <linux/ctype.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/sched/mm.h> | |
14 | #include <linux/sched/clock.h> | |
15 | #include <linux/sched/task.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/kprobes.h> | |
18 | #include <linux/kgdb.h> | |
19 | #include <linux/smp.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/syscore_ops.h> | |
22 | ||
23 | #include <asm/stackprotector.h> | |
24 | #include <asm/perf_event.h> | |
25 | #include <asm/mmu_context.h> | |
26 | #include <asm/archrandom.h> | |
27 | #include <asm/hypervisor.h> | |
28 | #include <asm/processor.h> | |
29 | #include <asm/tlbflush.h> | |
30 | #include <asm/debugreg.h> | |
31 | #include <asm/sections.h> | |
32 | #include <asm/vsyscall.h> | |
33 | #include <linux/topology.h> | |
34 | #include <linux/cpumask.h> | |
35 | #include <asm/pgtable.h> | |
36 | #include <linux/atomic.h> | |
37 | #include <asm/proto.h> | |
38 | #include <asm/setup.h> | |
39 | #include <asm/apic.h> | |
40 | #include <asm/desc.h> | |
41 | #include <asm/fpu/internal.h> | |
42 | #include <asm/mtrr.h> | |
43 | #include <asm/hwcap2.h> | |
44 | #include <linux/numa.h> | |
45 | #include <asm/asm.h> | |
46 | #include <asm/bugs.h> | |
47 | #include <asm/cpu.h> | |
48 | #include <asm/mce.h> | |
49 | #include <asm/msr.h> | |
50 | #include <asm/pat.h> | |
51 | #include <asm/microcode.h> | |
52 | #include <asm/microcode_intel.h> | |
53 | #include <asm/intel-family.h> | |
54 | #include <asm/cpu_device_id.h> | |
55 | ||
56 | #ifdef CONFIG_X86_LOCAL_APIC | |
57 | #include <asm/uv/uv.h> | |
58 | #endif | |
59 | ||
60 | #include "cpu.h" | |
61 | ||
62 | u32 elf_hwcap2 __read_mostly; | |
63 | ||
64 | /* all of these masks are initialized in setup_cpu_local_masks() */ | |
65 | cpumask_var_t cpu_initialized_mask; | |
66 | cpumask_var_t cpu_callout_mask; | |
67 | cpumask_var_t cpu_callin_mask; | |
68 | ||
69 | /* representing cpus for which sibling maps can be computed */ | |
70 | cpumask_var_t cpu_sibling_setup_mask; | |
71 | ||
72 | /* Number of siblings per CPU package */ | |
73 | int smp_num_siblings = 1; | |
74 | EXPORT_SYMBOL(smp_num_siblings); | |
75 | ||
76 | /* Last level cache ID of each logical CPU */ | |
77 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; | |
78 | ||
79 | /* correctly size the local cpu masks */ | |
80 | void __init setup_cpu_local_masks(void) | |
81 | { | |
82 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
83 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
84 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
85 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
86 | } | |
87 | ||
88 | static void default_init(struct cpuinfo_x86 *c) | |
89 | { | |
90 | #ifdef CONFIG_X86_64 | |
91 | cpu_detect_cache_sizes(c); | |
92 | #else | |
93 | /* Not much we can do here... */ | |
94 | /* Check if at least it has cpuid */ | |
95 | if (c->cpuid_level == -1) { | |
96 | /* No cpuid. It must be an ancient CPU */ | |
97 | if (c->x86 == 4) | |
98 | strcpy(c->x86_model_id, "486"); | |
99 | else if (c->x86 == 3) | |
100 | strcpy(c->x86_model_id, "386"); | |
101 | } | |
102 | #endif | |
103 | } | |
104 | ||
105 | static const struct cpu_dev default_cpu = { | |
106 | .c_init = default_init, | |
107 | .c_vendor = "Unknown", | |
108 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
109 | }; | |
110 | ||
111 | static const struct cpu_dev *this_cpu = &default_cpu; | |
112 | ||
113 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { | |
114 | #ifdef CONFIG_X86_64 | |
115 | /* | |
116 | * We need valid kernel segments for data and code in long mode too | |
117 | * IRET will check the segment types kkeil 2000/10/28 | |
118 | * Also sysret mandates a special GDT layout | |
119 | * | |
120 | * TLS descriptors are currently at a different place compared to i386. | |
121 | * Hopefully nobody expects them at a fixed place (Wine?) | |
122 | */ | |
123 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), | |
124 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
125 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
126 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
127 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
128 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
129 | #else | |
130 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), | |
131 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
132 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
133 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
134 | /* | |
135 | * Segments used for calling PnP BIOS have byte granularity. | |
136 | * They code segments and data segments have fixed 64k limits, | |
137 | * the transfer segment sizes are set at run time. | |
138 | */ | |
139 | /* 32-bit code */ | |
140 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), | |
141 | /* 16-bit code */ | |
142 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), | |
143 | /* 16-bit data */ | |
144 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), | |
145 | /* 16-bit data */ | |
146 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), | |
147 | /* 16-bit data */ | |
148 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), | |
149 | /* | |
150 | * The APM segments have byte granularity and their bases | |
151 | * are set at run time. All have 64k limits. | |
152 | */ | |
153 | /* 32-bit code */ | |
154 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), | |
155 | /* 16-bit code */ | |
156 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), | |
157 | /* data */ | |
158 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), | |
159 | ||
160 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
161 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
162 | GDT_STACK_CANARY_INIT | |
163 | #endif | |
164 | } }; | |
165 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); | |
166 | ||
167 | static int __init x86_mpx_setup(char *s) | |
168 | { | |
169 | /* require an exact match without trailing characters */ | |
170 | if (strlen(s)) | |
171 | return 0; | |
172 | ||
173 | /* do not emit a message if the feature is not present */ | |
174 | if (!boot_cpu_has(X86_FEATURE_MPX)) | |
175 | return 1; | |
176 | ||
177 | setup_clear_cpu_cap(X86_FEATURE_MPX); | |
178 | pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); | |
179 | return 1; | |
180 | } | |
181 | __setup("nompx", x86_mpx_setup); | |
182 | ||
183 | #ifdef CONFIG_X86_64 | |
184 | static int __init x86_nopcid_setup(char *s) | |
185 | { | |
186 | /* nopcid doesn't accept parameters */ | |
187 | if (s) | |
188 | return -EINVAL; | |
189 | ||
190 | /* do not emit a message if the feature is not present */ | |
191 | if (!boot_cpu_has(X86_FEATURE_PCID)) | |
192 | return 0; | |
193 | ||
194 | setup_clear_cpu_cap(X86_FEATURE_PCID); | |
195 | pr_info("nopcid: PCID feature disabled\n"); | |
196 | return 0; | |
197 | } | |
198 | early_param("nopcid", x86_nopcid_setup); | |
199 | #endif | |
200 | ||
201 | static int __init x86_noinvpcid_setup(char *s) | |
202 | { | |
203 | /* noinvpcid doesn't accept parameters */ | |
204 | if (s) | |
205 | return -EINVAL; | |
206 | ||
207 | /* do not emit a message if the feature is not present */ | |
208 | if (!boot_cpu_has(X86_FEATURE_INVPCID)) | |
209 | return 0; | |
210 | ||
211 | setup_clear_cpu_cap(X86_FEATURE_INVPCID); | |
212 | pr_info("noinvpcid: INVPCID feature disabled\n"); | |
213 | return 0; | |
214 | } | |
215 | early_param("noinvpcid", x86_noinvpcid_setup); | |
216 | ||
217 | #ifdef CONFIG_X86_32 | |
218 | static int cachesize_override = -1; | |
219 | static int disable_x86_serial_nr = 1; | |
220 | ||
221 | static int __init cachesize_setup(char *str) | |
222 | { | |
223 | get_option(&str, &cachesize_override); | |
224 | return 1; | |
225 | } | |
226 | __setup("cachesize=", cachesize_setup); | |
227 | ||
228 | static int __init x86_sep_setup(char *s) | |
229 | { | |
230 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
231 | return 1; | |
232 | } | |
233 | __setup("nosep", x86_sep_setup); | |
234 | ||
235 | /* Standard macro to see if a specific flag is changeable */ | |
236 | static inline int flag_is_changeable_p(u32 flag) | |
237 | { | |
238 | u32 f1, f2; | |
239 | ||
240 | /* | |
241 | * Cyrix and IDT cpus allow disabling of CPUID | |
242 | * so the code below may return different results | |
243 | * when it is executed before and after enabling | |
244 | * the CPUID. Add "volatile" to not allow gcc to | |
245 | * optimize the subsequent calls to this function. | |
246 | */ | |
247 | asm volatile ("pushfl \n\t" | |
248 | "pushfl \n\t" | |
249 | "popl %0 \n\t" | |
250 | "movl %0, %1 \n\t" | |
251 | "xorl %2, %0 \n\t" | |
252 | "pushl %0 \n\t" | |
253 | "popfl \n\t" | |
254 | "pushfl \n\t" | |
255 | "popl %0 \n\t" | |
256 | "popfl \n\t" | |
257 | ||
258 | : "=&r" (f1), "=&r" (f2) | |
259 | : "ir" (flag)); | |
260 | ||
261 | return ((f1^f2) & flag) != 0; | |
262 | } | |
263 | ||
264 | /* Probe for the CPUID instruction */ | |
265 | int have_cpuid_p(void) | |
266 | { | |
267 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
268 | } | |
269 | ||
270 | static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
271 | { | |
272 | unsigned long lo, hi; | |
273 | ||
274 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
275 | return; | |
276 | ||
277 | /* Disable processor serial number: */ | |
278 | ||
279 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
280 | lo |= 0x200000; | |
281 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
282 | ||
283 | pr_notice("CPU serial number disabled.\n"); | |
284 | clear_cpu_cap(c, X86_FEATURE_PN); | |
285 | ||
286 | /* Disabling the serial number may affect the cpuid level */ | |
287 | c->cpuid_level = cpuid_eax(0); | |
288 | } | |
289 | ||
290 | static int __init x86_serial_nr_setup(char *s) | |
291 | { | |
292 | disable_x86_serial_nr = 0; | |
293 | return 1; | |
294 | } | |
295 | __setup("serialnumber", x86_serial_nr_setup); | |
296 | #else | |
297 | static inline int flag_is_changeable_p(u32 flag) | |
298 | { | |
299 | return 1; | |
300 | } | |
301 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
302 | { | |
303 | } | |
304 | #endif | |
305 | ||
306 | static __init int setup_disable_smep(char *arg) | |
307 | { | |
308 | setup_clear_cpu_cap(X86_FEATURE_SMEP); | |
309 | /* Check for things that depend on SMEP being enabled: */ | |
310 | check_mpx_erratum(&boot_cpu_data); | |
311 | return 1; | |
312 | } | |
313 | __setup("nosmep", setup_disable_smep); | |
314 | ||
315 | static __always_inline void setup_smep(struct cpuinfo_x86 *c) | |
316 | { | |
317 | if (cpu_has(c, X86_FEATURE_SMEP)) | |
318 | cr4_set_bits(X86_CR4_SMEP); | |
319 | } | |
320 | ||
321 | static __init int setup_disable_smap(char *arg) | |
322 | { | |
323 | setup_clear_cpu_cap(X86_FEATURE_SMAP); | |
324 | return 1; | |
325 | } | |
326 | __setup("nosmap", setup_disable_smap); | |
327 | ||
328 | static __always_inline void setup_smap(struct cpuinfo_x86 *c) | |
329 | { | |
330 | unsigned long eflags = native_save_fl(); | |
331 | ||
332 | /* This should have been cleared long ago */ | |
333 | BUG_ON(eflags & X86_EFLAGS_AC); | |
334 | ||
335 | if (cpu_has(c, X86_FEATURE_SMAP)) { | |
336 | #ifdef CONFIG_X86_SMAP | |
337 | cr4_set_bits(X86_CR4_SMAP); | |
338 | #else | |
339 | cr4_clear_bits(X86_CR4_SMAP); | |
340 | #endif | |
341 | } | |
342 | } | |
343 | ||
344 | static __always_inline void setup_umip(struct cpuinfo_x86 *c) | |
345 | { | |
346 | /* Check the boot processor, plus build option for UMIP. */ | |
347 | if (!cpu_feature_enabled(X86_FEATURE_UMIP)) | |
348 | goto out; | |
349 | ||
350 | /* Check the current processor's cpuid bits. */ | |
351 | if (!cpu_has(c, X86_FEATURE_UMIP)) | |
352 | goto out; | |
353 | ||
354 | cr4_set_bits(X86_CR4_UMIP); | |
355 | ||
356 | pr_info("x86/cpu: Activated the Intel User Mode Instruction Prevention (UMIP) CPU feature\n"); | |
357 | ||
358 | return; | |
359 | ||
360 | out: | |
361 | /* | |
362 | * Make sure UMIP is disabled in case it was enabled in a | |
363 | * previous boot (e.g., via kexec). | |
364 | */ | |
365 | cr4_clear_bits(X86_CR4_UMIP); | |
366 | } | |
367 | ||
368 | /* | |
369 | * Protection Keys are not available in 32-bit mode. | |
370 | */ | |
371 | static bool pku_disabled; | |
372 | ||
373 | static __always_inline void setup_pku(struct cpuinfo_x86 *c) | |
374 | { | |
375 | /* check the boot processor, plus compile options for PKU: */ | |
376 | if (!cpu_feature_enabled(X86_FEATURE_PKU)) | |
377 | return; | |
378 | /* checks the actual processor's cpuid bits: */ | |
379 | if (!cpu_has(c, X86_FEATURE_PKU)) | |
380 | return; | |
381 | if (pku_disabled) | |
382 | return; | |
383 | ||
384 | cr4_set_bits(X86_CR4_PKE); | |
385 | /* | |
386 | * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE | |
387 | * cpuid bit to be set. We need to ensure that we | |
388 | * update that bit in this CPU's "cpu_info". | |
389 | */ | |
390 | get_cpu_cap(c); | |
391 | } | |
392 | ||
393 | #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS | |
394 | static __init int setup_disable_pku(char *arg) | |
395 | { | |
396 | /* | |
397 | * Do not clear the X86_FEATURE_PKU bit. All of the | |
398 | * runtime checks are against OSPKE so clearing the | |
399 | * bit does nothing. | |
400 | * | |
401 | * This way, we will see "pku" in cpuinfo, but not | |
402 | * "ospke", which is exactly what we want. It shows | |
403 | * that the CPU has PKU, but the OS has not enabled it. | |
404 | * This happens to be exactly how a system would look | |
405 | * if we disabled the config option. | |
406 | */ | |
407 | pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); | |
408 | pku_disabled = true; | |
409 | return 1; | |
410 | } | |
411 | __setup("nopku", setup_disable_pku); | |
412 | #endif /* CONFIG_X86_64 */ | |
413 | ||
414 | /* | |
415 | * Some CPU features depend on higher CPUID levels, which may not always | |
416 | * be available due to CPUID level capping or broken virtualization | |
417 | * software. Add those features to this table to auto-disable them. | |
418 | */ | |
419 | struct cpuid_dependent_feature { | |
420 | u32 feature; | |
421 | u32 level; | |
422 | }; | |
423 | ||
424 | static const struct cpuid_dependent_feature | |
425 | cpuid_dependent_features[] = { | |
426 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
427 | { X86_FEATURE_DCA, 0x00000009 }, | |
428 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
429 | { 0, 0 } | |
430 | }; | |
431 | ||
432 | static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) | |
433 | { | |
434 | const struct cpuid_dependent_feature *df; | |
435 | ||
436 | for (df = cpuid_dependent_features; df->feature; df++) { | |
437 | ||
438 | if (!cpu_has(c, df->feature)) | |
439 | continue; | |
440 | /* | |
441 | * Note: cpuid_level is set to -1 if unavailable, but | |
442 | * extended_extended_level is set to 0 if unavailable | |
443 | * and the legitimate extended levels are all negative | |
444 | * when signed; hence the weird messing around with | |
445 | * signs here... | |
446 | */ | |
447 | if (!((s32)df->level < 0 ? | |
448 | (u32)df->level > (u32)c->extended_cpuid_level : | |
449 | (s32)df->level > (s32)c->cpuid_level)) | |
450 | continue; | |
451 | ||
452 | clear_cpu_cap(c, df->feature); | |
453 | if (!warn) | |
454 | continue; | |
455 | ||
456 | pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", | |
457 | x86_cap_flag(df->feature), df->level); | |
458 | } | |
459 | } | |
460 | ||
461 | /* | |
462 | * Naming convention should be: <Name> [(<Codename>)] | |
463 | * This table only is used unless init_<vendor>() below doesn't set it; | |
464 | * in particular, if CPUID levels 0x80000002..4 are supported, this | |
465 | * isn't used | |
466 | */ | |
467 | ||
468 | /* Look up CPU names by table lookup. */ | |
469 | static const char *table_lookup_model(struct cpuinfo_x86 *c) | |
470 | { | |
471 | #ifdef CONFIG_X86_32 | |
472 | const struct legacy_cpu_model_info *info; | |
473 | ||
474 | if (c->x86_model >= 16) | |
475 | return NULL; /* Range check */ | |
476 | ||
477 | if (!this_cpu) | |
478 | return NULL; | |
479 | ||
480 | info = this_cpu->legacy_models; | |
481 | ||
482 | while (info->family) { | |
483 | if (info->family == c->x86) | |
484 | return info->model_names[c->x86_model]; | |
485 | info++; | |
486 | } | |
487 | #endif | |
488 | return NULL; /* Not found */ | |
489 | } | |
490 | ||
491 | __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; | |
492 | __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; | |
493 | ||
494 | void load_percpu_segment(int cpu) | |
495 | { | |
496 | #ifdef CONFIG_X86_32 | |
497 | loadsegment(fs, __KERNEL_PERCPU); | |
498 | #else | |
499 | __loadsegment_simple(gs, 0); | |
500 | wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); | |
501 | #endif | |
502 | load_stack_canary_segment(); | |
503 | } | |
504 | ||
505 | #ifdef CONFIG_X86_32 | |
506 | /* The 32-bit entry code needs to find cpu_entry_area. */ | |
507 | DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); | |
508 | #endif | |
509 | ||
510 | #ifdef CONFIG_X86_64 | |
511 | /* | |
512 | * Special IST stacks which the CPU switches to when it calls | |
513 | * an IST-marked descriptor entry. Up to 7 stacks (hardware | |
514 | * limit), all of them are 4K, except the debug stack which | |
515 | * is 8K. | |
516 | */ | |
517 | static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { | |
518 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
519 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
520 | }; | |
521 | #endif | |
522 | ||
523 | /* Load the original GDT from the per-cpu structure */ | |
524 | void load_direct_gdt(int cpu) | |
525 | { | |
526 | struct desc_ptr gdt_descr; | |
527 | ||
528 | gdt_descr.address = (long)get_cpu_gdt_rw(cpu); | |
529 | gdt_descr.size = GDT_SIZE - 1; | |
530 | load_gdt(&gdt_descr); | |
531 | } | |
532 | EXPORT_SYMBOL_GPL(load_direct_gdt); | |
533 | ||
534 | /* Load a fixmap remapping of the per-cpu GDT */ | |
535 | void load_fixmap_gdt(int cpu) | |
536 | { | |
537 | struct desc_ptr gdt_descr; | |
538 | ||
539 | gdt_descr.address = (long)get_cpu_gdt_ro(cpu); | |
540 | gdt_descr.size = GDT_SIZE - 1; | |
541 | load_gdt(&gdt_descr); | |
542 | } | |
543 | EXPORT_SYMBOL_GPL(load_fixmap_gdt); | |
544 | ||
545 | /* | |
546 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
547 | * it's on the real one. | |
548 | */ | |
549 | void switch_to_new_gdt(int cpu) | |
550 | { | |
551 | /* Load the original GDT */ | |
552 | load_direct_gdt(cpu); | |
553 | /* Reload the per-cpu base */ | |
554 | load_percpu_segment(cpu); | |
555 | } | |
556 | ||
557 | static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; | |
558 | ||
559 | static void get_model_name(struct cpuinfo_x86 *c) | |
560 | { | |
561 | unsigned int *v; | |
562 | char *p, *q, *s; | |
563 | ||
564 | if (c->extended_cpuid_level < 0x80000004) | |
565 | return; | |
566 | ||
567 | v = (unsigned int *)c->x86_model_id; | |
568 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
569 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
570 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
571 | c->x86_model_id[48] = 0; | |
572 | ||
573 | /* Trim whitespace */ | |
574 | p = q = s = &c->x86_model_id[0]; | |
575 | ||
576 | while (*p == ' ') | |
577 | p++; | |
578 | ||
579 | while (*p) { | |
580 | /* Note the last non-whitespace index */ | |
581 | if (!isspace(*p)) | |
582 | s = q; | |
583 | ||
584 | *q++ = *p++; | |
585 | } | |
586 | ||
587 | *(s + 1) = '\0'; | |
588 | } | |
589 | ||
590 | void detect_num_cpu_cores(struct cpuinfo_x86 *c) | |
591 | { | |
592 | unsigned int eax, ebx, ecx, edx; | |
593 | ||
594 | c->x86_max_cores = 1; | |
595 | if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) | |
596 | return; | |
597 | ||
598 | cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); | |
599 | if (eax & 0x1f) | |
600 | c->x86_max_cores = (eax >> 26) + 1; | |
601 | } | |
602 | ||
603 | void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) | |
604 | { | |
605 | unsigned int n, dummy, ebx, ecx, edx, l2size; | |
606 | ||
607 | n = c->extended_cpuid_level; | |
608 | ||
609 | if (n >= 0x80000005) { | |
610 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); | |
611 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
612 | #ifdef CONFIG_X86_64 | |
613 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
614 | c->x86_tlbsize = 0; | |
615 | #endif | |
616 | } | |
617 | ||
618 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
619 | return; | |
620 | ||
621 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); | |
622 | l2size = ecx >> 16; | |
623 | ||
624 | #ifdef CONFIG_X86_64 | |
625 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
626 | #else | |
627 | /* do processor-specific cache resizing */ | |
628 | if (this_cpu->legacy_cache_size) | |
629 | l2size = this_cpu->legacy_cache_size(c, l2size); | |
630 | ||
631 | /* Allow user to override all this if necessary. */ | |
632 | if (cachesize_override != -1) | |
633 | l2size = cachesize_override; | |
634 | ||
635 | if (l2size == 0) | |
636 | return; /* Again, no L2 cache is possible */ | |
637 | #endif | |
638 | ||
639 | c->x86_cache_size = l2size; | |
640 | } | |
641 | ||
642 | u16 __read_mostly tlb_lli_4k[NR_INFO]; | |
643 | u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
644 | u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
645 | u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
646 | u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
647 | u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
648 | u16 __read_mostly tlb_lld_1g[NR_INFO]; | |
649 | ||
650 | static void cpu_detect_tlb(struct cpuinfo_x86 *c) | |
651 | { | |
652 | if (this_cpu->c_detect_tlb) | |
653 | this_cpu->c_detect_tlb(c); | |
654 | ||
655 | pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", | |
656 | tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], | |
657 | tlb_lli_4m[ENTRIES]); | |
658 | ||
659 | pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", | |
660 | tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], | |
661 | tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); | |
662 | } | |
663 | ||
664 | int detect_ht_early(struct cpuinfo_x86 *c) | |
665 | { | |
666 | #ifdef CONFIG_SMP | |
667 | u32 eax, ebx, ecx, edx; | |
668 | ||
669 | if (!cpu_has(c, X86_FEATURE_HT)) | |
670 | return -1; | |
671 | ||
672 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) | |
673 | return -1; | |
674 | ||
675 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) | |
676 | return -1; | |
677 | ||
678 | cpuid(1, &eax, &ebx, &ecx, &edx); | |
679 | ||
680 | smp_num_siblings = (ebx & 0xff0000) >> 16; | |
681 | if (smp_num_siblings == 1) | |
682 | pr_info_once("CPU0: Hyper-Threading is disabled\n"); | |
683 | #endif | |
684 | return 0; | |
685 | } | |
686 | ||
687 | void detect_ht(struct cpuinfo_x86 *c) | |
688 | { | |
689 | #ifdef CONFIG_SMP | |
690 | int index_msb, core_bits; | |
691 | ||
692 | if (detect_ht_early(c) < 0) | |
693 | return; | |
694 | ||
695 | index_msb = get_count_order(smp_num_siblings); | |
696 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
697 | ||
698 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
699 | ||
700 | index_msb = get_count_order(smp_num_siblings); | |
701 | ||
702 | core_bits = get_count_order(c->x86_max_cores); | |
703 | ||
704 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & | |
705 | ((1 << core_bits) - 1); | |
706 | #endif | |
707 | } | |
708 | ||
709 | static void get_cpu_vendor(struct cpuinfo_x86 *c) | |
710 | { | |
711 | char *v = c->x86_vendor_id; | |
712 | int i; | |
713 | ||
714 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
715 | if (!cpu_devs[i]) | |
716 | break; | |
717 | ||
718 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
719 | (cpu_devs[i]->c_ident[1] && | |
720 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
721 | ||
722 | this_cpu = cpu_devs[i]; | |
723 | c->x86_vendor = this_cpu->c_x86_vendor; | |
724 | return; | |
725 | } | |
726 | } | |
727 | ||
728 | pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ | |
729 | "CPU: Your system may be unstable.\n", v); | |
730 | ||
731 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
732 | this_cpu = &default_cpu; | |
733 | } | |
734 | ||
735 | void cpu_detect(struct cpuinfo_x86 *c) | |
736 | { | |
737 | /* Get vendor name */ | |
738 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, | |
739 | (unsigned int *)&c->x86_vendor_id[0], | |
740 | (unsigned int *)&c->x86_vendor_id[8], | |
741 | (unsigned int *)&c->x86_vendor_id[4]); | |
742 | ||
743 | c->x86 = 4; | |
744 | /* Intel-defined flags: level 0x00000001 */ | |
745 | if (c->cpuid_level >= 0x00000001) { | |
746 | u32 junk, tfms, cap0, misc; | |
747 | ||
748 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
749 | c->x86 = x86_family(tfms); | |
750 | c->x86_model = x86_model(tfms); | |
751 | c->x86_stepping = x86_stepping(tfms); | |
752 | ||
753 | if (cap0 & (1<<19)) { | |
754 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; | |
755 | c->x86_cache_alignment = c->x86_clflush_size; | |
756 | } | |
757 | } | |
758 | } | |
759 | ||
760 | static void apply_forced_caps(struct cpuinfo_x86 *c) | |
761 | { | |
762 | int i; | |
763 | ||
764 | for (i = 0; i < NCAPINTS + NBUGINTS; i++) { | |
765 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
766 | c->x86_capability[i] |= cpu_caps_set[i]; | |
767 | } | |
768 | } | |
769 | ||
770 | static void init_speculation_control(struct cpuinfo_x86 *c) | |
771 | { | |
772 | /* | |
773 | * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, | |
774 | * and they also have a different bit for STIBP support. Also, | |
775 | * a hypervisor might have set the individual AMD bits even on | |
776 | * Intel CPUs, for finer-grained selection of what's available. | |
777 | */ | |
778 | if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { | |
779 | set_cpu_cap(c, X86_FEATURE_IBRS); | |
780 | set_cpu_cap(c, X86_FEATURE_IBPB); | |
781 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); | |
782 | } | |
783 | ||
784 | if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) | |
785 | set_cpu_cap(c, X86_FEATURE_STIBP); | |
786 | ||
787 | if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || | |
788 | cpu_has(c, X86_FEATURE_VIRT_SSBD)) | |
789 | set_cpu_cap(c, X86_FEATURE_SSBD); | |
790 | ||
791 | if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { | |
792 | set_cpu_cap(c, X86_FEATURE_IBRS); | |
793 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); | |
794 | } | |
795 | ||
796 | if (cpu_has(c, X86_FEATURE_AMD_IBPB)) | |
797 | set_cpu_cap(c, X86_FEATURE_IBPB); | |
798 | ||
799 | if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { | |
800 | set_cpu_cap(c, X86_FEATURE_STIBP); | |
801 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); | |
802 | } | |
803 | ||
804 | if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { | |
805 | set_cpu_cap(c, X86_FEATURE_SSBD); | |
806 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); | |
807 | clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); | |
808 | } | |
809 | } | |
810 | ||
811 | void get_cpu_cap(struct cpuinfo_x86 *c) | |
812 | { | |
813 | u32 eax, ebx, ecx, edx; | |
814 | ||
815 | /* Intel-defined flags: level 0x00000001 */ | |
816 | if (c->cpuid_level >= 0x00000001) { | |
817 | cpuid(0x00000001, &eax, &ebx, &ecx, &edx); | |
818 | ||
819 | c->x86_capability[CPUID_1_ECX] = ecx; | |
820 | c->x86_capability[CPUID_1_EDX] = edx; | |
821 | } | |
822 | ||
823 | /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ | |
824 | if (c->cpuid_level >= 0x00000006) | |
825 | c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); | |
826 | ||
827 | /* Additional Intel-defined flags: level 0x00000007 */ | |
828 | if (c->cpuid_level >= 0x00000007) { | |
829 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); | |
830 | c->x86_capability[CPUID_7_0_EBX] = ebx; | |
831 | c->x86_capability[CPUID_7_ECX] = ecx; | |
832 | c->x86_capability[CPUID_7_EDX] = edx; | |
833 | } | |
834 | ||
835 | /* Extended state features: level 0x0000000d */ | |
836 | if (c->cpuid_level >= 0x0000000d) { | |
837 | cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); | |
838 | ||
839 | c->x86_capability[CPUID_D_1_EAX] = eax; | |
840 | } | |
841 | ||
842 | /* Additional Intel-defined flags: level 0x0000000F */ | |
843 | if (c->cpuid_level >= 0x0000000F) { | |
844 | ||
845 | /* QoS sub-leaf, EAX=0Fh, ECX=0 */ | |
846 | cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); | |
847 | c->x86_capability[CPUID_F_0_EDX] = edx; | |
848 | ||
849 | if (cpu_has(c, X86_FEATURE_CQM_LLC)) { | |
850 | /* will be overridden if occupancy monitoring exists */ | |
851 | c->x86_cache_max_rmid = ebx; | |
852 | ||
853 | /* QoS sub-leaf, EAX=0Fh, ECX=1 */ | |
854 | cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); | |
855 | c->x86_capability[CPUID_F_1_EDX] = edx; | |
856 | ||
857 | if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) || | |
858 | ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) || | |
859 | (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) { | |
860 | c->x86_cache_max_rmid = ecx; | |
861 | c->x86_cache_occ_scale = ebx; | |
862 | } | |
863 | } else { | |
864 | c->x86_cache_max_rmid = -1; | |
865 | c->x86_cache_occ_scale = -1; | |
866 | } | |
867 | } | |
868 | ||
869 | /* AMD-defined flags: level 0x80000001 */ | |
870 | eax = cpuid_eax(0x80000000); | |
871 | c->extended_cpuid_level = eax; | |
872 | ||
873 | if ((eax & 0xffff0000) == 0x80000000) { | |
874 | if (eax >= 0x80000001) { | |
875 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
876 | ||
877 | c->x86_capability[CPUID_8000_0001_ECX] = ecx; | |
878 | c->x86_capability[CPUID_8000_0001_EDX] = edx; | |
879 | } | |
880 | } | |
881 | ||
882 | if (c->extended_cpuid_level >= 0x80000007) { | |
883 | cpuid(0x80000007, &eax, &ebx, &ecx, &edx); | |
884 | ||
885 | c->x86_capability[CPUID_8000_0007_EBX] = ebx; | |
886 | c->x86_power = edx; | |
887 | } | |
888 | ||
889 | if (c->extended_cpuid_level >= 0x80000008) { | |
890 | cpuid(0x80000008, &eax, &ebx, &ecx, &edx); | |
891 | c->x86_capability[CPUID_8000_0008_EBX] = ebx; | |
892 | } | |
893 | ||
894 | if (c->extended_cpuid_level >= 0x8000000a) | |
895 | c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); | |
896 | ||
897 | init_scattered_cpuid_features(c); | |
898 | init_speculation_control(c); | |
899 | ||
900 | /* | |
901 | * Clear/Set all flags overridden by options, after probe. | |
902 | * This needs to happen each time we re-probe, which may happen | |
903 | * several times during CPU initialization. | |
904 | */ | |
905 | apply_forced_caps(c); | |
906 | } | |
907 | ||
908 | void get_cpu_address_sizes(struct cpuinfo_x86 *c) | |
909 | { | |
910 | u32 eax, ebx, ecx, edx; | |
911 | ||
912 | if (c->extended_cpuid_level >= 0x80000008) { | |
913 | cpuid(0x80000008, &eax, &ebx, &ecx, &edx); | |
914 | ||
915 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
916 | c->x86_phys_bits = eax & 0xff; | |
917 | } | |
918 | #ifdef CONFIG_X86_32 | |
919 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
920 | c->x86_phys_bits = 36; | |
921 | #endif | |
922 | } | |
923 | ||
924 | static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) | |
925 | { | |
926 | #ifdef CONFIG_X86_32 | |
927 | int i; | |
928 | ||
929 | /* | |
930 | * First of all, decide if this is a 486 or higher | |
931 | * It's a 486 if we can modify the AC flag | |
932 | */ | |
933 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
934 | c->x86 = 4; | |
935 | else | |
936 | c->x86 = 3; | |
937 | ||
938 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
939 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
940 | c->x86_vendor_id[0] = 0; | |
941 | cpu_devs[i]->c_identify(c); | |
942 | if (c->x86_vendor_id[0]) { | |
943 | get_cpu_vendor(c); | |
944 | break; | |
945 | } | |
946 | } | |
947 | #endif | |
948 | } | |
949 | ||
950 | static const __initconst struct x86_cpu_id cpu_no_speculation[] = { | |
951 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CEDARVIEW, X86_FEATURE_ANY }, | |
952 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CLOVERVIEW, X86_FEATURE_ANY }, | |
953 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_LINCROFT, X86_FEATURE_ANY }, | |
954 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PENWELL, X86_FEATURE_ANY }, | |
955 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PINEVIEW, X86_FEATURE_ANY }, | |
956 | { X86_VENDOR_CENTAUR, 5 }, | |
957 | { X86_VENDOR_INTEL, 5 }, | |
958 | { X86_VENDOR_NSC, 5 }, | |
959 | { X86_VENDOR_ANY, 4 }, | |
960 | {} | |
961 | }; | |
962 | ||
963 | static const __initconst struct x86_cpu_id cpu_no_meltdown[] = { | |
964 | { X86_VENDOR_AMD }, | |
965 | {} | |
966 | }; | |
967 | ||
968 | /* Only list CPUs which speculate but are non susceptible to SSB */ | |
969 | static const __initconst struct x86_cpu_id cpu_no_spec_store_bypass[] = { | |
970 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1 }, | |
971 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT }, | |
972 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT2 }, | |
973 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_MERRIFIELD }, | |
974 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_CORE_YONAH }, | |
975 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNL }, | |
976 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNM }, | |
977 | { X86_VENDOR_AMD, 0x12, }, | |
978 | { X86_VENDOR_AMD, 0x11, }, | |
979 | { X86_VENDOR_AMD, 0x10, }, | |
980 | { X86_VENDOR_AMD, 0xf, }, | |
981 | {} | |
982 | }; | |
983 | ||
984 | static const __initconst struct x86_cpu_id cpu_no_l1tf[] = { | |
985 | /* in addition to cpu_no_speculation */ | |
986 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1 }, | |
987 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT2 }, | |
988 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT }, | |
989 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_MERRIFIELD }, | |
990 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_MOOREFIELD }, | |
991 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT }, | |
992 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_DENVERTON }, | |
993 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_GEMINI_LAKE }, | |
994 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNL }, | |
995 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNM }, | |
996 | {} | |
997 | }; | |
998 | ||
999 | static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) | |
1000 | { | |
1001 | u64 ia32_cap = 0; | |
1002 | ||
1003 | if (x86_match_cpu(cpu_no_speculation)) | |
1004 | return; | |
1005 | ||
1006 | setup_force_cpu_bug(X86_BUG_SPECTRE_V1); | |
1007 | setup_force_cpu_bug(X86_BUG_SPECTRE_V2); | |
1008 | ||
1009 | if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES)) | |
1010 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); | |
1011 | ||
1012 | if (!x86_match_cpu(cpu_no_spec_store_bypass) && | |
1013 | !(ia32_cap & ARCH_CAP_SSB_NO) && | |
1014 | !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) | |
1015 | setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); | |
1016 | ||
1017 | if (ia32_cap & ARCH_CAP_IBRS_ALL) | |
1018 | setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); | |
1019 | ||
1020 | if (x86_match_cpu(cpu_no_meltdown)) | |
1021 | return; | |
1022 | ||
1023 | /* Rogue Data Cache Load? No! */ | |
1024 | if (ia32_cap & ARCH_CAP_RDCL_NO) | |
1025 | return; | |
1026 | ||
1027 | setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); | |
1028 | ||
1029 | if (x86_match_cpu(cpu_no_l1tf)) | |
1030 | return; | |
1031 | ||
1032 | setup_force_cpu_bug(X86_BUG_L1TF); | |
1033 | } | |
1034 | ||
1035 | /* | |
1036 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; | |
1037 | * unfortunately, that's not true in practice because of early VIA | |
1038 | * chips and (more importantly) broken virtualizers that are not easy | |
1039 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
1040 | * probing for it doesn't even work. Disable it completely on 32-bit | |
1041 | * unless we can find a reliable way to detect all the broken cases. | |
1042 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). | |
1043 | */ | |
1044 | static void detect_nopl(void) | |
1045 | { | |
1046 | #ifdef CONFIG_X86_32 | |
1047 | setup_clear_cpu_cap(X86_FEATURE_NOPL); | |
1048 | #else | |
1049 | setup_force_cpu_cap(X86_FEATURE_NOPL); | |
1050 | #endif | |
1051 | } | |
1052 | ||
1053 | /* | |
1054 | * Do minimum CPU detection early. | |
1055 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
1056 | * cache alignment. | |
1057 | * The others are not touched to avoid unwanted side effects. | |
1058 | * | |
1059 | * WARNING: this function is only called on the boot CPU. Don't add code | |
1060 | * here that is supposed to run on all CPUs. | |
1061 | */ | |
1062 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) | |
1063 | { | |
1064 | #ifdef CONFIG_X86_64 | |
1065 | c->x86_clflush_size = 64; | |
1066 | c->x86_phys_bits = 36; | |
1067 | c->x86_virt_bits = 48; | |
1068 | #else | |
1069 | c->x86_clflush_size = 32; | |
1070 | c->x86_phys_bits = 32; | |
1071 | c->x86_virt_bits = 32; | |
1072 | #endif | |
1073 | c->x86_cache_alignment = c->x86_clflush_size; | |
1074 | ||
1075 | memset(&c->x86_capability, 0, sizeof c->x86_capability); | |
1076 | c->extended_cpuid_level = 0; | |
1077 | ||
1078 | /* cyrix could have cpuid enabled via c_identify()*/ | |
1079 | if (have_cpuid_p()) { | |
1080 | cpu_detect(c); | |
1081 | get_cpu_vendor(c); | |
1082 | get_cpu_cap(c); | |
1083 | get_cpu_address_sizes(c); | |
1084 | setup_force_cpu_cap(X86_FEATURE_CPUID); | |
1085 | ||
1086 | if (this_cpu->c_early_init) | |
1087 | this_cpu->c_early_init(c); | |
1088 | ||
1089 | c->cpu_index = 0; | |
1090 | filter_cpuid_features(c, false); | |
1091 | ||
1092 | if (this_cpu->c_bsp_init) | |
1093 | this_cpu->c_bsp_init(c); | |
1094 | } else { | |
1095 | identify_cpu_without_cpuid(c); | |
1096 | setup_clear_cpu_cap(X86_FEATURE_CPUID); | |
1097 | } | |
1098 | ||
1099 | setup_force_cpu_cap(X86_FEATURE_ALWAYS); | |
1100 | ||
1101 | cpu_set_bug_bits(c); | |
1102 | ||
1103 | fpu__init_system(c); | |
1104 | ||
1105 | #ifdef CONFIG_X86_32 | |
1106 | /* | |
1107 | * Regardless of whether PCID is enumerated, the SDM says | |
1108 | * that it can't be enabled in 32-bit mode. | |
1109 | */ | |
1110 | setup_clear_cpu_cap(X86_FEATURE_PCID); | |
1111 | #endif | |
1112 | ||
1113 | /* | |
1114 | * Later in the boot process pgtable_l5_enabled() relies on | |
1115 | * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not | |
1116 | * enabled by this point we need to clear the feature bit to avoid | |
1117 | * false-positives at the later stage. | |
1118 | * | |
1119 | * pgtable_l5_enabled() can be false here for several reasons: | |
1120 | * - 5-level paging is disabled compile-time; | |
1121 | * - it's 32-bit kernel; | |
1122 | * - machine doesn't support 5-level paging; | |
1123 | * - user specified 'no5lvl' in kernel command line. | |
1124 | */ | |
1125 | if (!pgtable_l5_enabled()) | |
1126 | setup_clear_cpu_cap(X86_FEATURE_LA57); | |
1127 | ||
1128 | detect_nopl(); | |
1129 | } | |
1130 | ||
1131 | void __init early_cpu_init(void) | |
1132 | { | |
1133 | const struct cpu_dev *const *cdev; | |
1134 | int count = 0; | |
1135 | ||
1136 | #ifdef CONFIG_PROCESSOR_SELECT | |
1137 | pr_info("KERNEL supported cpus:\n"); | |
1138 | #endif | |
1139 | ||
1140 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { | |
1141 | const struct cpu_dev *cpudev = *cdev; | |
1142 | ||
1143 | if (count >= X86_VENDOR_NUM) | |
1144 | break; | |
1145 | cpu_devs[count] = cpudev; | |
1146 | count++; | |
1147 | ||
1148 | #ifdef CONFIG_PROCESSOR_SELECT | |
1149 | { | |
1150 | unsigned int j; | |
1151 | ||
1152 | for (j = 0; j < 2; j++) { | |
1153 | if (!cpudev->c_ident[j]) | |
1154 | continue; | |
1155 | pr_info(" %s %s\n", cpudev->c_vendor, | |
1156 | cpudev->c_ident[j]); | |
1157 | } | |
1158 | } | |
1159 | #endif | |
1160 | } | |
1161 | early_identify_cpu(&boot_cpu_data); | |
1162 | } | |
1163 | ||
1164 | static void detect_null_seg_behavior(struct cpuinfo_x86 *c) | |
1165 | { | |
1166 | #ifdef CONFIG_X86_64 | |
1167 | /* | |
1168 | * Empirically, writing zero to a segment selector on AMD does | |
1169 | * not clear the base, whereas writing zero to a segment | |
1170 | * selector on Intel does clear the base. Intel's behavior | |
1171 | * allows slightly faster context switches in the common case | |
1172 | * where GS is unused by the prev and next threads. | |
1173 | * | |
1174 | * Since neither vendor documents this anywhere that I can see, | |
1175 | * detect it directly instead of hardcoding the choice by | |
1176 | * vendor. | |
1177 | * | |
1178 | * I've designated AMD's behavior as the "bug" because it's | |
1179 | * counterintuitive and less friendly. | |
1180 | */ | |
1181 | ||
1182 | unsigned long old_base, tmp; | |
1183 | rdmsrl(MSR_FS_BASE, old_base); | |
1184 | wrmsrl(MSR_FS_BASE, 1); | |
1185 | loadsegment(fs, 0); | |
1186 | rdmsrl(MSR_FS_BASE, tmp); | |
1187 | if (tmp != 0) | |
1188 | set_cpu_bug(c, X86_BUG_NULL_SEG); | |
1189 | wrmsrl(MSR_FS_BASE, old_base); | |
1190 | #endif | |
1191 | } | |
1192 | ||
1193 | static void generic_identify(struct cpuinfo_x86 *c) | |
1194 | { | |
1195 | c->extended_cpuid_level = 0; | |
1196 | ||
1197 | if (!have_cpuid_p()) | |
1198 | identify_cpu_without_cpuid(c); | |
1199 | ||
1200 | /* cyrix could have cpuid enabled via c_identify()*/ | |
1201 | if (!have_cpuid_p()) | |
1202 | return; | |
1203 | ||
1204 | cpu_detect(c); | |
1205 | ||
1206 | get_cpu_vendor(c); | |
1207 | ||
1208 | get_cpu_cap(c); | |
1209 | ||
1210 | get_cpu_address_sizes(c); | |
1211 | ||
1212 | if (c->cpuid_level >= 0x00000001) { | |
1213 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
1214 | #ifdef CONFIG_X86_32 | |
1215 | # ifdef CONFIG_SMP | |
1216 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); | |
1217 | # else | |
1218 | c->apicid = c->initial_apicid; | |
1219 | # endif | |
1220 | #endif | |
1221 | c->phys_proc_id = c->initial_apicid; | |
1222 | } | |
1223 | ||
1224 | get_model_name(c); /* Default name */ | |
1225 | ||
1226 | detect_null_seg_behavior(c); | |
1227 | ||
1228 | /* | |
1229 | * ESPFIX is a strange bug. All real CPUs have it. Paravirt | |
1230 | * systems that run Linux at CPL > 0 may or may not have the | |
1231 | * issue, but, even if they have the issue, there's absolutely | |
1232 | * nothing we can do about it because we can't use the real IRET | |
1233 | * instruction. | |
1234 | * | |
1235 | * NB: For the time being, only 32-bit kernels support | |
1236 | * X86_BUG_ESPFIX as such. 64-bit kernels directly choose | |
1237 | * whether to apply espfix using paravirt hooks. If any | |
1238 | * non-paravirt system ever shows up that does *not* have the | |
1239 | * ESPFIX issue, we can change this. | |
1240 | */ | |
1241 | #ifdef CONFIG_X86_32 | |
1242 | # ifdef CONFIG_PARAVIRT | |
1243 | do { | |
1244 | extern void native_iret(void); | |
1245 | if (pv_cpu_ops.iret == native_iret) | |
1246 | set_cpu_bug(c, X86_BUG_ESPFIX); | |
1247 | } while (0); | |
1248 | # else | |
1249 | set_cpu_bug(c, X86_BUG_ESPFIX); | |
1250 | # endif | |
1251 | #endif | |
1252 | } | |
1253 | ||
1254 | static void x86_init_cache_qos(struct cpuinfo_x86 *c) | |
1255 | { | |
1256 | /* | |
1257 | * The heavy lifting of max_rmid and cache_occ_scale are handled | |
1258 | * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu | |
1259 | * in case CQM bits really aren't there in this CPU. | |
1260 | */ | |
1261 | if (c != &boot_cpu_data) { | |
1262 | boot_cpu_data.x86_cache_max_rmid = | |
1263 | min(boot_cpu_data.x86_cache_max_rmid, | |
1264 | c->x86_cache_max_rmid); | |
1265 | } | |
1266 | } | |
1267 | ||
1268 | /* | |
1269 | * Validate that ACPI/mptables have the same information about the | |
1270 | * effective APIC id and update the package map. | |
1271 | */ | |
1272 | static void validate_apic_and_package_id(struct cpuinfo_x86 *c) | |
1273 | { | |
1274 | #ifdef CONFIG_SMP | |
1275 | unsigned int apicid, cpu = smp_processor_id(); | |
1276 | ||
1277 | apicid = apic->cpu_present_to_apicid(cpu); | |
1278 | ||
1279 | if (apicid != c->apicid) { | |
1280 | pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", | |
1281 | cpu, apicid, c->initial_apicid); | |
1282 | } | |
1283 | BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); | |
1284 | #else | |
1285 | c->logical_proc_id = 0; | |
1286 | #endif | |
1287 | } | |
1288 | ||
1289 | /* | |
1290 | * This does the hard work of actually picking apart the CPU stuff... | |
1291 | */ | |
1292 | static void identify_cpu(struct cpuinfo_x86 *c) | |
1293 | { | |
1294 | int i; | |
1295 | ||
1296 | c->loops_per_jiffy = loops_per_jiffy; | |
1297 | c->x86_cache_size = 0; | |
1298 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1299 | c->x86_model = c->x86_stepping = 0; /* So far unknown... */ | |
1300 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
1301 | c->x86_model_id[0] = '\0'; /* Unset */ | |
1302 | c->x86_max_cores = 1; | |
1303 | c->x86_coreid_bits = 0; | |
1304 | c->cu_id = 0xff; | |
1305 | #ifdef CONFIG_X86_64 | |
1306 | c->x86_clflush_size = 64; | |
1307 | c->x86_phys_bits = 36; | |
1308 | c->x86_virt_bits = 48; | |
1309 | #else | |
1310 | c->cpuid_level = -1; /* CPUID not detected */ | |
1311 | c->x86_clflush_size = 32; | |
1312 | c->x86_phys_bits = 32; | |
1313 | c->x86_virt_bits = 32; | |
1314 | #endif | |
1315 | c->x86_cache_alignment = c->x86_clflush_size; | |
1316 | memset(&c->x86_capability, 0, sizeof c->x86_capability); | |
1317 | ||
1318 | generic_identify(c); | |
1319 | ||
1320 | if (this_cpu->c_identify) | |
1321 | this_cpu->c_identify(c); | |
1322 | ||
1323 | /* Clear/Set all flags overridden by options, after probe */ | |
1324 | apply_forced_caps(c); | |
1325 | ||
1326 | #ifdef CONFIG_X86_64 | |
1327 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); | |
1328 | #endif | |
1329 | ||
1330 | /* | |
1331 | * Vendor-specific initialization. In this section we | |
1332 | * canonicalize the feature flags, meaning if there are | |
1333 | * features a certain CPU supports which CPUID doesn't | |
1334 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
1335 | * we handle them here. | |
1336 | * | |
1337 | * At the end of this section, c->x86_capability better | |
1338 | * indicate the features this CPU genuinely supports! | |
1339 | */ | |
1340 | if (this_cpu->c_init) | |
1341 | this_cpu->c_init(c); | |
1342 | ||
1343 | /* Disable the PN if appropriate */ | |
1344 | squash_the_stupid_serial_number(c); | |
1345 | ||
1346 | /* Set up SMEP/SMAP/UMIP */ | |
1347 | setup_smep(c); | |
1348 | setup_smap(c); | |
1349 | setup_umip(c); | |
1350 | ||
1351 | /* | |
1352 | * The vendor-specific functions might have changed features. | |
1353 | * Now we do "generic changes." | |
1354 | */ | |
1355 | ||
1356 | /* Filter out anything that depends on CPUID levels we don't have */ | |
1357 | filter_cpuid_features(c, true); | |
1358 | ||
1359 | /* If the model name is still unset, do table lookup. */ | |
1360 | if (!c->x86_model_id[0]) { | |
1361 | const char *p; | |
1362 | p = table_lookup_model(c); | |
1363 | if (p) | |
1364 | strcpy(c->x86_model_id, p); | |
1365 | else | |
1366 | /* Last resort... */ | |
1367 | sprintf(c->x86_model_id, "%02x/%02x", | |
1368 | c->x86, c->x86_model); | |
1369 | } | |
1370 | ||
1371 | #ifdef CONFIG_X86_64 | |
1372 | detect_ht(c); | |
1373 | #endif | |
1374 | ||
1375 | x86_init_rdrand(c); | |
1376 | x86_init_cache_qos(c); | |
1377 | setup_pku(c); | |
1378 | ||
1379 | /* | |
1380 | * Clear/Set all flags overridden by options, need do it | |
1381 | * before following smp all cpus cap AND. | |
1382 | */ | |
1383 | apply_forced_caps(c); | |
1384 | ||
1385 | /* | |
1386 | * On SMP, boot_cpu_data holds the common feature set between | |
1387 | * all CPUs; so make sure that we indicate which features are | |
1388 | * common between the CPUs. The first time this routine gets | |
1389 | * executed, c == &boot_cpu_data. | |
1390 | */ | |
1391 | if (c != &boot_cpu_data) { | |
1392 | /* AND the already accumulated flags with these */ | |
1393 | for (i = 0; i < NCAPINTS; i++) | |
1394 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; | |
1395 | ||
1396 | /* OR, i.e. replicate the bug flags */ | |
1397 | for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) | |
1398 | c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; | |
1399 | } | |
1400 | ||
1401 | /* Init Machine Check Exception if available. */ | |
1402 | mcheck_cpu_init(c); | |
1403 | ||
1404 | select_idle_routine(c); | |
1405 | ||
1406 | #ifdef CONFIG_NUMA | |
1407 | numa_add_cpu(smp_processor_id()); | |
1408 | #endif | |
1409 | } | |
1410 | ||
1411 | /* | |
1412 | * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions | |
1413 | * on 32-bit kernels: | |
1414 | */ | |
1415 | #ifdef CONFIG_X86_32 | |
1416 | void enable_sep_cpu(void) | |
1417 | { | |
1418 | struct tss_struct *tss; | |
1419 | int cpu; | |
1420 | ||
1421 | if (!boot_cpu_has(X86_FEATURE_SEP)) | |
1422 | return; | |
1423 | ||
1424 | cpu = get_cpu(); | |
1425 | tss = &per_cpu(cpu_tss_rw, cpu); | |
1426 | ||
1427 | /* | |
1428 | * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- | |
1429 | * see the big comment in struct x86_hw_tss's definition. | |
1430 | */ | |
1431 | ||
1432 | tss->x86_tss.ss1 = __KERNEL_CS; | |
1433 | wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); | |
1434 | wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); | |
1435 | wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); | |
1436 | ||
1437 | put_cpu(); | |
1438 | } | |
1439 | #endif | |
1440 | ||
1441 | void __init identify_boot_cpu(void) | |
1442 | { | |
1443 | identify_cpu(&boot_cpu_data); | |
1444 | #ifdef CONFIG_X86_32 | |
1445 | sysenter_setup(); | |
1446 | enable_sep_cpu(); | |
1447 | #endif | |
1448 | cpu_detect_tlb(&boot_cpu_data); | |
1449 | } | |
1450 | ||
1451 | void identify_secondary_cpu(struct cpuinfo_x86 *c) | |
1452 | { | |
1453 | BUG_ON(c == &boot_cpu_data); | |
1454 | identify_cpu(c); | |
1455 | #ifdef CONFIG_X86_32 | |
1456 | enable_sep_cpu(); | |
1457 | #endif | |
1458 | mtrr_ap_init(); | |
1459 | validate_apic_and_package_id(c); | |
1460 | x86_spec_ctrl_setup_ap(); | |
1461 | } | |
1462 | ||
1463 | static __init int setup_noclflush(char *arg) | |
1464 | { | |
1465 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); | |
1466 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); | |
1467 | return 1; | |
1468 | } | |
1469 | __setup("noclflush", setup_noclflush); | |
1470 | ||
1471 | void print_cpu_info(struct cpuinfo_x86 *c) | |
1472 | { | |
1473 | const char *vendor = NULL; | |
1474 | ||
1475 | if (c->x86_vendor < X86_VENDOR_NUM) { | |
1476 | vendor = this_cpu->c_vendor; | |
1477 | } else { | |
1478 | if (c->cpuid_level >= 0) | |
1479 | vendor = c->x86_vendor_id; | |
1480 | } | |
1481 | ||
1482 | if (vendor && !strstr(c->x86_model_id, vendor)) | |
1483 | pr_cont("%s ", vendor); | |
1484 | ||
1485 | if (c->x86_model_id[0]) | |
1486 | pr_cont("%s", c->x86_model_id); | |
1487 | else | |
1488 | pr_cont("%d86", c->x86); | |
1489 | ||
1490 | pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); | |
1491 | ||
1492 | if (c->x86_stepping || c->cpuid_level >= 0) | |
1493 | pr_cont(", stepping: 0x%x)\n", c->x86_stepping); | |
1494 | else | |
1495 | pr_cont(")\n"); | |
1496 | } | |
1497 | ||
1498 | /* | |
1499 | * clearcpuid= was already parsed in fpu__init_parse_early_param. | |
1500 | * But we need to keep a dummy __setup around otherwise it would | |
1501 | * show up as an environment variable for init. | |
1502 | */ | |
1503 | static __init int setup_clearcpuid(char *arg) | |
1504 | { | |
1505 | return 1; | |
1506 | } | |
1507 | __setup("clearcpuid=", setup_clearcpuid); | |
1508 | ||
1509 | #ifdef CONFIG_X86_64 | |
1510 | DEFINE_PER_CPU_FIRST(union irq_stack_union, | |
1511 | irq_stack_union) __aligned(PAGE_SIZE) __visible; | |
1512 | EXPORT_PER_CPU_SYMBOL_GPL(irq_stack_union); | |
1513 | ||
1514 | /* | |
1515 | * The following percpu variables are hot. Align current_task to | |
1516 | * cacheline size such that they fall in the same cacheline. | |
1517 | */ | |
1518 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1519 | &init_task; | |
1520 | EXPORT_PER_CPU_SYMBOL(current_task); | |
1521 | ||
1522 | DEFINE_PER_CPU(char *, irq_stack_ptr) = | |
1523 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE; | |
1524 | ||
1525 | DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; | |
1526 | ||
1527 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; | |
1528 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
1529 | ||
1530 | /* May not be marked __init: used by software suspend */ | |
1531 | void syscall_init(void) | |
1532 | { | |
1533 | extern char _entry_trampoline[]; | |
1534 | extern char entry_SYSCALL_64_trampoline[]; | |
1535 | ||
1536 | int cpu = smp_processor_id(); | |
1537 | unsigned long SYSCALL64_entry_trampoline = | |
1538 | (unsigned long)get_cpu_entry_area(cpu)->entry_trampoline + | |
1539 | (entry_SYSCALL_64_trampoline - _entry_trampoline); | |
1540 | ||
1541 | wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); | |
1542 | if (static_cpu_has(X86_FEATURE_PTI)) | |
1543 | wrmsrl(MSR_LSTAR, SYSCALL64_entry_trampoline); | |
1544 | else | |
1545 | wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); | |
1546 | ||
1547 | #ifdef CONFIG_IA32_EMULATION | |
1548 | wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); | |
1549 | /* | |
1550 | * This only works on Intel CPUs. | |
1551 | * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. | |
1552 | * This does not cause SYSENTER to jump to the wrong location, because | |
1553 | * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). | |
1554 | */ | |
1555 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); | |
1556 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1)); | |
1557 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); | |
1558 | #else | |
1559 | wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); | |
1560 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); | |
1561 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); | |
1562 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); | |
1563 | #endif | |
1564 | ||
1565 | /* Flags to clear on syscall */ | |
1566 | wrmsrl(MSR_SYSCALL_MASK, | |
1567 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| | |
1568 | X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); | |
1569 | } | |
1570 | ||
1571 | /* | |
1572 | * Copies of the original ist values from the tss are only accessed during | |
1573 | * debugging, no special alignment required. | |
1574 | */ | |
1575 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
1576 | ||
1577 | static DEFINE_PER_CPU(unsigned long, debug_stack_addr); | |
1578 | DEFINE_PER_CPU(int, debug_stack_usage); | |
1579 | ||
1580 | int is_debug_stack(unsigned long addr) | |
1581 | { | |
1582 | return __this_cpu_read(debug_stack_usage) || | |
1583 | (addr <= __this_cpu_read(debug_stack_addr) && | |
1584 | addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); | |
1585 | } | |
1586 | NOKPROBE_SYMBOL(is_debug_stack); | |
1587 | ||
1588 | DEFINE_PER_CPU(u32, debug_idt_ctr); | |
1589 | ||
1590 | void debug_stack_set_zero(void) | |
1591 | { | |
1592 | this_cpu_inc(debug_idt_ctr); | |
1593 | load_current_idt(); | |
1594 | } | |
1595 | NOKPROBE_SYMBOL(debug_stack_set_zero); | |
1596 | ||
1597 | void debug_stack_reset(void) | |
1598 | { | |
1599 | if (WARN_ON(!this_cpu_read(debug_idt_ctr))) | |
1600 | return; | |
1601 | if (this_cpu_dec_return(debug_idt_ctr) == 0) | |
1602 | load_current_idt(); | |
1603 | } | |
1604 | NOKPROBE_SYMBOL(debug_stack_reset); | |
1605 | ||
1606 | #else /* CONFIG_X86_64 */ | |
1607 | ||
1608 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; | |
1609 | EXPORT_PER_CPU_SYMBOL(current_task); | |
1610 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; | |
1611 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
1612 | ||
1613 | /* | |
1614 | * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find | |
1615 | * the top of the kernel stack. Use an extra percpu variable to track the | |
1616 | * top of the kernel stack directly. | |
1617 | */ | |
1618 | DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = | |
1619 | (unsigned long)&init_thread_union + THREAD_SIZE; | |
1620 | EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); | |
1621 | ||
1622 | #ifdef CONFIG_STACKPROTECTOR | |
1623 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); | |
1624 | #endif | |
1625 | ||
1626 | #endif /* CONFIG_X86_64 */ | |
1627 | ||
1628 | /* | |
1629 | * Clear all 6 debug registers: | |
1630 | */ | |
1631 | static void clear_all_debug_regs(void) | |
1632 | { | |
1633 | int i; | |
1634 | ||
1635 | for (i = 0; i < 8; i++) { | |
1636 | /* Ignore db4, db5 */ | |
1637 | if ((i == 4) || (i == 5)) | |
1638 | continue; | |
1639 | ||
1640 | set_debugreg(0, i); | |
1641 | } | |
1642 | } | |
1643 | ||
1644 | #ifdef CONFIG_KGDB | |
1645 | /* | |
1646 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1647 | * connection established. | |
1648 | */ | |
1649 | static void dbg_restore_debug_regs(void) | |
1650 | { | |
1651 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1652 | arch_kgdb_ops.correct_hw_break(); | |
1653 | } | |
1654 | #else /* ! CONFIG_KGDB */ | |
1655 | #define dbg_restore_debug_regs() | |
1656 | #endif /* ! CONFIG_KGDB */ | |
1657 | ||
1658 | static void wait_for_master_cpu(int cpu) | |
1659 | { | |
1660 | #ifdef CONFIG_SMP | |
1661 | /* | |
1662 | * wait for ACK from master CPU before continuing | |
1663 | * with AP initialization | |
1664 | */ | |
1665 | WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); | |
1666 | while (!cpumask_test_cpu(cpu, cpu_callout_mask)) | |
1667 | cpu_relax(); | |
1668 | #endif | |
1669 | } | |
1670 | ||
1671 | /* | |
1672 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1673 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1674 | * and IDT. We reload them nevertheless, this function acts as a | |
1675 | * 'CPU state barrier', nothing should get across. | |
1676 | * A lot of state is already set up in PDA init for 64 bit | |
1677 | */ | |
1678 | #ifdef CONFIG_X86_64 | |
1679 | ||
1680 | void cpu_init(void) | |
1681 | { | |
1682 | struct orig_ist *oist; | |
1683 | struct task_struct *me; | |
1684 | struct tss_struct *t; | |
1685 | unsigned long v; | |
1686 | int cpu = raw_smp_processor_id(); | |
1687 | int i; | |
1688 | ||
1689 | wait_for_master_cpu(cpu); | |
1690 | ||
1691 | /* | |
1692 | * Initialize the CR4 shadow before doing anything that could | |
1693 | * try to read it. | |
1694 | */ | |
1695 | cr4_init_shadow(); | |
1696 | ||
1697 | if (cpu) | |
1698 | load_ucode_ap(); | |
1699 | ||
1700 | t = &per_cpu(cpu_tss_rw, cpu); | |
1701 | oist = &per_cpu(orig_ist, cpu); | |
1702 | ||
1703 | #ifdef CONFIG_NUMA | |
1704 | if (this_cpu_read(numa_node) == 0 && | |
1705 | early_cpu_to_node(cpu) != NUMA_NO_NODE) | |
1706 | set_numa_node(early_cpu_to_node(cpu)); | |
1707 | #endif | |
1708 | ||
1709 | me = current; | |
1710 | ||
1711 | pr_debug("Initializing CPU#%d\n", cpu); | |
1712 | ||
1713 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1714 | ||
1715 | /* | |
1716 | * Initialize the per-CPU GDT with the boot GDT, | |
1717 | * and set up the GDT descriptor: | |
1718 | */ | |
1719 | ||
1720 | switch_to_new_gdt(cpu); | |
1721 | loadsegment(fs, 0); | |
1722 | ||
1723 | load_current_idt(); | |
1724 | ||
1725 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1726 | syscall_init(); | |
1727 | ||
1728 | wrmsrl(MSR_FS_BASE, 0); | |
1729 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1730 | barrier(); | |
1731 | ||
1732 | x86_configure_nx(); | |
1733 | x2apic_setup(); | |
1734 | ||
1735 | /* | |
1736 | * set up and load the per-CPU TSS | |
1737 | */ | |
1738 | if (!oist->ist[0]) { | |
1739 | char *estacks = get_cpu_entry_area(cpu)->exception_stacks; | |
1740 | ||
1741 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { | |
1742 | estacks += exception_stack_sizes[v]; | |
1743 | oist->ist[v] = t->x86_tss.ist[v] = | |
1744 | (unsigned long)estacks; | |
1745 | if (v == DEBUG_STACK-1) | |
1746 | per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; | |
1747 | } | |
1748 | } | |
1749 | ||
1750 | t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; | |
1751 | ||
1752 | /* | |
1753 | * <= is required because the CPU will access up to | |
1754 | * 8 bits beyond the end of the IO permission bitmap. | |
1755 | */ | |
1756 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1757 | t->io_bitmap[i] = ~0UL; | |
1758 | ||
1759 | mmgrab(&init_mm); | |
1760 | me->active_mm = &init_mm; | |
1761 | BUG_ON(me->mm); | |
1762 | initialize_tlbstate_and_flush(); | |
1763 | enter_lazy_tlb(&init_mm, me); | |
1764 | ||
1765 | /* | |
1766 | * Initialize the TSS. sp0 points to the entry trampoline stack | |
1767 | * regardless of what task is running. | |
1768 | */ | |
1769 | set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); | |
1770 | load_TR_desc(); | |
1771 | load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); | |
1772 | ||
1773 | load_mm_ldt(&init_mm); | |
1774 | ||
1775 | clear_all_debug_regs(); | |
1776 | dbg_restore_debug_regs(); | |
1777 | ||
1778 | fpu__init_cpu(); | |
1779 | ||
1780 | if (is_uv_system()) | |
1781 | uv_cpu_init(); | |
1782 | ||
1783 | load_fixmap_gdt(cpu); | |
1784 | } | |
1785 | ||
1786 | #else | |
1787 | ||
1788 | void cpu_init(void) | |
1789 | { | |
1790 | int cpu = smp_processor_id(); | |
1791 | struct task_struct *curr = current; | |
1792 | struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu); | |
1793 | ||
1794 | wait_for_master_cpu(cpu); | |
1795 | ||
1796 | /* | |
1797 | * Initialize the CR4 shadow before doing anything that could | |
1798 | * try to read it. | |
1799 | */ | |
1800 | cr4_init_shadow(); | |
1801 | ||
1802 | show_ucode_info_early(); | |
1803 | ||
1804 | pr_info("Initializing CPU#%d\n", cpu); | |
1805 | ||
1806 | if (cpu_feature_enabled(X86_FEATURE_VME) || | |
1807 | boot_cpu_has(X86_FEATURE_TSC) || | |
1808 | boot_cpu_has(X86_FEATURE_DE)) | |
1809 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1810 | ||
1811 | load_current_idt(); | |
1812 | switch_to_new_gdt(cpu); | |
1813 | ||
1814 | /* | |
1815 | * Set up and load the per-CPU TSS and LDT | |
1816 | */ | |
1817 | mmgrab(&init_mm); | |
1818 | curr->active_mm = &init_mm; | |
1819 | BUG_ON(curr->mm); | |
1820 | initialize_tlbstate_and_flush(); | |
1821 | enter_lazy_tlb(&init_mm, curr); | |
1822 | ||
1823 | /* | |
1824 | * Initialize the TSS. sp0 points to the entry trampoline stack | |
1825 | * regardless of what task is running. | |
1826 | */ | |
1827 | set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); | |
1828 | load_TR_desc(); | |
1829 | load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); | |
1830 | ||
1831 | load_mm_ldt(&init_mm); | |
1832 | ||
1833 | t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; | |
1834 | ||
1835 | #ifdef CONFIG_DOUBLEFAULT | |
1836 | /* Set up doublefault TSS pointer in the GDT */ | |
1837 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
1838 | #endif | |
1839 | ||
1840 | clear_all_debug_regs(); | |
1841 | dbg_restore_debug_regs(); | |
1842 | ||
1843 | fpu__init_cpu(); | |
1844 | ||
1845 | load_fixmap_gdt(cpu); | |
1846 | } | |
1847 | #endif | |
1848 | ||
1849 | static void bsp_resume(void) | |
1850 | { | |
1851 | if (this_cpu->c_bsp_resume) | |
1852 | this_cpu->c_bsp_resume(&boot_cpu_data); | |
1853 | } | |
1854 | ||
1855 | static struct syscore_ops cpu_syscore_ops = { | |
1856 | .resume = bsp_resume, | |
1857 | }; | |
1858 | ||
1859 | static int __init init_cpu_syscore(void) | |
1860 | { | |
1861 | register_syscore_ops(&cpu_syscore_ops); | |
1862 | return 0; | |
1863 | } | |
1864 | core_initcall(init_cpu_syscore); | |
1865 | ||
1866 | /* | |
1867 | * The microcode loader calls this upon late microcode load to recheck features, | |
1868 | * only when microcode has been updated. Caller holds microcode_mutex and CPU | |
1869 | * hotplug lock. | |
1870 | */ | |
1871 | void microcode_check(void) | |
1872 | { | |
1873 | struct cpuinfo_x86 info; | |
1874 | ||
1875 | perf_check_microcode(); | |
1876 | ||
1877 | /* Reload CPUID max function as it might've changed. */ | |
1878 | info.cpuid_level = cpuid_eax(0); | |
1879 | ||
1880 | /* | |
1881 | * Copy all capability leafs to pick up the synthetic ones so that | |
1882 | * memcmp() below doesn't fail on that. The ones coming from CPUID will | |
1883 | * get overwritten in get_cpu_cap(). | |
1884 | */ | |
1885 | memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); | |
1886 | ||
1887 | get_cpu_cap(&info); | |
1888 | ||
1889 | if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) | |
1890 | return; | |
1891 | ||
1892 | pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); | |
1893 | pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); | |
1894 | } |