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1 | #include <linux/bootmem.h> | |
2 | #include <linux/linkage.h> | |
3 | #include <linux/bitops.h> | |
4 | #include <linux/kernel.h> | |
5 | #include <linux/module.h> | |
6 | #include <linux/percpu.h> | |
7 | #include <linux/string.h> | |
8 | #include <linux/delay.h> | |
9 | #include <linux/sched.h> | |
10 | #include <linux/init.h> | |
11 | #include <linux/kgdb.h> | |
12 | #include <linux/smp.h> | |
13 | #include <linux/io.h> | |
14 | ||
15 | #include <asm/stackprotector.h> | |
16 | #include <asm/perf_event.h> | |
17 | #include <asm/mmu_context.h> | |
18 | #include <asm/hypervisor.h> | |
19 | #include <asm/processor.h> | |
20 | #include <asm/sections.h> | |
21 | #include <linux/topology.h> | |
22 | #include <linux/cpumask.h> | |
23 | #include <asm/pgtable.h> | |
24 | #include <asm/atomic.h> | |
25 | #include <asm/proto.h> | |
26 | #include <asm/setup.h> | |
27 | #include <asm/apic.h> | |
28 | #include <asm/desc.h> | |
29 | #include <asm/i387.h> | |
30 | #include <asm/mtrr.h> | |
31 | #include <linux/numa.h> | |
32 | #include <asm/asm.h> | |
33 | #include <asm/cpu.h> | |
34 | #include <asm/mce.h> | |
35 | #include <asm/msr.h> | |
36 | #include <asm/pat.h> | |
37 | ||
38 | #ifdef CONFIG_X86_LOCAL_APIC | |
39 | #include <asm/uv/uv.h> | |
40 | #endif | |
41 | ||
42 | #include "cpu.h" | |
43 | ||
44 | /* all of these masks are initialized in setup_cpu_local_masks() */ | |
45 | cpumask_var_t cpu_initialized_mask; | |
46 | cpumask_var_t cpu_callout_mask; | |
47 | cpumask_var_t cpu_callin_mask; | |
48 | ||
49 | /* representing cpus for which sibling maps can be computed */ | |
50 | cpumask_var_t cpu_sibling_setup_mask; | |
51 | ||
52 | /* correctly size the local cpu masks */ | |
53 | void __init setup_cpu_local_masks(void) | |
54 | { | |
55 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
56 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
57 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
58 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
59 | } | |
60 | ||
61 | static void __cpuinit default_init(struct cpuinfo_x86 *c) | |
62 | { | |
63 | #ifdef CONFIG_X86_64 | |
64 | cpu_detect_cache_sizes(c); | |
65 | #else | |
66 | /* Not much we can do here... */ | |
67 | /* Check if at least it has cpuid */ | |
68 | if (c->cpuid_level == -1) { | |
69 | /* No cpuid. It must be an ancient CPU */ | |
70 | if (c->x86 == 4) | |
71 | strcpy(c->x86_model_id, "486"); | |
72 | else if (c->x86 == 3) | |
73 | strcpy(c->x86_model_id, "386"); | |
74 | } | |
75 | #endif | |
76 | } | |
77 | ||
78 | static const struct cpu_dev __cpuinitconst default_cpu = { | |
79 | .c_init = default_init, | |
80 | .c_vendor = "Unknown", | |
81 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
82 | }; | |
83 | ||
84 | static const struct cpu_dev *this_cpu __cpuinitdata = &default_cpu; | |
85 | ||
86 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { | |
87 | #ifdef CONFIG_X86_64 | |
88 | /* | |
89 | * We need valid kernel segments for data and code in long mode too | |
90 | * IRET will check the segment types kkeil 2000/10/28 | |
91 | * Also sysret mandates a special GDT layout | |
92 | * | |
93 | * TLS descriptors are currently at a different place compared to i386. | |
94 | * Hopefully nobody expects them at a fixed place (Wine?) | |
95 | */ | |
96 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), | |
97 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
98 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
99 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
100 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
101 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
102 | #else | |
103 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), | |
104 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
105 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
106 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
107 | /* | |
108 | * Segments used for calling PnP BIOS have byte granularity. | |
109 | * They code segments and data segments have fixed 64k limits, | |
110 | * the transfer segment sizes are set at run time. | |
111 | */ | |
112 | /* 32-bit code */ | |
113 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), | |
114 | /* 16-bit code */ | |
115 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), | |
116 | /* 16-bit data */ | |
117 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), | |
118 | /* 16-bit data */ | |
119 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), | |
120 | /* 16-bit data */ | |
121 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), | |
122 | /* | |
123 | * The APM segments have byte granularity and their bases | |
124 | * are set at run time. All have 64k limits. | |
125 | */ | |
126 | /* 32-bit code */ | |
127 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), | |
128 | /* 16-bit code */ | |
129 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), | |
130 | /* data */ | |
131 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), | |
132 | ||
133 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
134 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
135 | GDT_STACK_CANARY_INIT | |
136 | #endif | |
137 | } }; | |
138 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); | |
139 | ||
140 | static int __init x86_xsave_setup(char *s) | |
141 | { | |
142 | setup_clear_cpu_cap(X86_FEATURE_XSAVE); | |
143 | return 1; | |
144 | } | |
145 | __setup("noxsave", x86_xsave_setup); | |
146 | ||
147 | #ifdef CONFIG_X86_32 | |
148 | static int cachesize_override __cpuinitdata = -1; | |
149 | static int disable_x86_serial_nr __cpuinitdata = 1; | |
150 | ||
151 | static int __init cachesize_setup(char *str) | |
152 | { | |
153 | get_option(&str, &cachesize_override); | |
154 | return 1; | |
155 | } | |
156 | __setup("cachesize=", cachesize_setup); | |
157 | ||
158 | static int __init x86_fxsr_setup(char *s) | |
159 | { | |
160 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
161 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
162 | return 1; | |
163 | } | |
164 | __setup("nofxsr", x86_fxsr_setup); | |
165 | ||
166 | static int __init x86_sep_setup(char *s) | |
167 | { | |
168 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
169 | return 1; | |
170 | } | |
171 | __setup("nosep", x86_sep_setup); | |
172 | ||
173 | /* Standard macro to see if a specific flag is changeable */ | |
174 | static inline int flag_is_changeable_p(u32 flag) | |
175 | { | |
176 | u32 f1, f2; | |
177 | ||
178 | /* | |
179 | * Cyrix and IDT cpus allow disabling of CPUID | |
180 | * so the code below may return different results | |
181 | * when it is executed before and after enabling | |
182 | * the CPUID. Add "volatile" to not allow gcc to | |
183 | * optimize the subsequent calls to this function. | |
184 | */ | |
185 | asm volatile ("pushfl \n\t" | |
186 | "pushfl \n\t" | |
187 | "popl %0 \n\t" | |
188 | "movl %0, %1 \n\t" | |
189 | "xorl %2, %0 \n\t" | |
190 | "pushl %0 \n\t" | |
191 | "popfl \n\t" | |
192 | "pushfl \n\t" | |
193 | "popl %0 \n\t" | |
194 | "popfl \n\t" | |
195 | ||
196 | : "=&r" (f1), "=&r" (f2) | |
197 | : "ir" (flag)); | |
198 | ||
199 | return ((f1^f2) & flag) != 0; | |
200 | } | |
201 | ||
202 | /* Probe for the CPUID instruction */ | |
203 | static int __cpuinit have_cpuid_p(void) | |
204 | { | |
205 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
206 | } | |
207 | ||
208 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
209 | { | |
210 | unsigned long lo, hi; | |
211 | ||
212 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
213 | return; | |
214 | ||
215 | /* Disable processor serial number: */ | |
216 | ||
217 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
218 | lo |= 0x200000; | |
219 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
220 | ||
221 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
222 | clear_cpu_cap(c, X86_FEATURE_PN); | |
223 | ||
224 | /* Disabling the serial number may affect the cpuid level */ | |
225 | c->cpuid_level = cpuid_eax(0); | |
226 | } | |
227 | ||
228 | static int __init x86_serial_nr_setup(char *s) | |
229 | { | |
230 | disable_x86_serial_nr = 0; | |
231 | return 1; | |
232 | } | |
233 | __setup("serialnumber", x86_serial_nr_setup); | |
234 | #else | |
235 | static inline int flag_is_changeable_p(u32 flag) | |
236 | { | |
237 | return 1; | |
238 | } | |
239 | /* Probe for the CPUID instruction */ | |
240 | static inline int have_cpuid_p(void) | |
241 | { | |
242 | return 1; | |
243 | } | |
244 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
245 | { | |
246 | } | |
247 | #endif | |
248 | ||
249 | /* | |
250 | * Some CPU features depend on higher CPUID levels, which may not always | |
251 | * be available due to CPUID level capping or broken virtualization | |
252 | * software. Add those features to this table to auto-disable them. | |
253 | */ | |
254 | struct cpuid_dependent_feature { | |
255 | u32 feature; | |
256 | u32 level; | |
257 | }; | |
258 | ||
259 | static const struct cpuid_dependent_feature __cpuinitconst | |
260 | cpuid_dependent_features[] = { | |
261 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
262 | { X86_FEATURE_DCA, 0x00000009 }, | |
263 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
264 | { 0, 0 } | |
265 | }; | |
266 | ||
267 | static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) | |
268 | { | |
269 | const struct cpuid_dependent_feature *df; | |
270 | ||
271 | for (df = cpuid_dependent_features; df->feature; df++) { | |
272 | ||
273 | if (!cpu_has(c, df->feature)) | |
274 | continue; | |
275 | /* | |
276 | * Note: cpuid_level is set to -1 if unavailable, but | |
277 | * extended_extended_level is set to 0 if unavailable | |
278 | * and the legitimate extended levels are all negative | |
279 | * when signed; hence the weird messing around with | |
280 | * signs here... | |
281 | */ | |
282 | if (!((s32)df->level < 0 ? | |
283 | (u32)df->level > (u32)c->extended_cpuid_level : | |
284 | (s32)df->level > (s32)c->cpuid_level)) | |
285 | continue; | |
286 | ||
287 | clear_cpu_cap(c, df->feature); | |
288 | if (!warn) | |
289 | continue; | |
290 | ||
291 | printk(KERN_WARNING | |
292 | "CPU: CPU feature %s disabled, no CPUID level 0x%x\n", | |
293 | x86_cap_flags[df->feature], df->level); | |
294 | } | |
295 | } | |
296 | ||
297 | /* | |
298 | * Naming convention should be: <Name> [(<Codename>)] | |
299 | * This table only is used unless init_<vendor>() below doesn't set it; | |
300 | * in particular, if CPUID levels 0x80000002..4 are supported, this | |
301 | * isn't used | |
302 | */ | |
303 | ||
304 | /* Look up CPU names by table lookup. */ | |
305 | static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c) | |
306 | { | |
307 | const struct cpu_model_info *info; | |
308 | ||
309 | if (c->x86_model >= 16) | |
310 | return NULL; /* Range check */ | |
311 | ||
312 | if (!this_cpu) | |
313 | return NULL; | |
314 | ||
315 | info = this_cpu->c_models; | |
316 | ||
317 | while (info && info->family) { | |
318 | if (info->family == c->x86) | |
319 | return info->model_names[c->x86_model]; | |
320 | info++; | |
321 | } | |
322 | return NULL; /* Not found */ | |
323 | } | |
324 | ||
325 | __u32 cpu_caps_cleared[NCAPINTS] __cpuinitdata; | |
326 | __u32 cpu_caps_set[NCAPINTS] __cpuinitdata; | |
327 | ||
328 | void load_percpu_segment(int cpu) | |
329 | { | |
330 | #ifdef CONFIG_X86_32 | |
331 | loadsegment(fs, __KERNEL_PERCPU); | |
332 | #else | |
333 | loadsegment(gs, 0); | |
334 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); | |
335 | #endif | |
336 | load_stack_canary_segment(); | |
337 | } | |
338 | ||
339 | /* | |
340 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
341 | * it's on the real one. | |
342 | */ | |
343 | void switch_to_new_gdt(int cpu) | |
344 | { | |
345 | struct desc_ptr gdt_descr; | |
346 | ||
347 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); | |
348 | gdt_descr.size = GDT_SIZE - 1; | |
349 | load_gdt(&gdt_descr); | |
350 | /* Reload the per-cpu base */ | |
351 | ||
352 | load_percpu_segment(cpu); | |
353 | } | |
354 | ||
355 | static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {}; | |
356 | ||
357 | static void __cpuinit get_model_name(struct cpuinfo_x86 *c) | |
358 | { | |
359 | unsigned int *v; | |
360 | char *p, *q; | |
361 | ||
362 | if (c->extended_cpuid_level < 0x80000004) | |
363 | return; | |
364 | ||
365 | v = (unsigned int *)c->x86_model_id; | |
366 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
367 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
368 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
369 | c->x86_model_id[48] = 0; | |
370 | ||
371 | /* | |
372 | * Intel chips right-justify this string for some dumb reason; | |
373 | * undo that brain damage: | |
374 | */ | |
375 | p = q = &c->x86_model_id[0]; | |
376 | while (*p == ' ') | |
377 | p++; | |
378 | if (p != q) { | |
379 | while (*p) | |
380 | *q++ = *p++; | |
381 | while (q <= &c->x86_model_id[48]) | |
382 | *q++ = '\0'; /* Zero-pad the rest */ | |
383 | } | |
384 | } | |
385 | ||
386 | void __cpuinit cpu_detect_cache_sizes(struct cpuinfo_x86 *c) | |
387 | { | |
388 | unsigned int n, dummy, ebx, ecx, edx, l2size; | |
389 | ||
390 | n = c->extended_cpuid_level; | |
391 | ||
392 | if (n >= 0x80000005) { | |
393 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); | |
394 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
395 | #ifdef CONFIG_X86_64 | |
396 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
397 | c->x86_tlbsize = 0; | |
398 | #endif | |
399 | } | |
400 | ||
401 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
402 | return; | |
403 | ||
404 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); | |
405 | l2size = ecx >> 16; | |
406 | ||
407 | #ifdef CONFIG_X86_64 | |
408 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
409 | #else | |
410 | /* do processor-specific cache resizing */ | |
411 | if (this_cpu->c_size_cache) | |
412 | l2size = this_cpu->c_size_cache(c, l2size); | |
413 | ||
414 | /* Allow user to override all this if necessary. */ | |
415 | if (cachesize_override != -1) | |
416 | l2size = cachesize_override; | |
417 | ||
418 | if (l2size == 0) | |
419 | return; /* Again, no L2 cache is possible */ | |
420 | #endif | |
421 | ||
422 | c->x86_cache_size = l2size; | |
423 | } | |
424 | ||
425 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) | |
426 | { | |
427 | #ifdef CONFIG_X86_HT | |
428 | u32 eax, ebx, ecx, edx; | |
429 | int index_msb, core_bits; | |
430 | static bool printed; | |
431 | ||
432 | if (!cpu_has(c, X86_FEATURE_HT)) | |
433 | return; | |
434 | ||
435 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) | |
436 | goto out; | |
437 | ||
438 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) | |
439 | return; | |
440 | ||
441 | cpuid(1, &eax, &ebx, &ecx, &edx); | |
442 | ||
443 | smp_num_siblings = (ebx & 0xff0000) >> 16; | |
444 | ||
445 | if (smp_num_siblings == 1) { | |
446 | printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n"); | |
447 | goto out; | |
448 | } | |
449 | ||
450 | if (smp_num_siblings <= 1) | |
451 | goto out; | |
452 | ||
453 | if (smp_num_siblings > nr_cpu_ids) { | |
454 | pr_warning("CPU: Unsupported number of siblings %d", | |
455 | smp_num_siblings); | |
456 | smp_num_siblings = 1; | |
457 | return; | |
458 | } | |
459 | ||
460 | index_msb = get_count_order(smp_num_siblings); | |
461 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
462 | ||
463 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
464 | ||
465 | index_msb = get_count_order(smp_num_siblings); | |
466 | ||
467 | core_bits = get_count_order(c->x86_max_cores); | |
468 | ||
469 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & | |
470 | ((1 << core_bits) - 1); | |
471 | ||
472 | out: | |
473 | if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { | |
474 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
475 | c->phys_proc_id); | |
476 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
477 | c->cpu_core_id); | |
478 | printed = 1; | |
479 | } | |
480 | #endif | |
481 | } | |
482 | ||
483 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) | |
484 | { | |
485 | char *v = c->x86_vendor_id; | |
486 | int i; | |
487 | ||
488 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
489 | if (!cpu_devs[i]) | |
490 | break; | |
491 | ||
492 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
493 | (cpu_devs[i]->c_ident[1] && | |
494 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
495 | ||
496 | this_cpu = cpu_devs[i]; | |
497 | c->x86_vendor = this_cpu->c_x86_vendor; | |
498 | return; | |
499 | } | |
500 | } | |
501 | ||
502 | printk_once(KERN_ERR | |
503 | "CPU: vendor_id '%s' unknown, using generic init.\n" \ | |
504 | "CPU: Your system may be unstable.\n", v); | |
505 | ||
506 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
507 | this_cpu = &default_cpu; | |
508 | } | |
509 | ||
510 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) | |
511 | { | |
512 | /* Get vendor name */ | |
513 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, | |
514 | (unsigned int *)&c->x86_vendor_id[0], | |
515 | (unsigned int *)&c->x86_vendor_id[8], | |
516 | (unsigned int *)&c->x86_vendor_id[4]); | |
517 | ||
518 | c->x86 = 4; | |
519 | /* Intel-defined flags: level 0x00000001 */ | |
520 | if (c->cpuid_level >= 0x00000001) { | |
521 | u32 junk, tfms, cap0, misc; | |
522 | ||
523 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
524 | c->x86 = (tfms >> 8) & 0xf; | |
525 | c->x86_model = (tfms >> 4) & 0xf; | |
526 | c->x86_mask = tfms & 0xf; | |
527 | ||
528 | if (c->x86 == 0xf) | |
529 | c->x86 += (tfms >> 20) & 0xff; | |
530 | if (c->x86 >= 0x6) | |
531 | c->x86_model += ((tfms >> 16) & 0xf) << 4; | |
532 | ||
533 | if (cap0 & (1<<19)) { | |
534 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; | |
535 | c->x86_cache_alignment = c->x86_clflush_size; | |
536 | } | |
537 | } | |
538 | } | |
539 | ||
540 | static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) | |
541 | { | |
542 | u32 tfms, xlvl; | |
543 | u32 ebx; | |
544 | ||
545 | /* Intel-defined flags: level 0x00000001 */ | |
546 | if (c->cpuid_level >= 0x00000001) { | |
547 | u32 capability, excap; | |
548 | ||
549 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
550 | c->x86_capability[0] = capability; | |
551 | c->x86_capability[4] = excap; | |
552 | } | |
553 | ||
554 | /* Additional Intel-defined flags: level 0x00000007 */ | |
555 | if (c->cpuid_level >= 0x00000007) { | |
556 | u32 eax, ebx, ecx, edx; | |
557 | ||
558 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); | |
559 | ||
560 | if (eax > 0) | |
561 | c->x86_capability[9] = ebx; | |
562 | } | |
563 | ||
564 | /* AMD-defined flags: level 0x80000001 */ | |
565 | xlvl = cpuid_eax(0x80000000); | |
566 | c->extended_cpuid_level = xlvl; | |
567 | ||
568 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
569 | if (xlvl >= 0x80000001) { | |
570 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
571 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
572 | } | |
573 | } | |
574 | ||
575 | if (c->extended_cpuid_level >= 0x80000008) { | |
576 | u32 eax = cpuid_eax(0x80000008); | |
577 | ||
578 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
579 | c->x86_phys_bits = eax & 0xff; | |
580 | } | |
581 | #ifdef CONFIG_X86_32 | |
582 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
583 | c->x86_phys_bits = 36; | |
584 | #endif | |
585 | ||
586 | if (c->extended_cpuid_level >= 0x80000007) | |
587 | c->x86_power = cpuid_edx(0x80000007); | |
588 | ||
589 | } | |
590 | ||
591 | static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) | |
592 | { | |
593 | #ifdef CONFIG_X86_32 | |
594 | int i; | |
595 | ||
596 | /* | |
597 | * First of all, decide if this is a 486 or higher | |
598 | * It's a 486 if we can modify the AC flag | |
599 | */ | |
600 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
601 | c->x86 = 4; | |
602 | else | |
603 | c->x86 = 3; | |
604 | ||
605 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
606 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
607 | c->x86_vendor_id[0] = 0; | |
608 | cpu_devs[i]->c_identify(c); | |
609 | if (c->x86_vendor_id[0]) { | |
610 | get_cpu_vendor(c); | |
611 | break; | |
612 | } | |
613 | } | |
614 | #endif | |
615 | } | |
616 | ||
617 | /* | |
618 | * Do minimum CPU detection early. | |
619 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
620 | * cache alignment. | |
621 | * The others are not touched to avoid unwanted side effects. | |
622 | * | |
623 | * WARNING: this function is only called on the BP. Don't add code here | |
624 | * that is supposed to run on all CPUs. | |
625 | */ | |
626 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) | |
627 | { | |
628 | #ifdef CONFIG_X86_64 | |
629 | c->x86_clflush_size = 64; | |
630 | c->x86_phys_bits = 36; | |
631 | c->x86_virt_bits = 48; | |
632 | #else | |
633 | c->x86_clflush_size = 32; | |
634 | c->x86_phys_bits = 32; | |
635 | c->x86_virt_bits = 32; | |
636 | #endif | |
637 | c->x86_cache_alignment = c->x86_clflush_size; | |
638 | ||
639 | memset(&c->x86_capability, 0, sizeof c->x86_capability); | |
640 | c->extended_cpuid_level = 0; | |
641 | ||
642 | if (!have_cpuid_p()) | |
643 | identify_cpu_without_cpuid(c); | |
644 | ||
645 | /* cyrix could have cpuid enabled via c_identify()*/ | |
646 | if (!have_cpuid_p()) | |
647 | return; | |
648 | ||
649 | cpu_detect(c); | |
650 | ||
651 | get_cpu_vendor(c); | |
652 | ||
653 | get_cpu_cap(c); | |
654 | ||
655 | if (this_cpu->c_early_init) | |
656 | this_cpu->c_early_init(c); | |
657 | ||
658 | #ifdef CONFIG_SMP | |
659 | c->cpu_index = boot_cpu_id; | |
660 | #endif | |
661 | filter_cpuid_features(c, false); | |
662 | } | |
663 | ||
664 | void __init early_cpu_init(void) | |
665 | { | |
666 | const struct cpu_dev *const *cdev; | |
667 | int count = 0; | |
668 | ||
669 | #ifdef PROCESSOR_SELECT | |
670 | printk(KERN_INFO "KERNEL supported cpus:\n"); | |
671 | #endif | |
672 | ||
673 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { | |
674 | const struct cpu_dev *cpudev = *cdev; | |
675 | ||
676 | if (count >= X86_VENDOR_NUM) | |
677 | break; | |
678 | cpu_devs[count] = cpudev; | |
679 | count++; | |
680 | ||
681 | #ifdef PROCESSOR_SELECT | |
682 | { | |
683 | unsigned int j; | |
684 | ||
685 | for (j = 0; j < 2; j++) { | |
686 | if (!cpudev->c_ident[j]) | |
687 | continue; | |
688 | printk(KERN_INFO " %s %s\n", cpudev->c_vendor, | |
689 | cpudev->c_ident[j]); | |
690 | } | |
691 | } | |
692 | #endif | |
693 | } | |
694 | early_identify_cpu(&boot_cpu_data); | |
695 | } | |
696 | ||
697 | /* | |
698 | * The NOPL instruction is supposed to exist on all CPUs with | |
699 | * family >= 6; unfortunately, that's not true in practice because | |
700 | * of early VIA chips and (more importantly) broken virtualizers that | |
701 | * are not easy to detect. In the latter case it doesn't even *fail* | |
702 | * reliably, so probing for it doesn't even work. Disable it completely | |
703 | * unless we can find a reliable way to detect all the broken cases. | |
704 | */ | |
705 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
706 | { | |
707 | clear_cpu_cap(c, X86_FEATURE_NOPL); | |
708 | } | |
709 | ||
710 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) | |
711 | { | |
712 | c->extended_cpuid_level = 0; | |
713 | ||
714 | if (!have_cpuid_p()) | |
715 | identify_cpu_without_cpuid(c); | |
716 | ||
717 | /* cyrix could have cpuid enabled via c_identify()*/ | |
718 | if (!have_cpuid_p()) | |
719 | return; | |
720 | ||
721 | cpu_detect(c); | |
722 | ||
723 | get_cpu_vendor(c); | |
724 | ||
725 | get_cpu_cap(c); | |
726 | ||
727 | if (c->cpuid_level >= 0x00000001) { | |
728 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
729 | #ifdef CONFIG_X86_32 | |
730 | # ifdef CONFIG_X86_HT | |
731 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); | |
732 | # else | |
733 | c->apicid = c->initial_apicid; | |
734 | # endif | |
735 | #endif | |
736 | ||
737 | #ifdef CONFIG_X86_HT | |
738 | c->phys_proc_id = c->initial_apicid; | |
739 | #endif | |
740 | } | |
741 | ||
742 | get_model_name(c); /* Default name */ | |
743 | ||
744 | init_scattered_cpuid_features(c); | |
745 | detect_nopl(c); | |
746 | } | |
747 | ||
748 | /* | |
749 | * This does the hard work of actually picking apart the CPU stuff... | |
750 | */ | |
751 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) | |
752 | { | |
753 | int i; | |
754 | ||
755 | c->loops_per_jiffy = loops_per_jiffy; | |
756 | c->x86_cache_size = -1; | |
757 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
758 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ | |
759 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
760 | c->x86_model_id[0] = '\0'; /* Unset */ | |
761 | c->x86_max_cores = 1; | |
762 | c->x86_coreid_bits = 0; | |
763 | #ifdef CONFIG_X86_64 | |
764 | c->x86_clflush_size = 64; | |
765 | c->x86_phys_bits = 36; | |
766 | c->x86_virt_bits = 48; | |
767 | #else | |
768 | c->cpuid_level = -1; /* CPUID not detected */ | |
769 | c->x86_clflush_size = 32; | |
770 | c->x86_phys_bits = 32; | |
771 | c->x86_virt_bits = 32; | |
772 | #endif | |
773 | c->x86_cache_alignment = c->x86_clflush_size; | |
774 | memset(&c->x86_capability, 0, sizeof c->x86_capability); | |
775 | ||
776 | generic_identify(c); | |
777 | ||
778 | if (this_cpu->c_identify) | |
779 | this_cpu->c_identify(c); | |
780 | ||
781 | /* Clear/Set all flags overriden by options, after probe */ | |
782 | for (i = 0; i < NCAPINTS; i++) { | |
783 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
784 | c->x86_capability[i] |= cpu_caps_set[i]; | |
785 | } | |
786 | ||
787 | #ifdef CONFIG_X86_64 | |
788 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); | |
789 | #endif | |
790 | ||
791 | /* | |
792 | * Vendor-specific initialization. In this section we | |
793 | * canonicalize the feature flags, meaning if there are | |
794 | * features a certain CPU supports which CPUID doesn't | |
795 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
796 | * we handle them here. | |
797 | * | |
798 | * At the end of this section, c->x86_capability better | |
799 | * indicate the features this CPU genuinely supports! | |
800 | */ | |
801 | if (this_cpu->c_init) | |
802 | this_cpu->c_init(c); | |
803 | ||
804 | /* Disable the PN if appropriate */ | |
805 | squash_the_stupid_serial_number(c); | |
806 | ||
807 | /* | |
808 | * The vendor-specific functions might have changed features. | |
809 | * Now we do "generic changes." | |
810 | */ | |
811 | ||
812 | /* Filter out anything that depends on CPUID levels we don't have */ | |
813 | filter_cpuid_features(c, true); | |
814 | ||
815 | /* If the model name is still unset, do table lookup. */ | |
816 | if (!c->x86_model_id[0]) { | |
817 | const char *p; | |
818 | p = table_lookup_model(c); | |
819 | if (p) | |
820 | strcpy(c->x86_model_id, p); | |
821 | else | |
822 | /* Last resort... */ | |
823 | sprintf(c->x86_model_id, "%02x/%02x", | |
824 | c->x86, c->x86_model); | |
825 | } | |
826 | ||
827 | #ifdef CONFIG_X86_64 | |
828 | detect_ht(c); | |
829 | #endif | |
830 | ||
831 | init_hypervisor(c); | |
832 | ||
833 | /* | |
834 | * Clear/Set all flags overriden by options, need do it | |
835 | * before following smp all cpus cap AND. | |
836 | */ | |
837 | for (i = 0; i < NCAPINTS; i++) { | |
838 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
839 | c->x86_capability[i] |= cpu_caps_set[i]; | |
840 | } | |
841 | ||
842 | /* | |
843 | * On SMP, boot_cpu_data holds the common feature set between | |
844 | * all CPUs; so make sure that we indicate which features are | |
845 | * common between the CPUs. The first time this routine gets | |
846 | * executed, c == &boot_cpu_data. | |
847 | */ | |
848 | if (c != &boot_cpu_data) { | |
849 | /* AND the already accumulated flags with these */ | |
850 | for (i = 0; i < NCAPINTS; i++) | |
851 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; | |
852 | } | |
853 | ||
854 | /* Init Machine Check Exception if available. */ | |
855 | mcheck_cpu_init(c); | |
856 | ||
857 | select_idle_routine(c); | |
858 | ||
859 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
860 | numa_add_cpu(smp_processor_id()); | |
861 | #endif | |
862 | } | |
863 | ||
864 | #ifdef CONFIG_X86_64 | |
865 | static void vgetcpu_set_mode(void) | |
866 | { | |
867 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | |
868 | vgetcpu_mode = VGETCPU_RDTSCP; | |
869 | else | |
870 | vgetcpu_mode = VGETCPU_LSL; | |
871 | } | |
872 | #endif | |
873 | ||
874 | void __init identify_boot_cpu(void) | |
875 | { | |
876 | identify_cpu(&boot_cpu_data); | |
877 | init_c1e_mask(); | |
878 | #ifdef CONFIG_X86_32 | |
879 | sysenter_setup(); | |
880 | enable_sep_cpu(); | |
881 | #else | |
882 | vgetcpu_set_mode(); | |
883 | #endif | |
884 | init_hw_perf_events(); | |
885 | } | |
886 | ||
887 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) | |
888 | { | |
889 | BUG_ON(c == &boot_cpu_data); | |
890 | identify_cpu(c); | |
891 | #ifdef CONFIG_X86_32 | |
892 | enable_sep_cpu(); | |
893 | #endif | |
894 | mtrr_ap_init(); | |
895 | } | |
896 | ||
897 | struct msr_range { | |
898 | unsigned min; | |
899 | unsigned max; | |
900 | }; | |
901 | ||
902 | static const struct msr_range msr_range_array[] __cpuinitconst = { | |
903 | { 0x00000000, 0x00000418}, | |
904 | { 0xc0000000, 0xc000040b}, | |
905 | { 0xc0010000, 0xc0010142}, | |
906 | { 0xc0011000, 0xc001103b}, | |
907 | }; | |
908 | ||
909 | static void __cpuinit print_cpu_msr(void) | |
910 | { | |
911 | unsigned index_min, index_max; | |
912 | unsigned index; | |
913 | u64 val; | |
914 | int i; | |
915 | ||
916 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
917 | index_min = msr_range_array[i].min; | |
918 | index_max = msr_range_array[i].max; | |
919 | ||
920 | for (index = index_min; index < index_max; index++) { | |
921 | if (rdmsrl_amd_safe(index, &val)) | |
922 | continue; | |
923 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
924 | } | |
925 | } | |
926 | } | |
927 | ||
928 | static int show_msr __cpuinitdata; | |
929 | ||
930 | static __init int setup_show_msr(char *arg) | |
931 | { | |
932 | int num; | |
933 | ||
934 | get_option(&arg, &num); | |
935 | ||
936 | if (num > 0) | |
937 | show_msr = num; | |
938 | return 1; | |
939 | } | |
940 | __setup("show_msr=", setup_show_msr); | |
941 | ||
942 | static __init int setup_noclflush(char *arg) | |
943 | { | |
944 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
945 | return 1; | |
946 | } | |
947 | __setup("noclflush", setup_noclflush); | |
948 | ||
949 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) | |
950 | { | |
951 | const char *vendor = NULL; | |
952 | ||
953 | if (c->x86_vendor < X86_VENDOR_NUM) { | |
954 | vendor = this_cpu->c_vendor; | |
955 | } else { | |
956 | if (c->cpuid_level >= 0) | |
957 | vendor = c->x86_vendor_id; | |
958 | } | |
959 | ||
960 | if (vendor && !strstr(c->x86_model_id, vendor)) | |
961 | printk(KERN_CONT "%s ", vendor); | |
962 | ||
963 | if (c->x86_model_id[0]) | |
964 | printk(KERN_CONT "%s", c->x86_model_id); | |
965 | else | |
966 | printk(KERN_CONT "%d86", c->x86); | |
967 | ||
968 | if (c->x86_mask || c->cpuid_level >= 0) | |
969 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); | |
970 | else | |
971 | printk(KERN_CONT "\n"); | |
972 | ||
973 | #ifdef CONFIG_SMP | |
974 | if (c->cpu_index < show_msr) | |
975 | print_cpu_msr(); | |
976 | #else | |
977 | if (show_msr) | |
978 | print_cpu_msr(); | |
979 | #endif | |
980 | } | |
981 | ||
982 | static __init int setup_disablecpuid(char *arg) | |
983 | { | |
984 | int bit; | |
985 | ||
986 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
987 | setup_clear_cpu_cap(bit); | |
988 | else | |
989 | return 0; | |
990 | ||
991 | return 1; | |
992 | } | |
993 | __setup("clearcpuid=", setup_disablecpuid); | |
994 | ||
995 | #ifdef CONFIG_X86_64 | |
996 | struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; | |
997 | ||
998 | DEFINE_PER_CPU_FIRST(union irq_stack_union, | |
999 | irq_stack_union) __aligned(PAGE_SIZE); | |
1000 | ||
1001 | /* | |
1002 | * The following four percpu variables are hot. Align current_task to | |
1003 | * cacheline size such that all four fall in the same cacheline. | |
1004 | */ | |
1005 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1006 | &init_task; | |
1007 | EXPORT_PER_CPU_SYMBOL(current_task); | |
1008 | ||
1009 | DEFINE_PER_CPU(unsigned long, kernel_stack) = | |
1010 | (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; | |
1011 | EXPORT_PER_CPU_SYMBOL(kernel_stack); | |
1012 | ||
1013 | DEFINE_PER_CPU(char *, irq_stack_ptr) = | |
1014 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; | |
1015 | ||
1016 | DEFINE_PER_CPU(unsigned int, irq_count) = -1; | |
1017 | ||
1018 | /* | |
1019 | * Special IST stacks which the CPU switches to when it calls | |
1020 | * an IST-marked descriptor entry. Up to 7 stacks (hardware | |
1021 | * limit), all of them are 4K, except the debug stack which | |
1022 | * is 8K. | |
1023 | */ | |
1024 | static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { | |
1025 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
1026 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
1027 | }; | |
1028 | ||
1029 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks | |
1030 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); | |
1031 | ||
1032 | /* May not be marked __init: used by software suspend */ | |
1033 | void syscall_init(void) | |
1034 | { | |
1035 | /* | |
1036 | * LSTAR and STAR live in a bit strange symbiosis. | |
1037 | * They both write to the same internal register. STAR allows to | |
1038 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
1039 | */ | |
1040 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
1041 | wrmsrl(MSR_LSTAR, system_call); | |
1042 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
1043 | ||
1044 | #ifdef CONFIG_IA32_EMULATION | |
1045 | syscall32_cpu_init(); | |
1046 | #endif | |
1047 | ||
1048 | /* Flags to clear on syscall */ | |
1049 | wrmsrl(MSR_SYSCALL_MASK, | |
1050 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
1051 | } | |
1052 | ||
1053 | unsigned long kernel_eflags; | |
1054 | ||
1055 | /* | |
1056 | * Copies of the original ist values from the tss are only accessed during | |
1057 | * debugging, no special alignment required. | |
1058 | */ | |
1059 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
1060 | ||
1061 | #else /* CONFIG_X86_64 */ | |
1062 | ||
1063 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; | |
1064 | EXPORT_PER_CPU_SYMBOL(current_task); | |
1065 | ||
1066 | #ifdef CONFIG_CC_STACKPROTECTOR | |
1067 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); | |
1068 | #endif | |
1069 | ||
1070 | /* Make sure %fs and %gs are initialized properly in idle threads */ | |
1071 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) | |
1072 | { | |
1073 | memset(regs, 0, sizeof(struct pt_regs)); | |
1074 | regs->fs = __KERNEL_PERCPU; | |
1075 | regs->gs = __KERNEL_STACK_CANARY; | |
1076 | ||
1077 | return regs; | |
1078 | } | |
1079 | #endif /* CONFIG_X86_64 */ | |
1080 | ||
1081 | /* | |
1082 | * Clear all 6 debug registers: | |
1083 | */ | |
1084 | static void clear_all_debug_regs(void) | |
1085 | { | |
1086 | int i; | |
1087 | ||
1088 | for (i = 0; i < 8; i++) { | |
1089 | /* Ignore db4, db5 */ | |
1090 | if ((i == 4) || (i == 5)) | |
1091 | continue; | |
1092 | ||
1093 | set_debugreg(0, i); | |
1094 | } | |
1095 | } | |
1096 | ||
1097 | #ifdef CONFIG_KGDB | |
1098 | /* | |
1099 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1100 | * connection established. | |
1101 | */ | |
1102 | static void dbg_restore_debug_regs(void) | |
1103 | { | |
1104 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1105 | arch_kgdb_ops.correct_hw_break(); | |
1106 | } | |
1107 | #else /* ! CONFIG_KGDB */ | |
1108 | #define dbg_restore_debug_regs() | |
1109 | #endif /* ! CONFIG_KGDB */ | |
1110 | ||
1111 | /* | |
1112 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1113 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1114 | * and IDT. We reload them nevertheless, this function acts as a | |
1115 | * 'CPU state barrier', nothing should get across. | |
1116 | * A lot of state is already set up in PDA init for 64 bit | |
1117 | */ | |
1118 | #ifdef CONFIG_X86_64 | |
1119 | ||
1120 | void __cpuinit cpu_init(void) | |
1121 | { | |
1122 | struct orig_ist *oist; | |
1123 | struct task_struct *me; | |
1124 | struct tss_struct *t; | |
1125 | unsigned long v; | |
1126 | int cpu; | |
1127 | int i; | |
1128 | ||
1129 | cpu = stack_smp_processor_id(); | |
1130 | t = &per_cpu(init_tss, cpu); | |
1131 | oist = &per_cpu(orig_ist, cpu); | |
1132 | ||
1133 | #ifdef CONFIG_NUMA | |
1134 | if (cpu != 0 && percpu_read(numa_node) == 0 && | |
1135 | early_cpu_to_node(cpu) != NUMA_NO_NODE) | |
1136 | set_numa_node(early_cpu_to_node(cpu)); | |
1137 | #endif | |
1138 | ||
1139 | me = current; | |
1140 | ||
1141 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) | |
1142 | panic("CPU#%d already initialized!\n", cpu); | |
1143 | ||
1144 | pr_debug("Initializing CPU#%d\n", cpu); | |
1145 | ||
1146 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1147 | ||
1148 | /* | |
1149 | * Initialize the per-CPU GDT with the boot GDT, | |
1150 | * and set up the GDT descriptor: | |
1151 | */ | |
1152 | ||
1153 | switch_to_new_gdt(cpu); | |
1154 | loadsegment(fs, 0); | |
1155 | ||
1156 | load_idt((const struct desc_ptr *)&idt_descr); | |
1157 | ||
1158 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1159 | syscall_init(); | |
1160 | ||
1161 | wrmsrl(MSR_FS_BASE, 0); | |
1162 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1163 | barrier(); | |
1164 | ||
1165 | x86_configure_nx(); | |
1166 | if (cpu != 0) | |
1167 | enable_x2apic(); | |
1168 | ||
1169 | /* | |
1170 | * set up and load the per-CPU TSS | |
1171 | */ | |
1172 | if (!oist->ist[0]) { | |
1173 | char *estacks = per_cpu(exception_stacks, cpu); | |
1174 | ||
1175 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { | |
1176 | estacks += exception_stack_sizes[v]; | |
1177 | oist->ist[v] = t->x86_tss.ist[v] = | |
1178 | (unsigned long)estacks; | |
1179 | } | |
1180 | } | |
1181 | ||
1182 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
1183 | ||
1184 | /* | |
1185 | * <= is required because the CPU will access up to | |
1186 | * 8 bits beyond the end of the IO permission bitmap. | |
1187 | */ | |
1188 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1189 | t->io_bitmap[i] = ~0UL; | |
1190 | ||
1191 | atomic_inc(&init_mm.mm_count); | |
1192 | me->active_mm = &init_mm; | |
1193 | BUG_ON(me->mm); | |
1194 | enter_lazy_tlb(&init_mm, me); | |
1195 | ||
1196 | load_sp0(t, ¤t->thread); | |
1197 | set_tss_desc(cpu, t); | |
1198 | load_TR_desc(); | |
1199 | load_LDT(&init_mm.context); | |
1200 | ||
1201 | clear_all_debug_regs(); | |
1202 | dbg_restore_debug_regs(); | |
1203 | ||
1204 | fpu_init(); | |
1205 | ||
1206 | raw_local_save_flags(kernel_eflags); | |
1207 | ||
1208 | if (is_uv_system()) | |
1209 | uv_cpu_init(); | |
1210 | } | |
1211 | ||
1212 | #else | |
1213 | ||
1214 | void __cpuinit cpu_init(void) | |
1215 | { | |
1216 | int cpu = smp_processor_id(); | |
1217 | struct task_struct *curr = current; | |
1218 | struct tss_struct *t = &per_cpu(init_tss, cpu); | |
1219 | struct thread_struct *thread = &curr->thread; | |
1220 | ||
1221 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { | |
1222 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); | |
1223 | for (;;) | |
1224 | local_irq_enable(); | |
1225 | } | |
1226 | ||
1227 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1228 | ||
1229 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1230 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1231 | ||
1232 | load_idt(&idt_descr); | |
1233 | switch_to_new_gdt(cpu); | |
1234 | ||
1235 | /* | |
1236 | * Set up and load the per-CPU TSS and LDT | |
1237 | */ | |
1238 | atomic_inc(&init_mm.mm_count); | |
1239 | curr->active_mm = &init_mm; | |
1240 | BUG_ON(curr->mm); | |
1241 | enter_lazy_tlb(&init_mm, curr); | |
1242 | ||
1243 | load_sp0(t, thread); | |
1244 | set_tss_desc(cpu, t); | |
1245 | load_TR_desc(); | |
1246 | load_LDT(&init_mm.context); | |
1247 | ||
1248 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
1249 | ||
1250 | #ifdef CONFIG_DOUBLEFAULT | |
1251 | /* Set up doublefault TSS pointer in the GDT */ | |
1252 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
1253 | #endif | |
1254 | ||
1255 | clear_all_debug_regs(); | |
1256 | dbg_restore_debug_regs(); | |
1257 | ||
1258 | /* | |
1259 | * Force FPU initialization: | |
1260 | */ | |
1261 | current_thread_info()->status = 0; | |
1262 | clear_used_math(); | |
1263 | mxcsr_feature_mask_init(); | |
1264 | ||
1265 | /* | |
1266 | * Boot processor to setup the FP and extended state context info. | |
1267 | */ | |
1268 | if (smp_processor_id() == boot_cpu_id) | |
1269 | init_thread_xstate(); | |
1270 | ||
1271 | xsave_init(); | |
1272 | } | |
1273 | #endif |