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x86/entry: Move SYSENTER_stack to the beginning of struct tss_struct
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kernel / cpu / common.c
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1#include <linux/bootmem.h>
2#include <linux/linkage.h>
3#include <linux/bitops.h>
4#include <linux/kernel.h>
5#include <linux/export.h>
6#include <linux/percpu.h>
7#include <linux/string.h>
8#include <linux/ctype.h>
9#include <linux/delay.h>
10#include <linux/sched/mm.h>
11#include <linux/sched/clock.h>
12#include <linux/sched/task.h>
13#include <linux/init.h>
14#include <linux/kprobes.h>
15#include <linux/kgdb.h>
16#include <linux/smp.h>
17#include <linux/io.h>
18#include <linux/syscore_ops.h>
19
20#include <asm/stackprotector.h>
21#include <asm/perf_event.h>
22#include <asm/mmu_context.h>
23#include <asm/archrandom.h>
24#include <asm/hypervisor.h>
25#include <asm/processor.h>
26#include <asm/tlbflush.h>
27#include <asm/debugreg.h>
28#include <asm/sections.h>
29#include <asm/vsyscall.h>
30#include <linux/topology.h>
31#include <linux/cpumask.h>
32#include <asm/pgtable.h>
33#include <linux/atomic.h>
34#include <asm/proto.h>
35#include <asm/setup.h>
36#include <asm/apic.h>
37#include <asm/desc.h>
38#include <asm/fpu/internal.h>
39#include <asm/mtrr.h>
40#include <asm/hwcap2.h>
41#include <linux/numa.h>
42#include <asm/asm.h>
43#include <asm/bugs.h>
44#include <asm/cpu.h>
45#include <asm/mce.h>
46#include <asm/msr.h>
47#include <asm/pat.h>
48#include <asm/microcode.h>
49#include <asm/microcode_intel.h>
50
51#ifdef CONFIG_X86_LOCAL_APIC
52#include <asm/uv/uv.h>
53#endif
54
55#include "cpu.h"
56
57u32 elf_hwcap2 __read_mostly;
58
59/* all of these masks are initialized in setup_cpu_local_masks() */
60cpumask_var_t cpu_initialized_mask;
61cpumask_var_t cpu_callout_mask;
62cpumask_var_t cpu_callin_mask;
63
64/* representing cpus for which sibling maps can be computed */
65cpumask_var_t cpu_sibling_setup_mask;
66
67/* correctly size the local cpu masks */
68void __init setup_cpu_local_masks(void)
69{
70 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
71 alloc_bootmem_cpumask_var(&cpu_callin_mask);
72 alloc_bootmem_cpumask_var(&cpu_callout_mask);
73 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
74}
75
76static void default_init(struct cpuinfo_x86 *c)
77{
78#ifdef CONFIG_X86_64
79 cpu_detect_cache_sizes(c);
80#else
81 /* Not much we can do here... */
82 /* Check if at least it has cpuid */
83 if (c->cpuid_level == -1) {
84 /* No cpuid. It must be an ancient CPU */
85 if (c->x86 == 4)
86 strcpy(c->x86_model_id, "486");
87 else if (c->x86 == 3)
88 strcpy(c->x86_model_id, "386");
89 }
90#endif
91}
92
93static const struct cpu_dev default_cpu = {
94 .c_init = default_init,
95 .c_vendor = "Unknown",
96 .c_x86_vendor = X86_VENDOR_UNKNOWN,
97};
98
99static const struct cpu_dev *this_cpu = &default_cpu;
100
101DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
102#ifdef CONFIG_X86_64
103 /*
104 * We need valid kernel segments for data and code in long mode too
105 * IRET will check the segment types kkeil 2000/10/28
106 * Also sysret mandates a special GDT layout
107 *
108 * TLS descriptors are currently at a different place compared to i386.
109 * Hopefully nobody expects them at a fixed place (Wine?)
110 */
111 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
112 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
113 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
114 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
115 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
116 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
117#else
118 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
119 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
120 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
121 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
122 /*
123 * Segments used for calling PnP BIOS have byte granularity.
124 * They code segments and data segments have fixed 64k limits,
125 * the transfer segment sizes are set at run time.
126 */
127 /* 32-bit code */
128 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
129 /* 16-bit code */
130 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
131 /* 16-bit data */
132 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
133 /* 16-bit data */
134 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
135 /* 16-bit data */
136 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
137 /*
138 * The APM segments have byte granularity and their bases
139 * are set at run time. All have 64k limits.
140 */
141 /* 32-bit code */
142 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
143 /* 16-bit code */
144 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
145 /* data */
146 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
147
148 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
149 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
150 GDT_STACK_CANARY_INIT
151#endif
152} };
153EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
154
155static int __init x86_mpx_setup(char *s)
156{
157 /* require an exact match without trailing characters */
158 if (strlen(s))
159 return 0;
160
161 /* do not emit a message if the feature is not present */
162 if (!boot_cpu_has(X86_FEATURE_MPX))
163 return 1;
164
165 setup_clear_cpu_cap(X86_FEATURE_MPX);
166 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
167 return 1;
168}
169__setup("nompx", x86_mpx_setup);
170
171#ifdef CONFIG_X86_64
172static int __init x86_nopcid_setup(char *s)
173{
174 /* nopcid doesn't accept parameters */
175 if (s)
176 return -EINVAL;
177
178 /* do not emit a message if the feature is not present */
179 if (!boot_cpu_has(X86_FEATURE_PCID))
180 return 0;
181
182 setup_clear_cpu_cap(X86_FEATURE_PCID);
183 pr_info("nopcid: PCID feature disabled\n");
184 return 0;
185}
186early_param("nopcid", x86_nopcid_setup);
187#endif
188
189static int __init x86_noinvpcid_setup(char *s)
190{
191 /* noinvpcid doesn't accept parameters */
192 if (s)
193 return -EINVAL;
194
195 /* do not emit a message if the feature is not present */
196 if (!boot_cpu_has(X86_FEATURE_INVPCID))
197 return 0;
198
199 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
200 pr_info("noinvpcid: INVPCID feature disabled\n");
201 return 0;
202}
203early_param("noinvpcid", x86_noinvpcid_setup);
204
205#ifdef CONFIG_X86_32
206static int cachesize_override = -1;
207static int disable_x86_serial_nr = 1;
208
209static int __init cachesize_setup(char *str)
210{
211 get_option(&str, &cachesize_override);
212 return 1;
213}
214__setup("cachesize=", cachesize_setup);
215
216static int __init x86_sep_setup(char *s)
217{
218 setup_clear_cpu_cap(X86_FEATURE_SEP);
219 return 1;
220}
221__setup("nosep", x86_sep_setup);
222
223/* Standard macro to see if a specific flag is changeable */
224static inline int flag_is_changeable_p(u32 flag)
225{
226 u32 f1, f2;
227
228 /*
229 * Cyrix and IDT cpus allow disabling of CPUID
230 * so the code below may return different results
231 * when it is executed before and after enabling
232 * the CPUID. Add "volatile" to not allow gcc to
233 * optimize the subsequent calls to this function.
234 */
235 asm volatile ("pushfl \n\t"
236 "pushfl \n\t"
237 "popl %0 \n\t"
238 "movl %0, %1 \n\t"
239 "xorl %2, %0 \n\t"
240 "pushl %0 \n\t"
241 "popfl \n\t"
242 "pushfl \n\t"
243 "popl %0 \n\t"
244 "popfl \n\t"
245
246 : "=&r" (f1), "=&r" (f2)
247 : "ir" (flag));
248
249 return ((f1^f2) & flag) != 0;
250}
251
252/* Probe for the CPUID instruction */
253int have_cpuid_p(void)
254{
255 return flag_is_changeable_p(X86_EFLAGS_ID);
256}
257
258static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
259{
260 unsigned long lo, hi;
261
262 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
263 return;
264
265 /* Disable processor serial number: */
266
267 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
268 lo |= 0x200000;
269 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
270
271 pr_notice("CPU serial number disabled.\n");
272 clear_cpu_cap(c, X86_FEATURE_PN);
273
274 /* Disabling the serial number may affect the cpuid level */
275 c->cpuid_level = cpuid_eax(0);
276}
277
278static int __init x86_serial_nr_setup(char *s)
279{
280 disable_x86_serial_nr = 0;
281 return 1;
282}
283__setup("serialnumber", x86_serial_nr_setup);
284#else
285static inline int flag_is_changeable_p(u32 flag)
286{
287 return 1;
288}
289static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
290{
291}
292#endif
293
294static __init int setup_disable_smep(char *arg)
295{
296 setup_clear_cpu_cap(X86_FEATURE_SMEP);
297 /* Check for things that depend on SMEP being enabled: */
298 check_mpx_erratum(&boot_cpu_data);
299 return 1;
300}
301__setup("nosmep", setup_disable_smep);
302
303static __always_inline void setup_smep(struct cpuinfo_x86 *c)
304{
305 if (cpu_has(c, X86_FEATURE_SMEP))
306 cr4_set_bits(X86_CR4_SMEP);
307}
308
309static __init int setup_disable_smap(char *arg)
310{
311 setup_clear_cpu_cap(X86_FEATURE_SMAP);
312 return 1;
313}
314__setup("nosmap", setup_disable_smap);
315
316static __always_inline void setup_smap(struct cpuinfo_x86 *c)
317{
318 unsigned long eflags = native_save_fl();
319
320 /* This should have been cleared long ago */
321 BUG_ON(eflags & X86_EFLAGS_AC);
322
323 if (cpu_has(c, X86_FEATURE_SMAP)) {
324#ifdef CONFIG_X86_SMAP
325 cr4_set_bits(X86_CR4_SMAP);
326#else
327 cr4_clear_bits(X86_CR4_SMAP);
328#endif
329 }
330}
331
332/*
333 * Protection Keys are not available in 32-bit mode.
334 */
335static bool pku_disabled;
336
337static __always_inline void setup_pku(struct cpuinfo_x86 *c)
338{
339 /* check the boot processor, plus compile options for PKU: */
340 if (!cpu_feature_enabled(X86_FEATURE_PKU))
341 return;
342 /* checks the actual processor's cpuid bits: */
343 if (!cpu_has(c, X86_FEATURE_PKU))
344 return;
345 if (pku_disabled)
346 return;
347
348 cr4_set_bits(X86_CR4_PKE);
349 /*
350 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
351 * cpuid bit to be set. We need to ensure that we
352 * update that bit in this CPU's "cpu_info".
353 */
354 get_cpu_cap(c);
355}
356
357#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
358static __init int setup_disable_pku(char *arg)
359{
360 /*
361 * Do not clear the X86_FEATURE_PKU bit. All of the
362 * runtime checks are against OSPKE so clearing the
363 * bit does nothing.
364 *
365 * This way, we will see "pku" in cpuinfo, but not
366 * "ospke", which is exactly what we want. It shows
367 * that the CPU has PKU, but the OS has not enabled it.
368 * This happens to be exactly how a system would look
369 * if we disabled the config option.
370 */
371 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
372 pku_disabled = true;
373 return 1;
374}
375__setup("nopku", setup_disable_pku);
376#endif /* CONFIG_X86_64 */
377
378/*
379 * Some CPU features depend on higher CPUID levels, which may not always
380 * be available due to CPUID level capping or broken virtualization
381 * software. Add those features to this table to auto-disable them.
382 */
383struct cpuid_dependent_feature {
384 u32 feature;
385 u32 level;
386};
387
388static const struct cpuid_dependent_feature
389cpuid_dependent_features[] = {
390 { X86_FEATURE_MWAIT, 0x00000005 },
391 { X86_FEATURE_DCA, 0x00000009 },
392 { X86_FEATURE_XSAVE, 0x0000000d },
393 { 0, 0 }
394};
395
396static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
397{
398 const struct cpuid_dependent_feature *df;
399
400 for (df = cpuid_dependent_features; df->feature; df++) {
401
402 if (!cpu_has(c, df->feature))
403 continue;
404 /*
405 * Note: cpuid_level is set to -1 if unavailable, but
406 * extended_extended_level is set to 0 if unavailable
407 * and the legitimate extended levels are all negative
408 * when signed; hence the weird messing around with
409 * signs here...
410 */
411 if (!((s32)df->level < 0 ?
412 (u32)df->level > (u32)c->extended_cpuid_level :
413 (s32)df->level > (s32)c->cpuid_level))
414 continue;
415
416 clear_cpu_cap(c, df->feature);
417 if (!warn)
418 continue;
419
420 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
421 x86_cap_flag(df->feature), df->level);
422 }
423}
424
425/*
426 * Naming convention should be: <Name> [(<Codename>)]
427 * This table only is used unless init_<vendor>() below doesn't set it;
428 * in particular, if CPUID levels 0x80000002..4 are supported, this
429 * isn't used
430 */
431
432/* Look up CPU names by table lookup. */
433static const char *table_lookup_model(struct cpuinfo_x86 *c)
434{
435#ifdef CONFIG_X86_32
436 const struct legacy_cpu_model_info *info;
437
438 if (c->x86_model >= 16)
439 return NULL; /* Range check */
440
441 if (!this_cpu)
442 return NULL;
443
444 info = this_cpu->legacy_models;
445
446 while (info->family) {
447 if (info->family == c->x86)
448 return info->model_names[c->x86_model];
449 info++;
450 }
451#endif
452 return NULL; /* Not found */
453}
454
455__u32 cpu_caps_cleared[NCAPINTS];
456__u32 cpu_caps_set[NCAPINTS];
457
458void load_percpu_segment(int cpu)
459{
460#ifdef CONFIG_X86_32
461 loadsegment(fs, __KERNEL_PERCPU);
462#else
463 __loadsegment_simple(gs, 0);
464 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
465#endif
466 load_stack_canary_segment();
467}
468
469/* Setup the fixmap mappings only once per-processor */
470static inline void setup_cpu_entry_area(int cpu)
471{
472#ifdef CONFIG_X86_64
473 /* On 64-bit systems, we use a read-only fixmap GDT. */
474 pgprot_t gdt_prot = PAGE_KERNEL_RO;
475#else
476 /*
477 * On native 32-bit systems, the GDT cannot be read-only because
478 * our double fault handler uses a task gate, and entering through
479 * a task gate needs to change an available TSS to busy. If the GDT
480 * is read-only, that will triple fault.
481 *
482 * On Xen PV, the GDT must be read-only because the hypervisor requires
483 * it.
484 */
485 pgprot_t gdt_prot = boot_cpu_has(X86_FEATURE_XENPV) ?
486 PAGE_KERNEL_RO : PAGE_KERNEL;
487#endif
488
489 __set_fixmap(get_cpu_entry_area_index(cpu, gdt), get_cpu_gdt_paddr(cpu), gdt_prot);
490
491 /*
492 * The Intel SDM says (Volume 3, 7.2.1):
493 *
494 * Avoid placing a page boundary in the part of the TSS that the
495 * processor reads during a task switch (the first 104 bytes). The
496 * processor may not correctly perform address translations if a
497 * boundary occurs in this area. During a task switch, the processor
498 * reads and writes into the first 104 bytes of each TSS (using
499 * contiguous physical addresses beginning with the physical address
500 * of the first byte of the TSS). So, after TSS access begins, if
501 * part of the 104 bytes is not physically contiguous, the processor
502 * will access incorrect information without generating a page-fault
503 * exception.
504 *
505 * There are also a lot of errata involving the TSS spanning a page
506 * boundary. Assert that we're not doing that.
507 */
508 BUILD_BUG_ON((offsetof(struct tss_struct, x86_tss) ^
509 offsetofend(struct tss_struct, x86_tss)) & PAGE_MASK);
510
511}
512
513/* Load the original GDT from the per-cpu structure */
514void load_direct_gdt(int cpu)
515{
516 struct desc_ptr gdt_descr;
517
518 gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
519 gdt_descr.size = GDT_SIZE - 1;
520 load_gdt(&gdt_descr);
521}
522EXPORT_SYMBOL_GPL(load_direct_gdt);
523
524/* Load a fixmap remapping of the per-cpu GDT */
525void load_fixmap_gdt(int cpu)
526{
527 struct desc_ptr gdt_descr;
528
529 gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
530 gdt_descr.size = GDT_SIZE - 1;
531 load_gdt(&gdt_descr);
532}
533EXPORT_SYMBOL_GPL(load_fixmap_gdt);
534
535/*
536 * Current gdt points %fs at the "master" per-cpu area: after this,
537 * it's on the real one.
538 */
539void switch_to_new_gdt(int cpu)
540{
541 /* Load the original GDT */
542 load_direct_gdt(cpu);
543 /* Reload the per-cpu base */
544 load_percpu_segment(cpu);
545}
546
547static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
548
549static void get_model_name(struct cpuinfo_x86 *c)
550{
551 unsigned int *v;
552 char *p, *q, *s;
553
554 if (c->extended_cpuid_level < 0x80000004)
555 return;
556
557 v = (unsigned int *)c->x86_model_id;
558 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
559 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
560 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
561 c->x86_model_id[48] = 0;
562
563 /* Trim whitespace */
564 p = q = s = &c->x86_model_id[0];
565
566 while (*p == ' ')
567 p++;
568
569 while (*p) {
570 /* Note the last non-whitespace index */
571 if (!isspace(*p))
572 s = q;
573
574 *q++ = *p++;
575 }
576
577 *(s + 1) = '\0';
578}
579
580void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
581{
582 unsigned int n, dummy, ebx, ecx, edx, l2size;
583
584 n = c->extended_cpuid_level;
585
586 if (n >= 0x80000005) {
587 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
588 c->x86_cache_size = (ecx>>24) + (edx>>24);
589#ifdef CONFIG_X86_64
590 /* On K8 L1 TLB is inclusive, so don't count it */
591 c->x86_tlbsize = 0;
592#endif
593 }
594
595 if (n < 0x80000006) /* Some chips just has a large L1. */
596 return;
597
598 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
599 l2size = ecx >> 16;
600
601#ifdef CONFIG_X86_64
602 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
603#else
604 /* do processor-specific cache resizing */
605 if (this_cpu->legacy_cache_size)
606 l2size = this_cpu->legacy_cache_size(c, l2size);
607
608 /* Allow user to override all this if necessary. */
609 if (cachesize_override != -1)
610 l2size = cachesize_override;
611
612 if (l2size == 0)
613 return; /* Again, no L2 cache is possible */
614#endif
615
616 c->x86_cache_size = l2size;
617}
618
619u16 __read_mostly tlb_lli_4k[NR_INFO];
620u16 __read_mostly tlb_lli_2m[NR_INFO];
621u16 __read_mostly tlb_lli_4m[NR_INFO];
622u16 __read_mostly tlb_lld_4k[NR_INFO];
623u16 __read_mostly tlb_lld_2m[NR_INFO];
624u16 __read_mostly tlb_lld_4m[NR_INFO];
625u16 __read_mostly tlb_lld_1g[NR_INFO];
626
627static void cpu_detect_tlb(struct cpuinfo_x86 *c)
628{
629 if (this_cpu->c_detect_tlb)
630 this_cpu->c_detect_tlb(c);
631
632 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
633 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
634 tlb_lli_4m[ENTRIES]);
635
636 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
637 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
638 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
639}
640
641void detect_ht(struct cpuinfo_x86 *c)
642{
643#ifdef CONFIG_SMP
644 u32 eax, ebx, ecx, edx;
645 int index_msb, core_bits;
646 static bool printed;
647
648 if (!cpu_has(c, X86_FEATURE_HT))
649 return;
650
651 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
652 goto out;
653
654 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
655 return;
656
657 cpuid(1, &eax, &ebx, &ecx, &edx);
658
659 smp_num_siblings = (ebx & 0xff0000) >> 16;
660
661 if (smp_num_siblings == 1) {
662 pr_info_once("CPU0: Hyper-Threading is disabled\n");
663 goto out;
664 }
665
666 if (smp_num_siblings <= 1)
667 goto out;
668
669 index_msb = get_count_order(smp_num_siblings);
670 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
671
672 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
673
674 index_msb = get_count_order(smp_num_siblings);
675
676 core_bits = get_count_order(c->x86_max_cores);
677
678 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
679 ((1 << core_bits) - 1);
680
681out:
682 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
683 pr_info("CPU: Physical Processor ID: %d\n",
684 c->phys_proc_id);
685 pr_info("CPU: Processor Core ID: %d\n",
686 c->cpu_core_id);
687 printed = 1;
688 }
689#endif
690}
691
692static void get_cpu_vendor(struct cpuinfo_x86 *c)
693{
694 char *v = c->x86_vendor_id;
695 int i;
696
697 for (i = 0; i < X86_VENDOR_NUM; i++) {
698 if (!cpu_devs[i])
699 break;
700
701 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
702 (cpu_devs[i]->c_ident[1] &&
703 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
704
705 this_cpu = cpu_devs[i];
706 c->x86_vendor = this_cpu->c_x86_vendor;
707 return;
708 }
709 }
710
711 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
712 "CPU: Your system may be unstable.\n", v);
713
714 c->x86_vendor = X86_VENDOR_UNKNOWN;
715 this_cpu = &default_cpu;
716}
717
718void cpu_detect(struct cpuinfo_x86 *c)
719{
720 /* Get vendor name */
721 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
722 (unsigned int *)&c->x86_vendor_id[0],
723 (unsigned int *)&c->x86_vendor_id[8],
724 (unsigned int *)&c->x86_vendor_id[4]);
725
726 c->x86 = 4;
727 /* Intel-defined flags: level 0x00000001 */
728 if (c->cpuid_level >= 0x00000001) {
729 u32 junk, tfms, cap0, misc;
730
731 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
732 c->x86 = x86_family(tfms);
733 c->x86_model = x86_model(tfms);
734 c->x86_mask = x86_stepping(tfms);
735
736 if (cap0 & (1<<19)) {
737 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
738 c->x86_cache_alignment = c->x86_clflush_size;
739 }
740 }
741}
742
743static void apply_forced_caps(struct cpuinfo_x86 *c)
744{
745 int i;
746
747 for (i = 0; i < NCAPINTS; i++) {
748 c->x86_capability[i] &= ~cpu_caps_cleared[i];
749 c->x86_capability[i] |= cpu_caps_set[i];
750 }
751}
752
753void get_cpu_cap(struct cpuinfo_x86 *c)
754{
755 u32 eax, ebx, ecx, edx;
756
757 /* Intel-defined flags: level 0x00000001 */
758 if (c->cpuid_level >= 0x00000001) {
759 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
760
761 c->x86_capability[CPUID_1_ECX] = ecx;
762 c->x86_capability[CPUID_1_EDX] = edx;
763 }
764
765 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
766 if (c->cpuid_level >= 0x00000006)
767 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
768
769 /* Additional Intel-defined flags: level 0x00000007 */
770 if (c->cpuid_level >= 0x00000007) {
771 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
772 c->x86_capability[CPUID_7_0_EBX] = ebx;
773 c->x86_capability[CPUID_7_ECX] = ecx;
774 }
775
776 /* Extended state features: level 0x0000000d */
777 if (c->cpuid_level >= 0x0000000d) {
778 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
779
780 c->x86_capability[CPUID_D_1_EAX] = eax;
781 }
782
783 /* Additional Intel-defined flags: level 0x0000000F */
784 if (c->cpuid_level >= 0x0000000F) {
785
786 /* QoS sub-leaf, EAX=0Fh, ECX=0 */
787 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx);
788 c->x86_capability[CPUID_F_0_EDX] = edx;
789
790 if (cpu_has(c, X86_FEATURE_CQM_LLC)) {
791 /* will be overridden if occupancy monitoring exists */
792 c->x86_cache_max_rmid = ebx;
793
794 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
795 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx);
796 c->x86_capability[CPUID_F_1_EDX] = edx;
797
798 if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) ||
799 ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) ||
800 (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) {
801 c->x86_cache_max_rmid = ecx;
802 c->x86_cache_occ_scale = ebx;
803 }
804 } else {
805 c->x86_cache_max_rmid = -1;
806 c->x86_cache_occ_scale = -1;
807 }
808 }
809
810 /* AMD-defined flags: level 0x80000001 */
811 eax = cpuid_eax(0x80000000);
812 c->extended_cpuid_level = eax;
813
814 if ((eax & 0xffff0000) == 0x80000000) {
815 if (eax >= 0x80000001) {
816 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
817
818 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
819 c->x86_capability[CPUID_8000_0001_EDX] = edx;
820 }
821 }
822
823 if (c->extended_cpuid_level >= 0x80000007) {
824 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
825
826 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
827 c->x86_power = edx;
828 }
829
830 if (c->extended_cpuid_level >= 0x80000008) {
831 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
832
833 c->x86_virt_bits = (eax >> 8) & 0xff;
834 c->x86_phys_bits = eax & 0xff;
835 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
836 }
837#ifdef CONFIG_X86_32
838 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
839 c->x86_phys_bits = 36;
840#endif
841
842 if (c->extended_cpuid_level >= 0x8000000a)
843 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
844
845 init_scattered_cpuid_features(c);
846
847 /*
848 * Clear/Set all flags overridden by options, after probe.
849 * This needs to happen each time we re-probe, which may happen
850 * several times during CPU initialization.
851 */
852 apply_forced_caps(c);
853}
854
855static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
856{
857#ifdef CONFIG_X86_32
858 int i;
859
860 /*
861 * First of all, decide if this is a 486 or higher
862 * It's a 486 if we can modify the AC flag
863 */
864 if (flag_is_changeable_p(X86_EFLAGS_AC))
865 c->x86 = 4;
866 else
867 c->x86 = 3;
868
869 for (i = 0; i < X86_VENDOR_NUM; i++)
870 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
871 c->x86_vendor_id[0] = 0;
872 cpu_devs[i]->c_identify(c);
873 if (c->x86_vendor_id[0]) {
874 get_cpu_vendor(c);
875 break;
876 }
877 }
878#endif
879}
880
881/*
882 * Do minimum CPU detection early.
883 * Fields really needed: vendor, cpuid_level, family, model, mask,
884 * cache alignment.
885 * The others are not touched to avoid unwanted side effects.
886 *
887 * WARNING: this function is only called on the BP. Don't add code here
888 * that is supposed to run on all CPUs.
889 */
890static void __init early_identify_cpu(struct cpuinfo_x86 *c)
891{
892#ifdef CONFIG_X86_64
893 c->x86_clflush_size = 64;
894 c->x86_phys_bits = 36;
895 c->x86_virt_bits = 48;
896#else
897 c->x86_clflush_size = 32;
898 c->x86_phys_bits = 32;
899 c->x86_virt_bits = 32;
900#endif
901 c->x86_cache_alignment = c->x86_clflush_size;
902
903 memset(&c->x86_capability, 0, sizeof c->x86_capability);
904 c->extended_cpuid_level = 0;
905
906 /* cyrix could have cpuid enabled via c_identify()*/
907 if (have_cpuid_p()) {
908 cpu_detect(c);
909 get_cpu_vendor(c);
910 get_cpu_cap(c);
911 setup_force_cpu_cap(X86_FEATURE_CPUID);
912
913 if (this_cpu->c_early_init)
914 this_cpu->c_early_init(c);
915
916 c->cpu_index = 0;
917 filter_cpuid_features(c, false);
918
919 if (this_cpu->c_bsp_init)
920 this_cpu->c_bsp_init(c);
921 } else {
922 identify_cpu_without_cpuid(c);
923 setup_clear_cpu_cap(X86_FEATURE_CPUID);
924 }
925
926 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
927 fpu__init_system(c);
928}
929
930void __init early_cpu_init(void)
931{
932 const struct cpu_dev *const *cdev;
933 int count = 0;
934
935#ifdef CONFIG_PROCESSOR_SELECT
936 pr_info("KERNEL supported cpus:\n");
937#endif
938
939 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
940 const struct cpu_dev *cpudev = *cdev;
941
942 if (count >= X86_VENDOR_NUM)
943 break;
944 cpu_devs[count] = cpudev;
945 count++;
946
947#ifdef CONFIG_PROCESSOR_SELECT
948 {
949 unsigned int j;
950
951 for (j = 0; j < 2; j++) {
952 if (!cpudev->c_ident[j])
953 continue;
954 pr_info(" %s %s\n", cpudev->c_vendor,
955 cpudev->c_ident[j]);
956 }
957 }
958#endif
959 }
960 early_identify_cpu(&boot_cpu_data);
961}
962
963/*
964 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
965 * unfortunately, that's not true in practice because of early VIA
966 * chips and (more importantly) broken virtualizers that are not easy
967 * to detect. In the latter case it doesn't even *fail* reliably, so
968 * probing for it doesn't even work. Disable it completely on 32-bit
969 * unless we can find a reliable way to detect all the broken cases.
970 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
971 */
972static void detect_nopl(struct cpuinfo_x86 *c)
973{
974#ifdef CONFIG_X86_32
975 clear_cpu_cap(c, X86_FEATURE_NOPL);
976#else
977 set_cpu_cap(c, X86_FEATURE_NOPL);
978#endif
979}
980
981static void detect_null_seg_behavior(struct cpuinfo_x86 *c)
982{
983#ifdef CONFIG_X86_64
984 /*
985 * Empirically, writing zero to a segment selector on AMD does
986 * not clear the base, whereas writing zero to a segment
987 * selector on Intel does clear the base. Intel's behavior
988 * allows slightly faster context switches in the common case
989 * where GS is unused by the prev and next threads.
990 *
991 * Since neither vendor documents this anywhere that I can see,
992 * detect it directly instead of hardcoding the choice by
993 * vendor.
994 *
995 * I've designated AMD's behavior as the "bug" because it's
996 * counterintuitive and less friendly.
997 */
998
999 unsigned long old_base, tmp;
1000 rdmsrl(MSR_FS_BASE, old_base);
1001 wrmsrl(MSR_FS_BASE, 1);
1002 loadsegment(fs, 0);
1003 rdmsrl(MSR_FS_BASE, tmp);
1004 if (tmp != 0)
1005 set_cpu_bug(c, X86_BUG_NULL_SEG);
1006 wrmsrl(MSR_FS_BASE, old_base);
1007#endif
1008}
1009
1010static void generic_identify(struct cpuinfo_x86 *c)
1011{
1012 c->extended_cpuid_level = 0;
1013
1014 if (!have_cpuid_p())
1015 identify_cpu_without_cpuid(c);
1016
1017 /* cyrix could have cpuid enabled via c_identify()*/
1018 if (!have_cpuid_p())
1019 return;
1020
1021 cpu_detect(c);
1022
1023 get_cpu_vendor(c);
1024
1025 get_cpu_cap(c);
1026
1027 if (c->cpuid_level >= 0x00000001) {
1028 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
1029#ifdef CONFIG_X86_32
1030# ifdef CONFIG_SMP
1031 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1032# else
1033 c->apicid = c->initial_apicid;
1034# endif
1035#endif
1036 c->phys_proc_id = c->initial_apicid;
1037 }
1038
1039 get_model_name(c); /* Default name */
1040
1041 detect_nopl(c);
1042
1043 detect_null_seg_behavior(c);
1044
1045 /*
1046 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1047 * systems that run Linux at CPL > 0 may or may not have the
1048 * issue, but, even if they have the issue, there's absolutely
1049 * nothing we can do about it because we can't use the real IRET
1050 * instruction.
1051 *
1052 * NB: For the time being, only 32-bit kernels support
1053 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1054 * whether to apply espfix using paravirt hooks. If any
1055 * non-paravirt system ever shows up that does *not* have the
1056 * ESPFIX issue, we can change this.
1057 */
1058#ifdef CONFIG_X86_32
1059# ifdef CONFIG_PARAVIRT
1060 do {
1061 extern void native_iret(void);
1062 if (pv_cpu_ops.iret == native_iret)
1063 set_cpu_bug(c, X86_BUG_ESPFIX);
1064 } while (0);
1065# else
1066 set_cpu_bug(c, X86_BUG_ESPFIX);
1067# endif
1068#endif
1069}
1070
1071static void x86_init_cache_qos(struct cpuinfo_x86 *c)
1072{
1073 /*
1074 * The heavy lifting of max_rmid and cache_occ_scale are handled
1075 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
1076 * in case CQM bits really aren't there in this CPU.
1077 */
1078 if (c != &boot_cpu_data) {
1079 boot_cpu_data.x86_cache_max_rmid =
1080 min(boot_cpu_data.x86_cache_max_rmid,
1081 c->x86_cache_max_rmid);
1082 }
1083}
1084
1085/*
1086 * Validate that ACPI/mptables have the same information about the
1087 * effective APIC id and update the package map.
1088 */
1089static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
1090{
1091#ifdef CONFIG_SMP
1092 unsigned int apicid, cpu = smp_processor_id();
1093
1094 apicid = apic->cpu_present_to_apicid(cpu);
1095
1096 if (apicid != c->apicid) {
1097 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1098 cpu, apicid, c->initial_apicid);
1099 }
1100 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
1101#else
1102 c->logical_proc_id = 0;
1103#endif
1104}
1105
1106/*
1107 * This does the hard work of actually picking apart the CPU stuff...
1108 */
1109static void identify_cpu(struct cpuinfo_x86 *c)
1110{
1111 int i;
1112
1113 c->loops_per_jiffy = loops_per_jiffy;
1114 c->x86_cache_size = -1;
1115 c->x86_vendor = X86_VENDOR_UNKNOWN;
1116 c->x86_model = c->x86_mask = 0; /* So far unknown... */
1117 c->x86_vendor_id[0] = '\0'; /* Unset */
1118 c->x86_model_id[0] = '\0'; /* Unset */
1119 c->x86_max_cores = 1;
1120 c->x86_coreid_bits = 0;
1121 c->cu_id = 0xff;
1122#ifdef CONFIG_X86_64
1123 c->x86_clflush_size = 64;
1124 c->x86_phys_bits = 36;
1125 c->x86_virt_bits = 48;
1126#else
1127 c->cpuid_level = -1; /* CPUID not detected */
1128 c->x86_clflush_size = 32;
1129 c->x86_phys_bits = 32;
1130 c->x86_virt_bits = 32;
1131#endif
1132 c->x86_cache_alignment = c->x86_clflush_size;
1133 memset(&c->x86_capability, 0, sizeof c->x86_capability);
1134
1135 generic_identify(c);
1136
1137 if (this_cpu->c_identify)
1138 this_cpu->c_identify(c);
1139
1140 /* Clear/Set all flags overridden by options, after probe */
1141 apply_forced_caps(c);
1142
1143#ifdef CONFIG_X86_64
1144 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1145#endif
1146
1147 /*
1148 * Vendor-specific initialization. In this section we
1149 * canonicalize the feature flags, meaning if there are
1150 * features a certain CPU supports which CPUID doesn't
1151 * tell us, CPUID claiming incorrect flags, or other bugs,
1152 * we handle them here.
1153 *
1154 * At the end of this section, c->x86_capability better
1155 * indicate the features this CPU genuinely supports!
1156 */
1157 if (this_cpu->c_init)
1158 this_cpu->c_init(c);
1159
1160 /* Disable the PN if appropriate */
1161 squash_the_stupid_serial_number(c);
1162
1163 /* Set up SMEP/SMAP */
1164 setup_smep(c);
1165 setup_smap(c);
1166
1167 /*
1168 * The vendor-specific functions might have changed features.
1169 * Now we do "generic changes."
1170 */
1171
1172 /* Filter out anything that depends on CPUID levels we don't have */
1173 filter_cpuid_features(c, true);
1174
1175 /* If the model name is still unset, do table lookup. */
1176 if (!c->x86_model_id[0]) {
1177 const char *p;
1178 p = table_lookup_model(c);
1179 if (p)
1180 strcpy(c->x86_model_id, p);
1181 else
1182 /* Last resort... */
1183 sprintf(c->x86_model_id, "%02x/%02x",
1184 c->x86, c->x86_model);
1185 }
1186
1187#ifdef CONFIG_X86_64
1188 detect_ht(c);
1189#endif
1190
1191 x86_init_rdrand(c);
1192 x86_init_cache_qos(c);
1193 setup_pku(c);
1194
1195 /*
1196 * Clear/Set all flags overridden by options, need do it
1197 * before following smp all cpus cap AND.
1198 */
1199 apply_forced_caps(c);
1200
1201 /*
1202 * On SMP, boot_cpu_data holds the common feature set between
1203 * all CPUs; so make sure that we indicate which features are
1204 * common between the CPUs. The first time this routine gets
1205 * executed, c == &boot_cpu_data.
1206 */
1207 if (c != &boot_cpu_data) {
1208 /* AND the already accumulated flags with these */
1209 for (i = 0; i < NCAPINTS; i++)
1210 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1211
1212 /* OR, i.e. replicate the bug flags */
1213 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1214 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1215 }
1216
1217 /* Init Machine Check Exception if available. */
1218 mcheck_cpu_init(c);
1219
1220 select_idle_routine(c);
1221
1222#ifdef CONFIG_NUMA
1223 numa_add_cpu(smp_processor_id());
1224#endif
1225}
1226
1227/*
1228 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1229 * on 32-bit kernels:
1230 */
1231#ifdef CONFIG_X86_32
1232void enable_sep_cpu(void)
1233{
1234 struct tss_struct *tss;
1235 int cpu;
1236
1237 if (!boot_cpu_has(X86_FEATURE_SEP))
1238 return;
1239
1240 cpu = get_cpu();
1241 tss = &per_cpu(cpu_tss, cpu);
1242
1243 /*
1244 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1245 * see the big comment in struct x86_hw_tss's definition.
1246 */
1247
1248 tss->x86_tss.ss1 = __KERNEL_CS;
1249 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1250
1251 wrmsr(MSR_IA32_SYSENTER_ESP,
1252 (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack),
1253 0);
1254
1255 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1256
1257 put_cpu();
1258}
1259#endif
1260
1261void __init identify_boot_cpu(void)
1262{
1263 identify_cpu(&boot_cpu_data);
1264#ifdef CONFIG_X86_32
1265 sysenter_setup();
1266 enable_sep_cpu();
1267#endif
1268 cpu_detect_tlb(&boot_cpu_data);
1269}
1270
1271void identify_secondary_cpu(struct cpuinfo_x86 *c)
1272{
1273 BUG_ON(c == &boot_cpu_data);
1274 identify_cpu(c);
1275#ifdef CONFIG_X86_32
1276 enable_sep_cpu();
1277#endif
1278 mtrr_ap_init();
1279 validate_apic_and_package_id(c);
1280}
1281
1282static __init int setup_noclflush(char *arg)
1283{
1284 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1285 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1286 return 1;
1287}
1288__setup("noclflush", setup_noclflush);
1289
1290void print_cpu_info(struct cpuinfo_x86 *c)
1291{
1292 const char *vendor = NULL;
1293
1294 if (c->x86_vendor < X86_VENDOR_NUM) {
1295 vendor = this_cpu->c_vendor;
1296 } else {
1297 if (c->cpuid_level >= 0)
1298 vendor = c->x86_vendor_id;
1299 }
1300
1301 if (vendor && !strstr(c->x86_model_id, vendor))
1302 pr_cont("%s ", vendor);
1303
1304 if (c->x86_model_id[0])
1305 pr_cont("%s", c->x86_model_id);
1306 else
1307 pr_cont("%d86", c->x86);
1308
1309 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1310
1311 if (c->x86_mask || c->cpuid_level >= 0)
1312 pr_cont(", stepping: 0x%x)\n", c->x86_mask);
1313 else
1314 pr_cont(")\n");
1315}
1316
1317/*
1318 * clearcpuid= was already parsed in fpu__init_parse_early_param.
1319 * But we need to keep a dummy __setup around otherwise it would
1320 * show up as an environment variable for init.
1321 */
1322static __init int setup_clearcpuid(char *arg)
1323{
1324 return 1;
1325}
1326__setup("clearcpuid=", setup_clearcpuid);
1327
1328#ifdef CONFIG_X86_64
1329struct desc_ptr idt_descr __ro_after_init = {
1330 .size = NR_VECTORS * 16 - 1,
1331 .address = (unsigned long) idt_table,
1332};
1333const struct desc_ptr debug_idt_descr = {
1334 .size = NR_VECTORS * 16 - 1,
1335 .address = (unsigned long) debug_idt_table,
1336};
1337
1338DEFINE_PER_CPU_FIRST(union irq_stack_union,
1339 irq_stack_union) __aligned(PAGE_SIZE) __visible;
1340
1341/*
1342 * The following percpu variables are hot. Align current_task to
1343 * cacheline size such that they fall in the same cacheline.
1344 */
1345DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1346 &init_task;
1347EXPORT_PER_CPU_SYMBOL(current_task);
1348
1349DEFINE_PER_CPU(char *, irq_stack_ptr) =
1350 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE;
1351
1352DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1353
1354DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1355EXPORT_PER_CPU_SYMBOL(__preempt_count);
1356
1357/*
1358 * Special IST stacks which the CPU switches to when it calls
1359 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1360 * limit), all of them are 4K, except the debug stack which
1361 * is 8K.
1362 */
1363static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1364 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1365 [DEBUG_STACK - 1] = DEBUG_STKSZ
1366};
1367
1368static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1369 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1370
1371/* May not be marked __init: used by software suspend */
1372void syscall_init(void)
1373{
1374 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1375 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1376
1377#ifdef CONFIG_IA32_EMULATION
1378 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1379 /*
1380 * This only works on Intel CPUs.
1381 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1382 * This does not cause SYSENTER to jump to the wrong location, because
1383 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1384 */
1385 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1386 wrmsrl_safe(MSR_IA32_SYSENTER_ESP,
1387 (unsigned long)this_cpu_ptr(&cpu_tss) +
1388 offsetofend(struct tss_struct, SYSENTER_stack));
1389 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1390#else
1391 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1392 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1393 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1394 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1395#endif
1396
1397 /* Flags to clear on syscall */
1398 wrmsrl(MSR_SYSCALL_MASK,
1399 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1400 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1401}
1402
1403/*
1404 * Copies of the original ist values from the tss are only accessed during
1405 * debugging, no special alignment required.
1406 */
1407DEFINE_PER_CPU(struct orig_ist, orig_ist);
1408
1409static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1410DEFINE_PER_CPU(int, debug_stack_usage);
1411
1412int is_debug_stack(unsigned long addr)
1413{
1414 return __this_cpu_read(debug_stack_usage) ||
1415 (addr <= __this_cpu_read(debug_stack_addr) &&
1416 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ));
1417}
1418NOKPROBE_SYMBOL(is_debug_stack);
1419
1420DEFINE_PER_CPU(u32, debug_idt_ctr);
1421
1422void debug_stack_set_zero(void)
1423{
1424 this_cpu_inc(debug_idt_ctr);
1425 load_current_idt();
1426}
1427NOKPROBE_SYMBOL(debug_stack_set_zero);
1428
1429void debug_stack_reset(void)
1430{
1431 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1432 return;
1433 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1434 load_current_idt();
1435}
1436NOKPROBE_SYMBOL(debug_stack_reset);
1437
1438#else /* CONFIG_X86_64 */
1439
1440DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1441EXPORT_PER_CPU_SYMBOL(current_task);
1442DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1443EXPORT_PER_CPU_SYMBOL(__preempt_count);
1444
1445/*
1446 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1447 * the top of the kernel stack. Use an extra percpu variable to track the
1448 * top of the kernel stack directly.
1449 */
1450DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1451 (unsigned long)&init_thread_union + THREAD_SIZE;
1452EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1453
1454#ifdef CONFIG_CC_STACKPROTECTOR
1455DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1456#endif
1457
1458#endif /* CONFIG_X86_64 */
1459
1460/*
1461 * Clear all 6 debug registers:
1462 */
1463static void clear_all_debug_regs(void)
1464{
1465 int i;
1466
1467 for (i = 0; i < 8; i++) {
1468 /* Ignore db4, db5 */
1469 if ((i == 4) || (i == 5))
1470 continue;
1471
1472 set_debugreg(0, i);
1473 }
1474}
1475
1476#ifdef CONFIG_KGDB
1477/*
1478 * Restore debug regs if using kgdbwait and you have a kernel debugger
1479 * connection established.
1480 */
1481static void dbg_restore_debug_regs(void)
1482{
1483 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1484 arch_kgdb_ops.correct_hw_break();
1485}
1486#else /* ! CONFIG_KGDB */
1487#define dbg_restore_debug_regs()
1488#endif /* ! CONFIG_KGDB */
1489
1490static void wait_for_master_cpu(int cpu)
1491{
1492#ifdef CONFIG_SMP
1493 /*
1494 * wait for ACK from master CPU before continuing
1495 * with AP initialization
1496 */
1497 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1498 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1499 cpu_relax();
1500#endif
1501}
1502
1503/*
1504 * cpu_init() initializes state that is per-CPU. Some data is already
1505 * initialized (naturally) in the bootstrap process, such as the GDT
1506 * and IDT. We reload them nevertheless, this function acts as a
1507 * 'CPU state barrier', nothing should get across.
1508 * A lot of state is already set up in PDA init for 64 bit
1509 */
1510#ifdef CONFIG_X86_64
1511
1512void cpu_init(void)
1513{
1514 struct orig_ist *oist;
1515 struct task_struct *me;
1516 struct tss_struct *t;
1517 unsigned long v;
1518 int cpu = raw_smp_processor_id();
1519 int i;
1520
1521 wait_for_master_cpu(cpu);
1522
1523 /*
1524 * Initialize the CR4 shadow before doing anything that could
1525 * try to read it.
1526 */
1527 cr4_init_shadow();
1528
1529 if (cpu)
1530 load_ucode_ap();
1531
1532 t = &per_cpu(cpu_tss, cpu);
1533 oist = &per_cpu(orig_ist, cpu);
1534
1535#ifdef CONFIG_NUMA
1536 if (this_cpu_read(numa_node) == 0 &&
1537 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1538 set_numa_node(early_cpu_to_node(cpu));
1539#endif
1540
1541 me = current;
1542
1543 pr_debug("Initializing CPU#%d\n", cpu);
1544
1545 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1546
1547 /*
1548 * Initialize the per-CPU GDT with the boot GDT,
1549 * and set up the GDT descriptor:
1550 */
1551
1552 switch_to_new_gdt(cpu);
1553 loadsegment(fs, 0);
1554
1555 load_current_idt();
1556
1557 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1558 syscall_init();
1559
1560 wrmsrl(MSR_FS_BASE, 0);
1561 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1562 barrier();
1563
1564 x86_configure_nx();
1565 x2apic_setup();
1566
1567 /*
1568 * set up and load the per-CPU TSS
1569 */
1570 if (!oist->ist[0]) {
1571 char *estacks = per_cpu(exception_stacks, cpu);
1572
1573 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1574 estacks += exception_stack_sizes[v];
1575 oist->ist[v] = t->x86_tss.ist[v] =
1576 (unsigned long)estacks;
1577 if (v == DEBUG_STACK-1)
1578 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1579 }
1580 }
1581
1582 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
1583
1584 /*
1585 * <= is required because the CPU will access up to
1586 * 8 bits beyond the end of the IO permission bitmap.
1587 */
1588 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1589 t->io_bitmap[i] = ~0UL;
1590
1591 mmgrab(&init_mm);
1592 me->active_mm = &init_mm;
1593 BUG_ON(me->mm);
1594 enter_lazy_tlb(&init_mm, me);
1595
1596 /*
1597 * Initialize the TSS. Don't bother initializing sp0, as the initial
1598 * task never enters user mode.
1599 */
1600 set_tss_desc(cpu, &t->x86_tss);
1601 load_TR_desc();
1602
1603 load_mm_ldt(&init_mm);
1604
1605 clear_all_debug_regs();
1606 dbg_restore_debug_regs();
1607
1608 fpu__init_cpu();
1609
1610 if (is_uv_system())
1611 uv_cpu_init();
1612
1613 setup_cpu_entry_area(cpu);
1614 load_fixmap_gdt(cpu);
1615}
1616
1617#else
1618
1619void cpu_init(void)
1620{
1621 int cpu = smp_processor_id();
1622 struct task_struct *curr = current;
1623 struct tss_struct *t = &per_cpu(cpu_tss, cpu);
1624
1625 wait_for_master_cpu(cpu);
1626
1627 /*
1628 * Initialize the CR4 shadow before doing anything that could
1629 * try to read it.
1630 */
1631 cr4_init_shadow();
1632
1633 show_ucode_info_early();
1634
1635 pr_info("Initializing CPU#%d\n", cpu);
1636
1637 if (cpu_feature_enabled(X86_FEATURE_VME) ||
1638 boot_cpu_has(X86_FEATURE_TSC) ||
1639 boot_cpu_has(X86_FEATURE_DE))
1640 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1641
1642 load_current_idt();
1643 switch_to_new_gdt(cpu);
1644
1645 /*
1646 * Set up and load the per-CPU TSS and LDT
1647 */
1648 mmgrab(&init_mm);
1649 curr->active_mm = &init_mm;
1650 BUG_ON(curr->mm);
1651 enter_lazy_tlb(&init_mm, curr);
1652
1653 /*
1654 * Initialize the TSS. Don't bother initializing sp0, as the initial
1655 * task never enters user mode.
1656 */
1657 set_tss_desc(cpu, &t->x86_tss);
1658 load_TR_desc();
1659
1660 load_mm_ldt(&init_mm);
1661
1662 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
1663
1664#ifdef CONFIG_DOUBLEFAULT
1665 /* Set up doublefault TSS pointer in the GDT */
1666 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1667#endif
1668
1669 clear_all_debug_regs();
1670 dbg_restore_debug_regs();
1671
1672 fpu__init_cpu();
1673
1674 setup_cpu_entry_area(cpu);
1675 load_fixmap_gdt(cpu);
1676}
1677#endif
1678
1679static void bsp_resume(void)
1680{
1681 if (this_cpu->c_bsp_resume)
1682 this_cpu->c_bsp_resume(&boot_cpu_data);
1683}
1684
1685static struct syscore_ops cpu_syscore_ops = {
1686 .resume = bsp_resume,
1687};
1688
1689static int __init init_cpu_syscore(void)
1690{
1691 register_syscore_ops(&cpu_syscore_ops);
1692 return 0;
1693}
1694core_initcall(init_cpu_syscore);
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