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1#include <linux/bootmem.h>
2#include <linux/linkage.h>
3#include <linux/bitops.h>
4#include <linux/kernel.h>
5#include <linux/export.h>
6#include <linux/percpu.h>
7#include <linux/string.h>
8#include <linux/ctype.h>
9#include <linux/delay.h>
10#include <linux/sched/mm.h>
11#include <linux/sched/clock.h>
12#include <linux/sched/task.h>
13#include <linux/init.h>
14#include <linux/kprobes.h>
15#include <linux/kgdb.h>
16#include <linux/smp.h>
17#include <linux/io.h>
18#include <linux/syscore_ops.h>
19
20#include <asm/stackprotector.h>
21#include <asm/perf_event.h>
22#include <asm/mmu_context.h>
23#include <asm/archrandom.h>
24#include <asm/hypervisor.h>
25#include <asm/processor.h>
26#include <asm/tlbflush.h>
27#include <asm/debugreg.h>
28#include <asm/sections.h>
29#include <asm/vsyscall.h>
30#include <linux/topology.h>
31#include <linux/cpumask.h>
32#include <asm/pgtable.h>
33#include <linux/atomic.h>
34#include <asm/proto.h>
35#include <asm/setup.h>
36#include <asm/apic.h>
37#include <asm/desc.h>
38#include <asm/fpu/internal.h>
39#include <asm/mtrr.h>
40#include <asm/hwcap2.h>
41#include <linux/numa.h>
42#include <asm/asm.h>
43#include <asm/bugs.h>
44#include <asm/cpu.h>
45#include <asm/mce.h>
46#include <asm/msr.h>
47#include <asm/pat.h>
48#include <asm/microcode.h>
49#include <asm/microcode_intel.h>
50
51#ifdef CONFIG_X86_LOCAL_APIC
52#include <asm/uv/uv.h>
53#endif
54
55#include "cpu.h"
56
57u32 elf_hwcap2 __read_mostly;
58
59/* all of these masks are initialized in setup_cpu_local_masks() */
60cpumask_var_t cpu_initialized_mask;
61cpumask_var_t cpu_callout_mask;
62cpumask_var_t cpu_callin_mask;
63
64/* representing cpus for which sibling maps can be computed */
65cpumask_var_t cpu_sibling_setup_mask;
66
67/* correctly size the local cpu masks */
68void __init setup_cpu_local_masks(void)
69{
70 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
71 alloc_bootmem_cpumask_var(&cpu_callin_mask);
72 alloc_bootmem_cpumask_var(&cpu_callout_mask);
73 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
74}
75
76static void default_init(struct cpuinfo_x86 *c)
77{
78#ifdef CONFIG_X86_64
79 cpu_detect_cache_sizes(c);
80#else
81 /* Not much we can do here... */
82 /* Check if at least it has cpuid */
83 if (c->cpuid_level == -1) {
84 /* No cpuid. It must be an ancient CPU */
85 if (c->x86 == 4)
86 strcpy(c->x86_model_id, "486");
87 else if (c->x86 == 3)
88 strcpy(c->x86_model_id, "386");
89 }
90#endif
91}
92
93static const struct cpu_dev default_cpu = {
94 .c_init = default_init,
95 .c_vendor = "Unknown",
96 .c_x86_vendor = X86_VENDOR_UNKNOWN,
97};
98
99static const struct cpu_dev *this_cpu = &default_cpu;
100
101DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
102#ifdef CONFIG_X86_64
103 /*
104 * We need valid kernel segments for data and code in long mode too
105 * IRET will check the segment types kkeil 2000/10/28
106 * Also sysret mandates a special GDT layout
107 *
108 * TLS descriptors are currently at a different place compared to i386.
109 * Hopefully nobody expects them at a fixed place (Wine?)
110 */
111 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
112 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
113 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
114 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
115 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
116 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
117#else
118 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
119 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
120 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
121 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
122 /*
123 * Segments used for calling PnP BIOS have byte granularity.
124 * They code segments and data segments have fixed 64k limits,
125 * the transfer segment sizes are set at run time.
126 */
127 /* 32-bit code */
128 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
129 /* 16-bit code */
130 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
131 /* 16-bit data */
132 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
133 /* 16-bit data */
134 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
135 /* 16-bit data */
136 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
137 /*
138 * The APM segments have byte granularity and their bases
139 * are set at run time. All have 64k limits.
140 */
141 /* 32-bit code */
142 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
143 /* 16-bit code */
144 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
145 /* data */
146 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
147
148 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
149 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
150 GDT_STACK_CANARY_INIT
151#endif
152} };
153EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
154
155static int __init x86_mpx_setup(char *s)
156{
157 /* require an exact match without trailing characters */
158 if (strlen(s))
159 return 0;
160
161 /* do not emit a message if the feature is not present */
162 if (!boot_cpu_has(X86_FEATURE_MPX))
163 return 1;
164
165 setup_clear_cpu_cap(X86_FEATURE_MPX);
166 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
167 return 1;
168}
169__setup("nompx", x86_mpx_setup);
170
171#ifdef CONFIG_X86_64
172static int __init x86_nopcid_setup(char *s)
173{
174 /* nopcid doesn't accept parameters */
175 if (s)
176 return -EINVAL;
177
178 /* do not emit a message if the feature is not present */
179 if (!boot_cpu_has(X86_FEATURE_PCID))
180 return 0;
181
182 setup_clear_cpu_cap(X86_FEATURE_PCID);
183 pr_info("nopcid: PCID feature disabled\n");
184 return 0;
185}
186early_param("nopcid", x86_nopcid_setup);
187#endif
188
189static int __init x86_noinvpcid_setup(char *s)
190{
191 /* noinvpcid doesn't accept parameters */
192 if (s)
193 return -EINVAL;
194
195 /* do not emit a message if the feature is not present */
196 if (!boot_cpu_has(X86_FEATURE_INVPCID))
197 return 0;
198
199 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
200 pr_info("noinvpcid: INVPCID feature disabled\n");
201 return 0;
202}
203early_param("noinvpcid", x86_noinvpcid_setup);
204
205#ifdef CONFIG_X86_32
206static int cachesize_override = -1;
207static int disable_x86_serial_nr = 1;
208
209static int __init cachesize_setup(char *str)
210{
211 get_option(&str, &cachesize_override);
212 return 1;
213}
214__setup("cachesize=", cachesize_setup);
215
216static int __init x86_sep_setup(char *s)
217{
218 setup_clear_cpu_cap(X86_FEATURE_SEP);
219 return 1;
220}
221__setup("nosep", x86_sep_setup);
222
223/* Standard macro to see if a specific flag is changeable */
224static inline int flag_is_changeable_p(u32 flag)
225{
226 u32 f1, f2;
227
228 /*
229 * Cyrix and IDT cpus allow disabling of CPUID
230 * so the code below may return different results
231 * when it is executed before and after enabling
232 * the CPUID. Add "volatile" to not allow gcc to
233 * optimize the subsequent calls to this function.
234 */
235 asm volatile ("pushfl \n\t"
236 "pushfl \n\t"
237 "popl %0 \n\t"
238 "movl %0, %1 \n\t"
239 "xorl %2, %0 \n\t"
240 "pushl %0 \n\t"
241 "popfl \n\t"
242 "pushfl \n\t"
243 "popl %0 \n\t"
244 "popfl \n\t"
245
246 : "=&r" (f1), "=&r" (f2)
247 : "ir" (flag));
248
249 return ((f1^f2) & flag) != 0;
250}
251
252/* Probe for the CPUID instruction */
253int have_cpuid_p(void)
254{
255 return flag_is_changeable_p(X86_EFLAGS_ID);
256}
257
258static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
259{
260 unsigned long lo, hi;
261
262 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
263 return;
264
265 /* Disable processor serial number: */
266
267 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
268 lo |= 0x200000;
269 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
270
271 pr_notice("CPU serial number disabled.\n");
272 clear_cpu_cap(c, X86_FEATURE_PN);
273
274 /* Disabling the serial number may affect the cpuid level */
275 c->cpuid_level = cpuid_eax(0);
276}
277
278static int __init x86_serial_nr_setup(char *s)
279{
280 disable_x86_serial_nr = 0;
281 return 1;
282}
283__setup("serialnumber", x86_serial_nr_setup);
284#else
285static inline int flag_is_changeable_p(u32 flag)
286{
287 return 1;
288}
289static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
290{
291}
292#endif
293
294static __init int setup_disable_smep(char *arg)
295{
296 setup_clear_cpu_cap(X86_FEATURE_SMEP);
297 /* Check for things that depend on SMEP being enabled: */
298 check_mpx_erratum(&boot_cpu_data);
299 return 1;
300}
301__setup("nosmep", setup_disable_smep);
302
303static __always_inline void setup_smep(struct cpuinfo_x86 *c)
304{
305 if (cpu_has(c, X86_FEATURE_SMEP))
306 cr4_set_bits(X86_CR4_SMEP);
307}
308
309static __init int setup_disable_smap(char *arg)
310{
311 setup_clear_cpu_cap(X86_FEATURE_SMAP);
312 return 1;
313}
314__setup("nosmap", setup_disable_smap);
315
316static __always_inline void setup_smap(struct cpuinfo_x86 *c)
317{
318 unsigned long eflags = native_save_fl();
319
320 /* This should have been cleared long ago */
321 BUG_ON(eflags & X86_EFLAGS_AC);
322
323 if (cpu_has(c, X86_FEATURE_SMAP)) {
324#ifdef CONFIG_X86_SMAP
325 cr4_set_bits(X86_CR4_SMAP);
326#else
327 cr4_clear_bits(X86_CR4_SMAP);
328#endif
329 }
330}
331
332/*
333 * Protection Keys are not available in 32-bit mode.
334 */
335static bool pku_disabled;
336
337static __always_inline void setup_pku(struct cpuinfo_x86 *c)
338{
339 /* check the boot processor, plus compile options for PKU: */
340 if (!cpu_feature_enabled(X86_FEATURE_PKU))
341 return;
342 /* checks the actual processor's cpuid bits: */
343 if (!cpu_has(c, X86_FEATURE_PKU))
344 return;
345 if (pku_disabled)
346 return;
347
348 cr4_set_bits(X86_CR4_PKE);
349 /*
350 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
351 * cpuid bit to be set. We need to ensure that we
352 * update that bit in this CPU's "cpu_info".
353 */
354 get_cpu_cap(c);
355}
356
357#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
358static __init int setup_disable_pku(char *arg)
359{
360 /*
361 * Do not clear the X86_FEATURE_PKU bit. All of the
362 * runtime checks are against OSPKE so clearing the
363 * bit does nothing.
364 *
365 * This way, we will see "pku" in cpuinfo, but not
366 * "ospke", which is exactly what we want. It shows
367 * that the CPU has PKU, but the OS has not enabled it.
368 * This happens to be exactly how a system would look
369 * if we disabled the config option.
370 */
371 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
372 pku_disabled = true;
373 return 1;
374}
375__setup("nopku", setup_disable_pku);
376#endif /* CONFIG_X86_64 */
377
378/*
379 * Some CPU features depend on higher CPUID levels, which may not always
380 * be available due to CPUID level capping or broken virtualization
381 * software. Add those features to this table to auto-disable them.
382 */
383struct cpuid_dependent_feature {
384 u32 feature;
385 u32 level;
386};
387
388static const struct cpuid_dependent_feature
389cpuid_dependent_features[] = {
390 { X86_FEATURE_MWAIT, 0x00000005 },
391 { X86_FEATURE_DCA, 0x00000009 },
392 { X86_FEATURE_XSAVE, 0x0000000d },
393 { 0, 0 }
394};
395
396static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
397{
398 const struct cpuid_dependent_feature *df;
399
400 for (df = cpuid_dependent_features; df->feature; df++) {
401
402 if (!cpu_has(c, df->feature))
403 continue;
404 /*
405 * Note: cpuid_level is set to -1 if unavailable, but
406 * extended_extended_level is set to 0 if unavailable
407 * and the legitimate extended levels are all negative
408 * when signed; hence the weird messing around with
409 * signs here...
410 */
411 if (!((s32)df->level < 0 ?
412 (u32)df->level > (u32)c->extended_cpuid_level :
413 (s32)df->level > (s32)c->cpuid_level))
414 continue;
415
416 clear_cpu_cap(c, df->feature);
417 if (!warn)
418 continue;
419
420 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
421 x86_cap_flag(df->feature), df->level);
422 }
423}
424
425/*
426 * Naming convention should be: <Name> [(<Codename>)]
427 * This table only is used unless init_<vendor>() below doesn't set it;
428 * in particular, if CPUID levels 0x80000002..4 are supported, this
429 * isn't used
430 */
431
432/* Look up CPU names by table lookup. */
433static const char *table_lookup_model(struct cpuinfo_x86 *c)
434{
435#ifdef CONFIG_X86_32
436 const struct legacy_cpu_model_info *info;
437
438 if (c->x86_model >= 16)
439 return NULL; /* Range check */
440
441 if (!this_cpu)
442 return NULL;
443
444 info = this_cpu->legacy_models;
445
446 while (info->family) {
447 if (info->family == c->x86)
448 return info->model_names[c->x86_model];
449 info++;
450 }
451#endif
452 return NULL; /* Not found */
453}
454
455__u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
456__u32 cpu_caps_set[NCAPINTS + NBUGINTS];
457
458void load_percpu_segment(int cpu)
459{
460#ifdef CONFIG_X86_32
461 loadsegment(fs, __KERNEL_PERCPU);
462#else
463 __loadsegment_simple(gs, 0);
464 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
465#endif
466 load_stack_canary_segment();
467}
468
469#ifdef CONFIG_X86_32
470/* The 32-bit entry code needs to find cpu_entry_area. */
471DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
472#endif
473
474#ifdef CONFIG_X86_64
475/*
476 * Special IST stacks which the CPU switches to when it calls
477 * an IST-marked descriptor entry. Up to 7 stacks (hardware
478 * limit), all of them are 4K, except the debug stack which
479 * is 8K.
480 */
481static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
482 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
483 [DEBUG_STACK - 1] = DEBUG_STKSZ
484};
485#endif
486
487/* Load the original GDT from the per-cpu structure */
488void load_direct_gdt(int cpu)
489{
490 struct desc_ptr gdt_descr;
491
492 gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
493 gdt_descr.size = GDT_SIZE - 1;
494 load_gdt(&gdt_descr);
495}
496EXPORT_SYMBOL_GPL(load_direct_gdt);
497
498/* Load a fixmap remapping of the per-cpu GDT */
499void load_fixmap_gdt(int cpu)
500{
501 struct desc_ptr gdt_descr;
502
503 gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
504 gdt_descr.size = GDT_SIZE - 1;
505 load_gdt(&gdt_descr);
506}
507EXPORT_SYMBOL_GPL(load_fixmap_gdt);
508
509/*
510 * Current gdt points %fs at the "master" per-cpu area: after this,
511 * it's on the real one.
512 */
513void switch_to_new_gdt(int cpu)
514{
515 /* Load the original GDT */
516 load_direct_gdt(cpu);
517 /* Reload the per-cpu base */
518 load_percpu_segment(cpu);
519}
520
521static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
522
523static void get_model_name(struct cpuinfo_x86 *c)
524{
525 unsigned int *v;
526 char *p, *q, *s;
527
528 if (c->extended_cpuid_level < 0x80000004)
529 return;
530
531 v = (unsigned int *)c->x86_model_id;
532 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
533 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
534 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
535 c->x86_model_id[48] = 0;
536
537 /* Trim whitespace */
538 p = q = s = &c->x86_model_id[0];
539
540 while (*p == ' ')
541 p++;
542
543 while (*p) {
544 /* Note the last non-whitespace index */
545 if (!isspace(*p))
546 s = q;
547
548 *q++ = *p++;
549 }
550
551 *(s + 1) = '\0';
552}
553
554void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
555{
556 unsigned int n, dummy, ebx, ecx, edx, l2size;
557
558 n = c->extended_cpuid_level;
559
560 if (n >= 0x80000005) {
561 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
562 c->x86_cache_size = (ecx>>24) + (edx>>24);
563#ifdef CONFIG_X86_64
564 /* On K8 L1 TLB is inclusive, so don't count it */
565 c->x86_tlbsize = 0;
566#endif
567 }
568
569 if (n < 0x80000006) /* Some chips just has a large L1. */
570 return;
571
572 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
573 l2size = ecx >> 16;
574
575#ifdef CONFIG_X86_64
576 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
577#else
578 /* do processor-specific cache resizing */
579 if (this_cpu->legacy_cache_size)
580 l2size = this_cpu->legacy_cache_size(c, l2size);
581
582 /* Allow user to override all this if necessary. */
583 if (cachesize_override != -1)
584 l2size = cachesize_override;
585
586 if (l2size == 0)
587 return; /* Again, no L2 cache is possible */
588#endif
589
590 c->x86_cache_size = l2size;
591}
592
593u16 __read_mostly tlb_lli_4k[NR_INFO];
594u16 __read_mostly tlb_lli_2m[NR_INFO];
595u16 __read_mostly tlb_lli_4m[NR_INFO];
596u16 __read_mostly tlb_lld_4k[NR_INFO];
597u16 __read_mostly tlb_lld_2m[NR_INFO];
598u16 __read_mostly tlb_lld_4m[NR_INFO];
599u16 __read_mostly tlb_lld_1g[NR_INFO];
600
601static void cpu_detect_tlb(struct cpuinfo_x86 *c)
602{
603 if (this_cpu->c_detect_tlb)
604 this_cpu->c_detect_tlb(c);
605
606 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
607 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
608 tlb_lli_4m[ENTRIES]);
609
610 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
611 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
612 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
613}
614
615void detect_ht(struct cpuinfo_x86 *c)
616{
617#ifdef CONFIG_SMP
618 u32 eax, ebx, ecx, edx;
619 int index_msb, core_bits;
620 static bool printed;
621
622 if (!cpu_has(c, X86_FEATURE_HT))
623 return;
624
625 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
626 goto out;
627
628 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
629 return;
630
631 cpuid(1, &eax, &ebx, &ecx, &edx);
632
633 smp_num_siblings = (ebx & 0xff0000) >> 16;
634
635 if (smp_num_siblings == 1) {
636 pr_info_once("CPU0: Hyper-Threading is disabled\n");
637 goto out;
638 }
639
640 if (smp_num_siblings <= 1)
641 goto out;
642
643 index_msb = get_count_order(smp_num_siblings);
644 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
645
646 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
647
648 index_msb = get_count_order(smp_num_siblings);
649
650 core_bits = get_count_order(c->x86_max_cores);
651
652 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
653 ((1 << core_bits) - 1);
654
655out:
656 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
657 pr_info("CPU: Physical Processor ID: %d\n",
658 c->phys_proc_id);
659 pr_info("CPU: Processor Core ID: %d\n",
660 c->cpu_core_id);
661 printed = 1;
662 }
663#endif
664}
665
666static void get_cpu_vendor(struct cpuinfo_x86 *c)
667{
668 char *v = c->x86_vendor_id;
669 int i;
670
671 for (i = 0; i < X86_VENDOR_NUM; i++) {
672 if (!cpu_devs[i])
673 break;
674
675 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
676 (cpu_devs[i]->c_ident[1] &&
677 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
678
679 this_cpu = cpu_devs[i];
680 c->x86_vendor = this_cpu->c_x86_vendor;
681 return;
682 }
683 }
684
685 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
686 "CPU: Your system may be unstable.\n", v);
687
688 c->x86_vendor = X86_VENDOR_UNKNOWN;
689 this_cpu = &default_cpu;
690}
691
692void cpu_detect(struct cpuinfo_x86 *c)
693{
694 /* Get vendor name */
695 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
696 (unsigned int *)&c->x86_vendor_id[0],
697 (unsigned int *)&c->x86_vendor_id[8],
698 (unsigned int *)&c->x86_vendor_id[4]);
699
700 c->x86 = 4;
701 /* Intel-defined flags: level 0x00000001 */
702 if (c->cpuid_level >= 0x00000001) {
703 u32 junk, tfms, cap0, misc;
704
705 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
706 c->x86 = x86_family(tfms);
707 c->x86_model = x86_model(tfms);
708 c->x86_mask = x86_stepping(tfms);
709
710 if (cap0 & (1<<19)) {
711 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
712 c->x86_cache_alignment = c->x86_clflush_size;
713 }
714 }
715}
716
717static void apply_forced_caps(struct cpuinfo_x86 *c)
718{
719 int i;
720
721 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
722 c->x86_capability[i] &= ~cpu_caps_cleared[i];
723 c->x86_capability[i] |= cpu_caps_set[i];
724 }
725}
726
727void get_cpu_cap(struct cpuinfo_x86 *c)
728{
729 u32 eax, ebx, ecx, edx;
730
731 /* Intel-defined flags: level 0x00000001 */
732 if (c->cpuid_level >= 0x00000001) {
733 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
734
735 c->x86_capability[CPUID_1_ECX] = ecx;
736 c->x86_capability[CPUID_1_EDX] = edx;
737 }
738
739 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
740 if (c->cpuid_level >= 0x00000006)
741 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
742
743 /* Additional Intel-defined flags: level 0x00000007 */
744 if (c->cpuid_level >= 0x00000007) {
745 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
746 c->x86_capability[CPUID_7_0_EBX] = ebx;
747 c->x86_capability[CPUID_7_ECX] = ecx;
748 }
749
750 /* Extended state features: level 0x0000000d */
751 if (c->cpuid_level >= 0x0000000d) {
752 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
753
754 c->x86_capability[CPUID_D_1_EAX] = eax;
755 }
756
757 /* Additional Intel-defined flags: level 0x0000000F */
758 if (c->cpuid_level >= 0x0000000F) {
759
760 /* QoS sub-leaf, EAX=0Fh, ECX=0 */
761 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx);
762 c->x86_capability[CPUID_F_0_EDX] = edx;
763
764 if (cpu_has(c, X86_FEATURE_CQM_LLC)) {
765 /* will be overridden if occupancy monitoring exists */
766 c->x86_cache_max_rmid = ebx;
767
768 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
769 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx);
770 c->x86_capability[CPUID_F_1_EDX] = edx;
771
772 if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) ||
773 ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) ||
774 (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) {
775 c->x86_cache_max_rmid = ecx;
776 c->x86_cache_occ_scale = ebx;
777 }
778 } else {
779 c->x86_cache_max_rmid = -1;
780 c->x86_cache_occ_scale = -1;
781 }
782 }
783
784 /* AMD-defined flags: level 0x80000001 */
785 eax = cpuid_eax(0x80000000);
786 c->extended_cpuid_level = eax;
787
788 if ((eax & 0xffff0000) == 0x80000000) {
789 if (eax >= 0x80000001) {
790 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
791
792 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
793 c->x86_capability[CPUID_8000_0001_EDX] = edx;
794 }
795 }
796
797 if (c->extended_cpuid_level >= 0x80000007) {
798 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
799
800 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
801 c->x86_power = edx;
802 }
803
804 if (c->extended_cpuid_level >= 0x80000008) {
805 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
806
807 c->x86_virt_bits = (eax >> 8) & 0xff;
808 c->x86_phys_bits = eax & 0xff;
809 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
810 }
811#ifdef CONFIG_X86_32
812 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
813 c->x86_phys_bits = 36;
814#endif
815
816 if (c->extended_cpuid_level >= 0x8000000a)
817 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
818
819 init_scattered_cpuid_features(c);
820
821 /*
822 * Clear/Set all flags overridden by options, after probe.
823 * This needs to happen each time we re-probe, which may happen
824 * several times during CPU initialization.
825 */
826 apply_forced_caps(c);
827}
828
829static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
830{
831#ifdef CONFIG_X86_32
832 int i;
833
834 /*
835 * First of all, decide if this is a 486 or higher
836 * It's a 486 if we can modify the AC flag
837 */
838 if (flag_is_changeable_p(X86_EFLAGS_AC))
839 c->x86 = 4;
840 else
841 c->x86 = 3;
842
843 for (i = 0; i < X86_VENDOR_NUM; i++)
844 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
845 c->x86_vendor_id[0] = 0;
846 cpu_devs[i]->c_identify(c);
847 if (c->x86_vendor_id[0]) {
848 get_cpu_vendor(c);
849 break;
850 }
851 }
852#endif
853}
854
855/*
856 * Do minimum CPU detection early.
857 * Fields really needed: vendor, cpuid_level, family, model, mask,
858 * cache alignment.
859 * The others are not touched to avoid unwanted side effects.
860 *
861 * WARNING: this function is only called on the BP. Don't add code here
862 * that is supposed to run on all CPUs.
863 */
864static void __init early_identify_cpu(struct cpuinfo_x86 *c)
865{
866#ifdef CONFIG_X86_64
867 c->x86_clflush_size = 64;
868 c->x86_phys_bits = 36;
869 c->x86_virt_bits = 48;
870#else
871 c->x86_clflush_size = 32;
872 c->x86_phys_bits = 32;
873 c->x86_virt_bits = 32;
874#endif
875 c->x86_cache_alignment = c->x86_clflush_size;
876
877 memset(&c->x86_capability, 0, sizeof c->x86_capability);
878 c->extended_cpuid_level = 0;
879
880 /* cyrix could have cpuid enabled via c_identify()*/
881 if (have_cpuid_p()) {
882 cpu_detect(c);
883 get_cpu_vendor(c);
884 get_cpu_cap(c);
885 setup_force_cpu_cap(X86_FEATURE_CPUID);
886
887 if (this_cpu->c_early_init)
888 this_cpu->c_early_init(c);
889
890 c->cpu_index = 0;
891 filter_cpuid_features(c, false);
892
893 if (this_cpu->c_bsp_init)
894 this_cpu->c_bsp_init(c);
895 } else {
896 identify_cpu_without_cpuid(c);
897 setup_clear_cpu_cap(X86_FEATURE_CPUID);
898 }
899
900 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
901
902 if (c->x86_vendor != X86_VENDOR_AMD)
903 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
904
905 setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
906 setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
907
908 fpu__init_system(c);
909}
910
911void __init early_cpu_init(void)
912{
913 const struct cpu_dev *const *cdev;
914 int count = 0;
915
916#ifdef CONFIG_PROCESSOR_SELECT
917 pr_info("KERNEL supported cpus:\n");
918#endif
919
920 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
921 const struct cpu_dev *cpudev = *cdev;
922
923 if (count >= X86_VENDOR_NUM)
924 break;
925 cpu_devs[count] = cpudev;
926 count++;
927
928#ifdef CONFIG_PROCESSOR_SELECT
929 {
930 unsigned int j;
931
932 for (j = 0; j < 2; j++) {
933 if (!cpudev->c_ident[j])
934 continue;
935 pr_info(" %s %s\n", cpudev->c_vendor,
936 cpudev->c_ident[j]);
937 }
938 }
939#endif
940 }
941 early_identify_cpu(&boot_cpu_data);
942}
943
944/*
945 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
946 * unfortunately, that's not true in practice because of early VIA
947 * chips and (more importantly) broken virtualizers that are not easy
948 * to detect. In the latter case it doesn't even *fail* reliably, so
949 * probing for it doesn't even work. Disable it completely on 32-bit
950 * unless we can find a reliable way to detect all the broken cases.
951 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
952 */
953static void detect_nopl(struct cpuinfo_x86 *c)
954{
955#ifdef CONFIG_X86_32
956 clear_cpu_cap(c, X86_FEATURE_NOPL);
957#else
958 set_cpu_cap(c, X86_FEATURE_NOPL);
959#endif
960}
961
962static void detect_null_seg_behavior(struct cpuinfo_x86 *c)
963{
964#ifdef CONFIG_X86_64
965 /*
966 * Empirically, writing zero to a segment selector on AMD does
967 * not clear the base, whereas writing zero to a segment
968 * selector on Intel does clear the base. Intel's behavior
969 * allows slightly faster context switches in the common case
970 * where GS is unused by the prev and next threads.
971 *
972 * Since neither vendor documents this anywhere that I can see,
973 * detect it directly instead of hardcoding the choice by
974 * vendor.
975 *
976 * I've designated AMD's behavior as the "bug" because it's
977 * counterintuitive and less friendly.
978 */
979
980 unsigned long old_base, tmp;
981 rdmsrl(MSR_FS_BASE, old_base);
982 wrmsrl(MSR_FS_BASE, 1);
983 loadsegment(fs, 0);
984 rdmsrl(MSR_FS_BASE, tmp);
985 if (tmp != 0)
986 set_cpu_bug(c, X86_BUG_NULL_SEG);
987 wrmsrl(MSR_FS_BASE, old_base);
988#endif
989}
990
991static void generic_identify(struct cpuinfo_x86 *c)
992{
993 c->extended_cpuid_level = 0;
994
995 if (!have_cpuid_p())
996 identify_cpu_without_cpuid(c);
997
998 /* cyrix could have cpuid enabled via c_identify()*/
999 if (!have_cpuid_p())
1000 return;
1001
1002 cpu_detect(c);
1003
1004 get_cpu_vendor(c);
1005
1006 get_cpu_cap(c);
1007
1008 if (c->cpuid_level >= 0x00000001) {
1009 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
1010#ifdef CONFIG_X86_32
1011# ifdef CONFIG_SMP
1012 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1013# else
1014 c->apicid = c->initial_apicid;
1015# endif
1016#endif
1017 c->phys_proc_id = c->initial_apicid;
1018 }
1019
1020 get_model_name(c); /* Default name */
1021
1022 detect_nopl(c);
1023
1024 detect_null_seg_behavior(c);
1025
1026 /*
1027 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1028 * systems that run Linux at CPL > 0 may or may not have the
1029 * issue, but, even if they have the issue, there's absolutely
1030 * nothing we can do about it because we can't use the real IRET
1031 * instruction.
1032 *
1033 * NB: For the time being, only 32-bit kernels support
1034 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1035 * whether to apply espfix using paravirt hooks. If any
1036 * non-paravirt system ever shows up that does *not* have the
1037 * ESPFIX issue, we can change this.
1038 */
1039#ifdef CONFIG_X86_32
1040# ifdef CONFIG_PARAVIRT
1041 do {
1042 extern void native_iret(void);
1043 if (pv_cpu_ops.iret == native_iret)
1044 set_cpu_bug(c, X86_BUG_ESPFIX);
1045 } while (0);
1046# else
1047 set_cpu_bug(c, X86_BUG_ESPFIX);
1048# endif
1049#endif
1050}
1051
1052static void x86_init_cache_qos(struct cpuinfo_x86 *c)
1053{
1054 /*
1055 * The heavy lifting of max_rmid and cache_occ_scale are handled
1056 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
1057 * in case CQM bits really aren't there in this CPU.
1058 */
1059 if (c != &boot_cpu_data) {
1060 boot_cpu_data.x86_cache_max_rmid =
1061 min(boot_cpu_data.x86_cache_max_rmid,
1062 c->x86_cache_max_rmid);
1063 }
1064}
1065
1066/*
1067 * Validate that ACPI/mptables have the same information about the
1068 * effective APIC id and update the package map.
1069 */
1070static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
1071{
1072#ifdef CONFIG_SMP
1073 unsigned int apicid, cpu = smp_processor_id();
1074
1075 apicid = apic->cpu_present_to_apicid(cpu);
1076
1077 if (apicid != c->apicid) {
1078 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1079 cpu, apicid, c->initial_apicid);
1080 }
1081 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
1082#else
1083 c->logical_proc_id = 0;
1084#endif
1085}
1086
1087/*
1088 * This does the hard work of actually picking apart the CPU stuff...
1089 */
1090static void identify_cpu(struct cpuinfo_x86 *c)
1091{
1092 int i;
1093
1094 c->loops_per_jiffy = loops_per_jiffy;
1095 c->x86_cache_size = -1;
1096 c->x86_vendor = X86_VENDOR_UNKNOWN;
1097 c->x86_model = c->x86_mask = 0; /* So far unknown... */
1098 c->x86_vendor_id[0] = '\0'; /* Unset */
1099 c->x86_model_id[0] = '\0'; /* Unset */
1100 c->x86_max_cores = 1;
1101 c->x86_coreid_bits = 0;
1102 c->cu_id = 0xff;
1103#ifdef CONFIG_X86_64
1104 c->x86_clflush_size = 64;
1105 c->x86_phys_bits = 36;
1106 c->x86_virt_bits = 48;
1107#else
1108 c->cpuid_level = -1; /* CPUID not detected */
1109 c->x86_clflush_size = 32;
1110 c->x86_phys_bits = 32;
1111 c->x86_virt_bits = 32;
1112#endif
1113 c->x86_cache_alignment = c->x86_clflush_size;
1114 memset(&c->x86_capability, 0, sizeof c->x86_capability);
1115
1116 generic_identify(c);
1117
1118 if (this_cpu->c_identify)
1119 this_cpu->c_identify(c);
1120
1121 /* Clear/Set all flags overridden by options, after probe */
1122 apply_forced_caps(c);
1123
1124#ifdef CONFIG_X86_64
1125 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1126#endif
1127
1128 /*
1129 * Vendor-specific initialization. In this section we
1130 * canonicalize the feature flags, meaning if there are
1131 * features a certain CPU supports which CPUID doesn't
1132 * tell us, CPUID claiming incorrect flags, or other bugs,
1133 * we handle them here.
1134 *
1135 * At the end of this section, c->x86_capability better
1136 * indicate the features this CPU genuinely supports!
1137 */
1138 if (this_cpu->c_init)
1139 this_cpu->c_init(c);
1140
1141 /* Disable the PN if appropriate */
1142 squash_the_stupid_serial_number(c);
1143
1144 /* Set up SMEP/SMAP */
1145 setup_smep(c);
1146 setup_smap(c);
1147
1148 /*
1149 * The vendor-specific functions might have changed features.
1150 * Now we do "generic changes."
1151 */
1152
1153 /* Filter out anything that depends on CPUID levels we don't have */
1154 filter_cpuid_features(c, true);
1155
1156 /* If the model name is still unset, do table lookup. */
1157 if (!c->x86_model_id[0]) {
1158 const char *p;
1159 p = table_lookup_model(c);
1160 if (p)
1161 strcpy(c->x86_model_id, p);
1162 else
1163 /* Last resort... */
1164 sprintf(c->x86_model_id, "%02x/%02x",
1165 c->x86, c->x86_model);
1166 }
1167
1168#ifdef CONFIG_X86_64
1169 detect_ht(c);
1170#endif
1171
1172 x86_init_rdrand(c);
1173 x86_init_cache_qos(c);
1174 setup_pku(c);
1175
1176 /*
1177 * Clear/Set all flags overridden by options, need do it
1178 * before following smp all cpus cap AND.
1179 */
1180 apply_forced_caps(c);
1181
1182 /*
1183 * On SMP, boot_cpu_data holds the common feature set between
1184 * all CPUs; so make sure that we indicate which features are
1185 * common between the CPUs. The first time this routine gets
1186 * executed, c == &boot_cpu_data.
1187 */
1188 if (c != &boot_cpu_data) {
1189 /* AND the already accumulated flags with these */
1190 for (i = 0; i < NCAPINTS; i++)
1191 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1192
1193 /* OR, i.e. replicate the bug flags */
1194 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1195 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1196 }
1197
1198 /* Init Machine Check Exception if available. */
1199 mcheck_cpu_init(c);
1200
1201 select_idle_routine(c);
1202
1203#ifdef CONFIG_NUMA
1204 numa_add_cpu(smp_processor_id());
1205#endif
1206}
1207
1208/*
1209 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1210 * on 32-bit kernels:
1211 */
1212#ifdef CONFIG_X86_32
1213void enable_sep_cpu(void)
1214{
1215 struct tss_struct *tss;
1216 int cpu;
1217
1218 if (!boot_cpu_has(X86_FEATURE_SEP))
1219 return;
1220
1221 cpu = get_cpu();
1222 tss = &per_cpu(cpu_tss_rw, cpu);
1223
1224 /*
1225 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1226 * see the big comment in struct x86_hw_tss's definition.
1227 */
1228
1229 tss->x86_tss.ss1 = __KERNEL_CS;
1230 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1231 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);
1232 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1233
1234 put_cpu();
1235}
1236#endif
1237
1238void __init identify_boot_cpu(void)
1239{
1240 identify_cpu(&boot_cpu_data);
1241#ifdef CONFIG_X86_32
1242 sysenter_setup();
1243 enable_sep_cpu();
1244#endif
1245 cpu_detect_tlb(&boot_cpu_data);
1246}
1247
1248void identify_secondary_cpu(struct cpuinfo_x86 *c)
1249{
1250 BUG_ON(c == &boot_cpu_data);
1251 identify_cpu(c);
1252#ifdef CONFIG_X86_32
1253 enable_sep_cpu();
1254#endif
1255 mtrr_ap_init();
1256 validate_apic_and_package_id(c);
1257}
1258
1259static __init int setup_noclflush(char *arg)
1260{
1261 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1262 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1263 return 1;
1264}
1265__setup("noclflush", setup_noclflush);
1266
1267void print_cpu_info(struct cpuinfo_x86 *c)
1268{
1269 const char *vendor = NULL;
1270
1271 if (c->x86_vendor < X86_VENDOR_NUM) {
1272 vendor = this_cpu->c_vendor;
1273 } else {
1274 if (c->cpuid_level >= 0)
1275 vendor = c->x86_vendor_id;
1276 }
1277
1278 if (vendor && !strstr(c->x86_model_id, vendor))
1279 pr_cont("%s ", vendor);
1280
1281 if (c->x86_model_id[0])
1282 pr_cont("%s", c->x86_model_id);
1283 else
1284 pr_cont("%d86", c->x86);
1285
1286 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1287
1288 if (c->x86_mask || c->cpuid_level >= 0)
1289 pr_cont(", stepping: 0x%x)\n", c->x86_mask);
1290 else
1291 pr_cont(")\n");
1292}
1293
1294/*
1295 * clearcpuid= was already parsed in fpu__init_parse_early_param.
1296 * But we need to keep a dummy __setup around otherwise it would
1297 * show up as an environment variable for init.
1298 */
1299static __init int setup_clearcpuid(char *arg)
1300{
1301 return 1;
1302}
1303__setup("clearcpuid=", setup_clearcpuid);
1304
1305#ifdef CONFIG_X86_64
1306struct desc_ptr idt_descr __ro_after_init = {
1307 .size = NR_VECTORS * 16 - 1,
1308 .address = (unsigned long) idt_table,
1309};
1310const struct desc_ptr debug_idt_descr = {
1311 .size = NR_VECTORS * 16 - 1,
1312 .address = (unsigned long) debug_idt_table,
1313};
1314
1315DEFINE_PER_CPU_FIRST(union irq_stack_union,
1316 irq_stack_union) __aligned(PAGE_SIZE) __visible;
1317
1318/*
1319 * The following percpu variables are hot. Align current_task to
1320 * cacheline size such that they fall in the same cacheline.
1321 */
1322DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1323 &init_task;
1324EXPORT_PER_CPU_SYMBOL(current_task);
1325
1326DEFINE_PER_CPU(char *, irq_stack_ptr) =
1327 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE;
1328
1329DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1330
1331DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1332EXPORT_PER_CPU_SYMBOL(__preempt_count);
1333
1334/* May not be marked __init: used by software suspend */
1335void syscall_init(void)
1336{
1337 extern char _entry_trampoline[];
1338 extern char entry_SYSCALL_64_trampoline[];
1339
1340 int cpu = smp_processor_id();
1341 unsigned long SYSCALL64_entry_trampoline =
1342 (unsigned long)get_cpu_entry_area(cpu)->entry_trampoline +
1343 (entry_SYSCALL_64_trampoline - _entry_trampoline);
1344
1345 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1346 if (static_cpu_has(X86_FEATURE_PTI))
1347 wrmsrl(MSR_LSTAR, SYSCALL64_entry_trampoline);
1348 else
1349 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1350
1351#ifdef CONFIG_IA32_EMULATION
1352 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1353 /*
1354 * This only works on Intel CPUs.
1355 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1356 * This does not cause SYSENTER to jump to the wrong location, because
1357 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1358 */
1359 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1360 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1));
1361 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1362#else
1363 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1364 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1365 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1366 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1367#endif
1368
1369 /* Flags to clear on syscall */
1370 wrmsrl(MSR_SYSCALL_MASK,
1371 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1372 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1373}
1374
1375/*
1376 * Copies of the original ist values from the tss are only accessed during
1377 * debugging, no special alignment required.
1378 */
1379DEFINE_PER_CPU(struct orig_ist, orig_ist);
1380
1381static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1382DEFINE_PER_CPU(int, debug_stack_usage);
1383
1384int is_debug_stack(unsigned long addr)
1385{
1386 return __this_cpu_read(debug_stack_usage) ||
1387 (addr <= __this_cpu_read(debug_stack_addr) &&
1388 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ));
1389}
1390NOKPROBE_SYMBOL(is_debug_stack);
1391
1392DEFINE_PER_CPU(u32, debug_idt_ctr);
1393
1394void debug_stack_set_zero(void)
1395{
1396 this_cpu_inc(debug_idt_ctr);
1397 load_current_idt();
1398}
1399NOKPROBE_SYMBOL(debug_stack_set_zero);
1400
1401void debug_stack_reset(void)
1402{
1403 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1404 return;
1405 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1406 load_current_idt();
1407}
1408NOKPROBE_SYMBOL(debug_stack_reset);
1409
1410#else /* CONFIG_X86_64 */
1411
1412DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1413EXPORT_PER_CPU_SYMBOL(current_task);
1414DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1415EXPORT_PER_CPU_SYMBOL(__preempt_count);
1416
1417/*
1418 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1419 * the top of the kernel stack. Use an extra percpu variable to track the
1420 * top of the kernel stack directly.
1421 */
1422DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1423 (unsigned long)&init_thread_union + THREAD_SIZE;
1424EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1425
1426#ifdef CONFIG_CC_STACKPROTECTOR
1427DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1428#endif
1429
1430#endif /* CONFIG_X86_64 */
1431
1432/*
1433 * Clear all 6 debug registers:
1434 */
1435static void clear_all_debug_regs(void)
1436{
1437 int i;
1438
1439 for (i = 0; i < 8; i++) {
1440 /* Ignore db4, db5 */
1441 if ((i == 4) || (i == 5))
1442 continue;
1443
1444 set_debugreg(0, i);
1445 }
1446}
1447
1448#ifdef CONFIG_KGDB
1449/*
1450 * Restore debug regs if using kgdbwait and you have a kernel debugger
1451 * connection established.
1452 */
1453static void dbg_restore_debug_regs(void)
1454{
1455 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1456 arch_kgdb_ops.correct_hw_break();
1457}
1458#else /* ! CONFIG_KGDB */
1459#define dbg_restore_debug_regs()
1460#endif /* ! CONFIG_KGDB */
1461
1462static void wait_for_master_cpu(int cpu)
1463{
1464#ifdef CONFIG_SMP
1465 /*
1466 * wait for ACK from master CPU before continuing
1467 * with AP initialization
1468 */
1469 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1470 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1471 cpu_relax();
1472#endif
1473}
1474
1475/*
1476 * cpu_init() initializes state that is per-CPU. Some data is already
1477 * initialized (naturally) in the bootstrap process, such as the GDT
1478 * and IDT. We reload them nevertheless, this function acts as a
1479 * 'CPU state barrier', nothing should get across.
1480 * A lot of state is already set up in PDA init for 64 bit
1481 */
1482#ifdef CONFIG_X86_64
1483
1484void cpu_init(void)
1485{
1486 struct orig_ist *oist;
1487 struct task_struct *me;
1488 struct tss_struct *t;
1489 unsigned long v;
1490 int cpu = raw_smp_processor_id();
1491 int i;
1492
1493 wait_for_master_cpu(cpu);
1494
1495 /*
1496 * Initialize the CR4 shadow before doing anything that could
1497 * try to read it.
1498 */
1499 cr4_init_shadow();
1500
1501 if (cpu)
1502 load_ucode_ap();
1503
1504 t = &per_cpu(cpu_tss_rw, cpu);
1505 oist = &per_cpu(orig_ist, cpu);
1506
1507#ifdef CONFIG_NUMA
1508 if (this_cpu_read(numa_node) == 0 &&
1509 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1510 set_numa_node(early_cpu_to_node(cpu));
1511#endif
1512
1513 me = current;
1514
1515 pr_debug("Initializing CPU#%d\n", cpu);
1516
1517 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1518
1519 /*
1520 * Initialize the per-CPU GDT with the boot GDT,
1521 * and set up the GDT descriptor:
1522 */
1523
1524 switch_to_new_gdt(cpu);
1525 loadsegment(fs, 0);
1526
1527 load_current_idt();
1528
1529 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1530 syscall_init();
1531
1532 wrmsrl(MSR_FS_BASE, 0);
1533 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1534 barrier();
1535
1536 x86_configure_nx();
1537 x2apic_setup();
1538
1539 /*
1540 * set up and load the per-CPU TSS
1541 */
1542 if (!oist->ist[0]) {
1543 char *estacks = get_cpu_entry_area(cpu)->exception_stacks;
1544
1545 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1546 estacks += exception_stack_sizes[v];
1547 oist->ist[v] = t->x86_tss.ist[v] =
1548 (unsigned long)estacks;
1549 if (v == DEBUG_STACK-1)
1550 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1551 }
1552 }
1553
1554 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
1555
1556 /*
1557 * <= is required because the CPU will access up to
1558 * 8 bits beyond the end of the IO permission bitmap.
1559 */
1560 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1561 t->io_bitmap[i] = ~0UL;
1562
1563 mmgrab(&init_mm);
1564 me->active_mm = &init_mm;
1565 BUG_ON(me->mm);
1566 enter_lazy_tlb(&init_mm, me);
1567
1568 /*
1569 * Initialize the TSS. sp0 points to the entry trampoline stack
1570 * regardless of what task is running.
1571 */
1572 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1573 load_TR_desc();
1574 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
1575
1576 load_mm_ldt(&init_mm);
1577
1578 clear_all_debug_regs();
1579 dbg_restore_debug_regs();
1580
1581 fpu__init_cpu();
1582
1583 if (is_uv_system())
1584 uv_cpu_init();
1585
1586 load_fixmap_gdt(cpu);
1587}
1588
1589#else
1590
1591void cpu_init(void)
1592{
1593 int cpu = smp_processor_id();
1594 struct task_struct *curr = current;
1595 struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu);
1596
1597 wait_for_master_cpu(cpu);
1598
1599 /*
1600 * Initialize the CR4 shadow before doing anything that could
1601 * try to read it.
1602 */
1603 cr4_init_shadow();
1604
1605 show_ucode_info_early();
1606
1607 pr_info("Initializing CPU#%d\n", cpu);
1608
1609 if (cpu_feature_enabled(X86_FEATURE_VME) ||
1610 boot_cpu_has(X86_FEATURE_TSC) ||
1611 boot_cpu_has(X86_FEATURE_DE))
1612 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1613
1614 load_current_idt();
1615 switch_to_new_gdt(cpu);
1616
1617 /*
1618 * Set up and load the per-CPU TSS and LDT
1619 */
1620 mmgrab(&init_mm);
1621 curr->active_mm = &init_mm;
1622 BUG_ON(curr->mm);
1623 enter_lazy_tlb(&init_mm, curr);
1624
1625 /*
1626 * Initialize the TSS. Don't bother initializing sp0, as the initial
1627 * task never enters user mode.
1628 */
1629 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1630 load_TR_desc();
1631
1632 load_mm_ldt(&init_mm);
1633
1634 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
1635
1636#ifdef CONFIG_DOUBLEFAULT
1637 /* Set up doublefault TSS pointer in the GDT */
1638 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1639#endif
1640
1641 clear_all_debug_regs();
1642 dbg_restore_debug_regs();
1643
1644 fpu__init_cpu();
1645
1646 load_fixmap_gdt(cpu);
1647}
1648#endif
1649
1650static void bsp_resume(void)
1651{
1652 if (this_cpu->c_bsp_resume)
1653 this_cpu->c_bsp_resume(&boot_cpu_data);
1654}
1655
1656static struct syscore_ops cpu_syscore_ops = {
1657 .resume = bsp_resume,
1658};
1659
1660static int __init init_cpu_syscore(void)
1661{
1662 register_syscore_ops(&cpu_syscore_ops);
1663 return 0;
1664}
1665core_initcall(init_cpu_syscore);
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