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[mirror_ubuntu-artful-kernel.git] / arch / x86 / kernel / cpu / common.c
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1#include <linux/bootmem.h>
2#include <linux/linkage.h>
3#include <linux/bitops.h>
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/percpu.h>
7#include <linux/string.h>
8#include <linux/delay.h>
9#include <linux/sched.h>
10#include <linux/init.h>
11#include <linux/kgdb.h>
12#include <linux/smp.h>
13#include <linux/io.h>
14
15#include <asm/stackprotector.h>
16#include <asm/perf_event.h>
17#include <asm/mmu_context.h>
18#include <asm/archrandom.h>
19#include <asm/hypervisor.h>
20#include <asm/processor.h>
21#include <asm/sections.h>
22#include <linux/topology.h>
23#include <linux/cpumask.h>
24#include <asm/pgtable.h>
25#include <linux/atomic.h>
26#include <asm/proto.h>
27#include <asm/setup.h>
28#include <asm/apic.h>
29#include <asm/desc.h>
30#include <asm/i387.h>
31#include <asm/mtrr.h>
32#include <linux/numa.h>
33#include <asm/asm.h>
34#include <asm/cpu.h>
35#include <asm/mce.h>
36#include <asm/msr.h>
37#include <asm/pat.h>
38
39#ifdef CONFIG_X86_LOCAL_APIC
40#include <asm/uv/uv.h>
41#endif
42
43#include "cpu.h"
44
45/* all of these masks are initialized in setup_cpu_local_masks() */
46cpumask_var_t cpu_initialized_mask;
47cpumask_var_t cpu_callout_mask;
48cpumask_var_t cpu_callin_mask;
49
50/* representing cpus for which sibling maps can be computed */
51cpumask_var_t cpu_sibling_setup_mask;
52
53/* correctly size the local cpu masks */
54void __init setup_cpu_local_masks(void)
55{
56 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
57 alloc_bootmem_cpumask_var(&cpu_callin_mask);
58 alloc_bootmem_cpumask_var(&cpu_callout_mask);
59 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
60}
61
62static void __cpuinit default_init(struct cpuinfo_x86 *c)
63{
64#ifdef CONFIG_X86_64
65 cpu_detect_cache_sizes(c);
66#else
67 /* Not much we can do here... */
68 /* Check if at least it has cpuid */
69 if (c->cpuid_level == -1) {
70 /* No cpuid. It must be an ancient CPU */
71 if (c->x86 == 4)
72 strcpy(c->x86_model_id, "486");
73 else if (c->x86 == 3)
74 strcpy(c->x86_model_id, "386");
75 }
76#endif
77}
78
79static const struct cpu_dev __cpuinitconst default_cpu = {
80 .c_init = default_init,
81 .c_vendor = "Unknown",
82 .c_x86_vendor = X86_VENDOR_UNKNOWN,
83};
84
85static const struct cpu_dev *this_cpu __cpuinitdata = &default_cpu;
86
87DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
88#ifdef CONFIG_X86_64
89 /*
90 * We need valid kernel segments for data and code in long mode too
91 * IRET will check the segment types kkeil 2000/10/28
92 * Also sysret mandates a special GDT layout
93 *
94 * TLS descriptors are currently at a different place compared to i386.
95 * Hopefully nobody expects them at a fixed place (Wine?)
96 */
97 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
98 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
99 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
100 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
101 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
102 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
103#else
104 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
105 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
106 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
107 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
108 /*
109 * Segments used for calling PnP BIOS have byte granularity.
110 * They code segments and data segments have fixed 64k limits,
111 * the transfer segment sizes are set at run time.
112 */
113 /* 32-bit code */
114 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
115 /* 16-bit code */
116 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
117 /* 16-bit data */
118 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
119 /* 16-bit data */
120 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
121 /* 16-bit data */
122 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
123 /*
124 * The APM segments have byte granularity and their bases
125 * are set at run time. All have 64k limits.
126 */
127 /* 32-bit code */
128 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
129 /* 16-bit code */
130 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
131 /* data */
132 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
133
134 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
135 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
136 GDT_STACK_CANARY_INIT
137#endif
138} };
139EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
140
141static int __init x86_xsave_setup(char *s)
142{
143 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
144 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
145 return 1;
146}
147__setup("noxsave", x86_xsave_setup);
148
149static int __init x86_xsaveopt_setup(char *s)
150{
151 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
152 return 1;
153}
154__setup("noxsaveopt", x86_xsaveopt_setup);
155
156#ifdef CONFIG_X86_32
157static int cachesize_override __cpuinitdata = -1;
158static int disable_x86_serial_nr __cpuinitdata = 1;
159
160static int __init cachesize_setup(char *str)
161{
162 get_option(&str, &cachesize_override);
163 return 1;
164}
165__setup("cachesize=", cachesize_setup);
166
167static int __init x86_fxsr_setup(char *s)
168{
169 setup_clear_cpu_cap(X86_FEATURE_FXSR);
170 setup_clear_cpu_cap(X86_FEATURE_XMM);
171 return 1;
172}
173__setup("nofxsr", x86_fxsr_setup);
174
175static int __init x86_sep_setup(char *s)
176{
177 setup_clear_cpu_cap(X86_FEATURE_SEP);
178 return 1;
179}
180__setup("nosep", x86_sep_setup);
181
182/* Standard macro to see if a specific flag is changeable */
183static inline int flag_is_changeable_p(u32 flag)
184{
185 u32 f1, f2;
186
187 /*
188 * Cyrix and IDT cpus allow disabling of CPUID
189 * so the code below may return different results
190 * when it is executed before and after enabling
191 * the CPUID. Add "volatile" to not allow gcc to
192 * optimize the subsequent calls to this function.
193 */
194 asm volatile ("pushfl \n\t"
195 "pushfl \n\t"
196 "popl %0 \n\t"
197 "movl %0, %1 \n\t"
198 "xorl %2, %0 \n\t"
199 "pushl %0 \n\t"
200 "popfl \n\t"
201 "pushfl \n\t"
202 "popl %0 \n\t"
203 "popfl \n\t"
204
205 : "=&r" (f1), "=&r" (f2)
206 : "ir" (flag));
207
208 return ((f1^f2) & flag) != 0;
209}
210
211/* Probe for the CPUID instruction */
212static int __cpuinit have_cpuid_p(void)
213{
214 return flag_is_changeable_p(X86_EFLAGS_ID);
215}
216
217static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
218{
219 unsigned long lo, hi;
220
221 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
222 return;
223
224 /* Disable processor serial number: */
225
226 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
227 lo |= 0x200000;
228 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
229
230 printk(KERN_NOTICE "CPU serial number disabled.\n");
231 clear_cpu_cap(c, X86_FEATURE_PN);
232
233 /* Disabling the serial number may affect the cpuid level */
234 c->cpuid_level = cpuid_eax(0);
235}
236
237static int __init x86_serial_nr_setup(char *s)
238{
239 disable_x86_serial_nr = 0;
240 return 1;
241}
242__setup("serialnumber", x86_serial_nr_setup);
243#else
244static inline int flag_is_changeable_p(u32 flag)
245{
246 return 1;
247}
248/* Probe for the CPUID instruction */
249static inline int have_cpuid_p(void)
250{
251 return 1;
252}
253static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
254{
255}
256#endif
257
258static int disable_smep __cpuinitdata;
259static __init int setup_disable_smep(char *arg)
260{
261 disable_smep = 1;
262 return 1;
263}
264__setup("nosmep", setup_disable_smep);
265
266static __cpuinit void setup_smep(struct cpuinfo_x86 *c)
267{
268 if (cpu_has(c, X86_FEATURE_SMEP)) {
269 if (unlikely(disable_smep)) {
270 setup_clear_cpu_cap(X86_FEATURE_SMEP);
271 clear_in_cr4(X86_CR4_SMEP);
272 } else
273 set_in_cr4(X86_CR4_SMEP);
274 }
275}
276
277/*
278 * Some CPU features depend on higher CPUID levels, which may not always
279 * be available due to CPUID level capping or broken virtualization
280 * software. Add those features to this table to auto-disable them.
281 */
282struct cpuid_dependent_feature {
283 u32 feature;
284 u32 level;
285};
286
287static const struct cpuid_dependent_feature __cpuinitconst
288cpuid_dependent_features[] = {
289 { X86_FEATURE_MWAIT, 0x00000005 },
290 { X86_FEATURE_DCA, 0x00000009 },
291 { X86_FEATURE_XSAVE, 0x0000000d },
292 { 0, 0 }
293};
294
295static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
296{
297 const struct cpuid_dependent_feature *df;
298
299 for (df = cpuid_dependent_features; df->feature; df++) {
300
301 if (!cpu_has(c, df->feature))
302 continue;
303 /*
304 * Note: cpuid_level is set to -1 if unavailable, but
305 * extended_extended_level is set to 0 if unavailable
306 * and the legitimate extended levels are all negative
307 * when signed; hence the weird messing around with
308 * signs here...
309 */
310 if (!((s32)df->level < 0 ?
311 (u32)df->level > (u32)c->extended_cpuid_level :
312 (s32)df->level > (s32)c->cpuid_level))
313 continue;
314
315 clear_cpu_cap(c, df->feature);
316 if (!warn)
317 continue;
318
319 printk(KERN_WARNING
320 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n",
321 x86_cap_flags[df->feature], df->level);
322 }
323}
324
325/*
326 * Naming convention should be: <Name> [(<Codename>)]
327 * This table only is used unless init_<vendor>() below doesn't set it;
328 * in particular, if CPUID levels 0x80000002..4 are supported, this
329 * isn't used
330 */
331
332/* Look up CPU names by table lookup. */
333static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c)
334{
335 const struct cpu_model_info *info;
336
337 if (c->x86_model >= 16)
338 return NULL; /* Range check */
339
340 if (!this_cpu)
341 return NULL;
342
343 info = this_cpu->c_models;
344
345 while (info && info->family) {
346 if (info->family == c->x86)
347 return info->model_names[c->x86_model];
348 info++;
349 }
350 return NULL; /* Not found */
351}
352
353__u32 cpu_caps_cleared[NCAPINTS] __cpuinitdata;
354__u32 cpu_caps_set[NCAPINTS] __cpuinitdata;
355
356void load_percpu_segment(int cpu)
357{
358#ifdef CONFIG_X86_32
359 loadsegment(fs, __KERNEL_PERCPU);
360#else
361 loadsegment(gs, 0);
362 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
363#endif
364 load_stack_canary_segment();
365}
366
367/*
368 * Current gdt points %fs at the "master" per-cpu area: after this,
369 * it's on the real one.
370 */
371void switch_to_new_gdt(int cpu)
372{
373 struct desc_ptr gdt_descr;
374
375 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
376 gdt_descr.size = GDT_SIZE - 1;
377 load_gdt(&gdt_descr);
378 /* Reload the per-cpu base */
379
380 load_percpu_segment(cpu);
381}
382
383static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {};
384
385static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
386{
387 unsigned int *v;
388 char *p, *q;
389
390 if (c->extended_cpuid_level < 0x80000004)
391 return;
392
393 v = (unsigned int *)c->x86_model_id;
394 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
395 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
396 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
397 c->x86_model_id[48] = 0;
398
399 /*
400 * Intel chips right-justify this string for some dumb reason;
401 * undo that brain damage:
402 */
403 p = q = &c->x86_model_id[0];
404 while (*p == ' ')
405 p++;
406 if (p != q) {
407 while (*p)
408 *q++ = *p++;
409 while (q <= &c->x86_model_id[48])
410 *q++ = '\0'; /* Zero-pad the rest */
411 }
412}
413
414void __cpuinit cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
415{
416 unsigned int n, dummy, ebx, ecx, edx, l2size;
417
418 n = c->extended_cpuid_level;
419
420 if (n >= 0x80000005) {
421 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
422 c->x86_cache_size = (ecx>>24) + (edx>>24);
423#ifdef CONFIG_X86_64
424 /* On K8 L1 TLB is inclusive, so don't count it */
425 c->x86_tlbsize = 0;
426#endif
427 }
428
429 if (n < 0x80000006) /* Some chips just has a large L1. */
430 return;
431
432 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
433 l2size = ecx >> 16;
434
435#ifdef CONFIG_X86_64
436 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
437#else
438 /* do processor-specific cache resizing */
439 if (this_cpu->c_size_cache)
440 l2size = this_cpu->c_size_cache(c, l2size);
441
442 /* Allow user to override all this if necessary. */
443 if (cachesize_override != -1)
444 l2size = cachesize_override;
445
446 if (l2size == 0)
447 return; /* Again, no L2 cache is possible */
448#endif
449
450 c->x86_cache_size = l2size;
451}
452
453void __cpuinit detect_ht(struct cpuinfo_x86 *c)
454{
455#ifdef CONFIG_X86_HT
456 u32 eax, ebx, ecx, edx;
457 int index_msb, core_bits;
458 static bool printed;
459
460 if (!cpu_has(c, X86_FEATURE_HT))
461 return;
462
463 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
464 goto out;
465
466 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
467 return;
468
469 cpuid(1, &eax, &ebx, &ecx, &edx);
470
471 smp_num_siblings = (ebx & 0xff0000) >> 16;
472
473 if (smp_num_siblings == 1) {
474 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n");
475 goto out;
476 }
477
478 if (smp_num_siblings <= 1)
479 goto out;
480
481 index_msb = get_count_order(smp_num_siblings);
482 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
483
484 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
485
486 index_msb = get_count_order(smp_num_siblings);
487
488 core_bits = get_count_order(c->x86_max_cores);
489
490 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
491 ((1 << core_bits) - 1);
492
493out:
494 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
495 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
496 c->phys_proc_id);
497 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
498 c->cpu_core_id);
499 printed = 1;
500 }
501#endif
502}
503
504static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
505{
506 char *v = c->x86_vendor_id;
507 int i;
508
509 for (i = 0; i < X86_VENDOR_NUM; i++) {
510 if (!cpu_devs[i])
511 break;
512
513 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
514 (cpu_devs[i]->c_ident[1] &&
515 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
516
517 this_cpu = cpu_devs[i];
518 c->x86_vendor = this_cpu->c_x86_vendor;
519 return;
520 }
521 }
522
523 printk_once(KERN_ERR
524 "CPU: vendor_id '%s' unknown, using generic init.\n" \
525 "CPU: Your system may be unstable.\n", v);
526
527 c->x86_vendor = X86_VENDOR_UNKNOWN;
528 this_cpu = &default_cpu;
529}
530
531void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
532{
533 /* Get vendor name */
534 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
535 (unsigned int *)&c->x86_vendor_id[0],
536 (unsigned int *)&c->x86_vendor_id[8],
537 (unsigned int *)&c->x86_vendor_id[4]);
538
539 c->x86 = 4;
540 /* Intel-defined flags: level 0x00000001 */
541 if (c->cpuid_level >= 0x00000001) {
542 u32 junk, tfms, cap0, misc;
543
544 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
545 c->x86 = (tfms >> 8) & 0xf;
546 c->x86_model = (tfms >> 4) & 0xf;
547 c->x86_mask = tfms & 0xf;
548
549 if (c->x86 == 0xf)
550 c->x86 += (tfms >> 20) & 0xff;
551 if (c->x86 >= 0x6)
552 c->x86_model += ((tfms >> 16) & 0xf) << 4;
553
554 if (cap0 & (1<<19)) {
555 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
556 c->x86_cache_alignment = c->x86_clflush_size;
557 }
558 }
559}
560
561void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
562{
563 u32 tfms, xlvl;
564 u32 ebx;
565
566 /* Intel-defined flags: level 0x00000001 */
567 if (c->cpuid_level >= 0x00000001) {
568 u32 capability, excap;
569
570 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
571 c->x86_capability[0] = capability;
572 c->x86_capability[4] = excap;
573 }
574
575 /* Additional Intel-defined flags: level 0x00000007 */
576 if (c->cpuid_level >= 0x00000007) {
577 u32 eax, ebx, ecx, edx;
578
579 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
580
581 c->x86_capability[9] = ebx;
582 }
583
584 /* AMD-defined flags: level 0x80000001 */
585 xlvl = cpuid_eax(0x80000000);
586 c->extended_cpuid_level = xlvl;
587
588 if ((xlvl & 0xffff0000) == 0x80000000) {
589 if (xlvl >= 0x80000001) {
590 c->x86_capability[1] = cpuid_edx(0x80000001);
591 c->x86_capability[6] = cpuid_ecx(0x80000001);
592 }
593 }
594
595 if (c->extended_cpuid_level >= 0x80000008) {
596 u32 eax = cpuid_eax(0x80000008);
597
598 c->x86_virt_bits = (eax >> 8) & 0xff;
599 c->x86_phys_bits = eax & 0xff;
600 }
601#ifdef CONFIG_X86_32
602 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
603 c->x86_phys_bits = 36;
604#endif
605
606 if (c->extended_cpuid_level >= 0x80000007)
607 c->x86_power = cpuid_edx(0x80000007);
608
609 init_scattered_cpuid_features(c);
610}
611
612static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
613{
614#ifdef CONFIG_X86_32
615 int i;
616
617 /*
618 * First of all, decide if this is a 486 or higher
619 * It's a 486 if we can modify the AC flag
620 */
621 if (flag_is_changeable_p(X86_EFLAGS_AC))
622 c->x86 = 4;
623 else
624 c->x86 = 3;
625
626 for (i = 0; i < X86_VENDOR_NUM; i++)
627 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
628 c->x86_vendor_id[0] = 0;
629 cpu_devs[i]->c_identify(c);
630 if (c->x86_vendor_id[0]) {
631 get_cpu_vendor(c);
632 break;
633 }
634 }
635#endif
636}
637
638/*
639 * Do minimum CPU detection early.
640 * Fields really needed: vendor, cpuid_level, family, model, mask,
641 * cache alignment.
642 * The others are not touched to avoid unwanted side effects.
643 *
644 * WARNING: this function is only called on the BP. Don't add code here
645 * that is supposed to run on all CPUs.
646 */
647static void __init early_identify_cpu(struct cpuinfo_x86 *c)
648{
649#ifdef CONFIG_X86_64
650 c->x86_clflush_size = 64;
651 c->x86_phys_bits = 36;
652 c->x86_virt_bits = 48;
653#else
654 c->x86_clflush_size = 32;
655 c->x86_phys_bits = 32;
656 c->x86_virt_bits = 32;
657#endif
658 c->x86_cache_alignment = c->x86_clflush_size;
659
660 memset(&c->x86_capability, 0, sizeof c->x86_capability);
661 c->extended_cpuid_level = 0;
662
663 if (!have_cpuid_p())
664 identify_cpu_without_cpuid(c);
665
666 /* cyrix could have cpuid enabled via c_identify()*/
667 if (!have_cpuid_p())
668 return;
669
670 cpu_detect(c);
671
672 get_cpu_vendor(c);
673
674 get_cpu_cap(c);
675
676 if (this_cpu->c_early_init)
677 this_cpu->c_early_init(c);
678
679 c->cpu_index = 0;
680 filter_cpuid_features(c, false);
681
682 setup_smep(c);
683
684 if (this_cpu->c_bsp_init)
685 this_cpu->c_bsp_init(c);
686}
687
688void __init early_cpu_init(void)
689{
690 const struct cpu_dev *const *cdev;
691 int count = 0;
692
693#ifdef CONFIG_PROCESSOR_SELECT
694 printk(KERN_INFO "KERNEL supported cpus:\n");
695#endif
696
697 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
698 const struct cpu_dev *cpudev = *cdev;
699
700 if (count >= X86_VENDOR_NUM)
701 break;
702 cpu_devs[count] = cpudev;
703 count++;
704
705#ifdef CONFIG_PROCESSOR_SELECT
706 {
707 unsigned int j;
708
709 for (j = 0; j < 2; j++) {
710 if (!cpudev->c_ident[j])
711 continue;
712 printk(KERN_INFO " %s %s\n", cpudev->c_vendor,
713 cpudev->c_ident[j]);
714 }
715 }
716#endif
717 }
718 early_identify_cpu(&boot_cpu_data);
719}
720
721/*
722 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
723 * unfortunately, that's not true in practice because of early VIA
724 * chips and (more importantly) broken virtualizers that are not easy
725 * to detect. In the latter case it doesn't even *fail* reliably, so
726 * probing for it doesn't even work. Disable it completely on 32-bit
727 * unless we can find a reliable way to detect all the broken cases.
728 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
729 */
730static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
731{
732#ifdef CONFIG_X86_32
733 clear_cpu_cap(c, X86_FEATURE_NOPL);
734#else
735 set_cpu_cap(c, X86_FEATURE_NOPL);
736#endif
737}
738
739static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
740{
741 c->extended_cpuid_level = 0;
742
743 if (!have_cpuid_p())
744 identify_cpu_without_cpuid(c);
745
746 /* cyrix could have cpuid enabled via c_identify()*/
747 if (!have_cpuid_p())
748 return;
749
750 cpu_detect(c);
751
752 get_cpu_vendor(c);
753
754 get_cpu_cap(c);
755
756 if (c->cpuid_level >= 0x00000001) {
757 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
758#ifdef CONFIG_X86_32
759# ifdef CONFIG_X86_HT
760 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
761# else
762 c->apicid = c->initial_apicid;
763# endif
764#endif
765 c->phys_proc_id = c->initial_apicid;
766 }
767
768 setup_smep(c);
769
770 get_model_name(c); /* Default name */
771
772 detect_nopl(c);
773}
774
775/*
776 * This does the hard work of actually picking apart the CPU stuff...
777 */
778static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
779{
780 int i;
781
782 c->loops_per_jiffy = loops_per_jiffy;
783 c->x86_cache_size = -1;
784 c->x86_vendor = X86_VENDOR_UNKNOWN;
785 c->x86_model = c->x86_mask = 0; /* So far unknown... */
786 c->x86_vendor_id[0] = '\0'; /* Unset */
787 c->x86_model_id[0] = '\0'; /* Unset */
788 c->x86_max_cores = 1;
789 c->x86_coreid_bits = 0;
790#ifdef CONFIG_X86_64
791 c->x86_clflush_size = 64;
792 c->x86_phys_bits = 36;
793 c->x86_virt_bits = 48;
794#else
795 c->cpuid_level = -1; /* CPUID not detected */
796 c->x86_clflush_size = 32;
797 c->x86_phys_bits = 32;
798 c->x86_virt_bits = 32;
799#endif
800 c->x86_cache_alignment = c->x86_clflush_size;
801 memset(&c->x86_capability, 0, sizeof c->x86_capability);
802
803 generic_identify(c);
804
805 if (this_cpu->c_identify)
806 this_cpu->c_identify(c);
807
808 /* Clear/Set all flags overriden by options, after probe */
809 for (i = 0; i < NCAPINTS; i++) {
810 c->x86_capability[i] &= ~cpu_caps_cleared[i];
811 c->x86_capability[i] |= cpu_caps_set[i];
812 }
813
814#ifdef CONFIG_X86_64
815 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
816#endif
817
818 /*
819 * Vendor-specific initialization. In this section we
820 * canonicalize the feature flags, meaning if there are
821 * features a certain CPU supports which CPUID doesn't
822 * tell us, CPUID claiming incorrect flags, or other bugs,
823 * we handle them here.
824 *
825 * At the end of this section, c->x86_capability better
826 * indicate the features this CPU genuinely supports!
827 */
828 if (this_cpu->c_init)
829 this_cpu->c_init(c);
830
831 /* Disable the PN if appropriate */
832 squash_the_stupid_serial_number(c);
833
834 /*
835 * The vendor-specific functions might have changed features.
836 * Now we do "generic changes."
837 */
838
839 /* Filter out anything that depends on CPUID levels we don't have */
840 filter_cpuid_features(c, true);
841
842 /* If the model name is still unset, do table lookup. */
843 if (!c->x86_model_id[0]) {
844 const char *p;
845 p = table_lookup_model(c);
846 if (p)
847 strcpy(c->x86_model_id, p);
848 else
849 /* Last resort... */
850 sprintf(c->x86_model_id, "%02x/%02x",
851 c->x86, c->x86_model);
852 }
853
854#ifdef CONFIG_X86_64
855 detect_ht(c);
856#endif
857
858 init_hypervisor(c);
859 x86_init_rdrand(c);
860
861 /*
862 * Clear/Set all flags overriden by options, need do it
863 * before following smp all cpus cap AND.
864 */
865 for (i = 0; i < NCAPINTS; i++) {
866 c->x86_capability[i] &= ~cpu_caps_cleared[i];
867 c->x86_capability[i] |= cpu_caps_set[i];
868 }
869
870 /*
871 * On SMP, boot_cpu_data holds the common feature set between
872 * all CPUs; so make sure that we indicate which features are
873 * common between the CPUs. The first time this routine gets
874 * executed, c == &boot_cpu_data.
875 */
876 if (c != &boot_cpu_data) {
877 /* AND the already accumulated flags with these */
878 for (i = 0; i < NCAPINTS; i++)
879 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
880 }
881
882 /* Init Machine Check Exception if available. */
883 mcheck_cpu_init(c);
884
885 select_idle_routine(c);
886
887#ifdef CONFIG_NUMA
888 numa_add_cpu(smp_processor_id());
889#endif
890}
891
892#ifdef CONFIG_X86_64
893static void vgetcpu_set_mode(void)
894{
895 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
896 vgetcpu_mode = VGETCPU_RDTSCP;
897 else
898 vgetcpu_mode = VGETCPU_LSL;
899}
900#endif
901
902void __init identify_boot_cpu(void)
903{
904 identify_cpu(&boot_cpu_data);
905 init_amd_e400_c1e_mask();
906#ifdef CONFIG_X86_32
907 sysenter_setup();
908 enable_sep_cpu();
909#else
910 vgetcpu_set_mode();
911#endif
912}
913
914void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
915{
916 BUG_ON(c == &boot_cpu_data);
917 identify_cpu(c);
918#ifdef CONFIG_X86_32
919 enable_sep_cpu();
920#endif
921 mtrr_ap_init();
922}
923
924struct msr_range {
925 unsigned min;
926 unsigned max;
927};
928
929static const struct msr_range msr_range_array[] __cpuinitconst = {
930 { 0x00000000, 0x00000418},
931 { 0xc0000000, 0xc000040b},
932 { 0xc0010000, 0xc0010142},
933 { 0xc0011000, 0xc001103b},
934};
935
936static void __cpuinit print_cpu_msr(void)
937{
938 unsigned index_min, index_max;
939 unsigned index;
940 u64 val;
941 int i;
942
943 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
944 index_min = msr_range_array[i].min;
945 index_max = msr_range_array[i].max;
946
947 for (index = index_min; index < index_max; index++) {
948 if (rdmsrl_amd_safe(index, &val))
949 continue;
950 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
951 }
952 }
953}
954
955static int show_msr __cpuinitdata;
956
957static __init int setup_show_msr(char *arg)
958{
959 int num;
960
961 get_option(&arg, &num);
962
963 if (num > 0)
964 show_msr = num;
965 return 1;
966}
967__setup("show_msr=", setup_show_msr);
968
969static __init int setup_noclflush(char *arg)
970{
971 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
972 return 1;
973}
974__setup("noclflush", setup_noclflush);
975
976void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
977{
978 const char *vendor = NULL;
979
980 if (c->x86_vendor < X86_VENDOR_NUM) {
981 vendor = this_cpu->c_vendor;
982 } else {
983 if (c->cpuid_level >= 0)
984 vendor = c->x86_vendor_id;
985 }
986
987 if (vendor && !strstr(c->x86_model_id, vendor))
988 printk(KERN_CONT "%s ", vendor);
989
990 if (c->x86_model_id[0])
991 printk(KERN_CONT "%s", c->x86_model_id);
992 else
993 printk(KERN_CONT "%d86", c->x86);
994
995 if (c->x86_mask || c->cpuid_level >= 0)
996 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
997 else
998 printk(KERN_CONT "\n");
999
1000#ifdef CONFIG_SMP
1001 if (c->cpu_index < show_msr)
1002 print_cpu_msr();
1003#else
1004 if (show_msr)
1005 print_cpu_msr();
1006#endif
1007}
1008
1009static __init int setup_disablecpuid(char *arg)
1010{
1011 int bit;
1012
1013 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1014 setup_clear_cpu_cap(bit);
1015 else
1016 return 0;
1017
1018 return 1;
1019}
1020__setup("clearcpuid=", setup_disablecpuid);
1021
1022#ifdef CONFIG_X86_64
1023struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
1024struct desc_ptr nmi_idt_descr = { NR_VECTORS * 16 - 1,
1025 (unsigned long) nmi_idt_table };
1026
1027DEFINE_PER_CPU_FIRST(union irq_stack_union,
1028 irq_stack_union) __aligned(PAGE_SIZE);
1029
1030/*
1031 * The following four percpu variables are hot. Align current_task to
1032 * cacheline size such that all four fall in the same cacheline.
1033 */
1034DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1035 &init_task;
1036EXPORT_PER_CPU_SYMBOL(current_task);
1037
1038DEFINE_PER_CPU(unsigned long, kernel_stack) =
1039 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE;
1040EXPORT_PER_CPU_SYMBOL(kernel_stack);
1041
1042DEFINE_PER_CPU(char *, irq_stack_ptr) =
1043 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
1044
1045DEFINE_PER_CPU(unsigned int, irq_count) = -1;
1046
1047/*
1048 * Special IST stacks which the CPU switches to when it calls
1049 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1050 * limit), all of them are 4K, except the debug stack which
1051 * is 8K.
1052 */
1053static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1054 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1055 [DEBUG_STACK - 1] = DEBUG_STKSZ
1056};
1057
1058static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1059 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1060
1061/* May not be marked __init: used by software suspend */
1062void syscall_init(void)
1063{
1064 /*
1065 * LSTAR and STAR live in a bit strange symbiosis.
1066 * They both write to the same internal register. STAR allows to
1067 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1068 */
1069 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
1070 wrmsrl(MSR_LSTAR, system_call);
1071 wrmsrl(MSR_CSTAR, ignore_sysret);
1072
1073#ifdef CONFIG_IA32_EMULATION
1074 syscall32_cpu_init();
1075#endif
1076
1077 /* Flags to clear on syscall */
1078 wrmsrl(MSR_SYSCALL_MASK,
1079 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
1080}
1081
1082unsigned long kernel_eflags;
1083
1084/*
1085 * Copies of the original ist values from the tss are only accessed during
1086 * debugging, no special alignment required.
1087 */
1088DEFINE_PER_CPU(struct orig_ist, orig_ist);
1089
1090static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1091DEFINE_PER_CPU(int, debug_stack_usage);
1092
1093int is_debug_stack(unsigned long addr)
1094{
1095 return __get_cpu_var(debug_stack_usage) ||
1096 (addr <= __get_cpu_var(debug_stack_addr) &&
1097 addr > (__get_cpu_var(debug_stack_addr) - DEBUG_STKSZ));
1098}
1099
1100void debug_stack_set_zero(void)
1101{
1102 load_idt((const struct desc_ptr *)&nmi_idt_descr);
1103}
1104
1105void debug_stack_reset(void)
1106{
1107 load_idt((const struct desc_ptr *)&idt_descr);
1108}
1109
1110#else /* CONFIG_X86_64 */
1111
1112DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1113EXPORT_PER_CPU_SYMBOL(current_task);
1114
1115#ifdef CONFIG_CC_STACKPROTECTOR
1116DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1117#endif
1118
1119/* Make sure %fs and %gs are initialized properly in idle threads */
1120struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
1121{
1122 memset(regs, 0, sizeof(struct pt_regs));
1123 regs->fs = __KERNEL_PERCPU;
1124 regs->gs = __KERNEL_STACK_CANARY;
1125
1126 return regs;
1127}
1128#endif /* CONFIG_X86_64 */
1129
1130/*
1131 * Clear all 6 debug registers:
1132 */
1133static void clear_all_debug_regs(void)
1134{
1135 int i;
1136
1137 for (i = 0; i < 8; i++) {
1138 /* Ignore db4, db5 */
1139 if ((i == 4) || (i == 5))
1140 continue;
1141
1142 set_debugreg(0, i);
1143 }
1144}
1145
1146#ifdef CONFIG_KGDB
1147/*
1148 * Restore debug regs if using kgdbwait and you have a kernel debugger
1149 * connection established.
1150 */
1151static void dbg_restore_debug_regs(void)
1152{
1153 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1154 arch_kgdb_ops.correct_hw_break();
1155}
1156#else /* ! CONFIG_KGDB */
1157#define dbg_restore_debug_regs()
1158#endif /* ! CONFIG_KGDB */
1159
1160/*
1161 * Prints an error where the NUMA and configured core-number mismatch and the
1162 * platform didn't override this to fix it up
1163 */
1164void __cpuinit x86_default_fixup_cpu_id(struct cpuinfo_x86 *c, int node)
1165{
1166 pr_err("NUMA core number %d differs from configured core number %d\n", node, c->phys_proc_id);
1167}
1168
1169/*
1170 * cpu_init() initializes state that is per-CPU. Some data is already
1171 * initialized (naturally) in the bootstrap process, such as the GDT
1172 * and IDT. We reload them nevertheless, this function acts as a
1173 * 'CPU state barrier', nothing should get across.
1174 * A lot of state is already set up in PDA init for 64 bit
1175 */
1176#ifdef CONFIG_X86_64
1177
1178void __cpuinit cpu_init(void)
1179{
1180 struct orig_ist *oist;
1181 struct task_struct *me;
1182 struct tss_struct *t;
1183 unsigned long v;
1184 int cpu;
1185 int i;
1186
1187 cpu = stack_smp_processor_id();
1188 t = &per_cpu(init_tss, cpu);
1189 oist = &per_cpu(orig_ist, cpu);
1190
1191#ifdef CONFIG_NUMA
1192 if (cpu != 0 && percpu_read(numa_node) == 0 &&
1193 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1194 set_numa_node(early_cpu_to_node(cpu));
1195#endif
1196
1197 me = current;
1198
1199 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask))
1200 panic("CPU#%d already initialized!\n", cpu);
1201
1202 pr_debug("Initializing CPU#%d\n", cpu);
1203
1204 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1205
1206 /*
1207 * Initialize the per-CPU GDT with the boot GDT,
1208 * and set up the GDT descriptor:
1209 */
1210
1211 switch_to_new_gdt(cpu);
1212 loadsegment(fs, 0);
1213
1214 load_idt((const struct desc_ptr *)&idt_descr);
1215
1216 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1217 syscall_init();
1218
1219 wrmsrl(MSR_FS_BASE, 0);
1220 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1221 barrier();
1222
1223 x86_configure_nx();
1224 if (cpu != 0)
1225 enable_x2apic();
1226
1227 /*
1228 * set up and load the per-CPU TSS
1229 */
1230 if (!oist->ist[0]) {
1231 char *estacks = per_cpu(exception_stacks, cpu);
1232
1233 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1234 estacks += exception_stack_sizes[v];
1235 oist->ist[v] = t->x86_tss.ist[v] =
1236 (unsigned long)estacks;
1237 if (v == DEBUG_STACK-1)
1238 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1239 }
1240 }
1241
1242 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1243
1244 /*
1245 * <= is required because the CPU will access up to
1246 * 8 bits beyond the end of the IO permission bitmap.
1247 */
1248 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1249 t->io_bitmap[i] = ~0UL;
1250
1251 atomic_inc(&init_mm.mm_count);
1252 me->active_mm = &init_mm;
1253 BUG_ON(me->mm);
1254 enter_lazy_tlb(&init_mm, me);
1255
1256 load_sp0(t, &current->thread);
1257 set_tss_desc(cpu, t);
1258 load_TR_desc();
1259 load_LDT(&init_mm.context);
1260
1261 clear_all_debug_regs();
1262 dbg_restore_debug_regs();
1263
1264 fpu_init();
1265 xsave_init();
1266
1267 raw_local_save_flags(kernel_eflags);
1268
1269 if (is_uv_system())
1270 uv_cpu_init();
1271}
1272
1273#else
1274
1275void __cpuinit cpu_init(void)
1276{
1277 int cpu = smp_processor_id();
1278 struct task_struct *curr = current;
1279 struct tss_struct *t = &per_cpu(init_tss, cpu);
1280 struct thread_struct *thread = &curr->thread;
1281
1282 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) {
1283 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1284 for (;;)
1285 local_irq_enable();
1286 }
1287
1288 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1289
1290 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1291 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1292
1293 load_idt(&idt_descr);
1294 switch_to_new_gdt(cpu);
1295
1296 /*
1297 * Set up and load the per-CPU TSS and LDT
1298 */
1299 atomic_inc(&init_mm.mm_count);
1300 curr->active_mm = &init_mm;
1301 BUG_ON(curr->mm);
1302 enter_lazy_tlb(&init_mm, curr);
1303
1304 load_sp0(t, thread);
1305 set_tss_desc(cpu, t);
1306 load_TR_desc();
1307 load_LDT(&init_mm.context);
1308
1309 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1310
1311#ifdef CONFIG_DOUBLEFAULT
1312 /* Set up doublefault TSS pointer in the GDT */
1313 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1314#endif
1315
1316 clear_all_debug_regs();
1317 dbg_restore_debug_regs();
1318
1319 fpu_init();
1320 xsave_init();
1321}
1322#endif
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