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1 | #include <linux/init.h> | |
2 | #include <linux/kernel.h> | |
3 | #include <linux/sched.h> | |
4 | #include <linux/string.h> | |
5 | #include <linux/bootmem.h> | |
6 | #include <linux/bitops.h> | |
7 | #include <linux/module.h> | |
8 | #include <linux/kgdb.h> | |
9 | #include <linux/topology.h> | |
10 | #include <linux/delay.h> | |
11 | #include <linux/smp.h> | |
12 | #include <linux/percpu.h> | |
13 | #include <asm/i387.h> | |
14 | #include <asm/msr.h> | |
15 | #include <asm/io.h> | |
16 | #include <asm/linkage.h> | |
17 | #include <asm/mmu_context.h> | |
18 | #include <asm/mtrr.h> | |
19 | #include <asm/mce.h> | |
20 | #include <asm/pat.h> | |
21 | #include <asm/asm.h> | |
22 | #include <asm/numa.h> | |
23 | #include <asm/smp.h> | |
24 | #include <asm/cpu.h> | |
25 | #include <asm/cpumask.h> | |
26 | #ifdef CONFIG_X86_LOCAL_APIC | |
27 | #include <asm/mpspec.h> | |
28 | #include <asm/apic.h> | |
29 | #include <asm/genapic.h> | |
30 | #include <asm/genapic.h> | |
31 | #include <asm/uv/uv.h> | |
32 | #endif | |
33 | ||
34 | #include <asm/pgtable.h> | |
35 | #include <asm/processor.h> | |
36 | #include <asm/desc.h> | |
37 | #include <asm/atomic.h> | |
38 | #include <asm/proto.h> | |
39 | #include <asm/sections.h> | |
40 | #include <asm/setup.h> | |
41 | #include <asm/hypervisor.h> | |
42 | #include <asm/stackprotector.h> | |
43 | ||
44 | #include "cpu.h" | |
45 | ||
46 | #ifdef CONFIG_X86_64 | |
47 | ||
48 | /* all of these masks are initialized in setup_cpu_local_masks() */ | |
49 | cpumask_var_t cpu_callin_mask; | |
50 | cpumask_var_t cpu_callout_mask; | |
51 | cpumask_var_t cpu_initialized_mask; | |
52 | ||
53 | /* representing cpus for which sibling maps can be computed */ | |
54 | cpumask_var_t cpu_sibling_setup_mask; | |
55 | ||
56 | /* correctly size the local cpu masks */ | |
57 | void __init setup_cpu_local_masks(void) | |
58 | { | |
59 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
60 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
61 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
62 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
63 | } | |
64 | ||
65 | #else /* CONFIG_X86_32 */ | |
66 | ||
67 | cpumask_t cpu_callin_map; | |
68 | cpumask_t cpu_callout_map; | |
69 | cpumask_t cpu_initialized; | |
70 | cpumask_t cpu_sibling_setup_map; | |
71 | ||
72 | #endif /* CONFIG_X86_32 */ | |
73 | ||
74 | ||
75 | static struct cpu_dev *this_cpu __cpuinitdata; | |
76 | ||
77 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { | |
78 | #ifdef CONFIG_X86_64 | |
79 | /* | |
80 | * We need valid kernel segments for data and code in long mode too | |
81 | * IRET will check the segment types kkeil 2000/10/28 | |
82 | * Also sysret mandates a special GDT layout | |
83 | * | |
84 | * The TLS descriptors are currently at a different place compared to i386. | |
85 | * Hopefully nobody expects them at a fixed place (Wine?) | |
86 | */ | |
87 | [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, | |
88 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, | |
89 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, | |
90 | [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, | |
91 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, | |
92 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, | |
93 | #else | |
94 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, | |
95 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
96 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, | |
97 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, | |
98 | /* | |
99 | * Segments used for calling PnP BIOS have byte granularity. | |
100 | * They code segments and data segments have fixed 64k limits, | |
101 | * the transfer segment sizes are set at run time. | |
102 | */ | |
103 | /* 32-bit code */ | |
104 | [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, | |
105 | /* 16-bit code */ | |
106 | [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, | |
107 | /* 16-bit data */ | |
108 | [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, | |
109 | /* 16-bit data */ | |
110 | [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, | |
111 | /* 16-bit data */ | |
112 | [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, | |
113 | /* | |
114 | * The APM segments have byte granularity and their bases | |
115 | * are set at run time. All have 64k limits. | |
116 | */ | |
117 | /* 32-bit code */ | |
118 | [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, | |
119 | /* 16-bit code */ | |
120 | [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, | |
121 | /* data */ | |
122 | [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, | |
123 | ||
124 | [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, | |
125 | [GDT_ENTRY_PERCPU] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
126 | GDT_STACK_CANARY_INIT | |
127 | #endif | |
128 | } }; | |
129 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); | |
130 | ||
131 | #ifdef CONFIG_X86_32 | |
132 | static int cachesize_override __cpuinitdata = -1; | |
133 | static int disable_x86_serial_nr __cpuinitdata = 1; | |
134 | ||
135 | static int __init cachesize_setup(char *str) | |
136 | { | |
137 | get_option(&str, &cachesize_override); | |
138 | return 1; | |
139 | } | |
140 | __setup("cachesize=", cachesize_setup); | |
141 | ||
142 | static int __init x86_fxsr_setup(char *s) | |
143 | { | |
144 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
145 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
146 | return 1; | |
147 | } | |
148 | __setup("nofxsr", x86_fxsr_setup); | |
149 | ||
150 | static int __init x86_sep_setup(char *s) | |
151 | { | |
152 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
153 | return 1; | |
154 | } | |
155 | __setup("nosep", x86_sep_setup); | |
156 | ||
157 | /* Standard macro to see if a specific flag is changeable */ | |
158 | static inline int flag_is_changeable_p(u32 flag) | |
159 | { | |
160 | u32 f1, f2; | |
161 | ||
162 | /* | |
163 | * Cyrix and IDT cpus allow disabling of CPUID | |
164 | * so the code below may return different results | |
165 | * when it is executed before and after enabling | |
166 | * the CPUID. Add "volatile" to not allow gcc to | |
167 | * optimize the subsequent calls to this function. | |
168 | */ | |
169 | asm volatile ("pushfl\n\t" | |
170 | "pushfl\n\t" | |
171 | "popl %0\n\t" | |
172 | "movl %0,%1\n\t" | |
173 | "xorl %2,%0\n\t" | |
174 | "pushl %0\n\t" | |
175 | "popfl\n\t" | |
176 | "pushfl\n\t" | |
177 | "popl %0\n\t" | |
178 | "popfl\n\t" | |
179 | : "=&r" (f1), "=&r" (f2) | |
180 | : "ir" (flag)); | |
181 | ||
182 | return ((f1^f2) & flag) != 0; | |
183 | } | |
184 | ||
185 | /* Probe for the CPUID instruction */ | |
186 | static int __cpuinit have_cpuid_p(void) | |
187 | { | |
188 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
189 | } | |
190 | ||
191 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
192 | { | |
193 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { | |
194 | /* Disable processor serial number */ | |
195 | unsigned long lo, hi; | |
196 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
197 | lo |= 0x200000; | |
198 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
199 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
200 | clear_cpu_cap(c, X86_FEATURE_PN); | |
201 | ||
202 | /* Disabling the serial number may affect the cpuid level */ | |
203 | c->cpuid_level = cpuid_eax(0); | |
204 | } | |
205 | } | |
206 | ||
207 | static int __init x86_serial_nr_setup(char *s) | |
208 | { | |
209 | disable_x86_serial_nr = 0; | |
210 | return 1; | |
211 | } | |
212 | __setup("serialnumber", x86_serial_nr_setup); | |
213 | #else | |
214 | static inline int flag_is_changeable_p(u32 flag) | |
215 | { | |
216 | return 1; | |
217 | } | |
218 | /* Probe for the CPUID instruction */ | |
219 | static inline int have_cpuid_p(void) | |
220 | { | |
221 | return 1; | |
222 | } | |
223 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
224 | { | |
225 | } | |
226 | #endif | |
227 | ||
228 | /* | |
229 | * Some CPU features depend on higher CPUID levels, which may not always | |
230 | * be available due to CPUID level capping or broken virtualization | |
231 | * software. Add those features to this table to auto-disable them. | |
232 | */ | |
233 | struct cpuid_dependent_feature { | |
234 | u32 feature; | |
235 | u32 level; | |
236 | }; | |
237 | static const struct cpuid_dependent_feature __cpuinitconst | |
238 | cpuid_dependent_features[] = { | |
239 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
240 | { X86_FEATURE_DCA, 0x00000009 }, | |
241 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
242 | { 0, 0 } | |
243 | }; | |
244 | ||
245 | static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) | |
246 | { | |
247 | const struct cpuid_dependent_feature *df; | |
248 | for (df = cpuid_dependent_features; df->feature; df++) { | |
249 | /* | |
250 | * Note: cpuid_level is set to -1 if unavailable, but | |
251 | * extended_extended_level is set to 0 if unavailable | |
252 | * and the legitimate extended levels are all negative | |
253 | * when signed; hence the weird messing around with | |
254 | * signs here... | |
255 | */ | |
256 | if (cpu_has(c, df->feature) && | |
257 | ((s32)df->level < 0 ? | |
258 | (u32)df->level > (u32)c->extended_cpuid_level : | |
259 | (s32)df->level > (s32)c->cpuid_level)) { | |
260 | clear_cpu_cap(c, df->feature); | |
261 | if (warn) | |
262 | printk(KERN_WARNING | |
263 | "CPU: CPU feature %s disabled " | |
264 | "due to lack of CPUID level 0x%x\n", | |
265 | x86_cap_flags[df->feature], | |
266 | df->level); | |
267 | } | |
268 | } | |
269 | } | |
270 | ||
271 | /* | |
272 | * Naming convention should be: <Name> [(<Codename>)] | |
273 | * This table only is used unless init_<vendor>() below doesn't set it; | |
274 | * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used | |
275 | * | |
276 | */ | |
277 | ||
278 | /* Look up CPU names by table lookup. */ | |
279 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) | |
280 | { | |
281 | struct cpu_model_info *info; | |
282 | ||
283 | if (c->x86_model >= 16) | |
284 | return NULL; /* Range check */ | |
285 | ||
286 | if (!this_cpu) | |
287 | return NULL; | |
288 | ||
289 | info = this_cpu->c_models; | |
290 | ||
291 | while (info && info->family) { | |
292 | if (info->family == c->x86) | |
293 | return info->model_names[c->x86_model]; | |
294 | info++; | |
295 | } | |
296 | return NULL; /* Not found */ | |
297 | } | |
298 | ||
299 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; | |
300 | ||
301 | void load_percpu_segment(int cpu) | |
302 | { | |
303 | #ifdef CONFIG_X86_32 | |
304 | loadsegment(fs, __KERNEL_PERCPU); | |
305 | #else | |
306 | loadsegment(gs, 0); | |
307 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); | |
308 | #endif | |
309 | load_stack_canary_segment(); | |
310 | } | |
311 | ||
312 | /* Current gdt points %fs at the "master" per-cpu area: after this, | |
313 | * it's on the real one. */ | |
314 | void switch_to_new_gdt(int cpu) | |
315 | { | |
316 | struct desc_ptr gdt_descr; | |
317 | ||
318 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); | |
319 | gdt_descr.size = GDT_SIZE - 1; | |
320 | load_gdt(&gdt_descr); | |
321 | /* Reload the per-cpu base */ | |
322 | ||
323 | load_percpu_segment(cpu); | |
324 | } | |
325 | ||
326 | static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; | |
327 | ||
328 | static void __cpuinit default_init(struct cpuinfo_x86 *c) | |
329 | { | |
330 | #ifdef CONFIG_X86_64 | |
331 | display_cacheinfo(c); | |
332 | #else | |
333 | /* Not much we can do here... */ | |
334 | /* Check if at least it has cpuid */ | |
335 | if (c->cpuid_level == -1) { | |
336 | /* No cpuid. It must be an ancient CPU */ | |
337 | if (c->x86 == 4) | |
338 | strcpy(c->x86_model_id, "486"); | |
339 | else if (c->x86 == 3) | |
340 | strcpy(c->x86_model_id, "386"); | |
341 | } | |
342 | #endif | |
343 | } | |
344 | ||
345 | static struct cpu_dev __cpuinitdata default_cpu = { | |
346 | .c_init = default_init, | |
347 | .c_vendor = "Unknown", | |
348 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
349 | }; | |
350 | ||
351 | static void __cpuinit get_model_name(struct cpuinfo_x86 *c) | |
352 | { | |
353 | unsigned int *v; | |
354 | char *p, *q; | |
355 | ||
356 | if (c->extended_cpuid_level < 0x80000004) | |
357 | return; | |
358 | ||
359 | v = (unsigned int *) c->x86_model_id; | |
360 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
361 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
362 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
363 | c->x86_model_id[48] = 0; | |
364 | ||
365 | /* Intel chips right-justify this string for some dumb reason; | |
366 | undo that brain damage */ | |
367 | p = q = &c->x86_model_id[0]; | |
368 | while (*p == ' ') | |
369 | p++; | |
370 | if (p != q) { | |
371 | while (*p) | |
372 | *q++ = *p++; | |
373 | while (q <= &c->x86_model_id[48]) | |
374 | *q++ = '\0'; /* Zero-pad the rest */ | |
375 | } | |
376 | } | |
377 | ||
378 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) | |
379 | { | |
380 | unsigned int n, dummy, ebx, ecx, edx, l2size; | |
381 | ||
382 | n = c->extended_cpuid_level; | |
383 | ||
384 | if (n >= 0x80000005) { | |
385 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); | |
386 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", | |
387 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); | |
388 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
389 | #ifdef CONFIG_X86_64 | |
390 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
391 | c->x86_tlbsize = 0; | |
392 | #endif | |
393 | } | |
394 | ||
395 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
396 | return; | |
397 | ||
398 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); | |
399 | l2size = ecx >> 16; | |
400 | ||
401 | #ifdef CONFIG_X86_64 | |
402 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
403 | #else | |
404 | /* do processor-specific cache resizing */ | |
405 | if (this_cpu->c_size_cache) | |
406 | l2size = this_cpu->c_size_cache(c, l2size); | |
407 | ||
408 | /* Allow user to override all this if necessary. */ | |
409 | if (cachesize_override != -1) | |
410 | l2size = cachesize_override; | |
411 | ||
412 | if (l2size == 0) | |
413 | return; /* Again, no L2 cache is possible */ | |
414 | #endif | |
415 | ||
416 | c->x86_cache_size = l2size; | |
417 | ||
418 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
419 | l2size, ecx & 0xFF); | |
420 | } | |
421 | ||
422 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) | |
423 | { | |
424 | #ifdef CONFIG_X86_HT | |
425 | u32 eax, ebx, ecx, edx; | |
426 | int index_msb, core_bits; | |
427 | ||
428 | if (!cpu_has(c, X86_FEATURE_HT)) | |
429 | return; | |
430 | ||
431 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) | |
432 | goto out; | |
433 | ||
434 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) | |
435 | return; | |
436 | ||
437 | cpuid(1, &eax, &ebx, &ecx, &edx); | |
438 | ||
439 | smp_num_siblings = (ebx & 0xff0000) >> 16; | |
440 | ||
441 | if (smp_num_siblings == 1) { | |
442 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
443 | } else if (smp_num_siblings > 1) { | |
444 | ||
445 | if (smp_num_siblings > nr_cpu_ids) { | |
446 | printk(KERN_WARNING "CPU: Unsupported number of siblings %d", | |
447 | smp_num_siblings); | |
448 | smp_num_siblings = 1; | |
449 | return; | |
450 | } | |
451 | ||
452 | index_msb = get_count_order(smp_num_siblings); | |
453 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
454 | ||
455 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
456 | ||
457 | index_msb = get_count_order(smp_num_siblings); | |
458 | ||
459 | core_bits = get_count_order(c->x86_max_cores); | |
460 | ||
461 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & | |
462 | ((1 << core_bits) - 1); | |
463 | } | |
464 | ||
465 | out: | |
466 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
467 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
468 | c->phys_proc_id); | |
469 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
470 | c->cpu_core_id); | |
471 | } | |
472 | #endif | |
473 | } | |
474 | ||
475 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) | |
476 | { | |
477 | char *v = c->x86_vendor_id; | |
478 | int i; | |
479 | static int printed; | |
480 | ||
481 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
482 | if (!cpu_devs[i]) | |
483 | break; | |
484 | ||
485 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
486 | (cpu_devs[i]->c_ident[1] && | |
487 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
488 | this_cpu = cpu_devs[i]; | |
489 | c->x86_vendor = this_cpu->c_x86_vendor; | |
490 | return; | |
491 | } | |
492 | } | |
493 | ||
494 | if (!printed) { | |
495 | printed++; | |
496 | printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v); | |
497 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); | |
498 | } | |
499 | ||
500 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
501 | this_cpu = &default_cpu; | |
502 | } | |
503 | ||
504 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) | |
505 | { | |
506 | /* Get vendor name */ | |
507 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, | |
508 | (unsigned int *)&c->x86_vendor_id[0], | |
509 | (unsigned int *)&c->x86_vendor_id[8], | |
510 | (unsigned int *)&c->x86_vendor_id[4]); | |
511 | ||
512 | c->x86 = 4; | |
513 | /* Intel-defined flags: level 0x00000001 */ | |
514 | if (c->cpuid_level >= 0x00000001) { | |
515 | u32 junk, tfms, cap0, misc; | |
516 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
517 | c->x86 = (tfms >> 8) & 0xf; | |
518 | c->x86_model = (tfms >> 4) & 0xf; | |
519 | c->x86_mask = tfms & 0xf; | |
520 | if (c->x86 == 0xf) | |
521 | c->x86 += (tfms >> 20) & 0xff; | |
522 | if (c->x86 >= 0x6) | |
523 | c->x86_model += ((tfms >> 16) & 0xf) << 4; | |
524 | if (cap0 & (1<<19)) { | |
525 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; | |
526 | c->x86_cache_alignment = c->x86_clflush_size; | |
527 | } | |
528 | } | |
529 | } | |
530 | ||
531 | static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) | |
532 | { | |
533 | u32 tfms, xlvl; | |
534 | u32 ebx; | |
535 | ||
536 | /* Intel-defined flags: level 0x00000001 */ | |
537 | if (c->cpuid_level >= 0x00000001) { | |
538 | u32 capability, excap; | |
539 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
540 | c->x86_capability[0] = capability; | |
541 | c->x86_capability[4] = excap; | |
542 | } | |
543 | ||
544 | /* AMD-defined flags: level 0x80000001 */ | |
545 | xlvl = cpuid_eax(0x80000000); | |
546 | c->extended_cpuid_level = xlvl; | |
547 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
548 | if (xlvl >= 0x80000001) { | |
549 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
550 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
551 | } | |
552 | } | |
553 | ||
554 | #ifdef CONFIG_X86_64 | |
555 | if (c->extended_cpuid_level >= 0x80000008) { | |
556 | u32 eax = cpuid_eax(0x80000008); | |
557 | ||
558 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
559 | c->x86_phys_bits = eax & 0xff; | |
560 | } | |
561 | #endif | |
562 | ||
563 | if (c->extended_cpuid_level >= 0x80000007) | |
564 | c->x86_power = cpuid_edx(0x80000007); | |
565 | ||
566 | } | |
567 | ||
568 | static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) | |
569 | { | |
570 | #ifdef CONFIG_X86_32 | |
571 | int i; | |
572 | ||
573 | /* | |
574 | * First of all, decide if this is a 486 or higher | |
575 | * It's a 486 if we can modify the AC flag | |
576 | */ | |
577 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
578 | c->x86 = 4; | |
579 | else | |
580 | c->x86 = 3; | |
581 | ||
582 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
583 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
584 | c->x86_vendor_id[0] = 0; | |
585 | cpu_devs[i]->c_identify(c); | |
586 | if (c->x86_vendor_id[0]) { | |
587 | get_cpu_vendor(c); | |
588 | break; | |
589 | } | |
590 | } | |
591 | #endif | |
592 | } | |
593 | ||
594 | /* | |
595 | * Do minimum CPU detection early. | |
596 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
597 | * cache alignment. | |
598 | * The others are not touched to avoid unwanted side effects. | |
599 | * | |
600 | * WARNING: this function is only called on the BP. Don't add code here | |
601 | * that is supposed to run on all CPUs. | |
602 | */ | |
603 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) | |
604 | { | |
605 | #ifdef CONFIG_X86_64 | |
606 | c->x86_clflush_size = 64; | |
607 | #else | |
608 | c->x86_clflush_size = 32; | |
609 | #endif | |
610 | c->x86_cache_alignment = c->x86_clflush_size; | |
611 | ||
612 | memset(&c->x86_capability, 0, sizeof c->x86_capability); | |
613 | c->extended_cpuid_level = 0; | |
614 | ||
615 | if (!have_cpuid_p()) | |
616 | identify_cpu_without_cpuid(c); | |
617 | ||
618 | /* cyrix could have cpuid enabled via c_identify()*/ | |
619 | if (!have_cpuid_p()) | |
620 | return; | |
621 | ||
622 | cpu_detect(c); | |
623 | ||
624 | get_cpu_vendor(c); | |
625 | ||
626 | get_cpu_cap(c); | |
627 | ||
628 | if (this_cpu->c_early_init) | |
629 | this_cpu->c_early_init(c); | |
630 | ||
631 | #ifdef CONFIG_SMP | |
632 | c->cpu_index = boot_cpu_id; | |
633 | #endif | |
634 | filter_cpuid_features(c, false); | |
635 | } | |
636 | ||
637 | void __init early_cpu_init(void) | |
638 | { | |
639 | struct cpu_dev **cdev; | |
640 | int count = 0; | |
641 | ||
642 | printk("KERNEL supported cpus:\n"); | |
643 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { | |
644 | struct cpu_dev *cpudev = *cdev; | |
645 | unsigned int j; | |
646 | ||
647 | if (count >= X86_VENDOR_NUM) | |
648 | break; | |
649 | cpu_devs[count] = cpudev; | |
650 | count++; | |
651 | ||
652 | for (j = 0; j < 2; j++) { | |
653 | if (!cpudev->c_ident[j]) | |
654 | continue; | |
655 | printk(" %s %s\n", cpudev->c_vendor, | |
656 | cpudev->c_ident[j]); | |
657 | } | |
658 | } | |
659 | ||
660 | early_identify_cpu(&boot_cpu_data); | |
661 | } | |
662 | ||
663 | /* | |
664 | * The NOPL instruction is supposed to exist on all CPUs with | |
665 | * family >= 6; unfortunately, that's not true in practice because | |
666 | * of early VIA chips and (more importantly) broken virtualizers that | |
667 | * are not easy to detect. In the latter case it doesn't even *fail* | |
668 | * reliably, so probing for it doesn't even work. Disable it completely | |
669 | * unless we can find a reliable way to detect all the broken cases. | |
670 | */ | |
671 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
672 | { | |
673 | clear_cpu_cap(c, X86_FEATURE_NOPL); | |
674 | } | |
675 | ||
676 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) | |
677 | { | |
678 | c->extended_cpuid_level = 0; | |
679 | ||
680 | if (!have_cpuid_p()) | |
681 | identify_cpu_without_cpuid(c); | |
682 | ||
683 | /* cyrix could have cpuid enabled via c_identify()*/ | |
684 | if (!have_cpuid_p()) | |
685 | return; | |
686 | ||
687 | cpu_detect(c); | |
688 | ||
689 | get_cpu_vendor(c); | |
690 | ||
691 | get_cpu_cap(c); | |
692 | ||
693 | if (c->cpuid_level >= 0x00000001) { | |
694 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
695 | #ifdef CONFIG_X86_32 | |
696 | # ifdef CONFIG_X86_HT | |
697 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); | |
698 | # else | |
699 | c->apicid = c->initial_apicid; | |
700 | # endif | |
701 | #endif | |
702 | ||
703 | #ifdef CONFIG_X86_HT | |
704 | c->phys_proc_id = c->initial_apicid; | |
705 | #endif | |
706 | } | |
707 | ||
708 | get_model_name(c); /* Default name */ | |
709 | ||
710 | init_scattered_cpuid_features(c); | |
711 | detect_nopl(c); | |
712 | } | |
713 | ||
714 | /* | |
715 | * This does the hard work of actually picking apart the CPU stuff... | |
716 | */ | |
717 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) | |
718 | { | |
719 | int i; | |
720 | ||
721 | c->loops_per_jiffy = loops_per_jiffy; | |
722 | c->x86_cache_size = -1; | |
723 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
724 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ | |
725 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
726 | c->x86_model_id[0] = '\0'; /* Unset */ | |
727 | c->x86_max_cores = 1; | |
728 | c->x86_coreid_bits = 0; | |
729 | #ifdef CONFIG_X86_64 | |
730 | c->x86_clflush_size = 64; | |
731 | #else | |
732 | c->cpuid_level = -1; /* CPUID not detected */ | |
733 | c->x86_clflush_size = 32; | |
734 | #endif | |
735 | c->x86_cache_alignment = c->x86_clflush_size; | |
736 | memset(&c->x86_capability, 0, sizeof c->x86_capability); | |
737 | ||
738 | generic_identify(c); | |
739 | ||
740 | if (this_cpu->c_identify) | |
741 | this_cpu->c_identify(c); | |
742 | ||
743 | #ifdef CONFIG_X86_64 | |
744 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); | |
745 | #endif | |
746 | ||
747 | /* | |
748 | * Vendor-specific initialization. In this section we | |
749 | * canonicalize the feature flags, meaning if there are | |
750 | * features a certain CPU supports which CPUID doesn't | |
751 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
752 | * we handle them here. | |
753 | * | |
754 | * At the end of this section, c->x86_capability better | |
755 | * indicate the features this CPU genuinely supports! | |
756 | */ | |
757 | if (this_cpu->c_init) | |
758 | this_cpu->c_init(c); | |
759 | ||
760 | /* Disable the PN if appropriate */ | |
761 | squash_the_stupid_serial_number(c); | |
762 | ||
763 | /* | |
764 | * The vendor-specific functions might have changed features. Now | |
765 | * we do "generic changes." | |
766 | */ | |
767 | ||
768 | /* Filter out anything that depends on CPUID levels we don't have */ | |
769 | filter_cpuid_features(c, true); | |
770 | ||
771 | /* If the model name is still unset, do table lookup. */ | |
772 | if (!c->x86_model_id[0]) { | |
773 | char *p; | |
774 | p = table_lookup_model(c); | |
775 | if (p) | |
776 | strcpy(c->x86_model_id, p); | |
777 | else | |
778 | /* Last resort... */ | |
779 | sprintf(c->x86_model_id, "%02x/%02x", | |
780 | c->x86, c->x86_model); | |
781 | } | |
782 | ||
783 | #ifdef CONFIG_X86_64 | |
784 | detect_ht(c); | |
785 | #endif | |
786 | ||
787 | init_hypervisor(c); | |
788 | /* | |
789 | * On SMP, boot_cpu_data holds the common feature set between | |
790 | * all CPUs; so make sure that we indicate which features are | |
791 | * common between the CPUs. The first time this routine gets | |
792 | * executed, c == &boot_cpu_data. | |
793 | */ | |
794 | if (c != &boot_cpu_data) { | |
795 | /* AND the already accumulated flags with these */ | |
796 | for (i = 0; i < NCAPINTS; i++) | |
797 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; | |
798 | } | |
799 | ||
800 | /* Clear all flags overriden by options */ | |
801 | for (i = 0; i < NCAPINTS; i++) | |
802 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; | |
803 | ||
804 | #ifdef CONFIG_X86_MCE | |
805 | /* Init Machine Check Exception if available. */ | |
806 | mcheck_init(c); | |
807 | #endif | |
808 | ||
809 | select_idle_routine(c); | |
810 | ||
811 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
812 | numa_add_cpu(smp_processor_id()); | |
813 | #endif | |
814 | } | |
815 | ||
816 | #ifdef CONFIG_X86_64 | |
817 | static void vgetcpu_set_mode(void) | |
818 | { | |
819 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | |
820 | vgetcpu_mode = VGETCPU_RDTSCP; | |
821 | else | |
822 | vgetcpu_mode = VGETCPU_LSL; | |
823 | } | |
824 | #endif | |
825 | ||
826 | void __init identify_boot_cpu(void) | |
827 | { | |
828 | identify_cpu(&boot_cpu_data); | |
829 | #ifdef CONFIG_X86_32 | |
830 | sysenter_setup(); | |
831 | enable_sep_cpu(); | |
832 | #else | |
833 | vgetcpu_set_mode(); | |
834 | #endif | |
835 | } | |
836 | ||
837 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) | |
838 | { | |
839 | BUG_ON(c == &boot_cpu_data); | |
840 | identify_cpu(c); | |
841 | #ifdef CONFIG_X86_32 | |
842 | enable_sep_cpu(); | |
843 | #endif | |
844 | mtrr_ap_init(); | |
845 | } | |
846 | ||
847 | struct msr_range { | |
848 | unsigned min; | |
849 | unsigned max; | |
850 | }; | |
851 | ||
852 | static struct msr_range msr_range_array[] __cpuinitdata = { | |
853 | { 0x00000000, 0x00000418}, | |
854 | { 0xc0000000, 0xc000040b}, | |
855 | { 0xc0010000, 0xc0010142}, | |
856 | { 0xc0011000, 0xc001103b}, | |
857 | }; | |
858 | ||
859 | static void __cpuinit print_cpu_msr(void) | |
860 | { | |
861 | unsigned index; | |
862 | u64 val; | |
863 | int i; | |
864 | unsigned index_min, index_max; | |
865 | ||
866 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
867 | index_min = msr_range_array[i].min; | |
868 | index_max = msr_range_array[i].max; | |
869 | for (index = index_min; index < index_max; index++) { | |
870 | if (rdmsrl_amd_safe(index, &val)) | |
871 | continue; | |
872 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
873 | } | |
874 | } | |
875 | } | |
876 | ||
877 | static int show_msr __cpuinitdata; | |
878 | static __init int setup_show_msr(char *arg) | |
879 | { | |
880 | int num; | |
881 | ||
882 | get_option(&arg, &num); | |
883 | ||
884 | if (num > 0) | |
885 | show_msr = num; | |
886 | return 1; | |
887 | } | |
888 | __setup("show_msr=", setup_show_msr); | |
889 | ||
890 | static __init int setup_noclflush(char *arg) | |
891 | { | |
892 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
893 | return 1; | |
894 | } | |
895 | __setup("noclflush", setup_noclflush); | |
896 | ||
897 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) | |
898 | { | |
899 | char *vendor = NULL; | |
900 | ||
901 | if (c->x86_vendor < X86_VENDOR_NUM) | |
902 | vendor = this_cpu->c_vendor; | |
903 | else if (c->cpuid_level >= 0) | |
904 | vendor = c->x86_vendor_id; | |
905 | ||
906 | if (vendor && !strstr(c->x86_model_id, vendor)) | |
907 | printk(KERN_CONT "%s ", vendor); | |
908 | ||
909 | if (c->x86_model_id[0]) | |
910 | printk(KERN_CONT "%s", c->x86_model_id); | |
911 | else | |
912 | printk(KERN_CONT "%d86", c->x86); | |
913 | ||
914 | if (c->x86_mask || c->cpuid_level >= 0) | |
915 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); | |
916 | else | |
917 | printk(KERN_CONT "\n"); | |
918 | ||
919 | #ifdef CONFIG_SMP | |
920 | if (c->cpu_index < show_msr) | |
921 | print_cpu_msr(); | |
922 | #else | |
923 | if (show_msr) | |
924 | print_cpu_msr(); | |
925 | #endif | |
926 | } | |
927 | ||
928 | static __init int setup_disablecpuid(char *arg) | |
929 | { | |
930 | int bit; | |
931 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
932 | setup_clear_cpu_cap(bit); | |
933 | else | |
934 | return 0; | |
935 | return 1; | |
936 | } | |
937 | __setup("clearcpuid=", setup_disablecpuid); | |
938 | ||
939 | #ifdef CONFIG_X86_64 | |
940 | struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; | |
941 | ||
942 | DEFINE_PER_CPU_FIRST(union irq_stack_union, | |
943 | irq_stack_union) __aligned(PAGE_SIZE); | |
944 | DEFINE_PER_CPU(char *, irq_stack_ptr) = | |
945 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; | |
946 | ||
947 | DEFINE_PER_CPU(unsigned long, kernel_stack) = | |
948 | (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; | |
949 | EXPORT_PER_CPU_SYMBOL(kernel_stack); | |
950 | ||
951 | DEFINE_PER_CPU(unsigned int, irq_count) = -1; | |
952 | ||
953 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks | |
954 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]) | |
955 | __aligned(PAGE_SIZE); | |
956 | ||
957 | extern asmlinkage void ignore_sysret(void); | |
958 | ||
959 | /* May not be marked __init: used by software suspend */ | |
960 | void syscall_init(void) | |
961 | { | |
962 | /* | |
963 | * LSTAR and STAR live in a bit strange symbiosis. | |
964 | * They both write to the same internal register. STAR allows to | |
965 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
966 | */ | |
967 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
968 | wrmsrl(MSR_LSTAR, system_call); | |
969 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
970 | ||
971 | #ifdef CONFIG_IA32_EMULATION | |
972 | syscall32_cpu_init(); | |
973 | #endif | |
974 | ||
975 | /* Flags to clear on syscall */ | |
976 | wrmsrl(MSR_SYSCALL_MASK, | |
977 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
978 | } | |
979 | ||
980 | unsigned long kernel_eflags; | |
981 | ||
982 | /* | |
983 | * Copies of the original ist values from the tss are only accessed during | |
984 | * debugging, no special alignment required. | |
985 | */ | |
986 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
987 | ||
988 | #else /* x86_64 */ | |
989 | ||
990 | #ifdef CONFIG_CC_STACKPROTECTOR | |
991 | DEFINE_PER_CPU(unsigned long, stack_canary); | |
992 | #endif | |
993 | ||
994 | /* Make sure %fs and %gs are initialized properly in idle threads */ | |
995 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) | |
996 | { | |
997 | memset(regs, 0, sizeof(struct pt_regs)); | |
998 | regs->fs = __KERNEL_PERCPU; | |
999 | regs->gs = __KERNEL_STACK_CANARY; | |
1000 | return regs; | |
1001 | } | |
1002 | #endif /* x86_64 */ | |
1003 | ||
1004 | /* | |
1005 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1006 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1007 | * and IDT. We reload them nevertheless, this function acts as a | |
1008 | * 'CPU state barrier', nothing should get across. | |
1009 | * A lot of state is already set up in PDA init for 64 bit | |
1010 | */ | |
1011 | #ifdef CONFIG_X86_64 | |
1012 | void __cpuinit cpu_init(void) | |
1013 | { | |
1014 | int cpu = stack_smp_processor_id(); | |
1015 | struct tss_struct *t = &per_cpu(init_tss, cpu); | |
1016 | struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu); | |
1017 | unsigned long v; | |
1018 | struct task_struct *me; | |
1019 | int i; | |
1020 | ||
1021 | #ifdef CONFIG_NUMA | |
1022 | if (cpu != 0 && percpu_read(node_number) == 0 && | |
1023 | cpu_to_node(cpu) != NUMA_NO_NODE) | |
1024 | percpu_write(node_number, cpu_to_node(cpu)); | |
1025 | #endif | |
1026 | ||
1027 | me = current; | |
1028 | ||
1029 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) | |
1030 | panic("CPU#%d already initialized!\n", cpu); | |
1031 | ||
1032 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1033 | ||
1034 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1035 | ||
1036 | /* | |
1037 | * Initialize the per-CPU GDT with the boot GDT, | |
1038 | * and set up the GDT descriptor: | |
1039 | */ | |
1040 | ||
1041 | switch_to_new_gdt(cpu); | |
1042 | loadsegment(fs, 0); | |
1043 | ||
1044 | load_idt((const struct desc_ptr *)&idt_descr); | |
1045 | ||
1046 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1047 | syscall_init(); | |
1048 | ||
1049 | wrmsrl(MSR_FS_BASE, 0); | |
1050 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1051 | barrier(); | |
1052 | ||
1053 | check_efer(); | |
1054 | if (cpu != 0) | |
1055 | enable_x2apic(); | |
1056 | ||
1057 | /* | |
1058 | * set up and load the per-CPU TSS | |
1059 | */ | |
1060 | if (!orig_ist->ist[0]) { | |
1061 | static const unsigned int sizes[N_EXCEPTION_STACKS] = { | |
1062 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
1063 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
1064 | }; | |
1065 | char *estacks = per_cpu(exception_stacks, cpu); | |
1066 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { | |
1067 | estacks += sizes[v]; | |
1068 | orig_ist->ist[v] = t->x86_tss.ist[v] = | |
1069 | (unsigned long)estacks; | |
1070 | } | |
1071 | } | |
1072 | ||
1073 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
1074 | /* | |
1075 | * <= is required because the CPU will access up to | |
1076 | * 8 bits beyond the end of the IO permission bitmap. | |
1077 | */ | |
1078 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1079 | t->io_bitmap[i] = ~0UL; | |
1080 | ||
1081 | atomic_inc(&init_mm.mm_count); | |
1082 | me->active_mm = &init_mm; | |
1083 | if (me->mm) | |
1084 | BUG(); | |
1085 | enter_lazy_tlb(&init_mm, me); | |
1086 | ||
1087 | load_sp0(t, ¤t->thread); | |
1088 | set_tss_desc(cpu, t); | |
1089 | load_TR_desc(); | |
1090 | load_LDT(&init_mm.context); | |
1091 | ||
1092 | #ifdef CONFIG_KGDB | |
1093 | /* | |
1094 | * If the kgdb is connected no debug regs should be altered. This | |
1095 | * is only applicable when KGDB and a KGDB I/O module are built | |
1096 | * into the kernel and you are using early debugging with | |
1097 | * kgdbwait. KGDB will control the kernel HW breakpoint registers. | |
1098 | */ | |
1099 | if (kgdb_connected && arch_kgdb_ops.correct_hw_break) | |
1100 | arch_kgdb_ops.correct_hw_break(); | |
1101 | else | |
1102 | #endif | |
1103 | { | |
1104 | /* | |
1105 | * Clear all 6 debug registers: | |
1106 | */ | |
1107 | set_debugreg(0UL, 0); | |
1108 | set_debugreg(0UL, 1); | |
1109 | set_debugreg(0UL, 2); | |
1110 | set_debugreg(0UL, 3); | |
1111 | set_debugreg(0UL, 6); | |
1112 | set_debugreg(0UL, 7); | |
1113 | } | |
1114 | ||
1115 | fpu_init(); | |
1116 | ||
1117 | raw_local_save_flags(kernel_eflags); | |
1118 | ||
1119 | if (is_uv_system()) | |
1120 | uv_cpu_init(); | |
1121 | } | |
1122 | ||
1123 | #else | |
1124 | ||
1125 | void __cpuinit cpu_init(void) | |
1126 | { | |
1127 | int cpu = smp_processor_id(); | |
1128 | struct task_struct *curr = current; | |
1129 | struct tss_struct *t = &per_cpu(init_tss, cpu); | |
1130 | struct thread_struct *thread = &curr->thread; | |
1131 | ||
1132 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { | |
1133 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); | |
1134 | for (;;) local_irq_enable(); | |
1135 | } | |
1136 | ||
1137 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1138 | ||
1139 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1140 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1141 | ||
1142 | load_idt(&idt_descr); | |
1143 | switch_to_new_gdt(cpu); | |
1144 | ||
1145 | /* | |
1146 | * Set up and load the per-CPU TSS and LDT | |
1147 | */ | |
1148 | atomic_inc(&init_mm.mm_count); | |
1149 | curr->active_mm = &init_mm; | |
1150 | if (curr->mm) | |
1151 | BUG(); | |
1152 | enter_lazy_tlb(&init_mm, curr); | |
1153 | ||
1154 | load_sp0(t, thread); | |
1155 | set_tss_desc(cpu, t); | |
1156 | load_TR_desc(); | |
1157 | load_LDT(&init_mm.context); | |
1158 | ||
1159 | #ifdef CONFIG_DOUBLEFAULT | |
1160 | /* Set up doublefault TSS pointer in the GDT */ | |
1161 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
1162 | #endif | |
1163 | ||
1164 | /* Clear all 6 debug registers: */ | |
1165 | set_debugreg(0, 0); | |
1166 | set_debugreg(0, 1); | |
1167 | set_debugreg(0, 2); | |
1168 | set_debugreg(0, 3); | |
1169 | set_debugreg(0, 6); | |
1170 | set_debugreg(0, 7); | |
1171 | ||
1172 | /* | |
1173 | * Force FPU initialization: | |
1174 | */ | |
1175 | if (cpu_has_xsave) | |
1176 | current_thread_info()->status = TS_XSAVE; | |
1177 | else | |
1178 | current_thread_info()->status = 0; | |
1179 | clear_used_math(); | |
1180 | mxcsr_feature_mask_init(); | |
1181 | ||
1182 | /* | |
1183 | * Boot processor to setup the FP and extended state context info. | |
1184 | */ | |
1185 | if (smp_processor_id() == boot_cpu_id) | |
1186 | init_thread_xstate(); | |
1187 | ||
1188 | xsave_init(); | |
1189 | } | |
1190 | ||
1191 | ||
1192 | #endif |