]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame_incremental - arch/x86/kernel/cpu/common.c
projects / mirror_ubuntu-artful-kernel.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
x86/asm: Make asm/alternative.h safe from assembly
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kernel / cpu / common.c
... / ...
CommitLineData
1#include <linux/bootmem.h>
2#include <linux/linkage.h>
3#include <linux/bitops.h>
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/percpu.h>
7#include <linux/string.h>
8#include <linux/ctype.h>
9#include <linux/delay.h>
10#include <linux/sched.h>
11#include <linux/init.h>
12#include <linux/kprobes.h>
13#include <linux/kgdb.h>
14#include <linux/smp.h>
15#include <linux/io.h>
16#include <linux/syscore_ops.h>
17
18#include <asm/stackprotector.h>
19#include <asm/perf_event.h>
20#include <asm/mmu_context.h>
21#include <asm/archrandom.h>
22#include <asm/hypervisor.h>
23#include <asm/processor.h>
24#include <asm/tlbflush.h>
25#include <asm/debugreg.h>
26#include <asm/sections.h>
27#include <asm/vsyscall.h>
28#include <linux/topology.h>
29#include <linux/cpumask.h>
30#include <asm/pgtable.h>
31#include <linux/atomic.h>
32#include <asm/proto.h>
33#include <asm/setup.h>
34#include <asm/apic.h>
35#include <asm/desc.h>
36#include <asm/fpu/internal.h>
37#include <asm/mtrr.h>
38#include <linux/numa.h>
39#include <asm/asm.h>
40#include <asm/cpu.h>
41#include <asm/mce.h>
42#include <asm/msr.h>
43#include <asm/pat.h>
44#include <asm/microcode.h>
45#include <asm/microcode_intel.h>
46
47#ifdef CONFIG_X86_LOCAL_APIC
48#include <asm/uv/uv.h>
49#endif
50
51#include "cpu.h"
52
53/* all of these masks are initialized in setup_cpu_local_masks() */
54cpumask_var_t cpu_initialized_mask;
55cpumask_var_t cpu_callout_mask;
56cpumask_var_t cpu_callin_mask;
57
58/* representing cpus for which sibling maps can be computed */
59cpumask_var_t cpu_sibling_setup_mask;
60
61/* correctly size the local cpu masks */
62void __init setup_cpu_local_masks(void)
63{
64 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
65 alloc_bootmem_cpumask_var(&cpu_callin_mask);
66 alloc_bootmem_cpumask_var(&cpu_callout_mask);
67 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
68}
69
70static void default_init(struct cpuinfo_x86 *c)
71{
72#ifdef CONFIG_X86_64
73 cpu_detect_cache_sizes(c);
74#else
75 /* Not much we can do here... */
76 /* Check if at least it has cpuid */
77 if (c->cpuid_level == -1) {
78 /* No cpuid. It must be an ancient CPU */
79 if (c->x86 == 4)
80 strcpy(c->x86_model_id, "486");
81 else if (c->x86 == 3)
82 strcpy(c->x86_model_id, "386");
83 }
84#endif
85}
86
87static const struct cpu_dev default_cpu = {
88 .c_init = default_init,
89 .c_vendor = "Unknown",
90 .c_x86_vendor = X86_VENDOR_UNKNOWN,
91};
92
93static const struct cpu_dev *this_cpu = &default_cpu;
94
95DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
96#ifdef CONFIG_X86_64
97 /*
98 * We need valid kernel segments for data and code in long mode too
99 * IRET will check the segment types kkeil 2000/10/28
100 * Also sysret mandates a special GDT layout
101 *
102 * TLS descriptors are currently at a different place compared to i386.
103 * Hopefully nobody expects them at a fixed place (Wine?)
104 */
105 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
106 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
107 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
108 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
109 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
110 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
111#else
112 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
113 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
114 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
115 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
116 /*
117 * Segments used for calling PnP BIOS have byte granularity.
118 * They code segments and data segments have fixed 64k limits,
119 * the transfer segment sizes are set at run time.
120 */
121 /* 32-bit code */
122 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
123 /* 16-bit code */
124 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
125 /* 16-bit data */
126 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
127 /* 16-bit data */
128 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
129 /* 16-bit data */
130 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
131 /*
132 * The APM segments have byte granularity and their bases
133 * are set at run time. All have 64k limits.
134 */
135 /* 32-bit code */
136 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
137 /* 16-bit code */
138 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
139 /* data */
140 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
141
142 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
143 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
144 GDT_STACK_CANARY_INIT
145#endif
146} };
147EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
148
149static int __init x86_mpx_setup(char *s)
150{
151 /* require an exact match without trailing characters */
152 if (strlen(s))
153 return 0;
154
155 /* do not emit a message if the feature is not present */
156 if (!boot_cpu_has(X86_FEATURE_MPX))
157 return 1;
158
159 setup_clear_cpu_cap(X86_FEATURE_MPX);
160 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
161 return 1;
162}
163__setup("nompx", x86_mpx_setup);
164
165static int __init x86_noinvpcid_setup(char *s)
166{
167 /* noinvpcid doesn't accept parameters */
168 if (s)
169 return -EINVAL;
170
171 /* do not emit a message if the feature is not present */
172 if (!boot_cpu_has(X86_FEATURE_INVPCID))
173 return 0;
174
175 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
176 pr_info("noinvpcid: INVPCID feature disabled\n");
177 return 0;
178}
179early_param("noinvpcid", x86_noinvpcid_setup);
180
181#ifdef CONFIG_X86_32
182static int cachesize_override = -1;
183static int disable_x86_serial_nr = 1;
184
185static int __init cachesize_setup(char *str)
186{
187 get_option(&str, &cachesize_override);
188 return 1;
189}
190__setup("cachesize=", cachesize_setup);
191
192static int __init x86_sep_setup(char *s)
193{
194 setup_clear_cpu_cap(X86_FEATURE_SEP);
195 return 1;
196}
197__setup("nosep", x86_sep_setup);
198
199/* Standard macro to see if a specific flag is changeable */
200static inline int flag_is_changeable_p(u32 flag)
201{
202 u32 f1, f2;
203
204 /*
205 * Cyrix and IDT cpus allow disabling of CPUID
206 * so the code below may return different results
207 * when it is executed before and after enabling
208 * the CPUID. Add "volatile" to not allow gcc to
209 * optimize the subsequent calls to this function.
210 */
211 asm volatile ("pushfl \n\t"
212 "pushfl \n\t"
213 "popl %0 \n\t"
214 "movl %0, %1 \n\t"
215 "xorl %2, %0 \n\t"
216 "pushl %0 \n\t"
217 "popfl \n\t"
218 "pushfl \n\t"
219 "popl %0 \n\t"
220 "popfl \n\t"
221
222 : "=&r" (f1), "=&r" (f2)
223 : "ir" (flag));
224
225 return ((f1^f2) & flag) != 0;
226}
227
228/* Probe for the CPUID instruction */
229int have_cpuid_p(void)
230{
231 return flag_is_changeable_p(X86_EFLAGS_ID);
232}
233
234static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
235{
236 unsigned long lo, hi;
237
238 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
239 return;
240
241 /* Disable processor serial number: */
242
243 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
244 lo |= 0x200000;
245 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
246
247 pr_notice("CPU serial number disabled.\n");
248 clear_cpu_cap(c, X86_FEATURE_PN);
249
250 /* Disabling the serial number may affect the cpuid level */
251 c->cpuid_level = cpuid_eax(0);
252}
253
254static int __init x86_serial_nr_setup(char *s)
255{
256 disable_x86_serial_nr = 0;
257 return 1;
258}
259__setup("serialnumber", x86_serial_nr_setup);
260#else
261static inline int flag_is_changeable_p(u32 flag)
262{
263 return 1;
264}
265static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
266{
267}
268#endif
269
270static __init int setup_disable_smep(char *arg)
271{
272 setup_clear_cpu_cap(X86_FEATURE_SMEP);
273 return 1;
274}
275__setup("nosmep", setup_disable_smep);
276
277static __always_inline void setup_smep(struct cpuinfo_x86 *c)
278{
279 if (cpu_has(c, X86_FEATURE_SMEP))
280 cr4_set_bits(X86_CR4_SMEP);
281}
282
283static __init int setup_disable_smap(char *arg)
284{
285 setup_clear_cpu_cap(X86_FEATURE_SMAP);
286 return 1;
287}
288__setup("nosmap", setup_disable_smap);
289
290static __always_inline void setup_smap(struct cpuinfo_x86 *c)
291{
292 unsigned long eflags = native_save_fl();
293
294 /* This should have been cleared long ago */
295 BUG_ON(eflags & X86_EFLAGS_AC);
296
297 if (cpu_has(c, X86_FEATURE_SMAP)) {
298#ifdef CONFIG_X86_SMAP
299 cr4_set_bits(X86_CR4_SMAP);
300#else
301 cr4_clear_bits(X86_CR4_SMAP);
302#endif
303 }
304}
305
306/*
307 * Protection Keys are not available in 32-bit mode.
308 */
309static bool pku_disabled;
310
311static __always_inline void setup_pku(struct cpuinfo_x86 *c)
312{
313 if (!cpu_has(c, X86_FEATURE_PKU))
314 return;
315 if (pku_disabled)
316 return;
317
318 cr4_set_bits(X86_CR4_PKE);
319 /*
320 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
321 * cpuid bit to be set. We need to ensure that we
322 * update that bit in this CPU's "cpu_info".
323 */
324 get_cpu_cap(c);
325}
326
327#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
328static __init int setup_disable_pku(char *arg)
329{
330 /*
331 * Do not clear the X86_FEATURE_PKU bit. All of the
332 * runtime checks are against OSPKE so clearing the
333 * bit does nothing.
334 *
335 * This way, we will see "pku" in cpuinfo, but not
336 * "ospke", which is exactly what we want. It shows
337 * that the CPU has PKU, but the OS has not enabled it.
338 * This happens to be exactly how a system would look
339 * if we disabled the config option.
340 */
341 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
342 pku_disabled = true;
343 return 1;
344}
345__setup("nopku", setup_disable_pku);
346#endif /* CONFIG_X86_64 */
347
348/*
349 * Some CPU features depend on higher CPUID levels, which may not always
350 * be available due to CPUID level capping or broken virtualization
351 * software. Add those features to this table to auto-disable them.
352 */
353struct cpuid_dependent_feature {
354 u32 feature;
355 u32 level;
356};
357
358static const struct cpuid_dependent_feature
359cpuid_dependent_features[] = {
360 { X86_FEATURE_MWAIT, 0x00000005 },
361 { X86_FEATURE_DCA, 0x00000009 },
362 { X86_FEATURE_XSAVE, 0x0000000d },
363 { 0, 0 }
364};
365
366static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
367{
368 const struct cpuid_dependent_feature *df;
369
370 for (df = cpuid_dependent_features; df->feature; df++) {
371
372 if (!cpu_has(c, df->feature))
373 continue;
374 /*
375 * Note: cpuid_level is set to -1 if unavailable, but
376 * extended_extended_level is set to 0 if unavailable
377 * and the legitimate extended levels are all negative
378 * when signed; hence the weird messing around with
379 * signs here...
380 */
381 if (!((s32)df->level < 0 ?
382 (u32)df->level > (u32)c->extended_cpuid_level :
383 (s32)df->level > (s32)c->cpuid_level))
384 continue;
385
386 clear_cpu_cap(c, df->feature);
387 if (!warn)
388 continue;
389
390 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
391 x86_cap_flag(df->feature), df->level);
392 }
393}
394
395/*
396 * Naming convention should be: <Name> [(<Codename>)]
397 * This table only is used unless init_<vendor>() below doesn't set it;
398 * in particular, if CPUID levels 0x80000002..4 are supported, this
399 * isn't used
400 */
401
402/* Look up CPU names by table lookup. */
403static const char *table_lookup_model(struct cpuinfo_x86 *c)
404{
405#ifdef CONFIG_X86_32
406 const struct legacy_cpu_model_info *info;
407
408 if (c->x86_model >= 16)
409 return NULL; /* Range check */
410
411 if (!this_cpu)
412 return NULL;
413
414 info = this_cpu->legacy_models;
415
416 while (info->family) {
417 if (info->family == c->x86)
418 return info->model_names[c->x86_model];
419 info++;
420 }
421#endif
422 return NULL; /* Not found */
423}
424
425__u32 cpu_caps_cleared[NCAPINTS];
426__u32 cpu_caps_set[NCAPINTS];
427
428void load_percpu_segment(int cpu)
429{
430#ifdef CONFIG_X86_32
431 loadsegment(fs, __KERNEL_PERCPU);
432#else
433 loadsegment(gs, 0);
434 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
435#endif
436 load_stack_canary_segment();
437}
438
439/*
440 * Current gdt points %fs at the "master" per-cpu area: after this,
441 * it's on the real one.
442 */
443void switch_to_new_gdt(int cpu)
444{
445 struct desc_ptr gdt_descr;
446
447 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
448 gdt_descr.size = GDT_SIZE - 1;
449 load_gdt(&gdt_descr);
450 /* Reload the per-cpu base */
451
452 load_percpu_segment(cpu);
453}
454
455static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
456
457static void get_model_name(struct cpuinfo_x86 *c)
458{
459 unsigned int *v;
460 char *p, *q, *s;
461
462 if (c->extended_cpuid_level < 0x80000004)
463 return;
464
465 v = (unsigned int *)c->x86_model_id;
466 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
467 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
468 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
469 c->x86_model_id[48] = 0;
470
471 /* Trim whitespace */
472 p = q = s = &c->x86_model_id[0];
473
474 while (*p == ' ')
475 p++;
476
477 while (*p) {
478 /* Note the last non-whitespace index */
479 if (!isspace(*p))
480 s = q;
481
482 *q++ = *p++;
483 }
484
485 *(s + 1) = '\0';
486}
487
488void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
489{
490 unsigned int n, dummy, ebx, ecx, edx, l2size;
491
492 n = c->extended_cpuid_level;
493
494 if (n >= 0x80000005) {
495 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
496 c->x86_cache_size = (ecx>>24) + (edx>>24);
497#ifdef CONFIG_X86_64
498 /* On K8 L1 TLB is inclusive, so don't count it */
499 c->x86_tlbsize = 0;
500#endif
501 }
502
503 if (n < 0x80000006) /* Some chips just has a large L1. */
504 return;
505
506 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
507 l2size = ecx >> 16;
508
509#ifdef CONFIG_X86_64
510 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
511#else
512 /* do processor-specific cache resizing */
513 if (this_cpu->legacy_cache_size)
514 l2size = this_cpu->legacy_cache_size(c, l2size);
515
516 /* Allow user to override all this if necessary. */
517 if (cachesize_override != -1)
518 l2size = cachesize_override;
519
520 if (l2size == 0)
521 return; /* Again, no L2 cache is possible */
522#endif
523
524 c->x86_cache_size = l2size;
525}
526
527u16 __read_mostly tlb_lli_4k[NR_INFO];
528u16 __read_mostly tlb_lli_2m[NR_INFO];
529u16 __read_mostly tlb_lli_4m[NR_INFO];
530u16 __read_mostly tlb_lld_4k[NR_INFO];
531u16 __read_mostly tlb_lld_2m[NR_INFO];
532u16 __read_mostly tlb_lld_4m[NR_INFO];
533u16 __read_mostly tlb_lld_1g[NR_INFO];
534
535static void cpu_detect_tlb(struct cpuinfo_x86 *c)
536{
537 if (this_cpu->c_detect_tlb)
538 this_cpu->c_detect_tlb(c);
539
540 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
541 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
542 tlb_lli_4m[ENTRIES]);
543
544 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
545 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
546 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
547}
548
549void detect_ht(struct cpuinfo_x86 *c)
550{
551#ifdef CONFIG_SMP
552 u32 eax, ebx, ecx, edx;
553 int index_msb, core_bits;
554 static bool printed;
555
556 if (!cpu_has(c, X86_FEATURE_HT))
557 return;
558
559 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
560 goto out;
561
562 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
563 return;
564
565 cpuid(1, &eax, &ebx, &ecx, &edx);
566
567 smp_num_siblings = (ebx & 0xff0000) >> 16;
568
569 if (smp_num_siblings == 1) {
570 pr_info_once("CPU0: Hyper-Threading is disabled\n");
571 goto out;
572 }
573
574 if (smp_num_siblings <= 1)
575 goto out;
576
577 index_msb = get_count_order(smp_num_siblings);
578 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
579
580 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
581
582 index_msb = get_count_order(smp_num_siblings);
583
584 core_bits = get_count_order(c->x86_max_cores);
585
586 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
587 ((1 << core_bits) - 1);
588
589out:
590 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
591 pr_info("CPU: Physical Processor ID: %d\n",
592 c->phys_proc_id);
593 pr_info("CPU: Processor Core ID: %d\n",
594 c->cpu_core_id);
595 printed = 1;
596 }
597#endif
598}
599
600static void get_cpu_vendor(struct cpuinfo_x86 *c)
601{
602 char *v = c->x86_vendor_id;
603 int i;
604
605 for (i = 0; i < X86_VENDOR_NUM; i++) {
606 if (!cpu_devs[i])
607 break;
608
609 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
610 (cpu_devs[i]->c_ident[1] &&
611 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
612
613 this_cpu = cpu_devs[i];
614 c->x86_vendor = this_cpu->c_x86_vendor;
615 return;
616 }
617 }
618
619 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
620 "CPU: Your system may be unstable.\n", v);
621
622 c->x86_vendor = X86_VENDOR_UNKNOWN;
623 this_cpu = &default_cpu;
624}
625
626void cpu_detect(struct cpuinfo_x86 *c)
627{
628 /* Get vendor name */
629 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
630 (unsigned int *)&c->x86_vendor_id[0],
631 (unsigned int *)&c->x86_vendor_id[8],
632 (unsigned int *)&c->x86_vendor_id[4]);
633
634 c->x86 = 4;
635 /* Intel-defined flags: level 0x00000001 */
636 if (c->cpuid_level >= 0x00000001) {
637 u32 junk, tfms, cap0, misc;
638
639 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
640 c->x86 = x86_family(tfms);
641 c->x86_model = x86_model(tfms);
642 c->x86_mask = x86_stepping(tfms);
643
644 if (cap0 & (1<<19)) {
645 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
646 c->x86_cache_alignment = c->x86_clflush_size;
647 }
648 }
649}
650
651void get_cpu_cap(struct cpuinfo_x86 *c)
652{
653 u32 eax, ebx, ecx, edx;
654
655 /* Intel-defined flags: level 0x00000001 */
656 if (c->cpuid_level >= 0x00000001) {
657 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
658
659 c->x86_capability[CPUID_1_ECX] = ecx;
660 c->x86_capability[CPUID_1_EDX] = edx;
661 }
662
663 /* Additional Intel-defined flags: level 0x00000007 */
664 if (c->cpuid_level >= 0x00000007) {
665 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
666
667 c->x86_capability[CPUID_7_0_EBX] = ebx;
668
669 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
670 c->x86_capability[CPUID_7_ECX] = ecx;
671 }
672
673 /* Extended state features: level 0x0000000d */
674 if (c->cpuid_level >= 0x0000000d) {
675 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
676
677 c->x86_capability[CPUID_D_1_EAX] = eax;
678 }
679
680 /* Additional Intel-defined flags: level 0x0000000F */
681 if (c->cpuid_level >= 0x0000000F) {
682
683 /* QoS sub-leaf, EAX=0Fh, ECX=0 */
684 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx);
685 c->x86_capability[CPUID_F_0_EDX] = edx;
686
687 if (cpu_has(c, X86_FEATURE_CQM_LLC)) {
688 /* will be overridden if occupancy monitoring exists */
689 c->x86_cache_max_rmid = ebx;
690
691 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
692 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx);
693 c->x86_capability[CPUID_F_1_EDX] = edx;
694
695 if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) ||
696 ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) ||
697 (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) {
698 c->x86_cache_max_rmid = ecx;
699 c->x86_cache_occ_scale = ebx;
700 }
701 } else {
702 c->x86_cache_max_rmid = -1;
703 c->x86_cache_occ_scale = -1;
704 }
705 }
706
707 /* AMD-defined flags: level 0x80000001 */
708 eax = cpuid_eax(0x80000000);
709 c->extended_cpuid_level = eax;
710
711 if ((eax & 0xffff0000) == 0x80000000) {
712 if (eax >= 0x80000001) {
713 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
714
715 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
716 c->x86_capability[CPUID_8000_0001_EDX] = edx;
717 }
718 }
719
720 if (c->extended_cpuid_level >= 0x80000008) {
721 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
722
723 c->x86_virt_bits = (eax >> 8) & 0xff;
724 c->x86_phys_bits = eax & 0xff;
725 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
726 }
727#ifdef CONFIG_X86_32
728 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
729 c->x86_phys_bits = 36;
730#endif
731
732 if (c->extended_cpuid_level >= 0x80000007)
733 c->x86_power = cpuid_edx(0x80000007);
734
735 if (c->extended_cpuid_level >= 0x8000000a)
736 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
737
738 init_scattered_cpuid_features(c);
739}
740
741static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
742{
743#ifdef CONFIG_X86_32
744 int i;
745
746 /*
747 * First of all, decide if this is a 486 or higher
748 * It's a 486 if we can modify the AC flag
749 */
750 if (flag_is_changeable_p(X86_EFLAGS_AC))
751 c->x86 = 4;
752 else
753 c->x86 = 3;
754
755 for (i = 0; i < X86_VENDOR_NUM; i++)
756 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
757 c->x86_vendor_id[0] = 0;
758 cpu_devs[i]->c_identify(c);
759 if (c->x86_vendor_id[0]) {
760 get_cpu_vendor(c);
761 break;
762 }
763 }
764#endif
765}
766
767/*
768 * Do minimum CPU detection early.
769 * Fields really needed: vendor, cpuid_level, family, model, mask,
770 * cache alignment.
771 * The others are not touched to avoid unwanted side effects.
772 *
773 * WARNING: this function is only called on the BP. Don't add code here
774 * that is supposed to run on all CPUs.
775 */
776static void __init early_identify_cpu(struct cpuinfo_x86 *c)
777{
778#ifdef CONFIG_X86_64
779 c->x86_clflush_size = 64;
780 c->x86_phys_bits = 36;
781 c->x86_virt_bits = 48;
782#else
783 c->x86_clflush_size = 32;
784 c->x86_phys_bits = 32;
785 c->x86_virt_bits = 32;
786#endif
787 c->x86_cache_alignment = c->x86_clflush_size;
788
789 memset(&c->x86_capability, 0, sizeof c->x86_capability);
790 c->extended_cpuid_level = 0;
791
792 if (!have_cpuid_p())
793 identify_cpu_without_cpuid(c);
794
795 /* cyrix could have cpuid enabled via c_identify()*/
796 if (!have_cpuid_p())
797 return;
798
799 cpu_detect(c);
800 get_cpu_vendor(c);
801 get_cpu_cap(c);
802
803 if (this_cpu->c_early_init)
804 this_cpu->c_early_init(c);
805
806 c->cpu_index = 0;
807 filter_cpuid_features(c, false);
808
809 if (this_cpu->c_bsp_init)
810 this_cpu->c_bsp_init(c);
811
812 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
813 fpu__init_system(c);
814}
815
816void __init early_cpu_init(void)
817{
818 const struct cpu_dev *const *cdev;
819 int count = 0;
820
821#ifdef CONFIG_PROCESSOR_SELECT
822 pr_info("KERNEL supported cpus:\n");
823#endif
824
825 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
826 const struct cpu_dev *cpudev = *cdev;
827
828 if (count >= X86_VENDOR_NUM)
829 break;
830 cpu_devs[count] = cpudev;
831 count++;
832
833#ifdef CONFIG_PROCESSOR_SELECT
834 {
835 unsigned int j;
836
837 for (j = 0; j < 2; j++) {
838 if (!cpudev->c_ident[j])
839 continue;
840 pr_info(" %s %s\n", cpudev->c_vendor,
841 cpudev->c_ident[j]);
842 }
843 }
844#endif
845 }
846 early_identify_cpu(&boot_cpu_data);
847}
848
849/*
850 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
851 * unfortunately, that's not true in practice because of early VIA
852 * chips and (more importantly) broken virtualizers that are not easy
853 * to detect. In the latter case it doesn't even *fail* reliably, so
854 * probing for it doesn't even work. Disable it completely on 32-bit
855 * unless we can find a reliable way to detect all the broken cases.
856 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
857 */
858static void detect_nopl(struct cpuinfo_x86 *c)
859{
860#ifdef CONFIG_X86_32
861 clear_cpu_cap(c, X86_FEATURE_NOPL);
862#else
863 set_cpu_cap(c, X86_FEATURE_NOPL);
864#endif
865}
866
867static void detect_null_seg_behavior(struct cpuinfo_x86 *c)
868{
869#ifdef CONFIG_X86_64
870 /*
871 * Empirically, writing zero to a segment selector on AMD does
872 * not clear the base, whereas writing zero to a segment
873 * selector on Intel does clear the base. Intel's behavior
874 * allows slightly faster context switches in the common case
875 * where GS is unused by the prev and next threads.
876 *
877 * Since neither vendor documents this anywhere that I can see,
878 * detect it directly instead of hardcoding the choice by
879 * vendor.
880 *
881 * I've designated AMD's behavior as the "bug" because it's
882 * counterintuitive and less friendly.
883 */
884
885 unsigned long old_base, tmp;
886 rdmsrl(MSR_FS_BASE, old_base);
887 wrmsrl(MSR_FS_BASE, 1);
888 loadsegment(fs, 0);
889 rdmsrl(MSR_FS_BASE, tmp);
890 if (tmp != 0)
891 set_cpu_bug(c, X86_BUG_NULL_SEG);
892 wrmsrl(MSR_FS_BASE, old_base);
893#endif
894}
895
896static void generic_identify(struct cpuinfo_x86 *c)
897{
898 c->extended_cpuid_level = 0;
899
900 if (!have_cpuid_p())
901 identify_cpu_without_cpuid(c);
902
903 /* cyrix could have cpuid enabled via c_identify()*/
904 if (!have_cpuid_p())
905 return;
906
907 cpu_detect(c);
908
909 get_cpu_vendor(c);
910
911 get_cpu_cap(c);
912
913 if (c->cpuid_level >= 0x00000001) {
914 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
915#ifdef CONFIG_X86_32
916# ifdef CONFIG_SMP
917 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
918# else
919 c->apicid = c->initial_apicid;
920# endif
921#endif
922 c->phys_proc_id = c->initial_apicid;
923 }
924
925 get_model_name(c); /* Default name */
926
927 detect_nopl(c);
928
929 detect_null_seg_behavior(c);
930
931 /*
932 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
933 * systems that run Linux at CPL > 0 may or may not have the
934 * issue, but, even if they have the issue, there's absolutely
935 * nothing we can do about it because we can't use the real IRET
936 * instruction.
937 *
938 * NB: For the time being, only 32-bit kernels support
939 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
940 * whether to apply espfix using paravirt hooks. If any
941 * non-paravirt system ever shows up that does *not* have the
942 * ESPFIX issue, we can change this.
943 */
944#ifdef CONFIG_X86_32
945# ifdef CONFIG_PARAVIRT
946 do {
947 extern void native_iret(void);
948 if (pv_cpu_ops.iret == native_iret)
949 set_cpu_bug(c, X86_BUG_ESPFIX);
950 } while (0);
951# else
952 set_cpu_bug(c, X86_BUG_ESPFIX);
953# endif
954#endif
955}
956
957static void x86_init_cache_qos(struct cpuinfo_x86 *c)
958{
959 /*
960 * The heavy lifting of max_rmid and cache_occ_scale are handled
961 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
962 * in case CQM bits really aren't there in this CPU.
963 */
964 if (c != &boot_cpu_data) {
965 boot_cpu_data.x86_cache_max_rmid =
966 min(boot_cpu_data.x86_cache_max_rmid,
967 c->x86_cache_max_rmid);
968 }
969}
970
971/*
972 * This does the hard work of actually picking apart the CPU stuff...
973 */
974static void identify_cpu(struct cpuinfo_x86 *c)
975{
976 int i;
977
978 c->loops_per_jiffy = loops_per_jiffy;
979 c->x86_cache_size = -1;
980 c->x86_vendor = X86_VENDOR_UNKNOWN;
981 c->x86_model = c->x86_mask = 0; /* So far unknown... */
982 c->x86_vendor_id[0] = '\0'; /* Unset */
983 c->x86_model_id[0] = '\0'; /* Unset */
984 c->x86_max_cores = 1;
985 c->x86_coreid_bits = 0;
986#ifdef CONFIG_X86_64
987 c->x86_clflush_size = 64;
988 c->x86_phys_bits = 36;
989 c->x86_virt_bits = 48;
990#else
991 c->cpuid_level = -1; /* CPUID not detected */
992 c->x86_clflush_size = 32;
993 c->x86_phys_bits = 32;
994 c->x86_virt_bits = 32;
995#endif
996 c->x86_cache_alignment = c->x86_clflush_size;
997 memset(&c->x86_capability, 0, sizeof c->x86_capability);
998
999 generic_identify(c);
1000
1001 if (this_cpu->c_identify)
1002 this_cpu->c_identify(c);
1003
1004 /* Clear/Set all flags overridden by options, after probe */
1005 for (i = 0; i < NCAPINTS; i++) {
1006 c->x86_capability[i] &= ~cpu_caps_cleared[i];
1007 c->x86_capability[i] |= cpu_caps_set[i];
1008 }
1009
1010#ifdef CONFIG_X86_64
1011 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1012#endif
1013
1014 /*
1015 * Vendor-specific initialization. In this section we
1016 * canonicalize the feature flags, meaning if there are
1017 * features a certain CPU supports which CPUID doesn't
1018 * tell us, CPUID claiming incorrect flags, or other bugs,
1019 * we handle them here.
1020 *
1021 * At the end of this section, c->x86_capability better
1022 * indicate the features this CPU genuinely supports!
1023 */
1024 if (this_cpu->c_init)
1025 this_cpu->c_init(c);
1026
1027 /* Disable the PN if appropriate */
1028 squash_the_stupid_serial_number(c);
1029
1030 /* Set up SMEP/SMAP */
1031 setup_smep(c);
1032 setup_smap(c);
1033
1034 /*
1035 * The vendor-specific functions might have changed features.
1036 * Now we do "generic changes."
1037 */
1038
1039 /* Filter out anything that depends on CPUID levels we don't have */
1040 filter_cpuid_features(c, true);
1041
1042 /* If the model name is still unset, do table lookup. */
1043 if (!c->x86_model_id[0]) {
1044 const char *p;
1045 p = table_lookup_model(c);
1046 if (p)
1047 strcpy(c->x86_model_id, p);
1048 else
1049 /* Last resort... */
1050 sprintf(c->x86_model_id, "%02x/%02x",
1051 c->x86, c->x86_model);
1052 }
1053
1054#ifdef CONFIG_X86_64
1055 detect_ht(c);
1056#endif
1057
1058 init_hypervisor(c);
1059 x86_init_rdrand(c);
1060 x86_init_cache_qos(c);
1061 setup_pku(c);
1062
1063 /*
1064 * Clear/Set all flags overridden by options, need do it
1065 * before following smp all cpus cap AND.
1066 */
1067 for (i = 0; i < NCAPINTS; i++) {
1068 c->x86_capability[i] &= ~cpu_caps_cleared[i];
1069 c->x86_capability[i] |= cpu_caps_set[i];
1070 }
1071
1072 /*
1073 * On SMP, boot_cpu_data holds the common feature set between
1074 * all CPUs; so make sure that we indicate which features are
1075 * common between the CPUs. The first time this routine gets
1076 * executed, c == &boot_cpu_data.
1077 */
1078 if (c != &boot_cpu_data) {
1079 /* AND the already accumulated flags with these */
1080 for (i = 0; i < NCAPINTS; i++)
1081 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1082
1083 /* OR, i.e. replicate the bug flags */
1084 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1085 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1086 }
1087
1088 /* Init Machine Check Exception if available. */
1089 mcheck_cpu_init(c);
1090
1091 select_idle_routine(c);
1092
1093#ifdef CONFIG_NUMA
1094 numa_add_cpu(smp_processor_id());
1095#endif
1096 /* The boot/hotplug time assigment got cleared, restore it */
1097 c->logical_proc_id = topology_phys_to_logical_pkg(c->phys_proc_id);
1098}
1099
1100/*
1101 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1102 * on 32-bit kernels:
1103 */
1104#ifdef CONFIG_X86_32
1105void enable_sep_cpu(void)
1106{
1107 struct tss_struct *tss;
1108 int cpu;
1109
1110 if (!boot_cpu_has(X86_FEATURE_SEP))
1111 return;
1112
1113 cpu = get_cpu();
1114 tss = &per_cpu(cpu_tss, cpu);
1115
1116 /*
1117 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1118 * see the big comment in struct x86_hw_tss's definition.
1119 */
1120
1121 tss->x86_tss.ss1 = __KERNEL_CS;
1122 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1123
1124 wrmsr(MSR_IA32_SYSENTER_ESP,
1125 (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack),
1126 0);
1127
1128 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1129
1130 put_cpu();
1131}
1132#endif
1133
1134void __init identify_boot_cpu(void)
1135{
1136 identify_cpu(&boot_cpu_data);
1137 init_amd_e400_c1e_mask();
1138#ifdef CONFIG_X86_32
1139 sysenter_setup();
1140 enable_sep_cpu();
1141#endif
1142 cpu_detect_tlb(&boot_cpu_data);
1143}
1144
1145void identify_secondary_cpu(struct cpuinfo_x86 *c)
1146{
1147 BUG_ON(c == &boot_cpu_data);
1148 identify_cpu(c);
1149#ifdef CONFIG_X86_32
1150 enable_sep_cpu();
1151#endif
1152 mtrr_ap_init();
1153}
1154
1155struct msr_range {
1156 unsigned min;
1157 unsigned max;
1158};
1159
1160static const struct msr_range msr_range_array[] = {
1161 { 0x00000000, 0x00000418},
1162 { 0xc0000000, 0xc000040b},
1163 { 0xc0010000, 0xc0010142},
1164 { 0xc0011000, 0xc001103b},
1165};
1166
1167static void __print_cpu_msr(void)
1168{
1169 unsigned index_min, index_max;
1170 unsigned index;
1171 u64 val;
1172 int i;
1173
1174 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
1175 index_min = msr_range_array[i].min;
1176 index_max = msr_range_array[i].max;
1177
1178 for (index = index_min; index < index_max; index++) {
1179 if (rdmsrl_safe(index, &val))
1180 continue;
1181 pr_info(" MSR%08x: %016llx\n", index, val);
1182 }
1183 }
1184}
1185
1186static int show_msr;
1187
1188static __init int setup_show_msr(char *arg)
1189{
1190 int num;
1191
1192 get_option(&arg, &num);
1193
1194 if (num > 0)
1195 show_msr = num;
1196 return 1;
1197}
1198__setup("show_msr=", setup_show_msr);
1199
1200static __init int setup_noclflush(char *arg)
1201{
1202 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1203 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1204 return 1;
1205}
1206__setup("noclflush", setup_noclflush);
1207
1208void print_cpu_info(struct cpuinfo_x86 *c)
1209{
1210 const char *vendor = NULL;
1211
1212 if (c->x86_vendor < X86_VENDOR_NUM) {
1213 vendor = this_cpu->c_vendor;
1214 } else {
1215 if (c->cpuid_level >= 0)
1216 vendor = c->x86_vendor_id;
1217 }
1218
1219 if (vendor && !strstr(c->x86_model_id, vendor))
1220 pr_cont("%s ", vendor);
1221
1222 if (c->x86_model_id[0])
1223 pr_cont("%s", c->x86_model_id);
1224 else
1225 pr_cont("%d86", c->x86);
1226
1227 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1228
1229 if (c->x86_mask || c->cpuid_level >= 0)
1230 pr_cont(", stepping: 0x%x)\n", c->x86_mask);
1231 else
1232 pr_cont(")\n");
1233
1234 print_cpu_msr(c);
1235}
1236
1237void print_cpu_msr(struct cpuinfo_x86 *c)
1238{
1239 if (c->cpu_index < show_msr)
1240 __print_cpu_msr();
1241}
1242
1243static __init int setup_disablecpuid(char *arg)
1244{
1245 int bit;
1246
1247 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1248 setup_clear_cpu_cap(bit);
1249 else
1250 return 0;
1251
1252 return 1;
1253}
1254__setup("clearcpuid=", setup_disablecpuid);
1255
1256#ifdef CONFIG_X86_64
1257struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
1258struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1,
1259 (unsigned long) debug_idt_table };
1260
1261DEFINE_PER_CPU_FIRST(union irq_stack_union,
1262 irq_stack_union) __aligned(PAGE_SIZE) __visible;
1263
1264/*
1265 * The following percpu variables are hot. Align current_task to
1266 * cacheline size such that they fall in the same cacheline.
1267 */
1268DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1269 &init_task;
1270EXPORT_PER_CPU_SYMBOL(current_task);
1271
1272DEFINE_PER_CPU(char *, irq_stack_ptr) =
1273 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
1274
1275DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1276
1277DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1278EXPORT_PER_CPU_SYMBOL(__preempt_count);
1279
1280/*
1281 * Special IST stacks which the CPU switches to when it calls
1282 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1283 * limit), all of them are 4K, except the debug stack which
1284 * is 8K.
1285 */
1286static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1287 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1288 [DEBUG_STACK - 1] = DEBUG_STKSZ
1289};
1290
1291static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1292 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1293
1294/* May not be marked __init: used by software suspend */
1295void syscall_init(void)
1296{
1297 /*
1298 * LSTAR and STAR live in a bit strange symbiosis.
1299 * They both write to the same internal register. STAR allows to
1300 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1301 */
1302 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1303 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1304
1305#ifdef CONFIG_IA32_EMULATION
1306 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1307 /*
1308 * This only works on Intel CPUs.
1309 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1310 * This does not cause SYSENTER to jump to the wrong location, because
1311 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1312 */
1313 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1314 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1315 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1316#else
1317 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1318 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1319 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1320 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1321#endif
1322
1323 /* Flags to clear on syscall */
1324 wrmsrl(MSR_SYSCALL_MASK,
1325 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1326 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1327}
1328
1329/*
1330 * Copies of the original ist values from the tss are only accessed during
1331 * debugging, no special alignment required.
1332 */
1333DEFINE_PER_CPU(struct orig_ist, orig_ist);
1334
1335static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1336DEFINE_PER_CPU(int, debug_stack_usage);
1337
1338int is_debug_stack(unsigned long addr)
1339{
1340 return __this_cpu_read(debug_stack_usage) ||
1341 (addr <= __this_cpu_read(debug_stack_addr) &&
1342 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ));
1343}
1344NOKPROBE_SYMBOL(is_debug_stack);
1345
1346DEFINE_PER_CPU(u32, debug_idt_ctr);
1347
1348void debug_stack_set_zero(void)
1349{
1350 this_cpu_inc(debug_idt_ctr);
1351 load_current_idt();
1352}
1353NOKPROBE_SYMBOL(debug_stack_set_zero);
1354
1355void debug_stack_reset(void)
1356{
1357 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1358 return;
1359 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1360 load_current_idt();
1361}
1362NOKPROBE_SYMBOL(debug_stack_reset);
1363
1364#else /* CONFIG_X86_64 */
1365
1366DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1367EXPORT_PER_CPU_SYMBOL(current_task);
1368DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1369EXPORT_PER_CPU_SYMBOL(__preempt_count);
1370
1371/*
1372 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1373 * the top of the kernel stack. Use an extra percpu variable to track the
1374 * top of the kernel stack directly.
1375 */
1376DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1377 (unsigned long)&init_thread_union + THREAD_SIZE;
1378EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1379
1380#ifdef CONFIG_CC_STACKPROTECTOR
1381DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1382#endif
1383
1384#endif /* CONFIG_X86_64 */
1385
1386/*
1387 * Clear all 6 debug registers:
1388 */
1389static void clear_all_debug_regs(void)
1390{
1391 int i;
1392
1393 for (i = 0; i < 8; i++) {
1394 /* Ignore db4, db5 */
1395 if ((i == 4) || (i == 5))
1396 continue;
1397
1398 set_debugreg(0, i);
1399 }
1400}
1401
1402#ifdef CONFIG_KGDB
1403/*
1404 * Restore debug regs if using kgdbwait and you have a kernel debugger
1405 * connection established.
1406 */
1407static void dbg_restore_debug_regs(void)
1408{
1409 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1410 arch_kgdb_ops.correct_hw_break();
1411}
1412#else /* ! CONFIG_KGDB */
1413#define dbg_restore_debug_regs()
1414#endif /* ! CONFIG_KGDB */
1415
1416static void wait_for_master_cpu(int cpu)
1417{
1418#ifdef CONFIG_SMP
1419 /*
1420 * wait for ACK from master CPU before continuing
1421 * with AP initialization
1422 */
1423 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1424 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1425 cpu_relax();
1426#endif
1427}
1428
1429/*
1430 * cpu_init() initializes state that is per-CPU. Some data is already
1431 * initialized (naturally) in the bootstrap process, such as the GDT
1432 * and IDT. We reload them nevertheless, this function acts as a
1433 * 'CPU state barrier', nothing should get across.
1434 * A lot of state is already set up in PDA init for 64 bit
1435 */
1436#ifdef CONFIG_X86_64
1437
1438void cpu_init(void)
1439{
1440 struct orig_ist *oist;
1441 struct task_struct *me;
1442 struct tss_struct *t;
1443 unsigned long v;
1444 int cpu = stack_smp_processor_id();
1445 int i;
1446
1447 wait_for_master_cpu(cpu);
1448
1449 /*
1450 * Initialize the CR4 shadow before doing anything that could
1451 * try to read it.
1452 */
1453 cr4_init_shadow();
1454
1455 /*
1456 * Load microcode on this cpu if a valid microcode is available.
1457 * This is early microcode loading procedure.
1458 */
1459 load_ucode_ap();
1460
1461 t = &per_cpu(cpu_tss, cpu);
1462 oist = &per_cpu(orig_ist, cpu);
1463
1464#ifdef CONFIG_NUMA
1465 if (this_cpu_read(numa_node) == 0 &&
1466 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1467 set_numa_node(early_cpu_to_node(cpu));
1468#endif
1469
1470 me = current;
1471
1472 pr_debug("Initializing CPU#%d\n", cpu);
1473
1474 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1475
1476 /*
1477 * Initialize the per-CPU GDT with the boot GDT,
1478 * and set up the GDT descriptor:
1479 */
1480
1481 switch_to_new_gdt(cpu);
1482 loadsegment(fs, 0);
1483
1484 load_current_idt();
1485
1486 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1487 syscall_init();
1488
1489 wrmsrl(MSR_FS_BASE, 0);
1490 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1491 barrier();
1492
1493 x86_configure_nx();
1494 x2apic_setup();
1495
1496 /*
1497 * set up and load the per-CPU TSS
1498 */
1499 if (!oist->ist[0]) {
1500 char *estacks = per_cpu(exception_stacks, cpu);
1501
1502 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1503 estacks += exception_stack_sizes[v];
1504 oist->ist[v] = t->x86_tss.ist[v] =
1505 (unsigned long)estacks;
1506 if (v == DEBUG_STACK-1)
1507 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1508 }
1509 }
1510
1511 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1512
1513 /*
1514 * <= is required because the CPU will access up to
1515 * 8 bits beyond the end of the IO permission bitmap.
1516 */
1517 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1518 t->io_bitmap[i] = ~0UL;
1519
1520 atomic_inc(&init_mm.mm_count);
1521 me->active_mm = &init_mm;
1522 BUG_ON(me->mm);
1523 enter_lazy_tlb(&init_mm, me);
1524
1525 load_sp0(t, &current->thread);
1526 set_tss_desc(cpu, t);
1527 load_TR_desc();
1528 load_mm_ldt(&init_mm);
1529
1530 clear_all_debug_regs();
1531 dbg_restore_debug_regs();
1532
1533 fpu__init_cpu();
1534
1535 if (is_uv_system())
1536 uv_cpu_init();
1537}
1538
1539#else
1540
1541void cpu_init(void)
1542{
1543 int cpu = smp_processor_id();
1544 struct task_struct *curr = current;
1545 struct tss_struct *t = &per_cpu(cpu_tss, cpu);
1546 struct thread_struct *thread = &curr->thread;
1547
1548 wait_for_master_cpu(cpu);
1549
1550 /*
1551 * Initialize the CR4 shadow before doing anything that could
1552 * try to read it.
1553 */
1554 cr4_init_shadow();
1555
1556 show_ucode_info_early();
1557
1558 pr_info("Initializing CPU#%d\n", cpu);
1559
1560 if (cpu_feature_enabled(X86_FEATURE_VME) ||
1561 boot_cpu_has(X86_FEATURE_TSC) ||
1562 boot_cpu_has(X86_FEATURE_DE))
1563 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1564
1565 load_current_idt();
1566 switch_to_new_gdt(cpu);
1567
1568 /*
1569 * Set up and load the per-CPU TSS and LDT
1570 */
1571 atomic_inc(&init_mm.mm_count);
1572 curr->active_mm = &init_mm;
1573 BUG_ON(curr->mm);
1574 enter_lazy_tlb(&init_mm, curr);
1575
1576 load_sp0(t, thread);
1577 set_tss_desc(cpu, t);
1578 load_TR_desc();
1579 load_mm_ldt(&init_mm);
1580
1581 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1582
1583#ifdef CONFIG_DOUBLEFAULT
1584 /* Set up doublefault TSS pointer in the GDT */
1585 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1586#endif
1587
1588 clear_all_debug_regs();
1589 dbg_restore_debug_regs();
1590
1591 fpu__init_cpu();
1592}
1593#endif
1594
1595static void bsp_resume(void)
1596{
1597 if (this_cpu->c_bsp_resume)
1598 this_cpu->c_bsp_resume(&boot_cpu_data);
1599}
1600
1601static struct syscore_ops cpu_syscore_ops = {
1602 .resume = bsp_resume,
1603};
1604
1605static int __init init_cpu_syscore(void)
1606{
1607 register_syscore_ops(&cpu_syscore_ops);
1608 return 0;
1609}
1610core_initcall(init_cpu_syscore);
Ubuntu Artful kernel mirror