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kvm: svm: Add support for additional SVM NPF error codes
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
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1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18#define pr_fmt(fmt) "SVM: " fmt
19
20#include <linux/kvm_host.h>
21
22#include "irq.h"
23#include "mmu.h"
24#include "kvm_cache_regs.h"
25#include "x86.h"
26#include "cpuid.h"
27#include "pmu.h"
28
29#include <linux/module.h>
30#include <linux/mod_devicetable.h>
31#include <linux/kernel.h>
32#include <linux/vmalloc.h>
33#include <linux/highmem.h>
34#include <linux/sched.h>
35#include <linux/trace_events.h>
36#include <linux/slab.h>
37#include <linux/amd-iommu.h>
38#include <linux/hashtable.h>
39
40#include <asm/apic.h>
41#include <asm/perf_event.h>
42#include <asm/tlbflush.h>
43#include <asm/desc.h>
44#include <asm/debugreg.h>
45#include <asm/kvm_para.h>
46#include <asm/irq_remapping.h>
47
48#include <asm/virtext.h>
49#include "trace.h"
50
51#define __ex(x) __kvm_handle_fault_on_reboot(x)
52
53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
56static const struct x86_cpu_id svm_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_SVM),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
61
62#define IOPM_ALLOC_ORDER 2
63#define MSRPM_ALLOC_ORDER 1
64
65#define SEG_TYPE_LDT 2
66#define SEG_TYPE_BUSY_TSS16 3
67
68#define SVM_FEATURE_NPT (1 << 0)
69#define SVM_FEATURE_LBRV (1 << 1)
70#define SVM_FEATURE_SVML (1 << 2)
71#define SVM_FEATURE_NRIP (1 << 3)
72#define SVM_FEATURE_TSC_RATE (1 << 4)
73#define SVM_FEATURE_VMCB_CLEAN (1 << 5)
74#define SVM_FEATURE_FLUSH_ASID (1 << 6)
75#define SVM_FEATURE_DECODE_ASSIST (1 << 7)
76#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
77
78#define SVM_AVIC_DOORBELL 0xc001011b
79
80#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
81#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
82#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
83
84#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
85
86#define TSC_RATIO_RSVD 0xffffff0000000000ULL
87#define TSC_RATIO_MIN 0x0000000000000001ULL
88#define TSC_RATIO_MAX 0x000000ffffffffffULL
89
90#define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
91
92/*
93 * 0xff is broadcast, so the max index allowed for physical APIC ID
94 * table is 0xfe. APIC IDs above 0xff are reserved.
95 */
96#define AVIC_MAX_PHYSICAL_ID_COUNT 255
97
98#define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
99#define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
100#define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
101
102/* AVIC GATAG is encoded using VM and VCPU IDs */
103#define AVIC_VCPU_ID_BITS 8
104#define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
105
106#define AVIC_VM_ID_BITS 24
107#define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
108#define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
109
110#define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
111 (y & AVIC_VCPU_ID_MASK))
112#define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
113#define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
114
115static bool erratum_383_found __read_mostly;
116
117static const u32 host_save_user_msrs[] = {
118#ifdef CONFIG_X86_64
119 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
120 MSR_FS_BASE,
121#endif
122 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
123 MSR_TSC_AUX,
124};
125
126#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
127
128struct kvm_vcpu;
129
130struct nested_state {
131 struct vmcb *hsave;
132 u64 hsave_msr;
133 u64 vm_cr_msr;
134 u64 vmcb;
135
136 /* These are the merged vectors */
137 u32 *msrpm;
138
139 /* gpa pointers to the real vectors */
140 u64 vmcb_msrpm;
141 u64 vmcb_iopm;
142
143 /* A VMEXIT is required but not yet emulated */
144 bool exit_required;
145
146 /* cache for intercepts of the guest */
147 u32 intercept_cr;
148 u32 intercept_dr;
149 u32 intercept_exceptions;
150 u64 intercept;
151
152 /* Nested Paging related state */
153 u64 nested_cr3;
154};
155
156#define MSRPM_OFFSETS 16
157static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
158
159/*
160 * Set osvw_len to higher value when updated Revision Guides
161 * are published and we know what the new status bits are
162 */
163static uint64_t osvw_len = 4, osvw_status;
164
165struct vcpu_svm {
166 struct kvm_vcpu vcpu;
167 struct vmcb *vmcb;
168 unsigned long vmcb_pa;
169 struct svm_cpu_data *svm_data;
170 uint64_t asid_generation;
171 uint64_t sysenter_esp;
172 uint64_t sysenter_eip;
173 uint64_t tsc_aux;
174
175 u64 next_rip;
176
177 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
178 struct {
179 u16 fs;
180 u16 gs;
181 u16 ldt;
182 u64 gs_base;
183 } host;
184
185 u32 *msrpm;
186
187 ulong nmi_iret_rip;
188
189 struct nested_state nested;
190
191 bool nmi_singlestep;
192
193 unsigned int3_injected;
194 unsigned long int3_rip;
195 u32 apf_reason;
196
197 /* cached guest cpuid flags for faster access */
198 bool nrips_enabled : 1;
199
200 u32 ldr_reg;
201 struct page *avic_backing_page;
202 u64 *avic_physical_id_cache;
203 bool avic_is_running;
204
205 /*
206 * Per-vcpu list of struct amd_svm_iommu_ir:
207 * This is used mainly to store interrupt remapping information used
208 * when update the vcpu affinity. This avoids the need to scan for
209 * IRTE and try to match ga_tag in the IOMMU driver.
210 */
211 struct list_head ir_list;
212 spinlock_t ir_list_lock;
213};
214
215/*
216 * This is a wrapper of struct amd_iommu_ir_data.
217 */
218struct amd_svm_iommu_ir {
219 struct list_head node; /* Used by SVM for per-vcpu ir_list */
220 void *data; /* Storing pointer to struct amd_ir_data */
221};
222
223#define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
224#define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
225
226#define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
227#define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
228#define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
229#define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
230
231static DEFINE_PER_CPU(u64, current_tsc_ratio);
232#define TSC_RATIO_DEFAULT 0x0100000000ULL
233
234#define MSR_INVALID 0xffffffffU
235
236static const struct svm_direct_access_msrs {
237 u32 index; /* Index of the MSR */
238 bool always; /* True if intercept is always on */
239} direct_access_msrs[] = {
240 { .index = MSR_STAR, .always = true },
241 { .index = MSR_IA32_SYSENTER_CS, .always = true },
242#ifdef CONFIG_X86_64
243 { .index = MSR_GS_BASE, .always = true },
244 { .index = MSR_FS_BASE, .always = true },
245 { .index = MSR_KERNEL_GS_BASE, .always = true },
246 { .index = MSR_LSTAR, .always = true },
247 { .index = MSR_CSTAR, .always = true },
248 { .index = MSR_SYSCALL_MASK, .always = true },
249#endif
250 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
251 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
252 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
253 { .index = MSR_IA32_LASTINTTOIP, .always = false },
254 { .index = MSR_INVALID, .always = false },
255};
256
257/* enable NPT for AMD64 and X86 with PAE */
258#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
259static bool npt_enabled = true;
260#else
261static bool npt_enabled;
262#endif
263
264/* allow nested paging (virtualized MMU) for all guests */
265static int npt = true;
266module_param(npt, int, S_IRUGO);
267
268/* allow nested virtualization in KVM/SVM */
269static int nested = true;
270module_param(nested, int, S_IRUGO);
271
272/* enable / disable AVIC */
273static int avic;
274#ifdef CONFIG_X86_LOCAL_APIC
275module_param(avic, int, S_IRUGO);
276#endif
277
278/* AVIC VM ID bit masks and lock */
279static DECLARE_BITMAP(avic_vm_id_bitmap, AVIC_VM_ID_NR);
280static DEFINE_SPINLOCK(avic_vm_id_lock);
281
282static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
283static void svm_flush_tlb(struct kvm_vcpu *vcpu);
284static void svm_complete_interrupts(struct vcpu_svm *svm);
285
286static int nested_svm_exit_handled(struct vcpu_svm *svm);
287static int nested_svm_intercept(struct vcpu_svm *svm);
288static int nested_svm_vmexit(struct vcpu_svm *svm);
289static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
290 bool has_error_code, u32 error_code);
291
292enum {
293 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
294 pause filter count */
295 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
296 VMCB_ASID, /* ASID */
297 VMCB_INTR, /* int_ctl, int_vector */
298 VMCB_NPT, /* npt_en, nCR3, gPAT */
299 VMCB_CR, /* CR0, CR3, CR4, EFER */
300 VMCB_DR, /* DR6, DR7 */
301 VMCB_DT, /* GDT, IDT */
302 VMCB_SEG, /* CS, DS, SS, ES, CPL */
303 VMCB_CR2, /* CR2 only */
304 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
305 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
306 * AVIC PHYSICAL_TABLE pointer,
307 * AVIC LOGICAL_TABLE pointer
308 */
309 VMCB_DIRTY_MAX,
310};
311
312/* TPR and CR2 are always written before VMRUN */
313#define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
314
315#define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
316
317static inline void mark_all_dirty(struct vmcb *vmcb)
318{
319 vmcb->control.clean = 0;
320}
321
322static inline void mark_all_clean(struct vmcb *vmcb)
323{
324 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
325 & ~VMCB_ALWAYS_DIRTY_MASK;
326}
327
328static inline void mark_dirty(struct vmcb *vmcb, int bit)
329{
330 vmcb->control.clean &= ~(1 << bit);
331}
332
333static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
334{
335 return container_of(vcpu, struct vcpu_svm, vcpu);
336}
337
338static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
339{
340 svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
341 mark_dirty(svm->vmcb, VMCB_AVIC);
342}
343
344static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
345{
346 struct vcpu_svm *svm = to_svm(vcpu);
347 u64 *entry = svm->avic_physical_id_cache;
348
349 if (!entry)
350 return false;
351
352 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
353}
354
355static void recalc_intercepts(struct vcpu_svm *svm)
356{
357 struct vmcb_control_area *c, *h;
358 struct nested_state *g;
359
360 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
361
362 if (!is_guest_mode(&svm->vcpu))
363 return;
364
365 c = &svm->vmcb->control;
366 h = &svm->nested.hsave->control;
367 g = &svm->nested;
368
369 c->intercept_cr = h->intercept_cr | g->intercept_cr;
370 c->intercept_dr = h->intercept_dr | g->intercept_dr;
371 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
372 c->intercept = h->intercept | g->intercept;
373}
374
375static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
376{
377 if (is_guest_mode(&svm->vcpu))
378 return svm->nested.hsave;
379 else
380 return svm->vmcb;
381}
382
383static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
384{
385 struct vmcb *vmcb = get_host_vmcb(svm);
386
387 vmcb->control.intercept_cr |= (1U << bit);
388
389 recalc_intercepts(svm);
390}
391
392static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
393{
394 struct vmcb *vmcb = get_host_vmcb(svm);
395
396 vmcb->control.intercept_cr &= ~(1U << bit);
397
398 recalc_intercepts(svm);
399}
400
401static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
402{
403 struct vmcb *vmcb = get_host_vmcb(svm);
404
405 return vmcb->control.intercept_cr & (1U << bit);
406}
407
408static inline void set_dr_intercepts(struct vcpu_svm *svm)
409{
410 struct vmcb *vmcb = get_host_vmcb(svm);
411
412 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
413 | (1 << INTERCEPT_DR1_READ)
414 | (1 << INTERCEPT_DR2_READ)
415 | (1 << INTERCEPT_DR3_READ)
416 | (1 << INTERCEPT_DR4_READ)
417 | (1 << INTERCEPT_DR5_READ)
418 | (1 << INTERCEPT_DR6_READ)
419 | (1 << INTERCEPT_DR7_READ)
420 | (1 << INTERCEPT_DR0_WRITE)
421 | (1 << INTERCEPT_DR1_WRITE)
422 | (1 << INTERCEPT_DR2_WRITE)
423 | (1 << INTERCEPT_DR3_WRITE)
424 | (1 << INTERCEPT_DR4_WRITE)
425 | (1 << INTERCEPT_DR5_WRITE)
426 | (1 << INTERCEPT_DR6_WRITE)
427 | (1 << INTERCEPT_DR7_WRITE);
428
429 recalc_intercepts(svm);
430}
431
432static inline void clr_dr_intercepts(struct vcpu_svm *svm)
433{
434 struct vmcb *vmcb = get_host_vmcb(svm);
435
436 vmcb->control.intercept_dr = 0;
437
438 recalc_intercepts(svm);
439}
440
441static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
442{
443 struct vmcb *vmcb = get_host_vmcb(svm);
444
445 vmcb->control.intercept_exceptions |= (1U << bit);
446
447 recalc_intercepts(svm);
448}
449
450static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
451{
452 struct vmcb *vmcb = get_host_vmcb(svm);
453
454 vmcb->control.intercept_exceptions &= ~(1U << bit);
455
456 recalc_intercepts(svm);
457}
458
459static inline void set_intercept(struct vcpu_svm *svm, int bit)
460{
461 struct vmcb *vmcb = get_host_vmcb(svm);
462
463 vmcb->control.intercept |= (1ULL << bit);
464
465 recalc_intercepts(svm);
466}
467
468static inline void clr_intercept(struct vcpu_svm *svm, int bit)
469{
470 struct vmcb *vmcb = get_host_vmcb(svm);
471
472 vmcb->control.intercept &= ~(1ULL << bit);
473
474 recalc_intercepts(svm);
475}
476
477static inline void enable_gif(struct vcpu_svm *svm)
478{
479 svm->vcpu.arch.hflags |= HF_GIF_MASK;
480}
481
482static inline void disable_gif(struct vcpu_svm *svm)
483{
484 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
485}
486
487static inline bool gif_set(struct vcpu_svm *svm)
488{
489 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
490}
491
492static unsigned long iopm_base;
493
494struct kvm_ldttss_desc {
495 u16 limit0;
496 u16 base0;
497 unsigned base1:8, type:5, dpl:2, p:1;
498 unsigned limit1:4, zero0:3, g:1, base2:8;
499 u32 base3;
500 u32 zero1;
501} __attribute__((packed));
502
503struct svm_cpu_data {
504 int cpu;
505
506 u64 asid_generation;
507 u32 max_asid;
508 u32 next_asid;
509 struct kvm_ldttss_desc *tss_desc;
510
511 struct page *save_area;
512};
513
514static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
515
516struct svm_init_data {
517 int cpu;
518 int r;
519};
520
521static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
522
523#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
524#define MSRS_RANGE_SIZE 2048
525#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
526
527static u32 svm_msrpm_offset(u32 msr)
528{
529 u32 offset;
530 int i;
531
532 for (i = 0; i < NUM_MSR_MAPS; i++) {
533 if (msr < msrpm_ranges[i] ||
534 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
535 continue;
536
537 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
538 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
539
540 /* Now we have the u8 offset - but need the u32 offset */
541 return offset / 4;
542 }
543
544 /* MSR not in any range */
545 return MSR_INVALID;
546}
547
548#define MAX_INST_SIZE 15
549
550static inline void clgi(void)
551{
552 asm volatile (__ex(SVM_CLGI));
553}
554
555static inline void stgi(void)
556{
557 asm volatile (__ex(SVM_STGI));
558}
559
560static inline void invlpga(unsigned long addr, u32 asid)
561{
562 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
563}
564
565static int get_npt_level(void)
566{
567#ifdef CONFIG_X86_64
568 return PT64_ROOT_LEVEL;
569#else
570 return PT32E_ROOT_LEVEL;
571#endif
572}
573
574static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
575{
576 vcpu->arch.efer = efer;
577 if (!npt_enabled && !(efer & EFER_LMA))
578 efer &= ~EFER_LME;
579
580 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
581 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
582}
583
584static int is_external_interrupt(u32 info)
585{
586 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
587 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
588}
589
590static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
591{
592 struct vcpu_svm *svm = to_svm(vcpu);
593 u32 ret = 0;
594
595 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
596 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
597 return ret;
598}
599
600static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
601{
602 struct vcpu_svm *svm = to_svm(vcpu);
603
604 if (mask == 0)
605 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
606 else
607 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
608
609}
610
611static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
612{
613 struct vcpu_svm *svm = to_svm(vcpu);
614
615 if (svm->vmcb->control.next_rip != 0) {
616 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
617 svm->next_rip = svm->vmcb->control.next_rip;
618 }
619
620 if (!svm->next_rip) {
621 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
622 EMULATE_DONE)
623 printk(KERN_DEBUG "%s: NOP\n", __func__);
624 return;
625 }
626 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
627 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
628 __func__, kvm_rip_read(vcpu), svm->next_rip);
629
630 kvm_rip_write(vcpu, svm->next_rip);
631 svm_set_interrupt_shadow(vcpu, 0);
632}
633
634static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
635 bool has_error_code, u32 error_code,
636 bool reinject)
637{
638 struct vcpu_svm *svm = to_svm(vcpu);
639
640 /*
641 * If we are within a nested VM we'd better #VMEXIT and let the guest
642 * handle the exception
643 */
644 if (!reinject &&
645 nested_svm_check_exception(svm, nr, has_error_code, error_code))
646 return;
647
648 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
649 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
650
651 /*
652 * For guest debugging where we have to reinject #BP if some
653 * INT3 is guest-owned:
654 * Emulate nRIP by moving RIP forward. Will fail if injection
655 * raises a fault that is not intercepted. Still better than
656 * failing in all cases.
657 */
658 skip_emulated_instruction(&svm->vcpu);
659 rip = kvm_rip_read(&svm->vcpu);
660 svm->int3_rip = rip + svm->vmcb->save.cs.base;
661 svm->int3_injected = rip - old_rip;
662 }
663
664 svm->vmcb->control.event_inj = nr
665 | SVM_EVTINJ_VALID
666 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
667 | SVM_EVTINJ_TYPE_EXEPT;
668 svm->vmcb->control.event_inj_err = error_code;
669}
670
671static void svm_init_erratum_383(void)
672{
673 u32 low, high;
674 int err;
675 u64 val;
676
677 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
678 return;
679
680 /* Use _safe variants to not break nested virtualization */
681 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
682 if (err)
683 return;
684
685 val |= (1ULL << 47);
686
687 low = lower_32_bits(val);
688 high = upper_32_bits(val);
689
690 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
691
692 erratum_383_found = true;
693}
694
695static void svm_init_osvw(struct kvm_vcpu *vcpu)
696{
697 /*
698 * Guests should see errata 400 and 415 as fixed (assuming that
699 * HLT and IO instructions are intercepted).
700 */
701 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
702 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
703
704 /*
705 * By increasing VCPU's osvw.length to 3 we are telling the guest that
706 * all osvw.status bits inside that length, including bit 0 (which is
707 * reserved for erratum 298), are valid. However, if host processor's
708 * osvw_len is 0 then osvw_status[0] carries no information. We need to
709 * be conservative here and therefore we tell the guest that erratum 298
710 * is present (because we really don't know).
711 */
712 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
713 vcpu->arch.osvw.status |= 1;
714}
715
716static int has_svm(void)
717{
718 const char *msg;
719
720 if (!cpu_has_svm(&msg)) {
721 printk(KERN_INFO "has_svm: %s\n", msg);
722 return 0;
723 }
724
725 return 1;
726}
727
728static void svm_hardware_disable(void)
729{
730 /* Make sure we clean up behind us */
731 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
732 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
733
734 cpu_svm_disable();
735
736 amd_pmu_disable_virt();
737}
738
739static int svm_hardware_enable(void)
740{
741
742 struct svm_cpu_data *sd;
743 uint64_t efer;
744 struct desc_ptr gdt_descr;
745 struct desc_struct *gdt;
746 int me = raw_smp_processor_id();
747
748 rdmsrl(MSR_EFER, efer);
749 if (efer & EFER_SVME)
750 return -EBUSY;
751
752 if (!has_svm()) {
753 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
754 return -EINVAL;
755 }
756 sd = per_cpu(svm_data, me);
757 if (!sd) {
758 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
759 return -EINVAL;
760 }
761
762 sd->asid_generation = 1;
763 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
764 sd->next_asid = sd->max_asid + 1;
765
766 native_store_gdt(&gdt_descr);
767 gdt = (struct desc_struct *)gdt_descr.address;
768 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
769
770 wrmsrl(MSR_EFER, efer | EFER_SVME);
771
772 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
773
774 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
775 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
776 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
777 }
778
779
780 /*
781 * Get OSVW bits.
782 *
783 * Note that it is possible to have a system with mixed processor
784 * revisions and therefore different OSVW bits. If bits are not the same
785 * on different processors then choose the worst case (i.e. if erratum
786 * is present on one processor and not on another then assume that the
787 * erratum is present everywhere).
788 */
789 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
790 uint64_t len, status = 0;
791 int err;
792
793 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
794 if (!err)
795 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
796 &err);
797
798 if (err)
799 osvw_status = osvw_len = 0;
800 else {
801 if (len < osvw_len)
802 osvw_len = len;
803 osvw_status |= status;
804 osvw_status &= (1ULL << osvw_len) - 1;
805 }
806 } else
807 osvw_status = osvw_len = 0;
808
809 svm_init_erratum_383();
810
811 amd_pmu_enable_virt();
812
813 return 0;
814}
815
816static void svm_cpu_uninit(int cpu)
817{
818 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
819
820 if (!sd)
821 return;
822
823 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
824 __free_page(sd->save_area);
825 kfree(sd);
826}
827
828static int svm_cpu_init(int cpu)
829{
830 struct svm_cpu_data *sd;
831 int r;
832
833 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
834 if (!sd)
835 return -ENOMEM;
836 sd->cpu = cpu;
837 sd->save_area = alloc_page(GFP_KERNEL);
838 r = -ENOMEM;
839 if (!sd->save_area)
840 goto err_1;
841
842 per_cpu(svm_data, cpu) = sd;
843
844 return 0;
845
846err_1:
847 kfree(sd);
848 return r;
849
850}
851
852static bool valid_msr_intercept(u32 index)
853{
854 int i;
855
856 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
857 if (direct_access_msrs[i].index == index)
858 return true;
859
860 return false;
861}
862
863static void set_msr_interception(u32 *msrpm, unsigned msr,
864 int read, int write)
865{
866 u8 bit_read, bit_write;
867 unsigned long tmp;
868 u32 offset;
869
870 /*
871 * If this warning triggers extend the direct_access_msrs list at the
872 * beginning of the file
873 */
874 WARN_ON(!valid_msr_intercept(msr));
875
876 offset = svm_msrpm_offset(msr);
877 bit_read = 2 * (msr & 0x0f);
878 bit_write = 2 * (msr & 0x0f) + 1;
879 tmp = msrpm[offset];
880
881 BUG_ON(offset == MSR_INVALID);
882
883 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
884 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
885
886 msrpm[offset] = tmp;
887}
888
889static void svm_vcpu_init_msrpm(u32 *msrpm)
890{
891 int i;
892
893 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
894
895 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
896 if (!direct_access_msrs[i].always)
897 continue;
898
899 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
900 }
901}
902
903static void add_msr_offset(u32 offset)
904{
905 int i;
906
907 for (i = 0; i < MSRPM_OFFSETS; ++i) {
908
909 /* Offset already in list? */
910 if (msrpm_offsets[i] == offset)
911 return;
912
913 /* Slot used by another offset? */
914 if (msrpm_offsets[i] != MSR_INVALID)
915 continue;
916
917 /* Add offset to list */
918 msrpm_offsets[i] = offset;
919
920 return;
921 }
922
923 /*
924 * If this BUG triggers the msrpm_offsets table has an overflow. Just
925 * increase MSRPM_OFFSETS in this case.
926 */
927 BUG();
928}
929
930static void init_msrpm_offsets(void)
931{
932 int i;
933
934 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
935
936 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
937 u32 offset;
938
939 offset = svm_msrpm_offset(direct_access_msrs[i].index);
940 BUG_ON(offset == MSR_INVALID);
941
942 add_msr_offset(offset);
943 }
944}
945
946static void svm_enable_lbrv(struct vcpu_svm *svm)
947{
948 u32 *msrpm = svm->msrpm;
949
950 svm->vmcb->control.lbr_ctl = 1;
951 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
952 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
953 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
954 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
955}
956
957static void svm_disable_lbrv(struct vcpu_svm *svm)
958{
959 u32 *msrpm = svm->msrpm;
960
961 svm->vmcb->control.lbr_ctl = 0;
962 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
963 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
964 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
965 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
966}
967
968/* Note:
969 * This hash table is used to map VM_ID to a struct kvm_arch,
970 * when handling AMD IOMMU GALOG notification to schedule in
971 * a particular vCPU.
972 */
973#define SVM_VM_DATA_HASH_BITS 8
974DECLARE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
975static spinlock_t svm_vm_data_hash_lock;
976
977/* Note:
978 * This function is called from IOMMU driver to notify
979 * SVM to schedule in a particular vCPU of a particular VM.
980 */
981static int avic_ga_log_notifier(u32 ga_tag)
982{
983 unsigned long flags;
984 struct kvm_arch *ka = NULL;
985 struct kvm_vcpu *vcpu = NULL;
986 u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
987 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
988
989 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
990
991 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
992 hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) {
993 struct kvm *kvm = container_of(ka, struct kvm, arch);
994 struct kvm_arch *vm_data = &kvm->arch;
995
996 if (vm_data->avic_vm_id != vm_id)
997 continue;
998 vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
999 break;
1000 }
1001 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1002
1003 if (!vcpu)
1004 return 0;
1005
1006 /* Note:
1007 * At this point, the IOMMU should have already set the pending
1008 * bit in the vAPIC backing page. So, we just need to schedule
1009 * in the vcpu.
1010 */
1011 if (vcpu->mode == OUTSIDE_GUEST_MODE)
1012 kvm_vcpu_wake_up(vcpu);
1013
1014 return 0;
1015}
1016
1017static __init int svm_hardware_setup(void)
1018{
1019 int cpu;
1020 struct page *iopm_pages;
1021 void *iopm_va;
1022 int r;
1023
1024 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1025
1026 if (!iopm_pages)
1027 return -ENOMEM;
1028
1029 iopm_va = page_address(iopm_pages);
1030 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1031 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1032
1033 init_msrpm_offsets();
1034
1035 if (boot_cpu_has(X86_FEATURE_NX))
1036 kvm_enable_efer_bits(EFER_NX);
1037
1038 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1039 kvm_enable_efer_bits(EFER_FFXSR);
1040
1041 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1042 kvm_has_tsc_control = true;
1043 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1044 kvm_tsc_scaling_ratio_frac_bits = 32;
1045 }
1046
1047 if (nested) {
1048 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1049 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1050 }
1051
1052 for_each_possible_cpu(cpu) {
1053 r = svm_cpu_init(cpu);
1054 if (r)
1055 goto err;
1056 }
1057
1058 if (!boot_cpu_has(X86_FEATURE_NPT))
1059 npt_enabled = false;
1060
1061 if (npt_enabled && !npt) {
1062 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1063 npt_enabled = false;
1064 }
1065
1066 if (npt_enabled) {
1067 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1068 kvm_enable_tdp();
1069 } else
1070 kvm_disable_tdp();
1071
1072 if (avic) {
1073 if (!npt_enabled ||
1074 !boot_cpu_has(X86_FEATURE_AVIC) ||
1075 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1076 avic = false;
1077 } else {
1078 pr_info("AVIC enabled\n");
1079
1080 hash_init(svm_vm_data_hash);
1081 spin_lock_init(&svm_vm_data_hash_lock);
1082 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1083 }
1084 }
1085
1086 return 0;
1087
1088err:
1089 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1090 iopm_base = 0;
1091 return r;
1092}
1093
1094static __exit void svm_hardware_unsetup(void)
1095{
1096 int cpu;
1097
1098 for_each_possible_cpu(cpu)
1099 svm_cpu_uninit(cpu);
1100
1101 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1102 iopm_base = 0;
1103}
1104
1105static void init_seg(struct vmcb_seg *seg)
1106{
1107 seg->selector = 0;
1108 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1109 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1110 seg->limit = 0xffff;
1111 seg->base = 0;
1112}
1113
1114static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1115{
1116 seg->selector = 0;
1117 seg->attrib = SVM_SELECTOR_P_MASK | type;
1118 seg->limit = 0xffff;
1119 seg->base = 0;
1120}
1121
1122static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1123{
1124 struct vcpu_svm *svm = to_svm(vcpu);
1125 u64 g_tsc_offset = 0;
1126
1127 if (is_guest_mode(vcpu)) {
1128 g_tsc_offset = svm->vmcb->control.tsc_offset -
1129 svm->nested.hsave->control.tsc_offset;
1130 svm->nested.hsave->control.tsc_offset = offset;
1131 } else
1132 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1133 svm->vmcb->control.tsc_offset,
1134 offset);
1135
1136 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1137
1138 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1139}
1140
1141static void avic_init_vmcb(struct vcpu_svm *svm)
1142{
1143 struct vmcb *vmcb = svm->vmcb;
1144 struct kvm_arch *vm_data = &svm->vcpu.kvm->arch;
1145 phys_addr_t bpa = page_to_phys(svm->avic_backing_page);
1146 phys_addr_t lpa = page_to_phys(vm_data->avic_logical_id_table_page);
1147 phys_addr_t ppa = page_to_phys(vm_data->avic_physical_id_table_page);
1148
1149 vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1150 vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1151 vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1152 vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1153 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1154 svm->vcpu.arch.apicv_active = true;
1155}
1156
1157static void init_vmcb(struct vcpu_svm *svm)
1158{
1159 struct vmcb_control_area *control = &svm->vmcb->control;
1160 struct vmcb_save_area *save = &svm->vmcb->save;
1161
1162 svm->vcpu.fpu_active = 1;
1163 svm->vcpu.arch.hflags = 0;
1164
1165 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1166 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1167 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1168 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1169 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1170 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1171 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1172 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1173
1174 set_dr_intercepts(svm);
1175
1176 set_exception_intercept(svm, PF_VECTOR);
1177 set_exception_intercept(svm, UD_VECTOR);
1178 set_exception_intercept(svm, MC_VECTOR);
1179 set_exception_intercept(svm, AC_VECTOR);
1180 set_exception_intercept(svm, DB_VECTOR);
1181
1182 set_intercept(svm, INTERCEPT_INTR);
1183 set_intercept(svm, INTERCEPT_NMI);
1184 set_intercept(svm, INTERCEPT_SMI);
1185 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1186 set_intercept(svm, INTERCEPT_RDPMC);
1187 set_intercept(svm, INTERCEPT_CPUID);
1188 set_intercept(svm, INTERCEPT_INVD);
1189 set_intercept(svm, INTERCEPT_HLT);
1190 set_intercept(svm, INTERCEPT_INVLPG);
1191 set_intercept(svm, INTERCEPT_INVLPGA);
1192 set_intercept(svm, INTERCEPT_IOIO_PROT);
1193 set_intercept(svm, INTERCEPT_MSR_PROT);
1194 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1195 set_intercept(svm, INTERCEPT_SHUTDOWN);
1196 set_intercept(svm, INTERCEPT_VMRUN);
1197 set_intercept(svm, INTERCEPT_VMMCALL);
1198 set_intercept(svm, INTERCEPT_VMLOAD);
1199 set_intercept(svm, INTERCEPT_VMSAVE);
1200 set_intercept(svm, INTERCEPT_STGI);
1201 set_intercept(svm, INTERCEPT_CLGI);
1202 set_intercept(svm, INTERCEPT_SKINIT);
1203 set_intercept(svm, INTERCEPT_WBINVD);
1204 set_intercept(svm, INTERCEPT_MONITOR);
1205 set_intercept(svm, INTERCEPT_MWAIT);
1206 set_intercept(svm, INTERCEPT_XSETBV);
1207
1208 control->iopm_base_pa = iopm_base;
1209 control->msrpm_base_pa = __pa(svm->msrpm);
1210 control->int_ctl = V_INTR_MASKING_MASK;
1211
1212 init_seg(&save->es);
1213 init_seg(&save->ss);
1214 init_seg(&save->ds);
1215 init_seg(&save->fs);
1216 init_seg(&save->gs);
1217
1218 save->cs.selector = 0xf000;
1219 save->cs.base = 0xffff0000;
1220 /* Executable/Readable Code Segment */
1221 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1222 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1223 save->cs.limit = 0xffff;
1224
1225 save->gdtr.limit = 0xffff;
1226 save->idtr.limit = 0xffff;
1227
1228 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1229 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1230
1231 svm_set_efer(&svm->vcpu, 0);
1232 save->dr6 = 0xffff0ff0;
1233 kvm_set_rflags(&svm->vcpu, 2);
1234 save->rip = 0x0000fff0;
1235 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1236
1237 /*
1238 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1239 * It also updates the guest-visible cr0 value.
1240 */
1241 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1242 kvm_mmu_reset_context(&svm->vcpu);
1243
1244 save->cr4 = X86_CR4_PAE;
1245 /* rdx = ?? */
1246
1247 if (npt_enabled) {
1248 /* Setup VMCB for Nested Paging */
1249 control->nested_ctl = 1;
1250 clr_intercept(svm, INTERCEPT_INVLPG);
1251 clr_exception_intercept(svm, PF_VECTOR);
1252 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1253 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1254 save->g_pat = svm->vcpu.arch.pat;
1255 save->cr3 = 0;
1256 save->cr4 = 0;
1257 }
1258 svm->asid_generation = 0;
1259
1260 svm->nested.vmcb = 0;
1261 svm->vcpu.arch.hflags = 0;
1262
1263 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1264 control->pause_filter_count = 3000;
1265 set_intercept(svm, INTERCEPT_PAUSE);
1266 }
1267
1268 if (avic)
1269 avic_init_vmcb(svm);
1270
1271 mark_all_dirty(svm->vmcb);
1272
1273 enable_gif(svm);
1274
1275}
1276
1277static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu, int index)
1278{
1279 u64 *avic_physical_id_table;
1280 struct kvm_arch *vm_data = &vcpu->kvm->arch;
1281
1282 if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1283 return NULL;
1284
1285 avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page);
1286
1287 return &avic_physical_id_table[index];
1288}
1289
1290/**
1291 * Note:
1292 * AVIC hardware walks the nested page table to check permissions,
1293 * but does not use the SPA address specified in the leaf page
1294 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1295 * field of the VMCB. Therefore, we set up the
1296 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1297 */
1298static int avic_init_access_page(struct kvm_vcpu *vcpu)
1299{
1300 struct kvm *kvm = vcpu->kvm;
1301 int ret;
1302
1303 if (kvm->arch.apic_access_page_done)
1304 return 0;
1305
1306 ret = x86_set_memory_region(kvm,
1307 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1308 APIC_DEFAULT_PHYS_BASE,
1309 PAGE_SIZE);
1310 if (ret)
1311 return ret;
1312
1313 kvm->arch.apic_access_page_done = true;
1314 return 0;
1315}
1316
1317static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1318{
1319 int ret;
1320 u64 *entry, new_entry;
1321 int id = vcpu->vcpu_id;
1322 struct vcpu_svm *svm = to_svm(vcpu);
1323
1324 ret = avic_init_access_page(vcpu);
1325 if (ret)
1326 return ret;
1327
1328 if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1329 return -EINVAL;
1330
1331 if (!svm->vcpu.arch.apic->regs)
1332 return -EINVAL;
1333
1334 svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1335
1336 /* Setting AVIC backing page address in the phy APIC ID table */
1337 entry = avic_get_physical_id_entry(vcpu, id);
1338 if (!entry)
1339 return -EINVAL;
1340
1341 new_entry = READ_ONCE(*entry);
1342 new_entry = (page_to_phys(svm->avic_backing_page) &
1343 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1344 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK;
1345 WRITE_ONCE(*entry, new_entry);
1346
1347 svm->avic_physical_id_cache = entry;
1348
1349 return 0;
1350}
1351
1352static inline int avic_get_next_vm_id(void)
1353{
1354 int id;
1355
1356 spin_lock(&avic_vm_id_lock);
1357
1358 /* AVIC VM ID is one-based. */
1359 id = find_next_zero_bit(avic_vm_id_bitmap, AVIC_VM_ID_NR, 1);
1360 if (id <= AVIC_VM_ID_MASK)
1361 __set_bit(id, avic_vm_id_bitmap);
1362 else
1363 id = -EAGAIN;
1364
1365 spin_unlock(&avic_vm_id_lock);
1366 return id;
1367}
1368
1369static inline int avic_free_vm_id(int id)
1370{
1371 if (id <= 0 || id > AVIC_VM_ID_MASK)
1372 return -EINVAL;
1373
1374 spin_lock(&avic_vm_id_lock);
1375 __clear_bit(id, avic_vm_id_bitmap);
1376 spin_unlock(&avic_vm_id_lock);
1377 return 0;
1378}
1379
1380static void avic_vm_destroy(struct kvm *kvm)
1381{
1382 unsigned long flags;
1383 struct kvm_arch *vm_data = &kvm->arch;
1384
1385 avic_free_vm_id(vm_data->avic_vm_id);
1386
1387 if (vm_data->avic_logical_id_table_page)
1388 __free_page(vm_data->avic_logical_id_table_page);
1389 if (vm_data->avic_physical_id_table_page)
1390 __free_page(vm_data->avic_physical_id_table_page);
1391
1392 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1393 hash_del(&vm_data->hnode);
1394 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1395}
1396
1397static int avic_vm_init(struct kvm *kvm)
1398{
1399 unsigned long flags;
1400 int vm_id, err = -ENOMEM;
1401 struct kvm_arch *vm_data = &kvm->arch;
1402 struct page *p_page;
1403 struct page *l_page;
1404
1405 if (!avic)
1406 return 0;
1407
1408 vm_id = avic_get_next_vm_id();
1409 if (vm_id < 0)
1410 return vm_id;
1411 vm_data->avic_vm_id = (u32)vm_id;
1412
1413 /* Allocating physical APIC ID table (4KB) */
1414 p_page = alloc_page(GFP_KERNEL);
1415 if (!p_page)
1416 goto free_avic;
1417
1418 vm_data->avic_physical_id_table_page = p_page;
1419 clear_page(page_address(p_page));
1420
1421 /* Allocating logical APIC ID table (4KB) */
1422 l_page = alloc_page(GFP_KERNEL);
1423 if (!l_page)
1424 goto free_avic;
1425
1426 vm_data->avic_logical_id_table_page = l_page;
1427 clear_page(page_address(l_page));
1428
1429 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1430 hash_add(svm_vm_data_hash, &vm_data->hnode, vm_data->avic_vm_id);
1431 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1432
1433 return 0;
1434
1435free_avic:
1436 avic_vm_destroy(kvm);
1437 return err;
1438}
1439
1440static inline int
1441avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1442{
1443 int ret = 0;
1444 unsigned long flags;
1445 struct amd_svm_iommu_ir *ir;
1446 struct vcpu_svm *svm = to_svm(vcpu);
1447
1448 if (!kvm_arch_has_assigned_device(vcpu->kvm))
1449 return 0;
1450
1451 /*
1452 * Here, we go through the per-vcpu ir_list to update all existing
1453 * interrupt remapping table entry targeting this vcpu.
1454 */
1455 spin_lock_irqsave(&svm->ir_list_lock, flags);
1456
1457 if (list_empty(&svm->ir_list))
1458 goto out;
1459
1460 list_for_each_entry(ir, &svm->ir_list, node) {
1461 ret = amd_iommu_update_ga(cpu, r, ir->data);
1462 if (ret)
1463 break;
1464 }
1465out:
1466 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
1467 return ret;
1468}
1469
1470static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1471{
1472 u64 entry;
1473 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1474 int h_physical_id = kvm_cpu_get_apicid(cpu);
1475 struct vcpu_svm *svm = to_svm(vcpu);
1476
1477 if (!kvm_vcpu_apicv_active(vcpu))
1478 return;
1479
1480 if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
1481 return;
1482
1483 entry = READ_ONCE(*(svm->avic_physical_id_cache));
1484 WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
1485
1486 entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
1487 entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
1488
1489 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1490 if (svm->avic_is_running)
1491 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1492
1493 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1494 avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
1495 svm->avic_is_running);
1496}
1497
1498static void avic_vcpu_put(struct kvm_vcpu *vcpu)
1499{
1500 u64 entry;
1501 struct vcpu_svm *svm = to_svm(vcpu);
1502
1503 if (!kvm_vcpu_apicv_active(vcpu))
1504 return;
1505
1506 entry = READ_ONCE(*(svm->avic_physical_id_cache));
1507 if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
1508 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
1509
1510 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1511 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1512}
1513
1514/**
1515 * This function is called during VCPU halt/unhalt.
1516 */
1517static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
1518{
1519 struct vcpu_svm *svm = to_svm(vcpu);
1520
1521 svm->avic_is_running = is_run;
1522 if (is_run)
1523 avic_vcpu_load(vcpu, vcpu->cpu);
1524 else
1525 avic_vcpu_put(vcpu);
1526}
1527
1528static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1529{
1530 struct vcpu_svm *svm = to_svm(vcpu);
1531 u32 dummy;
1532 u32 eax = 1;
1533
1534 if (!init_event) {
1535 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1536 MSR_IA32_APICBASE_ENABLE;
1537 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1538 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1539 }
1540 init_vmcb(svm);
1541
1542 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1543 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1544
1545 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1546 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1547}
1548
1549static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1550{
1551 struct vcpu_svm *svm;
1552 struct page *page;
1553 struct page *msrpm_pages;
1554 struct page *hsave_page;
1555 struct page *nested_msrpm_pages;
1556 int err;
1557
1558 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1559 if (!svm) {
1560 err = -ENOMEM;
1561 goto out;
1562 }
1563
1564 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1565 if (err)
1566 goto free_svm;
1567
1568 err = -ENOMEM;
1569 page = alloc_page(GFP_KERNEL);
1570 if (!page)
1571 goto uninit;
1572
1573 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1574 if (!msrpm_pages)
1575 goto free_page1;
1576
1577 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1578 if (!nested_msrpm_pages)
1579 goto free_page2;
1580
1581 hsave_page = alloc_page(GFP_KERNEL);
1582 if (!hsave_page)
1583 goto free_page3;
1584
1585 if (avic) {
1586 err = avic_init_backing_page(&svm->vcpu);
1587 if (err)
1588 goto free_page4;
1589
1590 INIT_LIST_HEAD(&svm->ir_list);
1591 spin_lock_init(&svm->ir_list_lock);
1592 }
1593
1594 /* We initialize this flag to true to make sure that the is_running
1595 * bit would be set the first time the vcpu is loaded.
1596 */
1597 svm->avic_is_running = true;
1598
1599 svm->nested.hsave = page_address(hsave_page);
1600
1601 svm->msrpm = page_address(msrpm_pages);
1602 svm_vcpu_init_msrpm(svm->msrpm);
1603
1604 svm->nested.msrpm = page_address(nested_msrpm_pages);
1605 svm_vcpu_init_msrpm(svm->nested.msrpm);
1606
1607 svm->vmcb = page_address(page);
1608 clear_page(svm->vmcb);
1609 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1610 svm->asid_generation = 0;
1611 init_vmcb(svm);
1612
1613 svm_init_osvw(&svm->vcpu);
1614
1615 return &svm->vcpu;
1616
1617free_page4:
1618 __free_page(hsave_page);
1619free_page3:
1620 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1621free_page2:
1622 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1623free_page1:
1624 __free_page(page);
1625uninit:
1626 kvm_vcpu_uninit(&svm->vcpu);
1627free_svm:
1628 kmem_cache_free(kvm_vcpu_cache, svm);
1629out:
1630 return ERR_PTR(err);
1631}
1632
1633static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1634{
1635 struct vcpu_svm *svm = to_svm(vcpu);
1636
1637 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1638 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1639 __free_page(virt_to_page(svm->nested.hsave));
1640 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1641 kvm_vcpu_uninit(vcpu);
1642 kmem_cache_free(kvm_vcpu_cache, svm);
1643}
1644
1645static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1646{
1647 struct vcpu_svm *svm = to_svm(vcpu);
1648 int i;
1649
1650 if (unlikely(cpu != vcpu->cpu)) {
1651 svm->asid_generation = 0;
1652 mark_all_dirty(svm->vmcb);
1653 }
1654
1655#ifdef CONFIG_X86_64
1656 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1657#endif
1658 savesegment(fs, svm->host.fs);
1659 savesegment(gs, svm->host.gs);
1660 svm->host.ldt = kvm_read_ldt();
1661
1662 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1663 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1664
1665 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1666 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1667 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1668 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1669 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1670 }
1671 }
1672 /* This assumes that the kernel never uses MSR_TSC_AUX */
1673 if (static_cpu_has(X86_FEATURE_RDTSCP))
1674 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1675
1676 avic_vcpu_load(vcpu, cpu);
1677}
1678
1679static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1680{
1681 struct vcpu_svm *svm = to_svm(vcpu);
1682 int i;
1683
1684 avic_vcpu_put(vcpu);
1685
1686 ++vcpu->stat.host_state_reload;
1687 kvm_load_ldt(svm->host.ldt);
1688#ifdef CONFIG_X86_64
1689 loadsegment(fs, svm->host.fs);
1690 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1691 load_gs_index(svm->host.gs);
1692#else
1693#ifdef CONFIG_X86_32_LAZY_GS
1694 loadsegment(gs, svm->host.gs);
1695#endif
1696#endif
1697 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1698 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1699}
1700
1701static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
1702{
1703 avic_set_running(vcpu, false);
1704}
1705
1706static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
1707{
1708 avic_set_running(vcpu, true);
1709}
1710
1711static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1712{
1713 return to_svm(vcpu)->vmcb->save.rflags;
1714}
1715
1716static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1717{
1718 /*
1719 * Any change of EFLAGS.VM is accompanied by a reload of SS
1720 * (caused by either a task switch or an inter-privilege IRET),
1721 * so we do not need to update the CPL here.
1722 */
1723 to_svm(vcpu)->vmcb->save.rflags = rflags;
1724}
1725
1726static u32 svm_get_pkru(struct kvm_vcpu *vcpu)
1727{
1728 return 0;
1729}
1730
1731static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1732{
1733 switch (reg) {
1734 case VCPU_EXREG_PDPTR:
1735 BUG_ON(!npt_enabled);
1736 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1737 break;
1738 default:
1739 BUG();
1740 }
1741}
1742
1743static void svm_set_vintr(struct vcpu_svm *svm)
1744{
1745 set_intercept(svm, INTERCEPT_VINTR);
1746}
1747
1748static void svm_clear_vintr(struct vcpu_svm *svm)
1749{
1750 clr_intercept(svm, INTERCEPT_VINTR);
1751}
1752
1753static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1754{
1755 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1756
1757 switch (seg) {
1758 case VCPU_SREG_CS: return &save->cs;
1759 case VCPU_SREG_DS: return &save->ds;
1760 case VCPU_SREG_ES: return &save->es;
1761 case VCPU_SREG_FS: return &save->fs;
1762 case VCPU_SREG_GS: return &save->gs;
1763 case VCPU_SREG_SS: return &save->ss;
1764 case VCPU_SREG_TR: return &save->tr;
1765 case VCPU_SREG_LDTR: return &save->ldtr;
1766 }
1767 BUG();
1768 return NULL;
1769}
1770
1771static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1772{
1773 struct vmcb_seg *s = svm_seg(vcpu, seg);
1774
1775 return s->base;
1776}
1777
1778static void svm_get_segment(struct kvm_vcpu *vcpu,
1779 struct kvm_segment *var, int seg)
1780{
1781 struct vmcb_seg *s = svm_seg(vcpu, seg);
1782
1783 var->base = s->base;
1784 var->limit = s->limit;
1785 var->selector = s->selector;
1786 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1787 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1788 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1789 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1790 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1791 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1792 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1793
1794 /*
1795 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1796 * However, the SVM spec states that the G bit is not observed by the
1797 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1798 * So let's synthesize a legal G bit for all segments, this helps
1799 * running KVM nested. It also helps cross-vendor migration, because
1800 * Intel's vmentry has a check on the 'G' bit.
1801 */
1802 var->g = s->limit > 0xfffff;
1803
1804 /*
1805 * AMD's VMCB does not have an explicit unusable field, so emulate it
1806 * for cross vendor migration purposes by "not present"
1807 */
1808 var->unusable = !var->present || (var->type == 0);
1809
1810 switch (seg) {
1811 case VCPU_SREG_TR:
1812 /*
1813 * Work around a bug where the busy flag in the tr selector
1814 * isn't exposed
1815 */
1816 var->type |= 0x2;
1817 break;
1818 case VCPU_SREG_DS:
1819 case VCPU_SREG_ES:
1820 case VCPU_SREG_FS:
1821 case VCPU_SREG_GS:
1822 /*
1823 * The accessed bit must always be set in the segment
1824 * descriptor cache, although it can be cleared in the
1825 * descriptor, the cached bit always remains at 1. Since
1826 * Intel has a check on this, set it here to support
1827 * cross-vendor migration.
1828 */
1829 if (!var->unusable)
1830 var->type |= 0x1;
1831 break;
1832 case VCPU_SREG_SS:
1833 /*
1834 * On AMD CPUs sometimes the DB bit in the segment
1835 * descriptor is left as 1, although the whole segment has
1836 * been made unusable. Clear it here to pass an Intel VMX
1837 * entry check when cross vendor migrating.
1838 */
1839 if (var->unusable)
1840 var->db = 0;
1841 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1842 break;
1843 }
1844}
1845
1846static int svm_get_cpl(struct kvm_vcpu *vcpu)
1847{
1848 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1849
1850 return save->cpl;
1851}
1852
1853static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1854{
1855 struct vcpu_svm *svm = to_svm(vcpu);
1856
1857 dt->size = svm->vmcb->save.idtr.limit;
1858 dt->address = svm->vmcb->save.idtr.base;
1859}
1860
1861static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1862{
1863 struct vcpu_svm *svm = to_svm(vcpu);
1864
1865 svm->vmcb->save.idtr.limit = dt->size;
1866 svm->vmcb->save.idtr.base = dt->address ;
1867 mark_dirty(svm->vmcb, VMCB_DT);
1868}
1869
1870static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1871{
1872 struct vcpu_svm *svm = to_svm(vcpu);
1873
1874 dt->size = svm->vmcb->save.gdtr.limit;
1875 dt->address = svm->vmcb->save.gdtr.base;
1876}
1877
1878static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1879{
1880 struct vcpu_svm *svm = to_svm(vcpu);
1881
1882 svm->vmcb->save.gdtr.limit = dt->size;
1883 svm->vmcb->save.gdtr.base = dt->address ;
1884 mark_dirty(svm->vmcb, VMCB_DT);
1885}
1886
1887static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1888{
1889}
1890
1891static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1892{
1893}
1894
1895static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1896{
1897}
1898
1899static void update_cr0_intercept(struct vcpu_svm *svm)
1900{
1901 ulong gcr0 = svm->vcpu.arch.cr0;
1902 u64 *hcr0 = &svm->vmcb->save.cr0;
1903
1904 if (!svm->vcpu.fpu_active)
1905 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1906 else
1907 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1908 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1909
1910 mark_dirty(svm->vmcb, VMCB_CR);
1911
1912 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1913 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1914 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1915 } else {
1916 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1917 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1918 }
1919}
1920
1921static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1922{
1923 struct vcpu_svm *svm = to_svm(vcpu);
1924
1925#ifdef CONFIG_X86_64
1926 if (vcpu->arch.efer & EFER_LME) {
1927 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1928 vcpu->arch.efer |= EFER_LMA;
1929 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1930 }
1931
1932 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1933 vcpu->arch.efer &= ~EFER_LMA;
1934 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1935 }
1936 }
1937#endif
1938 vcpu->arch.cr0 = cr0;
1939
1940 if (!npt_enabled)
1941 cr0 |= X86_CR0_PG | X86_CR0_WP;
1942
1943 if (!vcpu->fpu_active)
1944 cr0 |= X86_CR0_TS;
1945 /*
1946 * re-enable caching here because the QEMU bios
1947 * does not do it - this results in some delay at
1948 * reboot
1949 */
1950 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1951 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1952 svm->vmcb->save.cr0 = cr0;
1953 mark_dirty(svm->vmcb, VMCB_CR);
1954 update_cr0_intercept(svm);
1955}
1956
1957static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1958{
1959 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1960 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1961
1962 if (cr4 & X86_CR4_VMXE)
1963 return 1;
1964
1965 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1966 svm_flush_tlb(vcpu);
1967
1968 vcpu->arch.cr4 = cr4;
1969 if (!npt_enabled)
1970 cr4 |= X86_CR4_PAE;
1971 cr4 |= host_cr4_mce;
1972 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1973 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1974 return 0;
1975}
1976
1977static void svm_set_segment(struct kvm_vcpu *vcpu,
1978 struct kvm_segment *var, int seg)
1979{
1980 struct vcpu_svm *svm = to_svm(vcpu);
1981 struct vmcb_seg *s = svm_seg(vcpu, seg);
1982
1983 s->base = var->base;
1984 s->limit = var->limit;
1985 s->selector = var->selector;
1986 if (var->unusable)
1987 s->attrib = 0;
1988 else {
1989 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1990 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1991 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1992 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1993 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1994 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1995 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1996 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1997 }
1998
1999 /*
2000 * This is always accurate, except if SYSRET returned to a segment
2001 * with SS.DPL != 3. Intel does not have this quirk, and always
2002 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2003 * would entail passing the CPL to userspace and back.
2004 */
2005 if (seg == VCPU_SREG_SS)
2006 svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2007
2008 mark_dirty(svm->vmcb, VMCB_SEG);
2009}
2010
2011static void update_bp_intercept(struct kvm_vcpu *vcpu)
2012{
2013 struct vcpu_svm *svm = to_svm(vcpu);
2014
2015 clr_exception_intercept(svm, BP_VECTOR);
2016
2017 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2018 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2019 set_exception_intercept(svm, BP_VECTOR);
2020 } else
2021 vcpu->guest_debug = 0;
2022}
2023
2024static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2025{
2026 if (sd->next_asid > sd->max_asid) {
2027 ++sd->asid_generation;
2028 sd->next_asid = 1;
2029 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2030 }
2031
2032 svm->asid_generation = sd->asid_generation;
2033 svm->vmcb->control.asid = sd->next_asid++;
2034
2035 mark_dirty(svm->vmcb, VMCB_ASID);
2036}
2037
2038static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2039{
2040 return to_svm(vcpu)->vmcb->save.dr6;
2041}
2042
2043static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2044{
2045 struct vcpu_svm *svm = to_svm(vcpu);
2046
2047 svm->vmcb->save.dr6 = value;
2048 mark_dirty(svm->vmcb, VMCB_DR);
2049}
2050
2051static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2052{
2053 struct vcpu_svm *svm = to_svm(vcpu);
2054
2055 get_debugreg(vcpu->arch.db[0], 0);
2056 get_debugreg(vcpu->arch.db[1], 1);
2057 get_debugreg(vcpu->arch.db[2], 2);
2058 get_debugreg(vcpu->arch.db[3], 3);
2059 vcpu->arch.dr6 = svm_get_dr6(vcpu);
2060 vcpu->arch.dr7 = svm->vmcb->save.dr7;
2061
2062 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2063 set_dr_intercepts(svm);
2064}
2065
2066static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2067{
2068 struct vcpu_svm *svm = to_svm(vcpu);
2069
2070 svm->vmcb->save.dr7 = value;
2071 mark_dirty(svm->vmcb, VMCB_DR);
2072}
2073
2074static int pf_interception(struct vcpu_svm *svm)
2075{
2076 u64 fault_address = svm->vmcb->control.exit_info_2;
2077 u64 error_code;
2078 int r = 1;
2079
2080 switch (svm->apf_reason) {
2081 default:
2082 error_code = svm->vmcb->control.exit_info_1;
2083
2084 trace_kvm_page_fault(fault_address, error_code);
2085 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
2086 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
2087 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2088 svm->vmcb->control.insn_bytes,
2089 svm->vmcb->control.insn_len);
2090 break;
2091 case KVM_PV_REASON_PAGE_NOT_PRESENT:
2092 svm->apf_reason = 0;
2093 local_irq_disable();
2094 kvm_async_pf_task_wait(fault_address);
2095 local_irq_enable();
2096 break;
2097 case KVM_PV_REASON_PAGE_READY:
2098 svm->apf_reason = 0;
2099 local_irq_disable();
2100 kvm_async_pf_task_wake(fault_address);
2101 local_irq_enable();
2102 break;
2103 }
2104 return r;
2105}
2106
2107static int db_interception(struct vcpu_svm *svm)
2108{
2109 struct kvm_run *kvm_run = svm->vcpu.run;
2110
2111 if (!(svm->vcpu.guest_debug &
2112 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2113 !svm->nmi_singlestep) {
2114 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2115 return 1;
2116 }
2117
2118 if (svm->nmi_singlestep) {
2119 svm->nmi_singlestep = false;
2120 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
2121 svm->vmcb->save.rflags &=
2122 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
2123 }
2124
2125 if (svm->vcpu.guest_debug &
2126 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2127 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2128 kvm_run->debug.arch.pc =
2129 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2130 kvm_run->debug.arch.exception = DB_VECTOR;
2131 return 0;
2132 }
2133
2134 return 1;
2135}
2136
2137static int bp_interception(struct vcpu_svm *svm)
2138{
2139 struct kvm_run *kvm_run = svm->vcpu.run;
2140
2141 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2142 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2143 kvm_run->debug.arch.exception = BP_VECTOR;
2144 return 0;
2145}
2146
2147static int ud_interception(struct vcpu_svm *svm)
2148{
2149 int er;
2150
2151 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
2152 if (er != EMULATE_DONE)
2153 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2154 return 1;
2155}
2156
2157static int ac_interception(struct vcpu_svm *svm)
2158{
2159 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2160 return 1;
2161}
2162
2163static void svm_fpu_activate(struct kvm_vcpu *vcpu)
2164{
2165 struct vcpu_svm *svm = to_svm(vcpu);
2166
2167 clr_exception_intercept(svm, NM_VECTOR);
2168
2169 svm->vcpu.fpu_active = 1;
2170 update_cr0_intercept(svm);
2171}
2172
2173static int nm_interception(struct vcpu_svm *svm)
2174{
2175 svm_fpu_activate(&svm->vcpu);
2176 return 1;
2177}
2178
2179static bool is_erratum_383(void)
2180{
2181 int err, i;
2182 u64 value;
2183
2184 if (!erratum_383_found)
2185 return false;
2186
2187 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2188 if (err)
2189 return false;
2190
2191 /* Bit 62 may or may not be set for this mce */
2192 value &= ~(1ULL << 62);
2193
2194 if (value != 0xb600000000010015ULL)
2195 return false;
2196
2197 /* Clear MCi_STATUS registers */
2198 for (i = 0; i < 6; ++i)
2199 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2200
2201 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2202 if (!err) {
2203 u32 low, high;
2204
2205 value &= ~(1ULL << 2);
2206 low = lower_32_bits(value);
2207 high = upper_32_bits(value);
2208
2209 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2210 }
2211
2212 /* Flush tlb to evict multi-match entries */
2213 __flush_tlb_all();
2214
2215 return true;
2216}
2217
2218static void svm_handle_mce(struct vcpu_svm *svm)
2219{
2220 if (is_erratum_383()) {
2221 /*
2222 * Erratum 383 triggered. Guest state is corrupt so kill the
2223 * guest.
2224 */
2225 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2226
2227 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2228
2229 return;
2230 }
2231
2232 /*
2233 * On an #MC intercept the MCE handler is not called automatically in
2234 * the host. So do it by hand here.
2235 */
2236 asm volatile (
2237 "int $0x12\n");
2238 /* not sure if we ever come back to this point */
2239
2240 return;
2241}
2242
2243static int mc_interception(struct vcpu_svm *svm)
2244{
2245 return 1;
2246}
2247
2248static int shutdown_interception(struct vcpu_svm *svm)
2249{
2250 struct kvm_run *kvm_run = svm->vcpu.run;
2251
2252 /*
2253 * VMCB is undefined after a SHUTDOWN intercept
2254 * so reinitialize it.
2255 */
2256 clear_page(svm->vmcb);
2257 init_vmcb(svm);
2258
2259 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2260 return 0;
2261}
2262
2263static int io_interception(struct vcpu_svm *svm)
2264{
2265 struct kvm_vcpu *vcpu = &svm->vcpu;
2266 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2267 int size, in, string;
2268 unsigned port;
2269
2270 ++svm->vcpu.stat.io_exits;
2271 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2272 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2273 if (string || in)
2274 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2275
2276 port = io_info >> 16;
2277 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2278 svm->next_rip = svm->vmcb->control.exit_info_2;
2279 skip_emulated_instruction(&svm->vcpu);
2280
2281 return kvm_fast_pio_out(vcpu, size, port);
2282}
2283
2284static int nmi_interception(struct vcpu_svm *svm)
2285{
2286 return 1;
2287}
2288
2289static int intr_interception(struct vcpu_svm *svm)
2290{
2291 ++svm->vcpu.stat.irq_exits;
2292 return 1;
2293}
2294
2295static int nop_on_interception(struct vcpu_svm *svm)
2296{
2297 return 1;
2298}
2299
2300static int halt_interception(struct vcpu_svm *svm)
2301{
2302 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2303 return kvm_emulate_halt(&svm->vcpu);
2304}
2305
2306static int vmmcall_interception(struct vcpu_svm *svm)
2307{
2308 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2309 return kvm_emulate_hypercall(&svm->vcpu);
2310}
2311
2312static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2313{
2314 struct vcpu_svm *svm = to_svm(vcpu);
2315
2316 return svm->nested.nested_cr3;
2317}
2318
2319static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2320{
2321 struct vcpu_svm *svm = to_svm(vcpu);
2322 u64 cr3 = svm->nested.nested_cr3;
2323 u64 pdpte;
2324 int ret;
2325
2326 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte,
2327 offset_in_page(cr3) + index * 8, 8);
2328 if (ret)
2329 return 0;
2330 return pdpte;
2331}
2332
2333static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2334 unsigned long root)
2335{
2336 struct vcpu_svm *svm = to_svm(vcpu);
2337
2338 svm->vmcb->control.nested_cr3 = root;
2339 mark_dirty(svm->vmcb, VMCB_NPT);
2340 svm_flush_tlb(vcpu);
2341}
2342
2343static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2344 struct x86_exception *fault)
2345{
2346 struct vcpu_svm *svm = to_svm(vcpu);
2347
2348 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2349 /*
2350 * TODO: track the cause of the nested page fault, and
2351 * correctly fill in the high bits of exit_info_1.
2352 */
2353 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2354 svm->vmcb->control.exit_code_hi = 0;
2355 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2356 svm->vmcb->control.exit_info_2 = fault->address;
2357 }
2358
2359 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2360 svm->vmcb->control.exit_info_1 |= fault->error_code;
2361
2362 /*
2363 * The present bit is always zero for page structure faults on real
2364 * hardware.
2365 */
2366 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2367 svm->vmcb->control.exit_info_1 &= ~1;
2368
2369 nested_svm_vmexit(svm);
2370}
2371
2372static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2373{
2374 WARN_ON(mmu_is_nested(vcpu));
2375 kvm_init_shadow_mmu(vcpu);
2376 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
2377 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
2378 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
2379 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2380 vcpu->arch.mmu.shadow_root_level = get_npt_level();
2381 reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2382 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
2383}
2384
2385static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2386{
2387 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2388}
2389
2390static int nested_svm_check_permissions(struct vcpu_svm *svm)
2391{
2392 if (!(svm->vcpu.arch.efer & EFER_SVME)
2393 || !is_paging(&svm->vcpu)) {
2394 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2395 return 1;
2396 }
2397
2398 if (svm->vmcb->save.cpl) {
2399 kvm_inject_gp(&svm->vcpu, 0);
2400 return 1;
2401 }
2402
2403 return 0;
2404}
2405
2406static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2407 bool has_error_code, u32 error_code)
2408{
2409 int vmexit;
2410
2411 if (!is_guest_mode(&svm->vcpu))
2412 return 0;
2413
2414 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2415 svm->vmcb->control.exit_code_hi = 0;
2416 svm->vmcb->control.exit_info_1 = error_code;
2417 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2418
2419 vmexit = nested_svm_intercept(svm);
2420 if (vmexit == NESTED_EXIT_DONE)
2421 svm->nested.exit_required = true;
2422
2423 return vmexit;
2424}
2425
2426/* This function returns true if it is save to enable the irq window */
2427static inline bool nested_svm_intr(struct vcpu_svm *svm)
2428{
2429 if (!is_guest_mode(&svm->vcpu))
2430 return true;
2431
2432 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2433 return true;
2434
2435 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2436 return false;
2437
2438 /*
2439 * if vmexit was already requested (by intercepted exception
2440 * for instance) do not overwrite it with "external interrupt"
2441 * vmexit.
2442 */
2443 if (svm->nested.exit_required)
2444 return false;
2445
2446 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2447 svm->vmcb->control.exit_info_1 = 0;
2448 svm->vmcb->control.exit_info_2 = 0;
2449
2450 if (svm->nested.intercept & 1ULL) {
2451 /*
2452 * The #vmexit can't be emulated here directly because this
2453 * code path runs with irqs and preemption disabled. A
2454 * #vmexit emulation might sleep. Only signal request for
2455 * the #vmexit here.
2456 */
2457 svm->nested.exit_required = true;
2458 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2459 return false;
2460 }
2461
2462 return true;
2463}
2464
2465/* This function returns true if it is save to enable the nmi window */
2466static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2467{
2468 if (!is_guest_mode(&svm->vcpu))
2469 return true;
2470
2471 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2472 return true;
2473
2474 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2475 svm->nested.exit_required = true;
2476
2477 return false;
2478}
2479
2480static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2481{
2482 struct page *page;
2483
2484 might_sleep();
2485
2486 page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2487 if (is_error_page(page))
2488 goto error;
2489
2490 *_page = page;
2491
2492 return kmap(page);
2493
2494error:
2495 kvm_inject_gp(&svm->vcpu, 0);
2496
2497 return NULL;
2498}
2499
2500static void nested_svm_unmap(struct page *page)
2501{
2502 kunmap(page);
2503 kvm_release_page_dirty(page);
2504}
2505
2506static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2507{
2508 unsigned port, size, iopm_len;
2509 u16 val, mask;
2510 u8 start_bit;
2511 u64 gpa;
2512
2513 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2514 return NESTED_EXIT_HOST;
2515
2516 port = svm->vmcb->control.exit_info_1 >> 16;
2517 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2518 SVM_IOIO_SIZE_SHIFT;
2519 gpa = svm->nested.vmcb_iopm + (port / 8);
2520 start_bit = port % 8;
2521 iopm_len = (start_bit + size > 8) ? 2 : 1;
2522 mask = (0xf >> (4 - size)) << start_bit;
2523 val = 0;
2524
2525 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2526 return NESTED_EXIT_DONE;
2527
2528 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2529}
2530
2531static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2532{
2533 u32 offset, msr, value;
2534 int write, mask;
2535
2536 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2537 return NESTED_EXIT_HOST;
2538
2539 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2540 offset = svm_msrpm_offset(msr);
2541 write = svm->vmcb->control.exit_info_1 & 1;
2542 mask = 1 << ((2 * (msr & 0xf)) + write);
2543
2544 if (offset == MSR_INVALID)
2545 return NESTED_EXIT_DONE;
2546
2547 /* Offset is in 32 bit units but need in 8 bit units */
2548 offset *= 4;
2549
2550 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2551 return NESTED_EXIT_DONE;
2552
2553 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2554}
2555
2556static int nested_svm_exit_special(struct vcpu_svm *svm)
2557{
2558 u32 exit_code = svm->vmcb->control.exit_code;
2559
2560 switch (exit_code) {
2561 case SVM_EXIT_INTR:
2562 case SVM_EXIT_NMI:
2563 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2564 return NESTED_EXIT_HOST;
2565 case SVM_EXIT_NPF:
2566 /* For now we are always handling NPFs when using them */
2567 if (npt_enabled)
2568 return NESTED_EXIT_HOST;
2569 break;
2570 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2571 /* When we're shadowing, trap PFs, but not async PF */
2572 if (!npt_enabled && svm->apf_reason == 0)
2573 return NESTED_EXIT_HOST;
2574 break;
2575 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2576 nm_interception(svm);
2577 break;
2578 default:
2579 break;
2580 }
2581
2582 return NESTED_EXIT_CONTINUE;
2583}
2584
2585/*
2586 * If this function returns true, this #vmexit was already handled
2587 */
2588static int nested_svm_intercept(struct vcpu_svm *svm)
2589{
2590 u32 exit_code = svm->vmcb->control.exit_code;
2591 int vmexit = NESTED_EXIT_HOST;
2592
2593 switch (exit_code) {
2594 case SVM_EXIT_MSR:
2595 vmexit = nested_svm_exit_handled_msr(svm);
2596 break;
2597 case SVM_EXIT_IOIO:
2598 vmexit = nested_svm_intercept_ioio(svm);
2599 break;
2600 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2601 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2602 if (svm->nested.intercept_cr & bit)
2603 vmexit = NESTED_EXIT_DONE;
2604 break;
2605 }
2606 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2607 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2608 if (svm->nested.intercept_dr & bit)
2609 vmexit = NESTED_EXIT_DONE;
2610 break;
2611 }
2612 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2613 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2614 if (svm->nested.intercept_exceptions & excp_bits)
2615 vmexit = NESTED_EXIT_DONE;
2616 /* async page fault always cause vmexit */
2617 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2618 svm->apf_reason != 0)
2619 vmexit = NESTED_EXIT_DONE;
2620 break;
2621 }
2622 case SVM_EXIT_ERR: {
2623 vmexit = NESTED_EXIT_DONE;
2624 break;
2625 }
2626 default: {
2627 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2628 if (svm->nested.intercept & exit_bits)
2629 vmexit = NESTED_EXIT_DONE;
2630 }
2631 }
2632
2633 return vmexit;
2634}
2635
2636static int nested_svm_exit_handled(struct vcpu_svm *svm)
2637{
2638 int vmexit;
2639
2640 vmexit = nested_svm_intercept(svm);
2641
2642 if (vmexit == NESTED_EXIT_DONE)
2643 nested_svm_vmexit(svm);
2644
2645 return vmexit;
2646}
2647
2648static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2649{
2650 struct vmcb_control_area *dst = &dst_vmcb->control;
2651 struct vmcb_control_area *from = &from_vmcb->control;
2652
2653 dst->intercept_cr = from->intercept_cr;
2654 dst->intercept_dr = from->intercept_dr;
2655 dst->intercept_exceptions = from->intercept_exceptions;
2656 dst->intercept = from->intercept;
2657 dst->iopm_base_pa = from->iopm_base_pa;
2658 dst->msrpm_base_pa = from->msrpm_base_pa;
2659 dst->tsc_offset = from->tsc_offset;
2660 dst->asid = from->asid;
2661 dst->tlb_ctl = from->tlb_ctl;
2662 dst->int_ctl = from->int_ctl;
2663 dst->int_vector = from->int_vector;
2664 dst->int_state = from->int_state;
2665 dst->exit_code = from->exit_code;
2666 dst->exit_code_hi = from->exit_code_hi;
2667 dst->exit_info_1 = from->exit_info_1;
2668 dst->exit_info_2 = from->exit_info_2;
2669 dst->exit_int_info = from->exit_int_info;
2670 dst->exit_int_info_err = from->exit_int_info_err;
2671 dst->nested_ctl = from->nested_ctl;
2672 dst->event_inj = from->event_inj;
2673 dst->event_inj_err = from->event_inj_err;
2674 dst->nested_cr3 = from->nested_cr3;
2675 dst->lbr_ctl = from->lbr_ctl;
2676}
2677
2678static int nested_svm_vmexit(struct vcpu_svm *svm)
2679{
2680 struct vmcb *nested_vmcb;
2681 struct vmcb *hsave = svm->nested.hsave;
2682 struct vmcb *vmcb = svm->vmcb;
2683 struct page *page;
2684
2685 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2686 vmcb->control.exit_info_1,
2687 vmcb->control.exit_info_2,
2688 vmcb->control.exit_int_info,
2689 vmcb->control.exit_int_info_err,
2690 KVM_ISA_SVM);
2691
2692 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2693 if (!nested_vmcb)
2694 return 1;
2695
2696 /* Exit Guest-Mode */
2697 leave_guest_mode(&svm->vcpu);
2698 svm->nested.vmcb = 0;
2699
2700 /* Give the current vmcb to the guest */
2701 disable_gif(svm);
2702
2703 nested_vmcb->save.es = vmcb->save.es;
2704 nested_vmcb->save.cs = vmcb->save.cs;
2705 nested_vmcb->save.ss = vmcb->save.ss;
2706 nested_vmcb->save.ds = vmcb->save.ds;
2707 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2708 nested_vmcb->save.idtr = vmcb->save.idtr;
2709 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2710 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2711 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2712 nested_vmcb->save.cr2 = vmcb->save.cr2;
2713 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2714 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2715 nested_vmcb->save.rip = vmcb->save.rip;
2716 nested_vmcb->save.rsp = vmcb->save.rsp;
2717 nested_vmcb->save.rax = vmcb->save.rax;
2718 nested_vmcb->save.dr7 = vmcb->save.dr7;
2719 nested_vmcb->save.dr6 = vmcb->save.dr6;
2720 nested_vmcb->save.cpl = vmcb->save.cpl;
2721
2722 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2723 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2724 nested_vmcb->control.int_state = vmcb->control.int_state;
2725 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2726 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2727 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2728 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2729 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2730 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2731
2732 if (svm->nrips_enabled)
2733 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2734
2735 /*
2736 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2737 * to make sure that we do not lose injected events. So check event_inj
2738 * here and copy it to exit_int_info if it is valid.
2739 * Exit_int_info and event_inj can't be both valid because the case
2740 * below only happens on a VMRUN instruction intercept which has
2741 * no valid exit_int_info set.
2742 */
2743 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2744 struct vmcb_control_area *nc = &nested_vmcb->control;
2745
2746 nc->exit_int_info = vmcb->control.event_inj;
2747 nc->exit_int_info_err = vmcb->control.event_inj_err;
2748 }
2749
2750 nested_vmcb->control.tlb_ctl = 0;
2751 nested_vmcb->control.event_inj = 0;
2752 nested_vmcb->control.event_inj_err = 0;
2753
2754 /* We always set V_INTR_MASKING and remember the old value in hflags */
2755 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2756 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2757
2758 /* Restore the original control entries */
2759 copy_vmcb_control_area(vmcb, hsave);
2760
2761 kvm_clear_exception_queue(&svm->vcpu);
2762 kvm_clear_interrupt_queue(&svm->vcpu);
2763
2764 svm->nested.nested_cr3 = 0;
2765
2766 /* Restore selected save entries */
2767 svm->vmcb->save.es = hsave->save.es;
2768 svm->vmcb->save.cs = hsave->save.cs;
2769 svm->vmcb->save.ss = hsave->save.ss;
2770 svm->vmcb->save.ds = hsave->save.ds;
2771 svm->vmcb->save.gdtr = hsave->save.gdtr;
2772 svm->vmcb->save.idtr = hsave->save.idtr;
2773 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2774 svm_set_efer(&svm->vcpu, hsave->save.efer);
2775 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2776 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2777 if (npt_enabled) {
2778 svm->vmcb->save.cr3 = hsave->save.cr3;
2779 svm->vcpu.arch.cr3 = hsave->save.cr3;
2780 } else {
2781 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2782 }
2783 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2784 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2785 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2786 svm->vmcb->save.dr7 = 0;
2787 svm->vmcb->save.cpl = 0;
2788 svm->vmcb->control.exit_int_info = 0;
2789
2790 mark_all_dirty(svm->vmcb);
2791
2792 nested_svm_unmap(page);
2793
2794 nested_svm_uninit_mmu_context(&svm->vcpu);
2795 kvm_mmu_reset_context(&svm->vcpu);
2796 kvm_mmu_load(&svm->vcpu);
2797
2798 return 0;
2799}
2800
2801static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2802{
2803 /*
2804 * This function merges the msr permission bitmaps of kvm and the
2805 * nested vmcb. It is optimized in that it only merges the parts where
2806 * the kvm msr permission bitmap may contain zero bits
2807 */
2808 int i;
2809
2810 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2811 return true;
2812
2813 for (i = 0; i < MSRPM_OFFSETS; i++) {
2814 u32 value, p;
2815 u64 offset;
2816
2817 if (msrpm_offsets[i] == 0xffffffff)
2818 break;
2819
2820 p = msrpm_offsets[i];
2821 offset = svm->nested.vmcb_msrpm + (p * 4);
2822
2823 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2824 return false;
2825
2826 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2827 }
2828
2829 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2830
2831 return true;
2832}
2833
2834static bool nested_vmcb_checks(struct vmcb *vmcb)
2835{
2836 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2837 return false;
2838
2839 if (vmcb->control.asid == 0)
2840 return false;
2841
2842 if (vmcb->control.nested_ctl && !npt_enabled)
2843 return false;
2844
2845 return true;
2846}
2847
2848static bool nested_svm_vmrun(struct vcpu_svm *svm)
2849{
2850 struct vmcb *nested_vmcb;
2851 struct vmcb *hsave = svm->nested.hsave;
2852 struct vmcb *vmcb = svm->vmcb;
2853 struct page *page;
2854 u64 vmcb_gpa;
2855
2856 vmcb_gpa = svm->vmcb->save.rax;
2857
2858 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2859 if (!nested_vmcb)
2860 return false;
2861
2862 if (!nested_vmcb_checks(nested_vmcb)) {
2863 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2864 nested_vmcb->control.exit_code_hi = 0;
2865 nested_vmcb->control.exit_info_1 = 0;
2866 nested_vmcb->control.exit_info_2 = 0;
2867
2868 nested_svm_unmap(page);
2869
2870 return false;
2871 }
2872
2873 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2874 nested_vmcb->save.rip,
2875 nested_vmcb->control.int_ctl,
2876 nested_vmcb->control.event_inj,
2877 nested_vmcb->control.nested_ctl);
2878
2879 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2880 nested_vmcb->control.intercept_cr >> 16,
2881 nested_vmcb->control.intercept_exceptions,
2882 nested_vmcb->control.intercept);
2883
2884 /* Clear internal status */
2885 kvm_clear_exception_queue(&svm->vcpu);
2886 kvm_clear_interrupt_queue(&svm->vcpu);
2887
2888 /*
2889 * Save the old vmcb, so we don't need to pick what we save, but can
2890 * restore everything when a VMEXIT occurs
2891 */
2892 hsave->save.es = vmcb->save.es;
2893 hsave->save.cs = vmcb->save.cs;
2894 hsave->save.ss = vmcb->save.ss;
2895 hsave->save.ds = vmcb->save.ds;
2896 hsave->save.gdtr = vmcb->save.gdtr;
2897 hsave->save.idtr = vmcb->save.idtr;
2898 hsave->save.efer = svm->vcpu.arch.efer;
2899 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2900 hsave->save.cr4 = svm->vcpu.arch.cr4;
2901 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2902 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2903 hsave->save.rsp = vmcb->save.rsp;
2904 hsave->save.rax = vmcb->save.rax;
2905 if (npt_enabled)
2906 hsave->save.cr3 = vmcb->save.cr3;
2907 else
2908 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2909
2910 copy_vmcb_control_area(hsave, vmcb);
2911
2912 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2913 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2914 else
2915 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2916
2917 if (nested_vmcb->control.nested_ctl) {
2918 kvm_mmu_unload(&svm->vcpu);
2919 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2920 nested_svm_init_mmu_context(&svm->vcpu);
2921 }
2922
2923 /* Load the nested guest state */
2924 svm->vmcb->save.es = nested_vmcb->save.es;
2925 svm->vmcb->save.cs = nested_vmcb->save.cs;
2926 svm->vmcb->save.ss = nested_vmcb->save.ss;
2927 svm->vmcb->save.ds = nested_vmcb->save.ds;
2928 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2929 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2930 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2931 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2932 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2933 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2934 if (npt_enabled) {
2935 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2936 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2937 } else
2938 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2939
2940 /* Guest paging mode is active - reset mmu */
2941 kvm_mmu_reset_context(&svm->vcpu);
2942
2943 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2944 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2945 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2946 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2947
2948 /* In case we don't even reach vcpu_run, the fields are not updated */
2949 svm->vmcb->save.rax = nested_vmcb->save.rax;
2950 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2951 svm->vmcb->save.rip = nested_vmcb->save.rip;
2952 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2953 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2954 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2955
2956 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2957 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2958
2959 /* cache intercepts */
2960 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2961 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2962 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2963 svm->nested.intercept = nested_vmcb->control.intercept;
2964
2965 svm_flush_tlb(&svm->vcpu);
2966 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2967 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2968 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2969 else
2970 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2971
2972 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2973 /* We only want the cr8 intercept bits of the guest */
2974 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2975 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2976 }
2977
2978 /* We don't want to see VMMCALLs from a nested guest */
2979 clr_intercept(svm, INTERCEPT_VMMCALL);
2980
2981 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2982 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2983 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2984 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2985 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2986 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2987
2988 nested_svm_unmap(page);
2989
2990 /* Enter Guest-Mode */
2991 enter_guest_mode(&svm->vcpu);
2992
2993 /*
2994 * Merge guest and host intercepts - must be called with vcpu in
2995 * guest-mode to take affect here
2996 */
2997 recalc_intercepts(svm);
2998
2999 svm->nested.vmcb = vmcb_gpa;
3000
3001 enable_gif(svm);
3002
3003 mark_all_dirty(svm->vmcb);
3004
3005 return true;
3006}
3007
3008static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3009{
3010 to_vmcb->save.fs = from_vmcb->save.fs;
3011 to_vmcb->save.gs = from_vmcb->save.gs;
3012 to_vmcb->save.tr = from_vmcb->save.tr;
3013 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3014 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3015 to_vmcb->save.star = from_vmcb->save.star;
3016 to_vmcb->save.lstar = from_vmcb->save.lstar;
3017 to_vmcb->save.cstar = from_vmcb->save.cstar;
3018 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3019 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3020 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3021 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3022}
3023
3024static int vmload_interception(struct vcpu_svm *svm)
3025{
3026 struct vmcb *nested_vmcb;
3027 struct page *page;
3028
3029 if (nested_svm_check_permissions(svm))
3030 return 1;
3031
3032 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3033 if (!nested_vmcb)
3034 return 1;
3035
3036 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3037 skip_emulated_instruction(&svm->vcpu);
3038
3039 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3040 nested_svm_unmap(page);
3041
3042 return 1;
3043}
3044
3045static int vmsave_interception(struct vcpu_svm *svm)
3046{
3047 struct vmcb *nested_vmcb;
3048 struct page *page;
3049
3050 if (nested_svm_check_permissions(svm))
3051 return 1;
3052
3053 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3054 if (!nested_vmcb)
3055 return 1;
3056
3057 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3058 skip_emulated_instruction(&svm->vcpu);
3059
3060 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3061 nested_svm_unmap(page);
3062
3063 return 1;
3064}
3065
3066static int vmrun_interception(struct vcpu_svm *svm)
3067{
3068 if (nested_svm_check_permissions(svm))
3069 return 1;
3070
3071 /* Save rip after vmrun instruction */
3072 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3073
3074 if (!nested_svm_vmrun(svm))
3075 return 1;
3076
3077 if (!nested_svm_vmrun_msrpm(svm))
3078 goto failed;
3079
3080 return 1;
3081
3082failed:
3083
3084 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
3085 svm->vmcb->control.exit_code_hi = 0;
3086 svm->vmcb->control.exit_info_1 = 0;
3087 svm->vmcb->control.exit_info_2 = 0;
3088
3089 nested_svm_vmexit(svm);
3090
3091 return 1;
3092}
3093
3094static int stgi_interception(struct vcpu_svm *svm)
3095{
3096 if (nested_svm_check_permissions(svm))
3097 return 1;
3098
3099 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3100 skip_emulated_instruction(&svm->vcpu);
3101 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3102
3103 enable_gif(svm);
3104
3105 return 1;
3106}
3107
3108static int clgi_interception(struct vcpu_svm *svm)
3109{
3110 if (nested_svm_check_permissions(svm))
3111 return 1;
3112
3113 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3114 skip_emulated_instruction(&svm->vcpu);
3115
3116 disable_gif(svm);
3117
3118 /* After a CLGI no interrupts should come */
3119 if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3120 svm_clear_vintr(svm);
3121 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3122 mark_dirty(svm->vmcb, VMCB_INTR);
3123 }
3124
3125 return 1;
3126}
3127
3128static int invlpga_interception(struct vcpu_svm *svm)
3129{
3130 struct kvm_vcpu *vcpu = &svm->vcpu;
3131
3132 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3133 kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3134
3135 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3136 kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3137
3138 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3139 skip_emulated_instruction(&svm->vcpu);
3140 return 1;
3141}
3142
3143static int skinit_interception(struct vcpu_svm *svm)
3144{
3145 trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3146
3147 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3148 return 1;
3149}
3150
3151static int wbinvd_interception(struct vcpu_svm *svm)
3152{
3153 kvm_emulate_wbinvd(&svm->vcpu);
3154 return 1;
3155}
3156
3157static int xsetbv_interception(struct vcpu_svm *svm)
3158{
3159 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3160 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3161
3162 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3163 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3164 skip_emulated_instruction(&svm->vcpu);
3165 }
3166
3167 return 1;
3168}
3169
3170static int task_switch_interception(struct vcpu_svm *svm)
3171{
3172 u16 tss_selector;
3173 int reason;
3174 int int_type = svm->vmcb->control.exit_int_info &
3175 SVM_EXITINTINFO_TYPE_MASK;
3176 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3177 uint32_t type =
3178 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3179 uint32_t idt_v =
3180 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3181 bool has_error_code = false;
3182 u32 error_code = 0;
3183
3184 tss_selector = (u16)svm->vmcb->control.exit_info_1;
3185
3186 if (svm->vmcb->control.exit_info_2 &
3187 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3188 reason = TASK_SWITCH_IRET;
3189 else if (svm->vmcb->control.exit_info_2 &
3190 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3191 reason = TASK_SWITCH_JMP;
3192 else if (idt_v)
3193 reason = TASK_SWITCH_GATE;
3194 else
3195 reason = TASK_SWITCH_CALL;
3196
3197 if (reason == TASK_SWITCH_GATE) {
3198 switch (type) {
3199 case SVM_EXITINTINFO_TYPE_NMI:
3200 svm->vcpu.arch.nmi_injected = false;
3201 break;
3202 case SVM_EXITINTINFO_TYPE_EXEPT:
3203 if (svm->vmcb->control.exit_info_2 &
3204 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3205 has_error_code = true;
3206 error_code =
3207 (u32)svm->vmcb->control.exit_info_2;
3208 }
3209 kvm_clear_exception_queue(&svm->vcpu);
3210 break;
3211 case SVM_EXITINTINFO_TYPE_INTR:
3212 kvm_clear_interrupt_queue(&svm->vcpu);
3213 break;
3214 default:
3215 break;
3216 }
3217 }
3218
3219 if (reason != TASK_SWITCH_GATE ||
3220 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3221 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3222 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3223 skip_emulated_instruction(&svm->vcpu);
3224
3225 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3226 int_vec = -1;
3227
3228 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3229 has_error_code, error_code) == EMULATE_FAIL) {
3230 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3231 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3232 svm->vcpu.run->internal.ndata = 0;
3233 return 0;
3234 }
3235 return 1;
3236}
3237
3238static int cpuid_interception(struct vcpu_svm *svm)
3239{
3240 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3241 kvm_emulate_cpuid(&svm->vcpu);
3242 return 1;
3243}
3244
3245static int iret_interception(struct vcpu_svm *svm)
3246{
3247 ++svm->vcpu.stat.nmi_window_exits;
3248 clr_intercept(svm, INTERCEPT_IRET);
3249 svm->vcpu.arch.hflags |= HF_IRET_MASK;
3250 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3251 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3252 return 1;
3253}
3254
3255static int invlpg_interception(struct vcpu_svm *svm)
3256{
3257 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3258 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3259
3260 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3261 skip_emulated_instruction(&svm->vcpu);
3262 return 1;
3263}
3264
3265static int emulate_on_interception(struct vcpu_svm *svm)
3266{
3267 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3268}
3269
3270static int rdpmc_interception(struct vcpu_svm *svm)
3271{
3272 int err;
3273
3274 if (!static_cpu_has(X86_FEATURE_NRIPS))
3275 return emulate_on_interception(svm);
3276
3277 err = kvm_rdpmc(&svm->vcpu);
3278 kvm_complete_insn_gp(&svm->vcpu, err);
3279
3280 return 1;
3281}
3282
3283static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3284 unsigned long val)
3285{
3286 unsigned long cr0 = svm->vcpu.arch.cr0;
3287 bool ret = false;
3288 u64 intercept;
3289
3290 intercept = svm->nested.intercept;
3291
3292 if (!is_guest_mode(&svm->vcpu) ||
3293 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3294 return false;
3295
3296 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3297 val &= ~SVM_CR0_SELECTIVE_MASK;
3298
3299 if (cr0 ^ val) {
3300 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3301 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3302 }
3303
3304 return ret;
3305}
3306
3307#define CR_VALID (1ULL << 63)
3308
3309static int cr_interception(struct vcpu_svm *svm)
3310{
3311 int reg, cr;
3312 unsigned long val;
3313 int err;
3314
3315 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3316 return emulate_on_interception(svm);
3317
3318 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3319 return emulate_on_interception(svm);
3320
3321 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3322 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3323 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3324 else
3325 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3326
3327 err = 0;
3328 if (cr >= 16) { /* mov to cr */
3329 cr -= 16;
3330 val = kvm_register_read(&svm->vcpu, reg);
3331 switch (cr) {
3332 case 0:
3333 if (!check_selective_cr0_intercepted(svm, val))
3334 err = kvm_set_cr0(&svm->vcpu, val);
3335 else
3336 return 1;
3337
3338 break;
3339 case 3:
3340 err = kvm_set_cr3(&svm->vcpu, val);
3341 break;
3342 case 4:
3343 err = kvm_set_cr4(&svm->vcpu, val);
3344 break;
3345 case 8:
3346 err = kvm_set_cr8(&svm->vcpu, val);
3347 break;
3348 default:
3349 WARN(1, "unhandled write to CR%d", cr);
3350 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3351 return 1;
3352 }
3353 } else { /* mov from cr */
3354 switch (cr) {
3355 case 0:
3356 val = kvm_read_cr0(&svm->vcpu);
3357 break;
3358 case 2:
3359 val = svm->vcpu.arch.cr2;
3360 break;
3361 case 3:
3362 val = kvm_read_cr3(&svm->vcpu);
3363 break;
3364 case 4:
3365 val = kvm_read_cr4(&svm->vcpu);
3366 break;
3367 case 8:
3368 val = kvm_get_cr8(&svm->vcpu);
3369 break;
3370 default:
3371 WARN(1, "unhandled read from CR%d", cr);
3372 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3373 return 1;
3374 }
3375 kvm_register_write(&svm->vcpu, reg, val);
3376 }
3377 kvm_complete_insn_gp(&svm->vcpu, err);
3378
3379 return 1;
3380}
3381
3382static int dr_interception(struct vcpu_svm *svm)
3383{
3384 int reg, dr;
3385 unsigned long val;
3386
3387 if (svm->vcpu.guest_debug == 0) {
3388 /*
3389 * No more DR vmexits; force a reload of the debug registers
3390 * and reenter on this instruction. The next vmexit will
3391 * retrieve the full state of the debug registers.
3392 */
3393 clr_dr_intercepts(svm);
3394 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3395 return 1;
3396 }
3397
3398 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3399 return emulate_on_interception(svm);
3400
3401 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3402 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3403
3404 if (dr >= 16) { /* mov to DRn */
3405 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3406 return 1;
3407 val = kvm_register_read(&svm->vcpu, reg);
3408 kvm_set_dr(&svm->vcpu, dr - 16, val);
3409 } else {
3410 if (!kvm_require_dr(&svm->vcpu, dr))
3411 return 1;
3412 kvm_get_dr(&svm->vcpu, dr, &val);
3413 kvm_register_write(&svm->vcpu, reg, val);
3414 }
3415
3416 skip_emulated_instruction(&svm->vcpu);
3417
3418 return 1;
3419}
3420
3421static int cr8_write_interception(struct vcpu_svm *svm)
3422{
3423 struct kvm_run *kvm_run = svm->vcpu.run;
3424 int r;
3425
3426 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3427 /* instruction emulation calls kvm_set_cr8() */
3428 r = cr_interception(svm);
3429 if (lapic_in_kernel(&svm->vcpu))
3430 return r;
3431 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3432 return r;
3433 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3434 return 0;
3435}
3436
3437static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3438{
3439 struct vcpu_svm *svm = to_svm(vcpu);
3440
3441 switch (msr_info->index) {
3442 case MSR_IA32_TSC: {
3443 msr_info->data = svm->vmcb->control.tsc_offset +
3444 kvm_scale_tsc(vcpu, rdtsc());
3445
3446 break;
3447 }
3448 case MSR_STAR:
3449 msr_info->data = svm->vmcb->save.star;
3450 break;
3451#ifdef CONFIG_X86_64
3452 case MSR_LSTAR:
3453 msr_info->data = svm->vmcb->save.lstar;
3454 break;
3455 case MSR_CSTAR:
3456 msr_info->data = svm->vmcb->save.cstar;
3457 break;
3458 case MSR_KERNEL_GS_BASE:
3459 msr_info->data = svm->vmcb->save.kernel_gs_base;
3460 break;
3461 case MSR_SYSCALL_MASK:
3462 msr_info->data = svm->vmcb->save.sfmask;
3463 break;
3464#endif
3465 case MSR_IA32_SYSENTER_CS:
3466 msr_info->data = svm->vmcb->save.sysenter_cs;
3467 break;
3468 case MSR_IA32_SYSENTER_EIP:
3469 msr_info->data = svm->sysenter_eip;
3470 break;
3471 case MSR_IA32_SYSENTER_ESP:
3472 msr_info->data = svm->sysenter_esp;
3473 break;
3474 case MSR_TSC_AUX:
3475 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3476 return 1;
3477 msr_info->data = svm->tsc_aux;
3478 break;
3479 /*
3480 * Nobody will change the following 5 values in the VMCB so we can
3481 * safely return them on rdmsr. They will always be 0 until LBRV is
3482 * implemented.
3483 */
3484 case MSR_IA32_DEBUGCTLMSR:
3485 msr_info->data = svm->vmcb->save.dbgctl;
3486 break;
3487 case MSR_IA32_LASTBRANCHFROMIP:
3488 msr_info->data = svm->vmcb->save.br_from;
3489 break;
3490 case MSR_IA32_LASTBRANCHTOIP:
3491 msr_info->data = svm->vmcb->save.br_to;
3492 break;
3493 case MSR_IA32_LASTINTFROMIP:
3494 msr_info->data = svm->vmcb->save.last_excp_from;
3495 break;
3496 case MSR_IA32_LASTINTTOIP:
3497 msr_info->data = svm->vmcb->save.last_excp_to;
3498 break;
3499 case MSR_VM_HSAVE_PA:
3500 msr_info->data = svm->nested.hsave_msr;
3501 break;
3502 case MSR_VM_CR:
3503 msr_info->data = svm->nested.vm_cr_msr;
3504 break;
3505 case MSR_IA32_UCODE_REV:
3506 msr_info->data = 0x01000065;
3507 break;
3508 case MSR_F15H_IC_CFG: {
3509
3510 int family, model;
3511
3512 family = guest_cpuid_family(vcpu);
3513 model = guest_cpuid_model(vcpu);
3514
3515 if (family < 0 || model < 0)
3516 return kvm_get_msr_common(vcpu, msr_info);
3517
3518 msr_info->data = 0;
3519
3520 if (family == 0x15 &&
3521 (model >= 0x2 && model < 0x20))
3522 msr_info->data = 0x1E;
3523 }
3524 break;
3525 default:
3526 return kvm_get_msr_common(vcpu, msr_info);
3527 }
3528 return 0;
3529}
3530
3531static int rdmsr_interception(struct vcpu_svm *svm)
3532{
3533 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3534 struct msr_data msr_info;
3535
3536 msr_info.index = ecx;
3537 msr_info.host_initiated = false;
3538 if (svm_get_msr(&svm->vcpu, &msr_info)) {
3539 trace_kvm_msr_read_ex(ecx);
3540 kvm_inject_gp(&svm->vcpu, 0);
3541 } else {
3542 trace_kvm_msr_read(ecx, msr_info.data);
3543
3544 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3545 msr_info.data & 0xffffffff);
3546 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3547 msr_info.data >> 32);
3548 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3549 skip_emulated_instruction(&svm->vcpu);
3550 }
3551 return 1;
3552}
3553
3554static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3555{
3556 struct vcpu_svm *svm = to_svm(vcpu);
3557 int svm_dis, chg_mask;
3558
3559 if (data & ~SVM_VM_CR_VALID_MASK)
3560 return 1;
3561
3562 chg_mask = SVM_VM_CR_VALID_MASK;
3563
3564 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3565 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3566
3567 svm->nested.vm_cr_msr &= ~chg_mask;
3568 svm->nested.vm_cr_msr |= (data & chg_mask);
3569
3570 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3571
3572 /* check for svm_disable while efer.svme is set */
3573 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3574 return 1;
3575
3576 return 0;
3577}
3578
3579static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3580{
3581 struct vcpu_svm *svm = to_svm(vcpu);
3582
3583 u32 ecx = msr->index;
3584 u64 data = msr->data;
3585 switch (ecx) {
3586 case MSR_IA32_TSC:
3587 kvm_write_tsc(vcpu, msr);
3588 break;
3589 case MSR_STAR:
3590 svm->vmcb->save.star = data;
3591 break;
3592#ifdef CONFIG_X86_64
3593 case MSR_LSTAR:
3594 svm->vmcb->save.lstar = data;
3595 break;
3596 case MSR_CSTAR:
3597 svm->vmcb->save.cstar = data;
3598 break;
3599 case MSR_KERNEL_GS_BASE:
3600 svm->vmcb->save.kernel_gs_base = data;
3601 break;
3602 case MSR_SYSCALL_MASK:
3603 svm->vmcb->save.sfmask = data;
3604 break;
3605#endif
3606 case MSR_IA32_SYSENTER_CS:
3607 svm->vmcb->save.sysenter_cs = data;
3608 break;
3609 case MSR_IA32_SYSENTER_EIP:
3610 svm->sysenter_eip = data;
3611 svm->vmcb->save.sysenter_eip = data;
3612 break;
3613 case MSR_IA32_SYSENTER_ESP:
3614 svm->sysenter_esp = data;
3615 svm->vmcb->save.sysenter_esp = data;
3616 break;
3617 case MSR_TSC_AUX:
3618 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3619 return 1;
3620
3621 /*
3622 * This is rare, so we update the MSR here instead of using
3623 * direct_access_msrs. Doing that would require a rdmsr in
3624 * svm_vcpu_put.
3625 */
3626 svm->tsc_aux = data;
3627 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
3628 break;
3629 case MSR_IA32_DEBUGCTLMSR:
3630 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3631 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3632 __func__, data);
3633 break;
3634 }
3635 if (data & DEBUGCTL_RESERVED_BITS)
3636 return 1;
3637
3638 svm->vmcb->save.dbgctl = data;
3639 mark_dirty(svm->vmcb, VMCB_LBR);
3640 if (data & (1ULL<<0))
3641 svm_enable_lbrv(svm);
3642 else
3643 svm_disable_lbrv(svm);
3644 break;
3645 case MSR_VM_HSAVE_PA:
3646 svm->nested.hsave_msr = data;
3647 break;
3648 case MSR_VM_CR:
3649 return svm_set_vm_cr(vcpu, data);
3650 case MSR_VM_IGNNE:
3651 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3652 break;
3653 case MSR_IA32_APICBASE:
3654 if (kvm_vcpu_apicv_active(vcpu))
3655 avic_update_vapic_bar(to_svm(vcpu), data);
3656 /* Follow through */
3657 default:
3658 return kvm_set_msr_common(vcpu, msr);
3659 }
3660 return 0;
3661}
3662
3663static int wrmsr_interception(struct vcpu_svm *svm)
3664{
3665 struct msr_data msr;
3666 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3667 u64 data = kvm_read_edx_eax(&svm->vcpu);
3668
3669 msr.data = data;
3670 msr.index = ecx;
3671 msr.host_initiated = false;
3672
3673 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3674 if (kvm_set_msr(&svm->vcpu, &msr)) {
3675 trace_kvm_msr_write_ex(ecx, data);
3676 kvm_inject_gp(&svm->vcpu, 0);
3677 } else {
3678 trace_kvm_msr_write(ecx, data);
3679 skip_emulated_instruction(&svm->vcpu);
3680 }
3681 return 1;
3682}
3683
3684static int msr_interception(struct vcpu_svm *svm)
3685{
3686 if (svm->vmcb->control.exit_info_1)
3687 return wrmsr_interception(svm);
3688 else
3689 return rdmsr_interception(svm);
3690}
3691
3692static int interrupt_window_interception(struct vcpu_svm *svm)
3693{
3694 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3695 svm_clear_vintr(svm);
3696 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3697 mark_dirty(svm->vmcb, VMCB_INTR);
3698 ++svm->vcpu.stat.irq_window_exits;
3699 return 1;
3700}
3701
3702static int pause_interception(struct vcpu_svm *svm)
3703{
3704 kvm_vcpu_on_spin(&(svm->vcpu));
3705 return 1;
3706}
3707
3708static int nop_interception(struct vcpu_svm *svm)
3709{
3710 skip_emulated_instruction(&(svm->vcpu));
3711 return 1;
3712}
3713
3714static int monitor_interception(struct vcpu_svm *svm)
3715{
3716 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3717 return nop_interception(svm);
3718}
3719
3720static int mwait_interception(struct vcpu_svm *svm)
3721{
3722 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3723 return nop_interception(svm);
3724}
3725
3726enum avic_ipi_failure_cause {
3727 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
3728 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
3729 AVIC_IPI_FAILURE_INVALID_TARGET,
3730 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
3731};
3732
3733static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
3734{
3735 u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
3736 u32 icrl = svm->vmcb->control.exit_info_1;
3737 u32 id = svm->vmcb->control.exit_info_2 >> 32;
3738 u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
3739 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3740
3741 trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
3742
3743 switch (id) {
3744 case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
3745 /*
3746 * AVIC hardware handles the generation of
3747 * IPIs when the specified Message Type is Fixed
3748 * (also known as fixed delivery mode) and
3749 * the Trigger Mode is edge-triggered. The hardware
3750 * also supports self and broadcast delivery modes
3751 * specified via the Destination Shorthand(DSH)
3752 * field of the ICRL. Logical and physical APIC ID
3753 * formats are supported. All other IPI types cause
3754 * a #VMEXIT, which needs to emulated.
3755 */
3756 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
3757 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
3758 break;
3759 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
3760 int i;
3761 struct kvm_vcpu *vcpu;
3762 struct kvm *kvm = svm->vcpu.kvm;
3763 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3764
3765 /*
3766 * At this point, we expect that the AVIC HW has already
3767 * set the appropriate IRR bits on the valid target
3768 * vcpus. So, we just need to kick the appropriate vcpu.
3769 */
3770 kvm_for_each_vcpu(i, vcpu, kvm) {
3771 bool m = kvm_apic_match_dest(vcpu, apic,
3772 icrl & KVM_APIC_SHORT_MASK,
3773 GET_APIC_DEST_FIELD(icrh),
3774 icrl & KVM_APIC_DEST_MASK);
3775
3776 if (m && !avic_vcpu_is_running(vcpu))
3777 kvm_vcpu_wake_up(vcpu);
3778 }
3779 break;
3780 }
3781 case AVIC_IPI_FAILURE_INVALID_TARGET:
3782 break;
3783 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
3784 WARN_ONCE(1, "Invalid backing page\n");
3785 break;
3786 default:
3787 pr_err("Unknown IPI interception\n");
3788 }
3789
3790 return 1;
3791}
3792
3793static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
3794{
3795 struct kvm_arch *vm_data = &vcpu->kvm->arch;
3796 int index;
3797 u32 *logical_apic_id_table;
3798 int dlid = GET_APIC_LOGICAL_ID(ldr);
3799
3800 if (!dlid)
3801 return NULL;
3802
3803 if (flat) { /* flat */
3804 index = ffs(dlid) - 1;
3805 if (index > 7)
3806 return NULL;
3807 } else { /* cluster */
3808 int cluster = (dlid & 0xf0) >> 4;
3809 int apic = ffs(dlid & 0x0f) - 1;
3810
3811 if ((apic < 0) || (apic > 7) ||
3812 (cluster >= 0xf))
3813 return NULL;
3814 index = (cluster << 2) + apic;
3815 }
3816
3817 logical_apic_id_table = (u32 *) page_address(vm_data->avic_logical_id_table_page);
3818
3819 return &logical_apic_id_table[index];
3820}
3821
3822static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
3823 bool valid)
3824{
3825 bool flat;
3826 u32 *entry, new_entry;
3827
3828 flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
3829 entry = avic_get_logical_id_entry(vcpu, ldr, flat);
3830 if (!entry)
3831 return -EINVAL;
3832
3833 new_entry = READ_ONCE(*entry);
3834 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
3835 new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
3836 if (valid)
3837 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3838 else
3839 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3840 WRITE_ONCE(*entry, new_entry);
3841
3842 return 0;
3843}
3844
3845static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
3846{
3847 int ret;
3848 struct vcpu_svm *svm = to_svm(vcpu);
3849 u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
3850
3851 if (!ldr)
3852 return 1;
3853
3854 ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
3855 if (ret && svm->ldr_reg) {
3856 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
3857 svm->ldr_reg = 0;
3858 } else {
3859 svm->ldr_reg = ldr;
3860 }
3861 return ret;
3862}
3863
3864static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
3865{
3866 u64 *old, *new;
3867 struct vcpu_svm *svm = to_svm(vcpu);
3868 u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
3869 u32 id = (apic_id_reg >> 24) & 0xff;
3870
3871 if (vcpu->vcpu_id == id)
3872 return 0;
3873
3874 old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
3875 new = avic_get_physical_id_entry(vcpu, id);
3876 if (!new || !old)
3877 return 1;
3878
3879 /* We need to move physical_id_entry to new offset */
3880 *new = *old;
3881 *old = 0ULL;
3882 to_svm(vcpu)->avic_physical_id_cache = new;
3883
3884 /*
3885 * Also update the guest physical APIC ID in the logical
3886 * APIC ID table entry if already setup the LDR.
3887 */
3888 if (svm->ldr_reg)
3889 avic_handle_ldr_update(vcpu);
3890
3891 return 0;
3892}
3893
3894static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
3895{
3896 struct vcpu_svm *svm = to_svm(vcpu);
3897 struct kvm_arch *vm_data = &vcpu->kvm->arch;
3898 u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
3899 u32 mod = (dfr >> 28) & 0xf;
3900
3901 /*
3902 * We assume that all local APICs are using the same type.
3903 * If this changes, we need to flush the AVIC logical
3904 * APID id table.
3905 */
3906 if (vm_data->ldr_mode == mod)
3907 return 0;
3908
3909 clear_page(page_address(vm_data->avic_logical_id_table_page));
3910 vm_data->ldr_mode = mod;
3911
3912 if (svm->ldr_reg)
3913 avic_handle_ldr_update(vcpu);
3914 return 0;
3915}
3916
3917static int avic_unaccel_trap_write(struct vcpu_svm *svm)
3918{
3919 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3920 u32 offset = svm->vmcb->control.exit_info_1 &
3921 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3922
3923 switch (offset) {
3924 case APIC_ID:
3925 if (avic_handle_apic_id_update(&svm->vcpu))
3926 return 0;
3927 break;
3928 case APIC_LDR:
3929 if (avic_handle_ldr_update(&svm->vcpu))
3930 return 0;
3931 break;
3932 case APIC_DFR:
3933 avic_handle_dfr_update(&svm->vcpu);
3934 break;
3935 default:
3936 break;
3937 }
3938
3939 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
3940
3941 return 1;
3942}
3943
3944static bool is_avic_unaccelerated_access_trap(u32 offset)
3945{
3946 bool ret = false;
3947
3948 switch (offset) {
3949 case APIC_ID:
3950 case APIC_EOI:
3951 case APIC_RRR:
3952 case APIC_LDR:
3953 case APIC_DFR:
3954 case APIC_SPIV:
3955 case APIC_ESR:
3956 case APIC_ICR:
3957 case APIC_LVTT:
3958 case APIC_LVTTHMR:
3959 case APIC_LVTPC:
3960 case APIC_LVT0:
3961 case APIC_LVT1:
3962 case APIC_LVTERR:
3963 case APIC_TMICT:
3964 case APIC_TDCR:
3965 ret = true;
3966 break;
3967 default:
3968 break;
3969 }
3970 return ret;
3971}
3972
3973static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
3974{
3975 int ret = 0;
3976 u32 offset = svm->vmcb->control.exit_info_1 &
3977 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3978 u32 vector = svm->vmcb->control.exit_info_2 &
3979 AVIC_UNACCEL_ACCESS_VECTOR_MASK;
3980 bool write = (svm->vmcb->control.exit_info_1 >> 32) &
3981 AVIC_UNACCEL_ACCESS_WRITE_MASK;
3982 bool trap = is_avic_unaccelerated_access_trap(offset);
3983
3984 trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
3985 trap, write, vector);
3986 if (trap) {
3987 /* Handling Trap */
3988 WARN_ONCE(!write, "svm: Handling trap read.\n");
3989 ret = avic_unaccel_trap_write(svm);
3990 } else {
3991 /* Handling Fault */
3992 ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
3993 }
3994
3995 return ret;
3996}
3997
3998static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3999 [SVM_EXIT_READ_CR0] = cr_interception,
4000 [SVM_EXIT_READ_CR3] = cr_interception,
4001 [SVM_EXIT_READ_CR4] = cr_interception,
4002 [SVM_EXIT_READ_CR8] = cr_interception,
4003 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
4004 [SVM_EXIT_WRITE_CR0] = cr_interception,
4005 [SVM_EXIT_WRITE_CR3] = cr_interception,
4006 [SVM_EXIT_WRITE_CR4] = cr_interception,
4007 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
4008 [SVM_EXIT_READ_DR0] = dr_interception,
4009 [SVM_EXIT_READ_DR1] = dr_interception,
4010 [SVM_EXIT_READ_DR2] = dr_interception,
4011 [SVM_EXIT_READ_DR3] = dr_interception,
4012 [SVM_EXIT_READ_DR4] = dr_interception,
4013 [SVM_EXIT_READ_DR5] = dr_interception,
4014 [SVM_EXIT_READ_DR6] = dr_interception,
4015 [SVM_EXIT_READ_DR7] = dr_interception,
4016 [SVM_EXIT_WRITE_DR0] = dr_interception,
4017 [SVM_EXIT_WRITE_DR1] = dr_interception,
4018 [SVM_EXIT_WRITE_DR2] = dr_interception,
4019 [SVM_EXIT_WRITE_DR3] = dr_interception,
4020 [SVM_EXIT_WRITE_DR4] = dr_interception,
4021 [SVM_EXIT_WRITE_DR5] = dr_interception,
4022 [SVM_EXIT_WRITE_DR6] = dr_interception,
4023 [SVM_EXIT_WRITE_DR7] = dr_interception,
4024 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
4025 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
4026 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
4027 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
4028 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
4029 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
4030 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
4031 [SVM_EXIT_INTR] = intr_interception,
4032 [SVM_EXIT_NMI] = nmi_interception,
4033 [SVM_EXIT_SMI] = nop_on_interception,
4034 [SVM_EXIT_INIT] = nop_on_interception,
4035 [SVM_EXIT_VINTR] = interrupt_window_interception,
4036 [SVM_EXIT_RDPMC] = rdpmc_interception,
4037 [SVM_EXIT_CPUID] = cpuid_interception,
4038 [SVM_EXIT_IRET] = iret_interception,
4039 [SVM_EXIT_INVD] = emulate_on_interception,
4040 [SVM_EXIT_PAUSE] = pause_interception,
4041 [SVM_EXIT_HLT] = halt_interception,
4042 [SVM_EXIT_INVLPG] = invlpg_interception,
4043 [SVM_EXIT_INVLPGA] = invlpga_interception,
4044 [SVM_EXIT_IOIO] = io_interception,
4045 [SVM_EXIT_MSR] = msr_interception,
4046 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
4047 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
4048 [SVM_EXIT_VMRUN] = vmrun_interception,
4049 [SVM_EXIT_VMMCALL] = vmmcall_interception,
4050 [SVM_EXIT_VMLOAD] = vmload_interception,
4051 [SVM_EXIT_VMSAVE] = vmsave_interception,
4052 [SVM_EXIT_STGI] = stgi_interception,
4053 [SVM_EXIT_CLGI] = clgi_interception,
4054 [SVM_EXIT_SKINIT] = skinit_interception,
4055 [SVM_EXIT_WBINVD] = wbinvd_interception,
4056 [SVM_EXIT_MONITOR] = monitor_interception,
4057 [SVM_EXIT_MWAIT] = mwait_interception,
4058 [SVM_EXIT_XSETBV] = xsetbv_interception,
4059 [SVM_EXIT_NPF] = pf_interception,
4060 [SVM_EXIT_RSM] = emulate_on_interception,
4061 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
4062 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
4063};
4064
4065static void dump_vmcb(struct kvm_vcpu *vcpu)
4066{
4067 struct vcpu_svm *svm = to_svm(vcpu);
4068 struct vmcb_control_area *control = &svm->vmcb->control;
4069 struct vmcb_save_area *save = &svm->vmcb->save;
4070
4071 pr_err("VMCB Control Area:\n");
4072 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4073 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4074 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4075 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4076 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4077 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4078 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4079 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4080 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4081 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4082 pr_err("%-20s%d\n", "asid:", control->asid);
4083 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4084 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4085 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4086 pr_err("%-20s%08x\n", "int_state:", control->int_state);
4087 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4088 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4089 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4090 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4091 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4092 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4093 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4094 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4095 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4096 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4097 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
4098 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4099 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4100 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4101 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4102 pr_err("VMCB State Save Area:\n");
4103 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4104 "es:",
4105 save->es.selector, save->es.attrib,
4106 save->es.limit, save->es.base);
4107 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4108 "cs:",
4109 save->cs.selector, save->cs.attrib,
4110 save->cs.limit, save->cs.base);
4111 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4112 "ss:",
4113 save->ss.selector, save->ss.attrib,
4114 save->ss.limit, save->ss.base);
4115 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4116 "ds:",
4117 save->ds.selector, save->ds.attrib,
4118 save->ds.limit, save->ds.base);
4119 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4120 "fs:",
4121 save->fs.selector, save->fs.attrib,
4122 save->fs.limit, save->fs.base);
4123 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4124 "gs:",
4125 save->gs.selector, save->gs.attrib,
4126 save->gs.limit, save->gs.base);
4127 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4128 "gdtr:",
4129 save->gdtr.selector, save->gdtr.attrib,
4130 save->gdtr.limit, save->gdtr.base);
4131 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4132 "ldtr:",
4133 save->ldtr.selector, save->ldtr.attrib,
4134 save->ldtr.limit, save->ldtr.base);
4135 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4136 "idtr:",
4137 save->idtr.selector, save->idtr.attrib,
4138 save->idtr.limit, save->idtr.base);
4139 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4140 "tr:",
4141 save->tr.selector, save->tr.attrib,
4142 save->tr.limit, save->tr.base);
4143 pr_err("cpl: %d efer: %016llx\n",
4144 save->cpl, save->efer);
4145 pr_err("%-15s %016llx %-13s %016llx\n",
4146 "cr0:", save->cr0, "cr2:", save->cr2);
4147 pr_err("%-15s %016llx %-13s %016llx\n",
4148 "cr3:", save->cr3, "cr4:", save->cr4);
4149 pr_err("%-15s %016llx %-13s %016llx\n",
4150 "dr6:", save->dr6, "dr7:", save->dr7);
4151 pr_err("%-15s %016llx %-13s %016llx\n",
4152 "rip:", save->rip, "rflags:", save->rflags);
4153 pr_err("%-15s %016llx %-13s %016llx\n",
4154 "rsp:", save->rsp, "rax:", save->rax);
4155 pr_err("%-15s %016llx %-13s %016llx\n",
4156 "star:", save->star, "lstar:", save->lstar);
4157 pr_err("%-15s %016llx %-13s %016llx\n",
4158 "cstar:", save->cstar, "sfmask:", save->sfmask);
4159 pr_err("%-15s %016llx %-13s %016llx\n",
4160 "kernel_gs_base:", save->kernel_gs_base,
4161 "sysenter_cs:", save->sysenter_cs);
4162 pr_err("%-15s %016llx %-13s %016llx\n",
4163 "sysenter_esp:", save->sysenter_esp,
4164 "sysenter_eip:", save->sysenter_eip);
4165 pr_err("%-15s %016llx %-13s %016llx\n",
4166 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4167 pr_err("%-15s %016llx %-13s %016llx\n",
4168 "br_from:", save->br_from, "br_to:", save->br_to);
4169 pr_err("%-15s %016llx %-13s %016llx\n",
4170 "excp_from:", save->last_excp_from,
4171 "excp_to:", save->last_excp_to);
4172}
4173
4174static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4175{
4176 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4177
4178 *info1 = control->exit_info_1;
4179 *info2 = control->exit_info_2;
4180}
4181
4182static int handle_exit(struct kvm_vcpu *vcpu)
4183{
4184 struct vcpu_svm *svm = to_svm(vcpu);
4185 struct kvm_run *kvm_run = vcpu->run;
4186 u32 exit_code = svm->vmcb->control.exit_code;
4187
4188 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4189
4190 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4191 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4192 if (npt_enabled)
4193 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4194
4195 if (unlikely(svm->nested.exit_required)) {
4196 nested_svm_vmexit(svm);
4197 svm->nested.exit_required = false;
4198
4199 return 1;
4200 }
4201
4202 if (is_guest_mode(vcpu)) {
4203 int vmexit;
4204
4205 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4206 svm->vmcb->control.exit_info_1,
4207 svm->vmcb->control.exit_info_2,
4208 svm->vmcb->control.exit_int_info,
4209 svm->vmcb->control.exit_int_info_err,
4210 KVM_ISA_SVM);
4211
4212 vmexit = nested_svm_exit_special(svm);
4213
4214 if (vmexit == NESTED_EXIT_CONTINUE)
4215 vmexit = nested_svm_exit_handled(svm);
4216
4217 if (vmexit == NESTED_EXIT_DONE)
4218 return 1;
4219 }
4220
4221 svm_complete_interrupts(svm);
4222
4223 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4224 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4225 kvm_run->fail_entry.hardware_entry_failure_reason
4226 = svm->vmcb->control.exit_code;
4227 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4228 dump_vmcb(vcpu);
4229 return 0;
4230 }
4231
4232 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4233 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4234 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4235 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4236 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4237 "exit_code 0x%x\n",
4238 __func__, svm->vmcb->control.exit_int_info,
4239 exit_code);
4240
4241 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4242 || !svm_exit_handlers[exit_code]) {
4243 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4244 kvm_queue_exception(vcpu, UD_VECTOR);
4245 return 1;
4246 }
4247
4248 return svm_exit_handlers[exit_code](svm);
4249}
4250
4251static void reload_tss(struct kvm_vcpu *vcpu)
4252{
4253 int cpu = raw_smp_processor_id();
4254
4255 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4256 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4257 load_TR_desc();
4258}
4259
4260static void pre_svm_run(struct vcpu_svm *svm)
4261{
4262 int cpu = raw_smp_processor_id();
4263
4264 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4265
4266 /* FIXME: handle wraparound of asid_generation */
4267 if (svm->asid_generation != sd->asid_generation)
4268 new_asid(svm, sd);
4269}
4270
4271static void svm_inject_nmi(struct kvm_vcpu *vcpu)
4272{
4273 struct vcpu_svm *svm = to_svm(vcpu);
4274
4275 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
4276 vcpu->arch.hflags |= HF_NMI_MASK;
4277 set_intercept(svm, INTERCEPT_IRET);
4278 ++vcpu->stat.nmi_injections;
4279}
4280
4281static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
4282{
4283 struct vmcb_control_area *control;
4284
4285 /* The following fields are ignored when AVIC is enabled */
4286 control = &svm->vmcb->control;
4287 control->int_vector = irq;
4288 control->int_ctl &= ~V_INTR_PRIO_MASK;
4289 control->int_ctl |= V_IRQ_MASK |
4290 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
4291 mark_dirty(svm->vmcb, VMCB_INTR);
4292}
4293
4294static void svm_set_irq(struct kvm_vcpu *vcpu)
4295{
4296 struct vcpu_svm *svm = to_svm(vcpu);
4297
4298 BUG_ON(!(gif_set(svm)));
4299
4300 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
4301 ++vcpu->stat.irq_injections;
4302
4303 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
4304 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
4305}
4306
4307static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
4308{
4309 return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
4310}
4311
4312static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
4313{
4314 struct vcpu_svm *svm = to_svm(vcpu);
4315
4316 if (svm_nested_virtualize_tpr(vcpu) ||
4317 kvm_vcpu_apicv_active(vcpu))
4318 return;
4319
4320 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4321
4322 if (irr == -1)
4323 return;
4324
4325 if (tpr >= irr)
4326 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4327}
4328
4329static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
4330{
4331 return;
4332}
4333
4334static bool svm_get_enable_apicv(void)
4335{
4336 return avic;
4337}
4338
4339static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
4340{
4341}
4342
4343static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
4344{
4345}
4346
4347/* Note: Currently only used by Hyper-V. */
4348static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4349{
4350 struct vcpu_svm *svm = to_svm(vcpu);
4351 struct vmcb *vmcb = svm->vmcb;
4352
4353 if (!avic)
4354 return;
4355
4356 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
4357 mark_dirty(vmcb, VMCB_INTR);
4358}
4359
4360static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
4361{
4362 return;
4363}
4364
4365static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4366{
4367 return;
4368}
4369
4370static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
4371{
4372 kvm_lapic_set_irr(vec, vcpu->arch.apic);
4373 smp_mb__after_atomic();
4374
4375 if (avic_vcpu_is_running(vcpu))
4376 wrmsrl(SVM_AVIC_DOORBELL,
4377 kvm_cpu_get_apicid(vcpu->cpu));
4378 else
4379 kvm_vcpu_wake_up(vcpu);
4380}
4381
4382static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4383{
4384 unsigned long flags;
4385 struct amd_svm_iommu_ir *cur;
4386
4387 spin_lock_irqsave(&svm->ir_list_lock, flags);
4388 list_for_each_entry(cur, &svm->ir_list, node) {
4389 if (cur->data != pi->ir_data)
4390 continue;
4391 list_del(&cur->node);
4392 kfree(cur);
4393 break;
4394 }
4395 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4396}
4397
4398static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4399{
4400 int ret = 0;
4401 unsigned long flags;
4402 struct amd_svm_iommu_ir *ir;
4403
4404 /**
4405 * In some cases, the existing irte is updaed and re-set,
4406 * so we need to check here if it's already been * added
4407 * to the ir_list.
4408 */
4409 if (pi->ir_data && (pi->prev_ga_tag != 0)) {
4410 struct kvm *kvm = svm->vcpu.kvm;
4411 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
4412 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
4413 struct vcpu_svm *prev_svm;
4414
4415 if (!prev_vcpu) {
4416 ret = -EINVAL;
4417 goto out;
4418 }
4419
4420 prev_svm = to_svm(prev_vcpu);
4421 svm_ir_list_del(prev_svm, pi);
4422 }
4423
4424 /**
4425 * Allocating new amd_iommu_pi_data, which will get
4426 * add to the per-vcpu ir_list.
4427 */
4428 ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
4429 if (!ir) {
4430 ret = -ENOMEM;
4431 goto out;
4432 }
4433 ir->data = pi->ir_data;
4434
4435 spin_lock_irqsave(&svm->ir_list_lock, flags);
4436 list_add(&ir->node, &svm->ir_list);
4437 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4438out:
4439 return ret;
4440}
4441
4442/**
4443 * Note:
4444 * The HW cannot support posting multicast/broadcast
4445 * interrupts to a vCPU. So, we still use legacy interrupt
4446 * remapping for these kind of interrupts.
4447 *
4448 * For lowest-priority interrupts, we only support
4449 * those with single CPU as the destination, e.g. user
4450 * configures the interrupts via /proc/irq or uses
4451 * irqbalance to make the interrupts single-CPU.
4452 */
4453static int
4454get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
4455 struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
4456{
4457 struct kvm_lapic_irq irq;
4458 struct kvm_vcpu *vcpu = NULL;
4459
4460 kvm_set_msi_irq(kvm, e, &irq);
4461
4462 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
4463 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
4464 __func__, irq.vector);
4465 return -1;
4466 }
4467
4468 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
4469 irq.vector);
4470 *svm = to_svm(vcpu);
4471 vcpu_info->pi_desc_addr = page_to_phys((*svm)->avic_backing_page);
4472 vcpu_info->vector = irq.vector;
4473
4474 return 0;
4475}
4476
4477/*
4478 * svm_update_pi_irte - set IRTE for Posted-Interrupts
4479 *
4480 * @kvm: kvm
4481 * @host_irq: host irq of the interrupt
4482 * @guest_irq: gsi of the interrupt
4483 * @set: set or unset PI
4484 * returns 0 on success, < 0 on failure
4485 */
4486static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
4487 uint32_t guest_irq, bool set)
4488{
4489 struct kvm_kernel_irq_routing_entry *e;
4490 struct kvm_irq_routing_table *irq_rt;
4491 int idx, ret = -EINVAL;
4492
4493 if (!kvm_arch_has_assigned_device(kvm) ||
4494 !irq_remapping_cap(IRQ_POSTING_CAP))
4495 return 0;
4496
4497 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
4498 __func__, host_irq, guest_irq, set);
4499
4500 idx = srcu_read_lock(&kvm->irq_srcu);
4501 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
4502 WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
4503
4504 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
4505 struct vcpu_data vcpu_info;
4506 struct vcpu_svm *svm = NULL;
4507
4508 if (e->type != KVM_IRQ_ROUTING_MSI)
4509 continue;
4510
4511 /**
4512 * Here, we setup with legacy mode in the following cases:
4513 * 1. When cannot target interrupt to a specific vcpu.
4514 * 2. Unsetting posted interrupt.
4515 * 3. APIC virtialization is disabled for the vcpu.
4516 */
4517 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
4518 kvm_vcpu_apicv_active(&svm->vcpu)) {
4519 struct amd_iommu_pi_data pi;
4520
4521 /* Try to enable guest_mode in IRTE */
4522 pi.base = page_to_phys(svm->avic_backing_page) & AVIC_HPA_MASK;
4523 pi.ga_tag = AVIC_GATAG(kvm->arch.avic_vm_id,
4524 svm->vcpu.vcpu_id);
4525 pi.is_guest_mode = true;
4526 pi.vcpu_data = &vcpu_info;
4527 ret = irq_set_vcpu_affinity(host_irq, &pi);
4528
4529 /**
4530 * Here, we successfully setting up vcpu affinity in
4531 * IOMMU guest mode. Now, we need to store the posted
4532 * interrupt information in a per-vcpu ir_list so that
4533 * we can reference to them directly when we update vcpu
4534 * scheduling information in IOMMU irte.
4535 */
4536 if (!ret && pi.is_guest_mode)
4537 svm_ir_list_add(svm, &pi);
4538 } else {
4539 /* Use legacy mode in IRTE */
4540 struct amd_iommu_pi_data pi;
4541
4542 /**
4543 * Here, pi is used to:
4544 * - Tell IOMMU to use legacy mode for this interrupt.
4545 * - Retrieve ga_tag of prior interrupt remapping data.
4546 */
4547 pi.is_guest_mode = false;
4548 ret = irq_set_vcpu_affinity(host_irq, &pi);
4549
4550 /**
4551 * Check if the posted interrupt was previously
4552 * setup with the guest_mode by checking if the ga_tag
4553 * was cached. If so, we need to clean up the per-vcpu
4554 * ir_list.
4555 */
4556 if (!ret && pi.prev_ga_tag) {
4557 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
4558 struct kvm_vcpu *vcpu;
4559
4560 vcpu = kvm_get_vcpu_by_id(kvm, id);
4561 if (vcpu)
4562 svm_ir_list_del(to_svm(vcpu), &pi);
4563 }
4564 }
4565
4566 if (!ret && svm) {
4567 trace_kvm_pi_irte_update(svm->vcpu.vcpu_id,
4568 host_irq, e->gsi,
4569 vcpu_info.vector,
4570 vcpu_info.pi_desc_addr, set);
4571 }
4572
4573 if (ret < 0) {
4574 pr_err("%s: failed to update PI IRTE\n", __func__);
4575 goto out;
4576 }
4577 }
4578
4579 ret = 0;
4580out:
4581 srcu_read_unlock(&kvm->irq_srcu, idx);
4582 return ret;
4583}
4584
4585static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
4586{
4587 struct vcpu_svm *svm = to_svm(vcpu);
4588 struct vmcb *vmcb = svm->vmcb;
4589 int ret;
4590 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
4591 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
4592 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
4593
4594 return ret;
4595}
4596
4597static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
4598{
4599 struct vcpu_svm *svm = to_svm(vcpu);
4600
4601 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
4602}
4603
4604static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4605{
4606 struct vcpu_svm *svm = to_svm(vcpu);
4607
4608 if (masked) {
4609 svm->vcpu.arch.hflags |= HF_NMI_MASK;
4610 set_intercept(svm, INTERCEPT_IRET);
4611 } else {
4612 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
4613 clr_intercept(svm, INTERCEPT_IRET);
4614 }
4615}
4616
4617static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
4618{
4619 struct vcpu_svm *svm = to_svm(vcpu);
4620 struct vmcb *vmcb = svm->vmcb;
4621 int ret;
4622
4623 if (!gif_set(svm) ||
4624 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
4625 return 0;
4626
4627 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
4628
4629 if (is_guest_mode(vcpu))
4630 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
4631
4632 return ret;
4633}
4634
4635static void enable_irq_window(struct kvm_vcpu *vcpu)
4636{
4637 struct vcpu_svm *svm = to_svm(vcpu);
4638
4639 if (kvm_vcpu_apicv_active(vcpu))
4640 return;
4641
4642 /*
4643 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
4644 * 1, because that's a separate STGI/VMRUN intercept. The next time we
4645 * get that intercept, this function will be called again though and
4646 * we'll get the vintr intercept.
4647 */
4648 if (gif_set(svm) && nested_svm_intr(svm)) {
4649 svm_set_vintr(svm);
4650 svm_inject_irq(svm, 0x0);
4651 }
4652}
4653
4654static void enable_nmi_window(struct kvm_vcpu *vcpu)
4655{
4656 struct vcpu_svm *svm = to_svm(vcpu);
4657
4658 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
4659 == HF_NMI_MASK)
4660 return; /* IRET will cause a vm exit */
4661
4662 /*
4663 * Something prevents NMI from been injected. Single step over possible
4664 * problem (IRET or exception injection or interrupt shadow)
4665 */
4666 svm->nmi_singlestep = true;
4667 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
4668}
4669
4670static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
4671{
4672 return 0;
4673}
4674
4675static void svm_flush_tlb(struct kvm_vcpu *vcpu)
4676{
4677 struct vcpu_svm *svm = to_svm(vcpu);
4678
4679 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
4680 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
4681 else
4682 svm->asid_generation--;
4683}
4684
4685static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
4686{
4687}
4688
4689static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
4690{
4691 struct vcpu_svm *svm = to_svm(vcpu);
4692
4693 if (svm_nested_virtualize_tpr(vcpu))
4694 return;
4695
4696 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
4697 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
4698 kvm_set_cr8(vcpu, cr8);
4699 }
4700}
4701
4702static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
4703{
4704 struct vcpu_svm *svm = to_svm(vcpu);
4705 u64 cr8;
4706
4707 if (svm_nested_virtualize_tpr(vcpu) ||
4708 kvm_vcpu_apicv_active(vcpu))
4709 return;
4710
4711 cr8 = kvm_get_cr8(vcpu);
4712 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
4713 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
4714}
4715
4716static void svm_complete_interrupts(struct vcpu_svm *svm)
4717{
4718 u8 vector;
4719 int type;
4720 u32 exitintinfo = svm->vmcb->control.exit_int_info;
4721 unsigned int3_injected = svm->int3_injected;
4722
4723 svm->int3_injected = 0;
4724
4725 /*
4726 * If we've made progress since setting HF_IRET_MASK, we've
4727 * executed an IRET and can allow NMI injection.
4728 */
4729 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
4730 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
4731 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
4732 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4733 }
4734
4735 svm->vcpu.arch.nmi_injected = false;
4736 kvm_clear_exception_queue(&svm->vcpu);
4737 kvm_clear_interrupt_queue(&svm->vcpu);
4738
4739 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
4740 return;
4741
4742 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4743
4744 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
4745 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
4746
4747 switch (type) {
4748 case SVM_EXITINTINFO_TYPE_NMI:
4749 svm->vcpu.arch.nmi_injected = true;
4750 break;
4751 case SVM_EXITINTINFO_TYPE_EXEPT:
4752 /*
4753 * In case of software exceptions, do not reinject the vector,
4754 * but re-execute the instruction instead. Rewind RIP first
4755 * if we emulated INT3 before.
4756 */
4757 if (kvm_exception_is_soft(vector)) {
4758 if (vector == BP_VECTOR && int3_injected &&
4759 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
4760 kvm_rip_write(&svm->vcpu,
4761 kvm_rip_read(&svm->vcpu) -
4762 int3_injected);
4763 break;
4764 }
4765 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
4766 u32 err = svm->vmcb->control.exit_int_info_err;
4767 kvm_requeue_exception_e(&svm->vcpu, vector, err);
4768
4769 } else
4770 kvm_requeue_exception(&svm->vcpu, vector);
4771 break;
4772 case SVM_EXITINTINFO_TYPE_INTR:
4773 kvm_queue_interrupt(&svm->vcpu, vector, false);
4774 break;
4775 default:
4776 break;
4777 }
4778}
4779
4780static void svm_cancel_injection(struct kvm_vcpu *vcpu)
4781{
4782 struct vcpu_svm *svm = to_svm(vcpu);
4783 struct vmcb_control_area *control = &svm->vmcb->control;
4784
4785 control->exit_int_info = control->event_inj;
4786 control->exit_int_info_err = control->event_inj_err;
4787 control->event_inj = 0;
4788 svm_complete_interrupts(svm);
4789}
4790
4791static void svm_vcpu_run(struct kvm_vcpu *vcpu)
4792{
4793 struct vcpu_svm *svm = to_svm(vcpu);
4794
4795 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4796 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4797 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4798
4799 /*
4800 * A vmexit emulation is required before the vcpu can be executed
4801 * again.
4802 */
4803 if (unlikely(svm->nested.exit_required))
4804 return;
4805
4806 pre_svm_run(svm);
4807
4808 sync_lapic_to_cr8(vcpu);
4809
4810 svm->vmcb->save.cr2 = vcpu->arch.cr2;
4811
4812 clgi();
4813
4814 local_irq_enable();
4815
4816 asm volatile (
4817 "push %%" _ASM_BP "; \n\t"
4818 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
4819 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
4820 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
4821 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
4822 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
4823 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
4824#ifdef CONFIG_X86_64
4825 "mov %c[r8](%[svm]), %%r8 \n\t"
4826 "mov %c[r9](%[svm]), %%r9 \n\t"
4827 "mov %c[r10](%[svm]), %%r10 \n\t"
4828 "mov %c[r11](%[svm]), %%r11 \n\t"
4829 "mov %c[r12](%[svm]), %%r12 \n\t"
4830 "mov %c[r13](%[svm]), %%r13 \n\t"
4831 "mov %c[r14](%[svm]), %%r14 \n\t"
4832 "mov %c[r15](%[svm]), %%r15 \n\t"
4833#endif
4834
4835 /* Enter guest mode */
4836 "push %%" _ASM_AX " \n\t"
4837 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
4838 __ex(SVM_VMLOAD) "\n\t"
4839 __ex(SVM_VMRUN) "\n\t"
4840 __ex(SVM_VMSAVE) "\n\t"
4841 "pop %%" _ASM_AX " \n\t"
4842
4843 /* Save guest registers, load host registers */
4844 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
4845 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
4846 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
4847 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
4848 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
4849 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
4850#ifdef CONFIG_X86_64
4851 "mov %%r8, %c[r8](%[svm]) \n\t"
4852 "mov %%r9, %c[r9](%[svm]) \n\t"
4853 "mov %%r10, %c[r10](%[svm]) \n\t"
4854 "mov %%r11, %c[r11](%[svm]) \n\t"
4855 "mov %%r12, %c[r12](%[svm]) \n\t"
4856 "mov %%r13, %c[r13](%[svm]) \n\t"
4857 "mov %%r14, %c[r14](%[svm]) \n\t"
4858 "mov %%r15, %c[r15](%[svm]) \n\t"
4859#endif
4860 "pop %%" _ASM_BP
4861 :
4862 : [svm]"a"(svm),
4863 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
4864 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
4865 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
4866 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
4867 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
4868 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
4869 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
4870#ifdef CONFIG_X86_64
4871 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
4872 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
4873 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
4874 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
4875 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
4876 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
4877 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
4878 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
4879#endif
4880 : "cc", "memory"
4881#ifdef CONFIG_X86_64
4882 , "rbx", "rcx", "rdx", "rsi", "rdi"
4883 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
4884#else
4885 , "ebx", "ecx", "edx", "esi", "edi"
4886#endif
4887 );
4888
4889#ifdef CONFIG_X86_64
4890 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
4891#else
4892 loadsegment(fs, svm->host.fs);
4893#ifndef CONFIG_X86_32_LAZY_GS
4894 loadsegment(gs, svm->host.gs);
4895#endif
4896#endif
4897
4898 reload_tss(vcpu);
4899
4900 local_irq_disable();
4901
4902 vcpu->arch.cr2 = svm->vmcb->save.cr2;
4903 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
4904 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
4905 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
4906
4907 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4908 kvm_before_handle_nmi(&svm->vcpu);
4909
4910 stgi();
4911
4912 /* Any pending NMI will happen here */
4913
4914 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4915 kvm_after_handle_nmi(&svm->vcpu);
4916
4917 sync_cr8_to_lapic(vcpu);
4918
4919 svm->next_rip = 0;
4920
4921 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4922
4923 /* if exit due to PF check for async PF */
4924 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
4925 svm->apf_reason = kvm_read_and_reset_pf_reason();
4926
4927 if (npt_enabled) {
4928 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
4929 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
4930 }
4931
4932 /*
4933 * We need to handle MC intercepts here before the vcpu has a chance to
4934 * change the physical cpu
4935 */
4936 if (unlikely(svm->vmcb->control.exit_code ==
4937 SVM_EXIT_EXCP_BASE + MC_VECTOR))
4938 svm_handle_mce(svm);
4939
4940 mark_all_clean(svm->vmcb);
4941}
4942
4943static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4944{
4945 struct vcpu_svm *svm = to_svm(vcpu);
4946
4947 svm->vmcb->save.cr3 = root;
4948 mark_dirty(svm->vmcb, VMCB_CR);
4949 svm_flush_tlb(vcpu);
4950}
4951
4952static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4953{
4954 struct vcpu_svm *svm = to_svm(vcpu);
4955
4956 svm->vmcb->control.nested_cr3 = root;
4957 mark_dirty(svm->vmcb, VMCB_NPT);
4958
4959 /* Also sync guest cr3 here in case we live migrate */
4960 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
4961 mark_dirty(svm->vmcb, VMCB_CR);
4962
4963 svm_flush_tlb(vcpu);
4964}
4965
4966static int is_disabled(void)
4967{
4968 u64 vm_cr;
4969
4970 rdmsrl(MSR_VM_CR, vm_cr);
4971 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
4972 return 1;
4973
4974 return 0;
4975}
4976
4977static void
4978svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4979{
4980 /*
4981 * Patch in the VMMCALL instruction:
4982 */
4983 hypercall[0] = 0x0f;
4984 hypercall[1] = 0x01;
4985 hypercall[2] = 0xd9;
4986}
4987
4988static void svm_check_processor_compat(void *rtn)
4989{
4990 *(int *)rtn = 0;
4991}
4992
4993static bool svm_cpu_has_accelerated_tpr(void)
4994{
4995 return false;
4996}
4997
4998static bool svm_has_high_real_mode_segbase(void)
4999{
5000 return true;
5001}
5002
5003static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5004{
5005 return 0;
5006}
5007
5008static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5009{
5010 struct vcpu_svm *svm = to_svm(vcpu);
5011 struct kvm_cpuid_entry2 *entry;
5012
5013 /* Update nrips enabled cache */
5014 svm->nrips_enabled = !!guest_cpuid_has_nrips(&svm->vcpu);
5015
5016 if (!kvm_vcpu_apicv_active(vcpu))
5017 return;
5018
5019 entry = kvm_find_cpuid_entry(vcpu, 1, 0);
5020 if (entry)
5021 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5022}
5023
5024static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5025{
5026 switch (func) {
5027 case 0x1:
5028 if (avic)
5029 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5030 break;
5031 case 0x80000001:
5032 if (nested)
5033 entry->ecx |= (1 << 2); /* Set SVM bit */
5034 break;
5035 case 0x8000000A:
5036 entry->eax = 1; /* SVM revision 1 */
5037 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5038 ASID emulation to nested SVM */
5039 entry->ecx = 0; /* Reserved */
5040 entry->edx = 0; /* Per default do not support any
5041 additional features */
5042
5043 /* Support next_rip if host supports it */
5044 if (boot_cpu_has(X86_FEATURE_NRIPS))
5045 entry->edx |= SVM_FEATURE_NRIP;
5046
5047 /* Support NPT for the guest if enabled */
5048 if (npt_enabled)
5049 entry->edx |= SVM_FEATURE_NPT;
5050
5051 break;
5052 }
5053}
5054
5055static int svm_get_lpage_level(void)
5056{
5057 return PT_PDPE_LEVEL;
5058}
5059
5060static bool svm_rdtscp_supported(void)
5061{
5062 return boot_cpu_has(X86_FEATURE_RDTSCP);
5063}
5064
5065static bool svm_invpcid_supported(void)
5066{
5067 return false;
5068}
5069
5070static bool svm_mpx_supported(void)
5071{
5072 return false;
5073}
5074
5075static bool svm_xsaves_supported(void)
5076{
5077 return false;
5078}
5079
5080static bool svm_has_wbinvd_exit(void)
5081{
5082 return true;
5083}
5084
5085static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
5086{
5087 struct vcpu_svm *svm = to_svm(vcpu);
5088
5089 set_exception_intercept(svm, NM_VECTOR);
5090 update_cr0_intercept(svm);
5091}
5092
5093#define PRE_EX(exit) { .exit_code = (exit), \
5094 .stage = X86_ICPT_PRE_EXCEPT, }
5095#define POST_EX(exit) { .exit_code = (exit), \
5096 .stage = X86_ICPT_POST_EXCEPT, }
5097#define POST_MEM(exit) { .exit_code = (exit), \
5098 .stage = X86_ICPT_POST_MEMACCESS, }
5099
5100static const struct __x86_intercept {
5101 u32 exit_code;
5102 enum x86_intercept_stage stage;
5103} x86_intercept_map[] = {
5104 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
5105 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
5106 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
5107 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
5108 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
5109 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
5110 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
5111 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
5112 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
5113 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
5114 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
5115 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
5116 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
5117 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
5118 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
5119 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
5120 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
5121 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
5122 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
5123 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
5124 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
5125 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
5126 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
5127 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
5128 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
5129 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
5130 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
5131 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
5132 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
5133 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
5134 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
5135 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
5136 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
5137 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
5138 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
5139 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
5140 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
5141 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
5142 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
5143 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
5144 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
5145 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
5146 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
5147 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
5148 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
5149 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
5150};
5151
5152#undef PRE_EX
5153#undef POST_EX
5154#undef POST_MEM
5155
5156static int svm_check_intercept(struct kvm_vcpu *vcpu,
5157 struct x86_instruction_info *info,
5158 enum x86_intercept_stage stage)
5159{
5160 struct vcpu_svm *svm = to_svm(vcpu);
5161 int vmexit, ret = X86EMUL_CONTINUE;
5162 struct __x86_intercept icpt_info;
5163 struct vmcb *vmcb = svm->vmcb;
5164
5165 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
5166 goto out;
5167
5168 icpt_info = x86_intercept_map[info->intercept];
5169
5170 if (stage != icpt_info.stage)
5171 goto out;
5172
5173 switch (icpt_info.exit_code) {
5174 case SVM_EXIT_READ_CR0:
5175 if (info->intercept == x86_intercept_cr_read)
5176 icpt_info.exit_code += info->modrm_reg;
5177 break;
5178 case SVM_EXIT_WRITE_CR0: {
5179 unsigned long cr0, val;
5180 u64 intercept;
5181
5182 if (info->intercept == x86_intercept_cr_write)
5183 icpt_info.exit_code += info->modrm_reg;
5184
5185 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
5186 info->intercept == x86_intercept_clts)
5187 break;
5188
5189 intercept = svm->nested.intercept;
5190
5191 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
5192 break;
5193
5194 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
5195 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
5196
5197 if (info->intercept == x86_intercept_lmsw) {
5198 cr0 &= 0xfUL;
5199 val &= 0xfUL;
5200 /* lmsw can't clear PE - catch this here */
5201 if (cr0 & X86_CR0_PE)
5202 val |= X86_CR0_PE;
5203 }
5204
5205 if (cr0 ^ val)
5206 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
5207
5208 break;
5209 }
5210 case SVM_EXIT_READ_DR0:
5211 case SVM_EXIT_WRITE_DR0:
5212 icpt_info.exit_code += info->modrm_reg;
5213 break;
5214 case SVM_EXIT_MSR:
5215 if (info->intercept == x86_intercept_wrmsr)
5216 vmcb->control.exit_info_1 = 1;
5217 else
5218 vmcb->control.exit_info_1 = 0;
5219 break;
5220 case SVM_EXIT_PAUSE:
5221 /*
5222 * We get this for NOP only, but pause
5223 * is rep not, check this here
5224 */
5225 if (info->rep_prefix != REPE_PREFIX)
5226 goto out;
5227 case SVM_EXIT_IOIO: {
5228 u64 exit_info;
5229 u32 bytes;
5230
5231 if (info->intercept == x86_intercept_in ||
5232 info->intercept == x86_intercept_ins) {
5233 exit_info = ((info->src_val & 0xffff) << 16) |
5234 SVM_IOIO_TYPE_MASK;
5235 bytes = info->dst_bytes;
5236 } else {
5237 exit_info = (info->dst_val & 0xffff) << 16;
5238 bytes = info->src_bytes;
5239 }
5240
5241 if (info->intercept == x86_intercept_outs ||
5242 info->intercept == x86_intercept_ins)
5243 exit_info |= SVM_IOIO_STR_MASK;
5244
5245 if (info->rep_prefix)
5246 exit_info |= SVM_IOIO_REP_MASK;
5247
5248 bytes = min(bytes, 4u);
5249
5250 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
5251
5252 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
5253
5254 vmcb->control.exit_info_1 = exit_info;
5255 vmcb->control.exit_info_2 = info->next_rip;
5256
5257 break;
5258 }
5259 default:
5260 break;
5261 }
5262
5263 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
5264 if (static_cpu_has(X86_FEATURE_NRIPS))
5265 vmcb->control.next_rip = info->next_rip;
5266 vmcb->control.exit_code = icpt_info.exit_code;
5267 vmexit = nested_svm_exit_handled(svm);
5268
5269 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
5270 : X86EMUL_CONTINUE;
5271
5272out:
5273 return ret;
5274}
5275
5276static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
5277{
5278 local_irq_enable();
5279 /*
5280 * We must have an instruction with interrupts enabled, so
5281 * the timer interrupt isn't delayed by the interrupt shadow.
5282 */
5283 asm("nop");
5284 local_irq_disable();
5285}
5286
5287static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
5288{
5289}
5290
5291static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
5292{
5293 if (avic_handle_apic_id_update(vcpu) != 0)
5294 return;
5295 if (avic_handle_dfr_update(vcpu) != 0)
5296 return;
5297 avic_handle_ldr_update(vcpu);
5298}
5299
5300static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
5301 .cpu_has_kvm_support = has_svm,
5302 .disabled_by_bios = is_disabled,
5303 .hardware_setup = svm_hardware_setup,
5304 .hardware_unsetup = svm_hardware_unsetup,
5305 .check_processor_compatibility = svm_check_processor_compat,
5306 .hardware_enable = svm_hardware_enable,
5307 .hardware_disable = svm_hardware_disable,
5308 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
5309 .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
5310
5311 .vcpu_create = svm_create_vcpu,
5312 .vcpu_free = svm_free_vcpu,
5313 .vcpu_reset = svm_vcpu_reset,
5314
5315 .vm_init = avic_vm_init,
5316 .vm_destroy = avic_vm_destroy,
5317
5318 .prepare_guest_switch = svm_prepare_guest_switch,
5319 .vcpu_load = svm_vcpu_load,
5320 .vcpu_put = svm_vcpu_put,
5321 .vcpu_blocking = svm_vcpu_blocking,
5322 .vcpu_unblocking = svm_vcpu_unblocking,
5323
5324 .update_bp_intercept = update_bp_intercept,
5325 .get_msr = svm_get_msr,
5326 .set_msr = svm_set_msr,
5327 .get_segment_base = svm_get_segment_base,
5328 .get_segment = svm_get_segment,
5329 .set_segment = svm_set_segment,
5330 .get_cpl = svm_get_cpl,
5331 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
5332 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
5333 .decache_cr3 = svm_decache_cr3,
5334 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
5335 .set_cr0 = svm_set_cr0,
5336 .set_cr3 = svm_set_cr3,
5337 .set_cr4 = svm_set_cr4,
5338 .set_efer = svm_set_efer,
5339 .get_idt = svm_get_idt,
5340 .set_idt = svm_set_idt,
5341 .get_gdt = svm_get_gdt,
5342 .set_gdt = svm_set_gdt,
5343 .get_dr6 = svm_get_dr6,
5344 .set_dr6 = svm_set_dr6,
5345 .set_dr7 = svm_set_dr7,
5346 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
5347 .cache_reg = svm_cache_reg,
5348 .get_rflags = svm_get_rflags,
5349 .set_rflags = svm_set_rflags,
5350
5351 .get_pkru = svm_get_pkru,
5352
5353 .fpu_activate = svm_fpu_activate,
5354 .fpu_deactivate = svm_fpu_deactivate,
5355
5356 .tlb_flush = svm_flush_tlb,
5357
5358 .run = svm_vcpu_run,
5359 .handle_exit = handle_exit,
5360 .skip_emulated_instruction = skip_emulated_instruction,
5361 .set_interrupt_shadow = svm_set_interrupt_shadow,
5362 .get_interrupt_shadow = svm_get_interrupt_shadow,
5363 .patch_hypercall = svm_patch_hypercall,
5364 .set_irq = svm_set_irq,
5365 .set_nmi = svm_inject_nmi,
5366 .queue_exception = svm_queue_exception,
5367 .cancel_injection = svm_cancel_injection,
5368 .interrupt_allowed = svm_interrupt_allowed,
5369 .nmi_allowed = svm_nmi_allowed,
5370 .get_nmi_mask = svm_get_nmi_mask,
5371 .set_nmi_mask = svm_set_nmi_mask,
5372 .enable_nmi_window = enable_nmi_window,
5373 .enable_irq_window = enable_irq_window,
5374 .update_cr8_intercept = update_cr8_intercept,
5375 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
5376 .get_enable_apicv = svm_get_enable_apicv,
5377 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
5378 .load_eoi_exitmap = svm_load_eoi_exitmap,
5379 .sync_pir_to_irr = svm_sync_pir_to_irr,
5380 .hwapic_irr_update = svm_hwapic_irr_update,
5381 .hwapic_isr_update = svm_hwapic_isr_update,
5382 .apicv_post_state_restore = avic_post_state_restore,
5383
5384 .set_tss_addr = svm_set_tss_addr,
5385 .get_tdp_level = get_npt_level,
5386 .get_mt_mask = svm_get_mt_mask,
5387
5388 .get_exit_info = svm_get_exit_info,
5389
5390 .get_lpage_level = svm_get_lpage_level,
5391
5392 .cpuid_update = svm_cpuid_update,
5393
5394 .rdtscp_supported = svm_rdtscp_supported,
5395 .invpcid_supported = svm_invpcid_supported,
5396 .mpx_supported = svm_mpx_supported,
5397 .xsaves_supported = svm_xsaves_supported,
5398
5399 .set_supported_cpuid = svm_set_supported_cpuid,
5400
5401 .has_wbinvd_exit = svm_has_wbinvd_exit,
5402
5403 .write_tsc_offset = svm_write_tsc_offset,
5404
5405 .set_tdp_cr3 = set_tdp_cr3,
5406
5407 .check_intercept = svm_check_intercept,
5408 .handle_external_intr = svm_handle_external_intr,
5409
5410 .sched_in = svm_sched_in,
5411
5412 .pmu_ops = &amd_pmu_ops,
5413 .deliver_posted_interrupt = svm_deliver_avic_intr,
5414 .update_pi_irte = svm_update_pi_irte,
5415};
5416
5417static int __init svm_init(void)
5418{
5419 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
5420 __alignof__(struct vcpu_svm), THIS_MODULE);
5421}
5422
5423static void __exit svm_exit(void)
5424{
5425 kvm_exit();
5426}
5427
5428module_init(svm_init)
5429module_exit(svm_exit)
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