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KVM: VMX: Require KVM_SET_TSS_ADDR being called prior to running a VCPU
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
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1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17#include <linux/kvm_host.h>
18
19#include "irq.h"
20#include "mmu.h"
21#include "kvm_cache_regs.h"
22#include "x86.h"
23#include "cpuid.h"
24
25#include <linux/module.h>
26#include <linux/mod_devicetable.h>
27#include <linux/kernel.h>
28#include <linux/vmalloc.h>
29#include <linux/highmem.h>
30#include <linux/sched.h>
31#include <linux/ftrace_event.h>
32#include <linux/slab.h>
33
34#include <asm/perf_event.h>
35#include <asm/tlbflush.h>
36#include <asm/desc.h>
37#include <asm/kvm_para.h>
38
39#include <asm/virtext.h>
40#include "trace.h"
41
42#define __ex(x) __kvm_handle_fault_on_reboot(x)
43
44MODULE_AUTHOR("Qumranet");
45MODULE_LICENSE("GPL");
46
47static const struct x86_cpu_id svm_cpu_id[] = {
48 X86_FEATURE_MATCH(X86_FEATURE_SVM),
49 {}
50};
51MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
52
53#define IOPM_ALLOC_ORDER 2
54#define MSRPM_ALLOC_ORDER 1
55
56#define SEG_TYPE_LDT 2
57#define SEG_TYPE_BUSY_TSS16 3
58
59#define SVM_FEATURE_NPT (1 << 0)
60#define SVM_FEATURE_LBRV (1 << 1)
61#define SVM_FEATURE_SVML (1 << 2)
62#define SVM_FEATURE_NRIP (1 << 3)
63#define SVM_FEATURE_TSC_RATE (1 << 4)
64#define SVM_FEATURE_VMCB_CLEAN (1 << 5)
65#define SVM_FEATURE_FLUSH_ASID (1 << 6)
66#define SVM_FEATURE_DECODE_ASSIST (1 << 7)
67#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
68
69#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
70#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
71#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
72
73#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
74
75#define TSC_RATIO_RSVD 0xffffff0000000000ULL
76#define TSC_RATIO_MIN 0x0000000000000001ULL
77#define TSC_RATIO_MAX 0x000000ffffffffffULL
78
79static bool erratum_383_found __read_mostly;
80
81static const u32 host_save_user_msrs[] = {
82#ifdef CONFIG_X86_64
83 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
84 MSR_FS_BASE,
85#endif
86 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
87};
88
89#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
90
91struct kvm_vcpu;
92
93struct nested_state {
94 struct vmcb *hsave;
95 u64 hsave_msr;
96 u64 vm_cr_msr;
97 u64 vmcb;
98
99 /* These are the merged vectors */
100 u32 *msrpm;
101
102 /* gpa pointers to the real vectors */
103 u64 vmcb_msrpm;
104 u64 vmcb_iopm;
105
106 /* A VMEXIT is required but not yet emulated */
107 bool exit_required;
108
109 /* cache for intercepts of the guest */
110 u32 intercept_cr;
111 u32 intercept_dr;
112 u32 intercept_exceptions;
113 u64 intercept;
114
115 /* Nested Paging related state */
116 u64 nested_cr3;
117};
118
119#define MSRPM_OFFSETS 16
120static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
121
122/*
123 * Set osvw_len to higher value when updated Revision Guides
124 * are published and we know what the new status bits are
125 */
126static uint64_t osvw_len = 4, osvw_status;
127
128struct vcpu_svm {
129 struct kvm_vcpu vcpu;
130 struct vmcb *vmcb;
131 unsigned long vmcb_pa;
132 struct svm_cpu_data *svm_data;
133 uint64_t asid_generation;
134 uint64_t sysenter_esp;
135 uint64_t sysenter_eip;
136
137 u64 next_rip;
138
139 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
140 struct {
141 u16 fs;
142 u16 gs;
143 u16 ldt;
144 u64 gs_base;
145 } host;
146
147 u32 *msrpm;
148
149 ulong nmi_iret_rip;
150
151 struct nested_state nested;
152
153 bool nmi_singlestep;
154
155 unsigned int3_injected;
156 unsigned long int3_rip;
157 u32 apf_reason;
158
159 u64 tsc_ratio;
160};
161
162static DEFINE_PER_CPU(u64, current_tsc_ratio);
163#define TSC_RATIO_DEFAULT 0x0100000000ULL
164
165#define MSR_INVALID 0xffffffffU
166
167static const struct svm_direct_access_msrs {
168 u32 index; /* Index of the MSR */
169 bool always; /* True if intercept is always on */
170} direct_access_msrs[] = {
171 { .index = MSR_STAR, .always = true },
172 { .index = MSR_IA32_SYSENTER_CS, .always = true },
173#ifdef CONFIG_X86_64
174 { .index = MSR_GS_BASE, .always = true },
175 { .index = MSR_FS_BASE, .always = true },
176 { .index = MSR_KERNEL_GS_BASE, .always = true },
177 { .index = MSR_LSTAR, .always = true },
178 { .index = MSR_CSTAR, .always = true },
179 { .index = MSR_SYSCALL_MASK, .always = true },
180#endif
181 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
182 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
183 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
184 { .index = MSR_IA32_LASTINTTOIP, .always = false },
185 { .index = MSR_INVALID, .always = false },
186};
187
188/* enable NPT for AMD64 and X86 with PAE */
189#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
190static bool npt_enabled = true;
191#else
192static bool npt_enabled;
193#endif
194
195/* allow nested paging (virtualized MMU) for all guests */
196static int npt = true;
197module_param(npt, int, S_IRUGO);
198
199/* allow nested virtualization in KVM/SVM */
200static int nested = true;
201module_param(nested, int, S_IRUGO);
202
203static void svm_flush_tlb(struct kvm_vcpu *vcpu);
204static void svm_complete_interrupts(struct vcpu_svm *svm);
205
206static int nested_svm_exit_handled(struct vcpu_svm *svm);
207static int nested_svm_intercept(struct vcpu_svm *svm);
208static int nested_svm_vmexit(struct vcpu_svm *svm);
209static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
210 bool has_error_code, u32 error_code);
211static u64 __scale_tsc(u64 ratio, u64 tsc);
212
213enum {
214 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
215 pause filter count */
216 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
217 VMCB_ASID, /* ASID */
218 VMCB_INTR, /* int_ctl, int_vector */
219 VMCB_NPT, /* npt_en, nCR3, gPAT */
220 VMCB_CR, /* CR0, CR3, CR4, EFER */
221 VMCB_DR, /* DR6, DR7 */
222 VMCB_DT, /* GDT, IDT */
223 VMCB_SEG, /* CS, DS, SS, ES, CPL */
224 VMCB_CR2, /* CR2 only */
225 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
226 VMCB_DIRTY_MAX,
227};
228
229/* TPR and CR2 are always written before VMRUN */
230#define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
231
232static inline void mark_all_dirty(struct vmcb *vmcb)
233{
234 vmcb->control.clean = 0;
235}
236
237static inline void mark_all_clean(struct vmcb *vmcb)
238{
239 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
240 & ~VMCB_ALWAYS_DIRTY_MASK;
241}
242
243static inline void mark_dirty(struct vmcb *vmcb, int bit)
244{
245 vmcb->control.clean &= ~(1 << bit);
246}
247
248static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
249{
250 return container_of(vcpu, struct vcpu_svm, vcpu);
251}
252
253static void recalc_intercepts(struct vcpu_svm *svm)
254{
255 struct vmcb_control_area *c, *h;
256 struct nested_state *g;
257
258 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
259
260 if (!is_guest_mode(&svm->vcpu))
261 return;
262
263 c = &svm->vmcb->control;
264 h = &svm->nested.hsave->control;
265 g = &svm->nested;
266
267 c->intercept_cr = h->intercept_cr | g->intercept_cr;
268 c->intercept_dr = h->intercept_dr | g->intercept_dr;
269 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
270 c->intercept = h->intercept | g->intercept;
271}
272
273static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
274{
275 if (is_guest_mode(&svm->vcpu))
276 return svm->nested.hsave;
277 else
278 return svm->vmcb;
279}
280
281static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
282{
283 struct vmcb *vmcb = get_host_vmcb(svm);
284
285 vmcb->control.intercept_cr |= (1U << bit);
286
287 recalc_intercepts(svm);
288}
289
290static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
291{
292 struct vmcb *vmcb = get_host_vmcb(svm);
293
294 vmcb->control.intercept_cr &= ~(1U << bit);
295
296 recalc_intercepts(svm);
297}
298
299static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
300{
301 struct vmcb *vmcb = get_host_vmcb(svm);
302
303 return vmcb->control.intercept_cr & (1U << bit);
304}
305
306static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
307{
308 struct vmcb *vmcb = get_host_vmcb(svm);
309
310 vmcb->control.intercept_dr |= (1U << bit);
311
312 recalc_intercepts(svm);
313}
314
315static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
316{
317 struct vmcb *vmcb = get_host_vmcb(svm);
318
319 vmcb->control.intercept_dr &= ~(1U << bit);
320
321 recalc_intercepts(svm);
322}
323
324static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
325{
326 struct vmcb *vmcb = get_host_vmcb(svm);
327
328 vmcb->control.intercept_exceptions |= (1U << bit);
329
330 recalc_intercepts(svm);
331}
332
333static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
334{
335 struct vmcb *vmcb = get_host_vmcb(svm);
336
337 vmcb->control.intercept_exceptions &= ~(1U << bit);
338
339 recalc_intercepts(svm);
340}
341
342static inline void set_intercept(struct vcpu_svm *svm, int bit)
343{
344 struct vmcb *vmcb = get_host_vmcb(svm);
345
346 vmcb->control.intercept |= (1ULL << bit);
347
348 recalc_intercepts(svm);
349}
350
351static inline void clr_intercept(struct vcpu_svm *svm, int bit)
352{
353 struct vmcb *vmcb = get_host_vmcb(svm);
354
355 vmcb->control.intercept &= ~(1ULL << bit);
356
357 recalc_intercepts(svm);
358}
359
360static inline void enable_gif(struct vcpu_svm *svm)
361{
362 svm->vcpu.arch.hflags |= HF_GIF_MASK;
363}
364
365static inline void disable_gif(struct vcpu_svm *svm)
366{
367 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
368}
369
370static inline bool gif_set(struct vcpu_svm *svm)
371{
372 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
373}
374
375static unsigned long iopm_base;
376
377struct kvm_ldttss_desc {
378 u16 limit0;
379 u16 base0;
380 unsigned base1:8, type:5, dpl:2, p:1;
381 unsigned limit1:4, zero0:3, g:1, base2:8;
382 u32 base3;
383 u32 zero1;
384} __attribute__((packed));
385
386struct svm_cpu_data {
387 int cpu;
388
389 u64 asid_generation;
390 u32 max_asid;
391 u32 next_asid;
392 struct kvm_ldttss_desc *tss_desc;
393
394 struct page *save_area;
395};
396
397static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
398
399struct svm_init_data {
400 int cpu;
401 int r;
402};
403
404static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
405
406#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
407#define MSRS_RANGE_SIZE 2048
408#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
409
410static u32 svm_msrpm_offset(u32 msr)
411{
412 u32 offset;
413 int i;
414
415 for (i = 0; i < NUM_MSR_MAPS; i++) {
416 if (msr < msrpm_ranges[i] ||
417 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
418 continue;
419
420 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
421 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
422
423 /* Now we have the u8 offset - but need the u32 offset */
424 return offset / 4;
425 }
426
427 /* MSR not in any range */
428 return MSR_INVALID;
429}
430
431#define MAX_INST_SIZE 15
432
433static inline void clgi(void)
434{
435 asm volatile (__ex(SVM_CLGI));
436}
437
438static inline void stgi(void)
439{
440 asm volatile (__ex(SVM_STGI));
441}
442
443static inline void invlpga(unsigned long addr, u32 asid)
444{
445 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
446}
447
448static int get_npt_level(void)
449{
450#ifdef CONFIG_X86_64
451 return PT64_ROOT_LEVEL;
452#else
453 return PT32E_ROOT_LEVEL;
454#endif
455}
456
457static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
458{
459 vcpu->arch.efer = efer;
460 if (!npt_enabled && !(efer & EFER_LMA))
461 efer &= ~EFER_LME;
462
463 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
464 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
465}
466
467static int is_external_interrupt(u32 info)
468{
469 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
470 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
471}
472
473static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
474{
475 struct vcpu_svm *svm = to_svm(vcpu);
476 u32 ret = 0;
477
478 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
479 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
480 return ret & mask;
481}
482
483static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
484{
485 struct vcpu_svm *svm = to_svm(vcpu);
486
487 if (mask == 0)
488 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
489 else
490 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
491
492}
493
494static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
495{
496 struct vcpu_svm *svm = to_svm(vcpu);
497
498 if (svm->vmcb->control.next_rip != 0)
499 svm->next_rip = svm->vmcb->control.next_rip;
500
501 if (!svm->next_rip) {
502 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
503 EMULATE_DONE)
504 printk(KERN_DEBUG "%s: NOP\n", __func__);
505 return;
506 }
507 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
508 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
509 __func__, kvm_rip_read(vcpu), svm->next_rip);
510
511 kvm_rip_write(vcpu, svm->next_rip);
512 svm_set_interrupt_shadow(vcpu, 0);
513}
514
515static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
516 bool has_error_code, u32 error_code,
517 bool reinject)
518{
519 struct vcpu_svm *svm = to_svm(vcpu);
520
521 /*
522 * If we are within a nested VM we'd better #VMEXIT and let the guest
523 * handle the exception
524 */
525 if (!reinject &&
526 nested_svm_check_exception(svm, nr, has_error_code, error_code))
527 return;
528
529 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
530 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
531
532 /*
533 * For guest debugging where we have to reinject #BP if some
534 * INT3 is guest-owned:
535 * Emulate nRIP by moving RIP forward. Will fail if injection
536 * raises a fault that is not intercepted. Still better than
537 * failing in all cases.
538 */
539 skip_emulated_instruction(&svm->vcpu);
540 rip = kvm_rip_read(&svm->vcpu);
541 svm->int3_rip = rip + svm->vmcb->save.cs.base;
542 svm->int3_injected = rip - old_rip;
543 }
544
545 svm->vmcb->control.event_inj = nr
546 | SVM_EVTINJ_VALID
547 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
548 | SVM_EVTINJ_TYPE_EXEPT;
549 svm->vmcb->control.event_inj_err = error_code;
550}
551
552static void svm_init_erratum_383(void)
553{
554 u32 low, high;
555 int err;
556 u64 val;
557
558 if (!cpu_has_amd_erratum(amd_erratum_383))
559 return;
560
561 /* Use _safe variants to not break nested virtualization */
562 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
563 if (err)
564 return;
565
566 val |= (1ULL << 47);
567
568 low = lower_32_bits(val);
569 high = upper_32_bits(val);
570
571 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
572
573 erratum_383_found = true;
574}
575
576static void svm_init_osvw(struct kvm_vcpu *vcpu)
577{
578 /*
579 * Guests should see errata 400 and 415 as fixed (assuming that
580 * HLT and IO instructions are intercepted).
581 */
582 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
583 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
584
585 /*
586 * By increasing VCPU's osvw.length to 3 we are telling the guest that
587 * all osvw.status bits inside that length, including bit 0 (which is
588 * reserved for erratum 298), are valid. However, if host processor's
589 * osvw_len is 0 then osvw_status[0] carries no information. We need to
590 * be conservative here and therefore we tell the guest that erratum 298
591 * is present (because we really don't know).
592 */
593 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
594 vcpu->arch.osvw.status |= 1;
595}
596
597static int has_svm(void)
598{
599 const char *msg;
600
601 if (!cpu_has_svm(&msg)) {
602 printk(KERN_INFO "has_svm: %s\n", msg);
603 return 0;
604 }
605
606 return 1;
607}
608
609static void svm_hardware_disable(void *garbage)
610{
611 /* Make sure we clean up behind us */
612 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
613 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
614
615 cpu_svm_disable();
616
617 amd_pmu_disable_virt();
618}
619
620static int svm_hardware_enable(void *garbage)
621{
622
623 struct svm_cpu_data *sd;
624 uint64_t efer;
625 struct desc_ptr gdt_descr;
626 struct desc_struct *gdt;
627 int me = raw_smp_processor_id();
628
629 rdmsrl(MSR_EFER, efer);
630 if (efer & EFER_SVME)
631 return -EBUSY;
632
633 if (!has_svm()) {
634 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
635 return -EINVAL;
636 }
637 sd = per_cpu(svm_data, me);
638 if (!sd) {
639 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
640 return -EINVAL;
641 }
642
643 sd->asid_generation = 1;
644 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
645 sd->next_asid = sd->max_asid + 1;
646
647 native_store_gdt(&gdt_descr);
648 gdt = (struct desc_struct *)gdt_descr.address;
649 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
650
651 wrmsrl(MSR_EFER, efer | EFER_SVME);
652
653 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
654
655 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
656 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
657 __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT;
658 }
659
660
661 /*
662 * Get OSVW bits.
663 *
664 * Note that it is possible to have a system with mixed processor
665 * revisions and therefore different OSVW bits. If bits are not the same
666 * on different processors then choose the worst case (i.e. if erratum
667 * is present on one processor and not on another then assume that the
668 * erratum is present everywhere).
669 */
670 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
671 uint64_t len, status = 0;
672 int err;
673
674 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
675 if (!err)
676 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
677 &err);
678
679 if (err)
680 osvw_status = osvw_len = 0;
681 else {
682 if (len < osvw_len)
683 osvw_len = len;
684 osvw_status |= status;
685 osvw_status &= (1ULL << osvw_len) - 1;
686 }
687 } else
688 osvw_status = osvw_len = 0;
689
690 svm_init_erratum_383();
691
692 amd_pmu_enable_virt();
693
694 return 0;
695}
696
697static void svm_cpu_uninit(int cpu)
698{
699 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
700
701 if (!sd)
702 return;
703
704 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
705 __free_page(sd->save_area);
706 kfree(sd);
707}
708
709static int svm_cpu_init(int cpu)
710{
711 struct svm_cpu_data *sd;
712 int r;
713
714 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
715 if (!sd)
716 return -ENOMEM;
717 sd->cpu = cpu;
718 sd->save_area = alloc_page(GFP_KERNEL);
719 r = -ENOMEM;
720 if (!sd->save_area)
721 goto err_1;
722
723 per_cpu(svm_data, cpu) = sd;
724
725 return 0;
726
727err_1:
728 kfree(sd);
729 return r;
730
731}
732
733static bool valid_msr_intercept(u32 index)
734{
735 int i;
736
737 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
738 if (direct_access_msrs[i].index == index)
739 return true;
740
741 return false;
742}
743
744static void set_msr_interception(u32 *msrpm, unsigned msr,
745 int read, int write)
746{
747 u8 bit_read, bit_write;
748 unsigned long tmp;
749 u32 offset;
750
751 /*
752 * If this warning triggers extend the direct_access_msrs list at the
753 * beginning of the file
754 */
755 WARN_ON(!valid_msr_intercept(msr));
756
757 offset = svm_msrpm_offset(msr);
758 bit_read = 2 * (msr & 0x0f);
759 bit_write = 2 * (msr & 0x0f) + 1;
760 tmp = msrpm[offset];
761
762 BUG_ON(offset == MSR_INVALID);
763
764 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
765 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
766
767 msrpm[offset] = tmp;
768}
769
770static void svm_vcpu_init_msrpm(u32 *msrpm)
771{
772 int i;
773
774 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
775
776 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
777 if (!direct_access_msrs[i].always)
778 continue;
779
780 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
781 }
782}
783
784static void add_msr_offset(u32 offset)
785{
786 int i;
787
788 for (i = 0; i < MSRPM_OFFSETS; ++i) {
789
790 /* Offset already in list? */
791 if (msrpm_offsets[i] == offset)
792 return;
793
794 /* Slot used by another offset? */
795 if (msrpm_offsets[i] != MSR_INVALID)
796 continue;
797
798 /* Add offset to list */
799 msrpm_offsets[i] = offset;
800
801 return;
802 }
803
804 /*
805 * If this BUG triggers the msrpm_offsets table has an overflow. Just
806 * increase MSRPM_OFFSETS in this case.
807 */
808 BUG();
809}
810
811static void init_msrpm_offsets(void)
812{
813 int i;
814
815 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
816
817 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
818 u32 offset;
819
820 offset = svm_msrpm_offset(direct_access_msrs[i].index);
821 BUG_ON(offset == MSR_INVALID);
822
823 add_msr_offset(offset);
824 }
825}
826
827static void svm_enable_lbrv(struct vcpu_svm *svm)
828{
829 u32 *msrpm = svm->msrpm;
830
831 svm->vmcb->control.lbr_ctl = 1;
832 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
833 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
834 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
835 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
836}
837
838static void svm_disable_lbrv(struct vcpu_svm *svm)
839{
840 u32 *msrpm = svm->msrpm;
841
842 svm->vmcb->control.lbr_ctl = 0;
843 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
844 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
845 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
846 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
847}
848
849static __init int svm_hardware_setup(void)
850{
851 int cpu;
852 struct page *iopm_pages;
853 void *iopm_va;
854 int r;
855
856 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
857
858 if (!iopm_pages)
859 return -ENOMEM;
860
861 iopm_va = page_address(iopm_pages);
862 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
863 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
864
865 init_msrpm_offsets();
866
867 if (boot_cpu_has(X86_FEATURE_NX))
868 kvm_enable_efer_bits(EFER_NX);
869
870 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
871 kvm_enable_efer_bits(EFER_FFXSR);
872
873 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
874 u64 max;
875
876 kvm_has_tsc_control = true;
877
878 /*
879 * Make sure the user can only configure tsc_khz values that
880 * fit into a signed integer.
881 * A min value is not calculated needed because it will always
882 * be 1 on all machines and a value of 0 is used to disable
883 * tsc-scaling for the vcpu.
884 */
885 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
886
887 kvm_max_guest_tsc_khz = max;
888 }
889
890 if (nested) {
891 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
892 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
893 }
894
895 for_each_possible_cpu(cpu) {
896 r = svm_cpu_init(cpu);
897 if (r)
898 goto err;
899 }
900
901 if (!boot_cpu_has(X86_FEATURE_NPT))
902 npt_enabled = false;
903
904 if (npt_enabled && !npt) {
905 printk(KERN_INFO "kvm: Nested Paging disabled\n");
906 npt_enabled = false;
907 }
908
909 if (npt_enabled) {
910 printk(KERN_INFO "kvm: Nested Paging enabled\n");
911 kvm_enable_tdp();
912 } else
913 kvm_disable_tdp();
914
915 return 0;
916
917err:
918 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
919 iopm_base = 0;
920 return r;
921}
922
923static __exit void svm_hardware_unsetup(void)
924{
925 int cpu;
926
927 for_each_possible_cpu(cpu)
928 svm_cpu_uninit(cpu);
929
930 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
931 iopm_base = 0;
932}
933
934static void init_seg(struct vmcb_seg *seg)
935{
936 seg->selector = 0;
937 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
938 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
939 seg->limit = 0xffff;
940 seg->base = 0;
941}
942
943static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
944{
945 seg->selector = 0;
946 seg->attrib = SVM_SELECTOR_P_MASK | type;
947 seg->limit = 0xffff;
948 seg->base = 0;
949}
950
951static u64 __scale_tsc(u64 ratio, u64 tsc)
952{
953 u64 mult, frac, _tsc;
954
955 mult = ratio >> 32;
956 frac = ratio & ((1ULL << 32) - 1);
957
958 _tsc = tsc;
959 _tsc *= mult;
960 _tsc += (tsc >> 32) * frac;
961 _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
962
963 return _tsc;
964}
965
966static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
967{
968 struct vcpu_svm *svm = to_svm(vcpu);
969 u64 _tsc = tsc;
970
971 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
972 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
973
974 return _tsc;
975}
976
977static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
978{
979 struct vcpu_svm *svm = to_svm(vcpu);
980 u64 ratio;
981 u64 khz;
982
983 /* Guest TSC same frequency as host TSC? */
984 if (!scale) {
985 svm->tsc_ratio = TSC_RATIO_DEFAULT;
986 return;
987 }
988
989 /* TSC scaling supported? */
990 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
991 if (user_tsc_khz > tsc_khz) {
992 vcpu->arch.tsc_catchup = 1;
993 vcpu->arch.tsc_always_catchup = 1;
994 } else
995 WARN(1, "user requested TSC rate below hardware speed\n");
996 return;
997 }
998
999 khz = user_tsc_khz;
1000
1001 /* TSC scaling required - calculate ratio */
1002 ratio = khz << 32;
1003 do_div(ratio, tsc_khz);
1004
1005 if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
1006 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
1007 user_tsc_khz);
1008 return;
1009 }
1010 svm->tsc_ratio = ratio;
1011}
1012
1013static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu)
1014{
1015 struct vcpu_svm *svm = to_svm(vcpu);
1016
1017 return svm->vmcb->control.tsc_offset;
1018}
1019
1020static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1021{
1022 struct vcpu_svm *svm = to_svm(vcpu);
1023 u64 g_tsc_offset = 0;
1024
1025 if (is_guest_mode(vcpu)) {
1026 g_tsc_offset = svm->vmcb->control.tsc_offset -
1027 svm->nested.hsave->control.tsc_offset;
1028 svm->nested.hsave->control.tsc_offset = offset;
1029 }
1030
1031 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1032
1033 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1034}
1035
1036static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1037{
1038 struct vcpu_svm *svm = to_svm(vcpu);
1039
1040 WARN_ON(adjustment < 0);
1041 if (host)
1042 adjustment = svm_scale_tsc(vcpu, adjustment);
1043
1044 svm->vmcb->control.tsc_offset += adjustment;
1045 if (is_guest_mode(vcpu))
1046 svm->nested.hsave->control.tsc_offset += adjustment;
1047 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1048}
1049
1050static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1051{
1052 u64 tsc;
1053
1054 tsc = svm_scale_tsc(vcpu, native_read_tsc());
1055
1056 return target_tsc - tsc;
1057}
1058
1059static void init_vmcb(struct vcpu_svm *svm)
1060{
1061 struct vmcb_control_area *control = &svm->vmcb->control;
1062 struct vmcb_save_area *save = &svm->vmcb->save;
1063
1064 svm->vcpu.fpu_active = 1;
1065 svm->vcpu.arch.hflags = 0;
1066
1067 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1068 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1069 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1070 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1071 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1072 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1073 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1074
1075 set_dr_intercept(svm, INTERCEPT_DR0_READ);
1076 set_dr_intercept(svm, INTERCEPT_DR1_READ);
1077 set_dr_intercept(svm, INTERCEPT_DR2_READ);
1078 set_dr_intercept(svm, INTERCEPT_DR3_READ);
1079 set_dr_intercept(svm, INTERCEPT_DR4_READ);
1080 set_dr_intercept(svm, INTERCEPT_DR5_READ);
1081 set_dr_intercept(svm, INTERCEPT_DR6_READ);
1082 set_dr_intercept(svm, INTERCEPT_DR7_READ);
1083
1084 set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
1085 set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
1086 set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
1087 set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
1088 set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
1089 set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
1090 set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
1091 set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
1092
1093 set_exception_intercept(svm, PF_VECTOR);
1094 set_exception_intercept(svm, UD_VECTOR);
1095 set_exception_intercept(svm, MC_VECTOR);
1096
1097 set_intercept(svm, INTERCEPT_INTR);
1098 set_intercept(svm, INTERCEPT_NMI);
1099 set_intercept(svm, INTERCEPT_SMI);
1100 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1101 set_intercept(svm, INTERCEPT_RDPMC);
1102 set_intercept(svm, INTERCEPT_CPUID);
1103 set_intercept(svm, INTERCEPT_INVD);
1104 set_intercept(svm, INTERCEPT_HLT);
1105 set_intercept(svm, INTERCEPT_INVLPG);
1106 set_intercept(svm, INTERCEPT_INVLPGA);
1107 set_intercept(svm, INTERCEPT_IOIO_PROT);
1108 set_intercept(svm, INTERCEPT_MSR_PROT);
1109 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1110 set_intercept(svm, INTERCEPT_SHUTDOWN);
1111 set_intercept(svm, INTERCEPT_VMRUN);
1112 set_intercept(svm, INTERCEPT_VMMCALL);
1113 set_intercept(svm, INTERCEPT_VMLOAD);
1114 set_intercept(svm, INTERCEPT_VMSAVE);
1115 set_intercept(svm, INTERCEPT_STGI);
1116 set_intercept(svm, INTERCEPT_CLGI);
1117 set_intercept(svm, INTERCEPT_SKINIT);
1118 set_intercept(svm, INTERCEPT_WBINVD);
1119 set_intercept(svm, INTERCEPT_MONITOR);
1120 set_intercept(svm, INTERCEPT_MWAIT);
1121 set_intercept(svm, INTERCEPT_XSETBV);
1122
1123 control->iopm_base_pa = iopm_base;
1124 control->msrpm_base_pa = __pa(svm->msrpm);
1125 control->int_ctl = V_INTR_MASKING_MASK;
1126
1127 init_seg(&save->es);
1128 init_seg(&save->ss);
1129 init_seg(&save->ds);
1130 init_seg(&save->fs);
1131 init_seg(&save->gs);
1132
1133 save->cs.selector = 0xf000;
1134 /* Executable/Readable Code Segment */
1135 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1136 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1137 save->cs.limit = 0xffff;
1138 /*
1139 * cs.base should really be 0xffff0000, but vmx can't handle that, so
1140 * be consistent with it.
1141 *
1142 * Replace when we have real mode working for vmx.
1143 */
1144 save->cs.base = 0xf0000;
1145
1146 save->gdtr.limit = 0xffff;
1147 save->idtr.limit = 0xffff;
1148
1149 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1150 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1151
1152 svm_set_efer(&svm->vcpu, 0);
1153 save->dr6 = 0xffff0ff0;
1154 kvm_set_rflags(&svm->vcpu, 2);
1155 save->rip = 0x0000fff0;
1156 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1157
1158 /*
1159 * This is the guest-visible cr0 value.
1160 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1161 */
1162 svm->vcpu.arch.cr0 = 0;
1163 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1164
1165 save->cr4 = X86_CR4_PAE;
1166 /* rdx = ?? */
1167
1168 if (npt_enabled) {
1169 /* Setup VMCB for Nested Paging */
1170 control->nested_ctl = 1;
1171 clr_intercept(svm, INTERCEPT_INVLPG);
1172 clr_exception_intercept(svm, PF_VECTOR);
1173 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1174 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1175 save->g_pat = 0x0007040600070406ULL;
1176 save->cr3 = 0;
1177 save->cr4 = 0;
1178 }
1179 svm->asid_generation = 0;
1180
1181 svm->nested.vmcb = 0;
1182 svm->vcpu.arch.hflags = 0;
1183
1184 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1185 control->pause_filter_count = 3000;
1186 set_intercept(svm, INTERCEPT_PAUSE);
1187 }
1188
1189 mark_all_dirty(svm->vmcb);
1190
1191 enable_gif(svm);
1192}
1193
1194static void svm_vcpu_reset(struct kvm_vcpu *vcpu)
1195{
1196 struct vcpu_svm *svm = to_svm(vcpu);
1197 u32 dummy;
1198 u32 eax = 1;
1199
1200 init_vmcb(svm);
1201
1202 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1203 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1204}
1205
1206static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1207{
1208 struct vcpu_svm *svm;
1209 struct page *page;
1210 struct page *msrpm_pages;
1211 struct page *hsave_page;
1212 struct page *nested_msrpm_pages;
1213 int err;
1214
1215 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1216 if (!svm) {
1217 err = -ENOMEM;
1218 goto out;
1219 }
1220
1221 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1222
1223 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1224 if (err)
1225 goto free_svm;
1226
1227 err = -ENOMEM;
1228 page = alloc_page(GFP_KERNEL);
1229 if (!page)
1230 goto uninit;
1231
1232 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1233 if (!msrpm_pages)
1234 goto free_page1;
1235
1236 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1237 if (!nested_msrpm_pages)
1238 goto free_page2;
1239
1240 hsave_page = alloc_page(GFP_KERNEL);
1241 if (!hsave_page)
1242 goto free_page3;
1243
1244 svm->nested.hsave = page_address(hsave_page);
1245
1246 svm->msrpm = page_address(msrpm_pages);
1247 svm_vcpu_init_msrpm(svm->msrpm);
1248
1249 svm->nested.msrpm = page_address(nested_msrpm_pages);
1250 svm_vcpu_init_msrpm(svm->nested.msrpm);
1251
1252 svm->vmcb = page_address(page);
1253 clear_page(svm->vmcb);
1254 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1255 svm->asid_generation = 0;
1256 init_vmcb(svm);
1257
1258 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1259 if (kvm_vcpu_is_bsp(&svm->vcpu))
1260 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1261
1262 svm_init_osvw(&svm->vcpu);
1263
1264 return &svm->vcpu;
1265
1266free_page3:
1267 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1268free_page2:
1269 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1270free_page1:
1271 __free_page(page);
1272uninit:
1273 kvm_vcpu_uninit(&svm->vcpu);
1274free_svm:
1275 kmem_cache_free(kvm_vcpu_cache, svm);
1276out:
1277 return ERR_PTR(err);
1278}
1279
1280static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1281{
1282 struct vcpu_svm *svm = to_svm(vcpu);
1283
1284 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1285 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1286 __free_page(virt_to_page(svm->nested.hsave));
1287 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1288 kvm_vcpu_uninit(vcpu);
1289 kmem_cache_free(kvm_vcpu_cache, svm);
1290}
1291
1292static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1293{
1294 struct vcpu_svm *svm = to_svm(vcpu);
1295 int i;
1296
1297 if (unlikely(cpu != vcpu->cpu)) {
1298 svm->asid_generation = 0;
1299 mark_all_dirty(svm->vmcb);
1300 }
1301
1302#ifdef CONFIG_X86_64
1303 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1304#endif
1305 savesegment(fs, svm->host.fs);
1306 savesegment(gs, svm->host.gs);
1307 svm->host.ldt = kvm_read_ldt();
1308
1309 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1310 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1311
1312 if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1313 svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) {
1314 __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio;
1315 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1316 }
1317}
1318
1319static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1320{
1321 struct vcpu_svm *svm = to_svm(vcpu);
1322 int i;
1323
1324 ++vcpu->stat.host_state_reload;
1325 kvm_load_ldt(svm->host.ldt);
1326#ifdef CONFIG_X86_64
1327 loadsegment(fs, svm->host.fs);
1328 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1329 load_gs_index(svm->host.gs);
1330#else
1331#ifdef CONFIG_X86_32_LAZY_GS
1332 loadsegment(gs, svm->host.gs);
1333#endif
1334#endif
1335 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1336 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1337}
1338
1339static void svm_update_cpl(struct kvm_vcpu *vcpu)
1340{
1341 struct vcpu_svm *svm = to_svm(vcpu);
1342 int cpl;
1343
1344 if (!is_protmode(vcpu))
1345 cpl = 0;
1346 else if (svm->vmcb->save.rflags & X86_EFLAGS_VM)
1347 cpl = 3;
1348 else
1349 cpl = svm->vmcb->save.cs.selector & 0x3;
1350
1351 svm->vmcb->save.cpl = cpl;
1352}
1353
1354static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1355{
1356 return to_svm(vcpu)->vmcb->save.rflags;
1357}
1358
1359static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1360{
1361 unsigned long old_rflags = to_svm(vcpu)->vmcb->save.rflags;
1362
1363 to_svm(vcpu)->vmcb->save.rflags = rflags;
1364 if ((old_rflags ^ rflags) & X86_EFLAGS_VM)
1365 svm_update_cpl(vcpu);
1366}
1367
1368static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1369{
1370 switch (reg) {
1371 case VCPU_EXREG_PDPTR:
1372 BUG_ON(!npt_enabled);
1373 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1374 break;
1375 default:
1376 BUG();
1377 }
1378}
1379
1380static void svm_set_vintr(struct vcpu_svm *svm)
1381{
1382 set_intercept(svm, INTERCEPT_VINTR);
1383}
1384
1385static void svm_clear_vintr(struct vcpu_svm *svm)
1386{
1387 clr_intercept(svm, INTERCEPT_VINTR);
1388}
1389
1390static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1391{
1392 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1393
1394 switch (seg) {
1395 case VCPU_SREG_CS: return &save->cs;
1396 case VCPU_SREG_DS: return &save->ds;
1397 case VCPU_SREG_ES: return &save->es;
1398 case VCPU_SREG_FS: return &save->fs;
1399 case VCPU_SREG_GS: return &save->gs;
1400 case VCPU_SREG_SS: return &save->ss;
1401 case VCPU_SREG_TR: return &save->tr;
1402 case VCPU_SREG_LDTR: return &save->ldtr;
1403 }
1404 BUG();
1405 return NULL;
1406}
1407
1408static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1409{
1410 struct vmcb_seg *s = svm_seg(vcpu, seg);
1411
1412 return s->base;
1413}
1414
1415static void svm_get_segment(struct kvm_vcpu *vcpu,
1416 struct kvm_segment *var, int seg)
1417{
1418 struct vmcb_seg *s = svm_seg(vcpu, seg);
1419
1420 var->base = s->base;
1421 var->limit = s->limit;
1422 var->selector = s->selector;
1423 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1424 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1425 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1426 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1427 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1428 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1429 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1430 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1431
1432 /*
1433 * AMD's VMCB does not have an explicit unusable field, so emulate it
1434 * for cross vendor migration purposes by "not present"
1435 */
1436 var->unusable = !var->present || (var->type == 0);
1437
1438 switch (seg) {
1439 case VCPU_SREG_CS:
1440 /*
1441 * SVM always stores 0 for the 'G' bit in the CS selector in
1442 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1443 * Intel's VMENTRY has a check on the 'G' bit.
1444 */
1445 var->g = s->limit > 0xfffff;
1446 break;
1447 case VCPU_SREG_TR:
1448 /*
1449 * Work around a bug where the busy flag in the tr selector
1450 * isn't exposed
1451 */
1452 var->type |= 0x2;
1453 break;
1454 case VCPU_SREG_DS:
1455 case VCPU_SREG_ES:
1456 case VCPU_SREG_FS:
1457 case VCPU_SREG_GS:
1458 /*
1459 * The accessed bit must always be set in the segment
1460 * descriptor cache, although it can be cleared in the
1461 * descriptor, the cached bit always remains at 1. Since
1462 * Intel has a check on this, set it here to support
1463 * cross-vendor migration.
1464 */
1465 if (!var->unusable)
1466 var->type |= 0x1;
1467 break;
1468 case VCPU_SREG_SS:
1469 /*
1470 * On AMD CPUs sometimes the DB bit in the segment
1471 * descriptor is left as 1, although the whole segment has
1472 * been made unusable. Clear it here to pass an Intel VMX
1473 * entry check when cross vendor migrating.
1474 */
1475 if (var->unusable)
1476 var->db = 0;
1477 break;
1478 }
1479}
1480
1481static int svm_get_cpl(struct kvm_vcpu *vcpu)
1482{
1483 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1484
1485 return save->cpl;
1486}
1487
1488static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1489{
1490 struct vcpu_svm *svm = to_svm(vcpu);
1491
1492 dt->size = svm->vmcb->save.idtr.limit;
1493 dt->address = svm->vmcb->save.idtr.base;
1494}
1495
1496static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1497{
1498 struct vcpu_svm *svm = to_svm(vcpu);
1499
1500 svm->vmcb->save.idtr.limit = dt->size;
1501 svm->vmcb->save.idtr.base = dt->address ;
1502 mark_dirty(svm->vmcb, VMCB_DT);
1503}
1504
1505static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1506{
1507 struct vcpu_svm *svm = to_svm(vcpu);
1508
1509 dt->size = svm->vmcb->save.gdtr.limit;
1510 dt->address = svm->vmcb->save.gdtr.base;
1511}
1512
1513static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1514{
1515 struct vcpu_svm *svm = to_svm(vcpu);
1516
1517 svm->vmcb->save.gdtr.limit = dt->size;
1518 svm->vmcb->save.gdtr.base = dt->address ;
1519 mark_dirty(svm->vmcb, VMCB_DT);
1520}
1521
1522static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1523{
1524}
1525
1526static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1527{
1528}
1529
1530static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1531{
1532}
1533
1534static void update_cr0_intercept(struct vcpu_svm *svm)
1535{
1536 ulong gcr0 = svm->vcpu.arch.cr0;
1537 u64 *hcr0 = &svm->vmcb->save.cr0;
1538
1539 if (!svm->vcpu.fpu_active)
1540 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1541 else
1542 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1543 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1544
1545 mark_dirty(svm->vmcb, VMCB_CR);
1546
1547 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1548 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1549 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1550 } else {
1551 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1552 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1553 }
1554}
1555
1556static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1557{
1558 struct vcpu_svm *svm = to_svm(vcpu);
1559
1560#ifdef CONFIG_X86_64
1561 if (vcpu->arch.efer & EFER_LME) {
1562 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1563 vcpu->arch.efer |= EFER_LMA;
1564 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1565 }
1566
1567 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1568 vcpu->arch.efer &= ~EFER_LMA;
1569 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1570 }
1571 }
1572#endif
1573 vcpu->arch.cr0 = cr0;
1574
1575 if (!npt_enabled)
1576 cr0 |= X86_CR0_PG | X86_CR0_WP;
1577
1578 if (!vcpu->fpu_active)
1579 cr0 |= X86_CR0_TS;
1580 /*
1581 * re-enable caching here because the QEMU bios
1582 * does not do it - this results in some delay at
1583 * reboot
1584 */
1585 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1586 svm->vmcb->save.cr0 = cr0;
1587 mark_dirty(svm->vmcb, VMCB_CR);
1588 update_cr0_intercept(svm);
1589}
1590
1591static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1592{
1593 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1594 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1595
1596 if (cr4 & X86_CR4_VMXE)
1597 return 1;
1598
1599 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1600 svm_flush_tlb(vcpu);
1601
1602 vcpu->arch.cr4 = cr4;
1603 if (!npt_enabled)
1604 cr4 |= X86_CR4_PAE;
1605 cr4 |= host_cr4_mce;
1606 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1607 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1608 return 0;
1609}
1610
1611static void svm_set_segment(struct kvm_vcpu *vcpu,
1612 struct kvm_segment *var, int seg)
1613{
1614 struct vcpu_svm *svm = to_svm(vcpu);
1615 struct vmcb_seg *s = svm_seg(vcpu, seg);
1616
1617 s->base = var->base;
1618 s->limit = var->limit;
1619 s->selector = var->selector;
1620 if (var->unusable)
1621 s->attrib = 0;
1622 else {
1623 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1624 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1625 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1626 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1627 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1628 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1629 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1630 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1631 }
1632 if (seg == VCPU_SREG_CS)
1633 svm_update_cpl(vcpu);
1634
1635 mark_dirty(svm->vmcb, VMCB_SEG);
1636}
1637
1638static void update_db_bp_intercept(struct kvm_vcpu *vcpu)
1639{
1640 struct vcpu_svm *svm = to_svm(vcpu);
1641
1642 clr_exception_intercept(svm, DB_VECTOR);
1643 clr_exception_intercept(svm, BP_VECTOR);
1644
1645 if (svm->nmi_singlestep)
1646 set_exception_intercept(svm, DB_VECTOR);
1647
1648 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1649 if (vcpu->guest_debug &
1650 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1651 set_exception_intercept(svm, DB_VECTOR);
1652 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1653 set_exception_intercept(svm, BP_VECTOR);
1654 } else
1655 vcpu->guest_debug = 0;
1656}
1657
1658static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1659{
1660 if (sd->next_asid > sd->max_asid) {
1661 ++sd->asid_generation;
1662 sd->next_asid = 1;
1663 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1664 }
1665
1666 svm->asid_generation = sd->asid_generation;
1667 svm->vmcb->control.asid = sd->next_asid++;
1668
1669 mark_dirty(svm->vmcb, VMCB_ASID);
1670}
1671
1672static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1673{
1674 struct vcpu_svm *svm = to_svm(vcpu);
1675
1676 svm->vmcb->save.dr7 = value;
1677 mark_dirty(svm->vmcb, VMCB_DR);
1678}
1679
1680static int pf_interception(struct vcpu_svm *svm)
1681{
1682 u64 fault_address = svm->vmcb->control.exit_info_2;
1683 u32 error_code;
1684 int r = 1;
1685
1686 switch (svm->apf_reason) {
1687 default:
1688 error_code = svm->vmcb->control.exit_info_1;
1689
1690 trace_kvm_page_fault(fault_address, error_code);
1691 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1692 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1693 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1694 svm->vmcb->control.insn_bytes,
1695 svm->vmcb->control.insn_len);
1696 break;
1697 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1698 svm->apf_reason = 0;
1699 local_irq_disable();
1700 kvm_async_pf_task_wait(fault_address);
1701 local_irq_enable();
1702 break;
1703 case KVM_PV_REASON_PAGE_READY:
1704 svm->apf_reason = 0;
1705 local_irq_disable();
1706 kvm_async_pf_task_wake(fault_address);
1707 local_irq_enable();
1708 break;
1709 }
1710 return r;
1711}
1712
1713static int db_interception(struct vcpu_svm *svm)
1714{
1715 struct kvm_run *kvm_run = svm->vcpu.run;
1716
1717 if (!(svm->vcpu.guest_debug &
1718 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1719 !svm->nmi_singlestep) {
1720 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1721 return 1;
1722 }
1723
1724 if (svm->nmi_singlestep) {
1725 svm->nmi_singlestep = false;
1726 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1727 svm->vmcb->save.rflags &=
1728 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1729 update_db_bp_intercept(&svm->vcpu);
1730 }
1731
1732 if (svm->vcpu.guest_debug &
1733 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1734 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1735 kvm_run->debug.arch.pc =
1736 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1737 kvm_run->debug.arch.exception = DB_VECTOR;
1738 return 0;
1739 }
1740
1741 return 1;
1742}
1743
1744static int bp_interception(struct vcpu_svm *svm)
1745{
1746 struct kvm_run *kvm_run = svm->vcpu.run;
1747
1748 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1749 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1750 kvm_run->debug.arch.exception = BP_VECTOR;
1751 return 0;
1752}
1753
1754static int ud_interception(struct vcpu_svm *svm)
1755{
1756 int er;
1757
1758 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1759 if (er != EMULATE_DONE)
1760 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1761 return 1;
1762}
1763
1764static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1765{
1766 struct vcpu_svm *svm = to_svm(vcpu);
1767
1768 clr_exception_intercept(svm, NM_VECTOR);
1769
1770 svm->vcpu.fpu_active = 1;
1771 update_cr0_intercept(svm);
1772}
1773
1774static int nm_interception(struct vcpu_svm *svm)
1775{
1776 svm_fpu_activate(&svm->vcpu);
1777 return 1;
1778}
1779
1780static bool is_erratum_383(void)
1781{
1782 int err, i;
1783 u64 value;
1784
1785 if (!erratum_383_found)
1786 return false;
1787
1788 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1789 if (err)
1790 return false;
1791
1792 /* Bit 62 may or may not be set for this mce */
1793 value &= ~(1ULL << 62);
1794
1795 if (value != 0xb600000000010015ULL)
1796 return false;
1797
1798 /* Clear MCi_STATUS registers */
1799 for (i = 0; i < 6; ++i)
1800 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1801
1802 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1803 if (!err) {
1804 u32 low, high;
1805
1806 value &= ~(1ULL << 2);
1807 low = lower_32_bits(value);
1808 high = upper_32_bits(value);
1809
1810 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1811 }
1812
1813 /* Flush tlb to evict multi-match entries */
1814 __flush_tlb_all();
1815
1816 return true;
1817}
1818
1819static void svm_handle_mce(struct vcpu_svm *svm)
1820{
1821 if (is_erratum_383()) {
1822 /*
1823 * Erratum 383 triggered. Guest state is corrupt so kill the
1824 * guest.
1825 */
1826 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1827
1828 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1829
1830 return;
1831 }
1832
1833 /*
1834 * On an #MC intercept the MCE handler is not called automatically in
1835 * the host. So do it by hand here.
1836 */
1837 asm volatile (
1838 "int $0x12\n");
1839 /* not sure if we ever come back to this point */
1840
1841 return;
1842}
1843
1844static int mc_interception(struct vcpu_svm *svm)
1845{
1846 return 1;
1847}
1848
1849static int shutdown_interception(struct vcpu_svm *svm)
1850{
1851 struct kvm_run *kvm_run = svm->vcpu.run;
1852
1853 /*
1854 * VMCB is undefined after a SHUTDOWN intercept
1855 * so reinitialize it.
1856 */
1857 clear_page(svm->vmcb);
1858 init_vmcb(svm);
1859
1860 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1861 return 0;
1862}
1863
1864static int io_interception(struct vcpu_svm *svm)
1865{
1866 struct kvm_vcpu *vcpu = &svm->vcpu;
1867 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1868 int size, in, string;
1869 unsigned port;
1870
1871 ++svm->vcpu.stat.io_exits;
1872 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1873 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1874 if (string || in)
1875 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1876
1877 port = io_info >> 16;
1878 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1879 svm->next_rip = svm->vmcb->control.exit_info_2;
1880 skip_emulated_instruction(&svm->vcpu);
1881
1882 return kvm_fast_pio_out(vcpu, size, port);
1883}
1884
1885static int nmi_interception(struct vcpu_svm *svm)
1886{
1887 return 1;
1888}
1889
1890static int intr_interception(struct vcpu_svm *svm)
1891{
1892 ++svm->vcpu.stat.irq_exits;
1893 return 1;
1894}
1895
1896static int nop_on_interception(struct vcpu_svm *svm)
1897{
1898 return 1;
1899}
1900
1901static int halt_interception(struct vcpu_svm *svm)
1902{
1903 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1904 skip_emulated_instruction(&svm->vcpu);
1905 return kvm_emulate_halt(&svm->vcpu);
1906}
1907
1908static int vmmcall_interception(struct vcpu_svm *svm)
1909{
1910 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1911 skip_emulated_instruction(&svm->vcpu);
1912 kvm_emulate_hypercall(&svm->vcpu);
1913 return 1;
1914}
1915
1916static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1917{
1918 struct vcpu_svm *svm = to_svm(vcpu);
1919
1920 return svm->nested.nested_cr3;
1921}
1922
1923static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
1924{
1925 struct vcpu_svm *svm = to_svm(vcpu);
1926 u64 cr3 = svm->nested.nested_cr3;
1927 u64 pdpte;
1928 int ret;
1929
1930 ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte,
1931 offset_in_page(cr3) + index * 8, 8);
1932 if (ret)
1933 return 0;
1934 return pdpte;
1935}
1936
1937static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1938 unsigned long root)
1939{
1940 struct vcpu_svm *svm = to_svm(vcpu);
1941
1942 svm->vmcb->control.nested_cr3 = root;
1943 mark_dirty(svm->vmcb, VMCB_NPT);
1944 svm_flush_tlb(vcpu);
1945}
1946
1947static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1948 struct x86_exception *fault)
1949{
1950 struct vcpu_svm *svm = to_svm(vcpu);
1951
1952 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1953 svm->vmcb->control.exit_code_hi = 0;
1954 svm->vmcb->control.exit_info_1 = fault->error_code;
1955 svm->vmcb->control.exit_info_2 = fault->address;
1956
1957 nested_svm_vmexit(svm);
1958}
1959
1960static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1961{
1962 int r;
1963
1964 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1965
1966 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1967 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1968 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
1969 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1970 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1971 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1972
1973 return r;
1974}
1975
1976static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1977{
1978 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1979}
1980
1981static int nested_svm_check_permissions(struct vcpu_svm *svm)
1982{
1983 if (!(svm->vcpu.arch.efer & EFER_SVME)
1984 || !is_paging(&svm->vcpu)) {
1985 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1986 return 1;
1987 }
1988
1989 if (svm->vmcb->save.cpl) {
1990 kvm_inject_gp(&svm->vcpu, 0);
1991 return 1;
1992 }
1993
1994 return 0;
1995}
1996
1997static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1998 bool has_error_code, u32 error_code)
1999{
2000 int vmexit;
2001
2002 if (!is_guest_mode(&svm->vcpu))
2003 return 0;
2004
2005 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2006 svm->vmcb->control.exit_code_hi = 0;
2007 svm->vmcb->control.exit_info_1 = error_code;
2008 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2009
2010 vmexit = nested_svm_intercept(svm);
2011 if (vmexit == NESTED_EXIT_DONE)
2012 svm->nested.exit_required = true;
2013
2014 return vmexit;
2015}
2016
2017/* This function returns true if it is save to enable the irq window */
2018static inline bool nested_svm_intr(struct vcpu_svm *svm)
2019{
2020 if (!is_guest_mode(&svm->vcpu))
2021 return true;
2022
2023 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2024 return true;
2025
2026 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2027 return false;
2028
2029 /*
2030 * if vmexit was already requested (by intercepted exception
2031 * for instance) do not overwrite it with "external interrupt"
2032 * vmexit.
2033 */
2034 if (svm->nested.exit_required)
2035 return false;
2036
2037 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2038 svm->vmcb->control.exit_info_1 = 0;
2039 svm->vmcb->control.exit_info_2 = 0;
2040
2041 if (svm->nested.intercept & 1ULL) {
2042 /*
2043 * The #vmexit can't be emulated here directly because this
2044 * code path runs with irqs and preemption disabled. A
2045 * #vmexit emulation might sleep. Only signal request for
2046 * the #vmexit here.
2047 */
2048 svm->nested.exit_required = true;
2049 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2050 return false;
2051 }
2052
2053 return true;
2054}
2055
2056/* This function returns true if it is save to enable the nmi window */
2057static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2058{
2059 if (!is_guest_mode(&svm->vcpu))
2060 return true;
2061
2062 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2063 return true;
2064
2065 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2066 svm->nested.exit_required = true;
2067
2068 return false;
2069}
2070
2071static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2072{
2073 struct page *page;
2074
2075 might_sleep();
2076
2077 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
2078 if (is_error_page(page))
2079 goto error;
2080
2081 *_page = page;
2082
2083 return kmap(page);
2084
2085error:
2086 kvm_inject_gp(&svm->vcpu, 0);
2087
2088 return NULL;
2089}
2090
2091static void nested_svm_unmap(struct page *page)
2092{
2093 kunmap(page);
2094 kvm_release_page_dirty(page);
2095}
2096
2097static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2098{
2099 unsigned port;
2100 u8 val, bit;
2101 u64 gpa;
2102
2103 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2104 return NESTED_EXIT_HOST;
2105
2106 port = svm->vmcb->control.exit_info_1 >> 16;
2107 gpa = svm->nested.vmcb_iopm + (port / 8);
2108 bit = port % 8;
2109 val = 0;
2110
2111 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
2112 val &= (1 << bit);
2113
2114 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2115}
2116
2117static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2118{
2119 u32 offset, msr, value;
2120 int write, mask;
2121
2122 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2123 return NESTED_EXIT_HOST;
2124
2125 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2126 offset = svm_msrpm_offset(msr);
2127 write = svm->vmcb->control.exit_info_1 & 1;
2128 mask = 1 << ((2 * (msr & 0xf)) + write);
2129
2130 if (offset == MSR_INVALID)
2131 return NESTED_EXIT_DONE;
2132
2133 /* Offset is in 32 bit units but need in 8 bit units */
2134 offset *= 4;
2135
2136 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
2137 return NESTED_EXIT_DONE;
2138
2139 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2140}
2141
2142static int nested_svm_exit_special(struct vcpu_svm *svm)
2143{
2144 u32 exit_code = svm->vmcb->control.exit_code;
2145
2146 switch (exit_code) {
2147 case SVM_EXIT_INTR:
2148 case SVM_EXIT_NMI:
2149 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2150 return NESTED_EXIT_HOST;
2151 case SVM_EXIT_NPF:
2152 /* For now we are always handling NPFs when using them */
2153 if (npt_enabled)
2154 return NESTED_EXIT_HOST;
2155 break;
2156 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2157 /* When we're shadowing, trap PFs, but not async PF */
2158 if (!npt_enabled && svm->apf_reason == 0)
2159 return NESTED_EXIT_HOST;
2160 break;
2161 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2162 nm_interception(svm);
2163 break;
2164 default:
2165 break;
2166 }
2167
2168 return NESTED_EXIT_CONTINUE;
2169}
2170
2171/*
2172 * If this function returns true, this #vmexit was already handled
2173 */
2174static int nested_svm_intercept(struct vcpu_svm *svm)
2175{
2176 u32 exit_code = svm->vmcb->control.exit_code;
2177 int vmexit = NESTED_EXIT_HOST;
2178
2179 switch (exit_code) {
2180 case SVM_EXIT_MSR:
2181 vmexit = nested_svm_exit_handled_msr(svm);
2182 break;
2183 case SVM_EXIT_IOIO:
2184 vmexit = nested_svm_intercept_ioio(svm);
2185 break;
2186 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2187 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2188 if (svm->nested.intercept_cr & bit)
2189 vmexit = NESTED_EXIT_DONE;
2190 break;
2191 }
2192 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2193 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2194 if (svm->nested.intercept_dr & bit)
2195 vmexit = NESTED_EXIT_DONE;
2196 break;
2197 }
2198 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2199 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2200 if (svm->nested.intercept_exceptions & excp_bits)
2201 vmexit = NESTED_EXIT_DONE;
2202 /* async page fault always cause vmexit */
2203 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2204 svm->apf_reason != 0)
2205 vmexit = NESTED_EXIT_DONE;
2206 break;
2207 }
2208 case SVM_EXIT_ERR: {
2209 vmexit = NESTED_EXIT_DONE;
2210 break;
2211 }
2212 default: {
2213 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2214 if (svm->nested.intercept & exit_bits)
2215 vmexit = NESTED_EXIT_DONE;
2216 }
2217 }
2218
2219 return vmexit;
2220}
2221
2222static int nested_svm_exit_handled(struct vcpu_svm *svm)
2223{
2224 int vmexit;
2225
2226 vmexit = nested_svm_intercept(svm);
2227
2228 if (vmexit == NESTED_EXIT_DONE)
2229 nested_svm_vmexit(svm);
2230
2231 return vmexit;
2232}
2233
2234static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2235{
2236 struct vmcb_control_area *dst = &dst_vmcb->control;
2237 struct vmcb_control_area *from = &from_vmcb->control;
2238
2239 dst->intercept_cr = from->intercept_cr;
2240 dst->intercept_dr = from->intercept_dr;
2241 dst->intercept_exceptions = from->intercept_exceptions;
2242 dst->intercept = from->intercept;
2243 dst->iopm_base_pa = from->iopm_base_pa;
2244 dst->msrpm_base_pa = from->msrpm_base_pa;
2245 dst->tsc_offset = from->tsc_offset;
2246 dst->asid = from->asid;
2247 dst->tlb_ctl = from->tlb_ctl;
2248 dst->int_ctl = from->int_ctl;
2249 dst->int_vector = from->int_vector;
2250 dst->int_state = from->int_state;
2251 dst->exit_code = from->exit_code;
2252 dst->exit_code_hi = from->exit_code_hi;
2253 dst->exit_info_1 = from->exit_info_1;
2254 dst->exit_info_2 = from->exit_info_2;
2255 dst->exit_int_info = from->exit_int_info;
2256 dst->exit_int_info_err = from->exit_int_info_err;
2257 dst->nested_ctl = from->nested_ctl;
2258 dst->event_inj = from->event_inj;
2259 dst->event_inj_err = from->event_inj_err;
2260 dst->nested_cr3 = from->nested_cr3;
2261 dst->lbr_ctl = from->lbr_ctl;
2262}
2263
2264static int nested_svm_vmexit(struct vcpu_svm *svm)
2265{
2266 struct vmcb *nested_vmcb;
2267 struct vmcb *hsave = svm->nested.hsave;
2268 struct vmcb *vmcb = svm->vmcb;
2269 struct page *page;
2270
2271 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2272 vmcb->control.exit_info_1,
2273 vmcb->control.exit_info_2,
2274 vmcb->control.exit_int_info,
2275 vmcb->control.exit_int_info_err,
2276 KVM_ISA_SVM);
2277
2278 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2279 if (!nested_vmcb)
2280 return 1;
2281
2282 /* Exit Guest-Mode */
2283 leave_guest_mode(&svm->vcpu);
2284 svm->nested.vmcb = 0;
2285
2286 /* Give the current vmcb to the guest */
2287 disable_gif(svm);
2288
2289 nested_vmcb->save.es = vmcb->save.es;
2290 nested_vmcb->save.cs = vmcb->save.cs;
2291 nested_vmcb->save.ss = vmcb->save.ss;
2292 nested_vmcb->save.ds = vmcb->save.ds;
2293 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2294 nested_vmcb->save.idtr = vmcb->save.idtr;
2295 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2296 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2297 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2298 nested_vmcb->save.cr2 = vmcb->save.cr2;
2299 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2300 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2301 nested_vmcb->save.rip = vmcb->save.rip;
2302 nested_vmcb->save.rsp = vmcb->save.rsp;
2303 nested_vmcb->save.rax = vmcb->save.rax;
2304 nested_vmcb->save.dr7 = vmcb->save.dr7;
2305 nested_vmcb->save.dr6 = vmcb->save.dr6;
2306 nested_vmcb->save.cpl = vmcb->save.cpl;
2307
2308 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2309 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2310 nested_vmcb->control.int_state = vmcb->control.int_state;
2311 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2312 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2313 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2314 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2315 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2316 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2317 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2318
2319 /*
2320 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2321 * to make sure that we do not lose injected events. So check event_inj
2322 * here and copy it to exit_int_info if it is valid.
2323 * Exit_int_info and event_inj can't be both valid because the case
2324 * below only happens on a VMRUN instruction intercept which has
2325 * no valid exit_int_info set.
2326 */
2327 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2328 struct vmcb_control_area *nc = &nested_vmcb->control;
2329
2330 nc->exit_int_info = vmcb->control.event_inj;
2331 nc->exit_int_info_err = vmcb->control.event_inj_err;
2332 }
2333
2334 nested_vmcb->control.tlb_ctl = 0;
2335 nested_vmcb->control.event_inj = 0;
2336 nested_vmcb->control.event_inj_err = 0;
2337
2338 /* We always set V_INTR_MASKING and remember the old value in hflags */
2339 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2340 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2341
2342 /* Restore the original control entries */
2343 copy_vmcb_control_area(vmcb, hsave);
2344
2345 kvm_clear_exception_queue(&svm->vcpu);
2346 kvm_clear_interrupt_queue(&svm->vcpu);
2347
2348 svm->nested.nested_cr3 = 0;
2349
2350 /* Restore selected save entries */
2351 svm->vmcb->save.es = hsave->save.es;
2352 svm->vmcb->save.cs = hsave->save.cs;
2353 svm->vmcb->save.ss = hsave->save.ss;
2354 svm->vmcb->save.ds = hsave->save.ds;
2355 svm->vmcb->save.gdtr = hsave->save.gdtr;
2356 svm->vmcb->save.idtr = hsave->save.idtr;
2357 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2358 svm_set_efer(&svm->vcpu, hsave->save.efer);
2359 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2360 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2361 if (npt_enabled) {
2362 svm->vmcb->save.cr3 = hsave->save.cr3;
2363 svm->vcpu.arch.cr3 = hsave->save.cr3;
2364 } else {
2365 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2366 }
2367 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2368 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2369 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2370 svm->vmcb->save.dr7 = 0;
2371 svm->vmcb->save.cpl = 0;
2372 svm->vmcb->control.exit_int_info = 0;
2373
2374 mark_all_dirty(svm->vmcb);
2375
2376 nested_svm_unmap(page);
2377
2378 nested_svm_uninit_mmu_context(&svm->vcpu);
2379 kvm_mmu_reset_context(&svm->vcpu);
2380 kvm_mmu_load(&svm->vcpu);
2381
2382 return 0;
2383}
2384
2385static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2386{
2387 /*
2388 * This function merges the msr permission bitmaps of kvm and the
2389 * nested vmcb. It is optimized in that it only merges the parts where
2390 * the kvm msr permission bitmap may contain zero bits
2391 */
2392 int i;
2393
2394 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2395 return true;
2396
2397 for (i = 0; i < MSRPM_OFFSETS; i++) {
2398 u32 value, p;
2399 u64 offset;
2400
2401 if (msrpm_offsets[i] == 0xffffffff)
2402 break;
2403
2404 p = msrpm_offsets[i];
2405 offset = svm->nested.vmcb_msrpm + (p * 4);
2406
2407 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2408 return false;
2409
2410 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2411 }
2412
2413 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2414
2415 return true;
2416}
2417
2418static bool nested_vmcb_checks(struct vmcb *vmcb)
2419{
2420 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2421 return false;
2422
2423 if (vmcb->control.asid == 0)
2424 return false;
2425
2426 if (vmcb->control.nested_ctl && !npt_enabled)
2427 return false;
2428
2429 return true;
2430}
2431
2432static bool nested_svm_vmrun(struct vcpu_svm *svm)
2433{
2434 struct vmcb *nested_vmcb;
2435 struct vmcb *hsave = svm->nested.hsave;
2436 struct vmcb *vmcb = svm->vmcb;
2437 struct page *page;
2438 u64 vmcb_gpa;
2439
2440 vmcb_gpa = svm->vmcb->save.rax;
2441
2442 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2443 if (!nested_vmcb)
2444 return false;
2445
2446 if (!nested_vmcb_checks(nested_vmcb)) {
2447 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2448 nested_vmcb->control.exit_code_hi = 0;
2449 nested_vmcb->control.exit_info_1 = 0;
2450 nested_vmcb->control.exit_info_2 = 0;
2451
2452 nested_svm_unmap(page);
2453
2454 return false;
2455 }
2456
2457 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2458 nested_vmcb->save.rip,
2459 nested_vmcb->control.int_ctl,
2460 nested_vmcb->control.event_inj,
2461 nested_vmcb->control.nested_ctl);
2462
2463 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2464 nested_vmcb->control.intercept_cr >> 16,
2465 nested_vmcb->control.intercept_exceptions,
2466 nested_vmcb->control.intercept);
2467
2468 /* Clear internal status */
2469 kvm_clear_exception_queue(&svm->vcpu);
2470 kvm_clear_interrupt_queue(&svm->vcpu);
2471
2472 /*
2473 * Save the old vmcb, so we don't need to pick what we save, but can
2474 * restore everything when a VMEXIT occurs
2475 */
2476 hsave->save.es = vmcb->save.es;
2477 hsave->save.cs = vmcb->save.cs;
2478 hsave->save.ss = vmcb->save.ss;
2479 hsave->save.ds = vmcb->save.ds;
2480 hsave->save.gdtr = vmcb->save.gdtr;
2481 hsave->save.idtr = vmcb->save.idtr;
2482 hsave->save.efer = svm->vcpu.arch.efer;
2483 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2484 hsave->save.cr4 = svm->vcpu.arch.cr4;
2485 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2486 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2487 hsave->save.rsp = vmcb->save.rsp;
2488 hsave->save.rax = vmcb->save.rax;
2489 if (npt_enabled)
2490 hsave->save.cr3 = vmcb->save.cr3;
2491 else
2492 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2493
2494 copy_vmcb_control_area(hsave, vmcb);
2495
2496 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2497 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2498 else
2499 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2500
2501 if (nested_vmcb->control.nested_ctl) {
2502 kvm_mmu_unload(&svm->vcpu);
2503 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2504 nested_svm_init_mmu_context(&svm->vcpu);
2505 }
2506
2507 /* Load the nested guest state */
2508 svm->vmcb->save.es = nested_vmcb->save.es;
2509 svm->vmcb->save.cs = nested_vmcb->save.cs;
2510 svm->vmcb->save.ss = nested_vmcb->save.ss;
2511 svm->vmcb->save.ds = nested_vmcb->save.ds;
2512 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2513 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2514 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2515 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2516 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2517 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2518 if (npt_enabled) {
2519 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2520 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2521 } else
2522 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2523
2524 /* Guest paging mode is active - reset mmu */
2525 kvm_mmu_reset_context(&svm->vcpu);
2526
2527 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2528 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2529 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2530 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2531
2532 /* In case we don't even reach vcpu_run, the fields are not updated */
2533 svm->vmcb->save.rax = nested_vmcb->save.rax;
2534 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2535 svm->vmcb->save.rip = nested_vmcb->save.rip;
2536 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2537 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2538 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2539
2540 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2541 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2542
2543 /* cache intercepts */
2544 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2545 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2546 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2547 svm->nested.intercept = nested_vmcb->control.intercept;
2548
2549 svm_flush_tlb(&svm->vcpu);
2550 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2551 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2552 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2553 else
2554 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2555
2556 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2557 /* We only want the cr8 intercept bits of the guest */
2558 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2559 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2560 }
2561
2562 /* We don't want to see VMMCALLs from a nested guest */
2563 clr_intercept(svm, INTERCEPT_VMMCALL);
2564
2565 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2566 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2567 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2568 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2569 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2570 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2571
2572 nested_svm_unmap(page);
2573
2574 /* Enter Guest-Mode */
2575 enter_guest_mode(&svm->vcpu);
2576
2577 /*
2578 * Merge guest and host intercepts - must be called with vcpu in
2579 * guest-mode to take affect here
2580 */
2581 recalc_intercepts(svm);
2582
2583 svm->nested.vmcb = vmcb_gpa;
2584
2585 enable_gif(svm);
2586
2587 mark_all_dirty(svm->vmcb);
2588
2589 return true;
2590}
2591
2592static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2593{
2594 to_vmcb->save.fs = from_vmcb->save.fs;
2595 to_vmcb->save.gs = from_vmcb->save.gs;
2596 to_vmcb->save.tr = from_vmcb->save.tr;
2597 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2598 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2599 to_vmcb->save.star = from_vmcb->save.star;
2600 to_vmcb->save.lstar = from_vmcb->save.lstar;
2601 to_vmcb->save.cstar = from_vmcb->save.cstar;
2602 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2603 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2604 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2605 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2606}
2607
2608static int vmload_interception(struct vcpu_svm *svm)
2609{
2610 struct vmcb *nested_vmcb;
2611 struct page *page;
2612
2613 if (nested_svm_check_permissions(svm))
2614 return 1;
2615
2616 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2617 if (!nested_vmcb)
2618 return 1;
2619
2620 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2621 skip_emulated_instruction(&svm->vcpu);
2622
2623 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2624 nested_svm_unmap(page);
2625
2626 return 1;
2627}
2628
2629static int vmsave_interception(struct vcpu_svm *svm)
2630{
2631 struct vmcb *nested_vmcb;
2632 struct page *page;
2633
2634 if (nested_svm_check_permissions(svm))
2635 return 1;
2636
2637 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2638 if (!nested_vmcb)
2639 return 1;
2640
2641 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2642 skip_emulated_instruction(&svm->vcpu);
2643
2644 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2645 nested_svm_unmap(page);
2646
2647 return 1;
2648}
2649
2650static int vmrun_interception(struct vcpu_svm *svm)
2651{
2652 if (nested_svm_check_permissions(svm))
2653 return 1;
2654
2655 /* Save rip after vmrun instruction */
2656 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2657
2658 if (!nested_svm_vmrun(svm))
2659 return 1;
2660
2661 if (!nested_svm_vmrun_msrpm(svm))
2662 goto failed;
2663
2664 return 1;
2665
2666failed:
2667
2668 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2669 svm->vmcb->control.exit_code_hi = 0;
2670 svm->vmcb->control.exit_info_1 = 0;
2671 svm->vmcb->control.exit_info_2 = 0;
2672
2673 nested_svm_vmexit(svm);
2674
2675 return 1;
2676}
2677
2678static int stgi_interception(struct vcpu_svm *svm)
2679{
2680 if (nested_svm_check_permissions(svm))
2681 return 1;
2682
2683 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2684 skip_emulated_instruction(&svm->vcpu);
2685 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2686
2687 enable_gif(svm);
2688
2689 return 1;
2690}
2691
2692static int clgi_interception(struct vcpu_svm *svm)
2693{
2694 if (nested_svm_check_permissions(svm))
2695 return 1;
2696
2697 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2698 skip_emulated_instruction(&svm->vcpu);
2699
2700 disable_gif(svm);
2701
2702 /* After a CLGI no interrupts should come */
2703 svm_clear_vintr(svm);
2704 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2705
2706 mark_dirty(svm->vmcb, VMCB_INTR);
2707
2708 return 1;
2709}
2710
2711static int invlpga_interception(struct vcpu_svm *svm)
2712{
2713 struct kvm_vcpu *vcpu = &svm->vcpu;
2714
2715 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2716 vcpu->arch.regs[VCPU_REGS_RAX]);
2717
2718 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2719 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2720
2721 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2722 skip_emulated_instruction(&svm->vcpu);
2723 return 1;
2724}
2725
2726static int skinit_interception(struct vcpu_svm *svm)
2727{
2728 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2729
2730 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2731 return 1;
2732}
2733
2734static int xsetbv_interception(struct vcpu_svm *svm)
2735{
2736 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2737 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2738
2739 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2740 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2741 skip_emulated_instruction(&svm->vcpu);
2742 }
2743
2744 return 1;
2745}
2746
2747static int invalid_op_interception(struct vcpu_svm *svm)
2748{
2749 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2750 return 1;
2751}
2752
2753static int task_switch_interception(struct vcpu_svm *svm)
2754{
2755 u16 tss_selector;
2756 int reason;
2757 int int_type = svm->vmcb->control.exit_int_info &
2758 SVM_EXITINTINFO_TYPE_MASK;
2759 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2760 uint32_t type =
2761 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2762 uint32_t idt_v =
2763 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2764 bool has_error_code = false;
2765 u32 error_code = 0;
2766
2767 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2768
2769 if (svm->vmcb->control.exit_info_2 &
2770 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2771 reason = TASK_SWITCH_IRET;
2772 else if (svm->vmcb->control.exit_info_2 &
2773 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2774 reason = TASK_SWITCH_JMP;
2775 else if (idt_v)
2776 reason = TASK_SWITCH_GATE;
2777 else
2778 reason = TASK_SWITCH_CALL;
2779
2780 if (reason == TASK_SWITCH_GATE) {
2781 switch (type) {
2782 case SVM_EXITINTINFO_TYPE_NMI:
2783 svm->vcpu.arch.nmi_injected = false;
2784 break;
2785 case SVM_EXITINTINFO_TYPE_EXEPT:
2786 if (svm->vmcb->control.exit_info_2 &
2787 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2788 has_error_code = true;
2789 error_code =
2790 (u32)svm->vmcb->control.exit_info_2;
2791 }
2792 kvm_clear_exception_queue(&svm->vcpu);
2793 break;
2794 case SVM_EXITINTINFO_TYPE_INTR:
2795 kvm_clear_interrupt_queue(&svm->vcpu);
2796 break;
2797 default:
2798 break;
2799 }
2800 }
2801
2802 if (reason != TASK_SWITCH_GATE ||
2803 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2804 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2805 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2806 skip_emulated_instruction(&svm->vcpu);
2807
2808 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2809 int_vec = -1;
2810
2811 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2812 has_error_code, error_code) == EMULATE_FAIL) {
2813 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2814 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2815 svm->vcpu.run->internal.ndata = 0;
2816 return 0;
2817 }
2818 return 1;
2819}
2820
2821static int cpuid_interception(struct vcpu_svm *svm)
2822{
2823 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2824 kvm_emulate_cpuid(&svm->vcpu);
2825 return 1;
2826}
2827
2828static int iret_interception(struct vcpu_svm *svm)
2829{
2830 ++svm->vcpu.stat.nmi_window_exits;
2831 clr_intercept(svm, INTERCEPT_IRET);
2832 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2833 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2834 return 1;
2835}
2836
2837static int invlpg_interception(struct vcpu_svm *svm)
2838{
2839 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2840 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2841
2842 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2843 skip_emulated_instruction(&svm->vcpu);
2844 return 1;
2845}
2846
2847static int emulate_on_interception(struct vcpu_svm *svm)
2848{
2849 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2850}
2851
2852static int rdpmc_interception(struct vcpu_svm *svm)
2853{
2854 int err;
2855
2856 if (!static_cpu_has(X86_FEATURE_NRIPS))
2857 return emulate_on_interception(svm);
2858
2859 err = kvm_rdpmc(&svm->vcpu);
2860 kvm_complete_insn_gp(&svm->vcpu, err);
2861
2862 return 1;
2863}
2864
2865bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val)
2866{
2867 unsigned long cr0 = svm->vcpu.arch.cr0;
2868 bool ret = false;
2869 u64 intercept;
2870
2871 intercept = svm->nested.intercept;
2872
2873 if (!is_guest_mode(&svm->vcpu) ||
2874 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2875 return false;
2876
2877 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2878 val &= ~SVM_CR0_SELECTIVE_MASK;
2879
2880 if (cr0 ^ val) {
2881 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2882 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2883 }
2884
2885 return ret;
2886}
2887
2888#define CR_VALID (1ULL << 63)
2889
2890static int cr_interception(struct vcpu_svm *svm)
2891{
2892 int reg, cr;
2893 unsigned long val;
2894 int err;
2895
2896 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2897 return emulate_on_interception(svm);
2898
2899 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2900 return emulate_on_interception(svm);
2901
2902 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2903 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2904
2905 err = 0;
2906 if (cr >= 16) { /* mov to cr */
2907 cr -= 16;
2908 val = kvm_register_read(&svm->vcpu, reg);
2909 switch (cr) {
2910 case 0:
2911 if (!check_selective_cr0_intercepted(svm, val))
2912 err = kvm_set_cr0(&svm->vcpu, val);
2913 else
2914 return 1;
2915
2916 break;
2917 case 3:
2918 err = kvm_set_cr3(&svm->vcpu, val);
2919 break;
2920 case 4:
2921 err = kvm_set_cr4(&svm->vcpu, val);
2922 break;
2923 case 8:
2924 err = kvm_set_cr8(&svm->vcpu, val);
2925 break;
2926 default:
2927 WARN(1, "unhandled write to CR%d", cr);
2928 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2929 return 1;
2930 }
2931 } else { /* mov from cr */
2932 switch (cr) {
2933 case 0:
2934 val = kvm_read_cr0(&svm->vcpu);
2935 break;
2936 case 2:
2937 val = svm->vcpu.arch.cr2;
2938 break;
2939 case 3:
2940 val = kvm_read_cr3(&svm->vcpu);
2941 break;
2942 case 4:
2943 val = kvm_read_cr4(&svm->vcpu);
2944 break;
2945 case 8:
2946 val = kvm_get_cr8(&svm->vcpu);
2947 break;
2948 default:
2949 WARN(1, "unhandled read from CR%d", cr);
2950 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2951 return 1;
2952 }
2953 kvm_register_write(&svm->vcpu, reg, val);
2954 }
2955 kvm_complete_insn_gp(&svm->vcpu, err);
2956
2957 return 1;
2958}
2959
2960static int dr_interception(struct vcpu_svm *svm)
2961{
2962 int reg, dr;
2963 unsigned long val;
2964 int err;
2965
2966 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2967 return emulate_on_interception(svm);
2968
2969 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2970 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2971
2972 if (dr >= 16) { /* mov to DRn */
2973 val = kvm_register_read(&svm->vcpu, reg);
2974 kvm_set_dr(&svm->vcpu, dr - 16, val);
2975 } else {
2976 err = kvm_get_dr(&svm->vcpu, dr, &val);
2977 if (!err)
2978 kvm_register_write(&svm->vcpu, reg, val);
2979 }
2980
2981 skip_emulated_instruction(&svm->vcpu);
2982
2983 return 1;
2984}
2985
2986static int cr8_write_interception(struct vcpu_svm *svm)
2987{
2988 struct kvm_run *kvm_run = svm->vcpu.run;
2989 int r;
2990
2991 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2992 /* instruction emulation calls kvm_set_cr8() */
2993 r = cr_interception(svm);
2994 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2995 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2996 return r;
2997 }
2998 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2999 return r;
3000 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3001 return 0;
3002}
3003
3004u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
3005{
3006 struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
3007 return vmcb->control.tsc_offset +
3008 svm_scale_tsc(vcpu, host_tsc);
3009}
3010
3011static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
3012{
3013 struct vcpu_svm *svm = to_svm(vcpu);
3014
3015 switch (ecx) {
3016 case MSR_IA32_TSC: {
3017 *data = svm->vmcb->control.tsc_offset +
3018 svm_scale_tsc(vcpu, native_read_tsc());
3019
3020 break;
3021 }
3022 case MSR_STAR:
3023 *data = svm->vmcb->save.star;
3024 break;
3025#ifdef CONFIG_X86_64
3026 case MSR_LSTAR:
3027 *data = svm->vmcb->save.lstar;
3028 break;
3029 case MSR_CSTAR:
3030 *data = svm->vmcb->save.cstar;
3031 break;
3032 case MSR_KERNEL_GS_BASE:
3033 *data = svm->vmcb->save.kernel_gs_base;
3034 break;
3035 case MSR_SYSCALL_MASK:
3036 *data = svm->vmcb->save.sfmask;
3037 break;
3038#endif
3039 case MSR_IA32_SYSENTER_CS:
3040 *data = svm->vmcb->save.sysenter_cs;
3041 break;
3042 case MSR_IA32_SYSENTER_EIP:
3043 *data = svm->sysenter_eip;
3044 break;
3045 case MSR_IA32_SYSENTER_ESP:
3046 *data = svm->sysenter_esp;
3047 break;
3048 /*
3049 * Nobody will change the following 5 values in the VMCB so we can
3050 * safely return them on rdmsr. They will always be 0 until LBRV is
3051 * implemented.
3052 */
3053 case MSR_IA32_DEBUGCTLMSR:
3054 *data = svm->vmcb->save.dbgctl;
3055 break;
3056 case MSR_IA32_LASTBRANCHFROMIP:
3057 *data = svm->vmcb->save.br_from;
3058 break;
3059 case MSR_IA32_LASTBRANCHTOIP:
3060 *data = svm->vmcb->save.br_to;
3061 break;
3062 case MSR_IA32_LASTINTFROMIP:
3063 *data = svm->vmcb->save.last_excp_from;
3064 break;
3065 case MSR_IA32_LASTINTTOIP:
3066 *data = svm->vmcb->save.last_excp_to;
3067 break;
3068 case MSR_VM_HSAVE_PA:
3069 *data = svm->nested.hsave_msr;
3070 break;
3071 case MSR_VM_CR:
3072 *data = svm->nested.vm_cr_msr;
3073 break;
3074 case MSR_IA32_UCODE_REV:
3075 *data = 0x01000065;
3076 break;
3077 default:
3078 return kvm_get_msr_common(vcpu, ecx, data);
3079 }
3080 return 0;
3081}
3082
3083static int rdmsr_interception(struct vcpu_svm *svm)
3084{
3085 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3086 u64 data;
3087
3088 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
3089 trace_kvm_msr_read_ex(ecx);
3090 kvm_inject_gp(&svm->vcpu, 0);
3091 } else {
3092 trace_kvm_msr_read(ecx, data);
3093
3094 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
3095 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
3096 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3097 skip_emulated_instruction(&svm->vcpu);
3098 }
3099 return 1;
3100}
3101
3102static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3103{
3104 struct vcpu_svm *svm = to_svm(vcpu);
3105 int svm_dis, chg_mask;
3106
3107 if (data & ~SVM_VM_CR_VALID_MASK)
3108 return 1;
3109
3110 chg_mask = SVM_VM_CR_VALID_MASK;
3111
3112 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3113 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3114
3115 svm->nested.vm_cr_msr &= ~chg_mask;
3116 svm->nested.vm_cr_msr |= (data & chg_mask);
3117
3118 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3119
3120 /* check for svm_disable while efer.svme is set */
3121 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3122 return 1;
3123
3124 return 0;
3125}
3126
3127static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3128{
3129 struct vcpu_svm *svm = to_svm(vcpu);
3130
3131 u32 ecx = msr->index;
3132 u64 data = msr->data;
3133 switch (ecx) {
3134 case MSR_IA32_TSC:
3135 kvm_write_tsc(vcpu, msr);
3136 break;
3137 case MSR_STAR:
3138 svm->vmcb->save.star = data;
3139 break;
3140#ifdef CONFIG_X86_64
3141 case MSR_LSTAR:
3142 svm->vmcb->save.lstar = data;
3143 break;
3144 case MSR_CSTAR:
3145 svm->vmcb->save.cstar = data;
3146 break;
3147 case MSR_KERNEL_GS_BASE:
3148 svm->vmcb->save.kernel_gs_base = data;
3149 break;
3150 case MSR_SYSCALL_MASK:
3151 svm->vmcb->save.sfmask = data;
3152 break;
3153#endif
3154 case MSR_IA32_SYSENTER_CS:
3155 svm->vmcb->save.sysenter_cs = data;
3156 break;
3157 case MSR_IA32_SYSENTER_EIP:
3158 svm->sysenter_eip = data;
3159 svm->vmcb->save.sysenter_eip = data;
3160 break;
3161 case MSR_IA32_SYSENTER_ESP:
3162 svm->sysenter_esp = data;
3163 svm->vmcb->save.sysenter_esp = data;
3164 break;
3165 case MSR_IA32_DEBUGCTLMSR:
3166 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3167 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3168 __func__, data);
3169 break;
3170 }
3171 if (data & DEBUGCTL_RESERVED_BITS)
3172 return 1;
3173
3174 svm->vmcb->save.dbgctl = data;
3175 mark_dirty(svm->vmcb, VMCB_LBR);
3176 if (data & (1ULL<<0))
3177 svm_enable_lbrv(svm);
3178 else
3179 svm_disable_lbrv(svm);
3180 break;
3181 case MSR_VM_HSAVE_PA:
3182 svm->nested.hsave_msr = data;
3183 break;
3184 case MSR_VM_CR:
3185 return svm_set_vm_cr(vcpu, data);
3186 case MSR_VM_IGNNE:
3187 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3188 break;
3189 default:
3190 return kvm_set_msr_common(vcpu, msr);
3191 }
3192 return 0;
3193}
3194
3195static int wrmsr_interception(struct vcpu_svm *svm)
3196{
3197 struct msr_data msr;
3198 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3199 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
3200 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3201
3202 msr.data = data;
3203 msr.index = ecx;
3204 msr.host_initiated = false;
3205
3206 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3207 if (svm_set_msr(&svm->vcpu, &msr)) {
3208 trace_kvm_msr_write_ex(ecx, data);
3209 kvm_inject_gp(&svm->vcpu, 0);
3210 } else {
3211 trace_kvm_msr_write(ecx, data);
3212 skip_emulated_instruction(&svm->vcpu);
3213 }
3214 return 1;
3215}
3216
3217static int msr_interception(struct vcpu_svm *svm)
3218{
3219 if (svm->vmcb->control.exit_info_1)
3220 return wrmsr_interception(svm);
3221 else
3222 return rdmsr_interception(svm);
3223}
3224
3225static int interrupt_window_interception(struct vcpu_svm *svm)
3226{
3227 struct kvm_run *kvm_run = svm->vcpu.run;
3228
3229 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3230 svm_clear_vintr(svm);
3231 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3232 mark_dirty(svm->vmcb, VMCB_INTR);
3233 ++svm->vcpu.stat.irq_window_exits;
3234 /*
3235 * If the user space waits to inject interrupts, exit as soon as
3236 * possible
3237 */
3238 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3239 kvm_run->request_interrupt_window &&
3240 !kvm_cpu_has_interrupt(&svm->vcpu)) {
3241 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3242 return 0;
3243 }
3244
3245 return 1;
3246}
3247
3248static int pause_interception(struct vcpu_svm *svm)
3249{
3250 kvm_vcpu_on_spin(&(svm->vcpu));
3251 return 1;
3252}
3253
3254static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3255 [SVM_EXIT_READ_CR0] = cr_interception,
3256 [SVM_EXIT_READ_CR3] = cr_interception,
3257 [SVM_EXIT_READ_CR4] = cr_interception,
3258 [SVM_EXIT_READ_CR8] = cr_interception,
3259 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
3260 [SVM_EXIT_WRITE_CR0] = cr_interception,
3261 [SVM_EXIT_WRITE_CR3] = cr_interception,
3262 [SVM_EXIT_WRITE_CR4] = cr_interception,
3263 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3264 [SVM_EXIT_READ_DR0] = dr_interception,
3265 [SVM_EXIT_READ_DR1] = dr_interception,
3266 [SVM_EXIT_READ_DR2] = dr_interception,
3267 [SVM_EXIT_READ_DR3] = dr_interception,
3268 [SVM_EXIT_READ_DR4] = dr_interception,
3269 [SVM_EXIT_READ_DR5] = dr_interception,
3270 [SVM_EXIT_READ_DR6] = dr_interception,
3271 [SVM_EXIT_READ_DR7] = dr_interception,
3272 [SVM_EXIT_WRITE_DR0] = dr_interception,
3273 [SVM_EXIT_WRITE_DR1] = dr_interception,
3274 [SVM_EXIT_WRITE_DR2] = dr_interception,
3275 [SVM_EXIT_WRITE_DR3] = dr_interception,
3276 [SVM_EXIT_WRITE_DR4] = dr_interception,
3277 [SVM_EXIT_WRITE_DR5] = dr_interception,
3278 [SVM_EXIT_WRITE_DR6] = dr_interception,
3279 [SVM_EXIT_WRITE_DR7] = dr_interception,
3280 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3281 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3282 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3283 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3284 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
3285 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3286 [SVM_EXIT_INTR] = intr_interception,
3287 [SVM_EXIT_NMI] = nmi_interception,
3288 [SVM_EXIT_SMI] = nop_on_interception,
3289 [SVM_EXIT_INIT] = nop_on_interception,
3290 [SVM_EXIT_VINTR] = interrupt_window_interception,
3291 [SVM_EXIT_RDPMC] = rdpmc_interception,
3292 [SVM_EXIT_CPUID] = cpuid_interception,
3293 [SVM_EXIT_IRET] = iret_interception,
3294 [SVM_EXIT_INVD] = emulate_on_interception,
3295 [SVM_EXIT_PAUSE] = pause_interception,
3296 [SVM_EXIT_HLT] = halt_interception,
3297 [SVM_EXIT_INVLPG] = invlpg_interception,
3298 [SVM_EXIT_INVLPGA] = invlpga_interception,
3299 [SVM_EXIT_IOIO] = io_interception,
3300 [SVM_EXIT_MSR] = msr_interception,
3301 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3302 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3303 [SVM_EXIT_VMRUN] = vmrun_interception,
3304 [SVM_EXIT_VMMCALL] = vmmcall_interception,
3305 [SVM_EXIT_VMLOAD] = vmload_interception,
3306 [SVM_EXIT_VMSAVE] = vmsave_interception,
3307 [SVM_EXIT_STGI] = stgi_interception,
3308 [SVM_EXIT_CLGI] = clgi_interception,
3309 [SVM_EXIT_SKINIT] = skinit_interception,
3310 [SVM_EXIT_WBINVD] = emulate_on_interception,
3311 [SVM_EXIT_MONITOR] = invalid_op_interception,
3312 [SVM_EXIT_MWAIT] = invalid_op_interception,
3313 [SVM_EXIT_XSETBV] = xsetbv_interception,
3314 [SVM_EXIT_NPF] = pf_interception,
3315};
3316
3317static void dump_vmcb(struct kvm_vcpu *vcpu)
3318{
3319 struct vcpu_svm *svm = to_svm(vcpu);
3320 struct vmcb_control_area *control = &svm->vmcb->control;
3321 struct vmcb_save_area *save = &svm->vmcb->save;
3322
3323 pr_err("VMCB Control Area:\n");
3324 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3325 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3326 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3327 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3328 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3329 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3330 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3331 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3332 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3333 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3334 pr_err("%-20s%d\n", "asid:", control->asid);
3335 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3336 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3337 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3338 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3339 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3340 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3341 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3342 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3343 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3344 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3345 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3346 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3347 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3348 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3349 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3350 pr_err("VMCB State Save Area:\n");
3351 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3352 "es:",
3353 save->es.selector, save->es.attrib,
3354 save->es.limit, save->es.base);
3355 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3356 "cs:",
3357 save->cs.selector, save->cs.attrib,
3358 save->cs.limit, save->cs.base);
3359 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3360 "ss:",
3361 save->ss.selector, save->ss.attrib,
3362 save->ss.limit, save->ss.base);
3363 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3364 "ds:",
3365 save->ds.selector, save->ds.attrib,
3366 save->ds.limit, save->ds.base);
3367 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3368 "fs:",
3369 save->fs.selector, save->fs.attrib,
3370 save->fs.limit, save->fs.base);
3371 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3372 "gs:",
3373 save->gs.selector, save->gs.attrib,
3374 save->gs.limit, save->gs.base);
3375 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3376 "gdtr:",
3377 save->gdtr.selector, save->gdtr.attrib,
3378 save->gdtr.limit, save->gdtr.base);
3379 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3380 "ldtr:",
3381 save->ldtr.selector, save->ldtr.attrib,
3382 save->ldtr.limit, save->ldtr.base);
3383 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3384 "idtr:",
3385 save->idtr.selector, save->idtr.attrib,
3386 save->idtr.limit, save->idtr.base);
3387 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3388 "tr:",
3389 save->tr.selector, save->tr.attrib,
3390 save->tr.limit, save->tr.base);
3391 pr_err("cpl: %d efer: %016llx\n",
3392 save->cpl, save->efer);
3393 pr_err("%-15s %016llx %-13s %016llx\n",
3394 "cr0:", save->cr0, "cr2:", save->cr2);
3395 pr_err("%-15s %016llx %-13s %016llx\n",
3396 "cr3:", save->cr3, "cr4:", save->cr4);
3397 pr_err("%-15s %016llx %-13s %016llx\n",
3398 "dr6:", save->dr6, "dr7:", save->dr7);
3399 pr_err("%-15s %016llx %-13s %016llx\n",
3400 "rip:", save->rip, "rflags:", save->rflags);
3401 pr_err("%-15s %016llx %-13s %016llx\n",
3402 "rsp:", save->rsp, "rax:", save->rax);
3403 pr_err("%-15s %016llx %-13s %016llx\n",
3404 "star:", save->star, "lstar:", save->lstar);
3405 pr_err("%-15s %016llx %-13s %016llx\n",
3406 "cstar:", save->cstar, "sfmask:", save->sfmask);
3407 pr_err("%-15s %016llx %-13s %016llx\n",
3408 "kernel_gs_base:", save->kernel_gs_base,
3409 "sysenter_cs:", save->sysenter_cs);
3410 pr_err("%-15s %016llx %-13s %016llx\n",
3411 "sysenter_esp:", save->sysenter_esp,
3412 "sysenter_eip:", save->sysenter_eip);
3413 pr_err("%-15s %016llx %-13s %016llx\n",
3414 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3415 pr_err("%-15s %016llx %-13s %016llx\n",
3416 "br_from:", save->br_from, "br_to:", save->br_to);
3417 pr_err("%-15s %016llx %-13s %016llx\n",
3418 "excp_from:", save->last_excp_from,
3419 "excp_to:", save->last_excp_to);
3420}
3421
3422static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3423{
3424 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3425
3426 *info1 = control->exit_info_1;
3427 *info2 = control->exit_info_2;
3428}
3429
3430static int handle_exit(struct kvm_vcpu *vcpu)
3431{
3432 struct vcpu_svm *svm = to_svm(vcpu);
3433 struct kvm_run *kvm_run = vcpu->run;
3434 u32 exit_code = svm->vmcb->control.exit_code;
3435
3436 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3437 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3438 if (npt_enabled)
3439 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3440
3441 if (unlikely(svm->nested.exit_required)) {
3442 nested_svm_vmexit(svm);
3443 svm->nested.exit_required = false;
3444
3445 return 1;
3446 }
3447
3448 if (is_guest_mode(vcpu)) {
3449 int vmexit;
3450
3451 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3452 svm->vmcb->control.exit_info_1,
3453 svm->vmcb->control.exit_info_2,
3454 svm->vmcb->control.exit_int_info,
3455 svm->vmcb->control.exit_int_info_err,
3456 KVM_ISA_SVM);
3457
3458 vmexit = nested_svm_exit_special(svm);
3459
3460 if (vmexit == NESTED_EXIT_CONTINUE)
3461 vmexit = nested_svm_exit_handled(svm);
3462
3463 if (vmexit == NESTED_EXIT_DONE)
3464 return 1;
3465 }
3466
3467 svm_complete_interrupts(svm);
3468
3469 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3470 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3471 kvm_run->fail_entry.hardware_entry_failure_reason
3472 = svm->vmcb->control.exit_code;
3473 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3474 dump_vmcb(vcpu);
3475 return 0;
3476 }
3477
3478 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3479 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3480 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3481 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3482 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3483 "exit_code 0x%x\n",
3484 __func__, svm->vmcb->control.exit_int_info,
3485 exit_code);
3486
3487 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3488 || !svm_exit_handlers[exit_code]) {
3489 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3490 kvm_run->hw.hardware_exit_reason = exit_code;
3491 return 0;
3492 }
3493
3494 return svm_exit_handlers[exit_code](svm);
3495}
3496
3497static void reload_tss(struct kvm_vcpu *vcpu)
3498{
3499 int cpu = raw_smp_processor_id();
3500
3501 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3502 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3503 load_TR_desc();
3504}
3505
3506static void pre_svm_run(struct vcpu_svm *svm)
3507{
3508 int cpu = raw_smp_processor_id();
3509
3510 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3511
3512 /* FIXME: handle wraparound of asid_generation */
3513 if (svm->asid_generation != sd->asid_generation)
3514 new_asid(svm, sd);
3515}
3516
3517static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3518{
3519 struct vcpu_svm *svm = to_svm(vcpu);
3520
3521 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3522 vcpu->arch.hflags |= HF_NMI_MASK;
3523 set_intercept(svm, INTERCEPT_IRET);
3524 ++vcpu->stat.nmi_injections;
3525}
3526
3527static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3528{
3529 struct vmcb_control_area *control;
3530
3531 control = &svm->vmcb->control;
3532 control->int_vector = irq;
3533 control->int_ctl &= ~V_INTR_PRIO_MASK;
3534 control->int_ctl |= V_IRQ_MASK |
3535 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3536 mark_dirty(svm->vmcb, VMCB_INTR);
3537}
3538
3539static void svm_set_irq(struct kvm_vcpu *vcpu)
3540{
3541 struct vcpu_svm *svm = to_svm(vcpu);
3542
3543 BUG_ON(!(gif_set(svm)));
3544
3545 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3546 ++vcpu->stat.irq_injections;
3547
3548 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3549 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3550}
3551
3552static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3553{
3554 struct vcpu_svm *svm = to_svm(vcpu);
3555
3556 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3557 return;
3558
3559 if (irr == -1)
3560 return;
3561
3562 if (tpr >= irr)
3563 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3564}
3565
3566static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
3567{
3568 return;
3569}
3570
3571static int svm_vm_has_apicv(struct kvm *kvm)
3572{
3573 return 0;
3574}
3575
3576static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
3577{
3578 return;
3579}
3580
3581static void svm_hwapic_isr_update(struct kvm *kvm, int isr)
3582{
3583 return;
3584}
3585
3586static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3587{
3588 struct vcpu_svm *svm = to_svm(vcpu);
3589 struct vmcb *vmcb = svm->vmcb;
3590 int ret;
3591 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3592 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3593 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3594
3595 return ret;
3596}
3597
3598static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3599{
3600 struct vcpu_svm *svm = to_svm(vcpu);
3601
3602 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3603}
3604
3605static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3606{
3607 struct vcpu_svm *svm = to_svm(vcpu);
3608
3609 if (masked) {
3610 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3611 set_intercept(svm, INTERCEPT_IRET);
3612 } else {
3613 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3614 clr_intercept(svm, INTERCEPT_IRET);
3615 }
3616}
3617
3618static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3619{
3620 struct vcpu_svm *svm = to_svm(vcpu);
3621 struct vmcb *vmcb = svm->vmcb;
3622 int ret;
3623
3624 if (!gif_set(svm) ||
3625 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3626 return 0;
3627
3628 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3629
3630 if (is_guest_mode(vcpu))
3631 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3632
3633 return ret;
3634}
3635
3636static void enable_irq_window(struct kvm_vcpu *vcpu)
3637{
3638 struct vcpu_svm *svm = to_svm(vcpu);
3639
3640 /*
3641 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3642 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3643 * get that intercept, this function will be called again though and
3644 * we'll get the vintr intercept.
3645 */
3646 if (gif_set(svm) && nested_svm_intr(svm)) {
3647 svm_set_vintr(svm);
3648 svm_inject_irq(svm, 0x0);
3649 }
3650}
3651
3652static void enable_nmi_window(struct kvm_vcpu *vcpu)
3653{
3654 struct vcpu_svm *svm = to_svm(vcpu);
3655
3656 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3657 == HF_NMI_MASK)
3658 return; /* IRET will cause a vm exit */
3659
3660 /*
3661 * Something prevents NMI from been injected. Single step over possible
3662 * problem (IRET or exception injection or interrupt shadow)
3663 */
3664 svm->nmi_singlestep = true;
3665 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3666 update_db_bp_intercept(vcpu);
3667}
3668
3669static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3670{
3671 return 0;
3672}
3673
3674static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3675{
3676 struct vcpu_svm *svm = to_svm(vcpu);
3677
3678 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3679 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3680 else
3681 svm->asid_generation--;
3682}
3683
3684static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3685{
3686}
3687
3688static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3689{
3690 struct vcpu_svm *svm = to_svm(vcpu);
3691
3692 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3693 return;
3694
3695 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3696 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3697 kvm_set_cr8(vcpu, cr8);
3698 }
3699}
3700
3701static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3702{
3703 struct vcpu_svm *svm = to_svm(vcpu);
3704 u64 cr8;
3705
3706 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3707 return;
3708
3709 cr8 = kvm_get_cr8(vcpu);
3710 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3711 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3712}
3713
3714static void svm_complete_interrupts(struct vcpu_svm *svm)
3715{
3716 u8 vector;
3717 int type;
3718 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3719 unsigned int3_injected = svm->int3_injected;
3720
3721 svm->int3_injected = 0;
3722
3723 /*
3724 * If we've made progress since setting HF_IRET_MASK, we've
3725 * executed an IRET and can allow NMI injection.
3726 */
3727 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3728 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3729 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3730 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3731 }
3732
3733 svm->vcpu.arch.nmi_injected = false;
3734 kvm_clear_exception_queue(&svm->vcpu);
3735 kvm_clear_interrupt_queue(&svm->vcpu);
3736
3737 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3738 return;
3739
3740 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3741
3742 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3743 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3744
3745 switch (type) {
3746 case SVM_EXITINTINFO_TYPE_NMI:
3747 svm->vcpu.arch.nmi_injected = true;
3748 break;
3749 case SVM_EXITINTINFO_TYPE_EXEPT:
3750 /*
3751 * In case of software exceptions, do not reinject the vector,
3752 * but re-execute the instruction instead. Rewind RIP first
3753 * if we emulated INT3 before.
3754 */
3755 if (kvm_exception_is_soft(vector)) {
3756 if (vector == BP_VECTOR && int3_injected &&
3757 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3758 kvm_rip_write(&svm->vcpu,
3759 kvm_rip_read(&svm->vcpu) -
3760 int3_injected);
3761 break;
3762 }
3763 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3764 u32 err = svm->vmcb->control.exit_int_info_err;
3765 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3766
3767 } else
3768 kvm_requeue_exception(&svm->vcpu, vector);
3769 break;
3770 case SVM_EXITINTINFO_TYPE_INTR:
3771 kvm_queue_interrupt(&svm->vcpu, vector, false);
3772 break;
3773 default:
3774 break;
3775 }
3776}
3777
3778static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3779{
3780 struct vcpu_svm *svm = to_svm(vcpu);
3781 struct vmcb_control_area *control = &svm->vmcb->control;
3782
3783 control->exit_int_info = control->event_inj;
3784 control->exit_int_info_err = control->event_inj_err;
3785 control->event_inj = 0;
3786 svm_complete_interrupts(svm);
3787}
3788
3789static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3790{
3791 struct vcpu_svm *svm = to_svm(vcpu);
3792
3793 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3794 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3795 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3796
3797 /*
3798 * A vmexit emulation is required before the vcpu can be executed
3799 * again.
3800 */
3801 if (unlikely(svm->nested.exit_required))
3802 return;
3803
3804 pre_svm_run(svm);
3805
3806 sync_lapic_to_cr8(vcpu);
3807
3808 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3809
3810 clgi();
3811
3812 local_irq_enable();
3813
3814 asm volatile (
3815 "push %%" _ASM_BP "; \n\t"
3816 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
3817 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
3818 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
3819 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
3820 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
3821 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
3822#ifdef CONFIG_X86_64
3823 "mov %c[r8](%[svm]), %%r8 \n\t"
3824 "mov %c[r9](%[svm]), %%r9 \n\t"
3825 "mov %c[r10](%[svm]), %%r10 \n\t"
3826 "mov %c[r11](%[svm]), %%r11 \n\t"
3827 "mov %c[r12](%[svm]), %%r12 \n\t"
3828 "mov %c[r13](%[svm]), %%r13 \n\t"
3829 "mov %c[r14](%[svm]), %%r14 \n\t"
3830 "mov %c[r15](%[svm]), %%r15 \n\t"
3831#endif
3832
3833 /* Enter guest mode */
3834 "push %%" _ASM_AX " \n\t"
3835 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
3836 __ex(SVM_VMLOAD) "\n\t"
3837 __ex(SVM_VMRUN) "\n\t"
3838 __ex(SVM_VMSAVE) "\n\t"
3839 "pop %%" _ASM_AX " \n\t"
3840
3841 /* Save guest registers, load host registers */
3842 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
3843 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
3844 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
3845 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
3846 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
3847 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
3848#ifdef CONFIG_X86_64
3849 "mov %%r8, %c[r8](%[svm]) \n\t"
3850 "mov %%r9, %c[r9](%[svm]) \n\t"
3851 "mov %%r10, %c[r10](%[svm]) \n\t"
3852 "mov %%r11, %c[r11](%[svm]) \n\t"
3853 "mov %%r12, %c[r12](%[svm]) \n\t"
3854 "mov %%r13, %c[r13](%[svm]) \n\t"
3855 "mov %%r14, %c[r14](%[svm]) \n\t"
3856 "mov %%r15, %c[r15](%[svm]) \n\t"
3857#endif
3858 "pop %%" _ASM_BP
3859 :
3860 : [svm]"a"(svm),
3861 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3862 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3863 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3864 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3865 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3866 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3867 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3868#ifdef CONFIG_X86_64
3869 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3870 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3871 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3872 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3873 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3874 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3875 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3876 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3877#endif
3878 : "cc", "memory"
3879#ifdef CONFIG_X86_64
3880 , "rbx", "rcx", "rdx", "rsi", "rdi"
3881 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3882#else
3883 , "ebx", "ecx", "edx", "esi", "edi"
3884#endif
3885 );
3886
3887#ifdef CONFIG_X86_64
3888 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3889#else
3890 loadsegment(fs, svm->host.fs);
3891#ifndef CONFIG_X86_32_LAZY_GS
3892 loadsegment(gs, svm->host.gs);
3893#endif
3894#endif
3895
3896 reload_tss(vcpu);
3897
3898 local_irq_disable();
3899
3900 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3901 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3902 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3903 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3904
3905 trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
3906
3907 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3908 kvm_before_handle_nmi(&svm->vcpu);
3909
3910 stgi();
3911
3912 /* Any pending NMI will happen here */
3913
3914 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3915 kvm_after_handle_nmi(&svm->vcpu);
3916
3917 sync_cr8_to_lapic(vcpu);
3918
3919 svm->next_rip = 0;
3920
3921 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3922
3923 /* if exit due to PF check for async PF */
3924 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3925 svm->apf_reason = kvm_read_and_reset_pf_reason();
3926
3927 if (npt_enabled) {
3928 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3929 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3930 }
3931
3932 /*
3933 * We need to handle MC intercepts here before the vcpu has a chance to
3934 * change the physical cpu
3935 */
3936 if (unlikely(svm->vmcb->control.exit_code ==
3937 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3938 svm_handle_mce(svm);
3939
3940 mark_all_clean(svm->vmcb);
3941}
3942
3943static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3944{
3945 struct vcpu_svm *svm = to_svm(vcpu);
3946
3947 svm->vmcb->save.cr3 = root;
3948 mark_dirty(svm->vmcb, VMCB_CR);
3949 svm_flush_tlb(vcpu);
3950}
3951
3952static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3953{
3954 struct vcpu_svm *svm = to_svm(vcpu);
3955
3956 svm->vmcb->control.nested_cr3 = root;
3957 mark_dirty(svm->vmcb, VMCB_NPT);
3958
3959 /* Also sync guest cr3 here in case we live migrate */
3960 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
3961 mark_dirty(svm->vmcb, VMCB_CR);
3962
3963 svm_flush_tlb(vcpu);
3964}
3965
3966static int is_disabled(void)
3967{
3968 u64 vm_cr;
3969
3970 rdmsrl(MSR_VM_CR, vm_cr);
3971 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3972 return 1;
3973
3974 return 0;
3975}
3976
3977static void
3978svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3979{
3980 /*
3981 * Patch in the VMMCALL instruction:
3982 */
3983 hypercall[0] = 0x0f;
3984 hypercall[1] = 0x01;
3985 hypercall[2] = 0xd9;
3986}
3987
3988static void svm_check_processor_compat(void *rtn)
3989{
3990 *(int *)rtn = 0;
3991}
3992
3993static bool svm_cpu_has_accelerated_tpr(void)
3994{
3995 return false;
3996}
3997
3998static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3999{
4000 return 0;
4001}
4002
4003static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4004{
4005}
4006
4007static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4008{
4009 switch (func) {
4010 case 0x80000001:
4011 if (nested)
4012 entry->ecx |= (1 << 2); /* Set SVM bit */
4013 break;
4014 case 0x8000000A:
4015 entry->eax = 1; /* SVM revision 1 */
4016 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
4017 ASID emulation to nested SVM */
4018 entry->ecx = 0; /* Reserved */
4019 entry->edx = 0; /* Per default do not support any
4020 additional features */
4021
4022 /* Support next_rip if host supports it */
4023 if (boot_cpu_has(X86_FEATURE_NRIPS))
4024 entry->edx |= SVM_FEATURE_NRIP;
4025
4026 /* Support NPT for the guest if enabled */
4027 if (npt_enabled)
4028 entry->edx |= SVM_FEATURE_NPT;
4029
4030 break;
4031 }
4032}
4033
4034static int svm_get_lpage_level(void)
4035{
4036 return PT_PDPE_LEVEL;
4037}
4038
4039static bool svm_rdtscp_supported(void)
4040{
4041 return false;
4042}
4043
4044static bool svm_invpcid_supported(void)
4045{
4046 return false;
4047}
4048
4049static bool svm_has_wbinvd_exit(void)
4050{
4051 return true;
4052}
4053
4054static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
4055{
4056 struct vcpu_svm *svm = to_svm(vcpu);
4057
4058 set_exception_intercept(svm, NM_VECTOR);
4059 update_cr0_intercept(svm);
4060}
4061
4062#define PRE_EX(exit) { .exit_code = (exit), \
4063 .stage = X86_ICPT_PRE_EXCEPT, }
4064#define POST_EX(exit) { .exit_code = (exit), \
4065 .stage = X86_ICPT_POST_EXCEPT, }
4066#define POST_MEM(exit) { .exit_code = (exit), \
4067 .stage = X86_ICPT_POST_MEMACCESS, }
4068
4069static const struct __x86_intercept {
4070 u32 exit_code;
4071 enum x86_intercept_stage stage;
4072} x86_intercept_map[] = {
4073 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4074 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4075 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4076 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4077 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4078 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4079 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4080 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4081 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4082 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4083 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4084 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4085 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4086 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4087 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4088 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4089 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4090 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4091 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4092 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4093 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4094 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4095 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4096 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4097 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4098 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4099 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4100 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4101 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4102 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4103 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4104 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4105 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4106 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4107 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4108 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4109 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4110 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4111 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4112 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4113 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4114 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4115 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4116 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4117 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4118 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4119};
4120
4121#undef PRE_EX
4122#undef POST_EX
4123#undef POST_MEM
4124
4125static int svm_check_intercept(struct kvm_vcpu *vcpu,
4126 struct x86_instruction_info *info,
4127 enum x86_intercept_stage stage)
4128{
4129 struct vcpu_svm *svm = to_svm(vcpu);
4130 int vmexit, ret = X86EMUL_CONTINUE;
4131 struct __x86_intercept icpt_info;
4132 struct vmcb *vmcb = svm->vmcb;
4133
4134 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4135 goto out;
4136
4137 icpt_info = x86_intercept_map[info->intercept];
4138
4139 if (stage != icpt_info.stage)
4140 goto out;
4141
4142 switch (icpt_info.exit_code) {
4143 case SVM_EXIT_READ_CR0:
4144 if (info->intercept == x86_intercept_cr_read)
4145 icpt_info.exit_code += info->modrm_reg;
4146 break;
4147 case SVM_EXIT_WRITE_CR0: {
4148 unsigned long cr0, val;
4149 u64 intercept;
4150
4151 if (info->intercept == x86_intercept_cr_write)
4152 icpt_info.exit_code += info->modrm_reg;
4153
4154 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0)
4155 break;
4156
4157 intercept = svm->nested.intercept;
4158
4159 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4160 break;
4161
4162 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4163 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4164
4165 if (info->intercept == x86_intercept_lmsw) {
4166 cr0 &= 0xfUL;
4167 val &= 0xfUL;
4168 /* lmsw can't clear PE - catch this here */
4169 if (cr0 & X86_CR0_PE)
4170 val |= X86_CR0_PE;
4171 }
4172
4173 if (cr0 ^ val)
4174 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4175
4176 break;
4177 }
4178 case SVM_EXIT_READ_DR0:
4179 case SVM_EXIT_WRITE_DR0:
4180 icpt_info.exit_code += info->modrm_reg;
4181 break;
4182 case SVM_EXIT_MSR:
4183 if (info->intercept == x86_intercept_wrmsr)
4184 vmcb->control.exit_info_1 = 1;
4185 else
4186 vmcb->control.exit_info_1 = 0;
4187 break;
4188 case SVM_EXIT_PAUSE:
4189 /*
4190 * We get this for NOP only, but pause
4191 * is rep not, check this here
4192 */
4193 if (info->rep_prefix != REPE_PREFIX)
4194 goto out;
4195 case SVM_EXIT_IOIO: {
4196 u64 exit_info;
4197 u32 bytes;
4198
4199 exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16;
4200
4201 if (info->intercept == x86_intercept_in ||
4202 info->intercept == x86_intercept_ins) {
4203 exit_info |= SVM_IOIO_TYPE_MASK;
4204 bytes = info->src_bytes;
4205 } else {
4206 bytes = info->dst_bytes;
4207 }
4208
4209 if (info->intercept == x86_intercept_outs ||
4210 info->intercept == x86_intercept_ins)
4211 exit_info |= SVM_IOIO_STR_MASK;
4212
4213 if (info->rep_prefix)
4214 exit_info |= SVM_IOIO_REP_MASK;
4215
4216 bytes = min(bytes, 4u);
4217
4218 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4219
4220 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4221
4222 vmcb->control.exit_info_1 = exit_info;
4223 vmcb->control.exit_info_2 = info->next_rip;
4224
4225 break;
4226 }
4227 default:
4228 break;
4229 }
4230
4231 vmcb->control.next_rip = info->next_rip;
4232 vmcb->control.exit_code = icpt_info.exit_code;
4233 vmexit = nested_svm_exit_handled(svm);
4234
4235 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4236 : X86EMUL_CONTINUE;
4237
4238out:
4239 return ret;
4240}
4241
4242static struct kvm_x86_ops svm_x86_ops = {
4243 .cpu_has_kvm_support = has_svm,
4244 .disabled_by_bios = is_disabled,
4245 .hardware_setup = svm_hardware_setup,
4246 .hardware_unsetup = svm_hardware_unsetup,
4247 .check_processor_compatibility = svm_check_processor_compat,
4248 .hardware_enable = svm_hardware_enable,
4249 .hardware_disable = svm_hardware_disable,
4250 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4251
4252 .vcpu_create = svm_create_vcpu,
4253 .vcpu_free = svm_free_vcpu,
4254 .vcpu_reset = svm_vcpu_reset,
4255
4256 .prepare_guest_switch = svm_prepare_guest_switch,
4257 .vcpu_load = svm_vcpu_load,
4258 .vcpu_put = svm_vcpu_put,
4259
4260 .update_db_bp_intercept = update_db_bp_intercept,
4261 .get_msr = svm_get_msr,
4262 .set_msr = svm_set_msr,
4263 .get_segment_base = svm_get_segment_base,
4264 .get_segment = svm_get_segment,
4265 .set_segment = svm_set_segment,
4266 .get_cpl = svm_get_cpl,
4267 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4268 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4269 .decache_cr3 = svm_decache_cr3,
4270 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4271 .set_cr0 = svm_set_cr0,
4272 .set_cr3 = svm_set_cr3,
4273 .set_cr4 = svm_set_cr4,
4274 .set_efer = svm_set_efer,
4275 .get_idt = svm_get_idt,
4276 .set_idt = svm_set_idt,
4277 .get_gdt = svm_get_gdt,
4278 .set_gdt = svm_set_gdt,
4279 .set_dr7 = svm_set_dr7,
4280 .cache_reg = svm_cache_reg,
4281 .get_rflags = svm_get_rflags,
4282 .set_rflags = svm_set_rflags,
4283 .fpu_activate = svm_fpu_activate,
4284 .fpu_deactivate = svm_fpu_deactivate,
4285
4286 .tlb_flush = svm_flush_tlb,
4287
4288 .run = svm_vcpu_run,
4289 .handle_exit = handle_exit,
4290 .skip_emulated_instruction = skip_emulated_instruction,
4291 .set_interrupt_shadow = svm_set_interrupt_shadow,
4292 .get_interrupt_shadow = svm_get_interrupt_shadow,
4293 .patch_hypercall = svm_patch_hypercall,
4294 .set_irq = svm_set_irq,
4295 .set_nmi = svm_inject_nmi,
4296 .queue_exception = svm_queue_exception,
4297 .cancel_injection = svm_cancel_injection,
4298 .interrupt_allowed = svm_interrupt_allowed,
4299 .nmi_allowed = svm_nmi_allowed,
4300 .get_nmi_mask = svm_get_nmi_mask,
4301 .set_nmi_mask = svm_set_nmi_mask,
4302 .enable_nmi_window = enable_nmi_window,
4303 .enable_irq_window = enable_irq_window,
4304 .update_cr8_intercept = update_cr8_intercept,
4305 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
4306 .vm_has_apicv = svm_vm_has_apicv,
4307 .load_eoi_exitmap = svm_load_eoi_exitmap,
4308 .hwapic_isr_update = svm_hwapic_isr_update,
4309
4310 .set_tss_addr = svm_set_tss_addr,
4311 .get_tdp_level = get_npt_level,
4312 .get_mt_mask = svm_get_mt_mask,
4313
4314 .get_exit_info = svm_get_exit_info,
4315
4316 .get_lpage_level = svm_get_lpage_level,
4317
4318 .cpuid_update = svm_cpuid_update,
4319
4320 .rdtscp_supported = svm_rdtscp_supported,
4321 .invpcid_supported = svm_invpcid_supported,
4322
4323 .set_supported_cpuid = svm_set_supported_cpuid,
4324
4325 .has_wbinvd_exit = svm_has_wbinvd_exit,
4326
4327 .set_tsc_khz = svm_set_tsc_khz,
4328 .read_tsc_offset = svm_read_tsc_offset,
4329 .write_tsc_offset = svm_write_tsc_offset,
4330 .adjust_tsc_offset = svm_adjust_tsc_offset,
4331 .compute_tsc_offset = svm_compute_tsc_offset,
4332 .read_l1_tsc = svm_read_l1_tsc,
4333
4334 .set_tdp_cr3 = set_tdp_cr3,
4335
4336 .check_intercept = svm_check_intercept,
4337};
4338
4339static int __init svm_init(void)
4340{
4341 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4342 __alignof__(struct vcpu_svm), THIS_MODULE);
4343}
4344
4345static void __exit svm_exit(void)
4346{
4347 kvm_exit();
4348}
4349
4350module_init(svm_init)
4351module_exit(svm_exit)
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