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1 | /* | |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * Copyright 2010 Red Hat, Inc. and/or its affilates. | |
8 | * | |
9 | * Authors: | |
10 | * Yaniv Kamay <yaniv@qumranet.com> | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
17 | #include <linux/kvm_host.h> | |
18 | ||
19 | #include "irq.h" | |
20 | #include "mmu.h" | |
21 | #include "kvm_cache_regs.h" | |
22 | #include "x86.h" | |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/vmalloc.h> | |
27 | #include <linux/highmem.h> | |
28 | #include <linux/sched.h> | |
29 | #include <linux/ftrace_event.h> | |
30 | #include <linux/slab.h> | |
31 | ||
32 | #include <asm/tlbflush.h> | |
33 | #include <asm/desc.h> | |
34 | ||
35 | #include <asm/virtext.h> | |
36 | #include "trace.h" | |
37 | ||
38 | #define __ex(x) __kvm_handle_fault_on_reboot(x) | |
39 | ||
40 | MODULE_AUTHOR("Qumranet"); | |
41 | MODULE_LICENSE("GPL"); | |
42 | ||
43 | #define IOPM_ALLOC_ORDER 2 | |
44 | #define MSRPM_ALLOC_ORDER 1 | |
45 | ||
46 | #define SEG_TYPE_LDT 2 | |
47 | #define SEG_TYPE_BUSY_TSS16 3 | |
48 | ||
49 | #define SVM_FEATURE_NPT (1 << 0) | |
50 | #define SVM_FEATURE_LBRV (1 << 1) | |
51 | #define SVM_FEATURE_SVML (1 << 2) | |
52 | #define SVM_FEATURE_NRIP (1 << 3) | |
53 | #define SVM_FEATURE_PAUSE_FILTER (1 << 10) | |
54 | ||
55 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ | |
56 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
57 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
58 | ||
59 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) | |
60 | ||
61 | static bool erratum_383_found __read_mostly; | |
62 | ||
63 | static const u32 host_save_user_msrs[] = { | |
64 | #ifdef CONFIG_X86_64 | |
65 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
66 | MSR_FS_BASE, | |
67 | #endif | |
68 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
69 | }; | |
70 | ||
71 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
72 | ||
73 | struct kvm_vcpu; | |
74 | ||
75 | struct nested_state { | |
76 | struct vmcb *hsave; | |
77 | u64 hsave_msr; | |
78 | u64 vm_cr_msr; | |
79 | u64 vmcb; | |
80 | ||
81 | /* These are the merged vectors */ | |
82 | u32 *msrpm; | |
83 | ||
84 | /* gpa pointers to the real vectors */ | |
85 | u64 vmcb_msrpm; | |
86 | u64 vmcb_iopm; | |
87 | ||
88 | /* A VMEXIT is required but not yet emulated */ | |
89 | bool exit_required; | |
90 | ||
91 | /* cache for intercepts of the guest */ | |
92 | u16 intercept_cr_read; | |
93 | u16 intercept_cr_write; | |
94 | u16 intercept_dr_read; | |
95 | u16 intercept_dr_write; | |
96 | u32 intercept_exceptions; | |
97 | u64 intercept; | |
98 | ||
99 | }; | |
100 | ||
101 | #define MSRPM_OFFSETS 16 | |
102 | static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; | |
103 | ||
104 | struct vcpu_svm { | |
105 | struct kvm_vcpu vcpu; | |
106 | struct vmcb *vmcb; | |
107 | unsigned long vmcb_pa; | |
108 | struct svm_cpu_data *svm_data; | |
109 | uint64_t asid_generation; | |
110 | uint64_t sysenter_esp; | |
111 | uint64_t sysenter_eip; | |
112 | ||
113 | u64 next_rip; | |
114 | ||
115 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
116 | u64 host_gs_base; | |
117 | ||
118 | u32 *msrpm; | |
119 | ||
120 | struct nested_state nested; | |
121 | ||
122 | bool nmi_singlestep; | |
123 | ||
124 | unsigned int3_injected; | |
125 | unsigned long int3_rip; | |
126 | }; | |
127 | ||
128 | #define MSR_INVALID 0xffffffffU | |
129 | ||
130 | static struct svm_direct_access_msrs { | |
131 | u32 index; /* Index of the MSR */ | |
132 | bool always; /* True if intercept is always on */ | |
133 | } direct_access_msrs[] = { | |
134 | { .index = MSR_STAR, .always = true }, | |
135 | { .index = MSR_IA32_SYSENTER_CS, .always = true }, | |
136 | #ifdef CONFIG_X86_64 | |
137 | { .index = MSR_GS_BASE, .always = true }, | |
138 | { .index = MSR_FS_BASE, .always = true }, | |
139 | { .index = MSR_KERNEL_GS_BASE, .always = true }, | |
140 | { .index = MSR_LSTAR, .always = true }, | |
141 | { .index = MSR_CSTAR, .always = true }, | |
142 | { .index = MSR_SYSCALL_MASK, .always = true }, | |
143 | #endif | |
144 | { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false }, | |
145 | { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, | |
146 | { .index = MSR_IA32_LASTINTFROMIP, .always = false }, | |
147 | { .index = MSR_IA32_LASTINTTOIP, .always = false }, | |
148 | { .index = MSR_INVALID, .always = false }, | |
149 | }; | |
150 | ||
151 | /* enable NPT for AMD64 and X86 with PAE */ | |
152 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
153 | static bool npt_enabled = true; | |
154 | #else | |
155 | static bool npt_enabled; | |
156 | #endif | |
157 | static int npt = 1; | |
158 | ||
159 | module_param(npt, int, S_IRUGO); | |
160 | ||
161 | static int nested = 1; | |
162 | module_param(nested, int, S_IRUGO); | |
163 | ||
164 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); | |
165 | static void svm_complete_interrupts(struct vcpu_svm *svm); | |
166 | ||
167 | static int nested_svm_exit_handled(struct vcpu_svm *svm); | |
168 | static int nested_svm_intercept(struct vcpu_svm *svm); | |
169 | static int nested_svm_vmexit(struct vcpu_svm *svm); | |
170 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, | |
171 | bool has_error_code, u32 error_code); | |
172 | ||
173 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) | |
174 | { | |
175 | return container_of(vcpu, struct vcpu_svm, vcpu); | |
176 | } | |
177 | ||
178 | static inline bool is_nested(struct vcpu_svm *svm) | |
179 | { | |
180 | return svm->nested.vmcb; | |
181 | } | |
182 | ||
183 | static inline void enable_gif(struct vcpu_svm *svm) | |
184 | { | |
185 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
186 | } | |
187 | ||
188 | static inline void disable_gif(struct vcpu_svm *svm) | |
189 | { | |
190 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
191 | } | |
192 | ||
193 | static inline bool gif_set(struct vcpu_svm *svm) | |
194 | { | |
195 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
196 | } | |
197 | ||
198 | static unsigned long iopm_base; | |
199 | ||
200 | struct kvm_ldttss_desc { | |
201 | u16 limit0; | |
202 | u16 base0; | |
203 | unsigned base1:8, type:5, dpl:2, p:1; | |
204 | unsigned limit1:4, zero0:3, g:1, base2:8; | |
205 | u32 base3; | |
206 | u32 zero1; | |
207 | } __attribute__((packed)); | |
208 | ||
209 | struct svm_cpu_data { | |
210 | int cpu; | |
211 | ||
212 | u64 asid_generation; | |
213 | u32 max_asid; | |
214 | u32 next_asid; | |
215 | struct kvm_ldttss_desc *tss_desc; | |
216 | ||
217 | struct page *save_area; | |
218 | }; | |
219 | ||
220 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
221 | static uint32_t svm_features; | |
222 | ||
223 | struct svm_init_data { | |
224 | int cpu; | |
225 | int r; | |
226 | }; | |
227 | ||
228 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
229 | ||
230 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) | |
231 | #define MSRS_RANGE_SIZE 2048 | |
232 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
233 | ||
234 | static u32 svm_msrpm_offset(u32 msr) | |
235 | { | |
236 | u32 offset; | |
237 | int i; | |
238 | ||
239 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
240 | if (msr < msrpm_ranges[i] || | |
241 | msr >= msrpm_ranges[i] + MSRS_IN_RANGE) | |
242 | continue; | |
243 | ||
244 | offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ | |
245 | offset += (i * MSRS_RANGE_SIZE); /* add range offset */ | |
246 | ||
247 | /* Now we have the u8 offset - but need the u32 offset */ | |
248 | return offset / 4; | |
249 | } | |
250 | ||
251 | /* MSR not in any range */ | |
252 | return MSR_INVALID; | |
253 | } | |
254 | ||
255 | #define MAX_INST_SIZE 15 | |
256 | ||
257 | static inline u32 svm_has(u32 feat) | |
258 | { | |
259 | return svm_features & feat; | |
260 | } | |
261 | ||
262 | static inline void clgi(void) | |
263 | { | |
264 | asm volatile (__ex(SVM_CLGI)); | |
265 | } | |
266 | ||
267 | static inline void stgi(void) | |
268 | { | |
269 | asm volatile (__ex(SVM_STGI)); | |
270 | } | |
271 | ||
272 | static inline void invlpga(unsigned long addr, u32 asid) | |
273 | { | |
274 | asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid)); | |
275 | } | |
276 | ||
277 | static inline void force_new_asid(struct kvm_vcpu *vcpu) | |
278 | { | |
279 | to_svm(vcpu)->asid_generation--; | |
280 | } | |
281 | ||
282 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
283 | { | |
284 | force_new_asid(vcpu); | |
285 | } | |
286 | ||
287 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
288 | { | |
289 | vcpu->arch.efer = efer; | |
290 | if (!npt_enabled && !(efer & EFER_LMA)) | |
291 | efer &= ~EFER_LME; | |
292 | ||
293 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; | |
294 | } | |
295 | ||
296 | static int is_external_interrupt(u32 info) | |
297 | { | |
298 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
299 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
300 | } | |
301 | ||
302 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
303 | { | |
304 | struct vcpu_svm *svm = to_svm(vcpu); | |
305 | u32 ret = 0; | |
306 | ||
307 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
308 | ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS; | |
309 | return ret & mask; | |
310 | } | |
311 | ||
312 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
313 | { | |
314 | struct vcpu_svm *svm = to_svm(vcpu); | |
315 | ||
316 | if (mask == 0) | |
317 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
318 | else | |
319 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
320 | ||
321 | } | |
322 | ||
323 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
324 | { | |
325 | struct vcpu_svm *svm = to_svm(vcpu); | |
326 | ||
327 | if (svm->vmcb->control.next_rip != 0) | |
328 | svm->next_rip = svm->vmcb->control.next_rip; | |
329 | ||
330 | if (!svm->next_rip) { | |
331 | if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) != | |
332 | EMULATE_DONE) | |
333 | printk(KERN_DEBUG "%s: NOP\n", __func__); | |
334 | return; | |
335 | } | |
336 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) | |
337 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
338 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
339 | ||
340 | kvm_rip_write(vcpu, svm->next_rip); | |
341 | svm_set_interrupt_shadow(vcpu, 0); | |
342 | } | |
343 | ||
344 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, | |
345 | bool has_error_code, u32 error_code, | |
346 | bool reinject) | |
347 | { | |
348 | struct vcpu_svm *svm = to_svm(vcpu); | |
349 | ||
350 | /* | |
351 | * If we are within a nested VM we'd better #VMEXIT and let the guest | |
352 | * handle the exception | |
353 | */ | |
354 | if (!reinject && | |
355 | nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
356 | return; | |
357 | ||
358 | if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) { | |
359 | unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu); | |
360 | ||
361 | /* | |
362 | * For guest debugging where we have to reinject #BP if some | |
363 | * INT3 is guest-owned: | |
364 | * Emulate nRIP by moving RIP forward. Will fail if injection | |
365 | * raises a fault that is not intercepted. Still better than | |
366 | * failing in all cases. | |
367 | */ | |
368 | skip_emulated_instruction(&svm->vcpu); | |
369 | rip = kvm_rip_read(&svm->vcpu); | |
370 | svm->int3_rip = rip + svm->vmcb->save.cs.base; | |
371 | svm->int3_injected = rip - old_rip; | |
372 | } | |
373 | ||
374 | svm->vmcb->control.event_inj = nr | |
375 | | SVM_EVTINJ_VALID | |
376 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
377 | | SVM_EVTINJ_TYPE_EXEPT; | |
378 | svm->vmcb->control.event_inj_err = error_code; | |
379 | } | |
380 | ||
381 | static void svm_init_erratum_383(void) | |
382 | { | |
383 | u32 low, high; | |
384 | int err; | |
385 | u64 val; | |
386 | ||
387 | if (!cpu_has_amd_erratum(amd_erratum_383)) | |
388 | return; | |
389 | ||
390 | /* Use _safe variants to not break nested virtualization */ | |
391 | val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); | |
392 | if (err) | |
393 | return; | |
394 | ||
395 | val |= (1ULL << 47); | |
396 | ||
397 | low = lower_32_bits(val); | |
398 | high = upper_32_bits(val); | |
399 | ||
400 | native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); | |
401 | ||
402 | erratum_383_found = true; | |
403 | } | |
404 | ||
405 | static int has_svm(void) | |
406 | { | |
407 | const char *msg; | |
408 | ||
409 | if (!cpu_has_svm(&msg)) { | |
410 | printk(KERN_INFO "has_svm: %s\n", msg); | |
411 | return 0; | |
412 | } | |
413 | ||
414 | return 1; | |
415 | } | |
416 | ||
417 | static void svm_hardware_disable(void *garbage) | |
418 | { | |
419 | cpu_svm_disable(); | |
420 | } | |
421 | ||
422 | static int svm_hardware_enable(void *garbage) | |
423 | { | |
424 | ||
425 | struct svm_cpu_data *sd; | |
426 | uint64_t efer; | |
427 | struct desc_ptr gdt_descr; | |
428 | struct desc_struct *gdt; | |
429 | int me = raw_smp_processor_id(); | |
430 | ||
431 | rdmsrl(MSR_EFER, efer); | |
432 | if (efer & EFER_SVME) | |
433 | return -EBUSY; | |
434 | ||
435 | if (!has_svm()) { | |
436 | printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n", | |
437 | me); | |
438 | return -EINVAL; | |
439 | } | |
440 | sd = per_cpu(svm_data, me); | |
441 | ||
442 | if (!sd) { | |
443 | printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n", | |
444 | me); | |
445 | return -EINVAL; | |
446 | } | |
447 | ||
448 | sd->asid_generation = 1; | |
449 | sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
450 | sd->next_asid = sd->max_asid + 1; | |
451 | ||
452 | native_store_gdt(&gdt_descr); | |
453 | gdt = (struct desc_struct *)gdt_descr.address; | |
454 | sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); | |
455 | ||
456 | wrmsrl(MSR_EFER, efer | EFER_SVME); | |
457 | ||
458 | wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); | |
459 | ||
460 | svm_init_erratum_383(); | |
461 | ||
462 | return 0; | |
463 | } | |
464 | ||
465 | static void svm_cpu_uninit(int cpu) | |
466 | { | |
467 | struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id()); | |
468 | ||
469 | if (!sd) | |
470 | return; | |
471 | ||
472 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
473 | __free_page(sd->save_area); | |
474 | kfree(sd); | |
475 | } | |
476 | ||
477 | static int svm_cpu_init(int cpu) | |
478 | { | |
479 | struct svm_cpu_data *sd; | |
480 | int r; | |
481 | ||
482 | sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); | |
483 | if (!sd) | |
484 | return -ENOMEM; | |
485 | sd->cpu = cpu; | |
486 | sd->save_area = alloc_page(GFP_KERNEL); | |
487 | r = -ENOMEM; | |
488 | if (!sd->save_area) | |
489 | goto err_1; | |
490 | ||
491 | per_cpu(svm_data, cpu) = sd; | |
492 | ||
493 | return 0; | |
494 | ||
495 | err_1: | |
496 | kfree(sd); | |
497 | return r; | |
498 | ||
499 | } | |
500 | ||
501 | static bool valid_msr_intercept(u32 index) | |
502 | { | |
503 | int i; | |
504 | ||
505 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) | |
506 | if (direct_access_msrs[i].index == index) | |
507 | return true; | |
508 | ||
509 | return false; | |
510 | } | |
511 | ||
512 | static void set_msr_interception(u32 *msrpm, unsigned msr, | |
513 | int read, int write) | |
514 | { | |
515 | u8 bit_read, bit_write; | |
516 | unsigned long tmp; | |
517 | u32 offset; | |
518 | ||
519 | /* | |
520 | * If this warning triggers extend the direct_access_msrs list at the | |
521 | * beginning of the file | |
522 | */ | |
523 | WARN_ON(!valid_msr_intercept(msr)); | |
524 | ||
525 | offset = svm_msrpm_offset(msr); | |
526 | bit_read = 2 * (msr & 0x0f); | |
527 | bit_write = 2 * (msr & 0x0f) + 1; | |
528 | tmp = msrpm[offset]; | |
529 | ||
530 | BUG_ON(offset == MSR_INVALID); | |
531 | ||
532 | read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp); | |
533 | write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp); | |
534 | ||
535 | msrpm[offset] = tmp; | |
536 | } | |
537 | ||
538 | static void svm_vcpu_init_msrpm(u32 *msrpm) | |
539 | { | |
540 | int i; | |
541 | ||
542 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); | |
543 | ||
544 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { | |
545 | if (!direct_access_msrs[i].always) | |
546 | continue; | |
547 | ||
548 | set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); | |
549 | } | |
550 | } | |
551 | ||
552 | static void add_msr_offset(u32 offset) | |
553 | { | |
554 | int i; | |
555 | ||
556 | for (i = 0; i < MSRPM_OFFSETS; ++i) { | |
557 | ||
558 | /* Offset already in list? */ | |
559 | if (msrpm_offsets[i] == offset) | |
560 | return; | |
561 | ||
562 | /* Slot used by another offset? */ | |
563 | if (msrpm_offsets[i] != MSR_INVALID) | |
564 | continue; | |
565 | ||
566 | /* Add offset to list */ | |
567 | msrpm_offsets[i] = offset; | |
568 | ||
569 | return; | |
570 | } | |
571 | ||
572 | /* | |
573 | * If this BUG triggers the msrpm_offsets table has an overflow. Just | |
574 | * increase MSRPM_OFFSETS in this case. | |
575 | */ | |
576 | BUG(); | |
577 | } | |
578 | ||
579 | static void init_msrpm_offsets(void) | |
580 | { | |
581 | int i; | |
582 | ||
583 | memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); | |
584 | ||
585 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { | |
586 | u32 offset; | |
587 | ||
588 | offset = svm_msrpm_offset(direct_access_msrs[i].index); | |
589 | BUG_ON(offset == MSR_INVALID); | |
590 | ||
591 | add_msr_offset(offset); | |
592 | } | |
593 | } | |
594 | ||
595 | static void svm_enable_lbrv(struct vcpu_svm *svm) | |
596 | { | |
597 | u32 *msrpm = svm->msrpm; | |
598 | ||
599 | svm->vmcb->control.lbr_ctl = 1; | |
600 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
601 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
602 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
603 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
604 | } | |
605 | ||
606 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
607 | { | |
608 | u32 *msrpm = svm->msrpm; | |
609 | ||
610 | svm->vmcb->control.lbr_ctl = 0; | |
611 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
612 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
613 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
614 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
615 | } | |
616 | ||
617 | static __init int svm_hardware_setup(void) | |
618 | { | |
619 | int cpu; | |
620 | struct page *iopm_pages; | |
621 | void *iopm_va; | |
622 | int r; | |
623 | ||
624 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); | |
625 | ||
626 | if (!iopm_pages) | |
627 | return -ENOMEM; | |
628 | ||
629 | iopm_va = page_address(iopm_pages); | |
630 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
631 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; | |
632 | ||
633 | init_msrpm_offsets(); | |
634 | ||
635 | if (boot_cpu_has(X86_FEATURE_NX)) | |
636 | kvm_enable_efer_bits(EFER_NX); | |
637 | ||
638 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) | |
639 | kvm_enable_efer_bits(EFER_FFXSR); | |
640 | ||
641 | if (nested) { | |
642 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
643 | kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE); | |
644 | } | |
645 | ||
646 | for_each_possible_cpu(cpu) { | |
647 | r = svm_cpu_init(cpu); | |
648 | if (r) | |
649 | goto err; | |
650 | } | |
651 | ||
652 | svm_features = cpuid_edx(SVM_CPUID_FUNC); | |
653 | ||
654 | if (!svm_has(SVM_FEATURE_NPT)) | |
655 | npt_enabled = false; | |
656 | ||
657 | if (npt_enabled && !npt) { | |
658 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
659 | npt_enabled = false; | |
660 | } | |
661 | ||
662 | if (npt_enabled) { | |
663 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); | |
664 | kvm_enable_tdp(); | |
665 | } else | |
666 | kvm_disable_tdp(); | |
667 | ||
668 | return 0; | |
669 | ||
670 | err: | |
671 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); | |
672 | iopm_base = 0; | |
673 | return r; | |
674 | } | |
675 | ||
676 | static __exit void svm_hardware_unsetup(void) | |
677 | { | |
678 | int cpu; | |
679 | ||
680 | for_each_possible_cpu(cpu) | |
681 | svm_cpu_uninit(cpu); | |
682 | ||
683 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); | |
684 | iopm_base = 0; | |
685 | } | |
686 | ||
687 | static void init_seg(struct vmcb_seg *seg) | |
688 | { | |
689 | seg->selector = 0; | |
690 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
691 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ | |
692 | seg->limit = 0xffff; | |
693 | seg->base = 0; | |
694 | } | |
695 | ||
696 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
697 | { | |
698 | seg->selector = 0; | |
699 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
700 | seg->limit = 0xffff; | |
701 | seg->base = 0; | |
702 | } | |
703 | ||
704 | static void init_vmcb(struct vcpu_svm *svm) | |
705 | { | |
706 | struct vmcb_control_area *control = &svm->vmcb->control; | |
707 | struct vmcb_save_area *save = &svm->vmcb->save; | |
708 | ||
709 | svm->vcpu.fpu_active = 1; | |
710 | ||
711 | control->intercept_cr_read = INTERCEPT_CR0_MASK | | |
712 | INTERCEPT_CR3_MASK | | |
713 | INTERCEPT_CR4_MASK; | |
714 | ||
715 | control->intercept_cr_write = INTERCEPT_CR0_MASK | | |
716 | INTERCEPT_CR3_MASK | | |
717 | INTERCEPT_CR4_MASK | | |
718 | INTERCEPT_CR8_MASK; | |
719 | ||
720 | control->intercept_dr_read = INTERCEPT_DR0_MASK | | |
721 | INTERCEPT_DR1_MASK | | |
722 | INTERCEPT_DR2_MASK | | |
723 | INTERCEPT_DR3_MASK | | |
724 | INTERCEPT_DR4_MASK | | |
725 | INTERCEPT_DR5_MASK | | |
726 | INTERCEPT_DR6_MASK | | |
727 | INTERCEPT_DR7_MASK; | |
728 | ||
729 | control->intercept_dr_write = INTERCEPT_DR0_MASK | | |
730 | INTERCEPT_DR1_MASK | | |
731 | INTERCEPT_DR2_MASK | | |
732 | INTERCEPT_DR3_MASK | | |
733 | INTERCEPT_DR4_MASK | | |
734 | INTERCEPT_DR5_MASK | | |
735 | INTERCEPT_DR6_MASK | | |
736 | INTERCEPT_DR7_MASK; | |
737 | ||
738 | control->intercept_exceptions = (1 << PF_VECTOR) | | |
739 | (1 << UD_VECTOR) | | |
740 | (1 << MC_VECTOR); | |
741 | ||
742 | ||
743 | control->intercept = (1ULL << INTERCEPT_INTR) | | |
744 | (1ULL << INTERCEPT_NMI) | | |
745 | (1ULL << INTERCEPT_SMI) | | |
746 | (1ULL << INTERCEPT_SELECTIVE_CR0) | | |
747 | (1ULL << INTERCEPT_CPUID) | | |
748 | (1ULL << INTERCEPT_INVD) | | |
749 | (1ULL << INTERCEPT_HLT) | | |
750 | (1ULL << INTERCEPT_INVLPG) | | |
751 | (1ULL << INTERCEPT_INVLPGA) | | |
752 | (1ULL << INTERCEPT_IOIO_PROT) | | |
753 | (1ULL << INTERCEPT_MSR_PROT) | | |
754 | (1ULL << INTERCEPT_TASK_SWITCH) | | |
755 | (1ULL << INTERCEPT_SHUTDOWN) | | |
756 | (1ULL << INTERCEPT_VMRUN) | | |
757 | (1ULL << INTERCEPT_VMMCALL) | | |
758 | (1ULL << INTERCEPT_VMLOAD) | | |
759 | (1ULL << INTERCEPT_VMSAVE) | | |
760 | (1ULL << INTERCEPT_STGI) | | |
761 | (1ULL << INTERCEPT_CLGI) | | |
762 | (1ULL << INTERCEPT_SKINIT) | | |
763 | (1ULL << INTERCEPT_WBINVD) | | |
764 | (1ULL << INTERCEPT_MONITOR) | | |
765 | (1ULL << INTERCEPT_MWAIT); | |
766 | ||
767 | control->iopm_base_pa = iopm_base; | |
768 | control->msrpm_base_pa = __pa(svm->msrpm); | |
769 | control->int_ctl = V_INTR_MASKING_MASK; | |
770 | ||
771 | init_seg(&save->es); | |
772 | init_seg(&save->ss); | |
773 | init_seg(&save->ds); | |
774 | init_seg(&save->fs); | |
775 | init_seg(&save->gs); | |
776 | ||
777 | save->cs.selector = 0xf000; | |
778 | /* Executable/Readable Code Segment */ | |
779 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
780 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
781 | save->cs.limit = 0xffff; | |
782 | /* | |
783 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
784 | * be consistent with it. | |
785 | * | |
786 | * Replace when we have real mode working for vmx. | |
787 | */ | |
788 | save->cs.base = 0xf0000; | |
789 | ||
790 | save->gdtr.limit = 0xffff; | |
791 | save->idtr.limit = 0xffff; | |
792 | ||
793 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
794 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
795 | ||
796 | save->efer = EFER_SVME; | |
797 | save->dr6 = 0xffff0ff0; | |
798 | save->dr7 = 0x400; | |
799 | save->rflags = 2; | |
800 | save->rip = 0x0000fff0; | |
801 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; | |
802 | ||
803 | /* | |
804 | * This is the guest-visible cr0 value. | |
805 | * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. | |
806 | */ | |
807 | svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; | |
808 | (void)kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0); | |
809 | ||
810 | save->cr4 = X86_CR4_PAE; | |
811 | /* rdx = ?? */ | |
812 | ||
813 | if (npt_enabled) { | |
814 | /* Setup VMCB for Nested Paging */ | |
815 | control->nested_ctl = 1; | |
816 | control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) | | |
817 | (1ULL << INTERCEPT_INVLPG)); | |
818 | control->intercept_exceptions &= ~(1 << PF_VECTOR); | |
819 | control->intercept_cr_read &= ~INTERCEPT_CR3_MASK; | |
820 | control->intercept_cr_write &= ~INTERCEPT_CR3_MASK; | |
821 | save->g_pat = 0x0007040600070406ULL; | |
822 | save->cr3 = 0; | |
823 | save->cr4 = 0; | |
824 | } | |
825 | force_new_asid(&svm->vcpu); | |
826 | ||
827 | svm->nested.vmcb = 0; | |
828 | svm->vcpu.arch.hflags = 0; | |
829 | ||
830 | if (svm_has(SVM_FEATURE_PAUSE_FILTER)) { | |
831 | control->pause_filter_count = 3000; | |
832 | control->intercept |= (1ULL << INTERCEPT_PAUSE); | |
833 | } | |
834 | ||
835 | enable_gif(svm); | |
836 | } | |
837 | ||
838 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) | |
839 | { | |
840 | struct vcpu_svm *svm = to_svm(vcpu); | |
841 | ||
842 | init_vmcb(svm); | |
843 | ||
844 | if (!kvm_vcpu_is_bsp(vcpu)) { | |
845 | kvm_rip_write(vcpu, 0); | |
846 | svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12; | |
847 | svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8; | |
848 | } | |
849 | vcpu->arch.regs_avail = ~0; | |
850 | vcpu->arch.regs_dirty = ~0; | |
851 | ||
852 | return 0; | |
853 | } | |
854 | ||
855 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) | |
856 | { | |
857 | struct vcpu_svm *svm; | |
858 | struct page *page; | |
859 | struct page *msrpm_pages; | |
860 | struct page *hsave_page; | |
861 | struct page *nested_msrpm_pages; | |
862 | int err; | |
863 | ||
864 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); | |
865 | if (!svm) { | |
866 | err = -ENOMEM; | |
867 | goto out; | |
868 | } | |
869 | ||
870 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
871 | if (err) | |
872 | goto free_svm; | |
873 | ||
874 | err = -ENOMEM; | |
875 | page = alloc_page(GFP_KERNEL); | |
876 | if (!page) | |
877 | goto uninit; | |
878 | ||
879 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
880 | if (!msrpm_pages) | |
881 | goto free_page1; | |
882 | ||
883 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
884 | if (!nested_msrpm_pages) | |
885 | goto free_page2; | |
886 | ||
887 | hsave_page = alloc_page(GFP_KERNEL); | |
888 | if (!hsave_page) | |
889 | goto free_page3; | |
890 | ||
891 | svm->nested.hsave = page_address(hsave_page); | |
892 | ||
893 | svm->msrpm = page_address(msrpm_pages); | |
894 | svm_vcpu_init_msrpm(svm->msrpm); | |
895 | ||
896 | svm->nested.msrpm = page_address(nested_msrpm_pages); | |
897 | svm_vcpu_init_msrpm(svm->nested.msrpm); | |
898 | ||
899 | svm->vmcb = page_address(page); | |
900 | clear_page(svm->vmcb); | |
901 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
902 | svm->asid_generation = 0; | |
903 | init_vmcb(svm); | |
904 | svm->vmcb->control.tsc_offset = 0-native_read_tsc(); | |
905 | ||
906 | err = fx_init(&svm->vcpu); | |
907 | if (err) | |
908 | goto free_page4; | |
909 | ||
910 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; | |
911 | if (kvm_vcpu_is_bsp(&svm->vcpu)) | |
912 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; | |
913 | ||
914 | return &svm->vcpu; | |
915 | ||
916 | free_page4: | |
917 | __free_page(hsave_page); | |
918 | free_page3: | |
919 | __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER); | |
920 | free_page2: | |
921 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
922 | free_page1: | |
923 | __free_page(page); | |
924 | uninit: | |
925 | kvm_vcpu_uninit(&svm->vcpu); | |
926 | free_svm: | |
927 | kmem_cache_free(kvm_vcpu_cache, svm); | |
928 | out: | |
929 | return ERR_PTR(err); | |
930 | } | |
931 | ||
932 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
933 | { | |
934 | struct vcpu_svm *svm = to_svm(vcpu); | |
935 | ||
936 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); | |
937 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); | |
938 | __free_page(virt_to_page(svm->nested.hsave)); | |
939 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
940 | kvm_vcpu_uninit(vcpu); | |
941 | kmem_cache_free(kvm_vcpu_cache, svm); | |
942 | } | |
943 | ||
944 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) | |
945 | { | |
946 | struct vcpu_svm *svm = to_svm(vcpu); | |
947 | int i; | |
948 | ||
949 | if (unlikely(cpu != vcpu->cpu)) { | |
950 | u64 delta; | |
951 | ||
952 | if (check_tsc_unstable()) { | |
953 | /* | |
954 | * Make sure that the guest sees a monotonically | |
955 | * increasing TSC. | |
956 | */ | |
957 | delta = vcpu->arch.host_tsc - native_read_tsc(); | |
958 | svm->vmcb->control.tsc_offset += delta; | |
959 | if (is_nested(svm)) | |
960 | svm->nested.hsave->control.tsc_offset += delta; | |
961 | } | |
962 | vcpu->cpu = cpu; | |
963 | kvm_migrate_timers(vcpu); | |
964 | svm->asid_generation = 0; | |
965 | } | |
966 | ||
967 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
968 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); | |
969 | } | |
970 | ||
971 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
972 | { | |
973 | struct vcpu_svm *svm = to_svm(vcpu); | |
974 | int i; | |
975 | ||
976 | ++vcpu->stat.host_state_reload; | |
977 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
978 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); | |
979 | ||
980 | vcpu->arch.host_tsc = native_read_tsc(); | |
981 | } | |
982 | ||
983 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) | |
984 | { | |
985 | return to_svm(vcpu)->vmcb->save.rflags; | |
986 | } | |
987 | ||
988 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
989 | { | |
990 | to_svm(vcpu)->vmcb->save.rflags = rflags; | |
991 | } | |
992 | ||
993 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) | |
994 | { | |
995 | switch (reg) { | |
996 | case VCPU_EXREG_PDPTR: | |
997 | BUG_ON(!npt_enabled); | |
998 | load_pdptrs(vcpu, vcpu->arch.cr3); | |
999 | break; | |
1000 | default: | |
1001 | BUG(); | |
1002 | } | |
1003 | } | |
1004 | ||
1005 | static void svm_set_vintr(struct vcpu_svm *svm) | |
1006 | { | |
1007 | svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR; | |
1008 | } | |
1009 | ||
1010 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
1011 | { | |
1012 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR); | |
1013 | } | |
1014 | ||
1015 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) | |
1016 | { | |
1017 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
1018 | ||
1019 | switch (seg) { | |
1020 | case VCPU_SREG_CS: return &save->cs; | |
1021 | case VCPU_SREG_DS: return &save->ds; | |
1022 | case VCPU_SREG_ES: return &save->es; | |
1023 | case VCPU_SREG_FS: return &save->fs; | |
1024 | case VCPU_SREG_GS: return &save->gs; | |
1025 | case VCPU_SREG_SS: return &save->ss; | |
1026 | case VCPU_SREG_TR: return &save->tr; | |
1027 | case VCPU_SREG_LDTR: return &save->ldtr; | |
1028 | } | |
1029 | BUG(); | |
1030 | return NULL; | |
1031 | } | |
1032 | ||
1033 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
1034 | { | |
1035 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1036 | ||
1037 | return s->base; | |
1038 | } | |
1039 | ||
1040 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
1041 | struct kvm_segment *var, int seg) | |
1042 | { | |
1043 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1044 | ||
1045 | var->base = s->base; | |
1046 | var->limit = s->limit; | |
1047 | var->selector = s->selector; | |
1048 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
1049 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
1050 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
1051 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
1052 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
1053 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
1054 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
1055 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
1056 | ||
1057 | /* | |
1058 | * AMD's VMCB does not have an explicit unusable field, so emulate it | |
1059 | * for cross vendor migration purposes by "not present" | |
1060 | */ | |
1061 | var->unusable = !var->present || (var->type == 0); | |
1062 | ||
1063 | switch (seg) { | |
1064 | case VCPU_SREG_CS: | |
1065 | /* | |
1066 | * SVM always stores 0 for the 'G' bit in the CS selector in | |
1067 | * the VMCB on a VMEXIT. This hurts cross-vendor migration: | |
1068 | * Intel's VMENTRY has a check on the 'G' bit. | |
1069 | */ | |
1070 | var->g = s->limit > 0xfffff; | |
1071 | break; | |
1072 | case VCPU_SREG_TR: | |
1073 | /* | |
1074 | * Work around a bug where the busy flag in the tr selector | |
1075 | * isn't exposed | |
1076 | */ | |
1077 | var->type |= 0x2; | |
1078 | break; | |
1079 | case VCPU_SREG_DS: | |
1080 | case VCPU_SREG_ES: | |
1081 | case VCPU_SREG_FS: | |
1082 | case VCPU_SREG_GS: | |
1083 | /* | |
1084 | * The accessed bit must always be set in the segment | |
1085 | * descriptor cache, although it can be cleared in the | |
1086 | * descriptor, the cached bit always remains at 1. Since | |
1087 | * Intel has a check on this, set it here to support | |
1088 | * cross-vendor migration. | |
1089 | */ | |
1090 | if (!var->unusable) | |
1091 | var->type |= 0x1; | |
1092 | break; | |
1093 | case VCPU_SREG_SS: | |
1094 | /* | |
1095 | * On AMD CPUs sometimes the DB bit in the segment | |
1096 | * descriptor is left as 1, although the whole segment has | |
1097 | * been made unusable. Clear it here to pass an Intel VMX | |
1098 | * entry check when cross vendor migrating. | |
1099 | */ | |
1100 | if (var->unusable) | |
1101 | var->db = 0; | |
1102 | break; | |
1103 | } | |
1104 | } | |
1105 | ||
1106 | static int svm_get_cpl(struct kvm_vcpu *vcpu) | |
1107 | { | |
1108 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
1109 | ||
1110 | return save->cpl; | |
1111 | } | |
1112 | ||
1113 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) | |
1114 | { | |
1115 | struct vcpu_svm *svm = to_svm(vcpu); | |
1116 | ||
1117 | dt->size = svm->vmcb->save.idtr.limit; | |
1118 | dt->address = svm->vmcb->save.idtr.base; | |
1119 | } | |
1120 | ||
1121 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) | |
1122 | { | |
1123 | struct vcpu_svm *svm = to_svm(vcpu); | |
1124 | ||
1125 | svm->vmcb->save.idtr.limit = dt->size; | |
1126 | svm->vmcb->save.idtr.base = dt->address ; | |
1127 | } | |
1128 | ||
1129 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) | |
1130 | { | |
1131 | struct vcpu_svm *svm = to_svm(vcpu); | |
1132 | ||
1133 | dt->size = svm->vmcb->save.gdtr.limit; | |
1134 | dt->address = svm->vmcb->save.gdtr.base; | |
1135 | } | |
1136 | ||
1137 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) | |
1138 | { | |
1139 | struct vcpu_svm *svm = to_svm(vcpu); | |
1140 | ||
1141 | svm->vmcb->save.gdtr.limit = dt->size; | |
1142 | svm->vmcb->save.gdtr.base = dt->address ; | |
1143 | } | |
1144 | ||
1145 | static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) | |
1146 | { | |
1147 | } | |
1148 | ||
1149 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) | |
1150 | { | |
1151 | } | |
1152 | ||
1153 | static void update_cr0_intercept(struct vcpu_svm *svm) | |
1154 | { | |
1155 | struct vmcb *vmcb = svm->vmcb; | |
1156 | ulong gcr0 = svm->vcpu.arch.cr0; | |
1157 | u64 *hcr0 = &svm->vmcb->save.cr0; | |
1158 | ||
1159 | if (!svm->vcpu.fpu_active) | |
1160 | *hcr0 |= SVM_CR0_SELECTIVE_MASK; | |
1161 | else | |
1162 | *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK) | |
1163 | | (gcr0 & SVM_CR0_SELECTIVE_MASK); | |
1164 | ||
1165 | ||
1166 | if (gcr0 == *hcr0 && svm->vcpu.fpu_active) { | |
1167 | vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK; | |
1168 | vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK; | |
1169 | if (is_nested(svm)) { | |
1170 | struct vmcb *hsave = svm->nested.hsave; | |
1171 | ||
1172 | hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK; | |
1173 | hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK; | |
1174 | vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read; | |
1175 | vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write; | |
1176 | } | |
1177 | } else { | |
1178 | svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK; | |
1179 | svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK; | |
1180 | if (is_nested(svm)) { | |
1181 | struct vmcb *hsave = svm->nested.hsave; | |
1182 | ||
1183 | hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK; | |
1184 | hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK; | |
1185 | } | |
1186 | } | |
1187 | } | |
1188 | ||
1189 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) | |
1190 | { | |
1191 | struct vcpu_svm *svm = to_svm(vcpu); | |
1192 | ||
1193 | if (is_nested(svm)) { | |
1194 | /* | |
1195 | * We are here because we run in nested mode, the host kvm | |
1196 | * intercepts cr0 writes but the l1 hypervisor does not. | |
1197 | * But the L1 hypervisor may intercept selective cr0 writes. | |
1198 | * This needs to be checked here. | |
1199 | */ | |
1200 | unsigned long old, new; | |
1201 | ||
1202 | /* Remove bits that would trigger a real cr0 write intercept */ | |
1203 | old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK; | |
1204 | new = cr0 & SVM_CR0_SELECTIVE_MASK; | |
1205 | ||
1206 | if (old == new) { | |
1207 | /* cr0 write with ts and mp unchanged */ | |
1208 | svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
1209 | if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) | |
1210 | return; | |
1211 | } | |
1212 | } | |
1213 | ||
1214 | #ifdef CONFIG_X86_64 | |
1215 | if (vcpu->arch.efer & EFER_LME) { | |
1216 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
1217 | vcpu->arch.efer |= EFER_LMA; | |
1218 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; | |
1219 | } | |
1220 | ||
1221 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { | |
1222 | vcpu->arch.efer &= ~EFER_LMA; | |
1223 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); | |
1224 | } | |
1225 | } | |
1226 | #endif | |
1227 | vcpu->arch.cr0 = cr0; | |
1228 | ||
1229 | if (!npt_enabled) | |
1230 | cr0 |= X86_CR0_PG | X86_CR0_WP; | |
1231 | ||
1232 | if (!vcpu->fpu_active) | |
1233 | cr0 |= X86_CR0_TS; | |
1234 | /* | |
1235 | * re-enable caching here because the QEMU bios | |
1236 | * does not do it - this results in some delay at | |
1237 | * reboot | |
1238 | */ | |
1239 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
1240 | svm->vmcb->save.cr0 = cr0; | |
1241 | update_cr0_intercept(svm); | |
1242 | } | |
1243 | ||
1244 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1245 | { | |
1246 | unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE; | |
1247 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; | |
1248 | ||
1249 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) | |
1250 | force_new_asid(vcpu); | |
1251 | ||
1252 | vcpu->arch.cr4 = cr4; | |
1253 | if (!npt_enabled) | |
1254 | cr4 |= X86_CR4_PAE; | |
1255 | cr4 |= host_cr4_mce; | |
1256 | to_svm(vcpu)->vmcb->save.cr4 = cr4; | |
1257 | } | |
1258 | ||
1259 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
1260 | struct kvm_segment *var, int seg) | |
1261 | { | |
1262 | struct vcpu_svm *svm = to_svm(vcpu); | |
1263 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1264 | ||
1265 | s->base = var->base; | |
1266 | s->limit = var->limit; | |
1267 | s->selector = var->selector; | |
1268 | if (var->unusable) | |
1269 | s->attrib = 0; | |
1270 | else { | |
1271 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
1272 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
1273 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
1274 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
1275 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
1276 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
1277 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
1278 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
1279 | } | |
1280 | if (seg == VCPU_SREG_CS) | |
1281 | svm->vmcb->save.cpl | |
1282 | = (svm->vmcb->save.cs.attrib | |
1283 | >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
1284 | ||
1285 | } | |
1286 | ||
1287 | static void update_db_intercept(struct kvm_vcpu *vcpu) | |
1288 | { | |
1289 | struct vcpu_svm *svm = to_svm(vcpu); | |
1290 | ||
1291 | svm->vmcb->control.intercept_exceptions &= | |
1292 | ~((1 << DB_VECTOR) | (1 << BP_VECTOR)); | |
1293 | ||
1294 | if (svm->nmi_singlestep) | |
1295 | svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR); | |
1296 | ||
1297 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { | |
1298 | if (vcpu->guest_debug & | |
1299 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
1300 | svm->vmcb->control.intercept_exceptions |= | |
1301 | 1 << DB_VECTOR; | |
1302 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) | |
1303 | svm->vmcb->control.intercept_exceptions |= | |
1304 | 1 << BP_VECTOR; | |
1305 | } else | |
1306 | vcpu->guest_debug = 0; | |
1307 | } | |
1308 | ||
1309 | static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg) | |
1310 | { | |
1311 | struct vcpu_svm *svm = to_svm(vcpu); | |
1312 | ||
1313 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
1314 | svm->vmcb->save.dr7 = dbg->arch.debugreg[7]; | |
1315 | else | |
1316 | svm->vmcb->save.dr7 = vcpu->arch.dr7; | |
1317 | ||
1318 | update_db_intercept(vcpu); | |
1319 | } | |
1320 | ||
1321 | static void load_host_msrs(struct kvm_vcpu *vcpu) | |
1322 | { | |
1323 | #ifdef CONFIG_X86_64 | |
1324 | wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); | |
1325 | #endif | |
1326 | } | |
1327 | ||
1328 | static void save_host_msrs(struct kvm_vcpu *vcpu) | |
1329 | { | |
1330 | #ifdef CONFIG_X86_64 | |
1331 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); | |
1332 | #endif | |
1333 | } | |
1334 | ||
1335 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) | |
1336 | { | |
1337 | if (sd->next_asid > sd->max_asid) { | |
1338 | ++sd->asid_generation; | |
1339 | sd->next_asid = 1; | |
1340 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; | |
1341 | } | |
1342 | ||
1343 | svm->asid_generation = sd->asid_generation; | |
1344 | svm->vmcb->control.asid = sd->next_asid++; | |
1345 | } | |
1346 | ||
1347 | static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value) | |
1348 | { | |
1349 | struct vcpu_svm *svm = to_svm(vcpu); | |
1350 | ||
1351 | svm->vmcb->save.dr7 = value; | |
1352 | } | |
1353 | ||
1354 | static int pf_interception(struct vcpu_svm *svm) | |
1355 | { | |
1356 | u64 fault_address; | |
1357 | u32 error_code; | |
1358 | ||
1359 | fault_address = svm->vmcb->control.exit_info_2; | |
1360 | error_code = svm->vmcb->control.exit_info_1; | |
1361 | ||
1362 | trace_kvm_page_fault(fault_address, error_code); | |
1363 | if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu)) | |
1364 | kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address); | |
1365 | return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code); | |
1366 | } | |
1367 | ||
1368 | static int db_interception(struct vcpu_svm *svm) | |
1369 | { | |
1370 | struct kvm_run *kvm_run = svm->vcpu.run; | |
1371 | ||
1372 | if (!(svm->vcpu.guest_debug & | |
1373 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && | |
1374 | !svm->nmi_singlestep) { | |
1375 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); | |
1376 | return 1; | |
1377 | } | |
1378 | ||
1379 | if (svm->nmi_singlestep) { | |
1380 | svm->nmi_singlestep = false; | |
1381 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) | |
1382 | svm->vmcb->save.rflags &= | |
1383 | ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
1384 | update_db_intercept(&svm->vcpu); | |
1385 | } | |
1386 | ||
1387 | if (svm->vcpu.guest_debug & | |
1388 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) { | |
1389 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
1390 | kvm_run->debug.arch.pc = | |
1391 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1392 | kvm_run->debug.arch.exception = DB_VECTOR; | |
1393 | return 0; | |
1394 | } | |
1395 | ||
1396 | return 1; | |
1397 | } | |
1398 | ||
1399 | static int bp_interception(struct vcpu_svm *svm) | |
1400 | { | |
1401 | struct kvm_run *kvm_run = svm->vcpu.run; | |
1402 | ||
1403 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
1404 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1405 | kvm_run->debug.arch.exception = BP_VECTOR; | |
1406 | return 0; | |
1407 | } | |
1408 | ||
1409 | static int ud_interception(struct vcpu_svm *svm) | |
1410 | { | |
1411 | int er; | |
1412 | ||
1413 | er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD); | |
1414 | if (er != EMULATE_DONE) | |
1415 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
1416 | return 1; | |
1417 | } | |
1418 | ||
1419 | static void svm_fpu_activate(struct kvm_vcpu *vcpu) | |
1420 | { | |
1421 | struct vcpu_svm *svm = to_svm(vcpu); | |
1422 | u32 excp; | |
1423 | ||
1424 | if (is_nested(svm)) { | |
1425 | u32 h_excp, n_excp; | |
1426 | ||
1427 | h_excp = svm->nested.hsave->control.intercept_exceptions; | |
1428 | n_excp = svm->nested.intercept_exceptions; | |
1429 | h_excp &= ~(1 << NM_VECTOR); | |
1430 | excp = h_excp | n_excp; | |
1431 | } else { | |
1432 | excp = svm->vmcb->control.intercept_exceptions; | |
1433 | excp &= ~(1 << NM_VECTOR); | |
1434 | } | |
1435 | ||
1436 | svm->vmcb->control.intercept_exceptions = excp; | |
1437 | ||
1438 | svm->vcpu.fpu_active = 1; | |
1439 | update_cr0_intercept(svm); | |
1440 | } | |
1441 | ||
1442 | static int nm_interception(struct vcpu_svm *svm) | |
1443 | { | |
1444 | svm_fpu_activate(&svm->vcpu); | |
1445 | return 1; | |
1446 | } | |
1447 | ||
1448 | static bool is_erratum_383(void) | |
1449 | { | |
1450 | int err, i; | |
1451 | u64 value; | |
1452 | ||
1453 | if (!erratum_383_found) | |
1454 | return false; | |
1455 | ||
1456 | value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); | |
1457 | if (err) | |
1458 | return false; | |
1459 | ||
1460 | /* Bit 62 may or may not be set for this mce */ | |
1461 | value &= ~(1ULL << 62); | |
1462 | ||
1463 | if (value != 0xb600000000010015ULL) | |
1464 | return false; | |
1465 | ||
1466 | /* Clear MCi_STATUS registers */ | |
1467 | for (i = 0; i < 6; ++i) | |
1468 | native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); | |
1469 | ||
1470 | value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); | |
1471 | if (!err) { | |
1472 | u32 low, high; | |
1473 | ||
1474 | value &= ~(1ULL << 2); | |
1475 | low = lower_32_bits(value); | |
1476 | high = upper_32_bits(value); | |
1477 | ||
1478 | native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); | |
1479 | } | |
1480 | ||
1481 | /* Flush tlb to evict multi-match entries */ | |
1482 | __flush_tlb_all(); | |
1483 | ||
1484 | return true; | |
1485 | } | |
1486 | ||
1487 | static void svm_handle_mce(struct vcpu_svm *svm) | |
1488 | { | |
1489 | if (is_erratum_383()) { | |
1490 | /* | |
1491 | * Erratum 383 triggered. Guest state is corrupt so kill the | |
1492 | * guest. | |
1493 | */ | |
1494 | pr_err("KVM: Guest triggered AMD Erratum 383\n"); | |
1495 | ||
1496 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu); | |
1497 | ||
1498 | return; | |
1499 | } | |
1500 | ||
1501 | /* | |
1502 | * On an #MC intercept the MCE handler is not called automatically in | |
1503 | * the host. So do it by hand here. | |
1504 | */ | |
1505 | asm volatile ( | |
1506 | "int $0x12\n"); | |
1507 | /* not sure if we ever come back to this point */ | |
1508 | ||
1509 | return; | |
1510 | } | |
1511 | ||
1512 | static int mc_interception(struct vcpu_svm *svm) | |
1513 | { | |
1514 | return 1; | |
1515 | } | |
1516 | ||
1517 | static int shutdown_interception(struct vcpu_svm *svm) | |
1518 | { | |
1519 | struct kvm_run *kvm_run = svm->vcpu.run; | |
1520 | ||
1521 | /* | |
1522 | * VMCB is undefined after a SHUTDOWN intercept | |
1523 | * so reinitialize it. | |
1524 | */ | |
1525 | clear_page(svm->vmcb); | |
1526 | init_vmcb(svm); | |
1527 | ||
1528 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1529 | return 0; | |
1530 | } | |
1531 | ||
1532 | static int io_interception(struct vcpu_svm *svm) | |
1533 | { | |
1534 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
1535 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ | |
1536 | int size, in, string; | |
1537 | unsigned port; | |
1538 | ||
1539 | ++svm->vcpu.stat.io_exits; | |
1540 | string = (io_info & SVM_IOIO_STR_MASK) != 0; | |
1541 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; | |
1542 | if (string || in) | |
1543 | return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE; | |
1544 | ||
1545 | port = io_info >> 16; | |
1546 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
1547 | svm->next_rip = svm->vmcb->control.exit_info_2; | |
1548 | skip_emulated_instruction(&svm->vcpu); | |
1549 | ||
1550 | return kvm_fast_pio_out(vcpu, size, port); | |
1551 | } | |
1552 | ||
1553 | static int nmi_interception(struct vcpu_svm *svm) | |
1554 | { | |
1555 | return 1; | |
1556 | } | |
1557 | ||
1558 | static int intr_interception(struct vcpu_svm *svm) | |
1559 | { | |
1560 | ++svm->vcpu.stat.irq_exits; | |
1561 | return 1; | |
1562 | } | |
1563 | ||
1564 | static int nop_on_interception(struct vcpu_svm *svm) | |
1565 | { | |
1566 | return 1; | |
1567 | } | |
1568 | ||
1569 | static int halt_interception(struct vcpu_svm *svm) | |
1570 | { | |
1571 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; | |
1572 | skip_emulated_instruction(&svm->vcpu); | |
1573 | return kvm_emulate_halt(&svm->vcpu); | |
1574 | } | |
1575 | ||
1576 | static int vmmcall_interception(struct vcpu_svm *svm) | |
1577 | { | |
1578 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1579 | skip_emulated_instruction(&svm->vcpu); | |
1580 | kvm_emulate_hypercall(&svm->vcpu); | |
1581 | return 1; | |
1582 | } | |
1583 | ||
1584 | static int nested_svm_check_permissions(struct vcpu_svm *svm) | |
1585 | { | |
1586 | if (!(svm->vcpu.arch.efer & EFER_SVME) | |
1587 | || !is_paging(&svm->vcpu)) { | |
1588 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
1589 | return 1; | |
1590 | } | |
1591 | ||
1592 | if (svm->vmcb->save.cpl) { | |
1593 | kvm_inject_gp(&svm->vcpu, 0); | |
1594 | return 1; | |
1595 | } | |
1596 | ||
1597 | return 0; | |
1598 | } | |
1599 | ||
1600 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, | |
1601 | bool has_error_code, u32 error_code) | |
1602 | { | |
1603 | int vmexit; | |
1604 | ||
1605 | if (!is_nested(svm)) | |
1606 | return 0; | |
1607 | ||
1608 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; | |
1609 | svm->vmcb->control.exit_code_hi = 0; | |
1610 | svm->vmcb->control.exit_info_1 = error_code; | |
1611 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
1612 | ||
1613 | vmexit = nested_svm_intercept(svm); | |
1614 | if (vmexit == NESTED_EXIT_DONE) | |
1615 | svm->nested.exit_required = true; | |
1616 | ||
1617 | return vmexit; | |
1618 | } | |
1619 | ||
1620 | /* This function returns true if it is save to enable the irq window */ | |
1621 | static inline bool nested_svm_intr(struct vcpu_svm *svm) | |
1622 | { | |
1623 | if (!is_nested(svm)) | |
1624 | return true; | |
1625 | ||
1626 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
1627 | return true; | |
1628 | ||
1629 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) | |
1630 | return false; | |
1631 | ||
1632 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; | |
1633 | svm->vmcb->control.exit_info_1 = 0; | |
1634 | svm->vmcb->control.exit_info_2 = 0; | |
1635 | ||
1636 | if (svm->nested.intercept & 1ULL) { | |
1637 | /* | |
1638 | * The #vmexit can't be emulated here directly because this | |
1639 | * code path runs with irqs and preemtion disabled. A | |
1640 | * #vmexit emulation might sleep. Only signal request for | |
1641 | * the #vmexit here. | |
1642 | */ | |
1643 | svm->nested.exit_required = true; | |
1644 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); | |
1645 | return false; | |
1646 | } | |
1647 | ||
1648 | return true; | |
1649 | } | |
1650 | ||
1651 | /* This function returns true if it is save to enable the nmi window */ | |
1652 | static inline bool nested_svm_nmi(struct vcpu_svm *svm) | |
1653 | { | |
1654 | if (!is_nested(svm)) | |
1655 | return true; | |
1656 | ||
1657 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI))) | |
1658 | return true; | |
1659 | ||
1660 | svm->vmcb->control.exit_code = SVM_EXIT_NMI; | |
1661 | svm->nested.exit_required = true; | |
1662 | ||
1663 | return false; | |
1664 | } | |
1665 | ||
1666 | static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page) | |
1667 | { | |
1668 | struct page *page; | |
1669 | ||
1670 | might_sleep(); | |
1671 | ||
1672 | page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT); | |
1673 | if (is_error_page(page)) | |
1674 | goto error; | |
1675 | ||
1676 | *_page = page; | |
1677 | ||
1678 | return kmap(page); | |
1679 | ||
1680 | error: | |
1681 | kvm_release_page_clean(page); | |
1682 | kvm_inject_gp(&svm->vcpu, 0); | |
1683 | ||
1684 | return NULL; | |
1685 | } | |
1686 | ||
1687 | static void nested_svm_unmap(struct page *page) | |
1688 | { | |
1689 | kunmap(page); | |
1690 | kvm_release_page_dirty(page); | |
1691 | } | |
1692 | ||
1693 | static int nested_svm_intercept_ioio(struct vcpu_svm *svm) | |
1694 | { | |
1695 | unsigned port; | |
1696 | u8 val, bit; | |
1697 | u64 gpa; | |
1698 | ||
1699 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT))) | |
1700 | return NESTED_EXIT_HOST; | |
1701 | ||
1702 | port = svm->vmcb->control.exit_info_1 >> 16; | |
1703 | gpa = svm->nested.vmcb_iopm + (port / 8); | |
1704 | bit = port % 8; | |
1705 | val = 0; | |
1706 | ||
1707 | if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1)) | |
1708 | val &= (1 << bit); | |
1709 | ||
1710 | return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; | |
1711 | } | |
1712 | ||
1713 | static int nested_svm_exit_handled_msr(struct vcpu_svm *svm) | |
1714 | { | |
1715 | u32 offset, msr, value; | |
1716 | int write, mask; | |
1717 | ||
1718 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) | |
1719 | return NESTED_EXIT_HOST; | |
1720 | ||
1721 | msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; | |
1722 | offset = svm_msrpm_offset(msr); | |
1723 | write = svm->vmcb->control.exit_info_1 & 1; | |
1724 | mask = 1 << ((2 * (msr & 0xf)) + write); | |
1725 | ||
1726 | if (offset == MSR_INVALID) | |
1727 | return NESTED_EXIT_DONE; | |
1728 | ||
1729 | /* Offset is in 32 bit units but need in 8 bit units */ | |
1730 | offset *= 4; | |
1731 | ||
1732 | if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4)) | |
1733 | return NESTED_EXIT_DONE; | |
1734 | ||
1735 | return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; | |
1736 | } | |
1737 | ||
1738 | static int nested_svm_exit_special(struct vcpu_svm *svm) | |
1739 | { | |
1740 | u32 exit_code = svm->vmcb->control.exit_code; | |
1741 | ||
1742 | switch (exit_code) { | |
1743 | case SVM_EXIT_INTR: | |
1744 | case SVM_EXIT_NMI: | |
1745 | case SVM_EXIT_EXCP_BASE + MC_VECTOR: | |
1746 | return NESTED_EXIT_HOST; | |
1747 | case SVM_EXIT_NPF: | |
1748 | /* For now we are always handling NPFs when using them */ | |
1749 | if (npt_enabled) | |
1750 | return NESTED_EXIT_HOST; | |
1751 | break; | |
1752 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: | |
1753 | /* When we're shadowing, trap PFs */ | |
1754 | if (!npt_enabled) | |
1755 | return NESTED_EXIT_HOST; | |
1756 | break; | |
1757 | case SVM_EXIT_EXCP_BASE + NM_VECTOR: | |
1758 | nm_interception(svm); | |
1759 | break; | |
1760 | default: | |
1761 | break; | |
1762 | } | |
1763 | ||
1764 | return NESTED_EXIT_CONTINUE; | |
1765 | } | |
1766 | ||
1767 | /* | |
1768 | * If this function returns true, this #vmexit was already handled | |
1769 | */ | |
1770 | static int nested_svm_intercept(struct vcpu_svm *svm) | |
1771 | { | |
1772 | u32 exit_code = svm->vmcb->control.exit_code; | |
1773 | int vmexit = NESTED_EXIT_HOST; | |
1774 | ||
1775 | switch (exit_code) { | |
1776 | case SVM_EXIT_MSR: | |
1777 | vmexit = nested_svm_exit_handled_msr(svm); | |
1778 | break; | |
1779 | case SVM_EXIT_IOIO: | |
1780 | vmexit = nested_svm_intercept_ioio(svm); | |
1781 | break; | |
1782 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: { | |
1783 | u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0); | |
1784 | if (svm->nested.intercept_cr_read & cr_bits) | |
1785 | vmexit = NESTED_EXIT_DONE; | |
1786 | break; | |
1787 | } | |
1788 | case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: { | |
1789 | u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0); | |
1790 | if (svm->nested.intercept_cr_write & cr_bits) | |
1791 | vmexit = NESTED_EXIT_DONE; | |
1792 | break; | |
1793 | } | |
1794 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: { | |
1795 | u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0); | |
1796 | if (svm->nested.intercept_dr_read & dr_bits) | |
1797 | vmexit = NESTED_EXIT_DONE; | |
1798 | break; | |
1799 | } | |
1800 | case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: { | |
1801 | u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0); | |
1802 | if (svm->nested.intercept_dr_write & dr_bits) | |
1803 | vmexit = NESTED_EXIT_DONE; | |
1804 | break; | |
1805 | } | |
1806 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
1807 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
1808 | if (svm->nested.intercept_exceptions & excp_bits) | |
1809 | vmexit = NESTED_EXIT_DONE; | |
1810 | break; | |
1811 | } | |
1812 | case SVM_EXIT_ERR: { | |
1813 | vmexit = NESTED_EXIT_DONE; | |
1814 | break; | |
1815 | } | |
1816 | default: { | |
1817 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
1818 | if (svm->nested.intercept & exit_bits) | |
1819 | vmexit = NESTED_EXIT_DONE; | |
1820 | } | |
1821 | } | |
1822 | ||
1823 | return vmexit; | |
1824 | } | |
1825 | ||
1826 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
1827 | { | |
1828 | int vmexit; | |
1829 | ||
1830 | vmexit = nested_svm_intercept(svm); | |
1831 | ||
1832 | if (vmexit == NESTED_EXIT_DONE) | |
1833 | nested_svm_vmexit(svm); | |
1834 | ||
1835 | return vmexit; | |
1836 | } | |
1837 | ||
1838 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) | |
1839 | { | |
1840 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
1841 | struct vmcb_control_area *from = &from_vmcb->control; | |
1842 | ||
1843 | dst->intercept_cr_read = from->intercept_cr_read; | |
1844 | dst->intercept_cr_write = from->intercept_cr_write; | |
1845 | dst->intercept_dr_read = from->intercept_dr_read; | |
1846 | dst->intercept_dr_write = from->intercept_dr_write; | |
1847 | dst->intercept_exceptions = from->intercept_exceptions; | |
1848 | dst->intercept = from->intercept; | |
1849 | dst->iopm_base_pa = from->iopm_base_pa; | |
1850 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
1851 | dst->tsc_offset = from->tsc_offset; | |
1852 | dst->asid = from->asid; | |
1853 | dst->tlb_ctl = from->tlb_ctl; | |
1854 | dst->int_ctl = from->int_ctl; | |
1855 | dst->int_vector = from->int_vector; | |
1856 | dst->int_state = from->int_state; | |
1857 | dst->exit_code = from->exit_code; | |
1858 | dst->exit_code_hi = from->exit_code_hi; | |
1859 | dst->exit_info_1 = from->exit_info_1; | |
1860 | dst->exit_info_2 = from->exit_info_2; | |
1861 | dst->exit_int_info = from->exit_int_info; | |
1862 | dst->exit_int_info_err = from->exit_int_info_err; | |
1863 | dst->nested_ctl = from->nested_ctl; | |
1864 | dst->event_inj = from->event_inj; | |
1865 | dst->event_inj_err = from->event_inj_err; | |
1866 | dst->nested_cr3 = from->nested_cr3; | |
1867 | dst->lbr_ctl = from->lbr_ctl; | |
1868 | } | |
1869 | ||
1870 | static int nested_svm_vmexit(struct vcpu_svm *svm) | |
1871 | { | |
1872 | struct vmcb *nested_vmcb; | |
1873 | struct vmcb *hsave = svm->nested.hsave; | |
1874 | struct vmcb *vmcb = svm->vmcb; | |
1875 | struct page *page; | |
1876 | ||
1877 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, | |
1878 | vmcb->control.exit_info_1, | |
1879 | vmcb->control.exit_info_2, | |
1880 | vmcb->control.exit_int_info, | |
1881 | vmcb->control.exit_int_info_err); | |
1882 | ||
1883 | nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page); | |
1884 | if (!nested_vmcb) | |
1885 | return 1; | |
1886 | ||
1887 | /* Exit nested SVM mode */ | |
1888 | svm->nested.vmcb = 0; | |
1889 | ||
1890 | /* Give the current vmcb to the guest */ | |
1891 | disable_gif(svm); | |
1892 | ||
1893 | nested_vmcb->save.es = vmcb->save.es; | |
1894 | nested_vmcb->save.cs = vmcb->save.cs; | |
1895 | nested_vmcb->save.ss = vmcb->save.ss; | |
1896 | nested_vmcb->save.ds = vmcb->save.ds; | |
1897 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
1898 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
1899 | nested_vmcb->save.efer = svm->vcpu.arch.efer; | |
1900 | nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu); | |
1901 | nested_vmcb->save.cr3 = svm->vcpu.arch.cr3; | |
1902 | nested_vmcb->save.cr2 = vmcb->save.cr2; | |
1903 | nested_vmcb->save.cr4 = svm->vcpu.arch.cr4; | |
1904 | nested_vmcb->save.rflags = vmcb->save.rflags; | |
1905 | nested_vmcb->save.rip = vmcb->save.rip; | |
1906 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
1907 | nested_vmcb->save.rax = vmcb->save.rax; | |
1908 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
1909 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
1910 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
1911 | ||
1912 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
1913 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
1914 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
1915 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
1916 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
1917 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
1918 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
1919 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
1920 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
1921 | nested_vmcb->control.next_rip = vmcb->control.next_rip; | |
1922 | ||
1923 | /* | |
1924 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
1925 | * to make sure that we do not lose injected events. So check event_inj | |
1926 | * here and copy it to exit_int_info if it is valid. | |
1927 | * Exit_int_info and event_inj can't be both valid because the case | |
1928 | * below only happens on a VMRUN instruction intercept which has | |
1929 | * no valid exit_int_info set. | |
1930 | */ | |
1931 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
1932 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
1933 | ||
1934 | nc->exit_int_info = vmcb->control.event_inj; | |
1935 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
1936 | } | |
1937 | ||
1938 | nested_vmcb->control.tlb_ctl = 0; | |
1939 | nested_vmcb->control.event_inj = 0; | |
1940 | nested_vmcb->control.event_inj_err = 0; | |
1941 | ||
1942 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
1943 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
1944 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
1945 | ||
1946 | /* Restore the original control entries */ | |
1947 | copy_vmcb_control_area(vmcb, hsave); | |
1948 | ||
1949 | kvm_clear_exception_queue(&svm->vcpu); | |
1950 | kvm_clear_interrupt_queue(&svm->vcpu); | |
1951 | ||
1952 | /* Restore selected save entries */ | |
1953 | svm->vmcb->save.es = hsave->save.es; | |
1954 | svm->vmcb->save.cs = hsave->save.cs; | |
1955 | svm->vmcb->save.ss = hsave->save.ss; | |
1956 | svm->vmcb->save.ds = hsave->save.ds; | |
1957 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
1958 | svm->vmcb->save.idtr = hsave->save.idtr; | |
1959 | svm->vmcb->save.rflags = hsave->save.rflags; | |
1960 | svm_set_efer(&svm->vcpu, hsave->save.efer); | |
1961 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
1962 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
1963 | if (npt_enabled) { | |
1964 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
1965 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
1966 | } else { | |
1967 | (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3); | |
1968 | } | |
1969 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
1970 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
1971 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
1972 | svm->vmcb->save.dr7 = 0; | |
1973 | svm->vmcb->save.cpl = 0; | |
1974 | svm->vmcb->control.exit_int_info = 0; | |
1975 | ||
1976 | nested_svm_unmap(page); | |
1977 | ||
1978 | kvm_mmu_reset_context(&svm->vcpu); | |
1979 | kvm_mmu_load(&svm->vcpu); | |
1980 | ||
1981 | return 0; | |
1982 | } | |
1983 | ||
1984 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) | |
1985 | { | |
1986 | /* | |
1987 | * This function merges the msr permission bitmaps of kvm and the | |
1988 | * nested vmcb. It is omptimized in that it only merges the parts where | |
1989 | * the kvm msr permission bitmap may contain zero bits | |
1990 | */ | |
1991 | int i; | |
1992 | ||
1993 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) | |
1994 | return true; | |
1995 | ||
1996 | for (i = 0; i < MSRPM_OFFSETS; i++) { | |
1997 | u32 value, p; | |
1998 | u64 offset; | |
1999 | ||
2000 | if (msrpm_offsets[i] == 0xffffffff) | |
2001 | break; | |
2002 | ||
2003 | p = msrpm_offsets[i]; | |
2004 | offset = svm->nested.vmcb_msrpm + (p * 4); | |
2005 | ||
2006 | if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4)) | |
2007 | return false; | |
2008 | ||
2009 | svm->nested.msrpm[p] = svm->msrpm[p] | value; | |
2010 | } | |
2011 | ||
2012 | svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm); | |
2013 | ||
2014 | return true; | |
2015 | } | |
2016 | ||
2017 | static bool nested_vmcb_checks(struct vmcb *vmcb) | |
2018 | { | |
2019 | if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0) | |
2020 | return false; | |
2021 | ||
2022 | if (vmcb->control.asid == 0) | |
2023 | return false; | |
2024 | ||
2025 | return true; | |
2026 | } | |
2027 | ||
2028 | static bool nested_svm_vmrun(struct vcpu_svm *svm) | |
2029 | { | |
2030 | struct vmcb *nested_vmcb; | |
2031 | struct vmcb *hsave = svm->nested.hsave; | |
2032 | struct vmcb *vmcb = svm->vmcb; | |
2033 | struct page *page; | |
2034 | u64 vmcb_gpa; | |
2035 | ||
2036 | vmcb_gpa = svm->vmcb->save.rax; | |
2037 | ||
2038 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); | |
2039 | if (!nested_vmcb) | |
2040 | return false; | |
2041 | ||
2042 | if (!nested_vmcb_checks(nested_vmcb)) { | |
2043 | nested_vmcb->control.exit_code = SVM_EXIT_ERR; | |
2044 | nested_vmcb->control.exit_code_hi = 0; | |
2045 | nested_vmcb->control.exit_info_1 = 0; | |
2046 | nested_vmcb->control.exit_info_2 = 0; | |
2047 | ||
2048 | nested_svm_unmap(page); | |
2049 | ||
2050 | return false; | |
2051 | } | |
2052 | ||
2053 | trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, vmcb_gpa, | |
2054 | nested_vmcb->save.rip, | |
2055 | nested_vmcb->control.int_ctl, | |
2056 | nested_vmcb->control.event_inj, | |
2057 | nested_vmcb->control.nested_ctl); | |
2058 | ||
2059 | trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read, | |
2060 | nested_vmcb->control.intercept_cr_write, | |
2061 | nested_vmcb->control.intercept_exceptions, | |
2062 | nested_vmcb->control.intercept); | |
2063 | ||
2064 | /* Clear internal status */ | |
2065 | kvm_clear_exception_queue(&svm->vcpu); | |
2066 | kvm_clear_interrupt_queue(&svm->vcpu); | |
2067 | ||
2068 | /* | |
2069 | * Save the old vmcb, so we don't need to pick what we save, but can | |
2070 | * restore everything when a VMEXIT occurs | |
2071 | */ | |
2072 | hsave->save.es = vmcb->save.es; | |
2073 | hsave->save.cs = vmcb->save.cs; | |
2074 | hsave->save.ss = vmcb->save.ss; | |
2075 | hsave->save.ds = vmcb->save.ds; | |
2076 | hsave->save.gdtr = vmcb->save.gdtr; | |
2077 | hsave->save.idtr = vmcb->save.idtr; | |
2078 | hsave->save.efer = svm->vcpu.arch.efer; | |
2079 | hsave->save.cr0 = kvm_read_cr0(&svm->vcpu); | |
2080 | hsave->save.cr4 = svm->vcpu.arch.cr4; | |
2081 | hsave->save.rflags = vmcb->save.rflags; | |
2082 | hsave->save.rip = svm->next_rip; | |
2083 | hsave->save.rsp = vmcb->save.rsp; | |
2084 | hsave->save.rax = vmcb->save.rax; | |
2085 | if (npt_enabled) | |
2086 | hsave->save.cr3 = vmcb->save.cr3; | |
2087 | else | |
2088 | hsave->save.cr3 = svm->vcpu.arch.cr3; | |
2089 | ||
2090 | copy_vmcb_control_area(hsave, vmcb); | |
2091 | ||
2092 | if (svm->vmcb->save.rflags & X86_EFLAGS_IF) | |
2093 | svm->vcpu.arch.hflags |= HF_HIF_MASK; | |
2094 | else | |
2095 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
2096 | ||
2097 | /* Load the nested guest state */ | |
2098 | svm->vmcb->save.es = nested_vmcb->save.es; | |
2099 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
2100 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
2101 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
2102 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
2103 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
2104 | svm->vmcb->save.rflags = nested_vmcb->save.rflags; | |
2105 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); | |
2106 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
2107 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
2108 | if (npt_enabled) { | |
2109 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
2110 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
2111 | } else | |
2112 | (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); | |
2113 | ||
2114 | /* Guest paging mode is active - reset mmu */ | |
2115 | kvm_mmu_reset_context(&svm->vcpu); | |
2116 | ||
2117 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; | |
2118 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); | |
2119 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
2120 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
2121 | ||
2122 | /* In case we don't even reach vcpu_run, the fields are not updated */ | |
2123 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
2124 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
2125 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
2126 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
2127 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
2128 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
2129 | ||
2130 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL; | |
2131 | svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL; | |
2132 | ||
2133 | /* cache intercepts */ | |
2134 | svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read; | |
2135 | svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write; | |
2136 | svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read; | |
2137 | svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write; | |
2138 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; | |
2139 | svm->nested.intercept = nested_vmcb->control.intercept; | |
2140 | ||
2141 | force_new_asid(&svm->vcpu); | |
2142 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; | |
2143 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) | |
2144 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
2145 | else | |
2146 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
2147 | ||
2148 | if (svm->vcpu.arch.hflags & HF_VINTR_MASK) { | |
2149 | /* We only want the cr8 intercept bits of the guest */ | |
2150 | svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK; | |
2151 | svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK; | |
2152 | } | |
2153 | ||
2154 | /* We don't want to see VMMCALLs from a nested guest */ | |
2155 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL); | |
2156 | ||
2157 | /* | |
2158 | * We don't want a nested guest to be more powerful than the guest, so | |
2159 | * all intercepts are ORed | |
2160 | */ | |
2161 | svm->vmcb->control.intercept_cr_read |= | |
2162 | nested_vmcb->control.intercept_cr_read; | |
2163 | svm->vmcb->control.intercept_cr_write |= | |
2164 | nested_vmcb->control.intercept_cr_write; | |
2165 | svm->vmcb->control.intercept_dr_read |= | |
2166 | nested_vmcb->control.intercept_dr_read; | |
2167 | svm->vmcb->control.intercept_dr_write |= | |
2168 | nested_vmcb->control.intercept_dr_write; | |
2169 | svm->vmcb->control.intercept_exceptions |= | |
2170 | nested_vmcb->control.intercept_exceptions; | |
2171 | ||
2172 | svm->vmcb->control.intercept |= nested_vmcb->control.intercept; | |
2173 | ||
2174 | svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl; | |
2175 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; | |
2176 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
2177 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
2178 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; | |
2179 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
2180 | ||
2181 | nested_svm_unmap(page); | |
2182 | ||
2183 | /* nested_vmcb is our indicator if nested SVM is activated */ | |
2184 | svm->nested.vmcb = vmcb_gpa; | |
2185 | ||
2186 | enable_gif(svm); | |
2187 | ||
2188 | return true; | |
2189 | } | |
2190 | ||
2191 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) | |
2192 | { | |
2193 | to_vmcb->save.fs = from_vmcb->save.fs; | |
2194 | to_vmcb->save.gs = from_vmcb->save.gs; | |
2195 | to_vmcb->save.tr = from_vmcb->save.tr; | |
2196 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
2197 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
2198 | to_vmcb->save.star = from_vmcb->save.star; | |
2199 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
2200 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
2201 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
2202 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
2203 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
2204 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
2205 | } | |
2206 | ||
2207 | static int vmload_interception(struct vcpu_svm *svm) | |
2208 | { | |
2209 | struct vmcb *nested_vmcb; | |
2210 | struct page *page; | |
2211 | ||
2212 | if (nested_svm_check_permissions(svm)) | |
2213 | return 1; | |
2214 | ||
2215 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2216 | skip_emulated_instruction(&svm->vcpu); | |
2217 | ||
2218 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); | |
2219 | if (!nested_vmcb) | |
2220 | return 1; | |
2221 | ||
2222 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); | |
2223 | nested_svm_unmap(page); | |
2224 | ||
2225 | return 1; | |
2226 | } | |
2227 | ||
2228 | static int vmsave_interception(struct vcpu_svm *svm) | |
2229 | { | |
2230 | struct vmcb *nested_vmcb; | |
2231 | struct page *page; | |
2232 | ||
2233 | if (nested_svm_check_permissions(svm)) | |
2234 | return 1; | |
2235 | ||
2236 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2237 | skip_emulated_instruction(&svm->vcpu); | |
2238 | ||
2239 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); | |
2240 | if (!nested_vmcb) | |
2241 | return 1; | |
2242 | ||
2243 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); | |
2244 | nested_svm_unmap(page); | |
2245 | ||
2246 | return 1; | |
2247 | } | |
2248 | ||
2249 | static int vmrun_interception(struct vcpu_svm *svm) | |
2250 | { | |
2251 | if (nested_svm_check_permissions(svm)) | |
2252 | return 1; | |
2253 | ||
2254 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2255 | skip_emulated_instruction(&svm->vcpu); | |
2256 | ||
2257 | if (!nested_svm_vmrun(svm)) | |
2258 | return 1; | |
2259 | ||
2260 | if (!nested_svm_vmrun_msrpm(svm)) | |
2261 | goto failed; | |
2262 | ||
2263 | return 1; | |
2264 | ||
2265 | failed: | |
2266 | ||
2267 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
2268 | svm->vmcb->control.exit_code_hi = 0; | |
2269 | svm->vmcb->control.exit_info_1 = 0; | |
2270 | svm->vmcb->control.exit_info_2 = 0; | |
2271 | ||
2272 | nested_svm_vmexit(svm); | |
2273 | ||
2274 | return 1; | |
2275 | } | |
2276 | ||
2277 | static int stgi_interception(struct vcpu_svm *svm) | |
2278 | { | |
2279 | if (nested_svm_check_permissions(svm)) | |
2280 | return 1; | |
2281 | ||
2282 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2283 | skip_emulated_instruction(&svm->vcpu); | |
2284 | ||
2285 | enable_gif(svm); | |
2286 | ||
2287 | return 1; | |
2288 | } | |
2289 | ||
2290 | static int clgi_interception(struct vcpu_svm *svm) | |
2291 | { | |
2292 | if (nested_svm_check_permissions(svm)) | |
2293 | return 1; | |
2294 | ||
2295 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2296 | skip_emulated_instruction(&svm->vcpu); | |
2297 | ||
2298 | disable_gif(svm); | |
2299 | ||
2300 | /* After a CLGI no interrupts should come */ | |
2301 | svm_clear_vintr(svm); | |
2302 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
2303 | ||
2304 | return 1; | |
2305 | } | |
2306 | ||
2307 | static int invlpga_interception(struct vcpu_svm *svm) | |
2308 | { | |
2309 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
2310 | ||
2311 | trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX], | |
2312 | vcpu->arch.regs[VCPU_REGS_RAX]); | |
2313 | ||
2314 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ | |
2315 | kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]); | |
2316 | ||
2317 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2318 | skip_emulated_instruction(&svm->vcpu); | |
2319 | return 1; | |
2320 | } | |
2321 | ||
2322 | static int skinit_interception(struct vcpu_svm *svm) | |
2323 | { | |
2324 | trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]); | |
2325 | ||
2326 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2327 | return 1; | |
2328 | } | |
2329 | ||
2330 | static int invalid_op_interception(struct vcpu_svm *svm) | |
2331 | { | |
2332 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2333 | return 1; | |
2334 | } | |
2335 | ||
2336 | static int task_switch_interception(struct vcpu_svm *svm) | |
2337 | { | |
2338 | u16 tss_selector; | |
2339 | int reason; | |
2340 | int int_type = svm->vmcb->control.exit_int_info & | |
2341 | SVM_EXITINTINFO_TYPE_MASK; | |
2342 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; | |
2343 | uint32_t type = | |
2344 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
2345 | uint32_t idt_v = | |
2346 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
2347 | bool has_error_code = false; | |
2348 | u32 error_code = 0; | |
2349 | ||
2350 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
2351 | ||
2352 | if (svm->vmcb->control.exit_info_2 & | |
2353 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
2354 | reason = TASK_SWITCH_IRET; | |
2355 | else if (svm->vmcb->control.exit_info_2 & | |
2356 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
2357 | reason = TASK_SWITCH_JMP; | |
2358 | else if (idt_v) | |
2359 | reason = TASK_SWITCH_GATE; | |
2360 | else | |
2361 | reason = TASK_SWITCH_CALL; | |
2362 | ||
2363 | if (reason == TASK_SWITCH_GATE) { | |
2364 | switch (type) { | |
2365 | case SVM_EXITINTINFO_TYPE_NMI: | |
2366 | svm->vcpu.arch.nmi_injected = false; | |
2367 | break; | |
2368 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
2369 | if (svm->vmcb->control.exit_info_2 & | |
2370 | (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) { | |
2371 | has_error_code = true; | |
2372 | error_code = | |
2373 | (u32)svm->vmcb->control.exit_info_2; | |
2374 | } | |
2375 | kvm_clear_exception_queue(&svm->vcpu); | |
2376 | break; | |
2377 | case SVM_EXITINTINFO_TYPE_INTR: | |
2378 | kvm_clear_interrupt_queue(&svm->vcpu); | |
2379 | break; | |
2380 | default: | |
2381 | break; | |
2382 | } | |
2383 | } | |
2384 | ||
2385 | if (reason != TASK_SWITCH_GATE || | |
2386 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
2387 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
2388 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) | |
2389 | skip_emulated_instruction(&svm->vcpu); | |
2390 | ||
2391 | if (kvm_task_switch(&svm->vcpu, tss_selector, reason, | |
2392 | has_error_code, error_code) == EMULATE_FAIL) { | |
2393 | svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
2394 | svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
2395 | svm->vcpu.run->internal.ndata = 0; | |
2396 | return 0; | |
2397 | } | |
2398 | return 1; | |
2399 | } | |
2400 | ||
2401 | static int cpuid_interception(struct vcpu_svm *svm) | |
2402 | { | |
2403 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; | |
2404 | kvm_emulate_cpuid(&svm->vcpu); | |
2405 | return 1; | |
2406 | } | |
2407 | ||
2408 | static int iret_interception(struct vcpu_svm *svm) | |
2409 | { | |
2410 | ++svm->vcpu.stat.nmi_window_exits; | |
2411 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET); | |
2412 | svm->vcpu.arch.hflags |= HF_IRET_MASK; | |
2413 | return 1; | |
2414 | } | |
2415 | ||
2416 | static int invlpg_interception(struct vcpu_svm *svm) | |
2417 | { | |
2418 | return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE; | |
2419 | } | |
2420 | ||
2421 | static int emulate_on_interception(struct vcpu_svm *svm) | |
2422 | { | |
2423 | return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE; | |
2424 | } | |
2425 | ||
2426 | static int cr8_write_interception(struct vcpu_svm *svm) | |
2427 | { | |
2428 | struct kvm_run *kvm_run = svm->vcpu.run; | |
2429 | ||
2430 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); | |
2431 | /* instruction emulation calls kvm_set_cr8() */ | |
2432 | emulate_instruction(&svm->vcpu, 0, 0, 0); | |
2433 | if (irqchip_in_kernel(svm->vcpu.kvm)) { | |
2434 | svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK; | |
2435 | return 1; | |
2436 | } | |
2437 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) | |
2438 | return 1; | |
2439 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; | |
2440 | return 0; | |
2441 | } | |
2442 | ||
2443 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) | |
2444 | { | |
2445 | struct vcpu_svm *svm = to_svm(vcpu); | |
2446 | ||
2447 | switch (ecx) { | |
2448 | case MSR_IA32_TSC: { | |
2449 | u64 tsc_offset; | |
2450 | ||
2451 | if (is_nested(svm)) | |
2452 | tsc_offset = svm->nested.hsave->control.tsc_offset; | |
2453 | else | |
2454 | tsc_offset = svm->vmcb->control.tsc_offset; | |
2455 | ||
2456 | *data = tsc_offset + native_read_tsc(); | |
2457 | break; | |
2458 | } | |
2459 | case MSR_STAR: | |
2460 | *data = svm->vmcb->save.star; | |
2461 | break; | |
2462 | #ifdef CONFIG_X86_64 | |
2463 | case MSR_LSTAR: | |
2464 | *data = svm->vmcb->save.lstar; | |
2465 | break; | |
2466 | case MSR_CSTAR: | |
2467 | *data = svm->vmcb->save.cstar; | |
2468 | break; | |
2469 | case MSR_KERNEL_GS_BASE: | |
2470 | *data = svm->vmcb->save.kernel_gs_base; | |
2471 | break; | |
2472 | case MSR_SYSCALL_MASK: | |
2473 | *data = svm->vmcb->save.sfmask; | |
2474 | break; | |
2475 | #endif | |
2476 | case MSR_IA32_SYSENTER_CS: | |
2477 | *data = svm->vmcb->save.sysenter_cs; | |
2478 | break; | |
2479 | case MSR_IA32_SYSENTER_EIP: | |
2480 | *data = svm->sysenter_eip; | |
2481 | break; | |
2482 | case MSR_IA32_SYSENTER_ESP: | |
2483 | *data = svm->sysenter_esp; | |
2484 | break; | |
2485 | /* | |
2486 | * Nobody will change the following 5 values in the VMCB so we can | |
2487 | * safely return them on rdmsr. They will always be 0 until LBRV is | |
2488 | * implemented. | |
2489 | */ | |
2490 | case MSR_IA32_DEBUGCTLMSR: | |
2491 | *data = svm->vmcb->save.dbgctl; | |
2492 | break; | |
2493 | case MSR_IA32_LASTBRANCHFROMIP: | |
2494 | *data = svm->vmcb->save.br_from; | |
2495 | break; | |
2496 | case MSR_IA32_LASTBRANCHTOIP: | |
2497 | *data = svm->vmcb->save.br_to; | |
2498 | break; | |
2499 | case MSR_IA32_LASTINTFROMIP: | |
2500 | *data = svm->vmcb->save.last_excp_from; | |
2501 | break; | |
2502 | case MSR_IA32_LASTINTTOIP: | |
2503 | *data = svm->vmcb->save.last_excp_to; | |
2504 | break; | |
2505 | case MSR_VM_HSAVE_PA: | |
2506 | *data = svm->nested.hsave_msr; | |
2507 | break; | |
2508 | case MSR_VM_CR: | |
2509 | *data = svm->nested.vm_cr_msr; | |
2510 | break; | |
2511 | case MSR_IA32_UCODE_REV: | |
2512 | *data = 0x01000065; | |
2513 | break; | |
2514 | default: | |
2515 | return kvm_get_msr_common(vcpu, ecx, data); | |
2516 | } | |
2517 | return 0; | |
2518 | } | |
2519 | ||
2520 | static int rdmsr_interception(struct vcpu_svm *svm) | |
2521 | { | |
2522 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; | |
2523 | u64 data; | |
2524 | ||
2525 | if (svm_get_msr(&svm->vcpu, ecx, &data)) { | |
2526 | trace_kvm_msr_read_ex(ecx); | |
2527 | kvm_inject_gp(&svm->vcpu, 0); | |
2528 | } else { | |
2529 | trace_kvm_msr_read(ecx, data); | |
2530 | ||
2531 | svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff; | |
2532 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; | |
2533 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; | |
2534 | skip_emulated_instruction(&svm->vcpu); | |
2535 | } | |
2536 | return 1; | |
2537 | } | |
2538 | ||
2539 | static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) | |
2540 | { | |
2541 | struct vcpu_svm *svm = to_svm(vcpu); | |
2542 | int svm_dis, chg_mask; | |
2543 | ||
2544 | if (data & ~SVM_VM_CR_VALID_MASK) | |
2545 | return 1; | |
2546 | ||
2547 | chg_mask = SVM_VM_CR_VALID_MASK; | |
2548 | ||
2549 | if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK) | |
2550 | chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK); | |
2551 | ||
2552 | svm->nested.vm_cr_msr &= ~chg_mask; | |
2553 | svm->nested.vm_cr_msr |= (data & chg_mask); | |
2554 | ||
2555 | svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK; | |
2556 | ||
2557 | /* check for svm_disable while efer.svme is set */ | |
2558 | if (svm_dis && (vcpu->arch.efer & EFER_SVME)) | |
2559 | return 1; | |
2560 | ||
2561 | return 0; | |
2562 | } | |
2563 | ||
2564 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) | |
2565 | { | |
2566 | struct vcpu_svm *svm = to_svm(vcpu); | |
2567 | ||
2568 | switch (ecx) { | |
2569 | case MSR_IA32_TSC: { | |
2570 | u64 tsc_offset = data - native_read_tsc(); | |
2571 | u64 g_tsc_offset = 0; | |
2572 | ||
2573 | if (is_nested(svm)) { | |
2574 | g_tsc_offset = svm->vmcb->control.tsc_offset - | |
2575 | svm->nested.hsave->control.tsc_offset; | |
2576 | svm->nested.hsave->control.tsc_offset = tsc_offset; | |
2577 | } | |
2578 | ||
2579 | svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset; | |
2580 | ||
2581 | break; | |
2582 | } | |
2583 | case MSR_STAR: | |
2584 | svm->vmcb->save.star = data; | |
2585 | break; | |
2586 | #ifdef CONFIG_X86_64 | |
2587 | case MSR_LSTAR: | |
2588 | svm->vmcb->save.lstar = data; | |
2589 | break; | |
2590 | case MSR_CSTAR: | |
2591 | svm->vmcb->save.cstar = data; | |
2592 | break; | |
2593 | case MSR_KERNEL_GS_BASE: | |
2594 | svm->vmcb->save.kernel_gs_base = data; | |
2595 | break; | |
2596 | case MSR_SYSCALL_MASK: | |
2597 | svm->vmcb->save.sfmask = data; | |
2598 | break; | |
2599 | #endif | |
2600 | case MSR_IA32_SYSENTER_CS: | |
2601 | svm->vmcb->save.sysenter_cs = data; | |
2602 | break; | |
2603 | case MSR_IA32_SYSENTER_EIP: | |
2604 | svm->sysenter_eip = data; | |
2605 | svm->vmcb->save.sysenter_eip = data; | |
2606 | break; | |
2607 | case MSR_IA32_SYSENTER_ESP: | |
2608 | svm->sysenter_esp = data; | |
2609 | svm->vmcb->save.sysenter_esp = data; | |
2610 | break; | |
2611 | case MSR_IA32_DEBUGCTLMSR: | |
2612 | if (!svm_has(SVM_FEATURE_LBRV)) { | |
2613 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", | |
2614 | __func__, data); | |
2615 | break; | |
2616 | } | |
2617 | if (data & DEBUGCTL_RESERVED_BITS) | |
2618 | return 1; | |
2619 | ||
2620 | svm->vmcb->save.dbgctl = data; | |
2621 | if (data & (1ULL<<0)) | |
2622 | svm_enable_lbrv(svm); | |
2623 | else | |
2624 | svm_disable_lbrv(svm); | |
2625 | break; | |
2626 | case MSR_VM_HSAVE_PA: | |
2627 | svm->nested.hsave_msr = data; | |
2628 | break; | |
2629 | case MSR_VM_CR: | |
2630 | return svm_set_vm_cr(vcpu, data); | |
2631 | case MSR_VM_IGNNE: | |
2632 | pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); | |
2633 | break; | |
2634 | default: | |
2635 | return kvm_set_msr_common(vcpu, ecx, data); | |
2636 | } | |
2637 | return 0; | |
2638 | } | |
2639 | ||
2640 | static int wrmsr_interception(struct vcpu_svm *svm) | |
2641 | { | |
2642 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; | |
2643 | u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u) | |
2644 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); | |
2645 | ||
2646 | ||
2647 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; | |
2648 | if (svm_set_msr(&svm->vcpu, ecx, data)) { | |
2649 | trace_kvm_msr_write_ex(ecx, data); | |
2650 | kvm_inject_gp(&svm->vcpu, 0); | |
2651 | } else { | |
2652 | trace_kvm_msr_write(ecx, data); | |
2653 | skip_emulated_instruction(&svm->vcpu); | |
2654 | } | |
2655 | return 1; | |
2656 | } | |
2657 | ||
2658 | static int msr_interception(struct vcpu_svm *svm) | |
2659 | { | |
2660 | if (svm->vmcb->control.exit_info_1) | |
2661 | return wrmsr_interception(svm); | |
2662 | else | |
2663 | return rdmsr_interception(svm); | |
2664 | } | |
2665 | ||
2666 | static int interrupt_window_interception(struct vcpu_svm *svm) | |
2667 | { | |
2668 | struct kvm_run *kvm_run = svm->vcpu.run; | |
2669 | ||
2670 | svm_clear_vintr(svm); | |
2671 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
2672 | /* | |
2673 | * If the user space waits to inject interrupts, exit as soon as | |
2674 | * possible | |
2675 | */ | |
2676 | if (!irqchip_in_kernel(svm->vcpu.kvm) && | |
2677 | kvm_run->request_interrupt_window && | |
2678 | !kvm_cpu_has_interrupt(&svm->vcpu)) { | |
2679 | ++svm->vcpu.stat.irq_window_exits; | |
2680 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; | |
2681 | return 0; | |
2682 | } | |
2683 | ||
2684 | return 1; | |
2685 | } | |
2686 | ||
2687 | static int pause_interception(struct vcpu_svm *svm) | |
2688 | { | |
2689 | kvm_vcpu_on_spin(&(svm->vcpu)); | |
2690 | return 1; | |
2691 | } | |
2692 | ||
2693 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = { | |
2694 | [SVM_EXIT_READ_CR0] = emulate_on_interception, | |
2695 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
2696 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
2697 | [SVM_EXIT_READ_CR8] = emulate_on_interception, | |
2698 | [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, | |
2699 | [SVM_EXIT_WRITE_CR0] = emulate_on_interception, | |
2700 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, | |
2701 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
2702 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, | |
2703 | [SVM_EXIT_READ_DR0] = emulate_on_interception, | |
2704 | [SVM_EXIT_READ_DR1] = emulate_on_interception, | |
2705 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
2706 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
2707 | [SVM_EXIT_READ_DR4] = emulate_on_interception, | |
2708 | [SVM_EXIT_READ_DR5] = emulate_on_interception, | |
2709 | [SVM_EXIT_READ_DR6] = emulate_on_interception, | |
2710 | [SVM_EXIT_READ_DR7] = emulate_on_interception, | |
2711 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, | |
2712 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
2713 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
2714 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
2715 | [SVM_EXIT_WRITE_DR4] = emulate_on_interception, | |
2716 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, | |
2717 | [SVM_EXIT_WRITE_DR6] = emulate_on_interception, | |
2718 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, | |
2719 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, | |
2720 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
2721 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, | |
2722 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, | |
2723 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, | |
2724 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, | |
2725 | [SVM_EXIT_INTR] = intr_interception, | |
2726 | [SVM_EXIT_NMI] = nmi_interception, | |
2727 | [SVM_EXIT_SMI] = nop_on_interception, | |
2728 | [SVM_EXIT_INIT] = nop_on_interception, | |
2729 | [SVM_EXIT_VINTR] = interrupt_window_interception, | |
2730 | [SVM_EXIT_CPUID] = cpuid_interception, | |
2731 | [SVM_EXIT_IRET] = iret_interception, | |
2732 | [SVM_EXIT_INVD] = emulate_on_interception, | |
2733 | [SVM_EXIT_PAUSE] = pause_interception, | |
2734 | [SVM_EXIT_HLT] = halt_interception, | |
2735 | [SVM_EXIT_INVLPG] = invlpg_interception, | |
2736 | [SVM_EXIT_INVLPGA] = invlpga_interception, | |
2737 | [SVM_EXIT_IOIO] = io_interception, | |
2738 | [SVM_EXIT_MSR] = msr_interception, | |
2739 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
2740 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, | |
2741 | [SVM_EXIT_VMRUN] = vmrun_interception, | |
2742 | [SVM_EXIT_VMMCALL] = vmmcall_interception, | |
2743 | [SVM_EXIT_VMLOAD] = vmload_interception, | |
2744 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
2745 | [SVM_EXIT_STGI] = stgi_interception, | |
2746 | [SVM_EXIT_CLGI] = clgi_interception, | |
2747 | [SVM_EXIT_SKINIT] = skinit_interception, | |
2748 | [SVM_EXIT_WBINVD] = emulate_on_interception, | |
2749 | [SVM_EXIT_MONITOR] = invalid_op_interception, | |
2750 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
2751 | [SVM_EXIT_NPF] = pf_interception, | |
2752 | }; | |
2753 | ||
2754 | void dump_vmcb(struct kvm_vcpu *vcpu) | |
2755 | { | |
2756 | struct vcpu_svm *svm = to_svm(vcpu); | |
2757 | struct vmcb_control_area *control = &svm->vmcb->control; | |
2758 | struct vmcb_save_area *save = &svm->vmcb->save; | |
2759 | ||
2760 | pr_err("VMCB Control Area:\n"); | |
2761 | pr_err("cr_read: %04x\n", control->intercept_cr_read); | |
2762 | pr_err("cr_write: %04x\n", control->intercept_cr_write); | |
2763 | pr_err("dr_read: %04x\n", control->intercept_dr_read); | |
2764 | pr_err("dr_write: %04x\n", control->intercept_dr_write); | |
2765 | pr_err("exceptions: %08x\n", control->intercept_exceptions); | |
2766 | pr_err("intercepts: %016llx\n", control->intercept); | |
2767 | pr_err("pause filter count: %d\n", control->pause_filter_count); | |
2768 | pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa); | |
2769 | pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa); | |
2770 | pr_err("tsc_offset: %016llx\n", control->tsc_offset); | |
2771 | pr_err("asid: %d\n", control->asid); | |
2772 | pr_err("tlb_ctl: %d\n", control->tlb_ctl); | |
2773 | pr_err("int_ctl: %08x\n", control->int_ctl); | |
2774 | pr_err("int_vector: %08x\n", control->int_vector); | |
2775 | pr_err("int_state: %08x\n", control->int_state); | |
2776 | pr_err("exit_code: %08x\n", control->exit_code); | |
2777 | pr_err("exit_info1: %016llx\n", control->exit_info_1); | |
2778 | pr_err("exit_info2: %016llx\n", control->exit_info_2); | |
2779 | pr_err("exit_int_info: %08x\n", control->exit_int_info); | |
2780 | pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err); | |
2781 | pr_err("nested_ctl: %lld\n", control->nested_ctl); | |
2782 | pr_err("nested_cr3: %016llx\n", control->nested_cr3); | |
2783 | pr_err("event_inj: %08x\n", control->event_inj); | |
2784 | pr_err("event_inj_err: %08x\n", control->event_inj_err); | |
2785 | pr_err("lbr_ctl: %lld\n", control->lbr_ctl); | |
2786 | pr_err("next_rip: %016llx\n", control->next_rip); | |
2787 | pr_err("VMCB State Save Area:\n"); | |
2788 | pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n", | |
2789 | save->es.selector, save->es.attrib, | |
2790 | save->es.limit, save->es.base); | |
2791 | pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n", | |
2792 | save->cs.selector, save->cs.attrib, | |
2793 | save->cs.limit, save->cs.base); | |
2794 | pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n", | |
2795 | save->ss.selector, save->ss.attrib, | |
2796 | save->ss.limit, save->ss.base); | |
2797 | pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n", | |
2798 | save->ds.selector, save->ds.attrib, | |
2799 | save->ds.limit, save->ds.base); | |
2800 | pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n", | |
2801 | save->fs.selector, save->fs.attrib, | |
2802 | save->fs.limit, save->fs.base); | |
2803 | pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n", | |
2804 | save->gs.selector, save->gs.attrib, | |
2805 | save->gs.limit, save->gs.base); | |
2806 | pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
2807 | save->gdtr.selector, save->gdtr.attrib, | |
2808 | save->gdtr.limit, save->gdtr.base); | |
2809 | pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
2810 | save->ldtr.selector, save->ldtr.attrib, | |
2811 | save->ldtr.limit, save->ldtr.base); | |
2812 | pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
2813 | save->idtr.selector, save->idtr.attrib, | |
2814 | save->idtr.limit, save->idtr.base); | |
2815 | pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n", | |
2816 | save->tr.selector, save->tr.attrib, | |
2817 | save->tr.limit, save->tr.base); | |
2818 | pr_err("cpl: %d efer: %016llx\n", | |
2819 | save->cpl, save->efer); | |
2820 | pr_err("cr0: %016llx cr2: %016llx\n", | |
2821 | save->cr0, save->cr2); | |
2822 | pr_err("cr3: %016llx cr4: %016llx\n", | |
2823 | save->cr3, save->cr4); | |
2824 | pr_err("dr6: %016llx dr7: %016llx\n", | |
2825 | save->dr6, save->dr7); | |
2826 | pr_err("rip: %016llx rflags: %016llx\n", | |
2827 | save->rip, save->rflags); | |
2828 | pr_err("rsp: %016llx rax: %016llx\n", | |
2829 | save->rsp, save->rax); | |
2830 | pr_err("star: %016llx lstar: %016llx\n", | |
2831 | save->star, save->lstar); | |
2832 | pr_err("cstar: %016llx sfmask: %016llx\n", | |
2833 | save->cstar, save->sfmask); | |
2834 | pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n", | |
2835 | save->kernel_gs_base, save->sysenter_cs); | |
2836 | pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n", | |
2837 | save->sysenter_esp, save->sysenter_eip); | |
2838 | pr_err("gpat: %016llx dbgctl: %016llx\n", | |
2839 | save->g_pat, save->dbgctl); | |
2840 | pr_err("br_from: %016llx br_to: %016llx\n", | |
2841 | save->br_from, save->br_to); | |
2842 | pr_err("excp_from: %016llx excp_to: %016llx\n", | |
2843 | save->last_excp_from, save->last_excp_to); | |
2844 | ||
2845 | } | |
2846 | ||
2847 | static int handle_exit(struct kvm_vcpu *vcpu) | |
2848 | { | |
2849 | struct vcpu_svm *svm = to_svm(vcpu); | |
2850 | struct kvm_run *kvm_run = vcpu->run; | |
2851 | u32 exit_code = svm->vmcb->control.exit_code; | |
2852 | ||
2853 | trace_kvm_exit(exit_code, vcpu); | |
2854 | ||
2855 | if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK)) | |
2856 | vcpu->arch.cr0 = svm->vmcb->save.cr0; | |
2857 | if (npt_enabled) | |
2858 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
2859 | ||
2860 | if (unlikely(svm->nested.exit_required)) { | |
2861 | nested_svm_vmexit(svm); | |
2862 | svm->nested.exit_required = false; | |
2863 | ||
2864 | return 1; | |
2865 | } | |
2866 | ||
2867 | if (is_nested(svm)) { | |
2868 | int vmexit; | |
2869 | ||
2870 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, | |
2871 | svm->vmcb->control.exit_info_1, | |
2872 | svm->vmcb->control.exit_info_2, | |
2873 | svm->vmcb->control.exit_int_info, | |
2874 | svm->vmcb->control.exit_int_info_err); | |
2875 | ||
2876 | vmexit = nested_svm_exit_special(svm); | |
2877 | ||
2878 | if (vmexit == NESTED_EXIT_CONTINUE) | |
2879 | vmexit = nested_svm_exit_handled(svm); | |
2880 | ||
2881 | if (vmexit == NESTED_EXIT_DONE) | |
2882 | return 1; | |
2883 | } | |
2884 | ||
2885 | svm_complete_interrupts(svm); | |
2886 | ||
2887 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { | |
2888 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
2889 | kvm_run->fail_entry.hardware_entry_failure_reason | |
2890 | = svm->vmcb->control.exit_code; | |
2891 | pr_err("KVM: FAILED VMRUN WITH VMCB:\n"); | |
2892 | dump_vmcb(vcpu); | |
2893 | return 0; | |
2894 | } | |
2895 | ||
2896 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && | |
2897 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && | |
2898 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH) | |
2899 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " | |
2900 | "exit_code 0x%x\n", | |
2901 | __func__, svm->vmcb->control.exit_int_info, | |
2902 | exit_code); | |
2903 | ||
2904 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) | |
2905 | || !svm_exit_handlers[exit_code]) { | |
2906 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
2907 | kvm_run->hw.hardware_exit_reason = exit_code; | |
2908 | return 0; | |
2909 | } | |
2910 | ||
2911 | return svm_exit_handlers[exit_code](svm); | |
2912 | } | |
2913 | ||
2914 | static void reload_tss(struct kvm_vcpu *vcpu) | |
2915 | { | |
2916 | int cpu = raw_smp_processor_id(); | |
2917 | ||
2918 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); | |
2919 | sd->tss_desc->type = 9; /* available 32/64-bit TSS */ | |
2920 | load_TR_desc(); | |
2921 | } | |
2922 | ||
2923 | static void pre_svm_run(struct vcpu_svm *svm) | |
2924 | { | |
2925 | int cpu = raw_smp_processor_id(); | |
2926 | ||
2927 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); | |
2928 | ||
2929 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; | |
2930 | /* FIXME: handle wraparound of asid_generation */ | |
2931 | if (svm->asid_generation != sd->asid_generation) | |
2932 | new_asid(svm, sd); | |
2933 | } | |
2934 | ||
2935 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) | |
2936 | { | |
2937 | struct vcpu_svm *svm = to_svm(vcpu); | |
2938 | ||
2939 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
2940 | vcpu->arch.hflags |= HF_NMI_MASK; | |
2941 | svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET); | |
2942 | ++vcpu->stat.nmi_injections; | |
2943 | } | |
2944 | ||
2945 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) | |
2946 | { | |
2947 | struct vmcb_control_area *control; | |
2948 | ||
2949 | control = &svm->vmcb->control; | |
2950 | control->int_vector = irq; | |
2951 | control->int_ctl &= ~V_INTR_PRIO_MASK; | |
2952 | control->int_ctl |= V_IRQ_MASK | | |
2953 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
2954 | } | |
2955 | ||
2956 | static void svm_set_irq(struct kvm_vcpu *vcpu) | |
2957 | { | |
2958 | struct vcpu_svm *svm = to_svm(vcpu); | |
2959 | ||
2960 | BUG_ON(!(gif_set(svm))); | |
2961 | ||
2962 | trace_kvm_inj_virq(vcpu->arch.interrupt.nr); | |
2963 | ++vcpu->stat.irq_injections; | |
2964 | ||
2965 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | | |
2966 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2967 | } | |
2968 | ||
2969 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) | |
2970 | { | |
2971 | struct vcpu_svm *svm = to_svm(vcpu); | |
2972 | ||
2973 | if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK)) | |
2974 | return; | |
2975 | ||
2976 | if (irr == -1) | |
2977 | return; | |
2978 | ||
2979 | if (tpr >= irr) | |
2980 | svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK; | |
2981 | } | |
2982 | ||
2983 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) | |
2984 | { | |
2985 | struct vcpu_svm *svm = to_svm(vcpu); | |
2986 | struct vmcb *vmcb = svm->vmcb; | |
2987 | int ret; | |
2988 | ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
2989 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
2990 | ret = ret && gif_set(svm) && nested_svm_nmi(svm); | |
2991 | ||
2992 | return ret; | |
2993 | } | |
2994 | ||
2995 | static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) | |
2996 | { | |
2997 | struct vcpu_svm *svm = to_svm(vcpu); | |
2998 | ||
2999 | return !!(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3000 | } | |
3001 | ||
3002 | static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
3003 | { | |
3004 | struct vcpu_svm *svm = to_svm(vcpu); | |
3005 | ||
3006 | if (masked) { | |
3007 | svm->vcpu.arch.hflags |= HF_NMI_MASK; | |
3008 | svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET); | |
3009 | } else { | |
3010 | svm->vcpu.arch.hflags &= ~HF_NMI_MASK; | |
3011 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET); | |
3012 | } | |
3013 | } | |
3014 | ||
3015 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) | |
3016 | { | |
3017 | struct vcpu_svm *svm = to_svm(vcpu); | |
3018 | struct vmcb *vmcb = svm->vmcb; | |
3019 | int ret; | |
3020 | ||
3021 | if (!gif_set(svm) || | |
3022 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
3023 | return 0; | |
3024 | ||
3025 | ret = !!(vmcb->save.rflags & X86_EFLAGS_IF); | |
3026 | ||
3027 | if (is_nested(svm)) | |
3028 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); | |
3029 | ||
3030 | return ret; | |
3031 | } | |
3032 | ||
3033 | static void enable_irq_window(struct kvm_vcpu *vcpu) | |
3034 | { | |
3035 | struct vcpu_svm *svm = to_svm(vcpu); | |
3036 | ||
3037 | /* | |
3038 | * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes | |
3039 | * 1, because that's a separate STGI/VMRUN intercept. The next time we | |
3040 | * get that intercept, this function will be called again though and | |
3041 | * we'll get the vintr intercept. | |
3042 | */ | |
3043 | if (gif_set(svm) && nested_svm_intr(svm)) { | |
3044 | svm_set_vintr(svm); | |
3045 | svm_inject_irq(svm, 0x0); | |
3046 | } | |
3047 | } | |
3048 | ||
3049 | static void enable_nmi_window(struct kvm_vcpu *vcpu) | |
3050 | { | |
3051 | struct vcpu_svm *svm = to_svm(vcpu); | |
3052 | ||
3053 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) | |
3054 | == HF_NMI_MASK) | |
3055 | return; /* IRET will cause a vm exit */ | |
3056 | ||
3057 | /* | |
3058 | * Something prevents NMI from been injected. Single step over possible | |
3059 | * problem (IRET or exception injection or interrupt shadow) | |
3060 | */ | |
3061 | svm->nmi_singlestep = true; | |
3062 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); | |
3063 | update_db_intercept(vcpu); | |
3064 | } | |
3065 | ||
3066 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) | |
3067 | { | |
3068 | return 0; | |
3069 | } | |
3070 | ||
3071 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) | |
3072 | { | |
3073 | force_new_asid(vcpu); | |
3074 | } | |
3075 | ||
3076 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) | |
3077 | { | |
3078 | } | |
3079 | ||
3080 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) | |
3081 | { | |
3082 | struct vcpu_svm *svm = to_svm(vcpu); | |
3083 | ||
3084 | if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK)) | |
3085 | return; | |
3086 | ||
3087 | if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) { | |
3088 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; | |
3089 | kvm_set_cr8(vcpu, cr8); | |
3090 | } | |
3091 | } | |
3092 | ||
3093 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) | |
3094 | { | |
3095 | struct vcpu_svm *svm = to_svm(vcpu); | |
3096 | u64 cr8; | |
3097 | ||
3098 | if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK)) | |
3099 | return; | |
3100 | ||
3101 | cr8 = kvm_get_cr8(vcpu); | |
3102 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
3103 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
3104 | } | |
3105 | ||
3106 | static void svm_complete_interrupts(struct vcpu_svm *svm) | |
3107 | { | |
3108 | u8 vector; | |
3109 | int type; | |
3110 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
3111 | unsigned int3_injected = svm->int3_injected; | |
3112 | ||
3113 | svm->int3_injected = 0; | |
3114 | ||
3115 | if (svm->vcpu.arch.hflags & HF_IRET_MASK) | |
3116 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); | |
3117 | ||
3118 | svm->vcpu.arch.nmi_injected = false; | |
3119 | kvm_clear_exception_queue(&svm->vcpu); | |
3120 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3121 | ||
3122 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
3123 | return; | |
3124 | ||
3125 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; | |
3126 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
3127 | ||
3128 | switch (type) { | |
3129 | case SVM_EXITINTINFO_TYPE_NMI: | |
3130 | svm->vcpu.arch.nmi_injected = true; | |
3131 | break; | |
3132 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
3133 | /* | |
3134 | * In case of software exceptions, do not reinject the vector, | |
3135 | * but re-execute the instruction instead. Rewind RIP first | |
3136 | * if we emulated INT3 before. | |
3137 | */ | |
3138 | if (kvm_exception_is_soft(vector)) { | |
3139 | if (vector == BP_VECTOR && int3_injected && | |
3140 | kvm_is_linear_rip(&svm->vcpu, svm->int3_rip)) | |
3141 | kvm_rip_write(&svm->vcpu, | |
3142 | kvm_rip_read(&svm->vcpu) - | |
3143 | int3_injected); | |
3144 | break; | |
3145 | } | |
3146 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { | |
3147 | u32 err = svm->vmcb->control.exit_int_info_err; | |
3148 | kvm_requeue_exception_e(&svm->vcpu, vector, err); | |
3149 | ||
3150 | } else | |
3151 | kvm_requeue_exception(&svm->vcpu, vector); | |
3152 | break; | |
3153 | case SVM_EXITINTINFO_TYPE_INTR: | |
3154 | kvm_queue_interrupt(&svm->vcpu, vector, false); | |
3155 | break; | |
3156 | default: | |
3157 | break; | |
3158 | } | |
3159 | } | |
3160 | ||
3161 | #ifdef CONFIG_X86_64 | |
3162 | #define R "r" | |
3163 | #else | |
3164 | #define R "e" | |
3165 | #endif | |
3166 | ||
3167 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) | |
3168 | { | |
3169 | struct vcpu_svm *svm = to_svm(vcpu); | |
3170 | u16 fs_selector; | |
3171 | u16 gs_selector; | |
3172 | u16 ldt_selector; | |
3173 | ||
3174 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; | |
3175 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
3176 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
3177 | ||
3178 | /* | |
3179 | * A vmexit emulation is required before the vcpu can be executed | |
3180 | * again. | |
3181 | */ | |
3182 | if (unlikely(svm->nested.exit_required)) | |
3183 | return; | |
3184 | ||
3185 | pre_svm_run(svm); | |
3186 | ||
3187 | sync_lapic_to_cr8(vcpu); | |
3188 | ||
3189 | save_host_msrs(vcpu); | |
3190 | savesegment(fs, fs_selector); | |
3191 | savesegment(gs, gs_selector); | |
3192 | ldt_selector = kvm_read_ldt(); | |
3193 | svm->vmcb->save.cr2 = vcpu->arch.cr2; | |
3194 | /* required for live migration with NPT */ | |
3195 | if (npt_enabled) | |
3196 | svm->vmcb->save.cr3 = vcpu->arch.cr3; | |
3197 | ||
3198 | clgi(); | |
3199 | ||
3200 | local_irq_enable(); | |
3201 | ||
3202 | asm volatile ( | |
3203 | "push %%"R"bp; \n\t" | |
3204 | "mov %c[rbx](%[svm]), %%"R"bx \n\t" | |
3205 | "mov %c[rcx](%[svm]), %%"R"cx \n\t" | |
3206 | "mov %c[rdx](%[svm]), %%"R"dx \n\t" | |
3207 | "mov %c[rsi](%[svm]), %%"R"si \n\t" | |
3208 | "mov %c[rdi](%[svm]), %%"R"di \n\t" | |
3209 | "mov %c[rbp](%[svm]), %%"R"bp \n\t" | |
3210 | #ifdef CONFIG_X86_64 | |
3211 | "mov %c[r8](%[svm]), %%r8 \n\t" | |
3212 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
3213 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
3214 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
3215 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
3216 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
3217 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
3218 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
3219 | #endif | |
3220 | ||
3221 | /* Enter guest mode */ | |
3222 | "push %%"R"ax \n\t" | |
3223 | "mov %c[vmcb](%[svm]), %%"R"ax \n\t" | |
3224 | __ex(SVM_VMLOAD) "\n\t" | |
3225 | __ex(SVM_VMRUN) "\n\t" | |
3226 | __ex(SVM_VMSAVE) "\n\t" | |
3227 | "pop %%"R"ax \n\t" | |
3228 | ||
3229 | /* Save guest registers, load host registers */ | |
3230 | "mov %%"R"bx, %c[rbx](%[svm]) \n\t" | |
3231 | "mov %%"R"cx, %c[rcx](%[svm]) \n\t" | |
3232 | "mov %%"R"dx, %c[rdx](%[svm]) \n\t" | |
3233 | "mov %%"R"si, %c[rsi](%[svm]) \n\t" | |
3234 | "mov %%"R"di, %c[rdi](%[svm]) \n\t" | |
3235 | "mov %%"R"bp, %c[rbp](%[svm]) \n\t" | |
3236 | #ifdef CONFIG_X86_64 | |
3237 | "mov %%r8, %c[r8](%[svm]) \n\t" | |
3238 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
3239 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
3240 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
3241 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
3242 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
3243 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
3244 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
3245 | #endif | |
3246 | "pop %%"R"bp" | |
3247 | : | |
3248 | : [svm]"a"(svm), | |
3249 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), | |
3250 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), | |
3251 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
3252 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
3253 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
3254 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
3255 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
3256 | #ifdef CONFIG_X86_64 | |
3257 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), | |
3258 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
3259 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
3260 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
3261 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
3262 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
3263 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
3264 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
3265 | #endif | |
3266 | : "cc", "memory" | |
3267 | , R"bx", R"cx", R"dx", R"si", R"di" | |
3268 | #ifdef CONFIG_X86_64 | |
3269 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" | |
3270 | #endif | |
3271 | ); | |
3272 | ||
3273 | vcpu->arch.cr2 = svm->vmcb->save.cr2; | |
3274 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
3275 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
3276 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
3277 | ||
3278 | load_host_msrs(vcpu); | |
3279 | loadsegment(fs, fs_selector); | |
3280 | #ifdef CONFIG_X86_64 | |
3281 | load_gs_index(gs_selector); | |
3282 | wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs); | |
3283 | #else | |
3284 | loadsegment(gs, gs_selector); | |
3285 | #endif | |
3286 | kvm_load_ldt(ldt_selector); | |
3287 | ||
3288 | reload_tss(vcpu); | |
3289 | ||
3290 | local_irq_disable(); | |
3291 | ||
3292 | stgi(); | |
3293 | ||
3294 | sync_cr8_to_lapic(vcpu); | |
3295 | ||
3296 | svm->next_rip = 0; | |
3297 | ||
3298 | if (npt_enabled) { | |
3299 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
3300 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
3301 | } | |
3302 | ||
3303 | /* | |
3304 | * We need to handle MC intercepts here before the vcpu has a chance to | |
3305 | * change the physical cpu | |
3306 | */ | |
3307 | if (unlikely(svm->vmcb->control.exit_code == | |
3308 | SVM_EXIT_EXCP_BASE + MC_VECTOR)) | |
3309 | svm_handle_mce(svm); | |
3310 | } | |
3311 | ||
3312 | #undef R | |
3313 | ||
3314 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) | |
3315 | { | |
3316 | struct vcpu_svm *svm = to_svm(vcpu); | |
3317 | ||
3318 | if (npt_enabled) { | |
3319 | svm->vmcb->control.nested_cr3 = root; | |
3320 | force_new_asid(vcpu); | |
3321 | return; | |
3322 | } | |
3323 | ||
3324 | svm->vmcb->save.cr3 = root; | |
3325 | force_new_asid(vcpu); | |
3326 | } | |
3327 | ||
3328 | static int is_disabled(void) | |
3329 | { | |
3330 | u64 vm_cr; | |
3331 | ||
3332 | rdmsrl(MSR_VM_CR, vm_cr); | |
3333 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
3334 | return 1; | |
3335 | ||
3336 | return 0; | |
3337 | } | |
3338 | ||
3339 | static void | |
3340 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
3341 | { | |
3342 | /* | |
3343 | * Patch in the VMMCALL instruction: | |
3344 | */ | |
3345 | hypercall[0] = 0x0f; | |
3346 | hypercall[1] = 0x01; | |
3347 | hypercall[2] = 0xd9; | |
3348 | } | |
3349 | ||
3350 | static void svm_check_processor_compat(void *rtn) | |
3351 | { | |
3352 | *(int *)rtn = 0; | |
3353 | } | |
3354 | ||
3355 | static bool svm_cpu_has_accelerated_tpr(void) | |
3356 | { | |
3357 | return false; | |
3358 | } | |
3359 | ||
3360 | static int get_npt_level(void) | |
3361 | { | |
3362 | #ifdef CONFIG_X86_64 | |
3363 | return PT64_ROOT_LEVEL; | |
3364 | #else | |
3365 | return PT32E_ROOT_LEVEL; | |
3366 | #endif | |
3367 | } | |
3368 | ||
3369 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) | |
3370 | { | |
3371 | return 0; | |
3372 | } | |
3373 | ||
3374 | static void svm_cpuid_update(struct kvm_vcpu *vcpu) | |
3375 | { | |
3376 | } | |
3377 | ||
3378 | static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) | |
3379 | { | |
3380 | switch (func) { | |
3381 | case 0x8000000A: | |
3382 | entry->eax = 1; /* SVM revision 1 */ | |
3383 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
3384 | ASID emulation to nested SVM */ | |
3385 | entry->ecx = 0; /* Reserved */ | |
3386 | entry->edx = 0; /* Per default do not support any | |
3387 | additional features */ | |
3388 | ||
3389 | /* Support next_rip if host supports it */ | |
3390 | if (svm_has(SVM_FEATURE_NRIP)) | |
3391 | entry->edx |= SVM_FEATURE_NRIP; | |
3392 | ||
3393 | break; | |
3394 | } | |
3395 | } | |
3396 | ||
3397 | static const struct trace_print_flags svm_exit_reasons_str[] = { | |
3398 | { SVM_EXIT_READ_CR0, "read_cr0" }, | |
3399 | { SVM_EXIT_READ_CR3, "read_cr3" }, | |
3400 | { SVM_EXIT_READ_CR4, "read_cr4" }, | |
3401 | { SVM_EXIT_READ_CR8, "read_cr8" }, | |
3402 | { SVM_EXIT_WRITE_CR0, "write_cr0" }, | |
3403 | { SVM_EXIT_WRITE_CR3, "write_cr3" }, | |
3404 | { SVM_EXIT_WRITE_CR4, "write_cr4" }, | |
3405 | { SVM_EXIT_WRITE_CR8, "write_cr8" }, | |
3406 | { SVM_EXIT_READ_DR0, "read_dr0" }, | |
3407 | { SVM_EXIT_READ_DR1, "read_dr1" }, | |
3408 | { SVM_EXIT_READ_DR2, "read_dr2" }, | |
3409 | { SVM_EXIT_READ_DR3, "read_dr3" }, | |
3410 | { SVM_EXIT_WRITE_DR0, "write_dr0" }, | |
3411 | { SVM_EXIT_WRITE_DR1, "write_dr1" }, | |
3412 | { SVM_EXIT_WRITE_DR2, "write_dr2" }, | |
3413 | { SVM_EXIT_WRITE_DR3, "write_dr3" }, | |
3414 | { SVM_EXIT_WRITE_DR5, "write_dr5" }, | |
3415 | { SVM_EXIT_WRITE_DR7, "write_dr7" }, | |
3416 | { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" }, | |
3417 | { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" }, | |
3418 | { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" }, | |
3419 | { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" }, | |
3420 | { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" }, | |
3421 | { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" }, | |
3422 | { SVM_EXIT_INTR, "interrupt" }, | |
3423 | { SVM_EXIT_NMI, "nmi" }, | |
3424 | { SVM_EXIT_SMI, "smi" }, | |
3425 | { SVM_EXIT_INIT, "init" }, | |
3426 | { SVM_EXIT_VINTR, "vintr" }, | |
3427 | { SVM_EXIT_CPUID, "cpuid" }, | |
3428 | { SVM_EXIT_INVD, "invd" }, | |
3429 | { SVM_EXIT_HLT, "hlt" }, | |
3430 | { SVM_EXIT_INVLPG, "invlpg" }, | |
3431 | { SVM_EXIT_INVLPGA, "invlpga" }, | |
3432 | { SVM_EXIT_IOIO, "io" }, | |
3433 | { SVM_EXIT_MSR, "msr" }, | |
3434 | { SVM_EXIT_TASK_SWITCH, "task_switch" }, | |
3435 | { SVM_EXIT_SHUTDOWN, "shutdown" }, | |
3436 | { SVM_EXIT_VMRUN, "vmrun" }, | |
3437 | { SVM_EXIT_VMMCALL, "hypercall" }, | |
3438 | { SVM_EXIT_VMLOAD, "vmload" }, | |
3439 | { SVM_EXIT_VMSAVE, "vmsave" }, | |
3440 | { SVM_EXIT_STGI, "stgi" }, | |
3441 | { SVM_EXIT_CLGI, "clgi" }, | |
3442 | { SVM_EXIT_SKINIT, "skinit" }, | |
3443 | { SVM_EXIT_WBINVD, "wbinvd" }, | |
3444 | { SVM_EXIT_MONITOR, "monitor" }, | |
3445 | { SVM_EXIT_MWAIT, "mwait" }, | |
3446 | { SVM_EXIT_NPF, "npf" }, | |
3447 | { -1, NULL } | |
3448 | }; | |
3449 | ||
3450 | static int svm_get_lpage_level(void) | |
3451 | { | |
3452 | return PT_PDPE_LEVEL; | |
3453 | } | |
3454 | ||
3455 | static bool svm_rdtscp_supported(void) | |
3456 | { | |
3457 | return false; | |
3458 | } | |
3459 | ||
3460 | static bool svm_has_wbinvd_exit(void) | |
3461 | { | |
3462 | return true; | |
3463 | } | |
3464 | ||
3465 | static void svm_fpu_deactivate(struct kvm_vcpu *vcpu) | |
3466 | { | |
3467 | struct vcpu_svm *svm = to_svm(vcpu); | |
3468 | ||
3469 | svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR; | |
3470 | if (is_nested(svm)) | |
3471 | svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR; | |
3472 | update_cr0_intercept(svm); | |
3473 | } | |
3474 | ||
3475 | static struct kvm_x86_ops svm_x86_ops = { | |
3476 | .cpu_has_kvm_support = has_svm, | |
3477 | .disabled_by_bios = is_disabled, | |
3478 | .hardware_setup = svm_hardware_setup, | |
3479 | .hardware_unsetup = svm_hardware_unsetup, | |
3480 | .check_processor_compatibility = svm_check_processor_compat, | |
3481 | .hardware_enable = svm_hardware_enable, | |
3482 | .hardware_disable = svm_hardware_disable, | |
3483 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, | |
3484 | ||
3485 | .vcpu_create = svm_create_vcpu, | |
3486 | .vcpu_free = svm_free_vcpu, | |
3487 | .vcpu_reset = svm_vcpu_reset, | |
3488 | ||
3489 | .prepare_guest_switch = svm_prepare_guest_switch, | |
3490 | .vcpu_load = svm_vcpu_load, | |
3491 | .vcpu_put = svm_vcpu_put, | |
3492 | ||
3493 | .set_guest_debug = svm_guest_debug, | |
3494 | .get_msr = svm_get_msr, | |
3495 | .set_msr = svm_set_msr, | |
3496 | .get_segment_base = svm_get_segment_base, | |
3497 | .get_segment = svm_get_segment, | |
3498 | .set_segment = svm_set_segment, | |
3499 | .get_cpl = svm_get_cpl, | |
3500 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, | |
3501 | .decache_cr0_guest_bits = svm_decache_cr0_guest_bits, | |
3502 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, | |
3503 | .set_cr0 = svm_set_cr0, | |
3504 | .set_cr3 = svm_set_cr3, | |
3505 | .set_cr4 = svm_set_cr4, | |
3506 | .set_efer = svm_set_efer, | |
3507 | .get_idt = svm_get_idt, | |
3508 | .set_idt = svm_set_idt, | |
3509 | .get_gdt = svm_get_gdt, | |
3510 | .set_gdt = svm_set_gdt, | |
3511 | .set_dr7 = svm_set_dr7, | |
3512 | .cache_reg = svm_cache_reg, | |
3513 | .get_rflags = svm_get_rflags, | |
3514 | .set_rflags = svm_set_rflags, | |
3515 | .fpu_activate = svm_fpu_activate, | |
3516 | .fpu_deactivate = svm_fpu_deactivate, | |
3517 | ||
3518 | .tlb_flush = svm_flush_tlb, | |
3519 | ||
3520 | .run = svm_vcpu_run, | |
3521 | .handle_exit = handle_exit, | |
3522 | .skip_emulated_instruction = skip_emulated_instruction, | |
3523 | .set_interrupt_shadow = svm_set_interrupt_shadow, | |
3524 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
3525 | .patch_hypercall = svm_patch_hypercall, | |
3526 | .set_irq = svm_set_irq, | |
3527 | .set_nmi = svm_inject_nmi, | |
3528 | .queue_exception = svm_queue_exception, | |
3529 | .interrupt_allowed = svm_interrupt_allowed, | |
3530 | .nmi_allowed = svm_nmi_allowed, | |
3531 | .get_nmi_mask = svm_get_nmi_mask, | |
3532 | .set_nmi_mask = svm_set_nmi_mask, | |
3533 | .enable_nmi_window = enable_nmi_window, | |
3534 | .enable_irq_window = enable_irq_window, | |
3535 | .update_cr8_intercept = update_cr8_intercept, | |
3536 | ||
3537 | .set_tss_addr = svm_set_tss_addr, | |
3538 | .get_tdp_level = get_npt_level, | |
3539 | .get_mt_mask = svm_get_mt_mask, | |
3540 | ||
3541 | .exit_reasons_str = svm_exit_reasons_str, | |
3542 | .get_lpage_level = svm_get_lpage_level, | |
3543 | ||
3544 | .cpuid_update = svm_cpuid_update, | |
3545 | ||
3546 | .rdtscp_supported = svm_rdtscp_supported, | |
3547 | ||
3548 | .set_supported_cpuid = svm_set_supported_cpuid, | |
3549 | ||
3550 | .has_wbinvd_exit = svm_has_wbinvd_exit, | |
3551 | }; | |
3552 | ||
3553 | static int __init svm_init(void) | |
3554 | { | |
3555 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), | |
3556 | __alignof__(struct vcpu_svm), THIS_MODULE); | |
3557 | } | |
3558 | ||
3559 | static void __exit svm_exit(void) | |
3560 | { | |
3561 | kvm_exit(); | |
3562 | } | |
3563 | ||
3564 | module_init(svm_init) | |
3565 | module_exit(svm_exit) |