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KVM: x86: replace vm_has_apicv hook with cpu_uses_apicv
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
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1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17#include <linux/kvm_host.h>
18
19#include "irq.h"
20#include "mmu.h"
21#include "kvm_cache_regs.h"
22#include "x86.h"
23#include "cpuid.h"
24#include "pmu.h"
25
26#include <linux/module.h>
27#include <linux/mod_devicetable.h>
28#include <linux/kernel.h>
29#include <linux/vmalloc.h>
30#include <linux/highmem.h>
31#include <linux/sched.h>
32#include <linux/trace_events.h>
33#include <linux/slab.h>
34
35#include <asm/perf_event.h>
36#include <asm/tlbflush.h>
37#include <asm/desc.h>
38#include <asm/debugreg.h>
39#include <asm/kvm_para.h>
40
41#include <asm/virtext.h>
42#include "trace.h"
43
44#define __ex(x) __kvm_handle_fault_on_reboot(x)
45
46MODULE_AUTHOR("Qumranet");
47MODULE_LICENSE("GPL");
48
49static const struct x86_cpu_id svm_cpu_id[] = {
50 X86_FEATURE_MATCH(X86_FEATURE_SVM),
51 {}
52};
53MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
54
55#define IOPM_ALLOC_ORDER 2
56#define MSRPM_ALLOC_ORDER 1
57
58#define SEG_TYPE_LDT 2
59#define SEG_TYPE_BUSY_TSS16 3
60
61#define SVM_FEATURE_NPT (1 << 0)
62#define SVM_FEATURE_LBRV (1 << 1)
63#define SVM_FEATURE_SVML (1 << 2)
64#define SVM_FEATURE_NRIP (1 << 3)
65#define SVM_FEATURE_TSC_RATE (1 << 4)
66#define SVM_FEATURE_VMCB_CLEAN (1 << 5)
67#define SVM_FEATURE_FLUSH_ASID (1 << 6)
68#define SVM_FEATURE_DECODE_ASSIST (1 << 7)
69#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
70
71#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
72#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
73#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
74
75#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
76
77#define TSC_RATIO_RSVD 0xffffff0000000000ULL
78#define TSC_RATIO_MIN 0x0000000000000001ULL
79#define TSC_RATIO_MAX 0x000000ffffffffffULL
80
81static bool erratum_383_found __read_mostly;
82
83static const u32 host_save_user_msrs[] = {
84#ifdef CONFIG_X86_64
85 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
86 MSR_FS_BASE,
87#endif
88 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
89};
90
91#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
92
93struct kvm_vcpu;
94
95struct nested_state {
96 struct vmcb *hsave;
97 u64 hsave_msr;
98 u64 vm_cr_msr;
99 u64 vmcb;
100
101 /* These are the merged vectors */
102 u32 *msrpm;
103
104 /* gpa pointers to the real vectors */
105 u64 vmcb_msrpm;
106 u64 vmcb_iopm;
107
108 /* A VMEXIT is required but not yet emulated */
109 bool exit_required;
110
111 /* cache for intercepts of the guest */
112 u32 intercept_cr;
113 u32 intercept_dr;
114 u32 intercept_exceptions;
115 u64 intercept;
116
117 /* Nested Paging related state */
118 u64 nested_cr3;
119};
120
121#define MSRPM_OFFSETS 16
122static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
123
124/*
125 * Set osvw_len to higher value when updated Revision Guides
126 * are published and we know what the new status bits are
127 */
128static uint64_t osvw_len = 4, osvw_status;
129
130struct vcpu_svm {
131 struct kvm_vcpu vcpu;
132 struct vmcb *vmcb;
133 unsigned long vmcb_pa;
134 struct svm_cpu_data *svm_data;
135 uint64_t asid_generation;
136 uint64_t sysenter_esp;
137 uint64_t sysenter_eip;
138
139 u64 next_rip;
140
141 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
142 struct {
143 u16 fs;
144 u16 gs;
145 u16 ldt;
146 u64 gs_base;
147 } host;
148
149 u32 *msrpm;
150
151 ulong nmi_iret_rip;
152
153 struct nested_state nested;
154
155 bool nmi_singlestep;
156
157 unsigned int3_injected;
158 unsigned long int3_rip;
159 u32 apf_reason;
160
161 u64 tsc_ratio;
162};
163
164static DEFINE_PER_CPU(u64, current_tsc_ratio);
165#define TSC_RATIO_DEFAULT 0x0100000000ULL
166
167#define MSR_INVALID 0xffffffffU
168
169static const struct svm_direct_access_msrs {
170 u32 index; /* Index of the MSR */
171 bool always; /* True if intercept is always on */
172} direct_access_msrs[] = {
173 { .index = MSR_STAR, .always = true },
174 { .index = MSR_IA32_SYSENTER_CS, .always = true },
175#ifdef CONFIG_X86_64
176 { .index = MSR_GS_BASE, .always = true },
177 { .index = MSR_FS_BASE, .always = true },
178 { .index = MSR_KERNEL_GS_BASE, .always = true },
179 { .index = MSR_LSTAR, .always = true },
180 { .index = MSR_CSTAR, .always = true },
181 { .index = MSR_SYSCALL_MASK, .always = true },
182#endif
183 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
184 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
185 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
186 { .index = MSR_IA32_LASTINTTOIP, .always = false },
187 { .index = MSR_INVALID, .always = false },
188};
189
190/* enable NPT for AMD64 and X86 with PAE */
191#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
192static bool npt_enabled = true;
193#else
194static bool npt_enabled;
195#endif
196
197/* allow nested paging (virtualized MMU) for all guests */
198static int npt = true;
199module_param(npt, int, S_IRUGO);
200
201/* allow nested virtualization in KVM/SVM */
202static int nested = true;
203module_param(nested, int, S_IRUGO);
204
205static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
206static void svm_flush_tlb(struct kvm_vcpu *vcpu);
207static void svm_complete_interrupts(struct vcpu_svm *svm);
208
209static int nested_svm_exit_handled(struct vcpu_svm *svm);
210static int nested_svm_intercept(struct vcpu_svm *svm);
211static int nested_svm_vmexit(struct vcpu_svm *svm);
212static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
213 bool has_error_code, u32 error_code);
214static u64 __scale_tsc(u64 ratio, u64 tsc);
215
216enum {
217 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
218 pause filter count */
219 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
220 VMCB_ASID, /* ASID */
221 VMCB_INTR, /* int_ctl, int_vector */
222 VMCB_NPT, /* npt_en, nCR3, gPAT */
223 VMCB_CR, /* CR0, CR3, CR4, EFER */
224 VMCB_DR, /* DR6, DR7 */
225 VMCB_DT, /* GDT, IDT */
226 VMCB_SEG, /* CS, DS, SS, ES, CPL */
227 VMCB_CR2, /* CR2 only */
228 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
229 VMCB_DIRTY_MAX,
230};
231
232/* TPR and CR2 are always written before VMRUN */
233#define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
234
235static inline void mark_all_dirty(struct vmcb *vmcb)
236{
237 vmcb->control.clean = 0;
238}
239
240static inline void mark_all_clean(struct vmcb *vmcb)
241{
242 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
243 & ~VMCB_ALWAYS_DIRTY_MASK;
244}
245
246static inline void mark_dirty(struct vmcb *vmcb, int bit)
247{
248 vmcb->control.clean &= ~(1 << bit);
249}
250
251static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
252{
253 return container_of(vcpu, struct vcpu_svm, vcpu);
254}
255
256static void recalc_intercepts(struct vcpu_svm *svm)
257{
258 struct vmcb_control_area *c, *h;
259 struct nested_state *g;
260
261 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
262
263 if (!is_guest_mode(&svm->vcpu))
264 return;
265
266 c = &svm->vmcb->control;
267 h = &svm->nested.hsave->control;
268 g = &svm->nested;
269
270 c->intercept_cr = h->intercept_cr | g->intercept_cr;
271 c->intercept_dr = h->intercept_dr | g->intercept_dr;
272 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
273 c->intercept = h->intercept | g->intercept;
274}
275
276static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
277{
278 if (is_guest_mode(&svm->vcpu))
279 return svm->nested.hsave;
280 else
281 return svm->vmcb;
282}
283
284static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
285{
286 struct vmcb *vmcb = get_host_vmcb(svm);
287
288 vmcb->control.intercept_cr |= (1U << bit);
289
290 recalc_intercepts(svm);
291}
292
293static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
294{
295 struct vmcb *vmcb = get_host_vmcb(svm);
296
297 vmcb->control.intercept_cr &= ~(1U << bit);
298
299 recalc_intercepts(svm);
300}
301
302static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
303{
304 struct vmcb *vmcb = get_host_vmcb(svm);
305
306 return vmcb->control.intercept_cr & (1U << bit);
307}
308
309static inline void set_dr_intercepts(struct vcpu_svm *svm)
310{
311 struct vmcb *vmcb = get_host_vmcb(svm);
312
313 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
314 | (1 << INTERCEPT_DR1_READ)
315 | (1 << INTERCEPT_DR2_READ)
316 | (1 << INTERCEPT_DR3_READ)
317 | (1 << INTERCEPT_DR4_READ)
318 | (1 << INTERCEPT_DR5_READ)
319 | (1 << INTERCEPT_DR6_READ)
320 | (1 << INTERCEPT_DR7_READ)
321 | (1 << INTERCEPT_DR0_WRITE)
322 | (1 << INTERCEPT_DR1_WRITE)
323 | (1 << INTERCEPT_DR2_WRITE)
324 | (1 << INTERCEPT_DR3_WRITE)
325 | (1 << INTERCEPT_DR4_WRITE)
326 | (1 << INTERCEPT_DR5_WRITE)
327 | (1 << INTERCEPT_DR6_WRITE)
328 | (1 << INTERCEPT_DR7_WRITE);
329
330 recalc_intercepts(svm);
331}
332
333static inline void clr_dr_intercepts(struct vcpu_svm *svm)
334{
335 struct vmcb *vmcb = get_host_vmcb(svm);
336
337 vmcb->control.intercept_dr = 0;
338
339 recalc_intercepts(svm);
340}
341
342static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
343{
344 struct vmcb *vmcb = get_host_vmcb(svm);
345
346 vmcb->control.intercept_exceptions |= (1U << bit);
347
348 recalc_intercepts(svm);
349}
350
351static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
352{
353 struct vmcb *vmcb = get_host_vmcb(svm);
354
355 vmcb->control.intercept_exceptions &= ~(1U << bit);
356
357 recalc_intercepts(svm);
358}
359
360static inline void set_intercept(struct vcpu_svm *svm, int bit)
361{
362 struct vmcb *vmcb = get_host_vmcb(svm);
363
364 vmcb->control.intercept |= (1ULL << bit);
365
366 recalc_intercepts(svm);
367}
368
369static inline void clr_intercept(struct vcpu_svm *svm, int bit)
370{
371 struct vmcb *vmcb = get_host_vmcb(svm);
372
373 vmcb->control.intercept &= ~(1ULL << bit);
374
375 recalc_intercepts(svm);
376}
377
378static inline void enable_gif(struct vcpu_svm *svm)
379{
380 svm->vcpu.arch.hflags |= HF_GIF_MASK;
381}
382
383static inline void disable_gif(struct vcpu_svm *svm)
384{
385 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
386}
387
388static inline bool gif_set(struct vcpu_svm *svm)
389{
390 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
391}
392
393static unsigned long iopm_base;
394
395struct kvm_ldttss_desc {
396 u16 limit0;
397 u16 base0;
398 unsigned base1:8, type:5, dpl:2, p:1;
399 unsigned limit1:4, zero0:3, g:1, base2:8;
400 u32 base3;
401 u32 zero1;
402} __attribute__((packed));
403
404struct svm_cpu_data {
405 int cpu;
406
407 u64 asid_generation;
408 u32 max_asid;
409 u32 next_asid;
410 struct kvm_ldttss_desc *tss_desc;
411
412 struct page *save_area;
413};
414
415static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
416
417struct svm_init_data {
418 int cpu;
419 int r;
420};
421
422static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
423
424#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
425#define MSRS_RANGE_SIZE 2048
426#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
427
428static u32 svm_msrpm_offset(u32 msr)
429{
430 u32 offset;
431 int i;
432
433 for (i = 0; i < NUM_MSR_MAPS; i++) {
434 if (msr < msrpm_ranges[i] ||
435 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
436 continue;
437
438 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
439 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
440
441 /* Now we have the u8 offset - but need the u32 offset */
442 return offset / 4;
443 }
444
445 /* MSR not in any range */
446 return MSR_INVALID;
447}
448
449#define MAX_INST_SIZE 15
450
451static inline void clgi(void)
452{
453 asm volatile (__ex(SVM_CLGI));
454}
455
456static inline void stgi(void)
457{
458 asm volatile (__ex(SVM_STGI));
459}
460
461static inline void invlpga(unsigned long addr, u32 asid)
462{
463 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
464}
465
466static int get_npt_level(void)
467{
468#ifdef CONFIG_X86_64
469 return PT64_ROOT_LEVEL;
470#else
471 return PT32E_ROOT_LEVEL;
472#endif
473}
474
475static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
476{
477 vcpu->arch.efer = efer;
478 if (!npt_enabled && !(efer & EFER_LMA))
479 efer &= ~EFER_LME;
480
481 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
482 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
483}
484
485static int is_external_interrupt(u32 info)
486{
487 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
488 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
489}
490
491static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
492{
493 struct vcpu_svm *svm = to_svm(vcpu);
494 u32 ret = 0;
495
496 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
497 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
498 return ret;
499}
500
501static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
502{
503 struct vcpu_svm *svm = to_svm(vcpu);
504
505 if (mask == 0)
506 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
507 else
508 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
509
510}
511
512static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
513{
514 struct vcpu_svm *svm = to_svm(vcpu);
515
516 if (svm->vmcb->control.next_rip != 0) {
517 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
518 svm->next_rip = svm->vmcb->control.next_rip;
519 }
520
521 if (!svm->next_rip) {
522 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
523 EMULATE_DONE)
524 printk(KERN_DEBUG "%s: NOP\n", __func__);
525 return;
526 }
527 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
528 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
529 __func__, kvm_rip_read(vcpu), svm->next_rip);
530
531 kvm_rip_write(vcpu, svm->next_rip);
532 svm_set_interrupt_shadow(vcpu, 0);
533}
534
535static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
536 bool has_error_code, u32 error_code,
537 bool reinject)
538{
539 struct vcpu_svm *svm = to_svm(vcpu);
540
541 /*
542 * If we are within a nested VM we'd better #VMEXIT and let the guest
543 * handle the exception
544 */
545 if (!reinject &&
546 nested_svm_check_exception(svm, nr, has_error_code, error_code))
547 return;
548
549 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
550 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
551
552 /*
553 * For guest debugging where we have to reinject #BP if some
554 * INT3 is guest-owned:
555 * Emulate nRIP by moving RIP forward. Will fail if injection
556 * raises a fault that is not intercepted. Still better than
557 * failing in all cases.
558 */
559 skip_emulated_instruction(&svm->vcpu);
560 rip = kvm_rip_read(&svm->vcpu);
561 svm->int3_rip = rip + svm->vmcb->save.cs.base;
562 svm->int3_injected = rip - old_rip;
563 }
564
565 svm->vmcb->control.event_inj = nr
566 | SVM_EVTINJ_VALID
567 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
568 | SVM_EVTINJ_TYPE_EXEPT;
569 svm->vmcb->control.event_inj_err = error_code;
570}
571
572static void svm_init_erratum_383(void)
573{
574 u32 low, high;
575 int err;
576 u64 val;
577
578 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
579 return;
580
581 /* Use _safe variants to not break nested virtualization */
582 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
583 if (err)
584 return;
585
586 val |= (1ULL << 47);
587
588 low = lower_32_bits(val);
589 high = upper_32_bits(val);
590
591 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
592
593 erratum_383_found = true;
594}
595
596static void svm_init_osvw(struct kvm_vcpu *vcpu)
597{
598 /*
599 * Guests should see errata 400 and 415 as fixed (assuming that
600 * HLT and IO instructions are intercepted).
601 */
602 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
603 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
604
605 /*
606 * By increasing VCPU's osvw.length to 3 we are telling the guest that
607 * all osvw.status bits inside that length, including bit 0 (which is
608 * reserved for erratum 298), are valid. However, if host processor's
609 * osvw_len is 0 then osvw_status[0] carries no information. We need to
610 * be conservative here and therefore we tell the guest that erratum 298
611 * is present (because we really don't know).
612 */
613 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
614 vcpu->arch.osvw.status |= 1;
615}
616
617static int has_svm(void)
618{
619 const char *msg;
620
621 if (!cpu_has_svm(&msg)) {
622 printk(KERN_INFO "has_svm: %s\n", msg);
623 return 0;
624 }
625
626 return 1;
627}
628
629static void svm_hardware_disable(void)
630{
631 /* Make sure we clean up behind us */
632 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
633 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
634
635 cpu_svm_disable();
636
637 amd_pmu_disable_virt();
638}
639
640static int svm_hardware_enable(void)
641{
642
643 struct svm_cpu_data *sd;
644 uint64_t efer;
645 struct desc_ptr gdt_descr;
646 struct desc_struct *gdt;
647 int me = raw_smp_processor_id();
648
649 rdmsrl(MSR_EFER, efer);
650 if (efer & EFER_SVME)
651 return -EBUSY;
652
653 if (!has_svm()) {
654 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
655 return -EINVAL;
656 }
657 sd = per_cpu(svm_data, me);
658 if (!sd) {
659 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
660 return -EINVAL;
661 }
662
663 sd->asid_generation = 1;
664 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
665 sd->next_asid = sd->max_asid + 1;
666
667 native_store_gdt(&gdt_descr);
668 gdt = (struct desc_struct *)gdt_descr.address;
669 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
670
671 wrmsrl(MSR_EFER, efer | EFER_SVME);
672
673 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
674
675 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
676 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
677 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
678 }
679
680
681 /*
682 * Get OSVW bits.
683 *
684 * Note that it is possible to have a system with mixed processor
685 * revisions and therefore different OSVW bits. If bits are not the same
686 * on different processors then choose the worst case (i.e. if erratum
687 * is present on one processor and not on another then assume that the
688 * erratum is present everywhere).
689 */
690 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
691 uint64_t len, status = 0;
692 int err;
693
694 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
695 if (!err)
696 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
697 &err);
698
699 if (err)
700 osvw_status = osvw_len = 0;
701 else {
702 if (len < osvw_len)
703 osvw_len = len;
704 osvw_status |= status;
705 osvw_status &= (1ULL << osvw_len) - 1;
706 }
707 } else
708 osvw_status = osvw_len = 0;
709
710 svm_init_erratum_383();
711
712 amd_pmu_enable_virt();
713
714 return 0;
715}
716
717static void svm_cpu_uninit(int cpu)
718{
719 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
720
721 if (!sd)
722 return;
723
724 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
725 __free_page(sd->save_area);
726 kfree(sd);
727}
728
729static int svm_cpu_init(int cpu)
730{
731 struct svm_cpu_data *sd;
732 int r;
733
734 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
735 if (!sd)
736 return -ENOMEM;
737 sd->cpu = cpu;
738 sd->save_area = alloc_page(GFP_KERNEL);
739 r = -ENOMEM;
740 if (!sd->save_area)
741 goto err_1;
742
743 per_cpu(svm_data, cpu) = sd;
744
745 return 0;
746
747err_1:
748 kfree(sd);
749 return r;
750
751}
752
753static bool valid_msr_intercept(u32 index)
754{
755 int i;
756
757 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
758 if (direct_access_msrs[i].index == index)
759 return true;
760
761 return false;
762}
763
764static void set_msr_interception(u32 *msrpm, unsigned msr,
765 int read, int write)
766{
767 u8 bit_read, bit_write;
768 unsigned long tmp;
769 u32 offset;
770
771 /*
772 * If this warning triggers extend the direct_access_msrs list at the
773 * beginning of the file
774 */
775 WARN_ON(!valid_msr_intercept(msr));
776
777 offset = svm_msrpm_offset(msr);
778 bit_read = 2 * (msr & 0x0f);
779 bit_write = 2 * (msr & 0x0f) + 1;
780 tmp = msrpm[offset];
781
782 BUG_ON(offset == MSR_INVALID);
783
784 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
785 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
786
787 msrpm[offset] = tmp;
788}
789
790static void svm_vcpu_init_msrpm(u32 *msrpm)
791{
792 int i;
793
794 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
795
796 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
797 if (!direct_access_msrs[i].always)
798 continue;
799
800 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
801 }
802}
803
804static void add_msr_offset(u32 offset)
805{
806 int i;
807
808 for (i = 0; i < MSRPM_OFFSETS; ++i) {
809
810 /* Offset already in list? */
811 if (msrpm_offsets[i] == offset)
812 return;
813
814 /* Slot used by another offset? */
815 if (msrpm_offsets[i] != MSR_INVALID)
816 continue;
817
818 /* Add offset to list */
819 msrpm_offsets[i] = offset;
820
821 return;
822 }
823
824 /*
825 * If this BUG triggers the msrpm_offsets table has an overflow. Just
826 * increase MSRPM_OFFSETS in this case.
827 */
828 BUG();
829}
830
831static void init_msrpm_offsets(void)
832{
833 int i;
834
835 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
836
837 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
838 u32 offset;
839
840 offset = svm_msrpm_offset(direct_access_msrs[i].index);
841 BUG_ON(offset == MSR_INVALID);
842
843 add_msr_offset(offset);
844 }
845}
846
847static void svm_enable_lbrv(struct vcpu_svm *svm)
848{
849 u32 *msrpm = svm->msrpm;
850
851 svm->vmcb->control.lbr_ctl = 1;
852 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
853 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
854 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
855 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
856}
857
858static void svm_disable_lbrv(struct vcpu_svm *svm)
859{
860 u32 *msrpm = svm->msrpm;
861
862 svm->vmcb->control.lbr_ctl = 0;
863 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
864 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
865 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
866 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
867}
868
869static __init int svm_hardware_setup(void)
870{
871 int cpu;
872 struct page *iopm_pages;
873 void *iopm_va;
874 int r;
875
876 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
877
878 if (!iopm_pages)
879 return -ENOMEM;
880
881 iopm_va = page_address(iopm_pages);
882 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
883 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
884
885 init_msrpm_offsets();
886
887 if (boot_cpu_has(X86_FEATURE_NX))
888 kvm_enable_efer_bits(EFER_NX);
889
890 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
891 kvm_enable_efer_bits(EFER_FFXSR);
892
893 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
894 u64 max;
895
896 kvm_has_tsc_control = true;
897
898 /*
899 * Make sure the user can only configure tsc_khz values that
900 * fit into a signed integer.
901 * A min value is not calculated needed because it will always
902 * be 1 on all machines and a value of 0 is used to disable
903 * tsc-scaling for the vcpu.
904 */
905 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
906
907 kvm_max_guest_tsc_khz = max;
908 }
909
910 if (nested) {
911 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
912 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
913 }
914
915 for_each_possible_cpu(cpu) {
916 r = svm_cpu_init(cpu);
917 if (r)
918 goto err;
919 }
920
921 if (!boot_cpu_has(X86_FEATURE_NPT))
922 npt_enabled = false;
923
924 if (npt_enabled && !npt) {
925 printk(KERN_INFO "kvm: Nested Paging disabled\n");
926 npt_enabled = false;
927 }
928
929 if (npt_enabled) {
930 printk(KERN_INFO "kvm: Nested Paging enabled\n");
931 kvm_enable_tdp();
932 } else
933 kvm_disable_tdp();
934
935 return 0;
936
937err:
938 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
939 iopm_base = 0;
940 return r;
941}
942
943static __exit void svm_hardware_unsetup(void)
944{
945 int cpu;
946
947 for_each_possible_cpu(cpu)
948 svm_cpu_uninit(cpu);
949
950 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
951 iopm_base = 0;
952}
953
954static void init_seg(struct vmcb_seg *seg)
955{
956 seg->selector = 0;
957 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
958 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
959 seg->limit = 0xffff;
960 seg->base = 0;
961}
962
963static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
964{
965 seg->selector = 0;
966 seg->attrib = SVM_SELECTOR_P_MASK | type;
967 seg->limit = 0xffff;
968 seg->base = 0;
969}
970
971static u64 __scale_tsc(u64 ratio, u64 tsc)
972{
973 u64 mult, frac, _tsc;
974
975 mult = ratio >> 32;
976 frac = ratio & ((1ULL << 32) - 1);
977
978 _tsc = tsc;
979 _tsc *= mult;
980 _tsc += (tsc >> 32) * frac;
981 _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
982
983 return _tsc;
984}
985
986static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
987{
988 struct vcpu_svm *svm = to_svm(vcpu);
989 u64 _tsc = tsc;
990
991 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
992 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
993
994 return _tsc;
995}
996
997static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
998{
999 struct vcpu_svm *svm = to_svm(vcpu);
1000 u64 ratio;
1001 u64 khz;
1002
1003 /* Guest TSC same frequency as host TSC? */
1004 if (!scale) {
1005 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1006 return;
1007 }
1008
1009 /* TSC scaling supported? */
1010 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1011 if (user_tsc_khz > tsc_khz) {
1012 vcpu->arch.tsc_catchup = 1;
1013 vcpu->arch.tsc_always_catchup = 1;
1014 } else
1015 WARN(1, "user requested TSC rate below hardware speed\n");
1016 return;
1017 }
1018
1019 khz = user_tsc_khz;
1020
1021 /* TSC scaling required - calculate ratio */
1022 ratio = khz << 32;
1023 do_div(ratio, tsc_khz);
1024
1025 if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
1026 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
1027 user_tsc_khz);
1028 return;
1029 }
1030 svm->tsc_ratio = ratio;
1031}
1032
1033static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu)
1034{
1035 struct vcpu_svm *svm = to_svm(vcpu);
1036
1037 return svm->vmcb->control.tsc_offset;
1038}
1039
1040static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1041{
1042 struct vcpu_svm *svm = to_svm(vcpu);
1043 u64 g_tsc_offset = 0;
1044
1045 if (is_guest_mode(vcpu)) {
1046 g_tsc_offset = svm->vmcb->control.tsc_offset -
1047 svm->nested.hsave->control.tsc_offset;
1048 svm->nested.hsave->control.tsc_offset = offset;
1049 } else
1050 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1051 svm->vmcb->control.tsc_offset,
1052 offset);
1053
1054 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1055
1056 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1057}
1058
1059static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1060{
1061 struct vcpu_svm *svm = to_svm(vcpu);
1062
1063 if (host) {
1064 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
1065 WARN_ON(adjustment < 0);
1066 adjustment = svm_scale_tsc(vcpu, (u64)adjustment);
1067 }
1068
1069 svm->vmcb->control.tsc_offset += adjustment;
1070 if (is_guest_mode(vcpu))
1071 svm->nested.hsave->control.tsc_offset += adjustment;
1072 else
1073 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1074 svm->vmcb->control.tsc_offset - adjustment,
1075 svm->vmcb->control.tsc_offset);
1076
1077 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1078}
1079
1080static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1081{
1082 u64 tsc;
1083
1084 tsc = svm_scale_tsc(vcpu, rdtsc());
1085
1086 return target_tsc - tsc;
1087}
1088
1089static void init_vmcb(struct vcpu_svm *svm, bool init_event)
1090{
1091 struct vmcb_control_area *control = &svm->vmcb->control;
1092 struct vmcb_save_area *save = &svm->vmcb->save;
1093
1094 svm->vcpu.fpu_active = 1;
1095 svm->vcpu.arch.hflags = 0;
1096
1097 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1098 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1099 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1100 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1101 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1102 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1103 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1104
1105 set_dr_intercepts(svm);
1106
1107 set_exception_intercept(svm, PF_VECTOR);
1108 set_exception_intercept(svm, UD_VECTOR);
1109 set_exception_intercept(svm, MC_VECTOR);
1110
1111 set_intercept(svm, INTERCEPT_INTR);
1112 set_intercept(svm, INTERCEPT_NMI);
1113 set_intercept(svm, INTERCEPT_SMI);
1114 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1115 set_intercept(svm, INTERCEPT_RDPMC);
1116 set_intercept(svm, INTERCEPT_CPUID);
1117 set_intercept(svm, INTERCEPT_INVD);
1118 set_intercept(svm, INTERCEPT_HLT);
1119 set_intercept(svm, INTERCEPT_INVLPG);
1120 set_intercept(svm, INTERCEPT_INVLPGA);
1121 set_intercept(svm, INTERCEPT_IOIO_PROT);
1122 set_intercept(svm, INTERCEPT_MSR_PROT);
1123 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1124 set_intercept(svm, INTERCEPT_SHUTDOWN);
1125 set_intercept(svm, INTERCEPT_VMRUN);
1126 set_intercept(svm, INTERCEPT_VMMCALL);
1127 set_intercept(svm, INTERCEPT_VMLOAD);
1128 set_intercept(svm, INTERCEPT_VMSAVE);
1129 set_intercept(svm, INTERCEPT_STGI);
1130 set_intercept(svm, INTERCEPT_CLGI);
1131 set_intercept(svm, INTERCEPT_SKINIT);
1132 set_intercept(svm, INTERCEPT_WBINVD);
1133 set_intercept(svm, INTERCEPT_MONITOR);
1134 set_intercept(svm, INTERCEPT_MWAIT);
1135 set_intercept(svm, INTERCEPT_XSETBV);
1136
1137 control->iopm_base_pa = iopm_base;
1138 control->msrpm_base_pa = __pa(svm->msrpm);
1139 control->int_ctl = V_INTR_MASKING_MASK;
1140
1141 init_seg(&save->es);
1142 init_seg(&save->ss);
1143 init_seg(&save->ds);
1144 init_seg(&save->fs);
1145 init_seg(&save->gs);
1146
1147 save->cs.selector = 0xf000;
1148 save->cs.base = 0xffff0000;
1149 /* Executable/Readable Code Segment */
1150 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1151 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1152 save->cs.limit = 0xffff;
1153
1154 save->gdtr.limit = 0xffff;
1155 save->idtr.limit = 0xffff;
1156
1157 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1158 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1159
1160 if (!init_event)
1161 svm_set_efer(&svm->vcpu, 0);
1162 save->dr6 = 0xffff0ff0;
1163 kvm_set_rflags(&svm->vcpu, 2);
1164 save->rip = 0x0000fff0;
1165 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1166
1167 /*
1168 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1169 * It also updates the guest-visible cr0 value.
1170 */
1171 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1172 kvm_mmu_reset_context(&svm->vcpu);
1173
1174 save->cr4 = X86_CR4_PAE;
1175 /* rdx = ?? */
1176
1177 if (npt_enabled) {
1178 /* Setup VMCB for Nested Paging */
1179 control->nested_ctl = 1;
1180 clr_intercept(svm, INTERCEPT_INVLPG);
1181 clr_exception_intercept(svm, PF_VECTOR);
1182 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1183 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1184 save->g_pat = svm->vcpu.arch.pat;
1185 save->cr3 = 0;
1186 save->cr4 = 0;
1187 }
1188 svm->asid_generation = 0;
1189
1190 svm->nested.vmcb = 0;
1191 svm->vcpu.arch.hflags = 0;
1192
1193 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1194 control->pause_filter_count = 3000;
1195 set_intercept(svm, INTERCEPT_PAUSE);
1196 }
1197
1198 mark_all_dirty(svm->vmcb);
1199
1200 enable_gif(svm);
1201}
1202
1203static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1204{
1205 struct vcpu_svm *svm = to_svm(vcpu);
1206 u32 dummy;
1207 u32 eax = 1;
1208
1209 if (!init_event) {
1210 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1211 MSR_IA32_APICBASE_ENABLE;
1212 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1213 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1214 }
1215 init_vmcb(svm, init_event);
1216
1217 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1218 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1219}
1220
1221static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1222{
1223 struct vcpu_svm *svm;
1224 struct page *page;
1225 struct page *msrpm_pages;
1226 struct page *hsave_page;
1227 struct page *nested_msrpm_pages;
1228 int err;
1229
1230 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1231 if (!svm) {
1232 err = -ENOMEM;
1233 goto out;
1234 }
1235
1236 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1237
1238 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1239 if (err)
1240 goto free_svm;
1241
1242 err = -ENOMEM;
1243 page = alloc_page(GFP_KERNEL);
1244 if (!page)
1245 goto uninit;
1246
1247 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1248 if (!msrpm_pages)
1249 goto free_page1;
1250
1251 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1252 if (!nested_msrpm_pages)
1253 goto free_page2;
1254
1255 hsave_page = alloc_page(GFP_KERNEL);
1256 if (!hsave_page)
1257 goto free_page3;
1258
1259 svm->nested.hsave = page_address(hsave_page);
1260
1261 svm->msrpm = page_address(msrpm_pages);
1262 svm_vcpu_init_msrpm(svm->msrpm);
1263
1264 svm->nested.msrpm = page_address(nested_msrpm_pages);
1265 svm_vcpu_init_msrpm(svm->nested.msrpm);
1266
1267 svm->vmcb = page_address(page);
1268 clear_page(svm->vmcb);
1269 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1270 svm->asid_generation = 0;
1271 init_vmcb(svm, false);
1272
1273 svm_init_osvw(&svm->vcpu);
1274
1275 return &svm->vcpu;
1276
1277free_page3:
1278 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1279free_page2:
1280 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1281free_page1:
1282 __free_page(page);
1283uninit:
1284 kvm_vcpu_uninit(&svm->vcpu);
1285free_svm:
1286 kmem_cache_free(kvm_vcpu_cache, svm);
1287out:
1288 return ERR_PTR(err);
1289}
1290
1291static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1292{
1293 struct vcpu_svm *svm = to_svm(vcpu);
1294
1295 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1296 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1297 __free_page(virt_to_page(svm->nested.hsave));
1298 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1299 kvm_vcpu_uninit(vcpu);
1300 kmem_cache_free(kvm_vcpu_cache, svm);
1301}
1302
1303static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1304{
1305 struct vcpu_svm *svm = to_svm(vcpu);
1306 int i;
1307
1308 if (unlikely(cpu != vcpu->cpu)) {
1309 svm->asid_generation = 0;
1310 mark_all_dirty(svm->vmcb);
1311 }
1312
1313#ifdef CONFIG_X86_64
1314 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1315#endif
1316 savesegment(fs, svm->host.fs);
1317 savesegment(gs, svm->host.gs);
1318 svm->host.ldt = kvm_read_ldt();
1319
1320 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1321 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1322
1323 if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1324 svm->tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1325 __this_cpu_write(current_tsc_ratio, svm->tsc_ratio);
1326 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1327 }
1328}
1329
1330static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1331{
1332 struct vcpu_svm *svm = to_svm(vcpu);
1333 int i;
1334
1335 ++vcpu->stat.host_state_reload;
1336 kvm_load_ldt(svm->host.ldt);
1337#ifdef CONFIG_X86_64
1338 loadsegment(fs, svm->host.fs);
1339 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1340 load_gs_index(svm->host.gs);
1341#else
1342#ifdef CONFIG_X86_32_LAZY_GS
1343 loadsegment(gs, svm->host.gs);
1344#endif
1345#endif
1346 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1347 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1348}
1349
1350static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1351{
1352 return to_svm(vcpu)->vmcb->save.rflags;
1353}
1354
1355static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1356{
1357 /*
1358 * Any change of EFLAGS.VM is accompained by a reload of SS
1359 * (caused by either a task switch or an inter-privilege IRET),
1360 * so we do not need to update the CPL here.
1361 */
1362 to_svm(vcpu)->vmcb->save.rflags = rflags;
1363}
1364
1365static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1366{
1367 switch (reg) {
1368 case VCPU_EXREG_PDPTR:
1369 BUG_ON(!npt_enabled);
1370 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1371 break;
1372 default:
1373 BUG();
1374 }
1375}
1376
1377static void svm_set_vintr(struct vcpu_svm *svm)
1378{
1379 set_intercept(svm, INTERCEPT_VINTR);
1380}
1381
1382static void svm_clear_vintr(struct vcpu_svm *svm)
1383{
1384 clr_intercept(svm, INTERCEPT_VINTR);
1385}
1386
1387static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1388{
1389 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1390
1391 switch (seg) {
1392 case VCPU_SREG_CS: return &save->cs;
1393 case VCPU_SREG_DS: return &save->ds;
1394 case VCPU_SREG_ES: return &save->es;
1395 case VCPU_SREG_FS: return &save->fs;
1396 case VCPU_SREG_GS: return &save->gs;
1397 case VCPU_SREG_SS: return &save->ss;
1398 case VCPU_SREG_TR: return &save->tr;
1399 case VCPU_SREG_LDTR: return &save->ldtr;
1400 }
1401 BUG();
1402 return NULL;
1403}
1404
1405static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1406{
1407 struct vmcb_seg *s = svm_seg(vcpu, seg);
1408
1409 return s->base;
1410}
1411
1412static void svm_get_segment(struct kvm_vcpu *vcpu,
1413 struct kvm_segment *var, int seg)
1414{
1415 struct vmcb_seg *s = svm_seg(vcpu, seg);
1416
1417 var->base = s->base;
1418 var->limit = s->limit;
1419 var->selector = s->selector;
1420 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1421 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1422 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1423 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1424 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1425 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1426 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1427
1428 /*
1429 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1430 * However, the SVM spec states that the G bit is not observed by the
1431 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1432 * So let's synthesize a legal G bit for all segments, this helps
1433 * running KVM nested. It also helps cross-vendor migration, because
1434 * Intel's vmentry has a check on the 'G' bit.
1435 */
1436 var->g = s->limit > 0xfffff;
1437
1438 /*
1439 * AMD's VMCB does not have an explicit unusable field, so emulate it
1440 * for cross vendor migration purposes by "not present"
1441 */
1442 var->unusable = !var->present || (var->type == 0);
1443
1444 switch (seg) {
1445 case VCPU_SREG_TR:
1446 /*
1447 * Work around a bug where the busy flag in the tr selector
1448 * isn't exposed
1449 */
1450 var->type |= 0x2;
1451 break;
1452 case VCPU_SREG_DS:
1453 case VCPU_SREG_ES:
1454 case VCPU_SREG_FS:
1455 case VCPU_SREG_GS:
1456 /*
1457 * The accessed bit must always be set in the segment
1458 * descriptor cache, although it can be cleared in the
1459 * descriptor, the cached bit always remains at 1. Since
1460 * Intel has a check on this, set it here to support
1461 * cross-vendor migration.
1462 */
1463 if (!var->unusable)
1464 var->type |= 0x1;
1465 break;
1466 case VCPU_SREG_SS:
1467 /*
1468 * On AMD CPUs sometimes the DB bit in the segment
1469 * descriptor is left as 1, although the whole segment has
1470 * been made unusable. Clear it here to pass an Intel VMX
1471 * entry check when cross vendor migrating.
1472 */
1473 if (var->unusable)
1474 var->db = 0;
1475 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1476 break;
1477 }
1478}
1479
1480static int svm_get_cpl(struct kvm_vcpu *vcpu)
1481{
1482 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1483
1484 return save->cpl;
1485}
1486
1487static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1488{
1489 struct vcpu_svm *svm = to_svm(vcpu);
1490
1491 dt->size = svm->vmcb->save.idtr.limit;
1492 dt->address = svm->vmcb->save.idtr.base;
1493}
1494
1495static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1496{
1497 struct vcpu_svm *svm = to_svm(vcpu);
1498
1499 svm->vmcb->save.idtr.limit = dt->size;
1500 svm->vmcb->save.idtr.base = dt->address ;
1501 mark_dirty(svm->vmcb, VMCB_DT);
1502}
1503
1504static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1505{
1506 struct vcpu_svm *svm = to_svm(vcpu);
1507
1508 dt->size = svm->vmcb->save.gdtr.limit;
1509 dt->address = svm->vmcb->save.gdtr.base;
1510}
1511
1512static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1513{
1514 struct vcpu_svm *svm = to_svm(vcpu);
1515
1516 svm->vmcb->save.gdtr.limit = dt->size;
1517 svm->vmcb->save.gdtr.base = dt->address ;
1518 mark_dirty(svm->vmcb, VMCB_DT);
1519}
1520
1521static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1522{
1523}
1524
1525static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1526{
1527}
1528
1529static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1530{
1531}
1532
1533static void update_cr0_intercept(struct vcpu_svm *svm)
1534{
1535 ulong gcr0 = svm->vcpu.arch.cr0;
1536 u64 *hcr0 = &svm->vmcb->save.cr0;
1537
1538 if (!svm->vcpu.fpu_active)
1539 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1540 else
1541 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1542 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1543
1544 mark_dirty(svm->vmcb, VMCB_CR);
1545
1546 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1547 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1548 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1549 } else {
1550 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1551 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1552 }
1553}
1554
1555static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1556{
1557 struct vcpu_svm *svm = to_svm(vcpu);
1558
1559#ifdef CONFIG_X86_64
1560 if (vcpu->arch.efer & EFER_LME) {
1561 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1562 vcpu->arch.efer |= EFER_LMA;
1563 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1564 }
1565
1566 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1567 vcpu->arch.efer &= ~EFER_LMA;
1568 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1569 }
1570 }
1571#endif
1572 vcpu->arch.cr0 = cr0;
1573
1574 if (!npt_enabled)
1575 cr0 |= X86_CR0_PG | X86_CR0_WP;
1576
1577 if (!vcpu->fpu_active)
1578 cr0 |= X86_CR0_TS;
1579 /*
1580 * re-enable caching here because the QEMU bios
1581 * does not do it - this results in some delay at
1582 * reboot
1583 */
1584 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1585 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1586 svm->vmcb->save.cr0 = cr0;
1587 mark_dirty(svm->vmcb, VMCB_CR);
1588 update_cr0_intercept(svm);
1589}
1590
1591static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1592{
1593 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1594 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1595
1596 if (cr4 & X86_CR4_VMXE)
1597 return 1;
1598
1599 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1600 svm_flush_tlb(vcpu);
1601
1602 vcpu->arch.cr4 = cr4;
1603 if (!npt_enabled)
1604 cr4 |= X86_CR4_PAE;
1605 cr4 |= host_cr4_mce;
1606 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1607 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1608 return 0;
1609}
1610
1611static void svm_set_segment(struct kvm_vcpu *vcpu,
1612 struct kvm_segment *var, int seg)
1613{
1614 struct vcpu_svm *svm = to_svm(vcpu);
1615 struct vmcb_seg *s = svm_seg(vcpu, seg);
1616
1617 s->base = var->base;
1618 s->limit = var->limit;
1619 s->selector = var->selector;
1620 if (var->unusable)
1621 s->attrib = 0;
1622 else {
1623 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1624 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1625 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1626 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1627 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1628 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1629 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1630 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1631 }
1632
1633 /*
1634 * This is always accurate, except if SYSRET returned to a segment
1635 * with SS.DPL != 3. Intel does not have this quirk, and always
1636 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1637 * would entail passing the CPL to userspace and back.
1638 */
1639 if (seg == VCPU_SREG_SS)
1640 svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1641
1642 mark_dirty(svm->vmcb, VMCB_SEG);
1643}
1644
1645static void update_db_bp_intercept(struct kvm_vcpu *vcpu)
1646{
1647 struct vcpu_svm *svm = to_svm(vcpu);
1648
1649 clr_exception_intercept(svm, DB_VECTOR);
1650 clr_exception_intercept(svm, BP_VECTOR);
1651
1652 if (svm->nmi_singlestep)
1653 set_exception_intercept(svm, DB_VECTOR);
1654
1655 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1656 if (vcpu->guest_debug &
1657 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1658 set_exception_intercept(svm, DB_VECTOR);
1659 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1660 set_exception_intercept(svm, BP_VECTOR);
1661 } else
1662 vcpu->guest_debug = 0;
1663}
1664
1665static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1666{
1667 if (sd->next_asid > sd->max_asid) {
1668 ++sd->asid_generation;
1669 sd->next_asid = 1;
1670 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1671 }
1672
1673 svm->asid_generation = sd->asid_generation;
1674 svm->vmcb->control.asid = sd->next_asid++;
1675
1676 mark_dirty(svm->vmcb, VMCB_ASID);
1677}
1678
1679static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
1680{
1681 return to_svm(vcpu)->vmcb->save.dr6;
1682}
1683
1684static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
1685{
1686 struct vcpu_svm *svm = to_svm(vcpu);
1687
1688 svm->vmcb->save.dr6 = value;
1689 mark_dirty(svm->vmcb, VMCB_DR);
1690}
1691
1692static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1693{
1694 struct vcpu_svm *svm = to_svm(vcpu);
1695
1696 get_debugreg(vcpu->arch.db[0], 0);
1697 get_debugreg(vcpu->arch.db[1], 1);
1698 get_debugreg(vcpu->arch.db[2], 2);
1699 get_debugreg(vcpu->arch.db[3], 3);
1700 vcpu->arch.dr6 = svm_get_dr6(vcpu);
1701 vcpu->arch.dr7 = svm->vmcb->save.dr7;
1702
1703 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1704 set_dr_intercepts(svm);
1705}
1706
1707static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1708{
1709 struct vcpu_svm *svm = to_svm(vcpu);
1710
1711 svm->vmcb->save.dr7 = value;
1712 mark_dirty(svm->vmcb, VMCB_DR);
1713}
1714
1715static int pf_interception(struct vcpu_svm *svm)
1716{
1717 u64 fault_address = svm->vmcb->control.exit_info_2;
1718 u32 error_code;
1719 int r = 1;
1720
1721 switch (svm->apf_reason) {
1722 default:
1723 error_code = svm->vmcb->control.exit_info_1;
1724
1725 trace_kvm_page_fault(fault_address, error_code);
1726 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1727 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1728 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1729 svm->vmcb->control.insn_bytes,
1730 svm->vmcb->control.insn_len);
1731 break;
1732 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1733 svm->apf_reason = 0;
1734 local_irq_disable();
1735 kvm_async_pf_task_wait(fault_address);
1736 local_irq_enable();
1737 break;
1738 case KVM_PV_REASON_PAGE_READY:
1739 svm->apf_reason = 0;
1740 local_irq_disable();
1741 kvm_async_pf_task_wake(fault_address);
1742 local_irq_enable();
1743 break;
1744 }
1745 return r;
1746}
1747
1748static int db_interception(struct vcpu_svm *svm)
1749{
1750 struct kvm_run *kvm_run = svm->vcpu.run;
1751
1752 if (!(svm->vcpu.guest_debug &
1753 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1754 !svm->nmi_singlestep) {
1755 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1756 return 1;
1757 }
1758
1759 if (svm->nmi_singlestep) {
1760 svm->nmi_singlestep = false;
1761 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1762 svm->vmcb->save.rflags &=
1763 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1764 update_db_bp_intercept(&svm->vcpu);
1765 }
1766
1767 if (svm->vcpu.guest_debug &
1768 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1769 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1770 kvm_run->debug.arch.pc =
1771 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1772 kvm_run->debug.arch.exception = DB_VECTOR;
1773 return 0;
1774 }
1775
1776 return 1;
1777}
1778
1779static int bp_interception(struct vcpu_svm *svm)
1780{
1781 struct kvm_run *kvm_run = svm->vcpu.run;
1782
1783 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1784 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1785 kvm_run->debug.arch.exception = BP_VECTOR;
1786 return 0;
1787}
1788
1789static int ud_interception(struct vcpu_svm *svm)
1790{
1791 int er;
1792
1793 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1794 if (er != EMULATE_DONE)
1795 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1796 return 1;
1797}
1798
1799static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1800{
1801 struct vcpu_svm *svm = to_svm(vcpu);
1802
1803 clr_exception_intercept(svm, NM_VECTOR);
1804
1805 svm->vcpu.fpu_active = 1;
1806 update_cr0_intercept(svm);
1807}
1808
1809static int nm_interception(struct vcpu_svm *svm)
1810{
1811 svm_fpu_activate(&svm->vcpu);
1812 return 1;
1813}
1814
1815static bool is_erratum_383(void)
1816{
1817 int err, i;
1818 u64 value;
1819
1820 if (!erratum_383_found)
1821 return false;
1822
1823 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1824 if (err)
1825 return false;
1826
1827 /* Bit 62 may or may not be set for this mce */
1828 value &= ~(1ULL << 62);
1829
1830 if (value != 0xb600000000010015ULL)
1831 return false;
1832
1833 /* Clear MCi_STATUS registers */
1834 for (i = 0; i < 6; ++i)
1835 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1836
1837 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1838 if (!err) {
1839 u32 low, high;
1840
1841 value &= ~(1ULL << 2);
1842 low = lower_32_bits(value);
1843 high = upper_32_bits(value);
1844
1845 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1846 }
1847
1848 /* Flush tlb to evict multi-match entries */
1849 __flush_tlb_all();
1850
1851 return true;
1852}
1853
1854static void svm_handle_mce(struct vcpu_svm *svm)
1855{
1856 if (is_erratum_383()) {
1857 /*
1858 * Erratum 383 triggered. Guest state is corrupt so kill the
1859 * guest.
1860 */
1861 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1862
1863 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1864
1865 return;
1866 }
1867
1868 /*
1869 * On an #MC intercept the MCE handler is not called automatically in
1870 * the host. So do it by hand here.
1871 */
1872 asm volatile (
1873 "int $0x12\n");
1874 /* not sure if we ever come back to this point */
1875
1876 return;
1877}
1878
1879static int mc_interception(struct vcpu_svm *svm)
1880{
1881 return 1;
1882}
1883
1884static int shutdown_interception(struct vcpu_svm *svm)
1885{
1886 struct kvm_run *kvm_run = svm->vcpu.run;
1887
1888 /*
1889 * VMCB is undefined after a SHUTDOWN intercept
1890 * so reinitialize it.
1891 */
1892 clear_page(svm->vmcb);
1893 init_vmcb(svm, false);
1894
1895 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1896 return 0;
1897}
1898
1899static int io_interception(struct vcpu_svm *svm)
1900{
1901 struct kvm_vcpu *vcpu = &svm->vcpu;
1902 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1903 int size, in, string;
1904 unsigned port;
1905
1906 ++svm->vcpu.stat.io_exits;
1907 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1908 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1909 if (string || in)
1910 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1911
1912 port = io_info >> 16;
1913 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1914 svm->next_rip = svm->vmcb->control.exit_info_2;
1915 skip_emulated_instruction(&svm->vcpu);
1916
1917 return kvm_fast_pio_out(vcpu, size, port);
1918}
1919
1920static int nmi_interception(struct vcpu_svm *svm)
1921{
1922 return 1;
1923}
1924
1925static int intr_interception(struct vcpu_svm *svm)
1926{
1927 ++svm->vcpu.stat.irq_exits;
1928 return 1;
1929}
1930
1931static int nop_on_interception(struct vcpu_svm *svm)
1932{
1933 return 1;
1934}
1935
1936static int halt_interception(struct vcpu_svm *svm)
1937{
1938 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1939 return kvm_emulate_halt(&svm->vcpu);
1940}
1941
1942static int vmmcall_interception(struct vcpu_svm *svm)
1943{
1944 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1945 kvm_emulate_hypercall(&svm->vcpu);
1946 return 1;
1947}
1948
1949static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1950{
1951 struct vcpu_svm *svm = to_svm(vcpu);
1952
1953 return svm->nested.nested_cr3;
1954}
1955
1956static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
1957{
1958 struct vcpu_svm *svm = to_svm(vcpu);
1959 u64 cr3 = svm->nested.nested_cr3;
1960 u64 pdpte;
1961 int ret;
1962
1963 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte,
1964 offset_in_page(cr3) + index * 8, 8);
1965 if (ret)
1966 return 0;
1967 return pdpte;
1968}
1969
1970static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1971 unsigned long root)
1972{
1973 struct vcpu_svm *svm = to_svm(vcpu);
1974
1975 svm->vmcb->control.nested_cr3 = root;
1976 mark_dirty(svm->vmcb, VMCB_NPT);
1977 svm_flush_tlb(vcpu);
1978}
1979
1980static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1981 struct x86_exception *fault)
1982{
1983 struct vcpu_svm *svm = to_svm(vcpu);
1984
1985 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
1986 /*
1987 * TODO: track the cause of the nested page fault, and
1988 * correctly fill in the high bits of exit_info_1.
1989 */
1990 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1991 svm->vmcb->control.exit_code_hi = 0;
1992 svm->vmcb->control.exit_info_1 = (1ULL << 32);
1993 svm->vmcb->control.exit_info_2 = fault->address;
1994 }
1995
1996 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
1997 svm->vmcb->control.exit_info_1 |= fault->error_code;
1998
1999 /*
2000 * The present bit is always zero for page structure faults on real
2001 * hardware.
2002 */
2003 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2004 svm->vmcb->control.exit_info_1 &= ~1;
2005
2006 nested_svm_vmexit(svm);
2007}
2008
2009static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2010{
2011 WARN_ON(mmu_is_nested(vcpu));
2012 kvm_init_shadow_mmu(vcpu);
2013 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
2014 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
2015 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
2016 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2017 vcpu->arch.mmu.shadow_root_level = get_npt_level();
2018 reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2019 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
2020}
2021
2022static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2023{
2024 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2025}
2026
2027static int nested_svm_check_permissions(struct vcpu_svm *svm)
2028{
2029 if (!(svm->vcpu.arch.efer & EFER_SVME)
2030 || !is_paging(&svm->vcpu)) {
2031 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2032 return 1;
2033 }
2034
2035 if (svm->vmcb->save.cpl) {
2036 kvm_inject_gp(&svm->vcpu, 0);
2037 return 1;
2038 }
2039
2040 return 0;
2041}
2042
2043static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2044 bool has_error_code, u32 error_code)
2045{
2046 int vmexit;
2047
2048 if (!is_guest_mode(&svm->vcpu))
2049 return 0;
2050
2051 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2052 svm->vmcb->control.exit_code_hi = 0;
2053 svm->vmcb->control.exit_info_1 = error_code;
2054 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2055
2056 vmexit = nested_svm_intercept(svm);
2057 if (vmexit == NESTED_EXIT_DONE)
2058 svm->nested.exit_required = true;
2059
2060 return vmexit;
2061}
2062
2063/* This function returns true if it is save to enable the irq window */
2064static inline bool nested_svm_intr(struct vcpu_svm *svm)
2065{
2066 if (!is_guest_mode(&svm->vcpu))
2067 return true;
2068
2069 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2070 return true;
2071
2072 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2073 return false;
2074
2075 /*
2076 * if vmexit was already requested (by intercepted exception
2077 * for instance) do not overwrite it with "external interrupt"
2078 * vmexit.
2079 */
2080 if (svm->nested.exit_required)
2081 return false;
2082
2083 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2084 svm->vmcb->control.exit_info_1 = 0;
2085 svm->vmcb->control.exit_info_2 = 0;
2086
2087 if (svm->nested.intercept & 1ULL) {
2088 /*
2089 * The #vmexit can't be emulated here directly because this
2090 * code path runs with irqs and preemption disabled. A
2091 * #vmexit emulation might sleep. Only signal request for
2092 * the #vmexit here.
2093 */
2094 svm->nested.exit_required = true;
2095 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2096 return false;
2097 }
2098
2099 return true;
2100}
2101
2102/* This function returns true if it is save to enable the nmi window */
2103static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2104{
2105 if (!is_guest_mode(&svm->vcpu))
2106 return true;
2107
2108 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2109 return true;
2110
2111 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2112 svm->nested.exit_required = true;
2113
2114 return false;
2115}
2116
2117static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2118{
2119 struct page *page;
2120
2121 might_sleep();
2122
2123 page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2124 if (is_error_page(page))
2125 goto error;
2126
2127 *_page = page;
2128
2129 return kmap(page);
2130
2131error:
2132 kvm_inject_gp(&svm->vcpu, 0);
2133
2134 return NULL;
2135}
2136
2137static void nested_svm_unmap(struct page *page)
2138{
2139 kunmap(page);
2140 kvm_release_page_dirty(page);
2141}
2142
2143static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2144{
2145 unsigned port, size, iopm_len;
2146 u16 val, mask;
2147 u8 start_bit;
2148 u64 gpa;
2149
2150 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2151 return NESTED_EXIT_HOST;
2152
2153 port = svm->vmcb->control.exit_info_1 >> 16;
2154 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2155 SVM_IOIO_SIZE_SHIFT;
2156 gpa = svm->nested.vmcb_iopm + (port / 8);
2157 start_bit = port % 8;
2158 iopm_len = (start_bit + size > 8) ? 2 : 1;
2159 mask = (0xf >> (4 - size)) << start_bit;
2160 val = 0;
2161
2162 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2163 return NESTED_EXIT_DONE;
2164
2165 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2166}
2167
2168static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2169{
2170 u32 offset, msr, value;
2171 int write, mask;
2172
2173 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2174 return NESTED_EXIT_HOST;
2175
2176 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2177 offset = svm_msrpm_offset(msr);
2178 write = svm->vmcb->control.exit_info_1 & 1;
2179 mask = 1 << ((2 * (msr & 0xf)) + write);
2180
2181 if (offset == MSR_INVALID)
2182 return NESTED_EXIT_DONE;
2183
2184 /* Offset is in 32 bit units but need in 8 bit units */
2185 offset *= 4;
2186
2187 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2188 return NESTED_EXIT_DONE;
2189
2190 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2191}
2192
2193static int nested_svm_exit_special(struct vcpu_svm *svm)
2194{
2195 u32 exit_code = svm->vmcb->control.exit_code;
2196
2197 switch (exit_code) {
2198 case SVM_EXIT_INTR:
2199 case SVM_EXIT_NMI:
2200 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2201 return NESTED_EXIT_HOST;
2202 case SVM_EXIT_NPF:
2203 /* For now we are always handling NPFs when using them */
2204 if (npt_enabled)
2205 return NESTED_EXIT_HOST;
2206 break;
2207 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2208 /* When we're shadowing, trap PFs, but not async PF */
2209 if (!npt_enabled && svm->apf_reason == 0)
2210 return NESTED_EXIT_HOST;
2211 break;
2212 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2213 nm_interception(svm);
2214 break;
2215 default:
2216 break;
2217 }
2218
2219 return NESTED_EXIT_CONTINUE;
2220}
2221
2222/*
2223 * If this function returns true, this #vmexit was already handled
2224 */
2225static int nested_svm_intercept(struct vcpu_svm *svm)
2226{
2227 u32 exit_code = svm->vmcb->control.exit_code;
2228 int vmexit = NESTED_EXIT_HOST;
2229
2230 switch (exit_code) {
2231 case SVM_EXIT_MSR:
2232 vmexit = nested_svm_exit_handled_msr(svm);
2233 break;
2234 case SVM_EXIT_IOIO:
2235 vmexit = nested_svm_intercept_ioio(svm);
2236 break;
2237 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2238 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2239 if (svm->nested.intercept_cr & bit)
2240 vmexit = NESTED_EXIT_DONE;
2241 break;
2242 }
2243 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2244 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2245 if (svm->nested.intercept_dr & bit)
2246 vmexit = NESTED_EXIT_DONE;
2247 break;
2248 }
2249 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2250 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2251 if (svm->nested.intercept_exceptions & excp_bits)
2252 vmexit = NESTED_EXIT_DONE;
2253 /* async page fault always cause vmexit */
2254 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2255 svm->apf_reason != 0)
2256 vmexit = NESTED_EXIT_DONE;
2257 break;
2258 }
2259 case SVM_EXIT_ERR: {
2260 vmexit = NESTED_EXIT_DONE;
2261 break;
2262 }
2263 default: {
2264 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2265 if (svm->nested.intercept & exit_bits)
2266 vmexit = NESTED_EXIT_DONE;
2267 }
2268 }
2269
2270 return vmexit;
2271}
2272
2273static int nested_svm_exit_handled(struct vcpu_svm *svm)
2274{
2275 int vmexit;
2276
2277 vmexit = nested_svm_intercept(svm);
2278
2279 if (vmexit == NESTED_EXIT_DONE)
2280 nested_svm_vmexit(svm);
2281
2282 return vmexit;
2283}
2284
2285static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2286{
2287 struct vmcb_control_area *dst = &dst_vmcb->control;
2288 struct vmcb_control_area *from = &from_vmcb->control;
2289
2290 dst->intercept_cr = from->intercept_cr;
2291 dst->intercept_dr = from->intercept_dr;
2292 dst->intercept_exceptions = from->intercept_exceptions;
2293 dst->intercept = from->intercept;
2294 dst->iopm_base_pa = from->iopm_base_pa;
2295 dst->msrpm_base_pa = from->msrpm_base_pa;
2296 dst->tsc_offset = from->tsc_offset;
2297 dst->asid = from->asid;
2298 dst->tlb_ctl = from->tlb_ctl;
2299 dst->int_ctl = from->int_ctl;
2300 dst->int_vector = from->int_vector;
2301 dst->int_state = from->int_state;
2302 dst->exit_code = from->exit_code;
2303 dst->exit_code_hi = from->exit_code_hi;
2304 dst->exit_info_1 = from->exit_info_1;
2305 dst->exit_info_2 = from->exit_info_2;
2306 dst->exit_int_info = from->exit_int_info;
2307 dst->exit_int_info_err = from->exit_int_info_err;
2308 dst->nested_ctl = from->nested_ctl;
2309 dst->event_inj = from->event_inj;
2310 dst->event_inj_err = from->event_inj_err;
2311 dst->nested_cr3 = from->nested_cr3;
2312 dst->lbr_ctl = from->lbr_ctl;
2313}
2314
2315static int nested_svm_vmexit(struct vcpu_svm *svm)
2316{
2317 struct vmcb *nested_vmcb;
2318 struct vmcb *hsave = svm->nested.hsave;
2319 struct vmcb *vmcb = svm->vmcb;
2320 struct page *page;
2321
2322 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2323 vmcb->control.exit_info_1,
2324 vmcb->control.exit_info_2,
2325 vmcb->control.exit_int_info,
2326 vmcb->control.exit_int_info_err,
2327 KVM_ISA_SVM);
2328
2329 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2330 if (!nested_vmcb)
2331 return 1;
2332
2333 /* Exit Guest-Mode */
2334 leave_guest_mode(&svm->vcpu);
2335 svm->nested.vmcb = 0;
2336
2337 /* Give the current vmcb to the guest */
2338 disable_gif(svm);
2339
2340 nested_vmcb->save.es = vmcb->save.es;
2341 nested_vmcb->save.cs = vmcb->save.cs;
2342 nested_vmcb->save.ss = vmcb->save.ss;
2343 nested_vmcb->save.ds = vmcb->save.ds;
2344 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2345 nested_vmcb->save.idtr = vmcb->save.idtr;
2346 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2347 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2348 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2349 nested_vmcb->save.cr2 = vmcb->save.cr2;
2350 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2351 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2352 nested_vmcb->save.rip = vmcb->save.rip;
2353 nested_vmcb->save.rsp = vmcb->save.rsp;
2354 nested_vmcb->save.rax = vmcb->save.rax;
2355 nested_vmcb->save.dr7 = vmcb->save.dr7;
2356 nested_vmcb->save.dr6 = vmcb->save.dr6;
2357 nested_vmcb->save.cpl = vmcb->save.cpl;
2358
2359 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2360 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2361 nested_vmcb->control.int_state = vmcb->control.int_state;
2362 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2363 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2364 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2365 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2366 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2367 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2368 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2369
2370 /*
2371 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2372 * to make sure that we do not lose injected events. So check event_inj
2373 * here and copy it to exit_int_info if it is valid.
2374 * Exit_int_info and event_inj can't be both valid because the case
2375 * below only happens on a VMRUN instruction intercept which has
2376 * no valid exit_int_info set.
2377 */
2378 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2379 struct vmcb_control_area *nc = &nested_vmcb->control;
2380
2381 nc->exit_int_info = vmcb->control.event_inj;
2382 nc->exit_int_info_err = vmcb->control.event_inj_err;
2383 }
2384
2385 nested_vmcb->control.tlb_ctl = 0;
2386 nested_vmcb->control.event_inj = 0;
2387 nested_vmcb->control.event_inj_err = 0;
2388
2389 /* We always set V_INTR_MASKING and remember the old value in hflags */
2390 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2391 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2392
2393 /* Restore the original control entries */
2394 copy_vmcb_control_area(vmcb, hsave);
2395
2396 kvm_clear_exception_queue(&svm->vcpu);
2397 kvm_clear_interrupt_queue(&svm->vcpu);
2398
2399 svm->nested.nested_cr3 = 0;
2400
2401 /* Restore selected save entries */
2402 svm->vmcb->save.es = hsave->save.es;
2403 svm->vmcb->save.cs = hsave->save.cs;
2404 svm->vmcb->save.ss = hsave->save.ss;
2405 svm->vmcb->save.ds = hsave->save.ds;
2406 svm->vmcb->save.gdtr = hsave->save.gdtr;
2407 svm->vmcb->save.idtr = hsave->save.idtr;
2408 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2409 svm_set_efer(&svm->vcpu, hsave->save.efer);
2410 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2411 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2412 if (npt_enabled) {
2413 svm->vmcb->save.cr3 = hsave->save.cr3;
2414 svm->vcpu.arch.cr3 = hsave->save.cr3;
2415 } else {
2416 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2417 }
2418 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2419 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2420 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2421 svm->vmcb->save.dr7 = 0;
2422 svm->vmcb->save.cpl = 0;
2423 svm->vmcb->control.exit_int_info = 0;
2424
2425 mark_all_dirty(svm->vmcb);
2426
2427 nested_svm_unmap(page);
2428
2429 nested_svm_uninit_mmu_context(&svm->vcpu);
2430 kvm_mmu_reset_context(&svm->vcpu);
2431 kvm_mmu_load(&svm->vcpu);
2432
2433 return 0;
2434}
2435
2436static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2437{
2438 /*
2439 * This function merges the msr permission bitmaps of kvm and the
2440 * nested vmcb. It is optimized in that it only merges the parts where
2441 * the kvm msr permission bitmap may contain zero bits
2442 */
2443 int i;
2444
2445 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2446 return true;
2447
2448 for (i = 0; i < MSRPM_OFFSETS; i++) {
2449 u32 value, p;
2450 u64 offset;
2451
2452 if (msrpm_offsets[i] == 0xffffffff)
2453 break;
2454
2455 p = msrpm_offsets[i];
2456 offset = svm->nested.vmcb_msrpm + (p * 4);
2457
2458 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2459 return false;
2460
2461 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2462 }
2463
2464 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2465
2466 return true;
2467}
2468
2469static bool nested_vmcb_checks(struct vmcb *vmcb)
2470{
2471 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2472 return false;
2473
2474 if (vmcb->control.asid == 0)
2475 return false;
2476
2477 if (vmcb->control.nested_ctl && !npt_enabled)
2478 return false;
2479
2480 return true;
2481}
2482
2483static bool nested_svm_vmrun(struct vcpu_svm *svm)
2484{
2485 struct vmcb *nested_vmcb;
2486 struct vmcb *hsave = svm->nested.hsave;
2487 struct vmcb *vmcb = svm->vmcb;
2488 struct page *page;
2489 u64 vmcb_gpa;
2490
2491 vmcb_gpa = svm->vmcb->save.rax;
2492
2493 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2494 if (!nested_vmcb)
2495 return false;
2496
2497 if (!nested_vmcb_checks(nested_vmcb)) {
2498 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2499 nested_vmcb->control.exit_code_hi = 0;
2500 nested_vmcb->control.exit_info_1 = 0;
2501 nested_vmcb->control.exit_info_2 = 0;
2502
2503 nested_svm_unmap(page);
2504
2505 return false;
2506 }
2507
2508 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2509 nested_vmcb->save.rip,
2510 nested_vmcb->control.int_ctl,
2511 nested_vmcb->control.event_inj,
2512 nested_vmcb->control.nested_ctl);
2513
2514 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2515 nested_vmcb->control.intercept_cr >> 16,
2516 nested_vmcb->control.intercept_exceptions,
2517 nested_vmcb->control.intercept);
2518
2519 /* Clear internal status */
2520 kvm_clear_exception_queue(&svm->vcpu);
2521 kvm_clear_interrupt_queue(&svm->vcpu);
2522
2523 /*
2524 * Save the old vmcb, so we don't need to pick what we save, but can
2525 * restore everything when a VMEXIT occurs
2526 */
2527 hsave->save.es = vmcb->save.es;
2528 hsave->save.cs = vmcb->save.cs;
2529 hsave->save.ss = vmcb->save.ss;
2530 hsave->save.ds = vmcb->save.ds;
2531 hsave->save.gdtr = vmcb->save.gdtr;
2532 hsave->save.idtr = vmcb->save.idtr;
2533 hsave->save.efer = svm->vcpu.arch.efer;
2534 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2535 hsave->save.cr4 = svm->vcpu.arch.cr4;
2536 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2537 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2538 hsave->save.rsp = vmcb->save.rsp;
2539 hsave->save.rax = vmcb->save.rax;
2540 if (npt_enabled)
2541 hsave->save.cr3 = vmcb->save.cr3;
2542 else
2543 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2544
2545 copy_vmcb_control_area(hsave, vmcb);
2546
2547 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2548 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2549 else
2550 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2551
2552 if (nested_vmcb->control.nested_ctl) {
2553 kvm_mmu_unload(&svm->vcpu);
2554 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2555 nested_svm_init_mmu_context(&svm->vcpu);
2556 }
2557
2558 /* Load the nested guest state */
2559 svm->vmcb->save.es = nested_vmcb->save.es;
2560 svm->vmcb->save.cs = nested_vmcb->save.cs;
2561 svm->vmcb->save.ss = nested_vmcb->save.ss;
2562 svm->vmcb->save.ds = nested_vmcb->save.ds;
2563 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2564 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2565 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2566 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2567 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2568 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2569 if (npt_enabled) {
2570 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2571 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2572 } else
2573 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2574
2575 /* Guest paging mode is active - reset mmu */
2576 kvm_mmu_reset_context(&svm->vcpu);
2577
2578 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2579 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2580 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2581 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2582
2583 /* In case we don't even reach vcpu_run, the fields are not updated */
2584 svm->vmcb->save.rax = nested_vmcb->save.rax;
2585 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2586 svm->vmcb->save.rip = nested_vmcb->save.rip;
2587 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2588 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2589 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2590
2591 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2592 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2593
2594 /* cache intercepts */
2595 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2596 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2597 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2598 svm->nested.intercept = nested_vmcb->control.intercept;
2599
2600 svm_flush_tlb(&svm->vcpu);
2601 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2602 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2603 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2604 else
2605 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2606
2607 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2608 /* We only want the cr8 intercept bits of the guest */
2609 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2610 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2611 }
2612
2613 /* We don't want to see VMMCALLs from a nested guest */
2614 clr_intercept(svm, INTERCEPT_VMMCALL);
2615
2616 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2617 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2618 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2619 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2620 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2621 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2622
2623 nested_svm_unmap(page);
2624
2625 /* Enter Guest-Mode */
2626 enter_guest_mode(&svm->vcpu);
2627
2628 /*
2629 * Merge guest and host intercepts - must be called with vcpu in
2630 * guest-mode to take affect here
2631 */
2632 recalc_intercepts(svm);
2633
2634 svm->nested.vmcb = vmcb_gpa;
2635
2636 enable_gif(svm);
2637
2638 mark_all_dirty(svm->vmcb);
2639
2640 return true;
2641}
2642
2643static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2644{
2645 to_vmcb->save.fs = from_vmcb->save.fs;
2646 to_vmcb->save.gs = from_vmcb->save.gs;
2647 to_vmcb->save.tr = from_vmcb->save.tr;
2648 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2649 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2650 to_vmcb->save.star = from_vmcb->save.star;
2651 to_vmcb->save.lstar = from_vmcb->save.lstar;
2652 to_vmcb->save.cstar = from_vmcb->save.cstar;
2653 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2654 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2655 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2656 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2657}
2658
2659static int vmload_interception(struct vcpu_svm *svm)
2660{
2661 struct vmcb *nested_vmcb;
2662 struct page *page;
2663
2664 if (nested_svm_check_permissions(svm))
2665 return 1;
2666
2667 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2668 if (!nested_vmcb)
2669 return 1;
2670
2671 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2672 skip_emulated_instruction(&svm->vcpu);
2673
2674 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2675 nested_svm_unmap(page);
2676
2677 return 1;
2678}
2679
2680static int vmsave_interception(struct vcpu_svm *svm)
2681{
2682 struct vmcb *nested_vmcb;
2683 struct page *page;
2684
2685 if (nested_svm_check_permissions(svm))
2686 return 1;
2687
2688 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2689 if (!nested_vmcb)
2690 return 1;
2691
2692 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2693 skip_emulated_instruction(&svm->vcpu);
2694
2695 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2696 nested_svm_unmap(page);
2697
2698 return 1;
2699}
2700
2701static int vmrun_interception(struct vcpu_svm *svm)
2702{
2703 if (nested_svm_check_permissions(svm))
2704 return 1;
2705
2706 /* Save rip after vmrun instruction */
2707 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2708
2709 if (!nested_svm_vmrun(svm))
2710 return 1;
2711
2712 if (!nested_svm_vmrun_msrpm(svm))
2713 goto failed;
2714
2715 return 1;
2716
2717failed:
2718
2719 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2720 svm->vmcb->control.exit_code_hi = 0;
2721 svm->vmcb->control.exit_info_1 = 0;
2722 svm->vmcb->control.exit_info_2 = 0;
2723
2724 nested_svm_vmexit(svm);
2725
2726 return 1;
2727}
2728
2729static int stgi_interception(struct vcpu_svm *svm)
2730{
2731 if (nested_svm_check_permissions(svm))
2732 return 1;
2733
2734 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2735 skip_emulated_instruction(&svm->vcpu);
2736 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2737
2738 enable_gif(svm);
2739
2740 return 1;
2741}
2742
2743static int clgi_interception(struct vcpu_svm *svm)
2744{
2745 if (nested_svm_check_permissions(svm))
2746 return 1;
2747
2748 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2749 skip_emulated_instruction(&svm->vcpu);
2750
2751 disable_gif(svm);
2752
2753 /* After a CLGI no interrupts should come */
2754 svm_clear_vintr(svm);
2755 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2756
2757 mark_dirty(svm->vmcb, VMCB_INTR);
2758
2759 return 1;
2760}
2761
2762static int invlpga_interception(struct vcpu_svm *svm)
2763{
2764 struct kvm_vcpu *vcpu = &svm->vcpu;
2765
2766 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
2767 kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2768
2769 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2770 kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2771
2772 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2773 skip_emulated_instruction(&svm->vcpu);
2774 return 1;
2775}
2776
2777static int skinit_interception(struct vcpu_svm *svm)
2778{
2779 trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2780
2781 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2782 return 1;
2783}
2784
2785static int wbinvd_interception(struct vcpu_svm *svm)
2786{
2787 kvm_emulate_wbinvd(&svm->vcpu);
2788 return 1;
2789}
2790
2791static int xsetbv_interception(struct vcpu_svm *svm)
2792{
2793 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2794 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2795
2796 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2797 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2798 skip_emulated_instruction(&svm->vcpu);
2799 }
2800
2801 return 1;
2802}
2803
2804static int task_switch_interception(struct vcpu_svm *svm)
2805{
2806 u16 tss_selector;
2807 int reason;
2808 int int_type = svm->vmcb->control.exit_int_info &
2809 SVM_EXITINTINFO_TYPE_MASK;
2810 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2811 uint32_t type =
2812 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2813 uint32_t idt_v =
2814 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2815 bool has_error_code = false;
2816 u32 error_code = 0;
2817
2818 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2819
2820 if (svm->vmcb->control.exit_info_2 &
2821 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2822 reason = TASK_SWITCH_IRET;
2823 else if (svm->vmcb->control.exit_info_2 &
2824 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2825 reason = TASK_SWITCH_JMP;
2826 else if (idt_v)
2827 reason = TASK_SWITCH_GATE;
2828 else
2829 reason = TASK_SWITCH_CALL;
2830
2831 if (reason == TASK_SWITCH_GATE) {
2832 switch (type) {
2833 case SVM_EXITINTINFO_TYPE_NMI:
2834 svm->vcpu.arch.nmi_injected = false;
2835 break;
2836 case SVM_EXITINTINFO_TYPE_EXEPT:
2837 if (svm->vmcb->control.exit_info_2 &
2838 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2839 has_error_code = true;
2840 error_code =
2841 (u32)svm->vmcb->control.exit_info_2;
2842 }
2843 kvm_clear_exception_queue(&svm->vcpu);
2844 break;
2845 case SVM_EXITINTINFO_TYPE_INTR:
2846 kvm_clear_interrupt_queue(&svm->vcpu);
2847 break;
2848 default:
2849 break;
2850 }
2851 }
2852
2853 if (reason != TASK_SWITCH_GATE ||
2854 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2855 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2856 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2857 skip_emulated_instruction(&svm->vcpu);
2858
2859 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2860 int_vec = -1;
2861
2862 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2863 has_error_code, error_code) == EMULATE_FAIL) {
2864 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2865 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2866 svm->vcpu.run->internal.ndata = 0;
2867 return 0;
2868 }
2869 return 1;
2870}
2871
2872static int cpuid_interception(struct vcpu_svm *svm)
2873{
2874 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2875 kvm_emulate_cpuid(&svm->vcpu);
2876 return 1;
2877}
2878
2879static int iret_interception(struct vcpu_svm *svm)
2880{
2881 ++svm->vcpu.stat.nmi_window_exits;
2882 clr_intercept(svm, INTERCEPT_IRET);
2883 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2884 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2885 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2886 return 1;
2887}
2888
2889static int invlpg_interception(struct vcpu_svm *svm)
2890{
2891 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2892 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2893
2894 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2895 skip_emulated_instruction(&svm->vcpu);
2896 return 1;
2897}
2898
2899static int emulate_on_interception(struct vcpu_svm *svm)
2900{
2901 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2902}
2903
2904static int rdpmc_interception(struct vcpu_svm *svm)
2905{
2906 int err;
2907
2908 if (!static_cpu_has(X86_FEATURE_NRIPS))
2909 return emulate_on_interception(svm);
2910
2911 err = kvm_rdpmc(&svm->vcpu);
2912 kvm_complete_insn_gp(&svm->vcpu, err);
2913
2914 return 1;
2915}
2916
2917static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2918 unsigned long val)
2919{
2920 unsigned long cr0 = svm->vcpu.arch.cr0;
2921 bool ret = false;
2922 u64 intercept;
2923
2924 intercept = svm->nested.intercept;
2925
2926 if (!is_guest_mode(&svm->vcpu) ||
2927 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2928 return false;
2929
2930 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2931 val &= ~SVM_CR0_SELECTIVE_MASK;
2932
2933 if (cr0 ^ val) {
2934 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2935 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2936 }
2937
2938 return ret;
2939}
2940
2941#define CR_VALID (1ULL << 63)
2942
2943static int cr_interception(struct vcpu_svm *svm)
2944{
2945 int reg, cr;
2946 unsigned long val;
2947 int err;
2948
2949 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2950 return emulate_on_interception(svm);
2951
2952 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2953 return emulate_on_interception(svm);
2954
2955 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2956 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2957 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2958 else
2959 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2960
2961 err = 0;
2962 if (cr >= 16) { /* mov to cr */
2963 cr -= 16;
2964 val = kvm_register_read(&svm->vcpu, reg);
2965 switch (cr) {
2966 case 0:
2967 if (!check_selective_cr0_intercepted(svm, val))
2968 err = kvm_set_cr0(&svm->vcpu, val);
2969 else
2970 return 1;
2971
2972 break;
2973 case 3:
2974 err = kvm_set_cr3(&svm->vcpu, val);
2975 break;
2976 case 4:
2977 err = kvm_set_cr4(&svm->vcpu, val);
2978 break;
2979 case 8:
2980 err = kvm_set_cr8(&svm->vcpu, val);
2981 break;
2982 default:
2983 WARN(1, "unhandled write to CR%d", cr);
2984 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2985 return 1;
2986 }
2987 } else { /* mov from cr */
2988 switch (cr) {
2989 case 0:
2990 val = kvm_read_cr0(&svm->vcpu);
2991 break;
2992 case 2:
2993 val = svm->vcpu.arch.cr2;
2994 break;
2995 case 3:
2996 val = kvm_read_cr3(&svm->vcpu);
2997 break;
2998 case 4:
2999 val = kvm_read_cr4(&svm->vcpu);
3000 break;
3001 case 8:
3002 val = kvm_get_cr8(&svm->vcpu);
3003 break;
3004 default:
3005 WARN(1, "unhandled read from CR%d", cr);
3006 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3007 return 1;
3008 }
3009 kvm_register_write(&svm->vcpu, reg, val);
3010 }
3011 kvm_complete_insn_gp(&svm->vcpu, err);
3012
3013 return 1;
3014}
3015
3016static int dr_interception(struct vcpu_svm *svm)
3017{
3018 int reg, dr;
3019 unsigned long val;
3020
3021 if (svm->vcpu.guest_debug == 0) {
3022 /*
3023 * No more DR vmexits; force a reload of the debug registers
3024 * and reenter on this instruction. The next vmexit will
3025 * retrieve the full state of the debug registers.
3026 */
3027 clr_dr_intercepts(svm);
3028 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3029 return 1;
3030 }
3031
3032 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3033 return emulate_on_interception(svm);
3034
3035 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3036 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3037
3038 if (dr >= 16) { /* mov to DRn */
3039 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3040 return 1;
3041 val = kvm_register_read(&svm->vcpu, reg);
3042 kvm_set_dr(&svm->vcpu, dr - 16, val);
3043 } else {
3044 if (!kvm_require_dr(&svm->vcpu, dr))
3045 return 1;
3046 kvm_get_dr(&svm->vcpu, dr, &val);
3047 kvm_register_write(&svm->vcpu, reg, val);
3048 }
3049
3050 skip_emulated_instruction(&svm->vcpu);
3051
3052 return 1;
3053}
3054
3055static int cr8_write_interception(struct vcpu_svm *svm)
3056{
3057 struct kvm_run *kvm_run = svm->vcpu.run;
3058 int r;
3059
3060 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3061 /* instruction emulation calls kvm_set_cr8() */
3062 r = cr_interception(svm);
3063 if (irqchip_in_kernel(svm->vcpu.kvm))
3064 return r;
3065 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3066 return r;
3067 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3068 return 0;
3069}
3070
3071static u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
3072{
3073 struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
3074 return vmcb->control.tsc_offset +
3075 svm_scale_tsc(vcpu, host_tsc);
3076}
3077
3078static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3079{
3080 struct vcpu_svm *svm = to_svm(vcpu);
3081
3082 switch (msr_info->index) {
3083 case MSR_IA32_TSC: {
3084 msr_info->data = svm->vmcb->control.tsc_offset +
3085 svm_scale_tsc(vcpu, rdtsc());
3086
3087 break;
3088 }
3089 case MSR_STAR:
3090 msr_info->data = svm->vmcb->save.star;
3091 break;
3092#ifdef CONFIG_X86_64
3093 case MSR_LSTAR:
3094 msr_info->data = svm->vmcb->save.lstar;
3095 break;
3096 case MSR_CSTAR:
3097 msr_info->data = svm->vmcb->save.cstar;
3098 break;
3099 case MSR_KERNEL_GS_BASE:
3100 msr_info->data = svm->vmcb->save.kernel_gs_base;
3101 break;
3102 case MSR_SYSCALL_MASK:
3103 msr_info->data = svm->vmcb->save.sfmask;
3104 break;
3105#endif
3106 case MSR_IA32_SYSENTER_CS:
3107 msr_info->data = svm->vmcb->save.sysenter_cs;
3108 break;
3109 case MSR_IA32_SYSENTER_EIP:
3110 msr_info->data = svm->sysenter_eip;
3111 break;
3112 case MSR_IA32_SYSENTER_ESP:
3113 msr_info->data = svm->sysenter_esp;
3114 break;
3115 /*
3116 * Nobody will change the following 5 values in the VMCB so we can
3117 * safely return them on rdmsr. They will always be 0 until LBRV is
3118 * implemented.
3119 */
3120 case MSR_IA32_DEBUGCTLMSR:
3121 msr_info->data = svm->vmcb->save.dbgctl;
3122 break;
3123 case MSR_IA32_LASTBRANCHFROMIP:
3124 msr_info->data = svm->vmcb->save.br_from;
3125 break;
3126 case MSR_IA32_LASTBRANCHTOIP:
3127 msr_info->data = svm->vmcb->save.br_to;
3128 break;
3129 case MSR_IA32_LASTINTFROMIP:
3130 msr_info->data = svm->vmcb->save.last_excp_from;
3131 break;
3132 case MSR_IA32_LASTINTTOIP:
3133 msr_info->data = svm->vmcb->save.last_excp_to;
3134 break;
3135 case MSR_VM_HSAVE_PA:
3136 msr_info->data = svm->nested.hsave_msr;
3137 break;
3138 case MSR_VM_CR:
3139 msr_info->data = svm->nested.vm_cr_msr;
3140 break;
3141 case MSR_IA32_UCODE_REV:
3142 msr_info->data = 0x01000065;
3143 break;
3144 default:
3145 return kvm_get_msr_common(vcpu, msr_info);
3146 }
3147 return 0;
3148}
3149
3150static int rdmsr_interception(struct vcpu_svm *svm)
3151{
3152 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3153 struct msr_data msr_info;
3154
3155 msr_info.index = ecx;
3156 msr_info.host_initiated = false;
3157 if (svm_get_msr(&svm->vcpu, &msr_info)) {
3158 trace_kvm_msr_read_ex(ecx);
3159 kvm_inject_gp(&svm->vcpu, 0);
3160 } else {
3161 trace_kvm_msr_read(ecx, msr_info.data);
3162
3163 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3164 msr_info.data & 0xffffffff);
3165 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3166 msr_info.data >> 32);
3167 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3168 skip_emulated_instruction(&svm->vcpu);
3169 }
3170 return 1;
3171}
3172
3173static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3174{
3175 struct vcpu_svm *svm = to_svm(vcpu);
3176 int svm_dis, chg_mask;
3177
3178 if (data & ~SVM_VM_CR_VALID_MASK)
3179 return 1;
3180
3181 chg_mask = SVM_VM_CR_VALID_MASK;
3182
3183 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3184 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3185
3186 svm->nested.vm_cr_msr &= ~chg_mask;
3187 svm->nested.vm_cr_msr |= (data & chg_mask);
3188
3189 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3190
3191 /* check for svm_disable while efer.svme is set */
3192 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3193 return 1;
3194
3195 return 0;
3196}
3197
3198static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3199{
3200 struct vcpu_svm *svm = to_svm(vcpu);
3201
3202 u32 ecx = msr->index;
3203 u64 data = msr->data;
3204 switch (ecx) {
3205 case MSR_IA32_TSC:
3206 kvm_write_tsc(vcpu, msr);
3207 break;
3208 case MSR_STAR:
3209 svm->vmcb->save.star = data;
3210 break;
3211#ifdef CONFIG_X86_64
3212 case MSR_LSTAR:
3213 svm->vmcb->save.lstar = data;
3214 break;
3215 case MSR_CSTAR:
3216 svm->vmcb->save.cstar = data;
3217 break;
3218 case MSR_KERNEL_GS_BASE:
3219 svm->vmcb->save.kernel_gs_base = data;
3220 break;
3221 case MSR_SYSCALL_MASK:
3222 svm->vmcb->save.sfmask = data;
3223 break;
3224#endif
3225 case MSR_IA32_SYSENTER_CS:
3226 svm->vmcb->save.sysenter_cs = data;
3227 break;
3228 case MSR_IA32_SYSENTER_EIP:
3229 svm->sysenter_eip = data;
3230 svm->vmcb->save.sysenter_eip = data;
3231 break;
3232 case MSR_IA32_SYSENTER_ESP:
3233 svm->sysenter_esp = data;
3234 svm->vmcb->save.sysenter_esp = data;
3235 break;
3236 case MSR_IA32_DEBUGCTLMSR:
3237 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3238 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3239 __func__, data);
3240 break;
3241 }
3242 if (data & DEBUGCTL_RESERVED_BITS)
3243 return 1;
3244
3245 svm->vmcb->save.dbgctl = data;
3246 mark_dirty(svm->vmcb, VMCB_LBR);
3247 if (data & (1ULL<<0))
3248 svm_enable_lbrv(svm);
3249 else
3250 svm_disable_lbrv(svm);
3251 break;
3252 case MSR_VM_HSAVE_PA:
3253 svm->nested.hsave_msr = data;
3254 break;
3255 case MSR_VM_CR:
3256 return svm_set_vm_cr(vcpu, data);
3257 case MSR_VM_IGNNE:
3258 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3259 break;
3260 default:
3261 return kvm_set_msr_common(vcpu, msr);
3262 }
3263 return 0;
3264}
3265
3266static int wrmsr_interception(struct vcpu_svm *svm)
3267{
3268 struct msr_data msr;
3269 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3270 u64 data = kvm_read_edx_eax(&svm->vcpu);
3271
3272 msr.data = data;
3273 msr.index = ecx;
3274 msr.host_initiated = false;
3275
3276 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3277 if (kvm_set_msr(&svm->vcpu, &msr)) {
3278 trace_kvm_msr_write_ex(ecx, data);
3279 kvm_inject_gp(&svm->vcpu, 0);
3280 } else {
3281 trace_kvm_msr_write(ecx, data);
3282 skip_emulated_instruction(&svm->vcpu);
3283 }
3284 return 1;
3285}
3286
3287static int msr_interception(struct vcpu_svm *svm)
3288{
3289 if (svm->vmcb->control.exit_info_1)
3290 return wrmsr_interception(svm);
3291 else
3292 return rdmsr_interception(svm);
3293}
3294
3295static int interrupt_window_interception(struct vcpu_svm *svm)
3296{
3297 struct kvm_run *kvm_run = svm->vcpu.run;
3298
3299 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3300 svm_clear_vintr(svm);
3301 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3302 mark_dirty(svm->vmcb, VMCB_INTR);
3303 ++svm->vcpu.stat.irq_window_exits;
3304 /*
3305 * If the user space waits to inject interrupts, exit as soon as
3306 * possible
3307 */
3308 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3309 kvm_run->request_interrupt_window &&
3310 !kvm_cpu_has_interrupt(&svm->vcpu)) {
3311 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3312 return 0;
3313 }
3314
3315 return 1;
3316}
3317
3318static int pause_interception(struct vcpu_svm *svm)
3319{
3320 kvm_vcpu_on_spin(&(svm->vcpu));
3321 return 1;
3322}
3323
3324static int nop_interception(struct vcpu_svm *svm)
3325{
3326 skip_emulated_instruction(&(svm->vcpu));
3327 return 1;
3328}
3329
3330static int monitor_interception(struct vcpu_svm *svm)
3331{
3332 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3333 return nop_interception(svm);
3334}
3335
3336static int mwait_interception(struct vcpu_svm *svm)
3337{
3338 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3339 return nop_interception(svm);
3340}
3341
3342static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3343 [SVM_EXIT_READ_CR0] = cr_interception,
3344 [SVM_EXIT_READ_CR3] = cr_interception,
3345 [SVM_EXIT_READ_CR4] = cr_interception,
3346 [SVM_EXIT_READ_CR8] = cr_interception,
3347 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
3348 [SVM_EXIT_WRITE_CR0] = cr_interception,
3349 [SVM_EXIT_WRITE_CR3] = cr_interception,
3350 [SVM_EXIT_WRITE_CR4] = cr_interception,
3351 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3352 [SVM_EXIT_READ_DR0] = dr_interception,
3353 [SVM_EXIT_READ_DR1] = dr_interception,
3354 [SVM_EXIT_READ_DR2] = dr_interception,
3355 [SVM_EXIT_READ_DR3] = dr_interception,
3356 [SVM_EXIT_READ_DR4] = dr_interception,
3357 [SVM_EXIT_READ_DR5] = dr_interception,
3358 [SVM_EXIT_READ_DR6] = dr_interception,
3359 [SVM_EXIT_READ_DR7] = dr_interception,
3360 [SVM_EXIT_WRITE_DR0] = dr_interception,
3361 [SVM_EXIT_WRITE_DR1] = dr_interception,
3362 [SVM_EXIT_WRITE_DR2] = dr_interception,
3363 [SVM_EXIT_WRITE_DR3] = dr_interception,
3364 [SVM_EXIT_WRITE_DR4] = dr_interception,
3365 [SVM_EXIT_WRITE_DR5] = dr_interception,
3366 [SVM_EXIT_WRITE_DR6] = dr_interception,
3367 [SVM_EXIT_WRITE_DR7] = dr_interception,
3368 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3369 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3370 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3371 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3372 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
3373 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3374 [SVM_EXIT_INTR] = intr_interception,
3375 [SVM_EXIT_NMI] = nmi_interception,
3376 [SVM_EXIT_SMI] = nop_on_interception,
3377 [SVM_EXIT_INIT] = nop_on_interception,
3378 [SVM_EXIT_VINTR] = interrupt_window_interception,
3379 [SVM_EXIT_RDPMC] = rdpmc_interception,
3380 [SVM_EXIT_CPUID] = cpuid_interception,
3381 [SVM_EXIT_IRET] = iret_interception,
3382 [SVM_EXIT_INVD] = emulate_on_interception,
3383 [SVM_EXIT_PAUSE] = pause_interception,
3384 [SVM_EXIT_HLT] = halt_interception,
3385 [SVM_EXIT_INVLPG] = invlpg_interception,
3386 [SVM_EXIT_INVLPGA] = invlpga_interception,
3387 [SVM_EXIT_IOIO] = io_interception,
3388 [SVM_EXIT_MSR] = msr_interception,
3389 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3390 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3391 [SVM_EXIT_VMRUN] = vmrun_interception,
3392 [SVM_EXIT_VMMCALL] = vmmcall_interception,
3393 [SVM_EXIT_VMLOAD] = vmload_interception,
3394 [SVM_EXIT_VMSAVE] = vmsave_interception,
3395 [SVM_EXIT_STGI] = stgi_interception,
3396 [SVM_EXIT_CLGI] = clgi_interception,
3397 [SVM_EXIT_SKINIT] = skinit_interception,
3398 [SVM_EXIT_WBINVD] = wbinvd_interception,
3399 [SVM_EXIT_MONITOR] = monitor_interception,
3400 [SVM_EXIT_MWAIT] = mwait_interception,
3401 [SVM_EXIT_XSETBV] = xsetbv_interception,
3402 [SVM_EXIT_NPF] = pf_interception,
3403 [SVM_EXIT_RSM] = emulate_on_interception,
3404};
3405
3406static void dump_vmcb(struct kvm_vcpu *vcpu)
3407{
3408 struct vcpu_svm *svm = to_svm(vcpu);
3409 struct vmcb_control_area *control = &svm->vmcb->control;
3410 struct vmcb_save_area *save = &svm->vmcb->save;
3411
3412 pr_err("VMCB Control Area:\n");
3413 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3414 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3415 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3416 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3417 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3418 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3419 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3420 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3421 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3422 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3423 pr_err("%-20s%d\n", "asid:", control->asid);
3424 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3425 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3426 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3427 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3428 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3429 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3430 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3431 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3432 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3433 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3434 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3435 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3436 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3437 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3438 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3439 pr_err("VMCB State Save Area:\n");
3440 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3441 "es:",
3442 save->es.selector, save->es.attrib,
3443 save->es.limit, save->es.base);
3444 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3445 "cs:",
3446 save->cs.selector, save->cs.attrib,
3447 save->cs.limit, save->cs.base);
3448 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3449 "ss:",
3450 save->ss.selector, save->ss.attrib,
3451 save->ss.limit, save->ss.base);
3452 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3453 "ds:",
3454 save->ds.selector, save->ds.attrib,
3455 save->ds.limit, save->ds.base);
3456 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3457 "fs:",
3458 save->fs.selector, save->fs.attrib,
3459 save->fs.limit, save->fs.base);
3460 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3461 "gs:",
3462 save->gs.selector, save->gs.attrib,
3463 save->gs.limit, save->gs.base);
3464 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3465 "gdtr:",
3466 save->gdtr.selector, save->gdtr.attrib,
3467 save->gdtr.limit, save->gdtr.base);
3468 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3469 "ldtr:",
3470 save->ldtr.selector, save->ldtr.attrib,
3471 save->ldtr.limit, save->ldtr.base);
3472 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3473 "idtr:",
3474 save->idtr.selector, save->idtr.attrib,
3475 save->idtr.limit, save->idtr.base);
3476 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3477 "tr:",
3478 save->tr.selector, save->tr.attrib,
3479 save->tr.limit, save->tr.base);
3480 pr_err("cpl: %d efer: %016llx\n",
3481 save->cpl, save->efer);
3482 pr_err("%-15s %016llx %-13s %016llx\n",
3483 "cr0:", save->cr0, "cr2:", save->cr2);
3484 pr_err("%-15s %016llx %-13s %016llx\n",
3485 "cr3:", save->cr3, "cr4:", save->cr4);
3486 pr_err("%-15s %016llx %-13s %016llx\n",
3487 "dr6:", save->dr6, "dr7:", save->dr7);
3488 pr_err("%-15s %016llx %-13s %016llx\n",
3489 "rip:", save->rip, "rflags:", save->rflags);
3490 pr_err("%-15s %016llx %-13s %016llx\n",
3491 "rsp:", save->rsp, "rax:", save->rax);
3492 pr_err("%-15s %016llx %-13s %016llx\n",
3493 "star:", save->star, "lstar:", save->lstar);
3494 pr_err("%-15s %016llx %-13s %016llx\n",
3495 "cstar:", save->cstar, "sfmask:", save->sfmask);
3496 pr_err("%-15s %016llx %-13s %016llx\n",
3497 "kernel_gs_base:", save->kernel_gs_base,
3498 "sysenter_cs:", save->sysenter_cs);
3499 pr_err("%-15s %016llx %-13s %016llx\n",
3500 "sysenter_esp:", save->sysenter_esp,
3501 "sysenter_eip:", save->sysenter_eip);
3502 pr_err("%-15s %016llx %-13s %016llx\n",
3503 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3504 pr_err("%-15s %016llx %-13s %016llx\n",
3505 "br_from:", save->br_from, "br_to:", save->br_to);
3506 pr_err("%-15s %016llx %-13s %016llx\n",
3507 "excp_from:", save->last_excp_from,
3508 "excp_to:", save->last_excp_to);
3509}
3510
3511static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3512{
3513 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3514
3515 *info1 = control->exit_info_1;
3516 *info2 = control->exit_info_2;
3517}
3518
3519static int handle_exit(struct kvm_vcpu *vcpu)
3520{
3521 struct vcpu_svm *svm = to_svm(vcpu);
3522 struct kvm_run *kvm_run = vcpu->run;
3523 u32 exit_code = svm->vmcb->control.exit_code;
3524
3525 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3526 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3527 if (npt_enabled)
3528 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3529
3530 if (unlikely(svm->nested.exit_required)) {
3531 nested_svm_vmexit(svm);
3532 svm->nested.exit_required = false;
3533
3534 return 1;
3535 }
3536
3537 if (is_guest_mode(vcpu)) {
3538 int vmexit;
3539
3540 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3541 svm->vmcb->control.exit_info_1,
3542 svm->vmcb->control.exit_info_2,
3543 svm->vmcb->control.exit_int_info,
3544 svm->vmcb->control.exit_int_info_err,
3545 KVM_ISA_SVM);
3546
3547 vmexit = nested_svm_exit_special(svm);
3548
3549 if (vmexit == NESTED_EXIT_CONTINUE)
3550 vmexit = nested_svm_exit_handled(svm);
3551
3552 if (vmexit == NESTED_EXIT_DONE)
3553 return 1;
3554 }
3555
3556 svm_complete_interrupts(svm);
3557
3558 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3559 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3560 kvm_run->fail_entry.hardware_entry_failure_reason
3561 = svm->vmcb->control.exit_code;
3562 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3563 dump_vmcb(vcpu);
3564 return 0;
3565 }
3566
3567 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3568 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3569 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3570 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3571 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3572 "exit_code 0x%x\n",
3573 __func__, svm->vmcb->control.exit_int_info,
3574 exit_code);
3575
3576 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3577 || !svm_exit_handlers[exit_code]) {
3578 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
3579 kvm_queue_exception(vcpu, UD_VECTOR);
3580 return 1;
3581 }
3582
3583 return svm_exit_handlers[exit_code](svm);
3584}
3585
3586static void reload_tss(struct kvm_vcpu *vcpu)
3587{
3588 int cpu = raw_smp_processor_id();
3589
3590 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3591 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3592 load_TR_desc();
3593}
3594
3595static void pre_svm_run(struct vcpu_svm *svm)
3596{
3597 int cpu = raw_smp_processor_id();
3598
3599 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3600
3601 /* FIXME: handle wraparound of asid_generation */
3602 if (svm->asid_generation != sd->asid_generation)
3603 new_asid(svm, sd);
3604}
3605
3606static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3607{
3608 struct vcpu_svm *svm = to_svm(vcpu);
3609
3610 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3611 vcpu->arch.hflags |= HF_NMI_MASK;
3612 set_intercept(svm, INTERCEPT_IRET);
3613 ++vcpu->stat.nmi_injections;
3614}
3615
3616static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3617{
3618 struct vmcb_control_area *control;
3619
3620 control = &svm->vmcb->control;
3621 control->int_vector = irq;
3622 control->int_ctl &= ~V_INTR_PRIO_MASK;
3623 control->int_ctl |= V_IRQ_MASK |
3624 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3625 mark_dirty(svm->vmcb, VMCB_INTR);
3626}
3627
3628static void svm_set_irq(struct kvm_vcpu *vcpu)
3629{
3630 struct vcpu_svm *svm = to_svm(vcpu);
3631
3632 BUG_ON(!(gif_set(svm)));
3633
3634 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3635 ++vcpu->stat.irq_injections;
3636
3637 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3638 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3639}
3640
3641static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3642{
3643 struct vcpu_svm *svm = to_svm(vcpu);
3644
3645 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3646 return;
3647
3648 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3649
3650 if (irr == -1)
3651 return;
3652
3653 if (tpr >= irr)
3654 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3655}
3656
3657static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
3658{
3659 return;
3660}
3661
3662static int svm_cpu_uses_apicv(struct kvm_vcpu *vcpu)
3663{
3664 return 0;
3665}
3666
3667static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu)
3668{
3669 return;
3670}
3671
3672static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
3673{
3674 return;
3675}
3676
3677static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3678{
3679 struct vcpu_svm *svm = to_svm(vcpu);
3680 struct vmcb *vmcb = svm->vmcb;
3681 int ret;
3682 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3683 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3684 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3685
3686 return ret;
3687}
3688
3689static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3690{
3691 struct vcpu_svm *svm = to_svm(vcpu);
3692
3693 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3694}
3695
3696static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3697{
3698 struct vcpu_svm *svm = to_svm(vcpu);
3699
3700 if (masked) {
3701 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3702 set_intercept(svm, INTERCEPT_IRET);
3703 } else {
3704 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3705 clr_intercept(svm, INTERCEPT_IRET);
3706 }
3707}
3708
3709static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3710{
3711 struct vcpu_svm *svm = to_svm(vcpu);
3712 struct vmcb *vmcb = svm->vmcb;
3713 int ret;
3714
3715 if (!gif_set(svm) ||
3716 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3717 return 0;
3718
3719 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3720
3721 if (is_guest_mode(vcpu))
3722 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3723
3724 return ret;
3725}
3726
3727static void enable_irq_window(struct kvm_vcpu *vcpu)
3728{
3729 struct vcpu_svm *svm = to_svm(vcpu);
3730
3731 /*
3732 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3733 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3734 * get that intercept, this function will be called again though and
3735 * we'll get the vintr intercept.
3736 */
3737 if (gif_set(svm) && nested_svm_intr(svm)) {
3738 svm_set_vintr(svm);
3739 svm_inject_irq(svm, 0x0);
3740 }
3741}
3742
3743static void enable_nmi_window(struct kvm_vcpu *vcpu)
3744{
3745 struct vcpu_svm *svm = to_svm(vcpu);
3746
3747 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3748 == HF_NMI_MASK)
3749 return; /* IRET will cause a vm exit */
3750
3751 /*
3752 * Something prevents NMI from been injected. Single step over possible
3753 * problem (IRET or exception injection or interrupt shadow)
3754 */
3755 svm->nmi_singlestep = true;
3756 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3757 update_db_bp_intercept(vcpu);
3758}
3759
3760static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3761{
3762 return 0;
3763}
3764
3765static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3766{
3767 struct vcpu_svm *svm = to_svm(vcpu);
3768
3769 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3770 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3771 else
3772 svm->asid_generation--;
3773}
3774
3775static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3776{
3777}
3778
3779static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3780{
3781 struct vcpu_svm *svm = to_svm(vcpu);
3782
3783 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3784 return;
3785
3786 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3787 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3788 kvm_set_cr8(vcpu, cr8);
3789 }
3790}
3791
3792static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3793{
3794 struct vcpu_svm *svm = to_svm(vcpu);
3795 u64 cr8;
3796
3797 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3798 return;
3799
3800 cr8 = kvm_get_cr8(vcpu);
3801 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3802 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3803}
3804
3805static void svm_complete_interrupts(struct vcpu_svm *svm)
3806{
3807 u8 vector;
3808 int type;
3809 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3810 unsigned int3_injected = svm->int3_injected;
3811
3812 svm->int3_injected = 0;
3813
3814 /*
3815 * If we've made progress since setting HF_IRET_MASK, we've
3816 * executed an IRET and can allow NMI injection.
3817 */
3818 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3819 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3820 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3821 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3822 }
3823
3824 svm->vcpu.arch.nmi_injected = false;
3825 kvm_clear_exception_queue(&svm->vcpu);
3826 kvm_clear_interrupt_queue(&svm->vcpu);
3827
3828 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3829 return;
3830
3831 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3832
3833 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3834 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3835
3836 switch (type) {
3837 case SVM_EXITINTINFO_TYPE_NMI:
3838 svm->vcpu.arch.nmi_injected = true;
3839 break;
3840 case SVM_EXITINTINFO_TYPE_EXEPT:
3841 /*
3842 * In case of software exceptions, do not reinject the vector,
3843 * but re-execute the instruction instead. Rewind RIP first
3844 * if we emulated INT3 before.
3845 */
3846 if (kvm_exception_is_soft(vector)) {
3847 if (vector == BP_VECTOR && int3_injected &&
3848 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3849 kvm_rip_write(&svm->vcpu,
3850 kvm_rip_read(&svm->vcpu) -
3851 int3_injected);
3852 break;
3853 }
3854 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3855 u32 err = svm->vmcb->control.exit_int_info_err;
3856 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3857
3858 } else
3859 kvm_requeue_exception(&svm->vcpu, vector);
3860 break;
3861 case SVM_EXITINTINFO_TYPE_INTR:
3862 kvm_queue_interrupt(&svm->vcpu, vector, false);
3863 break;
3864 default:
3865 break;
3866 }
3867}
3868
3869static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3870{
3871 struct vcpu_svm *svm = to_svm(vcpu);
3872 struct vmcb_control_area *control = &svm->vmcb->control;
3873
3874 control->exit_int_info = control->event_inj;
3875 control->exit_int_info_err = control->event_inj_err;
3876 control->event_inj = 0;
3877 svm_complete_interrupts(svm);
3878}
3879
3880static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3881{
3882 struct vcpu_svm *svm = to_svm(vcpu);
3883
3884 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3885 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3886 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3887
3888 /*
3889 * A vmexit emulation is required before the vcpu can be executed
3890 * again.
3891 */
3892 if (unlikely(svm->nested.exit_required))
3893 return;
3894
3895 pre_svm_run(svm);
3896
3897 sync_lapic_to_cr8(vcpu);
3898
3899 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3900
3901 clgi();
3902
3903 local_irq_enable();
3904
3905 asm volatile (
3906 "push %%" _ASM_BP "; \n\t"
3907 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
3908 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
3909 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
3910 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
3911 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
3912 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
3913#ifdef CONFIG_X86_64
3914 "mov %c[r8](%[svm]), %%r8 \n\t"
3915 "mov %c[r9](%[svm]), %%r9 \n\t"
3916 "mov %c[r10](%[svm]), %%r10 \n\t"
3917 "mov %c[r11](%[svm]), %%r11 \n\t"
3918 "mov %c[r12](%[svm]), %%r12 \n\t"
3919 "mov %c[r13](%[svm]), %%r13 \n\t"
3920 "mov %c[r14](%[svm]), %%r14 \n\t"
3921 "mov %c[r15](%[svm]), %%r15 \n\t"
3922#endif
3923
3924 /* Enter guest mode */
3925 "push %%" _ASM_AX " \n\t"
3926 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
3927 __ex(SVM_VMLOAD) "\n\t"
3928 __ex(SVM_VMRUN) "\n\t"
3929 __ex(SVM_VMSAVE) "\n\t"
3930 "pop %%" _ASM_AX " \n\t"
3931
3932 /* Save guest registers, load host registers */
3933 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
3934 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
3935 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
3936 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
3937 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
3938 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
3939#ifdef CONFIG_X86_64
3940 "mov %%r8, %c[r8](%[svm]) \n\t"
3941 "mov %%r9, %c[r9](%[svm]) \n\t"
3942 "mov %%r10, %c[r10](%[svm]) \n\t"
3943 "mov %%r11, %c[r11](%[svm]) \n\t"
3944 "mov %%r12, %c[r12](%[svm]) \n\t"
3945 "mov %%r13, %c[r13](%[svm]) \n\t"
3946 "mov %%r14, %c[r14](%[svm]) \n\t"
3947 "mov %%r15, %c[r15](%[svm]) \n\t"
3948#endif
3949 "pop %%" _ASM_BP
3950 :
3951 : [svm]"a"(svm),
3952 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3953 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3954 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3955 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3956 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3957 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3958 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3959#ifdef CONFIG_X86_64
3960 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3961 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3962 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3963 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3964 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3965 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3966 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3967 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3968#endif
3969 : "cc", "memory"
3970#ifdef CONFIG_X86_64
3971 , "rbx", "rcx", "rdx", "rsi", "rdi"
3972 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3973#else
3974 , "ebx", "ecx", "edx", "esi", "edi"
3975#endif
3976 );
3977
3978#ifdef CONFIG_X86_64
3979 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3980#else
3981 loadsegment(fs, svm->host.fs);
3982#ifndef CONFIG_X86_32_LAZY_GS
3983 loadsegment(gs, svm->host.gs);
3984#endif
3985#endif
3986
3987 reload_tss(vcpu);
3988
3989 local_irq_disable();
3990
3991 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3992 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3993 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3994 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3995
3996 trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
3997
3998 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3999 kvm_before_handle_nmi(&svm->vcpu);
4000
4001 stgi();
4002
4003 /* Any pending NMI will happen here */
4004
4005 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4006 kvm_after_handle_nmi(&svm->vcpu);
4007
4008 sync_cr8_to_lapic(vcpu);
4009
4010 svm->next_rip = 0;
4011
4012 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4013
4014 /* if exit due to PF check for async PF */
4015 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
4016 svm->apf_reason = kvm_read_and_reset_pf_reason();
4017
4018 if (npt_enabled) {
4019 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
4020 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
4021 }
4022
4023 /*
4024 * We need to handle MC intercepts here before the vcpu has a chance to
4025 * change the physical cpu
4026 */
4027 if (unlikely(svm->vmcb->control.exit_code ==
4028 SVM_EXIT_EXCP_BASE + MC_VECTOR))
4029 svm_handle_mce(svm);
4030
4031 mark_all_clean(svm->vmcb);
4032}
4033
4034static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4035{
4036 struct vcpu_svm *svm = to_svm(vcpu);
4037
4038 svm->vmcb->save.cr3 = root;
4039 mark_dirty(svm->vmcb, VMCB_CR);
4040 svm_flush_tlb(vcpu);
4041}
4042
4043static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4044{
4045 struct vcpu_svm *svm = to_svm(vcpu);
4046
4047 svm->vmcb->control.nested_cr3 = root;
4048 mark_dirty(svm->vmcb, VMCB_NPT);
4049
4050 /* Also sync guest cr3 here in case we live migrate */
4051 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
4052 mark_dirty(svm->vmcb, VMCB_CR);
4053
4054 svm_flush_tlb(vcpu);
4055}
4056
4057static int is_disabled(void)
4058{
4059 u64 vm_cr;
4060
4061 rdmsrl(MSR_VM_CR, vm_cr);
4062 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
4063 return 1;
4064
4065 return 0;
4066}
4067
4068static void
4069svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4070{
4071 /*
4072 * Patch in the VMMCALL instruction:
4073 */
4074 hypercall[0] = 0x0f;
4075 hypercall[1] = 0x01;
4076 hypercall[2] = 0xd9;
4077}
4078
4079static void svm_check_processor_compat(void *rtn)
4080{
4081 *(int *)rtn = 0;
4082}
4083
4084static bool svm_cpu_has_accelerated_tpr(void)
4085{
4086 return false;
4087}
4088
4089static bool svm_has_high_real_mode_segbase(void)
4090{
4091 return true;
4092}
4093
4094static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4095{
4096 return 0;
4097}
4098
4099static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4100{
4101}
4102
4103static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4104{
4105 switch (func) {
4106 case 0x80000001:
4107 if (nested)
4108 entry->ecx |= (1 << 2); /* Set SVM bit */
4109 break;
4110 case 0x8000000A:
4111 entry->eax = 1; /* SVM revision 1 */
4112 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
4113 ASID emulation to nested SVM */
4114 entry->ecx = 0; /* Reserved */
4115 entry->edx = 0; /* Per default do not support any
4116 additional features */
4117
4118 /* Support next_rip if host supports it */
4119 if (boot_cpu_has(X86_FEATURE_NRIPS))
4120 entry->edx |= SVM_FEATURE_NRIP;
4121
4122 /* Support NPT for the guest if enabled */
4123 if (npt_enabled)
4124 entry->edx |= SVM_FEATURE_NPT;
4125
4126 break;
4127 }
4128}
4129
4130static int svm_get_lpage_level(void)
4131{
4132 return PT_PDPE_LEVEL;
4133}
4134
4135static bool svm_rdtscp_supported(void)
4136{
4137 return false;
4138}
4139
4140static bool svm_invpcid_supported(void)
4141{
4142 return false;
4143}
4144
4145static bool svm_mpx_supported(void)
4146{
4147 return false;
4148}
4149
4150static bool svm_xsaves_supported(void)
4151{
4152 return false;
4153}
4154
4155static bool svm_has_wbinvd_exit(void)
4156{
4157 return true;
4158}
4159
4160static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
4161{
4162 struct vcpu_svm *svm = to_svm(vcpu);
4163
4164 set_exception_intercept(svm, NM_VECTOR);
4165 update_cr0_intercept(svm);
4166}
4167
4168#define PRE_EX(exit) { .exit_code = (exit), \
4169 .stage = X86_ICPT_PRE_EXCEPT, }
4170#define POST_EX(exit) { .exit_code = (exit), \
4171 .stage = X86_ICPT_POST_EXCEPT, }
4172#define POST_MEM(exit) { .exit_code = (exit), \
4173 .stage = X86_ICPT_POST_MEMACCESS, }
4174
4175static const struct __x86_intercept {
4176 u32 exit_code;
4177 enum x86_intercept_stage stage;
4178} x86_intercept_map[] = {
4179 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4180 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4181 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4182 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4183 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4184 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4185 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4186 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4187 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4188 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4189 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4190 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4191 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4192 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4193 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4194 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4195 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4196 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4197 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4198 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4199 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4200 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4201 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4202 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4203 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4204 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4205 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4206 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4207 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4208 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4209 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4210 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4211 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4212 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4213 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4214 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4215 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4216 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4217 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4218 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4219 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4220 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4221 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4222 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4223 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4224 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4225};
4226
4227#undef PRE_EX
4228#undef POST_EX
4229#undef POST_MEM
4230
4231static int svm_check_intercept(struct kvm_vcpu *vcpu,
4232 struct x86_instruction_info *info,
4233 enum x86_intercept_stage stage)
4234{
4235 struct vcpu_svm *svm = to_svm(vcpu);
4236 int vmexit, ret = X86EMUL_CONTINUE;
4237 struct __x86_intercept icpt_info;
4238 struct vmcb *vmcb = svm->vmcb;
4239
4240 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4241 goto out;
4242
4243 icpt_info = x86_intercept_map[info->intercept];
4244
4245 if (stage != icpt_info.stage)
4246 goto out;
4247
4248 switch (icpt_info.exit_code) {
4249 case SVM_EXIT_READ_CR0:
4250 if (info->intercept == x86_intercept_cr_read)
4251 icpt_info.exit_code += info->modrm_reg;
4252 break;
4253 case SVM_EXIT_WRITE_CR0: {
4254 unsigned long cr0, val;
4255 u64 intercept;
4256
4257 if (info->intercept == x86_intercept_cr_write)
4258 icpt_info.exit_code += info->modrm_reg;
4259
4260 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4261 info->intercept == x86_intercept_clts)
4262 break;
4263
4264 intercept = svm->nested.intercept;
4265
4266 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4267 break;
4268
4269 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4270 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4271
4272 if (info->intercept == x86_intercept_lmsw) {
4273 cr0 &= 0xfUL;
4274 val &= 0xfUL;
4275 /* lmsw can't clear PE - catch this here */
4276 if (cr0 & X86_CR0_PE)
4277 val |= X86_CR0_PE;
4278 }
4279
4280 if (cr0 ^ val)
4281 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4282
4283 break;
4284 }
4285 case SVM_EXIT_READ_DR0:
4286 case SVM_EXIT_WRITE_DR0:
4287 icpt_info.exit_code += info->modrm_reg;
4288 break;
4289 case SVM_EXIT_MSR:
4290 if (info->intercept == x86_intercept_wrmsr)
4291 vmcb->control.exit_info_1 = 1;
4292 else
4293 vmcb->control.exit_info_1 = 0;
4294 break;
4295 case SVM_EXIT_PAUSE:
4296 /*
4297 * We get this for NOP only, but pause
4298 * is rep not, check this here
4299 */
4300 if (info->rep_prefix != REPE_PREFIX)
4301 goto out;
4302 case SVM_EXIT_IOIO: {
4303 u64 exit_info;
4304 u32 bytes;
4305
4306 if (info->intercept == x86_intercept_in ||
4307 info->intercept == x86_intercept_ins) {
4308 exit_info = ((info->src_val & 0xffff) << 16) |
4309 SVM_IOIO_TYPE_MASK;
4310 bytes = info->dst_bytes;
4311 } else {
4312 exit_info = (info->dst_val & 0xffff) << 16;
4313 bytes = info->src_bytes;
4314 }
4315
4316 if (info->intercept == x86_intercept_outs ||
4317 info->intercept == x86_intercept_ins)
4318 exit_info |= SVM_IOIO_STR_MASK;
4319
4320 if (info->rep_prefix)
4321 exit_info |= SVM_IOIO_REP_MASK;
4322
4323 bytes = min(bytes, 4u);
4324
4325 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4326
4327 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4328
4329 vmcb->control.exit_info_1 = exit_info;
4330 vmcb->control.exit_info_2 = info->next_rip;
4331
4332 break;
4333 }
4334 default:
4335 break;
4336 }
4337
4338 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4339 if (static_cpu_has(X86_FEATURE_NRIPS))
4340 vmcb->control.next_rip = info->next_rip;
4341 vmcb->control.exit_code = icpt_info.exit_code;
4342 vmexit = nested_svm_exit_handled(svm);
4343
4344 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4345 : X86EMUL_CONTINUE;
4346
4347out:
4348 return ret;
4349}
4350
4351static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
4352{
4353 local_irq_enable();
4354}
4355
4356static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4357{
4358}
4359
4360static struct kvm_x86_ops svm_x86_ops = {
4361 .cpu_has_kvm_support = has_svm,
4362 .disabled_by_bios = is_disabled,
4363 .hardware_setup = svm_hardware_setup,
4364 .hardware_unsetup = svm_hardware_unsetup,
4365 .check_processor_compatibility = svm_check_processor_compat,
4366 .hardware_enable = svm_hardware_enable,
4367 .hardware_disable = svm_hardware_disable,
4368 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4369 .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
4370
4371 .vcpu_create = svm_create_vcpu,
4372 .vcpu_free = svm_free_vcpu,
4373 .vcpu_reset = svm_vcpu_reset,
4374
4375 .prepare_guest_switch = svm_prepare_guest_switch,
4376 .vcpu_load = svm_vcpu_load,
4377 .vcpu_put = svm_vcpu_put,
4378
4379 .update_db_bp_intercept = update_db_bp_intercept,
4380 .get_msr = svm_get_msr,
4381 .set_msr = svm_set_msr,
4382 .get_segment_base = svm_get_segment_base,
4383 .get_segment = svm_get_segment,
4384 .set_segment = svm_set_segment,
4385 .get_cpl = svm_get_cpl,
4386 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4387 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4388 .decache_cr3 = svm_decache_cr3,
4389 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4390 .set_cr0 = svm_set_cr0,
4391 .set_cr3 = svm_set_cr3,
4392 .set_cr4 = svm_set_cr4,
4393 .set_efer = svm_set_efer,
4394 .get_idt = svm_get_idt,
4395 .set_idt = svm_set_idt,
4396 .get_gdt = svm_get_gdt,
4397 .set_gdt = svm_set_gdt,
4398 .get_dr6 = svm_get_dr6,
4399 .set_dr6 = svm_set_dr6,
4400 .set_dr7 = svm_set_dr7,
4401 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4402 .cache_reg = svm_cache_reg,
4403 .get_rflags = svm_get_rflags,
4404 .set_rflags = svm_set_rflags,
4405 .fpu_activate = svm_fpu_activate,
4406 .fpu_deactivate = svm_fpu_deactivate,
4407
4408 .tlb_flush = svm_flush_tlb,
4409
4410 .run = svm_vcpu_run,
4411 .handle_exit = handle_exit,
4412 .skip_emulated_instruction = skip_emulated_instruction,
4413 .set_interrupt_shadow = svm_set_interrupt_shadow,
4414 .get_interrupt_shadow = svm_get_interrupt_shadow,
4415 .patch_hypercall = svm_patch_hypercall,
4416 .set_irq = svm_set_irq,
4417 .set_nmi = svm_inject_nmi,
4418 .queue_exception = svm_queue_exception,
4419 .cancel_injection = svm_cancel_injection,
4420 .interrupt_allowed = svm_interrupt_allowed,
4421 .nmi_allowed = svm_nmi_allowed,
4422 .get_nmi_mask = svm_get_nmi_mask,
4423 .set_nmi_mask = svm_set_nmi_mask,
4424 .enable_nmi_window = enable_nmi_window,
4425 .enable_irq_window = enable_irq_window,
4426 .update_cr8_intercept = update_cr8_intercept,
4427 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
4428 .cpu_uses_apicv = svm_cpu_uses_apicv,
4429 .load_eoi_exitmap = svm_load_eoi_exitmap,
4430 .sync_pir_to_irr = svm_sync_pir_to_irr,
4431
4432 .set_tss_addr = svm_set_tss_addr,
4433 .get_tdp_level = get_npt_level,
4434 .get_mt_mask = svm_get_mt_mask,
4435
4436 .get_exit_info = svm_get_exit_info,
4437
4438 .get_lpage_level = svm_get_lpage_level,
4439
4440 .cpuid_update = svm_cpuid_update,
4441
4442 .rdtscp_supported = svm_rdtscp_supported,
4443 .invpcid_supported = svm_invpcid_supported,
4444 .mpx_supported = svm_mpx_supported,
4445 .xsaves_supported = svm_xsaves_supported,
4446
4447 .set_supported_cpuid = svm_set_supported_cpuid,
4448
4449 .has_wbinvd_exit = svm_has_wbinvd_exit,
4450
4451 .set_tsc_khz = svm_set_tsc_khz,
4452 .read_tsc_offset = svm_read_tsc_offset,
4453 .write_tsc_offset = svm_write_tsc_offset,
4454 .adjust_tsc_offset = svm_adjust_tsc_offset,
4455 .compute_tsc_offset = svm_compute_tsc_offset,
4456 .read_l1_tsc = svm_read_l1_tsc,
4457
4458 .set_tdp_cr3 = set_tdp_cr3,
4459
4460 .check_intercept = svm_check_intercept,
4461 .handle_external_intr = svm_handle_external_intr,
4462
4463 .sched_in = svm_sched_in,
4464
4465 .pmu_ops = &amd_pmu_ops,
4466};
4467
4468static int __init svm_init(void)
4469{
4470 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4471 __alignof__(struct vcpu_svm), THIS_MODULE);
4472}
4473
4474static void __exit svm_exit(void)
4475{
4476 kvm_exit();
4477}
4478
4479module_init(svm_init)
4480module_exit(svm_exit)
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