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KVM: x86: Convert tsc_write_lock to raw_spinlock
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1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
19#include "irq.h"
20#include "mmu.h"
21
22#include <linux/kvm_host.h>
23#include <linux/module.h>
24#include <linux/kernel.h>
25#include <linux/mm.h>
26#include <linux/highmem.h>
27#include <linux/sched.h>
28#include <linux/moduleparam.h>
29#include <linux/ftrace_event.h>
30#include <linux/slab.h>
31#include <linux/tboot.h>
32#include "kvm_cache_regs.h"
33#include "x86.h"
34
35#include <asm/io.h>
36#include <asm/desc.h>
37#include <asm/vmx.h>
38#include <asm/virtext.h>
39#include <asm/mce.h>
40#include <asm/i387.h>
41#include <asm/xcr.h>
42
43#include "trace.h"
44
45#define __ex(x) __kvm_handle_fault_on_reboot(x)
46
47MODULE_AUTHOR("Qumranet");
48MODULE_LICENSE("GPL");
49
50static int __read_mostly bypass_guest_pf = 1;
51module_param(bypass_guest_pf, bool, S_IRUGO);
52
53static int __read_mostly enable_vpid = 1;
54module_param_named(vpid, enable_vpid, bool, 0444);
55
56static int __read_mostly flexpriority_enabled = 1;
57module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
58
59static int __read_mostly enable_ept = 1;
60module_param_named(ept, enable_ept, bool, S_IRUGO);
61
62static int __read_mostly enable_unrestricted_guest = 1;
63module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
65
66static int __read_mostly emulate_invalid_guest_state = 0;
67module_param(emulate_invalid_guest_state, bool, S_IRUGO);
68
69static int __read_mostly vmm_exclusive = 1;
70module_param(vmm_exclusive, bool, S_IRUGO);
71
72static int __read_mostly yield_on_hlt = 1;
73module_param(yield_on_hlt, bool, S_IRUGO);
74
75#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
76 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
77#define KVM_GUEST_CR0_MASK \
78 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
79#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
80 (X86_CR0_WP | X86_CR0_NE)
81#define KVM_VM_CR0_ALWAYS_ON \
82 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
83#define KVM_CR4_GUEST_OWNED_BITS \
84 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
85 | X86_CR4_OSXMMEXCPT)
86
87#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
88#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
89
90#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
91
92/*
93 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
94 * ple_gap: upper bound on the amount of time between two successive
95 * executions of PAUSE in a loop. Also indicate if ple enabled.
96 * According to test, this time is usually smaller than 128 cycles.
97 * ple_window: upper bound on the amount of time a guest is allowed to execute
98 * in a PAUSE loop. Tests indicate that most spinlocks are held for
99 * less than 2^12 cycles
100 * Time is measured based on a counter that runs at the same rate as the TSC,
101 * refer SDM volume 3b section 21.6.13 & 22.1.3.
102 */
103#define KVM_VMX_DEFAULT_PLE_GAP 128
104#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
105static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
106module_param(ple_gap, int, S_IRUGO);
107
108static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
109module_param(ple_window, int, S_IRUGO);
110
111#define NR_AUTOLOAD_MSRS 1
112
113struct vmcs {
114 u32 revision_id;
115 u32 abort;
116 char data[0];
117};
118
119struct shared_msr_entry {
120 unsigned index;
121 u64 data;
122 u64 mask;
123};
124
125struct vcpu_vmx {
126 struct kvm_vcpu vcpu;
127 struct list_head local_vcpus_link;
128 unsigned long host_rsp;
129 int launched;
130 u8 fail;
131 u32 exit_intr_info;
132 u32 idt_vectoring_info;
133 struct shared_msr_entry *guest_msrs;
134 int nmsrs;
135 int save_nmsrs;
136#ifdef CONFIG_X86_64
137 u64 msr_host_kernel_gs_base;
138 u64 msr_guest_kernel_gs_base;
139#endif
140 struct vmcs *vmcs;
141 struct msr_autoload {
142 unsigned nr;
143 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
144 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
145 } msr_autoload;
146 struct {
147 int loaded;
148 u16 fs_sel, gs_sel, ldt_sel;
149 int gs_ldt_reload_needed;
150 int fs_reload_needed;
151 } host_state;
152 struct {
153 int vm86_active;
154 ulong save_rflags;
155 struct kvm_save_segment {
156 u16 selector;
157 unsigned long base;
158 u32 limit;
159 u32 ar;
160 } tr, es, ds, fs, gs;
161 } rmode;
162 int vpid;
163 bool emulation_required;
164
165 /* Support for vnmi-less CPUs */
166 int soft_vnmi_blocked;
167 ktime_t entry_time;
168 s64 vnmi_blocked_time;
169 u32 exit_reason;
170
171 bool rdtscp_enabled;
172};
173
174static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
175{
176 return container_of(vcpu, struct vcpu_vmx, vcpu);
177}
178
179static int init_rmode(struct kvm *kvm);
180static u64 construct_eptp(unsigned long root_hpa);
181static void kvm_cpu_vmxon(u64 addr);
182static void kvm_cpu_vmxoff(void);
183static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
184
185static DEFINE_PER_CPU(struct vmcs *, vmxarea);
186static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
187static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
188static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
189
190static unsigned long *vmx_io_bitmap_a;
191static unsigned long *vmx_io_bitmap_b;
192static unsigned long *vmx_msr_bitmap_legacy;
193static unsigned long *vmx_msr_bitmap_longmode;
194
195static bool cpu_has_load_ia32_efer;
196
197static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
198static DEFINE_SPINLOCK(vmx_vpid_lock);
199
200static struct vmcs_config {
201 int size;
202 int order;
203 u32 revision_id;
204 u32 pin_based_exec_ctrl;
205 u32 cpu_based_exec_ctrl;
206 u32 cpu_based_2nd_exec_ctrl;
207 u32 vmexit_ctrl;
208 u32 vmentry_ctrl;
209} vmcs_config;
210
211static struct vmx_capability {
212 u32 ept;
213 u32 vpid;
214} vmx_capability;
215
216#define VMX_SEGMENT_FIELD(seg) \
217 [VCPU_SREG_##seg] = { \
218 .selector = GUEST_##seg##_SELECTOR, \
219 .base = GUEST_##seg##_BASE, \
220 .limit = GUEST_##seg##_LIMIT, \
221 .ar_bytes = GUEST_##seg##_AR_BYTES, \
222 }
223
224static struct kvm_vmx_segment_field {
225 unsigned selector;
226 unsigned base;
227 unsigned limit;
228 unsigned ar_bytes;
229} kvm_vmx_segment_fields[] = {
230 VMX_SEGMENT_FIELD(CS),
231 VMX_SEGMENT_FIELD(DS),
232 VMX_SEGMENT_FIELD(ES),
233 VMX_SEGMENT_FIELD(FS),
234 VMX_SEGMENT_FIELD(GS),
235 VMX_SEGMENT_FIELD(SS),
236 VMX_SEGMENT_FIELD(TR),
237 VMX_SEGMENT_FIELD(LDTR),
238};
239
240static u64 host_efer;
241
242static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
243
244/*
245 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
246 * away by decrementing the array size.
247 */
248static const u32 vmx_msr_index[] = {
249#ifdef CONFIG_X86_64
250 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
251#endif
252 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
253};
254#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
255
256static inline bool is_page_fault(u32 intr_info)
257{
258 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
259 INTR_INFO_VALID_MASK)) ==
260 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
261}
262
263static inline bool is_no_device(u32 intr_info)
264{
265 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
266 INTR_INFO_VALID_MASK)) ==
267 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
268}
269
270static inline bool is_invalid_opcode(u32 intr_info)
271{
272 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
273 INTR_INFO_VALID_MASK)) ==
274 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
275}
276
277static inline bool is_external_interrupt(u32 intr_info)
278{
279 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
280 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
281}
282
283static inline bool is_machine_check(u32 intr_info)
284{
285 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
286 INTR_INFO_VALID_MASK)) ==
287 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
288}
289
290static inline bool cpu_has_vmx_msr_bitmap(void)
291{
292 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
293}
294
295static inline bool cpu_has_vmx_tpr_shadow(void)
296{
297 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
298}
299
300static inline bool vm_need_tpr_shadow(struct kvm *kvm)
301{
302 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
303}
304
305static inline bool cpu_has_secondary_exec_ctrls(void)
306{
307 return vmcs_config.cpu_based_exec_ctrl &
308 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
309}
310
311static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
312{
313 return vmcs_config.cpu_based_2nd_exec_ctrl &
314 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
315}
316
317static inline bool cpu_has_vmx_flexpriority(void)
318{
319 return cpu_has_vmx_tpr_shadow() &&
320 cpu_has_vmx_virtualize_apic_accesses();
321}
322
323static inline bool cpu_has_vmx_ept_execute_only(void)
324{
325 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
326}
327
328static inline bool cpu_has_vmx_eptp_uncacheable(void)
329{
330 return vmx_capability.ept & VMX_EPTP_UC_BIT;
331}
332
333static inline bool cpu_has_vmx_eptp_writeback(void)
334{
335 return vmx_capability.ept & VMX_EPTP_WB_BIT;
336}
337
338static inline bool cpu_has_vmx_ept_2m_page(void)
339{
340 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
341}
342
343static inline bool cpu_has_vmx_ept_1g_page(void)
344{
345 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
346}
347
348static inline bool cpu_has_vmx_ept_4levels(void)
349{
350 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
351}
352
353static inline bool cpu_has_vmx_invept_individual_addr(void)
354{
355 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
356}
357
358static inline bool cpu_has_vmx_invept_context(void)
359{
360 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
361}
362
363static inline bool cpu_has_vmx_invept_global(void)
364{
365 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
366}
367
368static inline bool cpu_has_vmx_invvpid_single(void)
369{
370 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
371}
372
373static inline bool cpu_has_vmx_invvpid_global(void)
374{
375 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
376}
377
378static inline bool cpu_has_vmx_ept(void)
379{
380 return vmcs_config.cpu_based_2nd_exec_ctrl &
381 SECONDARY_EXEC_ENABLE_EPT;
382}
383
384static inline bool cpu_has_vmx_unrestricted_guest(void)
385{
386 return vmcs_config.cpu_based_2nd_exec_ctrl &
387 SECONDARY_EXEC_UNRESTRICTED_GUEST;
388}
389
390static inline bool cpu_has_vmx_ple(void)
391{
392 return vmcs_config.cpu_based_2nd_exec_ctrl &
393 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
394}
395
396static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
397{
398 return flexpriority_enabled && irqchip_in_kernel(kvm);
399}
400
401static inline bool cpu_has_vmx_vpid(void)
402{
403 return vmcs_config.cpu_based_2nd_exec_ctrl &
404 SECONDARY_EXEC_ENABLE_VPID;
405}
406
407static inline bool cpu_has_vmx_rdtscp(void)
408{
409 return vmcs_config.cpu_based_2nd_exec_ctrl &
410 SECONDARY_EXEC_RDTSCP;
411}
412
413static inline bool cpu_has_virtual_nmis(void)
414{
415 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
416}
417
418static inline bool cpu_has_vmx_wbinvd_exit(void)
419{
420 return vmcs_config.cpu_based_2nd_exec_ctrl &
421 SECONDARY_EXEC_WBINVD_EXITING;
422}
423
424static inline bool report_flexpriority(void)
425{
426 return flexpriority_enabled;
427}
428
429static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
430{
431 int i;
432
433 for (i = 0; i < vmx->nmsrs; ++i)
434 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
435 return i;
436 return -1;
437}
438
439static inline void __invvpid(int ext, u16 vpid, gva_t gva)
440{
441 struct {
442 u64 vpid : 16;
443 u64 rsvd : 48;
444 u64 gva;
445 } operand = { vpid, 0, gva };
446
447 asm volatile (__ex(ASM_VMX_INVVPID)
448 /* CF==1 or ZF==1 --> rc = -1 */
449 "; ja 1f ; ud2 ; 1:"
450 : : "a"(&operand), "c"(ext) : "cc", "memory");
451}
452
453static inline void __invept(int ext, u64 eptp, gpa_t gpa)
454{
455 struct {
456 u64 eptp, gpa;
457 } operand = {eptp, gpa};
458
459 asm volatile (__ex(ASM_VMX_INVEPT)
460 /* CF==1 or ZF==1 --> rc = -1 */
461 "; ja 1f ; ud2 ; 1:\n"
462 : : "a" (&operand), "c" (ext) : "cc", "memory");
463}
464
465static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
466{
467 int i;
468
469 i = __find_msr_index(vmx, msr);
470 if (i >= 0)
471 return &vmx->guest_msrs[i];
472 return NULL;
473}
474
475static void vmcs_clear(struct vmcs *vmcs)
476{
477 u64 phys_addr = __pa(vmcs);
478 u8 error;
479
480 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
481 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
482 : "cc", "memory");
483 if (error)
484 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
485 vmcs, phys_addr);
486}
487
488static void vmcs_load(struct vmcs *vmcs)
489{
490 u64 phys_addr = __pa(vmcs);
491 u8 error;
492
493 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
494 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
495 : "cc", "memory");
496 if (error)
497 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
498 vmcs, phys_addr);
499}
500
501static void __vcpu_clear(void *arg)
502{
503 struct vcpu_vmx *vmx = arg;
504 int cpu = raw_smp_processor_id();
505
506 if (vmx->vcpu.cpu == cpu)
507 vmcs_clear(vmx->vmcs);
508 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
509 per_cpu(current_vmcs, cpu) = NULL;
510 list_del(&vmx->local_vcpus_link);
511 vmx->vcpu.cpu = -1;
512 vmx->launched = 0;
513}
514
515static void vcpu_clear(struct vcpu_vmx *vmx)
516{
517 if (vmx->vcpu.cpu == -1)
518 return;
519 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
520}
521
522static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
523{
524 if (vmx->vpid == 0)
525 return;
526
527 if (cpu_has_vmx_invvpid_single())
528 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
529}
530
531static inline void vpid_sync_vcpu_global(void)
532{
533 if (cpu_has_vmx_invvpid_global())
534 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
535}
536
537static inline void vpid_sync_context(struct vcpu_vmx *vmx)
538{
539 if (cpu_has_vmx_invvpid_single())
540 vpid_sync_vcpu_single(vmx);
541 else
542 vpid_sync_vcpu_global();
543}
544
545static inline void ept_sync_global(void)
546{
547 if (cpu_has_vmx_invept_global())
548 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
549}
550
551static inline void ept_sync_context(u64 eptp)
552{
553 if (enable_ept) {
554 if (cpu_has_vmx_invept_context())
555 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
556 else
557 ept_sync_global();
558 }
559}
560
561static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
562{
563 if (enable_ept) {
564 if (cpu_has_vmx_invept_individual_addr())
565 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
566 eptp, gpa);
567 else
568 ept_sync_context(eptp);
569 }
570}
571
572static unsigned long vmcs_readl(unsigned long field)
573{
574 unsigned long value = 0;
575
576 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
577 : "+a"(value) : "d"(field) : "cc");
578 return value;
579}
580
581static u16 vmcs_read16(unsigned long field)
582{
583 return vmcs_readl(field);
584}
585
586static u32 vmcs_read32(unsigned long field)
587{
588 return vmcs_readl(field);
589}
590
591static u64 vmcs_read64(unsigned long field)
592{
593#ifdef CONFIG_X86_64
594 return vmcs_readl(field);
595#else
596 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
597#endif
598}
599
600static noinline void vmwrite_error(unsigned long field, unsigned long value)
601{
602 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
603 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
604 dump_stack();
605}
606
607static void vmcs_writel(unsigned long field, unsigned long value)
608{
609 u8 error;
610
611 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
612 : "=q"(error) : "a"(value), "d"(field) : "cc");
613 if (unlikely(error))
614 vmwrite_error(field, value);
615}
616
617static void vmcs_write16(unsigned long field, u16 value)
618{
619 vmcs_writel(field, value);
620}
621
622static void vmcs_write32(unsigned long field, u32 value)
623{
624 vmcs_writel(field, value);
625}
626
627static void vmcs_write64(unsigned long field, u64 value)
628{
629 vmcs_writel(field, value);
630#ifndef CONFIG_X86_64
631 asm volatile ("");
632 vmcs_writel(field+1, value >> 32);
633#endif
634}
635
636static void vmcs_clear_bits(unsigned long field, u32 mask)
637{
638 vmcs_writel(field, vmcs_readl(field) & ~mask);
639}
640
641static void vmcs_set_bits(unsigned long field, u32 mask)
642{
643 vmcs_writel(field, vmcs_readl(field) | mask);
644}
645
646static void update_exception_bitmap(struct kvm_vcpu *vcpu)
647{
648 u32 eb;
649
650 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
651 (1u << NM_VECTOR) | (1u << DB_VECTOR);
652 if ((vcpu->guest_debug &
653 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
654 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
655 eb |= 1u << BP_VECTOR;
656 if (to_vmx(vcpu)->rmode.vm86_active)
657 eb = ~0;
658 if (enable_ept)
659 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
660 if (vcpu->fpu_active)
661 eb &= ~(1u << NM_VECTOR);
662 vmcs_write32(EXCEPTION_BITMAP, eb);
663}
664
665static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
666{
667 unsigned i;
668 struct msr_autoload *m = &vmx->msr_autoload;
669
670 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
671 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
672 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
673 return;
674 }
675
676 for (i = 0; i < m->nr; ++i)
677 if (m->guest[i].index == msr)
678 break;
679
680 if (i == m->nr)
681 return;
682 --m->nr;
683 m->guest[i] = m->guest[m->nr];
684 m->host[i] = m->host[m->nr];
685 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
686 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
687}
688
689static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
690 u64 guest_val, u64 host_val)
691{
692 unsigned i;
693 struct msr_autoload *m = &vmx->msr_autoload;
694
695 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
696 vmcs_write64(GUEST_IA32_EFER, guest_val);
697 vmcs_write64(HOST_IA32_EFER, host_val);
698 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
699 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
700 return;
701 }
702
703 for (i = 0; i < m->nr; ++i)
704 if (m->guest[i].index == msr)
705 break;
706
707 if (i == m->nr) {
708 ++m->nr;
709 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
710 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
711 }
712
713 m->guest[i].index = msr;
714 m->guest[i].value = guest_val;
715 m->host[i].index = msr;
716 m->host[i].value = host_val;
717}
718
719static void reload_tss(void)
720{
721 /*
722 * VT restores TR but not its size. Useless.
723 */
724 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
725 struct desc_struct *descs;
726
727 descs = (void *)gdt->address;
728 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
729 load_TR_desc();
730}
731
732static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
733{
734 u64 guest_efer;
735 u64 ignore_bits;
736
737 guest_efer = vmx->vcpu.arch.efer;
738
739 /*
740 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
741 * outside long mode
742 */
743 ignore_bits = EFER_NX | EFER_SCE;
744#ifdef CONFIG_X86_64
745 ignore_bits |= EFER_LMA | EFER_LME;
746 /* SCE is meaningful only in long mode on Intel */
747 if (guest_efer & EFER_LMA)
748 ignore_bits &= ~(u64)EFER_SCE;
749#endif
750 guest_efer &= ~ignore_bits;
751 guest_efer |= host_efer & ignore_bits;
752 vmx->guest_msrs[efer_offset].data = guest_efer;
753 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
754
755 clear_atomic_switch_msr(vmx, MSR_EFER);
756 /* On ept, can't emulate nx, and must switch nx atomically */
757 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
758 guest_efer = vmx->vcpu.arch.efer;
759 if (!(guest_efer & EFER_LMA))
760 guest_efer &= ~EFER_LME;
761 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
762 return false;
763 }
764
765 return true;
766}
767
768static unsigned long segment_base(u16 selector)
769{
770 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
771 struct desc_struct *d;
772 unsigned long table_base;
773 unsigned long v;
774
775 if (!(selector & ~3))
776 return 0;
777
778 table_base = gdt->address;
779
780 if (selector & 4) { /* from ldt */
781 u16 ldt_selector = kvm_read_ldt();
782
783 if (!(ldt_selector & ~3))
784 return 0;
785
786 table_base = segment_base(ldt_selector);
787 }
788 d = (struct desc_struct *)(table_base + (selector & ~7));
789 v = get_desc_base(d);
790#ifdef CONFIG_X86_64
791 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
792 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
793#endif
794 return v;
795}
796
797static inline unsigned long kvm_read_tr_base(void)
798{
799 u16 tr;
800 asm("str %0" : "=g"(tr));
801 return segment_base(tr);
802}
803
804static void vmx_save_host_state(struct kvm_vcpu *vcpu)
805{
806 struct vcpu_vmx *vmx = to_vmx(vcpu);
807 int i;
808
809 if (vmx->host_state.loaded)
810 return;
811
812 vmx->host_state.loaded = 1;
813 /*
814 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
815 * allow segment selectors with cpl > 0 or ti == 1.
816 */
817 vmx->host_state.ldt_sel = kvm_read_ldt();
818 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
819 savesegment(fs, vmx->host_state.fs_sel);
820 if (!(vmx->host_state.fs_sel & 7)) {
821 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
822 vmx->host_state.fs_reload_needed = 0;
823 } else {
824 vmcs_write16(HOST_FS_SELECTOR, 0);
825 vmx->host_state.fs_reload_needed = 1;
826 }
827 savesegment(gs, vmx->host_state.gs_sel);
828 if (!(vmx->host_state.gs_sel & 7))
829 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
830 else {
831 vmcs_write16(HOST_GS_SELECTOR, 0);
832 vmx->host_state.gs_ldt_reload_needed = 1;
833 }
834
835#ifdef CONFIG_X86_64
836 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
837 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
838#else
839 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
840 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
841#endif
842
843#ifdef CONFIG_X86_64
844 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
845 if (is_long_mode(&vmx->vcpu))
846 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
847#endif
848 for (i = 0; i < vmx->save_nmsrs; ++i)
849 kvm_set_shared_msr(vmx->guest_msrs[i].index,
850 vmx->guest_msrs[i].data,
851 vmx->guest_msrs[i].mask);
852}
853
854static void __vmx_load_host_state(struct vcpu_vmx *vmx)
855{
856 if (!vmx->host_state.loaded)
857 return;
858
859 ++vmx->vcpu.stat.host_state_reload;
860 vmx->host_state.loaded = 0;
861#ifdef CONFIG_X86_64
862 if (is_long_mode(&vmx->vcpu))
863 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
864#endif
865 if (vmx->host_state.gs_ldt_reload_needed) {
866 kvm_load_ldt(vmx->host_state.ldt_sel);
867#ifdef CONFIG_X86_64
868 load_gs_index(vmx->host_state.gs_sel);
869#else
870 loadsegment(gs, vmx->host_state.gs_sel);
871#endif
872 }
873 if (vmx->host_state.fs_reload_needed)
874 loadsegment(fs, vmx->host_state.fs_sel);
875 reload_tss();
876#ifdef CONFIG_X86_64
877 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
878#endif
879 if (current_thread_info()->status & TS_USEDFPU)
880 clts();
881 load_gdt(&__get_cpu_var(host_gdt));
882}
883
884static void vmx_load_host_state(struct vcpu_vmx *vmx)
885{
886 preempt_disable();
887 __vmx_load_host_state(vmx);
888 preempt_enable();
889}
890
891/*
892 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
893 * vcpu mutex is already taken.
894 */
895static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
896{
897 struct vcpu_vmx *vmx = to_vmx(vcpu);
898 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
899
900 if (!vmm_exclusive)
901 kvm_cpu_vmxon(phys_addr);
902 else if (vcpu->cpu != cpu)
903 vcpu_clear(vmx);
904
905 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
906 per_cpu(current_vmcs, cpu) = vmx->vmcs;
907 vmcs_load(vmx->vmcs);
908 }
909
910 if (vcpu->cpu != cpu) {
911 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
912 unsigned long sysenter_esp;
913
914 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
915 local_irq_disable();
916 list_add(&vmx->local_vcpus_link,
917 &per_cpu(vcpus_on_cpu, cpu));
918 local_irq_enable();
919
920 /*
921 * Linux uses per-cpu TSS and GDT, so set these when switching
922 * processors.
923 */
924 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
925 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
926
927 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
928 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
929 }
930}
931
932static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
933{
934 __vmx_load_host_state(to_vmx(vcpu));
935 if (!vmm_exclusive) {
936 __vcpu_clear(to_vmx(vcpu));
937 kvm_cpu_vmxoff();
938 }
939}
940
941static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
942{
943 ulong cr0;
944
945 if (vcpu->fpu_active)
946 return;
947 vcpu->fpu_active = 1;
948 cr0 = vmcs_readl(GUEST_CR0);
949 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
950 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
951 vmcs_writel(GUEST_CR0, cr0);
952 update_exception_bitmap(vcpu);
953 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
954 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
955}
956
957static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
958
959static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
960{
961 vmx_decache_cr0_guest_bits(vcpu);
962 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
963 update_exception_bitmap(vcpu);
964 vcpu->arch.cr0_guest_owned_bits = 0;
965 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
966 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
967}
968
969static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
970{
971 unsigned long rflags, save_rflags;
972
973 rflags = vmcs_readl(GUEST_RFLAGS);
974 if (to_vmx(vcpu)->rmode.vm86_active) {
975 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
976 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
977 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
978 }
979 return rflags;
980}
981
982static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
983{
984 if (to_vmx(vcpu)->rmode.vm86_active) {
985 to_vmx(vcpu)->rmode.save_rflags = rflags;
986 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
987 }
988 vmcs_writel(GUEST_RFLAGS, rflags);
989}
990
991static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
992{
993 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
994 int ret = 0;
995
996 if (interruptibility & GUEST_INTR_STATE_STI)
997 ret |= KVM_X86_SHADOW_INT_STI;
998 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
999 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1000
1001 return ret & mask;
1002}
1003
1004static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1005{
1006 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1007 u32 interruptibility = interruptibility_old;
1008
1009 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1010
1011 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1012 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1013 else if (mask & KVM_X86_SHADOW_INT_STI)
1014 interruptibility |= GUEST_INTR_STATE_STI;
1015
1016 if ((interruptibility != interruptibility_old))
1017 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1018}
1019
1020static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1021{
1022 unsigned long rip;
1023
1024 rip = kvm_rip_read(vcpu);
1025 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1026 kvm_rip_write(vcpu, rip);
1027
1028 /* skipping an emulated instruction also counts */
1029 vmx_set_interrupt_shadow(vcpu, 0);
1030}
1031
1032static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1033{
1034 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1035 * explicitly skip the instruction because if the HLT state is set, then
1036 * the instruction is already executing and RIP has already been
1037 * advanced. */
1038 if (!yield_on_hlt &&
1039 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1040 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1041}
1042
1043static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1044 bool has_error_code, u32 error_code,
1045 bool reinject)
1046{
1047 struct vcpu_vmx *vmx = to_vmx(vcpu);
1048 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1049
1050 if (has_error_code) {
1051 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1052 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1053 }
1054
1055 if (vmx->rmode.vm86_active) {
1056 if (kvm_inject_realmode_interrupt(vcpu, nr) != EMULATE_DONE)
1057 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1058 return;
1059 }
1060
1061 if (kvm_exception_is_soft(nr)) {
1062 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1063 vmx->vcpu.arch.event_exit_inst_len);
1064 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1065 } else
1066 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1067
1068 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1069 vmx_clear_hlt(vcpu);
1070}
1071
1072static bool vmx_rdtscp_supported(void)
1073{
1074 return cpu_has_vmx_rdtscp();
1075}
1076
1077/*
1078 * Swap MSR entry in host/guest MSR entry array.
1079 */
1080static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1081{
1082 struct shared_msr_entry tmp;
1083
1084 tmp = vmx->guest_msrs[to];
1085 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1086 vmx->guest_msrs[from] = tmp;
1087}
1088
1089/*
1090 * Set up the vmcs to automatically save and restore system
1091 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1092 * mode, as fiddling with msrs is very expensive.
1093 */
1094static void setup_msrs(struct vcpu_vmx *vmx)
1095{
1096 int save_nmsrs, index;
1097 unsigned long *msr_bitmap;
1098
1099 vmx_load_host_state(vmx);
1100 save_nmsrs = 0;
1101#ifdef CONFIG_X86_64
1102 if (is_long_mode(&vmx->vcpu)) {
1103 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1104 if (index >= 0)
1105 move_msr_up(vmx, index, save_nmsrs++);
1106 index = __find_msr_index(vmx, MSR_LSTAR);
1107 if (index >= 0)
1108 move_msr_up(vmx, index, save_nmsrs++);
1109 index = __find_msr_index(vmx, MSR_CSTAR);
1110 if (index >= 0)
1111 move_msr_up(vmx, index, save_nmsrs++);
1112 index = __find_msr_index(vmx, MSR_TSC_AUX);
1113 if (index >= 0 && vmx->rdtscp_enabled)
1114 move_msr_up(vmx, index, save_nmsrs++);
1115 /*
1116 * MSR_STAR is only needed on long mode guests, and only
1117 * if efer.sce is enabled.
1118 */
1119 index = __find_msr_index(vmx, MSR_STAR);
1120 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1121 move_msr_up(vmx, index, save_nmsrs++);
1122 }
1123#endif
1124 index = __find_msr_index(vmx, MSR_EFER);
1125 if (index >= 0 && update_transition_efer(vmx, index))
1126 move_msr_up(vmx, index, save_nmsrs++);
1127
1128 vmx->save_nmsrs = save_nmsrs;
1129
1130 if (cpu_has_vmx_msr_bitmap()) {
1131 if (is_long_mode(&vmx->vcpu))
1132 msr_bitmap = vmx_msr_bitmap_longmode;
1133 else
1134 msr_bitmap = vmx_msr_bitmap_legacy;
1135
1136 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1137 }
1138}
1139
1140/*
1141 * reads and returns guest's timestamp counter "register"
1142 * guest_tsc = host_tsc + tsc_offset -- 21.3
1143 */
1144static u64 guest_read_tsc(void)
1145{
1146 u64 host_tsc, tsc_offset;
1147
1148 rdtscll(host_tsc);
1149 tsc_offset = vmcs_read64(TSC_OFFSET);
1150 return host_tsc + tsc_offset;
1151}
1152
1153/*
1154 * writes 'offset' into guest's timestamp counter offset register
1155 */
1156static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1157{
1158 vmcs_write64(TSC_OFFSET, offset);
1159}
1160
1161static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1162{
1163 u64 offset = vmcs_read64(TSC_OFFSET);
1164 vmcs_write64(TSC_OFFSET, offset + adjustment);
1165}
1166
1167/*
1168 * Reads an msr value (of 'msr_index') into 'pdata'.
1169 * Returns 0 on success, non-0 otherwise.
1170 * Assumes vcpu_load() was already called.
1171 */
1172static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1173{
1174 u64 data;
1175 struct shared_msr_entry *msr;
1176
1177 if (!pdata) {
1178 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1179 return -EINVAL;
1180 }
1181
1182 switch (msr_index) {
1183#ifdef CONFIG_X86_64
1184 case MSR_FS_BASE:
1185 data = vmcs_readl(GUEST_FS_BASE);
1186 break;
1187 case MSR_GS_BASE:
1188 data = vmcs_readl(GUEST_GS_BASE);
1189 break;
1190 case MSR_KERNEL_GS_BASE:
1191 vmx_load_host_state(to_vmx(vcpu));
1192 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1193 break;
1194#endif
1195 case MSR_EFER:
1196 return kvm_get_msr_common(vcpu, msr_index, pdata);
1197 case MSR_IA32_TSC:
1198 data = guest_read_tsc();
1199 break;
1200 case MSR_IA32_SYSENTER_CS:
1201 data = vmcs_read32(GUEST_SYSENTER_CS);
1202 break;
1203 case MSR_IA32_SYSENTER_EIP:
1204 data = vmcs_readl(GUEST_SYSENTER_EIP);
1205 break;
1206 case MSR_IA32_SYSENTER_ESP:
1207 data = vmcs_readl(GUEST_SYSENTER_ESP);
1208 break;
1209 case MSR_TSC_AUX:
1210 if (!to_vmx(vcpu)->rdtscp_enabled)
1211 return 1;
1212 /* Otherwise falls through */
1213 default:
1214 vmx_load_host_state(to_vmx(vcpu));
1215 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1216 if (msr) {
1217 vmx_load_host_state(to_vmx(vcpu));
1218 data = msr->data;
1219 break;
1220 }
1221 return kvm_get_msr_common(vcpu, msr_index, pdata);
1222 }
1223
1224 *pdata = data;
1225 return 0;
1226}
1227
1228/*
1229 * Writes msr value into into the appropriate "register".
1230 * Returns 0 on success, non-0 otherwise.
1231 * Assumes vcpu_load() was already called.
1232 */
1233static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1234{
1235 struct vcpu_vmx *vmx = to_vmx(vcpu);
1236 struct shared_msr_entry *msr;
1237 int ret = 0;
1238
1239 switch (msr_index) {
1240 case MSR_EFER:
1241 vmx_load_host_state(vmx);
1242 ret = kvm_set_msr_common(vcpu, msr_index, data);
1243 break;
1244#ifdef CONFIG_X86_64
1245 case MSR_FS_BASE:
1246 vmcs_writel(GUEST_FS_BASE, data);
1247 break;
1248 case MSR_GS_BASE:
1249 vmcs_writel(GUEST_GS_BASE, data);
1250 break;
1251 case MSR_KERNEL_GS_BASE:
1252 vmx_load_host_state(vmx);
1253 vmx->msr_guest_kernel_gs_base = data;
1254 break;
1255#endif
1256 case MSR_IA32_SYSENTER_CS:
1257 vmcs_write32(GUEST_SYSENTER_CS, data);
1258 break;
1259 case MSR_IA32_SYSENTER_EIP:
1260 vmcs_writel(GUEST_SYSENTER_EIP, data);
1261 break;
1262 case MSR_IA32_SYSENTER_ESP:
1263 vmcs_writel(GUEST_SYSENTER_ESP, data);
1264 break;
1265 case MSR_IA32_TSC:
1266 kvm_write_tsc(vcpu, data);
1267 break;
1268 case MSR_IA32_CR_PAT:
1269 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1270 vmcs_write64(GUEST_IA32_PAT, data);
1271 vcpu->arch.pat = data;
1272 break;
1273 }
1274 ret = kvm_set_msr_common(vcpu, msr_index, data);
1275 break;
1276 case MSR_TSC_AUX:
1277 if (!vmx->rdtscp_enabled)
1278 return 1;
1279 /* Check reserved bit, higher 32 bits should be zero */
1280 if ((data >> 32) != 0)
1281 return 1;
1282 /* Otherwise falls through */
1283 default:
1284 msr = find_msr_entry(vmx, msr_index);
1285 if (msr) {
1286 vmx_load_host_state(vmx);
1287 msr->data = data;
1288 break;
1289 }
1290 ret = kvm_set_msr_common(vcpu, msr_index, data);
1291 }
1292
1293 return ret;
1294}
1295
1296static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1297{
1298 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1299 switch (reg) {
1300 case VCPU_REGS_RSP:
1301 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1302 break;
1303 case VCPU_REGS_RIP:
1304 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1305 break;
1306 case VCPU_EXREG_PDPTR:
1307 if (enable_ept)
1308 ept_save_pdptrs(vcpu);
1309 break;
1310 default:
1311 break;
1312 }
1313}
1314
1315static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1316{
1317 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1318 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1319 else
1320 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1321
1322 update_exception_bitmap(vcpu);
1323}
1324
1325static __init int cpu_has_kvm_support(void)
1326{
1327 return cpu_has_vmx();
1328}
1329
1330static __init int vmx_disabled_by_bios(void)
1331{
1332 u64 msr;
1333
1334 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1335 if (msr & FEATURE_CONTROL_LOCKED) {
1336 /* launched w/ TXT and VMX disabled */
1337 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1338 && tboot_enabled())
1339 return 1;
1340 /* launched w/o TXT and VMX only enabled w/ TXT */
1341 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1342 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1343 && !tboot_enabled()) {
1344 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
1345 "activate TXT before enabling KVM\n");
1346 return 1;
1347 }
1348 /* launched w/o TXT and VMX disabled */
1349 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1350 && !tboot_enabled())
1351 return 1;
1352 }
1353
1354 return 0;
1355}
1356
1357static void kvm_cpu_vmxon(u64 addr)
1358{
1359 asm volatile (ASM_VMX_VMXON_RAX
1360 : : "a"(&addr), "m"(addr)
1361 : "memory", "cc");
1362}
1363
1364static int hardware_enable(void *garbage)
1365{
1366 int cpu = raw_smp_processor_id();
1367 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1368 u64 old, test_bits;
1369
1370 if (read_cr4() & X86_CR4_VMXE)
1371 return -EBUSY;
1372
1373 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1374 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1375
1376 test_bits = FEATURE_CONTROL_LOCKED;
1377 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1378 if (tboot_enabled())
1379 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1380
1381 if ((old & test_bits) != test_bits) {
1382 /* enable and lock */
1383 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1384 }
1385 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1386
1387 if (vmm_exclusive) {
1388 kvm_cpu_vmxon(phys_addr);
1389 ept_sync_global();
1390 }
1391
1392 store_gdt(&__get_cpu_var(host_gdt));
1393
1394 return 0;
1395}
1396
1397static void vmclear_local_vcpus(void)
1398{
1399 int cpu = raw_smp_processor_id();
1400 struct vcpu_vmx *vmx, *n;
1401
1402 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1403 local_vcpus_link)
1404 __vcpu_clear(vmx);
1405}
1406
1407
1408/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1409 * tricks.
1410 */
1411static void kvm_cpu_vmxoff(void)
1412{
1413 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1414}
1415
1416static void hardware_disable(void *garbage)
1417{
1418 if (vmm_exclusive) {
1419 vmclear_local_vcpus();
1420 kvm_cpu_vmxoff();
1421 }
1422 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1423}
1424
1425static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1426 u32 msr, u32 *result)
1427{
1428 u32 vmx_msr_low, vmx_msr_high;
1429 u32 ctl = ctl_min | ctl_opt;
1430
1431 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1432
1433 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1434 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1435
1436 /* Ensure minimum (required) set of control bits are supported. */
1437 if (ctl_min & ~ctl)
1438 return -EIO;
1439
1440 *result = ctl;
1441 return 0;
1442}
1443
1444static __init bool allow_1_setting(u32 msr, u32 ctl)
1445{
1446 u32 vmx_msr_low, vmx_msr_high;
1447
1448 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1449 return vmx_msr_high & ctl;
1450}
1451
1452static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1453{
1454 u32 vmx_msr_low, vmx_msr_high;
1455 u32 min, opt, min2, opt2;
1456 u32 _pin_based_exec_control = 0;
1457 u32 _cpu_based_exec_control = 0;
1458 u32 _cpu_based_2nd_exec_control = 0;
1459 u32 _vmexit_control = 0;
1460 u32 _vmentry_control = 0;
1461
1462 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1463 opt = PIN_BASED_VIRTUAL_NMIS;
1464 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1465 &_pin_based_exec_control) < 0)
1466 return -EIO;
1467
1468 min =
1469#ifdef CONFIG_X86_64
1470 CPU_BASED_CR8_LOAD_EXITING |
1471 CPU_BASED_CR8_STORE_EXITING |
1472#endif
1473 CPU_BASED_CR3_LOAD_EXITING |
1474 CPU_BASED_CR3_STORE_EXITING |
1475 CPU_BASED_USE_IO_BITMAPS |
1476 CPU_BASED_MOV_DR_EXITING |
1477 CPU_BASED_USE_TSC_OFFSETING |
1478 CPU_BASED_MWAIT_EXITING |
1479 CPU_BASED_MONITOR_EXITING |
1480 CPU_BASED_INVLPG_EXITING;
1481
1482 if (yield_on_hlt)
1483 min |= CPU_BASED_HLT_EXITING;
1484
1485 opt = CPU_BASED_TPR_SHADOW |
1486 CPU_BASED_USE_MSR_BITMAPS |
1487 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1488 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1489 &_cpu_based_exec_control) < 0)
1490 return -EIO;
1491#ifdef CONFIG_X86_64
1492 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1493 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1494 ~CPU_BASED_CR8_STORE_EXITING;
1495#endif
1496 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1497 min2 = 0;
1498 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1499 SECONDARY_EXEC_WBINVD_EXITING |
1500 SECONDARY_EXEC_ENABLE_VPID |
1501 SECONDARY_EXEC_ENABLE_EPT |
1502 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1503 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1504 SECONDARY_EXEC_RDTSCP;
1505 if (adjust_vmx_controls(min2, opt2,
1506 MSR_IA32_VMX_PROCBASED_CTLS2,
1507 &_cpu_based_2nd_exec_control) < 0)
1508 return -EIO;
1509 }
1510#ifndef CONFIG_X86_64
1511 if (!(_cpu_based_2nd_exec_control &
1512 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1513 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1514#endif
1515 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1516 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1517 enabled */
1518 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1519 CPU_BASED_CR3_STORE_EXITING |
1520 CPU_BASED_INVLPG_EXITING);
1521 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1522 vmx_capability.ept, vmx_capability.vpid);
1523 }
1524
1525 min = 0;
1526#ifdef CONFIG_X86_64
1527 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1528#endif
1529 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1530 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1531 &_vmexit_control) < 0)
1532 return -EIO;
1533
1534 min = 0;
1535 opt = VM_ENTRY_LOAD_IA32_PAT;
1536 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1537 &_vmentry_control) < 0)
1538 return -EIO;
1539
1540 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1541
1542 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1543 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1544 return -EIO;
1545
1546#ifdef CONFIG_X86_64
1547 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1548 if (vmx_msr_high & (1u<<16))
1549 return -EIO;
1550#endif
1551
1552 /* Require Write-Back (WB) memory type for VMCS accesses. */
1553 if (((vmx_msr_high >> 18) & 15) != 6)
1554 return -EIO;
1555
1556 vmcs_conf->size = vmx_msr_high & 0x1fff;
1557 vmcs_conf->order = get_order(vmcs_config.size);
1558 vmcs_conf->revision_id = vmx_msr_low;
1559
1560 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1561 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1562 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1563 vmcs_conf->vmexit_ctrl = _vmexit_control;
1564 vmcs_conf->vmentry_ctrl = _vmentry_control;
1565
1566 cpu_has_load_ia32_efer =
1567 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
1568 VM_ENTRY_LOAD_IA32_EFER)
1569 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
1570 VM_EXIT_LOAD_IA32_EFER);
1571
1572 return 0;
1573}
1574
1575static struct vmcs *alloc_vmcs_cpu(int cpu)
1576{
1577 int node = cpu_to_node(cpu);
1578 struct page *pages;
1579 struct vmcs *vmcs;
1580
1581 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1582 if (!pages)
1583 return NULL;
1584 vmcs = page_address(pages);
1585 memset(vmcs, 0, vmcs_config.size);
1586 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1587 return vmcs;
1588}
1589
1590static struct vmcs *alloc_vmcs(void)
1591{
1592 return alloc_vmcs_cpu(raw_smp_processor_id());
1593}
1594
1595static void free_vmcs(struct vmcs *vmcs)
1596{
1597 free_pages((unsigned long)vmcs, vmcs_config.order);
1598}
1599
1600static void free_kvm_area(void)
1601{
1602 int cpu;
1603
1604 for_each_possible_cpu(cpu) {
1605 free_vmcs(per_cpu(vmxarea, cpu));
1606 per_cpu(vmxarea, cpu) = NULL;
1607 }
1608}
1609
1610static __init int alloc_kvm_area(void)
1611{
1612 int cpu;
1613
1614 for_each_possible_cpu(cpu) {
1615 struct vmcs *vmcs;
1616
1617 vmcs = alloc_vmcs_cpu(cpu);
1618 if (!vmcs) {
1619 free_kvm_area();
1620 return -ENOMEM;
1621 }
1622
1623 per_cpu(vmxarea, cpu) = vmcs;
1624 }
1625 return 0;
1626}
1627
1628static __init int hardware_setup(void)
1629{
1630 if (setup_vmcs_config(&vmcs_config) < 0)
1631 return -EIO;
1632
1633 if (boot_cpu_has(X86_FEATURE_NX))
1634 kvm_enable_efer_bits(EFER_NX);
1635
1636 if (!cpu_has_vmx_vpid())
1637 enable_vpid = 0;
1638
1639 if (!cpu_has_vmx_ept() ||
1640 !cpu_has_vmx_ept_4levels()) {
1641 enable_ept = 0;
1642 enable_unrestricted_guest = 0;
1643 }
1644
1645 if (!cpu_has_vmx_unrestricted_guest())
1646 enable_unrestricted_guest = 0;
1647
1648 if (!cpu_has_vmx_flexpriority())
1649 flexpriority_enabled = 0;
1650
1651 if (!cpu_has_vmx_tpr_shadow())
1652 kvm_x86_ops->update_cr8_intercept = NULL;
1653
1654 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1655 kvm_disable_largepages();
1656
1657 if (!cpu_has_vmx_ple())
1658 ple_gap = 0;
1659
1660 return alloc_kvm_area();
1661}
1662
1663static __exit void hardware_unsetup(void)
1664{
1665 free_kvm_area();
1666}
1667
1668static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1669{
1670 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1671
1672 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1673 vmcs_write16(sf->selector, save->selector);
1674 vmcs_writel(sf->base, save->base);
1675 vmcs_write32(sf->limit, save->limit);
1676 vmcs_write32(sf->ar_bytes, save->ar);
1677 } else {
1678 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1679 << AR_DPL_SHIFT;
1680 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1681 }
1682}
1683
1684static void enter_pmode(struct kvm_vcpu *vcpu)
1685{
1686 unsigned long flags;
1687 struct vcpu_vmx *vmx = to_vmx(vcpu);
1688
1689 vmx->emulation_required = 1;
1690 vmx->rmode.vm86_active = 0;
1691
1692 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
1693 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1694 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1695 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1696
1697 flags = vmcs_readl(GUEST_RFLAGS);
1698 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1699 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1700 vmcs_writel(GUEST_RFLAGS, flags);
1701
1702 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1703 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1704
1705 update_exception_bitmap(vcpu);
1706
1707 if (emulate_invalid_guest_state)
1708 return;
1709
1710 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1711 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1712 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1713 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1714
1715 vmcs_write16(GUEST_SS_SELECTOR, 0);
1716 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1717
1718 vmcs_write16(GUEST_CS_SELECTOR,
1719 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1720 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1721}
1722
1723static gva_t rmode_tss_base(struct kvm *kvm)
1724{
1725 if (!kvm->arch.tss_addr) {
1726 struct kvm_memslots *slots;
1727 gfn_t base_gfn;
1728
1729 slots = kvm_memslots(kvm);
1730 base_gfn = slots->memslots[0].base_gfn +
1731 kvm->memslots->memslots[0].npages - 3;
1732 return base_gfn << PAGE_SHIFT;
1733 }
1734 return kvm->arch.tss_addr;
1735}
1736
1737static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1738{
1739 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1740
1741 save->selector = vmcs_read16(sf->selector);
1742 save->base = vmcs_readl(sf->base);
1743 save->limit = vmcs_read32(sf->limit);
1744 save->ar = vmcs_read32(sf->ar_bytes);
1745 vmcs_write16(sf->selector, save->base >> 4);
1746 vmcs_write32(sf->base, save->base & 0xffff0);
1747 vmcs_write32(sf->limit, 0xffff);
1748 vmcs_write32(sf->ar_bytes, 0xf3);
1749 if (save->base & 0xf)
1750 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
1751 " aligned when entering protected mode (seg=%d)",
1752 seg);
1753}
1754
1755static void enter_rmode(struct kvm_vcpu *vcpu)
1756{
1757 unsigned long flags;
1758 struct vcpu_vmx *vmx = to_vmx(vcpu);
1759
1760 if (enable_unrestricted_guest)
1761 return;
1762
1763 vmx->emulation_required = 1;
1764 vmx->rmode.vm86_active = 1;
1765
1766 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
1767 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1768 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1769
1770 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1771 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1772
1773 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1774 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1775
1776 flags = vmcs_readl(GUEST_RFLAGS);
1777 vmx->rmode.save_rflags = flags;
1778
1779 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1780
1781 vmcs_writel(GUEST_RFLAGS, flags);
1782 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1783 update_exception_bitmap(vcpu);
1784
1785 if (emulate_invalid_guest_state)
1786 goto continue_rmode;
1787
1788 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1789 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1790 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1791
1792 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1793 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1794 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1795 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1796 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1797
1798 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1799 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1800 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1801 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1802
1803continue_rmode:
1804 kvm_mmu_reset_context(vcpu);
1805 init_rmode(vcpu->kvm);
1806}
1807
1808static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1809{
1810 struct vcpu_vmx *vmx = to_vmx(vcpu);
1811 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1812
1813 if (!msr)
1814 return;
1815
1816 /*
1817 * Force kernel_gs_base reloading before EFER changes, as control
1818 * of this msr depends on is_long_mode().
1819 */
1820 vmx_load_host_state(to_vmx(vcpu));
1821 vcpu->arch.efer = efer;
1822 if (efer & EFER_LMA) {
1823 vmcs_write32(VM_ENTRY_CONTROLS,
1824 vmcs_read32(VM_ENTRY_CONTROLS) |
1825 VM_ENTRY_IA32E_MODE);
1826 msr->data = efer;
1827 } else {
1828 vmcs_write32(VM_ENTRY_CONTROLS,
1829 vmcs_read32(VM_ENTRY_CONTROLS) &
1830 ~VM_ENTRY_IA32E_MODE);
1831
1832 msr->data = efer & ~EFER_LME;
1833 }
1834 setup_msrs(vmx);
1835}
1836
1837#ifdef CONFIG_X86_64
1838
1839static void enter_lmode(struct kvm_vcpu *vcpu)
1840{
1841 u32 guest_tr_ar;
1842
1843 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1844 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1845 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1846 __func__);
1847 vmcs_write32(GUEST_TR_AR_BYTES,
1848 (guest_tr_ar & ~AR_TYPE_MASK)
1849 | AR_TYPE_BUSY_64_TSS);
1850 }
1851 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
1852}
1853
1854static void exit_lmode(struct kvm_vcpu *vcpu)
1855{
1856 vmcs_write32(VM_ENTRY_CONTROLS,
1857 vmcs_read32(VM_ENTRY_CONTROLS)
1858 & ~VM_ENTRY_IA32E_MODE);
1859 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
1860}
1861
1862#endif
1863
1864static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1865{
1866 vpid_sync_context(to_vmx(vcpu));
1867 if (enable_ept) {
1868 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1869 return;
1870 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1871 }
1872}
1873
1874static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1875{
1876 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1877
1878 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1879 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1880}
1881
1882static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
1883{
1884 if (enable_ept && is_paging(vcpu))
1885 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1886 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
1887}
1888
1889static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1890{
1891 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1892
1893 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1894 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1895}
1896
1897static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1898{
1899 if (!test_bit(VCPU_EXREG_PDPTR,
1900 (unsigned long *)&vcpu->arch.regs_dirty))
1901 return;
1902
1903 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1904 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
1905 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
1906 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
1907 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1908 }
1909}
1910
1911static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1912{
1913 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1914 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1915 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1916 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1917 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1918 }
1919
1920 __set_bit(VCPU_EXREG_PDPTR,
1921 (unsigned long *)&vcpu->arch.regs_avail);
1922 __set_bit(VCPU_EXREG_PDPTR,
1923 (unsigned long *)&vcpu->arch.regs_dirty);
1924}
1925
1926static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1927
1928static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1929 unsigned long cr0,
1930 struct kvm_vcpu *vcpu)
1931{
1932 vmx_decache_cr3(vcpu);
1933 if (!(cr0 & X86_CR0_PG)) {
1934 /* From paging/starting to nonpaging */
1935 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1936 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1937 (CPU_BASED_CR3_LOAD_EXITING |
1938 CPU_BASED_CR3_STORE_EXITING));
1939 vcpu->arch.cr0 = cr0;
1940 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1941 } else if (!is_paging(vcpu)) {
1942 /* From nonpaging to paging */
1943 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1944 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1945 ~(CPU_BASED_CR3_LOAD_EXITING |
1946 CPU_BASED_CR3_STORE_EXITING));
1947 vcpu->arch.cr0 = cr0;
1948 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1949 }
1950
1951 if (!(cr0 & X86_CR0_WP))
1952 *hw_cr0 &= ~X86_CR0_WP;
1953}
1954
1955static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1956{
1957 struct vcpu_vmx *vmx = to_vmx(vcpu);
1958 unsigned long hw_cr0;
1959
1960 if (enable_unrestricted_guest)
1961 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1962 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1963 else
1964 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1965
1966 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1967 enter_pmode(vcpu);
1968
1969 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1970 enter_rmode(vcpu);
1971
1972#ifdef CONFIG_X86_64
1973 if (vcpu->arch.efer & EFER_LME) {
1974 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1975 enter_lmode(vcpu);
1976 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1977 exit_lmode(vcpu);
1978 }
1979#endif
1980
1981 if (enable_ept)
1982 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1983
1984 if (!vcpu->fpu_active)
1985 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1986
1987 vmcs_writel(CR0_READ_SHADOW, cr0);
1988 vmcs_writel(GUEST_CR0, hw_cr0);
1989 vcpu->arch.cr0 = cr0;
1990}
1991
1992static u64 construct_eptp(unsigned long root_hpa)
1993{
1994 u64 eptp;
1995
1996 /* TODO write the value reading from MSR */
1997 eptp = VMX_EPT_DEFAULT_MT |
1998 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1999 eptp |= (root_hpa & PAGE_MASK);
2000
2001 return eptp;
2002}
2003
2004static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2005{
2006 unsigned long guest_cr3;
2007 u64 eptp;
2008
2009 guest_cr3 = cr3;
2010 if (enable_ept) {
2011 eptp = construct_eptp(cr3);
2012 vmcs_write64(EPT_POINTER, eptp);
2013 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
2014 vcpu->kvm->arch.ept_identity_map_addr;
2015 ept_load_pdptrs(vcpu);
2016 }
2017
2018 vmx_flush_tlb(vcpu);
2019 vmcs_writel(GUEST_CR3, guest_cr3);
2020}
2021
2022static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2023{
2024 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
2025 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2026
2027 vcpu->arch.cr4 = cr4;
2028 if (enable_ept) {
2029 if (!is_paging(vcpu)) {
2030 hw_cr4 &= ~X86_CR4_PAE;
2031 hw_cr4 |= X86_CR4_PSE;
2032 } else if (!(cr4 & X86_CR4_PAE)) {
2033 hw_cr4 &= ~X86_CR4_PAE;
2034 }
2035 }
2036
2037 vmcs_writel(CR4_READ_SHADOW, cr4);
2038 vmcs_writel(GUEST_CR4, hw_cr4);
2039}
2040
2041static void vmx_get_segment(struct kvm_vcpu *vcpu,
2042 struct kvm_segment *var, int seg)
2043{
2044 struct vcpu_vmx *vmx = to_vmx(vcpu);
2045 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2046 struct kvm_save_segment *save;
2047 u32 ar;
2048
2049 if (vmx->rmode.vm86_active
2050 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2051 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2052 || seg == VCPU_SREG_GS)
2053 && !emulate_invalid_guest_state) {
2054 switch (seg) {
2055 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2056 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2057 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2058 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2059 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2060 default: BUG();
2061 }
2062 var->selector = save->selector;
2063 var->base = save->base;
2064 var->limit = save->limit;
2065 ar = save->ar;
2066 if (seg == VCPU_SREG_TR
2067 || var->selector == vmcs_read16(sf->selector))
2068 goto use_saved_rmode_seg;
2069 }
2070 var->base = vmcs_readl(sf->base);
2071 var->limit = vmcs_read32(sf->limit);
2072 var->selector = vmcs_read16(sf->selector);
2073 ar = vmcs_read32(sf->ar_bytes);
2074use_saved_rmode_seg:
2075 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2076 ar = 0;
2077 var->type = ar & 15;
2078 var->s = (ar >> 4) & 1;
2079 var->dpl = (ar >> 5) & 3;
2080 var->present = (ar >> 7) & 1;
2081 var->avl = (ar >> 12) & 1;
2082 var->l = (ar >> 13) & 1;
2083 var->db = (ar >> 14) & 1;
2084 var->g = (ar >> 15) & 1;
2085 var->unusable = (ar >> 16) & 1;
2086}
2087
2088static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2089{
2090 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2091 struct kvm_segment s;
2092
2093 if (to_vmx(vcpu)->rmode.vm86_active) {
2094 vmx_get_segment(vcpu, &s, seg);
2095 return s.base;
2096 }
2097 return vmcs_readl(sf->base);
2098}
2099
2100static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2101{
2102 if (!is_protmode(vcpu))
2103 return 0;
2104
2105 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2106 return 3;
2107
2108 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2109}
2110
2111static u32 vmx_segment_access_rights(struct kvm_segment *var)
2112{
2113 u32 ar;
2114
2115 if (var->unusable)
2116 ar = 1 << 16;
2117 else {
2118 ar = var->type & 15;
2119 ar |= (var->s & 1) << 4;
2120 ar |= (var->dpl & 3) << 5;
2121 ar |= (var->present & 1) << 7;
2122 ar |= (var->avl & 1) << 12;
2123 ar |= (var->l & 1) << 13;
2124 ar |= (var->db & 1) << 14;
2125 ar |= (var->g & 1) << 15;
2126 }
2127 if (ar == 0) /* a 0 value means unusable */
2128 ar = AR_UNUSABLE_MASK;
2129
2130 return ar;
2131}
2132
2133static void vmx_set_segment(struct kvm_vcpu *vcpu,
2134 struct kvm_segment *var, int seg)
2135{
2136 struct vcpu_vmx *vmx = to_vmx(vcpu);
2137 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2138 u32 ar;
2139
2140 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2141 vmx->rmode.tr.selector = var->selector;
2142 vmx->rmode.tr.base = var->base;
2143 vmx->rmode.tr.limit = var->limit;
2144 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2145 return;
2146 }
2147 vmcs_writel(sf->base, var->base);
2148 vmcs_write32(sf->limit, var->limit);
2149 vmcs_write16(sf->selector, var->selector);
2150 if (vmx->rmode.vm86_active && var->s) {
2151 /*
2152 * Hack real-mode segments into vm86 compatibility.
2153 */
2154 if (var->base == 0xffff0000 && var->selector == 0xf000)
2155 vmcs_writel(sf->base, 0xf0000);
2156 ar = 0xf3;
2157 } else
2158 ar = vmx_segment_access_rights(var);
2159
2160 /*
2161 * Fix the "Accessed" bit in AR field of segment registers for older
2162 * qemu binaries.
2163 * IA32 arch specifies that at the time of processor reset the
2164 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2165 * is setting it to 0 in the usedland code. This causes invalid guest
2166 * state vmexit when "unrestricted guest" mode is turned on.
2167 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2168 * tree. Newer qemu binaries with that qemu fix would not need this
2169 * kvm hack.
2170 */
2171 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2172 ar |= 0x1; /* Accessed */
2173
2174 vmcs_write32(sf->ar_bytes, ar);
2175}
2176
2177static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2178{
2179 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2180
2181 *db = (ar >> 14) & 1;
2182 *l = (ar >> 13) & 1;
2183}
2184
2185static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2186{
2187 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2188 dt->address = vmcs_readl(GUEST_IDTR_BASE);
2189}
2190
2191static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2192{
2193 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2194 vmcs_writel(GUEST_IDTR_BASE, dt->address);
2195}
2196
2197static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2198{
2199 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2200 dt->address = vmcs_readl(GUEST_GDTR_BASE);
2201}
2202
2203static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2204{
2205 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2206 vmcs_writel(GUEST_GDTR_BASE, dt->address);
2207}
2208
2209static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2210{
2211 struct kvm_segment var;
2212 u32 ar;
2213
2214 vmx_get_segment(vcpu, &var, seg);
2215 ar = vmx_segment_access_rights(&var);
2216
2217 if (var.base != (var.selector << 4))
2218 return false;
2219 if (var.limit != 0xffff)
2220 return false;
2221 if (ar != 0xf3)
2222 return false;
2223
2224 return true;
2225}
2226
2227static bool code_segment_valid(struct kvm_vcpu *vcpu)
2228{
2229 struct kvm_segment cs;
2230 unsigned int cs_rpl;
2231
2232 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2233 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2234
2235 if (cs.unusable)
2236 return false;
2237 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2238 return false;
2239 if (!cs.s)
2240 return false;
2241 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2242 if (cs.dpl > cs_rpl)
2243 return false;
2244 } else {
2245 if (cs.dpl != cs_rpl)
2246 return false;
2247 }
2248 if (!cs.present)
2249 return false;
2250
2251 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2252 return true;
2253}
2254
2255static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2256{
2257 struct kvm_segment ss;
2258 unsigned int ss_rpl;
2259
2260 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2261 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2262
2263 if (ss.unusable)
2264 return true;
2265 if (ss.type != 3 && ss.type != 7)
2266 return false;
2267 if (!ss.s)
2268 return false;
2269 if (ss.dpl != ss_rpl) /* DPL != RPL */
2270 return false;
2271 if (!ss.present)
2272 return false;
2273
2274 return true;
2275}
2276
2277static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2278{
2279 struct kvm_segment var;
2280 unsigned int rpl;
2281
2282 vmx_get_segment(vcpu, &var, seg);
2283 rpl = var.selector & SELECTOR_RPL_MASK;
2284
2285 if (var.unusable)
2286 return true;
2287 if (!var.s)
2288 return false;
2289 if (!var.present)
2290 return false;
2291 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2292 if (var.dpl < rpl) /* DPL < RPL */
2293 return false;
2294 }
2295
2296 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2297 * rights flags
2298 */
2299 return true;
2300}
2301
2302static bool tr_valid(struct kvm_vcpu *vcpu)
2303{
2304 struct kvm_segment tr;
2305
2306 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2307
2308 if (tr.unusable)
2309 return false;
2310 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2311 return false;
2312 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2313 return false;
2314 if (!tr.present)
2315 return false;
2316
2317 return true;
2318}
2319
2320static bool ldtr_valid(struct kvm_vcpu *vcpu)
2321{
2322 struct kvm_segment ldtr;
2323
2324 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2325
2326 if (ldtr.unusable)
2327 return true;
2328 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2329 return false;
2330 if (ldtr.type != 2)
2331 return false;
2332 if (!ldtr.present)
2333 return false;
2334
2335 return true;
2336}
2337
2338static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2339{
2340 struct kvm_segment cs, ss;
2341
2342 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2343 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2344
2345 return ((cs.selector & SELECTOR_RPL_MASK) ==
2346 (ss.selector & SELECTOR_RPL_MASK));
2347}
2348
2349/*
2350 * Check if guest state is valid. Returns true if valid, false if
2351 * not.
2352 * We assume that registers are always usable
2353 */
2354static bool guest_state_valid(struct kvm_vcpu *vcpu)
2355{
2356 /* real mode guest state checks */
2357 if (!is_protmode(vcpu)) {
2358 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2359 return false;
2360 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2361 return false;
2362 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2363 return false;
2364 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2365 return false;
2366 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2367 return false;
2368 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2369 return false;
2370 } else {
2371 /* protected mode guest state checks */
2372 if (!cs_ss_rpl_check(vcpu))
2373 return false;
2374 if (!code_segment_valid(vcpu))
2375 return false;
2376 if (!stack_segment_valid(vcpu))
2377 return false;
2378 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2379 return false;
2380 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2381 return false;
2382 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2383 return false;
2384 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2385 return false;
2386 if (!tr_valid(vcpu))
2387 return false;
2388 if (!ldtr_valid(vcpu))
2389 return false;
2390 }
2391 /* TODO:
2392 * - Add checks on RIP
2393 * - Add checks on RFLAGS
2394 */
2395
2396 return true;
2397}
2398
2399static int init_rmode_tss(struct kvm *kvm)
2400{
2401 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2402 u16 data = 0;
2403 int ret = 0;
2404 int r;
2405
2406 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2407 if (r < 0)
2408 goto out;
2409 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2410 r = kvm_write_guest_page(kvm, fn++, &data,
2411 TSS_IOPB_BASE_OFFSET, sizeof(u16));
2412 if (r < 0)
2413 goto out;
2414 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2415 if (r < 0)
2416 goto out;
2417 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2418 if (r < 0)
2419 goto out;
2420 data = ~0;
2421 r = kvm_write_guest_page(kvm, fn, &data,
2422 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2423 sizeof(u8));
2424 if (r < 0)
2425 goto out;
2426
2427 ret = 1;
2428out:
2429 return ret;
2430}
2431
2432static int init_rmode_identity_map(struct kvm *kvm)
2433{
2434 int i, r, ret;
2435 pfn_t identity_map_pfn;
2436 u32 tmp;
2437
2438 if (!enable_ept)
2439 return 1;
2440 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2441 printk(KERN_ERR "EPT: identity-mapping pagetable "
2442 "haven't been allocated!\n");
2443 return 0;
2444 }
2445 if (likely(kvm->arch.ept_identity_pagetable_done))
2446 return 1;
2447 ret = 0;
2448 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2449 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2450 if (r < 0)
2451 goto out;
2452 /* Set up identity-mapping pagetable for EPT in real mode */
2453 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2454 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2455 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2456 r = kvm_write_guest_page(kvm, identity_map_pfn,
2457 &tmp, i * sizeof(tmp), sizeof(tmp));
2458 if (r < 0)
2459 goto out;
2460 }
2461 kvm->arch.ept_identity_pagetable_done = true;
2462 ret = 1;
2463out:
2464 return ret;
2465}
2466
2467static void seg_setup(int seg)
2468{
2469 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2470 unsigned int ar;
2471
2472 vmcs_write16(sf->selector, 0);
2473 vmcs_writel(sf->base, 0);
2474 vmcs_write32(sf->limit, 0xffff);
2475 if (enable_unrestricted_guest) {
2476 ar = 0x93;
2477 if (seg == VCPU_SREG_CS)
2478 ar |= 0x08; /* code segment */
2479 } else
2480 ar = 0xf3;
2481
2482 vmcs_write32(sf->ar_bytes, ar);
2483}
2484
2485static int alloc_apic_access_page(struct kvm *kvm)
2486{
2487 struct kvm_userspace_memory_region kvm_userspace_mem;
2488 int r = 0;
2489
2490 mutex_lock(&kvm->slots_lock);
2491 if (kvm->arch.apic_access_page)
2492 goto out;
2493 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2494 kvm_userspace_mem.flags = 0;
2495 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2496 kvm_userspace_mem.memory_size = PAGE_SIZE;
2497 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2498 if (r)
2499 goto out;
2500
2501 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2502out:
2503 mutex_unlock(&kvm->slots_lock);
2504 return r;
2505}
2506
2507static int alloc_identity_pagetable(struct kvm *kvm)
2508{
2509 struct kvm_userspace_memory_region kvm_userspace_mem;
2510 int r = 0;
2511
2512 mutex_lock(&kvm->slots_lock);
2513 if (kvm->arch.ept_identity_pagetable)
2514 goto out;
2515 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2516 kvm_userspace_mem.flags = 0;
2517 kvm_userspace_mem.guest_phys_addr =
2518 kvm->arch.ept_identity_map_addr;
2519 kvm_userspace_mem.memory_size = PAGE_SIZE;
2520 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2521 if (r)
2522 goto out;
2523
2524 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2525 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2526out:
2527 mutex_unlock(&kvm->slots_lock);
2528 return r;
2529}
2530
2531static void allocate_vpid(struct vcpu_vmx *vmx)
2532{
2533 int vpid;
2534
2535 vmx->vpid = 0;
2536 if (!enable_vpid)
2537 return;
2538 spin_lock(&vmx_vpid_lock);
2539 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2540 if (vpid < VMX_NR_VPIDS) {
2541 vmx->vpid = vpid;
2542 __set_bit(vpid, vmx_vpid_bitmap);
2543 }
2544 spin_unlock(&vmx_vpid_lock);
2545}
2546
2547static void free_vpid(struct vcpu_vmx *vmx)
2548{
2549 if (!enable_vpid)
2550 return;
2551 spin_lock(&vmx_vpid_lock);
2552 if (vmx->vpid != 0)
2553 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2554 spin_unlock(&vmx_vpid_lock);
2555}
2556
2557static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2558{
2559 int f = sizeof(unsigned long);
2560
2561 if (!cpu_has_vmx_msr_bitmap())
2562 return;
2563
2564 /*
2565 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2566 * have the write-low and read-high bitmap offsets the wrong way round.
2567 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2568 */
2569 if (msr <= 0x1fff) {
2570 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2571 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2572 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2573 msr &= 0x1fff;
2574 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2575 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2576 }
2577}
2578
2579static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2580{
2581 if (!longmode_only)
2582 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2583 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2584}
2585
2586/*
2587 * Sets up the vmcs for emulated real mode.
2588 */
2589static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2590{
2591 u32 host_sysenter_cs, msr_low, msr_high;
2592 u32 junk;
2593 u64 host_pat;
2594 unsigned long a;
2595 struct desc_ptr dt;
2596 int i;
2597 unsigned long kvm_vmx_return;
2598 u32 exec_control;
2599
2600 /* I/O */
2601 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2602 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2603
2604 if (cpu_has_vmx_msr_bitmap())
2605 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2606
2607 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2608
2609 /* Control */
2610 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2611 vmcs_config.pin_based_exec_ctrl);
2612
2613 exec_control = vmcs_config.cpu_based_exec_ctrl;
2614 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2615 exec_control &= ~CPU_BASED_TPR_SHADOW;
2616#ifdef CONFIG_X86_64
2617 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2618 CPU_BASED_CR8_LOAD_EXITING;
2619#endif
2620 }
2621 if (!enable_ept)
2622 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2623 CPU_BASED_CR3_LOAD_EXITING |
2624 CPU_BASED_INVLPG_EXITING;
2625 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2626
2627 if (cpu_has_secondary_exec_ctrls()) {
2628 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2629 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2630 exec_control &=
2631 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2632 if (vmx->vpid == 0)
2633 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2634 if (!enable_ept) {
2635 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2636 enable_unrestricted_guest = 0;
2637 }
2638 if (!enable_unrestricted_guest)
2639 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2640 if (!ple_gap)
2641 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2642 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2643 }
2644
2645 if (ple_gap) {
2646 vmcs_write32(PLE_GAP, ple_gap);
2647 vmcs_write32(PLE_WINDOW, ple_window);
2648 }
2649
2650 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2651 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2652 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2653
2654 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
2655 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2656 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2657
2658 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2659 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2660 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2661 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
2662 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
2663 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2664#ifdef CONFIG_X86_64
2665 rdmsrl(MSR_FS_BASE, a);
2666 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2667 rdmsrl(MSR_GS_BASE, a);
2668 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2669#else
2670 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2671 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2672#endif
2673
2674 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2675
2676 native_store_idt(&dt);
2677 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
2678
2679 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2680 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2681 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2682 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2683 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2684 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2685 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2686
2687 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2688 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2689 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2690 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2691 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2692 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2693
2694 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2695 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2696 host_pat = msr_low | ((u64) msr_high << 32);
2697 vmcs_write64(HOST_IA32_PAT, host_pat);
2698 }
2699 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2700 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2701 host_pat = msr_low | ((u64) msr_high << 32);
2702 /* Write the default value follow host pat */
2703 vmcs_write64(GUEST_IA32_PAT, host_pat);
2704 /* Keep arch.pat sync with GUEST_IA32_PAT */
2705 vmx->vcpu.arch.pat = host_pat;
2706 }
2707
2708 for (i = 0; i < NR_VMX_MSR; ++i) {
2709 u32 index = vmx_msr_index[i];
2710 u32 data_low, data_high;
2711 int j = vmx->nmsrs;
2712
2713 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2714 continue;
2715 if (wrmsr_safe(index, data_low, data_high) < 0)
2716 continue;
2717 vmx->guest_msrs[j].index = i;
2718 vmx->guest_msrs[j].data = 0;
2719 vmx->guest_msrs[j].mask = -1ull;
2720 ++vmx->nmsrs;
2721 }
2722
2723 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2724
2725 /* 22.2.1, 20.8.1 */
2726 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2727
2728 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2729 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2730 if (enable_ept)
2731 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2732 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2733
2734 kvm_write_tsc(&vmx->vcpu, 0);
2735
2736 return 0;
2737}
2738
2739static int init_rmode(struct kvm *kvm)
2740{
2741 int idx, ret = 0;
2742
2743 idx = srcu_read_lock(&kvm->srcu);
2744 if (!init_rmode_tss(kvm))
2745 goto exit;
2746 if (!init_rmode_identity_map(kvm))
2747 goto exit;
2748
2749 ret = 1;
2750exit:
2751 srcu_read_unlock(&kvm->srcu, idx);
2752 return ret;
2753}
2754
2755static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2756{
2757 struct vcpu_vmx *vmx = to_vmx(vcpu);
2758 u64 msr;
2759 int ret;
2760
2761 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2762 if (!init_rmode(vmx->vcpu.kvm)) {
2763 ret = -ENOMEM;
2764 goto out;
2765 }
2766
2767 vmx->rmode.vm86_active = 0;
2768
2769 vmx->soft_vnmi_blocked = 0;
2770
2771 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2772 kvm_set_cr8(&vmx->vcpu, 0);
2773 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2774 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2775 msr |= MSR_IA32_APICBASE_BSP;
2776 kvm_set_apic_base(&vmx->vcpu, msr);
2777
2778 ret = fx_init(&vmx->vcpu);
2779 if (ret != 0)
2780 goto out;
2781
2782 seg_setup(VCPU_SREG_CS);
2783 /*
2784 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2785 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2786 */
2787 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2788 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2789 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2790 } else {
2791 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2792 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2793 }
2794
2795 seg_setup(VCPU_SREG_DS);
2796 seg_setup(VCPU_SREG_ES);
2797 seg_setup(VCPU_SREG_FS);
2798 seg_setup(VCPU_SREG_GS);
2799 seg_setup(VCPU_SREG_SS);
2800
2801 vmcs_write16(GUEST_TR_SELECTOR, 0);
2802 vmcs_writel(GUEST_TR_BASE, 0);
2803 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2804 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2805
2806 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2807 vmcs_writel(GUEST_LDTR_BASE, 0);
2808 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2809 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2810
2811 vmcs_write32(GUEST_SYSENTER_CS, 0);
2812 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2813 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2814
2815 vmcs_writel(GUEST_RFLAGS, 0x02);
2816 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2817 kvm_rip_write(vcpu, 0xfff0);
2818 else
2819 kvm_rip_write(vcpu, 0);
2820 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2821
2822 vmcs_writel(GUEST_DR7, 0x400);
2823
2824 vmcs_writel(GUEST_GDTR_BASE, 0);
2825 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2826
2827 vmcs_writel(GUEST_IDTR_BASE, 0);
2828 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2829
2830 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
2831 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2832 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2833
2834 /* Special registers */
2835 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2836
2837 setup_msrs(vmx);
2838
2839 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2840
2841 if (cpu_has_vmx_tpr_shadow()) {
2842 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2843 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2844 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2845 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2846 vmcs_write32(TPR_THRESHOLD, 0);
2847 }
2848
2849 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2850 vmcs_write64(APIC_ACCESS_ADDR,
2851 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2852
2853 if (vmx->vpid != 0)
2854 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2855
2856 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2857 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2858 vmx_set_cr4(&vmx->vcpu, 0);
2859 vmx_set_efer(&vmx->vcpu, 0);
2860 vmx_fpu_activate(&vmx->vcpu);
2861 update_exception_bitmap(&vmx->vcpu);
2862
2863 vpid_sync_context(vmx);
2864
2865 ret = 0;
2866
2867 /* HACK: Don't enable emulation on guest boot/reset */
2868 vmx->emulation_required = 0;
2869
2870out:
2871 return ret;
2872}
2873
2874static void enable_irq_window(struct kvm_vcpu *vcpu)
2875{
2876 u32 cpu_based_vm_exec_control;
2877
2878 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2879 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2880 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2881}
2882
2883static void enable_nmi_window(struct kvm_vcpu *vcpu)
2884{
2885 u32 cpu_based_vm_exec_control;
2886
2887 if (!cpu_has_virtual_nmis()) {
2888 enable_irq_window(vcpu);
2889 return;
2890 }
2891
2892 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
2893 enable_irq_window(vcpu);
2894 return;
2895 }
2896 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2897 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2898 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2899}
2900
2901static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2902{
2903 struct vcpu_vmx *vmx = to_vmx(vcpu);
2904 uint32_t intr;
2905 int irq = vcpu->arch.interrupt.nr;
2906
2907 trace_kvm_inj_virq(irq);
2908
2909 ++vcpu->stat.irq_injections;
2910 if (vmx->rmode.vm86_active) {
2911 if (kvm_inject_realmode_interrupt(vcpu, irq) != EMULATE_DONE)
2912 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2913 return;
2914 }
2915 intr = irq | INTR_INFO_VALID_MASK;
2916 if (vcpu->arch.interrupt.soft) {
2917 intr |= INTR_TYPE_SOFT_INTR;
2918 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2919 vmx->vcpu.arch.event_exit_inst_len);
2920 } else
2921 intr |= INTR_TYPE_EXT_INTR;
2922 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2923 vmx_clear_hlt(vcpu);
2924}
2925
2926static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2927{
2928 struct vcpu_vmx *vmx = to_vmx(vcpu);
2929
2930 if (!cpu_has_virtual_nmis()) {
2931 /*
2932 * Tracking the NMI-blocked state in software is built upon
2933 * finding the next open IRQ window. This, in turn, depends on
2934 * well-behaving guests: They have to keep IRQs disabled at
2935 * least as long as the NMI handler runs. Otherwise we may
2936 * cause NMI nesting, maybe breaking the guest. But as this is
2937 * highly unlikely, we can live with the residual risk.
2938 */
2939 vmx->soft_vnmi_blocked = 1;
2940 vmx->vnmi_blocked_time = 0;
2941 }
2942
2943 ++vcpu->stat.nmi_injections;
2944 if (vmx->rmode.vm86_active) {
2945 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR) != EMULATE_DONE)
2946 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2947 return;
2948 }
2949 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2950 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2951 vmx_clear_hlt(vcpu);
2952}
2953
2954static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2955{
2956 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2957 return 0;
2958
2959 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2960 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
2961 | GUEST_INTR_STATE_NMI));
2962}
2963
2964static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2965{
2966 if (!cpu_has_virtual_nmis())
2967 return to_vmx(vcpu)->soft_vnmi_blocked;
2968 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
2969}
2970
2971static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2972{
2973 struct vcpu_vmx *vmx = to_vmx(vcpu);
2974
2975 if (!cpu_has_virtual_nmis()) {
2976 if (vmx->soft_vnmi_blocked != masked) {
2977 vmx->soft_vnmi_blocked = masked;
2978 vmx->vnmi_blocked_time = 0;
2979 }
2980 } else {
2981 if (masked)
2982 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2983 GUEST_INTR_STATE_NMI);
2984 else
2985 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2986 GUEST_INTR_STATE_NMI);
2987 }
2988}
2989
2990static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2991{
2992 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2993 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2994 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2995}
2996
2997static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2998{
2999 int ret;
3000 struct kvm_userspace_memory_region tss_mem = {
3001 .slot = TSS_PRIVATE_MEMSLOT,
3002 .guest_phys_addr = addr,
3003 .memory_size = PAGE_SIZE * 3,
3004 .flags = 0,
3005 };
3006
3007 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3008 if (ret)
3009 return ret;
3010 kvm->arch.tss_addr = addr;
3011 return 0;
3012}
3013
3014static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3015 int vec, u32 err_code)
3016{
3017 /*
3018 * Instruction with address size override prefix opcode 0x67
3019 * Cause the #SS fault with 0 error code in VM86 mode.
3020 */
3021 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3022 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
3023 return 1;
3024 /*
3025 * Forward all other exceptions that are valid in real mode.
3026 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3027 * the required debugging infrastructure rework.
3028 */
3029 switch (vec) {
3030 case DB_VECTOR:
3031 if (vcpu->guest_debug &
3032 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3033 return 0;
3034 kvm_queue_exception(vcpu, vec);
3035 return 1;
3036 case BP_VECTOR:
3037 /*
3038 * Update instruction length as we may reinject the exception
3039 * from user space while in guest debugging mode.
3040 */
3041 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3042 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3043 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3044 return 0;
3045 /* fall through */
3046 case DE_VECTOR:
3047 case OF_VECTOR:
3048 case BR_VECTOR:
3049 case UD_VECTOR:
3050 case DF_VECTOR:
3051 case SS_VECTOR:
3052 case GP_VECTOR:
3053 case MF_VECTOR:
3054 kvm_queue_exception(vcpu, vec);
3055 return 1;
3056 }
3057 return 0;
3058}
3059
3060/*
3061 * Trigger machine check on the host. We assume all the MSRs are already set up
3062 * by the CPU and that we still run on the same CPU as the MCE occurred on.
3063 * We pass a fake environment to the machine check handler because we want
3064 * the guest to be always treated like user space, no matter what context
3065 * it used internally.
3066 */
3067static void kvm_machine_check(void)
3068{
3069#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3070 struct pt_regs regs = {
3071 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3072 .flags = X86_EFLAGS_IF,
3073 };
3074
3075 do_machine_check(&regs, 0);
3076#endif
3077}
3078
3079static int handle_machine_check(struct kvm_vcpu *vcpu)
3080{
3081 /* already handled by vcpu_run */
3082 return 1;
3083}
3084
3085static int handle_exception(struct kvm_vcpu *vcpu)
3086{
3087 struct vcpu_vmx *vmx = to_vmx(vcpu);
3088 struct kvm_run *kvm_run = vcpu->run;
3089 u32 intr_info, ex_no, error_code;
3090 unsigned long cr2, rip, dr6;
3091 u32 vect_info;
3092 enum emulation_result er;
3093
3094 vect_info = vmx->idt_vectoring_info;
3095 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3096
3097 if (is_machine_check(intr_info))
3098 return handle_machine_check(vcpu);
3099
3100 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3101 !is_page_fault(intr_info)) {
3102 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3103 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3104 vcpu->run->internal.ndata = 2;
3105 vcpu->run->internal.data[0] = vect_info;
3106 vcpu->run->internal.data[1] = intr_info;
3107 return 0;
3108 }
3109
3110 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3111 return 1; /* already handled by vmx_vcpu_run() */
3112
3113 if (is_no_device(intr_info)) {
3114 vmx_fpu_activate(vcpu);
3115 return 1;
3116 }
3117
3118 if (is_invalid_opcode(intr_info)) {
3119 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
3120 if (er != EMULATE_DONE)
3121 kvm_queue_exception(vcpu, UD_VECTOR);
3122 return 1;
3123 }
3124
3125 error_code = 0;
3126 rip = kvm_rip_read(vcpu);
3127 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3128 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3129 if (is_page_fault(intr_info)) {
3130 /* EPT won't cause page fault directly */
3131 if (enable_ept)
3132 BUG();
3133 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3134 trace_kvm_page_fault(cr2, error_code);
3135
3136 if (kvm_event_needs_reinjection(vcpu))
3137 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3138 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
3139 }
3140
3141 if (vmx->rmode.vm86_active &&
3142 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3143 error_code)) {
3144 if (vcpu->arch.halt_request) {
3145 vcpu->arch.halt_request = 0;
3146 return kvm_emulate_halt(vcpu);
3147 }
3148 return 1;
3149 }
3150
3151 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3152 switch (ex_no) {
3153 case DB_VECTOR:
3154 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3155 if (!(vcpu->guest_debug &
3156 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3157 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3158 kvm_queue_exception(vcpu, DB_VECTOR);
3159 return 1;
3160 }
3161 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3162 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3163 /* fall through */
3164 case BP_VECTOR:
3165 /*
3166 * Update instruction length as we may reinject #BP from
3167 * user space while in guest debugging mode. Reading it for
3168 * #DB as well causes no harm, it is not used in that case.
3169 */
3170 vmx->vcpu.arch.event_exit_inst_len =
3171 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3172 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3173 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3174 kvm_run->debug.arch.exception = ex_no;
3175 break;
3176 default:
3177 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3178 kvm_run->ex.exception = ex_no;
3179 kvm_run->ex.error_code = error_code;
3180 break;
3181 }
3182 return 0;
3183}
3184
3185static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3186{
3187 ++vcpu->stat.irq_exits;
3188 return 1;
3189}
3190
3191static int handle_triple_fault(struct kvm_vcpu *vcpu)
3192{
3193 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3194 return 0;
3195}
3196
3197static int handle_io(struct kvm_vcpu *vcpu)
3198{
3199 unsigned long exit_qualification;
3200 int size, in, string;
3201 unsigned port;
3202
3203 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3204 string = (exit_qualification & 16) != 0;
3205 in = (exit_qualification & 8) != 0;
3206
3207 ++vcpu->stat.io_exits;
3208
3209 if (string || in)
3210 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3211
3212 port = exit_qualification >> 16;
3213 size = (exit_qualification & 7) + 1;
3214 skip_emulated_instruction(vcpu);
3215
3216 return kvm_fast_pio_out(vcpu, size, port);
3217}
3218
3219static void
3220vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3221{
3222 /*
3223 * Patch in the VMCALL instruction:
3224 */
3225 hypercall[0] = 0x0f;
3226 hypercall[1] = 0x01;
3227 hypercall[2] = 0xc1;
3228}
3229
3230static int handle_cr(struct kvm_vcpu *vcpu)
3231{
3232 unsigned long exit_qualification, val;
3233 int cr;
3234 int reg;
3235 int err;
3236
3237 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3238 cr = exit_qualification & 15;
3239 reg = (exit_qualification >> 8) & 15;
3240 switch ((exit_qualification >> 4) & 3) {
3241 case 0: /* mov to cr */
3242 val = kvm_register_read(vcpu, reg);
3243 trace_kvm_cr_write(cr, val);
3244 switch (cr) {
3245 case 0:
3246 err = kvm_set_cr0(vcpu, val);
3247 kvm_complete_insn_gp(vcpu, err);
3248 return 1;
3249 case 3:
3250 err = kvm_set_cr3(vcpu, val);
3251 kvm_complete_insn_gp(vcpu, err);
3252 return 1;
3253 case 4:
3254 err = kvm_set_cr4(vcpu, val);
3255 kvm_complete_insn_gp(vcpu, err);
3256 return 1;
3257 case 8: {
3258 u8 cr8_prev = kvm_get_cr8(vcpu);
3259 u8 cr8 = kvm_register_read(vcpu, reg);
3260 err = kvm_set_cr8(vcpu, cr8);
3261 kvm_complete_insn_gp(vcpu, err);
3262 if (irqchip_in_kernel(vcpu->kvm))
3263 return 1;
3264 if (cr8_prev <= cr8)
3265 return 1;
3266 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3267 return 0;
3268 }
3269 };
3270 break;
3271 case 2: /* clts */
3272 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3273 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3274 skip_emulated_instruction(vcpu);
3275 vmx_fpu_activate(vcpu);
3276 return 1;
3277 case 1: /*mov from cr*/
3278 switch (cr) {
3279 case 3:
3280 val = kvm_read_cr3(vcpu);
3281 kvm_register_write(vcpu, reg, val);
3282 trace_kvm_cr_read(cr, val);
3283 skip_emulated_instruction(vcpu);
3284 return 1;
3285 case 8:
3286 val = kvm_get_cr8(vcpu);
3287 kvm_register_write(vcpu, reg, val);
3288 trace_kvm_cr_read(cr, val);
3289 skip_emulated_instruction(vcpu);
3290 return 1;
3291 }
3292 break;
3293 case 3: /* lmsw */
3294 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3295 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3296 kvm_lmsw(vcpu, val);
3297
3298 skip_emulated_instruction(vcpu);
3299 return 1;
3300 default:
3301 break;
3302 }
3303 vcpu->run->exit_reason = 0;
3304 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3305 (int)(exit_qualification >> 4) & 3, cr);
3306 return 0;
3307}
3308
3309static int handle_dr(struct kvm_vcpu *vcpu)
3310{
3311 unsigned long exit_qualification;
3312 int dr, reg;
3313
3314 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3315 if (!kvm_require_cpl(vcpu, 0))
3316 return 1;
3317 dr = vmcs_readl(GUEST_DR7);
3318 if (dr & DR7_GD) {
3319 /*
3320 * As the vm-exit takes precedence over the debug trap, we
3321 * need to emulate the latter, either for the host or the
3322 * guest debugging itself.
3323 */
3324 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3325 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3326 vcpu->run->debug.arch.dr7 = dr;
3327 vcpu->run->debug.arch.pc =
3328 vmcs_readl(GUEST_CS_BASE) +
3329 vmcs_readl(GUEST_RIP);
3330 vcpu->run->debug.arch.exception = DB_VECTOR;
3331 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3332 return 0;
3333 } else {
3334 vcpu->arch.dr7 &= ~DR7_GD;
3335 vcpu->arch.dr6 |= DR6_BD;
3336 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3337 kvm_queue_exception(vcpu, DB_VECTOR);
3338 return 1;
3339 }
3340 }
3341
3342 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3343 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3344 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3345 if (exit_qualification & TYPE_MOV_FROM_DR) {
3346 unsigned long val;
3347 if (!kvm_get_dr(vcpu, dr, &val))
3348 kvm_register_write(vcpu, reg, val);
3349 } else
3350 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3351 skip_emulated_instruction(vcpu);
3352 return 1;
3353}
3354
3355static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3356{
3357 vmcs_writel(GUEST_DR7, val);
3358}
3359
3360static int handle_cpuid(struct kvm_vcpu *vcpu)
3361{
3362 kvm_emulate_cpuid(vcpu);
3363 return 1;
3364}
3365
3366static int handle_rdmsr(struct kvm_vcpu *vcpu)
3367{
3368 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3369 u64 data;
3370
3371 if (vmx_get_msr(vcpu, ecx, &data)) {
3372 trace_kvm_msr_read_ex(ecx);
3373 kvm_inject_gp(vcpu, 0);
3374 return 1;
3375 }
3376
3377 trace_kvm_msr_read(ecx, data);
3378
3379 /* FIXME: handling of bits 32:63 of rax, rdx */
3380 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3381 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3382 skip_emulated_instruction(vcpu);
3383 return 1;
3384}
3385
3386static int handle_wrmsr(struct kvm_vcpu *vcpu)
3387{
3388 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3389 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3390 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3391
3392 if (vmx_set_msr(vcpu, ecx, data) != 0) {
3393 trace_kvm_msr_write_ex(ecx, data);
3394 kvm_inject_gp(vcpu, 0);
3395 return 1;
3396 }
3397
3398 trace_kvm_msr_write(ecx, data);
3399 skip_emulated_instruction(vcpu);
3400 return 1;
3401}
3402
3403static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3404{
3405 kvm_make_request(KVM_REQ_EVENT, vcpu);
3406 return 1;
3407}
3408
3409static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3410{
3411 u32 cpu_based_vm_exec_control;
3412
3413 /* clear pending irq */
3414 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3415 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3416 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3417
3418 kvm_make_request(KVM_REQ_EVENT, vcpu);
3419
3420 ++vcpu->stat.irq_window_exits;
3421
3422 /*
3423 * If the user space waits to inject interrupts, exit as soon as
3424 * possible
3425 */
3426 if (!irqchip_in_kernel(vcpu->kvm) &&
3427 vcpu->run->request_interrupt_window &&
3428 !kvm_cpu_has_interrupt(vcpu)) {
3429 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3430 return 0;
3431 }
3432 return 1;
3433}
3434
3435static int handle_halt(struct kvm_vcpu *vcpu)
3436{
3437 skip_emulated_instruction(vcpu);
3438 return kvm_emulate_halt(vcpu);
3439}
3440
3441static int handle_vmcall(struct kvm_vcpu *vcpu)
3442{
3443 skip_emulated_instruction(vcpu);
3444 kvm_emulate_hypercall(vcpu);
3445 return 1;
3446}
3447
3448static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3449{
3450 kvm_queue_exception(vcpu, UD_VECTOR);
3451 return 1;
3452}
3453
3454static int handle_invd(struct kvm_vcpu *vcpu)
3455{
3456 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3457}
3458
3459static int handle_invlpg(struct kvm_vcpu *vcpu)
3460{
3461 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3462
3463 kvm_mmu_invlpg(vcpu, exit_qualification);
3464 skip_emulated_instruction(vcpu);
3465 return 1;
3466}
3467
3468static int handle_wbinvd(struct kvm_vcpu *vcpu)
3469{
3470 skip_emulated_instruction(vcpu);
3471 kvm_emulate_wbinvd(vcpu);
3472 return 1;
3473}
3474
3475static int handle_xsetbv(struct kvm_vcpu *vcpu)
3476{
3477 u64 new_bv = kvm_read_edx_eax(vcpu);
3478 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3479
3480 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3481 skip_emulated_instruction(vcpu);
3482 return 1;
3483}
3484
3485static int handle_apic_access(struct kvm_vcpu *vcpu)
3486{
3487 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3488}
3489
3490static int handle_task_switch(struct kvm_vcpu *vcpu)
3491{
3492 struct vcpu_vmx *vmx = to_vmx(vcpu);
3493 unsigned long exit_qualification;
3494 bool has_error_code = false;
3495 u32 error_code = 0;
3496 u16 tss_selector;
3497 int reason, type, idt_v;
3498
3499 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3500 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3501
3502 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3503
3504 reason = (u32)exit_qualification >> 30;
3505 if (reason == TASK_SWITCH_GATE && idt_v) {
3506 switch (type) {
3507 case INTR_TYPE_NMI_INTR:
3508 vcpu->arch.nmi_injected = false;
3509 if (cpu_has_virtual_nmis())
3510 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3511 GUEST_INTR_STATE_NMI);
3512 break;
3513 case INTR_TYPE_EXT_INTR:
3514 case INTR_TYPE_SOFT_INTR:
3515 kvm_clear_interrupt_queue(vcpu);
3516 break;
3517 case INTR_TYPE_HARD_EXCEPTION:
3518 if (vmx->idt_vectoring_info &
3519 VECTORING_INFO_DELIVER_CODE_MASK) {
3520 has_error_code = true;
3521 error_code =
3522 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3523 }
3524 /* fall through */
3525 case INTR_TYPE_SOFT_EXCEPTION:
3526 kvm_clear_exception_queue(vcpu);
3527 break;
3528 default:
3529 break;
3530 }
3531 }
3532 tss_selector = exit_qualification;
3533
3534 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3535 type != INTR_TYPE_EXT_INTR &&
3536 type != INTR_TYPE_NMI_INTR))
3537 skip_emulated_instruction(vcpu);
3538
3539 if (kvm_task_switch(vcpu, tss_selector, reason,
3540 has_error_code, error_code) == EMULATE_FAIL) {
3541 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3542 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3543 vcpu->run->internal.ndata = 0;
3544 return 0;
3545 }
3546
3547 /* clear all local breakpoint enable flags */
3548 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3549
3550 /*
3551 * TODO: What about debug traps on tss switch?
3552 * Are we supposed to inject them and update dr6?
3553 */
3554
3555 return 1;
3556}
3557
3558static int handle_ept_violation(struct kvm_vcpu *vcpu)
3559{
3560 unsigned long exit_qualification;
3561 gpa_t gpa;
3562 int gla_validity;
3563
3564 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3565
3566 if (exit_qualification & (1 << 6)) {
3567 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3568 return -EINVAL;
3569 }
3570
3571 gla_validity = (exit_qualification >> 7) & 0x3;
3572 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3573 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3574 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3575 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3576 vmcs_readl(GUEST_LINEAR_ADDRESS));
3577 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3578 (long unsigned int)exit_qualification);
3579 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3580 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3581 return 0;
3582 }
3583
3584 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3585 trace_kvm_page_fault(gpa, exit_qualification);
3586 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
3587}
3588
3589static u64 ept_rsvd_mask(u64 spte, int level)
3590{
3591 int i;
3592 u64 mask = 0;
3593
3594 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3595 mask |= (1ULL << i);
3596
3597 if (level > 2)
3598 /* bits 7:3 reserved */
3599 mask |= 0xf8;
3600 else if (level == 2) {
3601 if (spte & (1ULL << 7))
3602 /* 2MB ref, bits 20:12 reserved */
3603 mask |= 0x1ff000;
3604 else
3605 /* bits 6:3 reserved */
3606 mask |= 0x78;
3607 }
3608
3609 return mask;
3610}
3611
3612static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3613 int level)
3614{
3615 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3616
3617 /* 010b (write-only) */
3618 WARN_ON((spte & 0x7) == 0x2);
3619
3620 /* 110b (write/execute) */
3621 WARN_ON((spte & 0x7) == 0x6);
3622
3623 /* 100b (execute-only) and value not supported by logical processor */
3624 if (!cpu_has_vmx_ept_execute_only())
3625 WARN_ON((spte & 0x7) == 0x4);
3626
3627 /* not 000b */
3628 if ((spte & 0x7)) {
3629 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3630
3631 if (rsvd_bits != 0) {
3632 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3633 __func__, rsvd_bits);
3634 WARN_ON(1);
3635 }
3636
3637 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3638 u64 ept_mem_type = (spte & 0x38) >> 3;
3639
3640 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3641 ept_mem_type == 7) {
3642 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3643 __func__, ept_mem_type);
3644 WARN_ON(1);
3645 }
3646 }
3647 }
3648}
3649
3650static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3651{
3652 u64 sptes[4];
3653 int nr_sptes, i;
3654 gpa_t gpa;
3655
3656 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3657
3658 printk(KERN_ERR "EPT: Misconfiguration.\n");
3659 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3660
3661 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3662
3663 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3664 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3665
3666 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3667 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3668
3669 return 0;
3670}
3671
3672static int handle_nmi_window(struct kvm_vcpu *vcpu)
3673{
3674 u32 cpu_based_vm_exec_control;
3675
3676 /* clear pending NMI */
3677 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3678 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3679 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3680 ++vcpu->stat.nmi_window_exits;
3681 kvm_make_request(KVM_REQ_EVENT, vcpu);
3682
3683 return 1;
3684}
3685
3686static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3687{
3688 struct vcpu_vmx *vmx = to_vmx(vcpu);
3689 enum emulation_result err = EMULATE_DONE;
3690 int ret = 1;
3691 u32 cpu_exec_ctrl;
3692 bool intr_window_requested;
3693
3694 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3695 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
3696
3697 while (!guest_state_valid(vcpu)) {
3698 if (intr_window_requested
3699 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
3700 return handle_interrupt_window(&vmx->vcpu);
3701
3702 err = emulate_instruction(vcpu, 0);
3703
3704 if (err == EMULATE_DO_MMIO) {
3705 ret = 0;
3706 goto out;
3707 }
3708
3709 if (err != EMULATE_DONE)
3710 return 0;
3711
3712 if (signal_pending(current))
3713 goto out;
3714 if (need_resched())
3715 schedule();
3716 }
3717
3718 vmx->emulation_required = 0;
3719out:
3720 return ret;
3721}
3722
3723/*
3724 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3725 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3726 */
3727static int handle_pause(struct kvm_vcpu *vcpu)
3728{
3729 skip_emulated_instruction(vcpu);
3730 kvm_vcpu_on_spin(vcpu);
3731
3732 return 1;
3733}
3734
3735static int handle_invalid_op(struct kvm_vcpu *vcpu)
3736{
3737 kvm_queue_exception(vcpu, UD_VECTOR);
3738 return 1;
3739}
3740
3741/*
3742 * The exit handlers return 1 if the exit was handled fully and guest execution
3743 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3744 * to be done to userspace and return 0.
3745 */
3746static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3747 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3748 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3749 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3750 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3751 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3752 [EXIT_REASON_CR_ACCESS] = handle_cr,
3753 [EXIT_REASON_DR_ACCESS] = handle_dr,
3754 [EXIT_REASON_CPUID] = handle_cpuid,
3755 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3756 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3757 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3758 [EXIT_REASON_HLT] = handle_halt,
3759 [EXIT_REASON_INVD] = handle_invd,
3760 [EXIT_REASON_INVLPG] = handle_invlpg,
3761 [EXIT_REASON_VMCALL] = handle_vmcall,
3762 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3763 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3764 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3765 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3766 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3767 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3768 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3769 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3770 [EXIT_REASON_VMON] = handle_vmx_insn,
3771 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3772 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3773 [EXIT_REASON_WBINVD] = handle_wbinvd,
3774 [EXIT_REASON_XSETBV] = handle_xsetbv,
3775 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3776 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3777 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3778 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
3779 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
3780 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3781 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
3782};
3783
3784static const int kvm_vmx_max_exit_handlers =
3785 ARRAY_SIZE(kvm_vmx_exit_handlers);
3786
3787static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3788{
3789 *info1 = vmcs_readl(EXIT_QUALIFICATION);
3790 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
3791}
3792
3793/*
3794 * The guest has exited. See if we can fix it or if we need userspace
3795 * assistance.
3796 */
3797static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3798{
3799 struct vcpu_vmx *vmx = to_vmx(vcpu);
3800 u32 exit_reason = vmx->exit_reason;
3801 u32 vectoring_info = vmx->idt_vectoring_info;
3802
3803 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
3804
3805 /* If guest state is invalid, start emulating */
3806 if (vmx->emulation_required && emulate_invalid_guest_state)
3807 return handle_invalid_guest_state(vcpu);
3808
3809 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3810 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3811 vcpu->run->fail_entry.hardware_entry_failure_reason
3812 = exit_reason;
3813 return 0;
3814 }
3815
3816 if (unlikely(vmx->fail)) {
3817 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3818 vcpu->run->fail_entry.hardware_entry_failure_reason
3819 = vmcs_read32(VM_INSTRUCTION_ERROR);
3820 return 0;
3821 }
3822
3823 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3824 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3825 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3826 exit_reason != EXIT_REASON_TASK_SWITCH))
3827 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3828 "(0x%x) and exit reason is 0x%x\n",
3829 __func__, vectoring_info, exit_reason);
3830
3831 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3832 if (vmx_interrupt_allowed(vcpu)) {
3833 vmx->soft_vnmi_blocked = 0;
3834 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3835 vcpu->arch.nmi_pending) {
3836 /*
3837 * This CPU don't support us in finding the end of an
3838 * NMI-blocked window if the guest runs with IRQs
3839 * disabled. So we pull the trigger after 1 s of
3840 * futile waiting, but inform the user about this.
3841 */
3842 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3843 "state on VCPU %d after 1 s timeout\n",
3844 __func__, vcpu->vcpu_id);
3845 vmx->soft_vnmi_blocked = 0;
3846 }
3847 }
3848
3849 if (exit_reason < kvm_vmx_max_exit_handlers
3850 && kvm_vmx_exit_handlers[exit_reason])
3851 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3852 else {
3853 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3854 vcpu->run->hw.hardware_exit_reason = exit_reason;
3855 }
3856 return 0;
3857}
3858
3859static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3860{
3861 if (irr == -1 || tpr < irr) {
3862 vmcs_write32(TPR_THRESHOLD, 0);
3863 return;
3864 }
3865
3866 vmcs_write32(TPR_THRESHOLD, irr);
3867}
3868
3869static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
3870{
3871 u32 exit_intr_info = vmx->exit_intr_info;
3872
3873 /* Handle machine checks before interrupts are enabled */
3874 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3875 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3876 && is_machine_check(exit_intr_info)))
3877 kvm_machine_check();
3878
3879 /* We need to handle NMIs before interrupts are enabled */
3880 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3881 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3882 kvm_before_handle_nmi(&vmx->vcpu);
3883 asm("int $2");
3884 kvm_after_handle_nmi(&vmx->vcpu);
3885 }
3886}
3887
3888static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
3889{
3890 u32 exit_intr_info = vmx->exit_intr_info;
3891 bool unblock_nmi;
3892 u8 vector;
3893 bool idtv_info_valid;
3894
3895 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3896
3897 if (cpu_has_virtual_nmis()) {
3898 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3899 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3900 /*
3901 * SDM 3: 27.7.1.2 (September 2008)
3902 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3903 * a guest IRET fault.
3904 * SDM 3: 23.2.2 (September 2008)
3905 * Bit 12 is undefined in any of the following cases:
3906 * If the VM exit sets the valid bit in the IDT-vectoring
3907 * information field.
3908 * If the VM exit is due to a double fault.
3909 */
3910 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3911 vector != DF_VECTOR && !idtv_info_valid)
3912 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3913 GUEST_INTR_STATE_NMI);
3914 } else if (unlikely(vmx->soft_vnmi_blocked))
3915 vmx->vnmi_blocked_time +=
3916 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3917}
3918
3919static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
3920 u32 idt_vectoring_info,
3921 int instr_len_field,
3922 int error_code_field)
3923{
3924 u8 vector;
3925 int type;
3926 bool idtv_info_valid;
3927
3928 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3929
3930 vmx->vcpu.arch.nmi_injected = false;
3931 kvm_clear_exception_queue(&vmx->vcpu);
3932 kvm_clear_interrupt_queue(&vmx->vcpu);
3933
3934 if (!idtv_info_valid)
3935 return;
3936
3937 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
3938
3939 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3940 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3941
3942 switch (type) {
3943 case INTR_TYPE_NMI_INTR:
3944 vmx->vcpu.arch.nmi_injected = true;
3945 /*
3946 * SDM 3: 27.7.1.2 (September 2008)
3947 * Clear bit "block by NMI" before VM entry if a NMI
3948 * delivery faulted.
3949 */
3950 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3951 GUEST_INTR_STATE_NMI);
3952 break;
3953 case INTR_TYPE_SOFT_EXCEPTION:
3954 vmx->vcpu.arch.event_exit_inst_len =
3955 vmcs_read32(instr_len_field);
3956 /* fall through */
3957 case INTR_TYPE_HARD_EXCEPTION:
3958 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3959 u32 err = vmcs_read32(error_code_field);
3960 kvm_queue_exception_e(&vmx->vcpu, vector, err);
3961 } else
3962 kvm_queue_exception(&vmx->vcpu, vector);
3963 break;
3964 case INTR_TYPE_SOFT_INTR:
3965 vmx->vcpu.arch.event_exit_inst_len =
3966 vmcs_read32(instr_len_field);
3967 /* fall through */
3968 case INTR_TYPE_EXT_INTR:
3969 kvm_queue_interrupt(&vmx->vcpu, vector,
3970 type == INTR_TYPE_SOFT_INTR);
3971 break;
3972 default:
3973 break;
3974 }
3975}
3976
3977static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3978{
3979 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
3980 VM_EXIT_INSTRUCTION_LEN,
3981 IDT_VECTORING_ERROR_CODE);
3982}
3983
3984static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
3985{
3986 __vmx_complete_interrupts(to_vmx(vcpu),
3987 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
3988 VM_ENTRY_INSTRUCTION_LEN,
3989 VM_ENTRY_EXCEPTION_ERROR_CODE);
3990
3991 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
3992}
3993
3994#ifdef CONFIG_X86_64
3995#define R "r"
3996#define Q "q"
3997#else
3998#define R "e"
3999#define Q "l"
4000#endif
4001
4002static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
4003{
4004 struct vcpu_vmx *vmx = to_vmx(vcpu);
4005
4006 /* Record the guest's net vcpu time for enforced NMI injections. */
4007 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
4008 vmx->entry_time = ktime_get();
4009
4010 /* Don't enter VMX if guest state is invalid, let the exit handler
4011 start emulation until we arrive back to a valid state */
4012 if (vmx->emulation_required && emulate_invalid_guest_state)
4013 return;
4014
4015 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
4016 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
4017 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
4018 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
4019
4020 /* When single-stepping over STI and MOV SS, we must clear the
4021 * corresponding interruptibility bits in the guest state. Otherwise
4022 * vmentry fails as it then expects bit 14 (BS) in pending debug
4023 * exceptions being set, but that's not correct for the guest debugging
4024 * case. */
4025 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
4026 vmx_set_interrupt_shadow(vcpu, 0);
4027
4028 asm(
4029 /* Store host registers */
4030 "push %%"R"dx; push %%"R"bp;"
4031 "push %%"R"cx \n\t" /* placeholder for guest rcx */
4032 "push %%"R"cx \n\t"
4033 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
4034 "je 1f \n\t"
4035 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4036 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
4037 "1: \n\t"
4038 /* Reload cr2 if changed */
4039 "mov %c[cr2](%0), %%"R"ax \n\t"
4040 "mov %%cr2, %%"R"dx \n\t"
4041 "cmp %%"R"ax, %%"R"dx \n\t"
4042 "je 2f \n\t"
4043 "mov %%"R"ax, %%cr2 \n\t"
4044 "2: \n\t"
4045 /* Check if vmlaunch of vmresume is needed */
4046 "cmpl $0, %c[launched](%0) \n\t"
4047 /* Load guest registers. Don't clobber flags. */
4048 "mov %c[rax](%0), %%"R"ax \n\t"
4049 "mov %c[rbx](%0), %%"R"bx \n\t"
4050 "mov %c[rdx](%0), %%"R"dx \n\t"
4051 "mov %c[rsi](%0), %%"R"si \n\t"
4052 "mov %c[rdi](%0), %%"R"di \n\t"
4053 "mov %c[rbp](%0), %%"R"bp \n\t"
4054#ifdef CONFIG_X86_64
4055 "mov %c[r8](%0), %%r8 \n\t"
4056 "mov %c[r9](%0), %%r9 \n\t"
4057 "mov %c[r10](%0), %%r10 \n\t"
4058 "mov %c[r11](%0), %%r11 \n\t"
4059 "mov %c[r12](%0), %%r12 \n\t"
4060 "mov %c[r13](%0), %%r13 \n\t"
4061 "mov %c[r14](%0), %%r14 \n\t"
4062 "mov %c[r15](%0), %%r15 \n\t"
4063#endif
4064 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
4065
4066 /* Enter guest mode */
4067 "jne .Llaunched \n\t"
4068 __ex(ASM_VMX_VMLAUNCH) "\n\t"
4069 "jmp .Lkvm_vmx_return \n\t"
4070 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
4071 ".Lkvm_vmx_return: "
4072 /* Save guest registers, load host registers, keep flags */
4073 "mov %0, %c[wordsize](%%"R"sp) \n\t"
4074 "pop %0 \n\t"
4075 "mov %%"R"ax, %c[rax](%0) \n\t"
4076 "mov %%"R"bx, %c[rbx](%0) \n\t"
4077 "pop"Q" %c[rcx](%0) \n\t"
4078 "mov %%"R"dx, %c[rdx](%0) \n\t"
4079 "mov %%"R"si, %c[rsi](%0) \n\t"
4080 "mov %%"R"di, %c[rdi](%0) \n\t"
4081 "mov %%"R"bp, %c[rbp](%0) \n\t"
4082#ifdef CONFIG_X86_64
4083 "mov %%r8, %c[r8](%0) \n\t"
4084 "mov %%r9, %c[r9](%0) \n\t"
4085 "mov %%r10, %c[r10](%0) \n\t"
4086 "mov %%r11, %c[r11](%0) \n\t"
4087 "mov %%r12, %c[r12](%0) \n\t"
4088 "mov %%r13, %c[r13](%0) \n\t"
4089 "mov %%r14, %c[r14](%0) \n\t"
4090 "mov %%r15, %c[r15](%0) \n\t"
4091#endif
4092 "mov %%cr2, %%"R"ax \n\t"
4093 "mov %%"R"ax, %c[cr2](%0) \n\t"
4094
4095 "pop %%"R"bp; pop %%"R"dx \n\t"
4096 "setbe %c[fail](%0) \n\t"
4097 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4098 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4099 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
4100 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
4101 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4102 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4103 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4104 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4105 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4106 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4107 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
4108#ifdef CONFIG_X86_64
4109 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4110 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4111 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4112 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4113 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4114 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4115 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4116 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
4117#endif
4118 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
4119 [wordsize]"i"(sizeof(ulong))
4120 : "cc", "memory"
4121 , R"ax", R"bx", R"di", R"si"
4122#ifdef CONFIG_X86_64
4123 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4124#endif
4125 );
4126
4127 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4128 | (1 << VCPU_EXREG_PDPTR)
4129 | (1 << VCPU_EXREG_CR3));
4130 vcpu->arch.regs_dirty = 0;
4131
4132 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4133
4134 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
4135 vmx->launched = 1;
4136
4137 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
4138 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4139
4140 vmx_complete_atomic_exit(vmx);
4141 vmx_recover_nmi_blocking(vmx);
4142 vmx_complete_interrupts(vmx);
4143}
4144
4145#undef R
4146#undef Q
4147
4148static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4149{
4150 struct vcpu_vmx *vmx = to_vmx(vcpu);
4151
4152 if (vmx->vmcs) {
4153 vcpu_clear(vmx);
4154 free_vmcs(vmx->vmcs);
4155 vmx->vmcs = NULL;
4156 }
4157}
4158
4159static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4160{
4161 struct vcpu_vmx *vmx = to_vmx(vcpu);
4162
4163 free_vpid(vmx);
4164 vmx_free_vmcs(vcpu);
4165 kfree(vmx->guest_msrs);
4166 kvm_vcpu_uninit(vcpu);
4167 kmem_cache_free(kvm_vcpu_cache, vmx);
4168}
4169
4170static inline void vmcs_init(struct vmcs *vmcs)
4171{
4172 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4173
4174 if (!vmm_exclusive)
4175 kvm_cpu_vmxon(phys_addr);
4176
4177 vmcs_clear(vmcs);
4178
4179 if (!vmm_exclusive)
4180 kvm_cpu_vmxoff();
4181}
4182
4183static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4184{
4185 int err;
4186 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4187 int cpu;
4188
4189 if (!vmx)
4190 return ERR_PTR(-ENOMEM);
4191
4192 allocate_vpid(vmx);
4193
4194 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4195 if (err)
4196 goto free_vcpu;
4197
4198 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4199 if (!vmx->guest_msrs) {
4200 err = -ENOMEM;
4201 goto uninit_vcpu;
4202 }
4203
4204 vmx->vmcs = alloc_vmcs();
4205 if (!vmx->vmcs)
4206 goto free_msrs;
4207
4208 vmcs_init(vmx->vmcs);
4209
4210 cpu = get_cpu();
4211 vmx_vcpu_load(&vmx->vcpu, cpu);
4212 vmx->vcpu.cpu = cpu;
4213 err = vmx_vcpu_setup(vmx);
4214 vmx_vcpu_put(&vmx->vcpu);
4215 put_cpu();
4216 if (err)
4217 goto free_vmcs;
4218 if (vm_need_virtualize_apic_accesses(kvm))
4219 if (alloc_apic_access_page(kvm) != 0)
4220 goto free_vmcs;
4221
4222 if (enable_ept) {
4223 if (!kvm->arch.ept_identity_map_addr)
4224 kvm->arch.ept_identity_map_addr =
4225 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4226 if (alloc_identity_pagetable(kvm) != 0)
4227 goto free_vmcs;
4228 }
4229
4230 return &vmx->vcpu;
4231
4232free_vmcs:
4233 free_vmcs(vmx->vmcs);
4234free_msrs:
4235 kfree(vmx->guest_msrs);
4236uninit_vcpu:
4237 kvm_vcpu_uninit(&vmx->vcpu);
4238free_vcpu:
4239 free_vpid(vmx);
4240 kmem_cache_free(kvm_vcpu_cache, vmx);
4241 return ERR_PTR(err);
4242}
4243
4244static void __init vmx_check_processor_compat(void *rtn)
4245{
4246 struct vmcs_config vmcs_conf;
4247
4248 *(int *)rtn = 0;
4249 if (setup_vmcs_config(&vmcs_conf) < 0)
4250 *(int *)rtn = -EIO;
4251 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4252 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4253 smp_processor_id());
4254 *(int *)rtn = -EIO;
4255 }
4256}
4257
4258static int get_ept_level(void)
4259{
4260 return VMX_EPT_DEFAULT_GAW + 1;
4261}
4262
4263static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4264{
4265 u64 ret;
4266
4267 /* For VT-d and EPT combination
4268 * 1. MMIO: always map as UC
4269 * 2. EPT with VT-d:
4270 * a. VT-d without snooping control feature: can't guarantee the
4271 * result, try to trust guest.
4272 * b. VT-d with snooping control feature: snooping control feature of
4273 * VT-d engine can guarantee the cache correctness. Just set it
4274 * to WB to keep consistent with host. So the same as item 3.
4275 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4276 * consistent with host MTRR
4277 */
4278 if (is_mmio)
4279 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4280 else if (vcpu->kvm->arch.iommu_domain &&
4281 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4282 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4283 VMX_EPT_MT_EPTE_SHIFT;
4284 else
4285 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4286 | VMX_EPT_IPAT_BIT;
4287
4288 return ret;
4289}
4290
4291#define _ER(x) { EXIT_REASON_##x, #x }
4292
4293static const struct trace_print_flags vmx_exit_reasons_str[] = {
4294 _ER(EXCEPTION_NMI),
4295 _ER(EXTERNAL_INTERRUPT),
4296 _ER(TRIPLE_FAULT),
4297 _ER(PENDING_INTERRUPT),
4298 _ER(NMI_WINDOW),
4299 _ER(TASK_SWITCH),
4300 _ER(CPUID),
4301 _ER(HLT),
4302 _ER(INVLPG),
4303 _ER(RDPMC),
4304 _ER(RDTSC),
4305 _ER(VMCALL),
4306 _ER(VMCLEAR),
4307 _ER(VMLAUNCH),
4308 _ER(VMPTRLD),
4309 _ER(VMPTRST),
4310 _ER(VMREAD),
4311 _ER(VMRESUME),
4312 _ER(VMWRITE),
4313 _ER(VMOFF),
4314 _ER(VMON),
4315 _ER(CR_ACCESS),
4316 _ER(DR_ACCESS),
4317 _ER(IO_INSTRUCTION),
4318 _ER(MSR_READ),
4319 _ER(MSR_WRITE),
4320 _ER(MWAIT_INSTRUCTION),
4321 _ER(MONITOR_INSTRUCTION),
4322 _ER(PAUSE_INSTRUCTION),
4323 _ER(MCE_DURING_VMENTRY),
4324 _ER(TPR_BELOW_THRESHOLD),
4325 _ER(APIC_ACCESS),
4326 _ER(EPT_VIOLATION),
4327 _ER(EPT_MISCONFIG),
4328 _ER(WBINVD),
4329 { -1, NULL }
4330};
4331
4332#undef _ER
4333
4334static int vmx_get_lpage_level(void)
4335{
4336 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4337 return PT_DIRECTORY_LEVEL;
4338 else
4339 /* For shadow and EPT supported 1GB page */
4340 return PT_PDPE_LEVEL;
4341}
4342
4343static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4344{
4345 struct kvm_cpuid_entry2 *best;
4346 struct vcpu_vmx *vmx = to_vmx(vcpu);
4347 u32 exec_control;
4348
4349 vmx->rdtscp_enabled = false;
4350 if (vmx_rdtscp_supported()) {
4351 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4352 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4353 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4354 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4355 vmx->rdtscp_enabled = true;
4356 else {
4357 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4358 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4359 exec_control);
4360 }
4361 }
4362 }
4363}
4364
4365static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4366{
4367}
4368
4369static struct kvm_x86_ops vmx_x86_ops = {
4370 .cpu_has_kvm_support = cpu_has_kvm_support,
4371 .disabled_by_bios = vmx_disabled_by_bios,
4372 .hardware_setup = hardware_setup,
4373 .hardware_unsetup = hardware_unsetup,
4374 .check_processor_compatibility = vmx_check_processor_compat,
4375 .hardware_enable = hardware_enable,
4376 .hardware_disable = hardware_disable,
4377 .cpu_has_accelerated_tpr = report_flexpriority,
4378
4379 .vcpu_create = vmx_create_vcpu,
4380 .vcpu_free = vmx_free_vcpu,
4381 .vcpu_reset = vmx_vcpu_reset,
4382
4383 .prepare_guest_switch = vmx_save_host_state,
4384 .vcpu_load = vmx_vcpu_load,
4385 .vcpu_put = vmx_vcpu_put,
4386
4387 .set_guest_debug = set_guest_debug,
4388 .get_msr = vmx_get_msr,
4389 .set_msr = vmx_set_msr,
4390 .get_segment_base = vmx_get_segment_base,
4391 .get_segment = vmx_get_segment,
4392 .set_segment = vmx_set_segment,
4393 .get_cpl = vmx_get_cpl,
4394 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4395 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4396 .decache_cr3 = vmx_decache_cr3,
4397 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4398 .set_cr0 = vmx_set_cr0,
4399 .set_cr3 = vmx_set_cr3,
4400 .set_cr4 = vmx_set_cr4,
4401 .set_efer = vmx_set_efer,
4402 .get_idt = vmx_get_idt,
4403 .set_idt = vmx_set_idt,
4404 .get_gdt = vmx_get_gdt,
4405 .set_gdt = vmx_set_gdt,
4406 .set_dr7 = vmx_set_dr7,
4407 .cache_reg = vmx_cache_reg,
4408 .get_rflags = vmx_get_rflags,
4409 .set_rflags = vmx_set_rflags,
4410 .fpu_activate = vmx_fpu_activate,
4411 .fpu_deactivate = vmx_fpu_deactivate,
4412
4413 .tlb_flush = vmx_flush_tlb,
4414
4415 .run = vmx_vcpu_run,
4416 .handle_exit = vmx_handle_exit,
4417 .skip_emulated_instruction = skip_emulated_instruction,
4418 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4419 .get_interrupt_shadow = vmx_get_interrupt_shadow,
4420 .patch_hypercall = vmx_patch_hypercall,
4421 .set_irq = vmx_inject_irq,
4422 .set_nmi = vmx_inject_nmi,
4423 .queue_exception = vmx_queue_exception,
4424 .cancel_injection = vmx_cancel_injection,
4425 .interrupt_allowed = vmx_interrupt_allowed,
4426 .nmi_allowed = vmx_nmi_allowed,
4427 .get_nmi_mask = vmx_get_nmi_mask,
4428 .set_nmi_mask = vmx_set_nmi_mask,
4429 .enable_nmi_window = enable_nmi_window,
4430 .enable_irq_window = enable_irq_window,
4431 .update_cr8_intercept = update_cr8_intercept,
4432
4433 .set_tss_addr = vmx_set_tss_addr,
4434 .get_tdp_level = get_ept_level,
4435 .get_mt_mask = vmx_get_mt_mask,
4436
4437 .get_exit_info = vmx_get_exit_info,
4438 .exit_reasons_str = vmx_exit_reasons_str,
4439
4440 .get_lpage_level = vmx_get_lpage_level,
4441
4442 .cpuid_update = vmx_cpuid_update,
4443
4444 .rdtscp_supported = vmx_rdtscp_supported,
4445
4446 .set_supported_cpuid = vmx_set_supported_cpuid,
4447
4448 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
4449
4450 .write_tsc_offset = vmx_write_tsc_offset,
4451 .adjust_tsc_offset = vmx_adjust_tsc_offset,
4452
4453 .set_tdp_cr3 = vmx_set_cr3,
4454};
4455
4456static int __init vmx_init(void)
4457{
4458 int r, i;
4459
4460 rdmsrl_safe(MSR_EFER, &host_efer);
4461
4462 for (i = 0; i < NR_VMX_MSR; ++i)
4463 kvm_define_shared_msr(i, vmx_msr_index[i]);
4464
4465 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4466 if (!vmx_io_bitmap_a)
4467 return -ENOMEM;
4468
4469 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4470 if (!vmx_io_bitmap_b) {
4471 r = -ENOMEM;
4472 goto out;
4473 }
4474
4475 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4476 if (!vmx_msr_bitmap_legacy) {
4477 r = -ENOMEM;
4478 goto out1;
4479 }
4480
4481 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4482 if (!vmx_msr_bitmap_longmode) {
4483 r = -ENOMEM;
4484 goto out2;
4485 }
4486
4487 /*
4488 * Allow direct access to the PC debug port (it is often used for I/O
4489 * delays, but the vmexits simply slow things down).
4490 */
4491 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4492 clear_bit(0x80, vmx_io_bitmap_a);
4493
4494 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4495
4496 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4497 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4498
4499 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4500
4501 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4502 __alignof__(struct vcpu_vmx), THIS_MODULE);
4503 if (r)
4504 goto out3;
4505
4506 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4507 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4508 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4509 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4510 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4511 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4512
4513 if (enable_ept) {
4514 bypass_guest_pf = 0;
4515 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4516 VMX_EPT_EXECUTABLE_MASK);
4517 kvm_enable_tdp();
4518 } else
4519 kvm_disable_tdp();
4520
4521 if (bypass_guest_pf)
4522 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4523
4524 return 0;
4525
4526out3:
4527 free_page((unsigned long)vmx_msr_bitmap_longmode);
4528out2:
4529 free_page((unsigned long)vmx_msr_bitmap_legacy);
4530out1:
4531 free_page((unsigned long)vmx_io_bitmap_b);
4532out:
4533 free_page((unsigned long)vmx_io_bitmap_a);
4534 return r;
4535}
4536
4537static void __exit vmx_exit(void)
4538{
4539 free_page((unsigned long)vmx_msr_bitmap_legacy);
4540 free_page((unsigned long)vmx_msr_bitmap_longmode);
4541 free_page((unsigned long)vmx_io_bitmap_b);
4542 free_page((unsigned long)vmx_io_bitmap_a);
4543
4544 kvm_exit();
4545}
4546
4547module_init(vmx_init)
4548module_exit(vmx_exit)
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