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1 | /* | |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
8 | * | |
9 | * Authors: | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * Yaniv Kamay <yaniv@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include "irq.h" | |
19 | #include "vmx.h" | |
20 | #include "mmu.h" | |
21 | ||
22 | #include <linux/kvm_host.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/mm.h> | |
26 | #include <linux/highmem.h> | |
27 | #include <linux/sched.h> | |
28 | #include <linux/moduleparam.h> | |
29 | ||
30 | #include <asm/io.h> | |
31 | #include <asm/desc.h> | |
32 | ||
33 | MODULE_AUTHOR("Qumranet"); | |
34 | MODULE_LICENSE("GPL"); | |
35 | ||
36 | static int bypass_guest_pf = 1; | |
37 | module_param(bypass_guest_pf, bool, 0); | |
38 | ||
39 | static int enable_vpid = 1; | |
40 | module_param(enable_vpid, bool, 0); | |
41 | ||
42 | static int flexpriority_enabled = 1; | |
43 | module_param(flexpriority_enabled, bool, 0); | |
44 | ||
45 | struct vmcs { | |
46 | u32 revision_id; | |
47 | u32 abort; | |
48 | char data[0]; | |
49 | }; | |
50 | ||
51 | struct vcpu_vmx { | |
52 | struct kvm_vcpu vcpu; | |
53 | int launched; | |
54 | u8 fail; | |
55 | u32 idt_vectoring_info; | |
56 | struct kvm_msr_entry *guest_msrs; | |
57 | struct kvm_msr_entry *host_msrs; | |
58 | int nmsrs; | |
59 | int save_nmsrs; | |
60 | int msr_offset_efer; | |
61 | #ifdef CONFIG_X86_64 | |
62 | int msr_offset_kernel_gs_base; | |
63 | #endif | |
64 | struct vmcs *vmcs; | |
65 | struct { | |
66 | int loaded; | |
67 | u16 fs_sel, gs_sel, ldt_sel; | |
68 | int gs_ldt_reload_needed; | |
69 | int fs_reload_needed; | |
70 | int guest_efer_loaded; | |
71 | } host_state; | |
72 | struct { | |
73 | struct { | |
74 | bool pending; | |
75 | u8 vector; | |
76 | unsigned rip; | |
77 | } irq; | |
78 | } rmode; | |
79 | int vpid; | |
80 | }; | |
81 | ||
82 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) | |
83 | { | |
84 | return container_of(vcpu, struct vcpu_vmx, vcpu); | |
85 | } | |
86 | ||
87 | static int init_rmode_tss(struct kvm *kvm); | |
88 | ||
89 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); | |
90 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
91 | ||
92 | static struct page *vmx_io_bitmap_a; | |
93 | static struct page *vmx_io_bitmap_b; | |
94 | static struct page *vmx_msr_bitmap; | |
95 | ||
96 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
97 | static DEFINE_SPINLOCK(vmx_vpid_lock); | |
98 | ||
99 | static struct vmcs_config { | |
100 | int size; | |
101 | int order; | |
102 | u32 revision_id; | |
103 | u32 pin_based_exec_ctrl; | |
104 | u32 cpu_based_exec_ctrl; | |
105 | u32 cpu_based_2nd_exec_ctrl; | |
106 | u32 vmexit_ctrl; | |
107 | u32 vmentry_ctrl; | |
108 | } vmcs_config; | |
109 | ||
110 | #define VMX_SEGMENT_FIELD(seg) \ | |
111 | [VCPU_SREG_##seg] = { \ | |
112 | .selector = GUEST_##seg##_SELECTOR, \ | |
113 | .base = GUEST_##seg##_BASE, \ | |
114 | .limit = GUEST_##seg##_LIMIT, \ | |
115 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
116 | } | |
117 | ||
118 | static struct kvm_vmx_segment_field { | |
119 | unsigned selector; | |
120 | unsigned base; | |
121 | unsigned limit; | |
122 | unsigned ar_bytes; | |
123 | } kvm_vmx_segment_fields[] = { | |
124 | VMX_SEGMENT_FIELD(CS), | |
125 | VMX_SEGMENT_FIELD(DS), | |
126 | VMX_SEGMENT_FIELD(ES), | |
127 | VMX_SEGMENT_FIELD(FS), | |
128 | VMX_SEGMENT_FIELD(GS), | |
129 | VMX_SEGMENT_FIELD(SS), | |
130 | VMX_SEGMENT_FIELD(TR), | |
131 | VMX_SEGMENT_FIELD(LDTR), | |
132 | }; | |
133 | ||
134 | /* | |
135 | * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it | |
136 | * away by decrementing the array size. | |
137 | */ | |
138 | static const u32 vmx_msr_index[] = { | |
139 | #ifdef CONFIG_X86_64 | |
140 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE, | |
141 | #endif | |
142 | MSR_EFER, MSR_K6_STAR, | |
143 | }; | |
144 | #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index) | |
145 | ||
146 | static void load_msrs(struct kvm_msr_entry *e, int n) | |
147 | { | |
148 | int i; | |
149 | ||
150 | for (i = 0; i < n; ++i) | |
151 | wrmsrl(e[i].index, e[i].data); | |
152 | } | |
153 | ||
154 | static void save_msrs(struct kvm_msr_entry *e, int n) | |
155 | { | |
156 | int i; | |
157 | ||
158 | for (i = 0; i < n; ++i) | |
159 | rdmsrl(e[i].index, e[i].data); | |
160 | } | |
161 | ||
162 | static inline int is_page_fault(u32 intr_info) | |
163 | { | |
164 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
165 | INTR_INFO_VALID_MASK)) == | |
166 | (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK); | |
167 | } | |
168 | ||
169 | static inline int is_no_device(u32 intr_info) | |
170 | { | |
171 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
172 | INTR_INFO_VALID_MASK)) == | |
173 | (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK); | |
174 | } | |
175 | ||
176 | static inline int is_invalid_opcode(u32 intr_info) | |
177 | { | |
178 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
179 | INTR_INFO_VALID_MASK)) == | |
180 | (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK); | |
181 | } | |
182 | ||
183 | static inline int is_external_interrupt(u32 intr_info) | |
184 | { | |
185 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
186 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
187 | } | |
188 | ||
189 | static inline int cpu_has_vmx_msr_bitmap(void) | |
190 | { | |
191 | return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS); | |
192 | } | |
193 | ||
194 | static inline int cpu_has_vmx_tpr_shadow(void) | |
195 | { | |
196 | return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW); | |
197 | } | |
198 | ||
199 | static inline int vm_need_tpr_shadow(struct kvm *kvm) | |
200 | { | |
201 | return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm))); | |
202 | } | |
203 | ||
204 | static inline int cpu_has_secondary_exec_ctrls(void) | |
205 | { | |
206 | return (vmcs_config.cpu_based_exec_ctrl & | |
207 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS); | |
208 | } | |
209 | ||
210 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) | |
211 | { | |
212 | return flexpriority_enabled | |
213 | && (vmcs_config.cpu_based_2nd_exec_ctrl & | |
214 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
215 | } | |
216 | ||
217 | static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm) | |
218 | { | |
219 | return ((cpu_has_vmx_virtualize_apic_accesses()) && | |
220 | (irqchip_in_kernel(kvm))); | |
221 | } | |
222 | ||
223 | static inline int cpu_has_vmx_vpid(void) | |
224 | { | |
225 | return (vmcs_config.cpu_based_2nd_exec_ctrl & | |
226 | SECONDARY_EXEC_ENABLE_VPID); | |
227 | } | |
228 | ||
229 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) | |
230 | { | |
231 | int i; | |
232 | ||
233 | for (i = 0; i < vmx->nmsrs; ++i) | |
234 | if (vmx->guest_msrs[i].index == msr) | |
235 | return i; | |
236 | return -1; | |
237 | } | |
238 | ||
239 | static inline void __invvpid(int ext, u16 vpid, gva_t gva) | |
240 | { | |
241 | struct { | |
242 | u64 vpid : 16; | |
243 | u64 rsvd : 48; | |
244 | u64 gva; | |
245 | } operand = { vpid, 0, gva }; | |
246 | ||
247 | asm volatile (ASM_VMX_INVVPID | |
248 | /* CF==1 or ZF==1 --> rc = -1 */ | |
249 | "; ja 1f ; ud2 ; 1:" | |
250 | : : "a"(&operand), "c"(ext) : "cc", "memory"); | |
251 | } | |
252 | ||
253 | static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) | |
254 | { | |
255 | int i; | |
256 | ||
257 | i = __find_msr_index(vmx, msr); | |
258 | if (i >= 0) | |
259 | return &vmx->guest_msrs[i]; | |
260 | return NULL; | |
261 | } | |
262 | ||
263 | static void vmcs_clear(struct vmcs *vmcs) | |
264 | { | |
265 | u64 phys_addr = __pa(vmcs); | |
266 | u8 error; | |
267 | ||
268 | asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0" | |
269 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) | |
270 | : "cc", "memory"); | |
271 | if (error) | |
272 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
273 | vmcs, phys_addr); | |
274 | } | |
275 | ||
276 | static void __vcpu_clear(void *arg) | |
277 | { | |
278 | struct vcpu_vmx *vmx = arg; | |
279 | int cpu = raw_smp_processor_id(); | |
280 | ||
281 | if (vmx->vcpu.cpu == cpu) | |
282 | vmcs_clear(vmx->vmcs); | |
283 | if (per_cpu(current_vmcs, cpu) == vmx->vmcs) | |
284 | per_cpu(current_vmcs, cpu) = NULL; | |
285 | rdtscll(vmx->vcpu.arch.host_tsc); | |
286 | } | |
287 | ||
288 | static void vcpu_clear(struct vcpu_vmx *vmx) | |
289 | { | |
290 | if (vmx->vcpu.cpu == -1) | |
291 | return; | |
292 | smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 0, 1); | |
293 | vmx->launched = 0; | |
294 | } | |
295 | ||
296 | static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx) | |
297 | { | |
298 | if (vmx->vpid == 0) | |
299 | return; | |
300 | ||
301 | __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0); | |
302 | } | |
303 | ||
304 | static unsigned long vmcs_readl(unsigned long field) | |
305 | { | |
306 | unsigned long value; | |
307 | ||
308 | asm volatile (ASM_VMX_VMREAD_RDX_RAX | |
309 | : "=a"(value) : "d"(field) : "cc"); | |
310 | return value; | |
311 | } | |
312 | ||
313 | static u16 vmcs_read16(unsigned long field) | |
314 | { | |
315 | return vmcs_readl(field); | |
316 | } | |
317 | ||
318 | static u32 vmcs_read32(unsigned long field) | |
319 | { | |
320 | return vmcs_readl(field); | |
321 | } | |
322 | ||
323 | static u64 vmcs_read64(unsigned long field) | |
324 | { | |
325 | #ifdef CONFIG_X86_64 | |
326 | return vmcs_readl(field); | |
327 | #else | |
328 | return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32); | |
329 | #endif | |
330 | } | |
331 | ||
332 | static noinline void vmwrite_error(unsigned long field, unsigned long value) | |
333 | { | |
334 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
335 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
336 | dump_stack(); | |
337 | } | |
338 | ||
339 | static void vmcs_writel(unsigned long field, unsigned long value) | |
340 | { | |
341 | u8 error; | |
342 | ||
343 | asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0" | |
344 | : "=q"(error) : "a"(value), "d"(field) : "cc"); | |
345 | if (unlikely(error)) | |
346 | vmwrite_error(field, value); | |
347 | } | |
348 | ||
349 | static void vmcs_write16(unsigned long field, u16 value) | |
350 | { | |
351 | vmcs_writel(field, value); | |
352 | } | |
353 | ||
354 | static void vmcs_write32(unsigned long field, u32 value) | |
355 | { | |
356 | vmcs_writel(field, value); | |
357 | } | |
358 | ||
359 | static void vmcs_write64(unsigned long field, u64 value) | |
360 | { | |
361 | #ifdef CONFIG_X86_64 | |
362 | vmcs_writel(field, value); | |
363 | #else | |
364 | vmcs_writel(field, value); | |
365 | asm volatile (""); | |
366 | vmcs_writel(field+1, value >> 32); | |
367 | #endif | |
368 | } | |
369 | ||
370 | static void vmcs_clear_bits(unsigned long field, u32 mask) | |
371 | { | |
372 | vmcs_writel(field, vmcs_readl(field) & ~mask); | |
373 | } | |
374 | ||
375 | static void vmcs_set_bits(unsigned long field, u32 mask) | |
376 | { | |
377 | vmcs_writel(field, vmcs_readl(field) | mask); | |
378 | } | |
379 | ||
380 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) | |
381 | { | |
382 | u32 eb; | |
383 | ||
384 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR); | |
385 | if (!vcpu->fpu_active) | |
386 | eb |= 1u << NM_VECTOR; | |
387 | if (vcpu->guest_debug.enabled) | |
388 | eb |= 1u << 1; | |
389 | if (vcpu->arch.rmode.active) | |
390 | eb = ~0; | |
391 | vmcs_write32(EXCEPTION_BITMAP, eb); | |
392 | } | |
393 | ||
394 | static void reload_tss(void) | |
395 | { | |
396 | /* | |
397 | * VT restores TR but not its size. Useless. | |
398 | */ | |
399 | struct descriptor_table gdt; | |
400 | struct desc_struct *descs; | |
401 | ||
402 | get_gdt(&gdt); | |
403 | descs = (void *)gdt.base; | |
404 | descs[GDT_ENTRY_TSS].type = 9; /* available TSS */ | |
405 | load_TR_desc(); | |
406 | } | |
407 | ||
408 | static void load_transition_efer(struct vcpu_vmx *vmx) | |
409 | { | |
410 | int efer_offset = vmx->msr_offset_efer; | |
411 | u64 host_efer = vmx->host_msrs[efer_offset].data; | |
412 | u64 guest_efer = vmx->guest_msrs[efer_offset].data; | |
413 | u64 ignore_bits; | |
414 | ||
415 | if (efer_offset < 0) | |
416 | return; | |
417 | /* | |
418 | * NX is emulated; LMA and LME handled by hardware; SCE meaninless | |
419 | * outside long mode | |
420 | */ | |
421 | ignore_bits = EFER_NX | EFER_SCE; | |
422 | #ifdef CONFIG_X86_64 | |
423 | ignore_bits |= EFER_LMA | EFER_LME; | |
424 | /* SCE is meaningful only in long mode on Intel */ | |
425 | if (guest_efer & EFER_LMA) | |
426 | ignore_bits &= ~(u64)EFER_SCE; | |
427 | #endif | |
428 | if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits)) | |
429 | return; | |
430 | ||
431 | vmx->host_state.guest_efer_loaded = 1; | |
432 | guest_efer &= ~ignore_bits; | |
433 | guest_efer |= host_efer & ignore_bits; | |
434 | wrmsrl(MSR_EFER, guest_efer); | |
435 | vmx->vcpu.stat.efer_reload++; | |
436 | } | |
437 | ||
438 | static void reload_host_efer(struct vcpu_vmx *vmx) | |
439 | { | |
440 | if (vmx->host_state.guest_efer_loaded) { | |
441 | vmx->host_state.guest_efer_loaded = 0; | |
442 | load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1); | |
443 | } | |
444 | } | |
445 | ||
446 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) | |
447 | { | |
448 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
449 | ||
450 | if (vmx->host_state.loaded) | |
451 | return; | |
452 | ||
453 | vmx->host_state.loaded = 1; | |
454 | /* | |
455 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
456 | * allow segment selectors with cpl > 0 or ti == 1. | |
457 | */ | |
458 | vmx->host_state.ldt_sel = read_ldt(); | |
459 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; | |
460 | vmx->host_state.fs_sel = read_fs(); | |
461 | if (!(vmx->host_state.fs_sel & 7)) { | |
462 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); | |
463 | vmx->host_state.fs_reload_needed = 0; | |
464 | } else { | |
465 | vmcs_write16(HOST_FS_SELECTOR, 0); | |
466 | vmx->host_state.fs_reload_needed = 1; | |
467 | } | |
468 | vmx->host_state.gs_sel = read_gs(); | |
469 | if (!(vmx->host_state.gs_sel & 7)) | |
470 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
471 | else { | |
472 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
473 | vmx->host_state.gs_ldt_reload_needed = 1; | |
474 | } | |
475 | ||
476 | #ifdef CONFIG_X86_64 | |
477 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
478 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
479 | #else | |
480 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); | |
481 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
482 | #endif | |
483 | ||
484 | #ifdef CONFIG_X86_64 | |
485 | if (is_long_mode(&vmx->vcpu)) | |
486 | save_msrs(vmx->host_msrs + | |
487 | vmx->msr_offset_kernel_gs_base, 1); | |
488 | ||
489 | #endif | |
490 | load_msrs(vmx->guest_msrs, vmx->save_nmsrs); | |
491 | load_transition_efer(vmx); | |
492 | } | |
493 | ||
494 | static void vmx_load_host_state(struct vcpu_vmx *vmx) | |
495 | { | |
496 | unsigned long flags; | |
497 | ||
498 | if (!vmx->host_state.loaded) | |
499 | return; | |
500 | ||
501 | ++vmx->vcpu.stat.host_state_reload; | |
502 | vmx->host_state.loaded = 0; | |
503 | if (vmx->host_state.fs_reload_needed) | |
504 | load_fs(vmx->host_state.fs_sel); | |
505 | if (vmx->host_state.gs_ldt_reload_needed) { | |
506 | load_ldt(vmx->host_state.ldt_sel); | |
507 | /* | |
508 | * If we have to reload gs, we must take care to | |
509 | * preserve our gs base. | |
510 | */ | |
511 | local_irq_save(flags); | |
512 | load_gs(vmx->host_state.gs_sel); | |
513 | #ifdef CONFIG_X86_64 | |
514 | wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE)); | |
515 | #endif | |
516 | local_irq_restore(flags); | |
517 | } | |
518 | reload_tss(); | |
519 | save_msrs(vmx->guest_msrs, vmx->save_nmsrs); | |
520 | load_msrs(vmx->host_msrs, vmx->save_nmsrs); | |
521 | reload_host_efer(vmx); | |
522 | } | |
523 | ||
524 | /* | |
525 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
526 | * vcpu mutex is already taken. | |
527 | */ | |
528 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) | |
529 | { | |
530 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
531 | u64 phys_addr = __pa(vmx->vmcs); | |
532 | u64 tsc_this, delta, new_offset; | |
533 | ||
534 | if (vcpu->cpu != cpu) { | |
535 | vcpu_clear(vmx); | |
536 | kvm_migrate_apic_timer(vcpu); | |
537 | vpid_sync_vcpu_all(vmx); | |
538 | } | |
539 | ||
540 | if (per_cpu(current_vmcs, cpu) != vmx->vmcs) { | |
541 | u8 error; | |
542 | ||
543 | per_cpu(current_vmcs, cpu) = vmx->vmcs; | |
544 | asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0" | |
545 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) | |
546 | : "cc"); | |
547 | if (error) | |
548 | printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n", | |
549 | vmx->vmcs, phys_addr); | |
550 | } | |
551 | ||
552 | if (vcpu->cpu != cpu) { | |
553 | struct descriptor_table dt; | |
554 | unsigned long sysenter_esp; | |
555 | ||
556 | vcpu->cpu = cpu; | |
557 | /* | |
558 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
559 | * processors. | |
560 | */ | |
561 | vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */ | |
562 | get_gdt(&dt); | |
563 | vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */ | |
564 | ||
565 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); | |
566 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
567 | ||
568 | /* | |
569 | * Make sure the time stamp counter is monotonous. | |
570 | */ | |
571 | rdtscll(tsc_this); | |
572 | if (tsc_this < vcpu->arch.host_tsc) { | |
573 | delta = vcpu->arch.host_tsc - tsc_this; | |
574 | new_offset = vmcs_read64(TSC_OFFSET) + delta; | |
575 | vmcs_write64(TSC_OFFSET, new_offset); | |
576 | } | |
577 | } | |
578 | } | |
579 | ||
580 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
581 | { | |
582 | vmx_load_host_state(to_vmx(vcpu)); | |
583 | } | |
584 | ||
585 | static void vmx_fpu_activate(struct kvm_vcpu *vcpu) | |
586 | { | |
587 | if (vcpu->fpu_active) | |
588 | return; | |
589 | vcpu->fpu_active = 1; | |
590 | vmcs_clear_bits(GUEST_CR0, X86_CR0_TS); | |
591 | if (vcpu->arch.cr0 & X86_CR0_TS) | |
592 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS); | |
593 | update_exception_bitmap(vcpu); | |
594 | } | |
595 | ||
596 | static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu) | |
597 | { | |
598 | if (!vcpu->fpu_active) | |
599 | return; | |
600 | vcpu->fpu_active = 0; | |
601 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS); | |
602 | update_exception_bitmap(vcpu); | |
603 | } | |
604 | ||
605 | static void vmx_vcpu_decache(struct kvm_vcpu *vcpu) | |
606 | { | |
607 | vcpu_clear(to_vmx(vcpu)); | |
608 | } | |
609 | ||
610 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) | |
611 | { | |
612 | return vmcs_readl(GUEST_RFLAGS); | |
613 | } | |
614 | ||
615 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
616 | { | |
617 | if (vcpu->arch.rmode.active) | |
618 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; | |
619 | vmcs_writel(GUEST_RFLAGS, rflags); | |
620 | } | |
621 | ||
622 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
623 | { | |
624 | unsigned long rip; | |
625 | u32 interruptibility; | |
626 | ||
627 | rip = vmcs_readl(GUEST_RIP); | |
628 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
629 | vmcs_writel(GUEST_RIP, rip); | |
630 | ||
631 | /* | |
632 | * We emulated an instruction, so temporary interrupt blocking | |
633 | * should be removed, if set. | |
634 | */ | |
635 | interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
636 | if (interruptibility & 3) | |
637 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
638 | interruptibility & ~3); | |
639 | vcpu->arch.interrupt_window_open = 1; | |
640 | } | |
641 | ||
642 | static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, | |
643 | bool has_error_code, u32 error_code) | |
644 | { | |
645 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
646 | nr | INTR_TYPE_EXCEPTION | |
647 | | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0) | |
648 | | INTR_INFO_VALID_MASK); | |
649 | if (has_error_code) | |
650 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); | |
651 | } | |
652 | ||
653 | static bool vmx_exception_injected(struct kvm_vcpu *vcpu) | |
654 | { | |
655 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
656 | ||
657 | return !(vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); | |
658 | } | |
659 | ||
660 | /* | |
661 | * Swap MSR entry in host/guest MSR entry array. | |
662 | */ | |
663 | #ifdef CONFIG_X86_64 | |
664 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) | |
665 | { | |
666 | struct kvm_msr_entry tmp; | |
667 | ||
668 | tmp = vmx->guest_msrs[to]; | |
669 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
670 | vmx->guest_msrs[from] = tmp; | |
671 | tmp = vmx->host_msrs[to]; | |
672 | vmx->host_msrs[to] = vmx->host_msrs[from]; | |
673 | vmx->host_msrs[from] = tmp; | |
674 | } | |
675 | #endif | |
676 | ||
677 | /* | |
678 | * Set up the vmcs to automatically save and restore system | |
679 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
680 | * mode, as fiddling with msrs is very expensive. | |
681 | */ | |
682 | static void setup_msrs(struct vcpu_vmx *vmx) | |
683 | { | |
684 | int save_nmsrs; | |
685 | ||
686 | vmx_load_host_state(vmx); | |
687 | save_nmsrs = 0; | |
688 | #ifdef CONFIG_X86_64 | |
689 | if (is_long_mode(&vmx->vcpu)) { | |
690 | int index; | |
691 | ||
692 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); | |
693 | if (index >= 0) | |
694 | move_msr_up(vmx, index, save_nmsrs++); | |
695 | index = __find_msr_index(vmx, MSR_LSTAR); | |
696 | if (index >= 0) | |
697 | move_msr_up(vmx, index, save_nmsrs++); | |
698 | index = __find_msr_index(vmx, MSR_CSTAR); | |
699 | if (index >= 0) | |
700 | move_msr_up(vmx, index, save_nmsrs++); | |
701 | index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE); | |
702 | if (index >= 0) | |
703 | move_msr_up(vmx, index, save_nmsrs++); | |
704 | /* | |
705 | * MSR_K6_STAR is only needed on long mode guests, and only | |
706 | * if efer.sce is enabled. | |
707 | */ | |
708 | index = __find_msr_index(vmx, MSR_K6_STAR); | |
709 | if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE)) | |
710 | move_msr_up(vmx, index, save_nmsrs++); | |
711 | } | |
712 | #endif | |
713 | vmx->save_nmsrs = save_nmsrs; | |
714 | ||
715 | #ifdef CONFIG_X86_64 | |
716 | vmx->msr_offset_kernel_gs_base = | |
717 | __find_msr_index(vmx, MSR_KERNEL_GS_BASE); | |
718 | #endif | |
719 | vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER); | |
720 | } | |
721 | ||
722 | /* | |
723 | * reads and returns guest's timestamp counter "register" | |
724 | * guest_tsc = host_tsc + tsc_offset -- 21.3 | |
725 | */ | |
726 | static u64 guest_read_tsc(void) | |
727 | { | |
728 | u64 host_tsc, tsc_offset; | |
729 | ||
730 | rdtscll(host_tsc); | |
731 | tsc_offset = vmcs_read64(TSC_OFFSET); | |
732 | return host_tsc + tsc_offset; | |
733 | } | |
734 | ||
735 | /* | |
736 | * writes 'guest_tsc' into guest's timestamp counter "register" | |
737 | * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc | |
738 | */ | |
739 | static void guest_write_tsc(u64 guest_tsc) | |
740 | { | |
741 | u64 host_tsc; | |
742 | ||
743 | rdtscll(host_tsc); | |
744 | vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc); | |
745 | } | |
746 | ||
747 | /* | |
748 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
749 | * Returns 0 on success, non-0 otherwise. | |
750 | * Assumes vcpu_load() was already called. | |
751 | */ | |
752 | static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
753 | { | |
754 | u64 data; | |
755 | struct kvm_msr_entry *msr; | |
756 | ||
757 | if (!pdata) { | |
758 | printk(KERN_ERR "BUG: get_msr called with NULL pdata\n"); | |
759 | return -EINVAL; | |
760 | } | |
761 | ||
762 | switch (msr_index) { | |
763 | #ifdef CONFIG_X86_64 | |
764 | case MSR_FS_BASE: | |
765 | data = vmcs_readl(GUEST_FS_BASE); | |
766 | break; | |
767 | case MSR_GS_BASE: | |
768 | data = vmcs_readl(GUEST_GS_BASE); | |
769 | break; | |
770 | case MSR_EFER: | |
771 | return kvm_get_msr_common(vcpu, msr_index, pdata); | |
772 | #endif | |
773 | case MSR_IA32_TIME_STAMP_COUNTER: | |
774 | data = guest_read_tsc(); | |
775 | break; | |
776 | case MSR_IA32_SYSENTER_CS: | |
777 | data = vmcs_read32(GUEST_SYSENTER_CS); | |
778 | break; | |
779 | case MSR_IA32_SYSENTER_EIP: | |
780 | data = vmcs_readl(GUEST_SYSENTER_EIP); | |
781 | break; | |
782 | case MSR_IA32_SYSENTER_ESP: | |
783 | data = vmcs_readl(GUEST_SYSENTER_ESP); | |
784 | break; | |
785 | default: | |
786 | msr = find_msr_entry(to_vmx(vcpu), msr_index); | |
787 | if (msr) { | |
788 | data = msr->data; | |
789 | break; | |
790 | } | |
791 | return kvm_get_msr_common(vcpu, msr_index, pdata); | |
792 | } | |
793 | ||
794 | *pdata = data; | |
795 | return 0; | |
796 | } | |
797 | ||
798 | /* | |
799 | * Writes msr value into into the appropriate "register". | |
800 | * Returns 0 on success, non-0 otherwise. | |
801 | * Assumes vcpu_load() was already called. | |
802 | */ | |
803 | static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
804 | { | |
805 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
806 | struct kvm_msr_entry *msr; | |
807 | int ret = 0; | |
808 | ||
809 | switch (msr_index) { | |
810 | #ifdef CONFIG_X86_64 | |
811 | case MSR_EFER: | |
812 | ret = kvm_set_msr_common(vcpu, msr_index, data); | |
813 | if (vmx->host_state.loaded) { | |
814 | reload_host_efer(vmx); | |
815 | load_transition_efer(vmx); | |
816 | } | |
817 | break; | |
818 | case MSR_FS_BASE: | |
819 | vmcs_writel(GUEST_FS_BASE, data); | |
820 | break; | |
821 | case MSR_GS_BASE: | |
822 | vmcs_writel(GUEST_GS_BASE, data); | |
823 | break; | |
824 | #endif | |
825 | case MSR_IA32_SYSENTER_CS: | |
826 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
827 | break; | |
828 | case MSR_IA32_SYSENTER_EIP: | |
829 | vmcs_writel(GUEST_SYSENTER_EIP, data); | |
830 | break; | |
831 | case MSR_IA32_SYSENTER_ESP: | |
832 | vmcs_writel(GUEST_SYSENTER_ESP, data); | |
833 | break; | |
834 | case MSR_IA32_TIME_STAMP_COUNTER: | |
835 | guest_write_tsc(data); | |
836 | break; | |
837 | default: | |
838 | msr = find_msr_entry(vmx, msr_index); | |
839 | if (msr) { | |
840 | msr->data = data; | |
841 | if (vmx->host_state.loaded) | |
842 | load_msrs(vmx->guest_msrs, vmx->save_nmsrs); | |
843 | break; | |
844 | } | |
845 | ret = kvm_set_msr_common(vcpu, msr_index, data); | |
846 | } | |
847 | ||
848 | return ret; | |
849 | } | |
850 | ||
851 | /* | |
852 | * Sync the rsp and rip registers into the vcpu structure. This allows | |
853 | * registers to be accessed by indexing vcpu->arch.regs. | |
854 | */ | |
855 | static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu) | |
856 | { | |
857 | vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
858 | vcpu->arch.rip = vmcs_readl(GUEST_RIP); | |
859 | } | |
860 | ||
861 | /* | |
862 | * Syncs rsp and rip back into the vmcs. Should be called after possible | |
863 | * modification. | |
864 | */ | |
865 | static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu) | |
866 | { | |
867 | vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); | |
868 | vmcs_writel(GUEST_RIP, vcpu->arch.rip); | |
869 | } | |
870 | ||
871 | static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) | |
872 | { | |
873 | unsigned long dr7 = 0x400; | |
874 | int old_singlestep; | |
875 | ||
876 | old_singlestep = vcpu->guest_debug.singlestep; | |
877 | ||
878 | vcpu->guest_debug.enabled = dbg->enabled; | |
879 | if (vcpu->guest_debug.enabled) { | |
880 | int i; | |
881 | ||
882 | dr7 |= 0x200; /* exact */ | |
883 | for (i = 0; i < 4; ++i) { | |
884 | if (!dbg->breakpoints[i].enabled) | |
885 | continue; | |
886 | vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address; | |
887 | dr7 |= 2 << (i*2); /* global enable */ | |
888 | dr7 |= 0 << (i*4+16); /* execution breakpoint */ | |
889 | } | |
890 | ||
891 | vcpu->guest_debug.singlestep = dbg->singlestep; | |
892 | } else | |
893 | vcpu->guest_debug.singlestep = 0; | |
894 | ||
895 | if (old_singlestep && !vcpu->guest_debug.singlestep) { | |
896 | unsigned long flags; | |
897 | ||
898 | flags = vmcs_readl(GUEST_RFLAGS); | |
899 | flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
900 | vmcs_writel(GUEST_RFLAGS, flags); | |
901 | } | |
902 | ||
903 | update_exception_bitmap(vcpu); | |
904 | vmcs_writel(GUEST_DR7, dr7); | |
905 | ||
906 | return 0; | |
907 | } | |
908 | ||
909 | static int vmx_get_irq(struct kvm_vcpu *vcpu) | |
910 | { | |
911 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
912 | u32 idtv_info_field; | |
913 | ||
914 | idtv_info_field = vmx->idt_vectoring_info; | |
915 | if (idtv_info_field & INTR_INFO_VALID_MASK) { | |
916 | if (is_external_interrupt(idtv_info_field)) | |
917 | return idtv_info_field & VECTORING_INFO_VECTOR_MASK; | |
918 | else | |
919 | printk(KERN_DEBUG "pending exception: not handled yet\n"); | |
920 | } | |
921 | return -1; | |
922 | } | |
923 | ||
924 | static __init int cpu_has_kvm_support(void) | |
925 | { | |
926 | unsigned long ecx = cpuid_ecx(1); | |
927 | return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */ | |
928 | } | |
929 | ||
930 | static __init int vmx_disabled_by_bios(void) | |
931 | { | |
932 | u64 msr; | |
933 | ||
934 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
935 | return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED | | |
936 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED)) | |
937 | == MSR_IA32_FEATURE_CONTROL_LOCKED; | |
938 | /* locked but not enabled */ | |
939 | } | |
940 | ||
941 | static void hardware_enable(void *garbage) | |
942 | { | |
943 | int cpu = raw_smp_processor_id(); | |
944 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
945 | u64 old; | |
946 | ||
947 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); | |
948 | if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED | | |
949 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED)) | |
950 | != (MSR_IA32_FEATURE_CONTROL_LOCKED | | |
951 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED)) | |
952 | /* enable and lock */ | |
953 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | | |
954 | MSR_IA32_FEATURE_CONTROL_LOCKED | | |
955 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED); | |
956 | write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */ | |
957 | asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr) | |
958 | : "memory", "cc"); | |
959 | } | |
960 | ||
961 | static void hardware_disable(void *garbage) | |
962 | { | |
963 | asm volatile (ASM_VMX_VMXOFF : : : "cc"); | |
964 | } | |
965 | ||
966 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, | |
967 | u32 msr, u32 *result) | |
968 | { | |
969 | u32 vmx_msr_low, vmx_msr_high; | |
970 | u32 ctl = ctl_min | ctl_opt; | |
971 | ||
972 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
973 | ||
974 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
975 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
976 | ||
977 | /* Ensure minimum (required) set of control bits are supported. */ | |
978 | if (ctl_min & ~ctl) | |
979 | return -EIO; | |
980 | ||
981 | *result = ctl; | |
982 | return 0; | |
983 | } | |
984 | ||
985 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) | |
986 | { | |
987 | u32 vmx_msr_low, vmx_msr_high; | |
988 | u32 min, opt; | |
989 | u32 _pin_based_exec_control = 0; | |
990 | u32 _cpu_based_exec_control = 0; | |
991 | u32 _cpu_based_2nd_exec_control = 0; | |
992 | u32 _vmexit_control = 0; | |
993 | u32 _vmentry_control = 0; | |
994 | ||
995 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; | |
996 | opt = 0; | |
997 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, | |
998 | &_pin_based_exec_control) < 0) | |
999 | return -EIO; | |
1000 | ||
1001 | min = CPU_BASED_HLT_EXITING | | |
1002 | #ifdef CONFIG_X86_64 | |
1003 | CPU_BASED_CR8_LOAD_EXITING | | |
1004 | CPU_BASED_CR8_STORE_EXITING | | |
1005 | #endif | |
1006 | CPU_BASED_USE_IO_BITMAPS | | |
1007 | CPU_BASED_MOV_DR_EXITING | | |
1008 | CPU_BASED_USE_TSC_OFFSETING; | |
1009 | opt = CPU_BASED_TPR_SHADOW | | |
1010 | CPU_BASED_USE_MSR_BITMAPS | | |
1011 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
1012 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, | |
1013 | &_cpu_based_exec_control) < 0) | |
1014 | return -EIO; | |
1015 | #ifdef CONFIG_X86_64 | |
1016 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
1017 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
1018 | ~CPU_BASED_CR8_STORE_EXITING; | |
1019 | #endif | |
1020 | if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { | |
1021 | min = 0; | |
1022 | opt = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
1023 | SECONDARY_EXEC_WBINVD_EXITING | | |
1024 | SECONDARY_EXEC_ENABLE_VPID; | |
1025 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS2, | |
1026 | &_cpu_based_2nd_exec_control) < 0) | |
1027 | return -EIO; | |
1028 | } | |
1029 | #ifndef CONFIG_X86_64 | |
1030 | if (!(_cpu_based_2nd_exec_control & | |
1031 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
1032 | _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; | |
1033 | #endif | |
1034 | ||
1035 | min = 0; | |
1036 | #ifdef CONFIG_X86_64 | |
1037 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
1038 | #endif | |
1039 | opt = 0; | |
1040 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, | |
1041 | &_vmexit_control) < 0) | |
1042 | return -EIO; | |
1043 | ||
1044 | min = opt = 0; | |
1045 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, | |
1046 | &_vmentry_control) < 0) | |
1047 | return -EIO; | |
1048 | ||
1049 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); | |
1050 | ||
1051 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
1052 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
1053 | return -EIO; | |
1054 | ||
1055 | #ifdef CONFIG_X86_64 | |
1056 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
1057 | if (vmx_msr_high & (1u<<16)) | |
1058 | return -EIO; | |
1059 | #endif | |
1060 | ||
1061 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
1062 | if (((vmx_msr_high >> 18) & 15) != 6) | |
1063 | return -EIO; | |
1064 | ||
1065 | vmcs_conf->size = vmx_msr_high & 0x1fff; | |
1066 | vmcs_conf->order = get_order(vmcs_config.size); | |
1067 | vmcs_conf->revision_id = vmx_msr_low; | |
1068 | ||
1069 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; | |
1070 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
1071 | vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; | |
1072 | vmcs_conf->vmexit_ctrl = _vmexit_control; | |
1073 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1074 | ||
1075 | return 0; | |
1076 | } | |
1077 | ||
1078 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
1079 | { | |
1080 | int node = cpu_to_node(cpu); | |
1081 | struct page *pages; | |
1082 | struct vmcs *vmcs; | |
1083 | ||
1084 | pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order); | |
1085 | if (!pages) | |
1086 | return NULL; | |
1087 | vmcs = page_address(pages); | |
1088 | memset(vmcs, 0, vmcs_config.size); | |
1089 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
1090 | return vmcs; | |
1091 | } | |
1092 | ||
1093 | static struct vmcs *alloc_vmcs(void) | |
1094 | { | |
1095 | return alloc_vmcs_cpu(raw_smp_processor_id()); | |
1096 | } | |
1097 | ||
1098 | static void free_vmcs(struct vmcs *vmcs) | |
1099 | { | |
1100 | free_pages((unsigned long)vmcs, vmcs_config.order); | |
1101 | } | |
1102 | ||
1103 | static void free_kvm_area(void) | |
1104 | { | |
1105 | int cpu; | |
1106 | ||
1107 | for_each_online_cpu(cpu) | |
1108 | free_vmcs(per_cpu(vmxarea, cpu)); | |
1109 | } | |
1110 | ||
1111 | static __init int alloc_kvm_area(void) | |
1112 | { | |
1113 | int cpu; | |
1114 | ||
1115 | for_each_online_cpu(cpu) { | |
1116 | struct vmcs *vmcs; | |
1117 | ||
1118 | vmcs = alloc_vmcs_cpu(cpu); | |
1119 | if (!vmcs) { | |
1120 | free_kvm_area(); | |
1121 | return -ENOMEM; | |
1122 | } | |
1123 | ||
1124 | per_cpu(vmxarea, cpu) = vmcs; | |
1125 | } | |
1126 | return 0; | |
1127 | } | |
1128 | ||
1129 | static __init int hardware_setup(void) | |
1130 | { | |
1131 | if (setup_vmcs_config(&vmcs_config) < 0) | |
1132 | return -EIO; | |
1133 | ||
1134 | if (boot_cpu_has(X86_FEATURE_NX)) | |
1135 | kvm_enable_efer_bits(EFER_NX); | |
1136 | ||
1137 | return alloc_kvm_area(); | |
1138 | } | |
1139 | ||
1140 | static __exit void hardware_unsetup(void) | |
1141 | { | |
1142 | free_kvm_area(); | |
1143 | } | |
1144 | ||
1145 | static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save) | |
1146 | { | |
1147 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1148 | ||
1149 | if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) { | |
1150 | vmcs_write16(sf->selector, save->selector); | |
1151 | vmcs_writel(sf->base, save->base); | |
1152 | vmcs_write32(sf->limit, save->limit); | |
1153 | vmcs_write32(sf->ar_bytes, save->ar); | |
1154 | } else { | |
1155 | u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK) | |
1156 | << AR_DPL_SHIFT; | |
1157 | vmcs_write32(sf->ar_bytes, 0x93 | dpl); | |
1158 | } | |
1159 | } | |
1160 | ||
1161 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
1162 | { | |
1163 | unsigned long flags; | |
1164 | ||
1165 | vcpu->arch.rmode.active = 0; | |
1166 | ||
1167 | vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base); | |
1168 | vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit); | |
1169 | vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar); | |
1170 | ||
1171 | flags = vmcs_readl(GUEST_RFLAGS); | |
1172 | flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM); | |
1173 | flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT); | |
1174 | vmcs_writel(GUEST_RFLAGS, flags); | |
1175 | ||
1176 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | | |
1177 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
1178 | ||
1179 | update_exception_bitmap(vcpu); | |
1180 | ||
1181 | fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es); | |
1182 | fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds); | |
1183 | fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs); | |
1184 | fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs); | |
1185 | ||
1186 | vmcs_write16(GUEST_SS_SELECTOR, 0); | |
1187 | vmcs_write32(GUEST_SS_AR_BYTES, 0x93); | |
1188 | ||
1189 | vmcs_write16(GUEST_CS_SELECTOR, | |
1190 | vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK); | |
1191 | vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); | |
1192 | } | |
1193 | ||
1194 | static gva_t rmode_tss_base(struct kvm *kvm) | |
1195 | { | |
1196 | if (!kvm->arch.tss_addr) { | |
1197 | gfn_t base_gfn = kvm->memslots[0].base_gfn + | |
1198 | kvm->memslots[0].npages - 3; | |
1199 | return base_gfn << PAGE_SHIFT; | |
1200 | } | |
1201 | return kvm->arch.tss_addr; | |
1202 | } | |
1203 | ||
1204 | static void fix_rmode_seg(int seg, struct kvm_save_segment *save) | |
1205 | { | |
1206 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1207 | ||
1208 | save->selector = vmcs_read16(sf->selector); | |
1209 | save->base = vmcs_readl(sf->base); | |
1210 | save->limit = vmcs_read32(sf->limit); | |
1211 | save->ar = vmcs_read32(sf->ar_bytes); | |
1212 | vmcs_write16(sf->selector, save->base >> 4); | |
1213 | vmcs_write32(sf->base, save->base & 0xfffff); | |
1214 | vmcs_write32(sf->limit, 0xffff); | |
1215 | vmcs_write32(sf->ar_bytes, 0xf3); | |
1216 | } | |
1217 | ||
1218 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
1219 | { | |
1220 | unsigned long flags; | |
1221 | ||
1222 | vcpu->arch.rmode.active = 1; | |
1223 | ||
1224 | vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE); | |
1225 | vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm)); | |
1226 | ||
1227 | vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT); | |
1228 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); | |
1229 | ||
1230 | vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES); | |
1231 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
1232 | ||
1233 | flags = vmcs_readl(GUEST_RFLAGS); | |
1234 | vcpu->arch.rmode.save_iopl | |
1235 | = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
1236 | ||
1237 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; | |
1238 | ||
1239 | vmcs_writel(GUEST_RFLAGS, flags); | |
1240 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); | |
1241 | update_exception_bitmap(vcpu); | |
1242 | ||
1243 | vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4); | |
1244 | vmcs_write32(GUEST_SS_LIMIT, 0xffff); | |
1245 | vmcs_write32(GUEST_SS_AR_BYTES, 0xf3); | |
1246 | ||
1247 | vmcs_write32(GUEST_CS_AR_BYTES, 0xf3); | |
1248 | vmcs_write32(GUEST_CS_LIMIT, 0xffff); | |
1249 | if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000) | |
1250 | vmcs_writel(GUEST_CS_BASE, 0xf0000); | |
1251 | vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4); | |
1252 | ||
1253 | fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es); | |
1254 | fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds); | |
1255 | fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs); | |
1256 | fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs); | |
1257 | ||
1258 | kvm_mmu_reset_context(vcpu); | |
1259 | init_rmode_tss(vcpu->kvm); | |
1260 | } | |
1261 | ||
1262 | #ifdef CONFIG_X86_64 | |
1263 | ||
1264 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
1265 | { | |
1266 | u32 guest_tr_ar; | |
1267 | ||
1268 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); | |
1269 | if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) { | |
1270 | printk(KERN_DEBUG "%s: tss fixup for long mode. \n", | |
1271 | __func__); | |
1272 | vmcs_write32(GUEST_TR_AR_BYTES, | |
1273 | (guest_tr_ar & ~AR_TYPE_MASK) | |
1274 | | AR_TYPE_BUSY_64_TSS); | |
1275 | } | |
1276 | ||
1277 | vcpu->arch.shadow_efer |= EFER_LMA; | |
1278 | ||
1279 | find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME; | |
1280 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1281 | vmcs_read32(VM_ENTRY_CONTROLS) | |
1282 | | VM_ENTRY_IA32E_MODE); | |
1283 | } | |
1284 | ||
1285 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
1286 | { | |
1287 | vcpu->arch.shadow_efer &= ~EFER_LMA; | |
1288 | ||
1289 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1290 | vmcs_read32(VM_ENTRY_CONTROLS) | |
1291 | & ~VM_ENTRY_IA32E_MODE); | |
1292 | } | |
1293 | ||
1294 | #endif | |
1295 | ||
1296 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) | |
1297 | { | |
1298 | vpid_sync_vcpu_all(to_vmx(vcpu)); | |
1299 | } | |
1300 | ||
1301 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) | |
1302 | { | |
1303 | vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK; | |
1304 | vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK; | |
1305 | } | |
1306 | ||
1307 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) | |
1308 | { | |
1309 | vmx_fpu_deactivate(vcpu); | |
1310 | ||
1311 | if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE)) | |
1312 | enter_pmode(vcpu); | |
1313 | ||
1314 | if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE)) | |
1315 | enter_rmode(vcpu); | |
1316 | ||
1317 | #ifdef CONFIG_X86_64 | |
1318 | if (vcpu->arch.shadow_efer & EFER_LME) { | |
1319 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) | |
1320 | enter_lmode(vcpu); | |
1321 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) | |
1322 | exit_lmode(vcpu); | |
1323 | } | |
1324 | #endif | |
1325 | ||
1326 | vmcs_writel(CR0_READ_SHADOW, cr0); | |
1327 | vmcs_writel(GUEST_CR0, | |
1328 | (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON); | |
1329 | vcpu->arch.cr0 = cr0; | |
1330 | ||
1331 | if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE)) | |
1332 | vmx_fpu_activate(vcpu); | |
1333 | } | |
1334 | ||
1335 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) | |
1336 | { | |
1337 | vmx_flush_tlb(vcpu); | |
1338 | vmcs_writel(GUEST_CR3, cr3); | |
1339 | if (vcpu->arch.cr0 & X86_CR0_PE) | |
1340 | vmx_fpu_deactivate(vcpu); | |
1341 | } | |
1342 | ||
1343 | static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1344 | { | |
1345 | vmcs_writel(CR4_READ_SHADOW, cr4); | |
1346 | vmcs_writel(GUEST_CR4, cr4 | (vcpu->arch.rmode.active ? | |
1347 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON)); | |
1348 | vcpu->arch.cr4 = cr4; | |
1349 | } | |
1350 | ||
1351 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
1352 | { | |
1353 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
1354 | struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); | |
1355 | ||
1356 | vcpu->arch.shadow_efer = efer; | |
1357 | if (!msr) | |
1358 | return; | |
1359 | if (efer & EFER_LMA) { | |
1360 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1361 | vmcs_read32(VM_ENTRY_CONTROLS) | | |
1362 | VM_ENTRY_IA32E_MODE); | |
1363 | msr->data = efer; | |
1364 | ||
1365 | } else { | |
1366 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1367 | vmcs_read32(VM_ENTRY_CONTROLS) & | |
1368 | ~VM_ENTRY_IA32E_MODE); | |
1369 | ||
1370 | msr->data = efer & ~EFER_LME; | |
1371 | } | |
1372 | setup_msrs(vmx); | |
1373 | } | |
1374 | ||
1375 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
1376 | { | |
1377 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1378 | ||
1379 | return vmcs_readl(sf->base); | |
1380 | } | |
1381 | ||
1382 | static void vmx_get_segment(struct kvm_vcpu *vcpu, | |
1383 | struct kvm_segment *var, int seg) | |
1384 | { | |
1385 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1386 | u32 ar; | |
1387 | ||
1388 | var->base = vmcs_readl(sf->base); | |
1389 | var->limit = vmcs_read32(sf->limit); | |
1390 | var->selector = vmcs_read16(sf->selector); | |
1391 | ar = vmcs_read32(sf->ar_bytes); | |
1392 | if (ar & AR_UNUSABLE_MASK) | |
1393 | ar = 0; | |
1394 | var->type = ar & 15; | |
1395 | var->s = (ar >> 4) & 1; | |
1396 | var->dpl = (ar >> 5) & 3; | |
1397 | var->present = (ar >> 7) & 1; | |
1398 | var->avl = (ar >> 12) & 1; | |
1399 | var->l = (ar >> 13) & 1; | |
1400 | var->db = (ar >> 14) & 1; | |
1401 | var->g = (ar >> 15) & 1; | |
1402 | var->unusable = (ar >> 16) & 1; | |
1403 | } | |
1404 | ||
1405 | static int vmx_get_cpl(struct kvm_vcpu *vcpu) | |
1406 | { | |
1407 | struct kvm_segment kvm_seg; | |
1408 | ||
1409 | if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */ | |
1410 | return 0; | |
1411 | ||
1412 | if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */ | |
1413 | return 3; | |
1414 | ||
1415 | vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS); | |
1416 | return kvm_seg.selector & 3; | |
1417 | } | |
1418 | ||
1419 | static u32 vmx_segment_access_rights(struct kvm_segment *var) | |
1420 | { | |
1421 | u32 ar; | |
1422 | ||
1423 | if (var->unusable) | |
1424 | ar = 1 << 16; | |
1425 | else { | |
1426 | ar = var->type & 15; | |
1427 | ar |= (var->s & 1) << 4; | |
1428 | ar |= (var->dpl & 3) << 5; | |
1429 | ar |= (var->present & 1) << 7; | |
1430 | ar |= (var->avl & 1) << 12; | |
1431 | ar |= (var->l & 1) << 13; | |
1432 | ar |= (var->db & 1) << 14; | |
1433 | ar |= (var->g & 1) << 15; | |
1434 | } | |
1435 | if (ar == 0) /* a 0 value means unusable */ | |
1436 | ar = AR_UNUSABLE_MASK; | |
1437 | ||
1438 | return ar; | |
1439 | } | |
1440 | ||
1441 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
1442 | struct kvm_segment *var, int seg) | |
1443 | { | |
1444 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1445 | u32 ar; | |
1446 | ||
1447 | if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) { | |
1448 | vcpu->arch.rmode.tr.selector = var->selector; | |
1449 | vcpu->arch.rmode.tr.base = var->base; | |
1450 | vcpu->arch.rmode.tr.limit = var->limit; | |
1451 | vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var); | |
1452 | return; | |
1453 | } | |
1454 | vmcs_writel(sf->base, var->base); | |
1455 | vmcs_write32(sf->limit, var->limit); | |
1456 | vmcs_write16(sf->selector, var->selector); | |
1457 | if (vcpu->arch.rmode.active && var->s) { | |
1458 | /* | |
1459 | * Hack real-mode segments into vm86 compatibility. | |
1460 | */ | |
1461 | if (var->base == 0xffff0000 && var->selector == 0xf000) | |
1462 | vmcs_writel(sf->base, 0xf0000); | |
1463 | ar = 0xf3; | |
1464 | } else | |
1465 | ar = vmx_segment_access_rights(var); | |
1466 | vmcs_write32(sf->ar_bytes, ar); | |
1467 | } | |
1468 | ||
1469 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) | |
1470 | { | |
1471 | u32 ar = vmcs_read32(GUEST_CS_AR_BYTES); | |
1472 | ||
1473 | *db = (ar >> 14) & 1; | |
1474 | *l = (ar >> 13) & 1; | |
1475 | } | |
1476 | ||
1477 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1478 | { | |
1479 | dt->limit = vmcs_read32(GUEST_IDTR_LIMIT); | |
1480 | dt->base = vmcs_readl(GUEST_IDTR_BASE); | |
1481 | } | |
1482 | ||
1483 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1484 | { | |
1485 | vmcs_write32(GUEST_IDTR_LIMIT, dt->limit); | |
1486 | vmcs_writel(GUEST_IDTR_BASE, dt->base); | |
1487 | } | |
1488 | ||
1489 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1490 | { | |
1491 | dt->limit = vmcs_read32(GUEST_GDTR_LIMIT); | |
1492 | dt->base = vmcs_readl(GUEST_GDTR_BASE); | |
1493 | } | |
1494 | ||
1495 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1496 | { | |
1497 | vmcs_write32(GUEST_GDTR_LIMIT, dt->limit); | |
1498 | vmcs_writel(GUEST_GDTR_BASE, dt->base); | |
1499 | } | |
1500 | ||
1501 | static int init_rmode_tss(struct kvm *kvm) | |
1502 | { | |
1503 | gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT; | |
1504 | u16 data = 0; | |
1505 | int ret = 0; | |
1506 | int r; | |
1507 | ||
1508 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); | |
1509 | if (r < 0) | |
1510 | goto out; | |
1511 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; | |
1512 | r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16)); | |
1513 | if (r < 0) | |
1514 | goto out; | |
1515 | r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); | |
1516 | if (r < 0) | |
1517 | goto out; | |
1518 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); | |
1519 | if (r < 0) | |
1520 | goto out; | |
1521 | data = ~0; | |
1522 | r = kvm_write_guest_page(kvm, fn, &data, | |
1523 | RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, | |
1524 | sizeof(u8)); | |
1525 | if (r < 0) | |
1526 | goto out; | |
1527 | ||
1528 | ret = 1; | |
1529 | out: | |
1530 | return ret; | |
1531 | } | |
1532 | ||
1533 | static void seg_setup(int seg) | |
1534 | { | |
1535 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1536 | ||
1537 | vmcs_write16(sf->selector, 0); | |
1538 | vmcs_writel(sf->base, 0); | |
1539 | vmcs_write32(sf->limit, 0xffff); | |
1540 | vmcs_write32(sf->ar_bytes, 0x93); | |
1541 | } | |
1542 | ||
1543 | static int alloc_apic_access_page(struct kvm *kvm) | |
1544 | { | |
1545 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
1546 | int r = 0; | |
1547 | ||
1548 | down_write(&kvm->slots_lock); | |
1549 | if (kvm->arch.apic_access_page) | |
1550 | goto out; | |
1551 | kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; | |
1552 | kvm_userspace_mem.flags = 0; | |
1553 | kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL; | |
1554 | kvm_userspace_mem.memory_size = PAGE_SIZE; | |
1555 | r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
1556 | if (r) | |
1557 | goto out; | |
1558 | ||
1559 | down_read(¤t->mm->mmap_sem); | |
1560 | kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00); | |
1561 | up_read(¤t->mm->mmap_sem); | |
1562 | out: | |
1563 | up_write(&kvm->slots_lock); | |
1564 | return r; | |
1565 | } | |
1566 | ||
1567 | static void allocate_vpid(struct vcpu_vmx *vmx) | |
1568 | { | |
1569 | int vpid; | |
1570 | ||
1571 | vmx->vpid = 0; | |
1572 | if (!enable_vpid || !cpu_has_vmx_vpid()) | |
1573 | return; | |
1574 | spin_lock(&vmx_vpid_lock); | |
1575 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
1576 | if (vpid < VMX_NR_VPIDS) { | |
1577 | vmx->vpid = vpid; | |
1578 | __set_bit(vpid, vmx_vpid_bitmap); | |
1579 | } | |
1580 | spin_unlock(&vmx_vpid_lock); | |
1581 | } | |
1582 | ||
1583 | void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr) | |
1584 | { | |
1585 | void *va; | |
1586 | ||
1587 | if (!cpu_has_vmx_msr_bitmap()) | |
1588 | return; | |
1589 | ||
1590 | /* | |
1591 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
1592 | * have the write-low and read-high bitmap offsets the wrong way round. | |
1593 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
1594 | */ | |
1595 | va = kmap(msr_bitmap); | |
1596 | if (msr <= 0x1fff) { | |
1597 | __clear_bit(msr, va + 0x000); /* read-low */ | |
1598 | __clear_bit(msr, va + 0x800); /* write-low */ | |
1599 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
1600 | msr &= 0x1fff; | |
1601 | __clear_bit(msr, va + 0x400); /* read-high */ | |
1602 | __clear_bit(msr, va + 0xc00); /* write-high */ | |
1603 | } | |
1604 | kunmap(msr_bitmap); | |
1605 | } | |
1606 | ||
1607 | /* | |
1608 | * Sets up the vmcs for emulated real mode. | |
1609 | */ | |
1610 | static int vmx_vcpu_setup(struct vcpu_vmx *vmx) | |
1611 | { | |
1612 | u32 host_sysenter_cs; | |
1613 | u32 junk; | |
1614 | unsigned long a; | |
1615 | struct descriptor_table dt; | |
1616 | int i; | |
1617 | unsigned long kvm_vmx_return; | |
1618 | u32 exec_control; | |
1619 | ||
1620 | /* I/O */ | |
1621 | vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a)); | |
1622 | vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b)); | |
1623 | ||
1624 | if (cpu_has_vmx_msr_bitmap()) | |
1625 | vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap)); | |
1626 | ||
1627 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ | |
1628 | ||
1629 | /* Control */ | |
1630 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, | |
1631 | vmcs_config.pin_based_exec_ctrl); | |
1632 | ||
1633 | exec_control = vmcs_config.cpu_based_exec_ctrl; | |
1634 | if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) { | |
1635 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
1636 | #ifdef CONFIG_X86_64 | |
1637 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
1638 | CPU_BASED_CR8_LOAD_EXITING; | |
1639 | #endif | |
1640 | } | |
1641 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); | |
1642 | ||
1643 | if (cpu_has_secondary_exec_ctrls()) { | |
1644 | exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; | |
1645 | if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
1646 | exec_control &= | |
1647 | ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
1648 | if (vmx->vpid == 0) | |
1649 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | |
1650 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); | |
1651 | } | |
1652 | ||
1653 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf); | |
1654 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf); | |
1655 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ | |
1656 | ||
1657 | vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */ | |
1658 | vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */ | |
1659 | vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */ | |
1660 | ||
1661 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ | |
1662 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
1663 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
1664 | vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */ | |
1665 | vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */ | |
1666 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
1667 | #ifdef CONFIG_X86_64 | |
1668 | rdmsrl(MSR_FS_BASE, a); | |
1669 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
1670 | rdmsrl(MSR_GS_BASE, a); | |
1671 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
1672 | #else | |
1673 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
1674 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
1675 | #endif | |
1676 | ||
1677 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
1678 | ||
1679 | get_idt(&dt); | |
1680 | vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */ | |
1681 | ||
1682 | asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return)); | |
1683 | vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */ | |
1684 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); | |
1685 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
1686 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); | |
1687 | ||
1688 | rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk); | |
1689 | vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs); | |
1690 | rdmsrl(MSR_IA32_SYSENTER_ESP, a); | |
1691 | vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */ | |
1692 | rdmsrl(MSR_IA32_SYSENTER_EIP, a); | |
1693 | vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */ | |
1694 | ||
1695 | for (i = 0; i < NR_VMX_MSR; ++i) { | |
1696 | u32 index = vmx_msr_index[i]; | |
1697 | u32 data_low, data_high; | |
1698 | u64 data; | |
1699 | int j = vmx->nmsrs; | |
1700 | ||
1701 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
1702 | continue; | |
1703 | if (wrmsr_safe(index, data_low, data_high) < 0) | |
1704 | continue; | |
1705 | data = data_low | ((u64)data_high << 32); | |
1706 | vmx->host_msrs[j].index = index; | |
1707 | vmx->host_msrs[j].reserved = 0; | |
1708 | vmx->host_msrs[j].data = data; | |
1709 | vmx->guest_msrs[j] = vmx->host_msrs[j]; | |
1710 | ++vmx->nmsrs; | |
1711 | } | |
1712 | ||
1713 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); | |
1714 | ||
1715 | /* 22.2.1, 20.8.1 */ | |
1716 | vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl); | |
1717 | ||
1718 | vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL); | |
1719 | vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK); | |
1720 | ||
1721 | ||
1722 | return 0; | |
1723 | } | |
1724 | ||
1725 | static int vmx_vcpu_reset(struct kvm_vcpu *vcpu) | |
1726 | { | |
1727 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
1728 | u64 msr; | |
1729 | int ret; | |
1730 | ||
1731 | down_read(&vcpu->kvm->slots_lock); | |
1732 | if (!init_rmode_tss(vmx->vcpu.kvm)) { | |
1733 | ret = -ENOMEM; | |
1734 | goto out; | |
1735 | } | |
1736 | ||
1737 | vmx->vcpu.arch.rmode.active = 0; | |
1738 | ||
1739 | vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); | |
1740 | kvm_set_cr8(&vmx->vcpu, 0); | |
1741 | msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; | |
1742 | if (vmx->vcpu.vcpu_id == 0) | |
1743 | msr |= MSR_IA32_APICBASE_BSP; | |
1744 | kvm_set_apic_base(&vmx->vcpu, msr); | |
1745 | ||
1746 | fx_init(&vmx->vcpu); | |
1747 | ||
1748 | /* | |
1749 | * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode | |
1750 | * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh. | |
1751 | */ | |
1752 | if (vmx->vcpu.vcpu_id == 0) { | |
1753 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); | |
1754 | vmcs_writel(GUEST_CS_BASE, 0x000f0000); | |
1755 | } else { | |
1756 | vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8); | |
1757 | vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12); | |
1758 | } | |
1759 | vmcs_write32(GUEST_CS_LIMIT, 0xffff); | |
1760 | vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); | |
1761 | ||
1762 | seg_setup(VCPU_SREG_DS); | |
1763 | seg_setup(VCPU_SREG_ES); | |
1764 | seg_setup(VCPU_SREG_FS); | |
1765 | seg_setup(VCPU_SREG_GS); | |
1766 | seg_setup(VCPU_SREG_SS); | |
1767 | ||
1768 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
1769 | vmcs_writel(GUEST_TR_BASE, 0); | |
1770 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
1771 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
1772 | ||
1773 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
1774 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
1775 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
1776 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
1777 | ||
1778 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
1779 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
1780 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
1781 | ||
1782 | vmcs_writel(GUEST_RFLAGS, 0x02); | |
1783 | if (vmx->vcpu.vcpu_id == 0) | |
1784 | vmcs_writel(GUEST_RIP, 0xfff0); | |
1785 | else | |
1786 | vmcs_writel(GUEST_RIP, 0); | |
1787 | vmcs_writel(GUEST_RSP, 0); | |
1788 | ||
1789 | /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */ | |
1790 | vmcs_writel(GUEST_DR7, 0x400); | |
1791 | ||
1792 | vmcs_writel(GUEST_GDTR_BASE, 0); | |
1793 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
1794 | ||
1795 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
1796 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
1797 | ||
1798 | vmcs_write32(GUEST_ACTIVITY_STATE, 0); | |
1799 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); | |
1800 | vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0); | |
1801 | ||
1802 | guest_write_tsc(0); | |
1803 | ||
1804 | /* Special registers */ | |
1805 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
1806 | ||
1807 | setup_msrs(vmx); | |
1808 | ||
1809 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ | |
1810 | ||
1811 | if (cpu_has_vmx_tpr_shadow()) { | |
1812 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); | |
1813 | if (vm_need_tpr_shadow(vmx->vcpu.kvm)) | |
1814 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, | |
1815 | page_to_phys(vmx->vcpu.arch.apic->regs_page)); | |
1816 | vmcs_write32(TPR_THRESHOLD, 0); | |
1817 | } | |
1818 | ||
1819 | if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
1820 | vmcs_write64(APIC_ACCESS_ADDR, | |
1821 | page_to_phys(vmx->vcpu.kvm->arch.apic_access_page)); | |
1822 | ||
1823 | if (vmx->vpid != 0) | |
1824 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
1825 | ||
1826 | vmx->vcpu.arch.cr0 = 0x60000010; | |
1827 | vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */ | |
1828 | vmx_set_cr4(&vmx->vcpu, 0); | |
1829 | vmx_set_efer(&vmx->vcpu, 0); | |
1830 | vmx_fpu_activate(&vmx->vcpu); | |
1831 | update_exception_bitmap(&vmx->vcpu); | |
1832 | ||
1833 | vpid_sync_vcpu_all(vmx); | |
1834 | ||
1835 | ret = 0; | |
1836 | ||
1837 | out: | |
1838 | up_read(&vcpu->kvm->slots_lock); | |
1839 | return ret; | |
1840 | } | |
1841 | ||
1842 | static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq) | |
1843 | { | |
1844 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
1845 | ||
1846 | if (vcpu->arch.rmode.active) { | |
1847 | vmx->rmode.irq.pending = true; | |
1848 | vmx->rmode.irq.vector = irq; | |
1849 | vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP); | |
1850 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
1851 | irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK); | |
1852 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1); | |
1853 | vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1); | |
1854 | return; | |
1855 | } | |
1856 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
1857 | irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
1858 | } | |
1859 | ||
1860 | static void kvm_do_inject_irq(struct kvm_vcpu *vcpu) | |
1861 | { | |
1862 | int word_index = __ffs(vcpu->arch.irq_summary); | |
1863 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
1864 | int irq = word_index * BITS_PER_LONG + bit_index; | |
1865 | ||
1866 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); | |
1867 | if (!vcpu->arch.irq_pending[word_index]) | |
1868 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
1869 | vmx_inject_irq(vcpu, irq); | |
1870 | } | |
1871 | ||
1872 | ||
1873 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, | |
1874 | struct kvm_run *kvm_run) | |
1875 | { | |
1876 | u32 cpu_based_vm_exec_control; | |
1877 | ||
1878 | vcpu->arch.interrupt_window_open = | |
1879 | ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && | |
1880 | (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0); | |
1881 | ||
1882 | if (vcpu->arch.interrupt_window_open && | |
1883 | vcpu->arch.irq_summary && | |
1884 | !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK)) | |
1885 | /* | |
1886 | * If interrupts enabled, and not blocked by sti or mov ss. Good. | |
1887 | */ | |
1888 | kvm_do_inject_irq(vcpu); | |
1889 | ||
1890 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
1891 | if (!vcpu->arch.interrupt_window_open && | |
1892 | (vcpu->arch.irq_summary || kvm_run->request_interrupt_window)) | |
1893 | /* | |
1894 | * Interrupts blocked. Wait for unblock. | |
1895 | */ | |
1896 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; | |
1897 | else | |
1898 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
1899 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
1900 | } | |
1901 | ||
1902 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) | |
1903 | { | |
1904 | int ret; | |
1905 | struct kvm_userspace_memory_region tss_mem = { | |
1906 | .slot = 8, | |
1907 | .guest_phys_addr = addr, | |
1908 | .memory_size = PAGE_SIZE * 3, | |
1909 | .flags = 0, | |
1910 | }; | |
1911 | ||
1912 | ret = kvm_set_memory_region(kvm, &tss_mem, 0); | |
1913 | if (ret) | |
1914 | return ret; | |
1915 | kvm->arch.tss_addr = addr; | |
1916 | return 0; | |
1917 | } | |
1918 | ||
1919 | static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu) | |
1920 | { | |
1921 | struct kvm_guest_debug *dbg = &vcpu->guest_debug; | |
1922 | ||
1923 | set_debugreg(dbg->bp[0], 0); | |
1924 | set_debugreg(dbg->bp[1], 1); | |
1925 | set_debugreg(dbg->bp[2], 2); | |
1926 | set_debugreg(dbg->bp[3], 3); | |
1927 | ||
1928 | if (dbg->singlestep) { | |
1929 | unsigned long flags; | |
1930 | ||
1931 | flags = vmcs_readl(GUEST_RFLAGS); | |
1932 | flags |= X86_EFLAGS_TF | X86_EFLAGS_RF; | |
1933 | vmcs_writel(GUEST_RFLAGS, flags); | |
1934 | } | |
1935 | } | |
1936 | ||
1937 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, | |
1938 | int vec, u32 err_code) | |
1939 | { | |
1940 | if (!vcpu->arch.rmode.active) | |
1941 | return 0; | |
1942 | ||
1943 | /* | |
1944 | * Instruction with address size override prefix opcode 0x67 | |
1945 | * Cause the #SS fault with 0 error code in VM86 mode. | |
1946 | */ | |
1947 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) | |
1948 | if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE) | |
1949 | return 1; | |
1950 | return 0; | |
1951 | } | |
1952 | ||
1953 | static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
1954 | { | |
1955 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
1956 | u32 intr_info, error_code; | |
1957 | unsigned long cr2, rip; | |
1958 | u32 vect_info; | |
1959 | enum emulation_result er; | |
1960 | ||
1961 | vect_info = vmx->idt_vectoring_info; | |
1962 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
1963 | ||
1964 | if ((vect_info & VECTORING_INFO_VALID_MASK) && | |
1965 | !is_page_fault(intr_info)) | |
1966 | printk(KERN_ERR "%s: unexpected, vectoring info 0x%x " | |
1967 | "intr info 0x%x\n", __func__, vect_info, intr_info); | |
1968 | ||
1969 | if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) { | |
1970 | int irq = vect_info & VECTORING_INFO_VECTOR_MASK; | |
1971 | set_bit(irq, vcpu->arch.irq_pending); | |
1972 | set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary); | |
1973 | } | |
1974 | ||
1975 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */ | |
1976 | return 1; /* already handled by vmx_vcpu_run() */ | |
1977 | ||
1978 | if (is_no_device(intr_info)) { | |
1979 | vmx_fpu_activate(vcpu); | |
1980 | return 1; | |
1981 | } | |
1982 | ||
1983 | if (is_invalid_opcode(intr_info)) { | |
1984 | er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD); | |
1985 | if (er != EMULATE_DONE) | |
1986 | kvm_queue_exception(vcpu, UD_VECTOR); | |
1987 | return 1; | |
1988 | } | |
1989 | ||
1990 | error_code = 0; | |
1991 | rip = vmcs_readl(GUEST_RIP); | |
1992 | if (intr_info & INTR_INFO_DELIVER_CODE_MASK) | |
1993 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); | |
1994 | if (is_page_fault(intr_info)) { | |
1995 | cr2 = vmcs_readl(EXIT_QUALIFICATION); | |
1996 | return kvm_mmu_page_fault(vcpu, cr2, error_code); | |
1997 | } | |
1998 | ||
1999 | if (vcpu->arch.rmode.active && | |
2000 | handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK, | |
2001 | error_code)) { | |
2002 | if (vcpu->arch.halt_request) { | |
2003 | vcpu->arch.halt_request = 0; | |
2004 | return kvm_emulate_halt(vcpu); | |
2005 | } | |
2006 | return 1; | |
2007 | } | |
2008 | ||
2009 | if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == | |
2010 | (INTR_TYPE_EXCEPTION | 1)) { | |
2011 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
2012 | return 0; | |
2013 | } | |
2014 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; | |
2015 | kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK; | |
2016 | kvm_run->ex.error_code = error_code; | |
2017 | return 0; | |
2018 | } | |
2019 | ||
2020 | static int handle_external_interrupt(struct kvm_vcpu *vcpu, | |
2021 | struct kvm_run *kvm_run) | |
2022 | { | |
2023 | ++vcpu->stat.irq_exits; | |
2024 | return 1; | |
2025 | } | |
2026 | ||
2027 | static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2028 | { | |
2029 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
2030 | return 0; | |
2031 | } | |
2032 | ||
2033 | static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2034 | { | |
2035 | unsigned long exit_qualification; | |
2036 | int size, down, in, string, rep; | |
2037 | unsigned port; | |
2038 | ||
2039 | ++vcpu->stat.io_exits; | |
2040 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
2041 | string = (exit_qualification & 16) != 0; | |
2042 | ||
2043 | if (string) { | |
2044 | if (emulate_instruction(vcpu, | |
2045 | kvm_run, 0, 0, 0) == EMULATE_DO_MMIO) | |
2046 | return 0; | |
2047 | return 1; | |
2048 | } | |
2049 | ||
2050 | size = (exit_qualification & 7) + 1; | |
2051 | in = (exit_qualification & 8) != 0; | |
2052 | down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0; | |
2053 | rep = (exit_qualification & 32) != 0; | |
2054 | port = exit_qualification >> 16; | |
2055 | ||
2056 | return kvm_emulate_pio(vcpu, kvm_run, in, size, port); | |
2057 | } | |
2058 | ||
2059 | static void | |
2060 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
2061 | { | |
2062 | /* | |
2063 | * Patch in the VMCALL instruction: | |
2064 | */ | |
2065 | hypercall[0] = 0x0f; | |
2066 | hypercall[1] = 0x01; | |
2067 | hypercall[2] = 0xc1; | |
2068 | } | |
2069 | ||
2070 | static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2071 | { | |
2072 | unsigned long exit_qualification; | |
2073 | int cr; | |
2074 | int reg; | |
2075 | ||
2076 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
2077 | cr = exit_qualification & 15; | |
2078 | reg = (exit_qualification >> 8) & 15; | |
2079 | switch ((exit_qualification >> 4) & 3) { | |
2080 | case 0: /* mov to cr */ | |
2081 | switch (cr) { | |
2082 | case 0: | |
2083 | vcpu_load_rsp_rip(vcpu); | |
2084 | kvm_set_cr0(vcpu, vcpu->arch.regs[reg]); | |
2085 | skip_emulated_instruction(vcpu); | |
2086 | return 1; | |
2087 | case 3: | |
2088 | vcpu_load_rsp_rip(vcpu); | |
2089 | kvm_set_cr3(vcpu, vcpu->arch.regs[reg]); | |
2090 | skip_emulated_instruction(vcpu); | |
2091 | return 1; | |
2092 | case 4: | |
2093 | vcpu_load_rsp_rip(vcpu); | |
2094 | kvm_set_cr4(vcpu, vcpu->arch.regs[reg]); | |
2095 | skip_emulated_instruction(vcpu); | |
2096 | return 1; | |
2097 | case 8: | |
2098 | vcpu_load_rsp_rip(vcpu); | |
2099 | kvm_set_cr8(vcpu, vcpu->arch.regs[reg]); | |
2100 | skip_emulated_instruction(vcpu); | |
2101 | if (irqchip_in_kernel(vcpu->kvm)) | |
2102 | return 1; | |
2103 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; | |
2104 | return 0; | |
2105 | }; | |
2106 | break; | |
2107 | case 2: /* clts */ | |
2108 | vcpu_load_rsp_rip(vcpu); | |
2109 | vmx_fpu_deactivate(vcpu); | |
2110 | vcpu->arch.cr0 &= ~X86_CR0_TS; | |
2111 | vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0); | |
2112 | vmx_fpu_activate(vcpu); | |
2113 | skip_emulated_instruction(vcpu); | |
2114 | return 1; | |
2115 | case 1: /*mov from cr*/ | |
2116 | switch (cr) { | |
2117 | case 3: | |
2118 | vcpu_load_rsp_rip(vcpu); | |
2119 | vcpu->arch.regs[reg] = vcpu->arch.cr3; | |
2120 | vcpu_put_rsp_rip(vcpu); | |
2121 | skip_emulated_instruction(vcpu); | |
2122 | return 1; | |
2123 | case 8: | |
2124 | vcpu_load_rsp_rip(vcpu); | |
2125 | vcpu->arch.regs[reg] = kvm_get_cr8(vcpu); | |
2126 | vcpu_put_rsp_rip(vcpu); | |
2127 | skip_emulated_instruction(vcpu); | |
2128 | return 1; | |
2129 | } | |
2130 | break; | |
2131 | case 3: /* lmsw */ | |
2132 | kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f); | |
2133 | ||
2134 | skip_emulated_instruction(vcpu); | |
2135 | return 1; | |
2136 | default: | |
2137 | break; | |
2138 | } | |
2139 | kvm_run->exit_reason = 0; | |
2140 | pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n", | |
2141 | (int)(exit_qualification >> 4) & 3, cr); | |
2142 | return 0; | |
2143 | } | |
2144 | ||
2145 | static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2146 | { | |
2147 | unsigned long exit_qualification; | |
2148 | unsigned long val; | |
2149 | int dr, reg; | |
2150 | ||
2151 | /* | |
2152 | * FIXME: this code assumes the host is debugging the guest. | |
2153 | * need to deal with guest debugging itself too. | |
2154 | */ | |
2155 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
2156 | dr = exit_qualification & 7; | |
2157 | reg = (exit_qualification >> 8) & 15; | |
2158 | vcpu_load_rsp_rip(vcpu); | |
2159 | if (exit_qualification & 16) { | |
2160 | /* mov from dr */ | |
2161 | switch (dr) { | |
2162 | case 6: | |
2163 | val = 0xffff0ff0; | |
2164 | break; | |
2165 | case 7: | |
2166 | val = 0x400; | |
2167 | break; | |
2168 | default: | |
2169 | val = 0; | |
2170 | } | |
2171 | vcpu->arch.regs[reg] = val; | |
2172 | } else { | |
2173 | /* mov to dr */ | |
2174 | } | |
2175 | vcpu_put_rsp_rip(vcpu); | |
2176 | skip_emulated_instruction(vcpu); | |
2177 | return 1; | |
2178 | } | |
2179 | ||
2180 | static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2181 | { | |
2182 | kvm_emulate_cpuid(vcpu); | |
2183 | return 1; | |
2184 | } | |
2185 | ||
2186 | static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2187 | { | |
2188 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; | |
2189 | u64 data; | |
2190 | ||
2191 | if (vmx_get_msr(vcpu, ecx, &data)) { | |
2192 | kvm_inject_gp(vcpu, 0); | |
2193 | return 1; | |
2194 | } | |
2195 | ||
2196 | /* FIXME: handling of bits 32:63 of rax, rdx */ | |
2197 | vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u; | |
2198 | vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u; | |
2199 | skip_emulated_instruction(vcpu); | |
2200 | return 1; | |
2201 | } | |
2202 | ||
2203 | static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2204 | { | |
2205 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; | |
2206 | u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u) | |
2207 | | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32); | |
2208 | ||
2209 | if (vmx_set_msr(vcpu, ecx, data) != 0) { | |
2210 | kvm_inject_gp(vcpu, 0); | |
2211 | return 1; | |
2212 | } | |
2213 | ||
2214 | skip_emulated_instruction(vcpu); | |
2215 | return 1; | |
2216 | } | |
2217 | ||
2218 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu, | |
2219 | struct kvm_run *kvm_run) | |
2220 | { | |
2221 | return 1; | |
2222 | } | |
2223 | ||
2224 | static int handle_interrupt_window(struct kvm_vcpu *vcpu, | |
2225 | struct kvm_run *kvm_run) | |
2226 | { | |
2227 | u32 cpu_based_vm_exec_control; | |
2228 | ||
2229 | /* clear pending irq */ | |
2230 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2231 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
2232 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2233 | /* | |
2234 | * If the user space waits to inject interrupts, exit as soon as | |
2235 | * possible | |
2236 | */ | |
2237 | if (kvm_run->request_interrupt_window && | |
2238 | !vcpu->arch.irq_summary) { | |
2239 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; | |
2240 | ++vcpu->stat.irq_window_exits; | |
2241 | return 0; | |
2242 | } | |
2243 | return 1; | |
2244 | } | |
2245 | ||
2246 | static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2247 | { | |
2248 | skip_emulated_instruction(vcpu); | |
2249 | return kvm_emulate_halt(vcpu); | |
2250 | } | |
2251 | ||
2252 | static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2253 | { | |
2254 | skip_emulated_instruction(vcpu); | |
2255 | kvm_emulate_hypercall(vcpu); | |
2256 | return 1; | |
2257 | } | |
2258 | ||
2259 | static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2260 | { | |
2261 | skip_emulated_instruction(vcpu); | |
2262 | /* TODO: Add support for VT-d/pass-through device */ | |
2263 | return 1; | |
2264 | } | |
2265 | ||
2266 | static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2267 | { | |
2268 | u64 exit_qualification; | |
2269 | enum emulation_result er; | |
2270 | unsigned long offset; | |
2271 | ||
2272 | exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | |
2273 | offset = exit_qualification & 0xffful; | |
2274 | ||
2275 | er = emulate_instruction(vcpu, kvm_run, 0, 0, 0); | |
2276 | ||
2277 | if (er != EMULATE_DONE) { | |
2278 | printk(KERN_ERR | |
2279 | "Fail to handle apic access vmexit! Offset is 0x%lx\n", | |
2280 | offset); | |
2281 | return -ENOTSUPP; | |
2282 | } | |
2283 | return 1; | |
2284 | } | |
2285 | ||
2286 | static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2287 | { | |
2288 | unsigned long exit_qualification; | |
2289 | u16 tss_selector; | |
2290 | int reason; | |
2291 | ||
2292 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
2293 | ||
2294 | reason = (u32)exit_qualification >> 30; | |
2295 | tss_selector = exit_qualification; | |
2296 | ||
2297 | return kvm_task_switch(vcpu, tss_selector, reason); | |
2298 | } | |
2299 | ||
2300 | /* | |
2301 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
2302 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
2303 | * to be done to userspace and return 0. | |
2304 | */ | |
2305 | static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu, | |
2306 | struct kvm_run *kvm_run) = { | |
2307 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, | |
2308 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
2309 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, | |
2310 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, | |
2311 | [EXIT_REASON_CR_ACCESS] = handle_cr, | |
2312 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
2313 | [EXIT_REASON_CPUID] = handle_cpuid, | |
2314 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
2315 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
2316 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
2317 | [EXIT_REASON_HLT] = handle_halt, | |
2318 | [EXIT_REASON_VMCALL] = handle_vmcall, | |
2319 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, | |
2320 | [EXIT_REASON_APIC_ACCESS] = handle_apic_access, | |
2321 | [EXIT_REASON_WBINVD] = handle_wbinvd, | |
2322 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, | |
2323 | }; | |
2324 | ||
2325 | static const int kvm_vmx_max_exit_handlers = | |
2326 | ARRAY_SIZE(kvm_vmx_exit_handlers); | |
2327 | ||
2328 | /* | |
2329 | * The guest has exited. See if we can fix it or if we need userspace | |
2330 | * assistance. | |
2331 | */ | |
2332 | static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) | |
2333 | { | |
2334 | u32 exit_reason = vmcs_read32(VM_EXIT_REASON); | |
2335 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
2336 | u32 vectoring_info = vmx->idt_vectoring_info; | |
2337 | ||
2338 | if (unlikely(vmx->fail)) { | |
2339 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
2340 | kvm_run->fail_entry.hardware_entry_failure_reason | |
2341 | = vmcs_read32(VM_INSTRUCTION_ERROR); | |
2342 | return 0; | |
2343 | } | |
2344 | ||
2345 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && | |
2346 | exit_reason != EXIT_REASON_EXCEPTION_NMI) | |
2347 | printk(KERN_WARNING "%s: unexpected, valid vectoring info and " | |
2348 | "exit reason is 0x%x\n", __func__, exit_reason); | |
2349 | if (exit_reason < kvm_vmx_max_exit_handlers | |
2350 | && kvm_vmx_exit_handlers[exit_reason]) | |
2351 | return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run); | |
2352 | else { | |
2353 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
2354 | kvm_run->hw.hardware_exit_reason = exit_reason; | |
2355 | } | |
2356 | return 0; | |
2357 | } | |
2358 | ||
2359 | static void update_tpr_threshold(struct kvm_vcpu *vcpu) | |
2360 | { | |
2361 | int max_irr, tpr; | |
2362 | ||
2363 | if (!vm_need_tpr_shadow(vcpu->kvm)) | |
2364 | return; | |
2365 | ||
2366 | if (!kvm_lapic_enabled(vcpu) || | |
2367 | ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) { | |
2368 | vmcs_write32(TPR_THRESHOLD, 0); | |
2369 | return; | |
2370 | } | |
2371 | ||
2372 | tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4; | |
2373 | vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4); | |
2374 | } | |
2375 | ||
2376 | static void enable_irq_window(struct kvm_vcpu *vcpu) | |
2377 | { | |
2378 | u32 cpu_based_vm_exec_control; | |
2379 | ||
2380 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2381 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; | |
2382 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2383 | } | |
2384 | ||
2385 | static void vmx_intr_assist(struct kvm_vcpu *vcpu) | |
2386 | { | |
2387 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
2388 | u32 idtv_info_field, intr_info_field; | |
2389 | int has_ext_irq, interrupt_window_open; | |
2390 | int vector; | |
2391 | ||
2392 | update_tpr_threshold(vcpu); | |
2393 | ||
2394 | has_ext_irq = kvm_cpu_has_interrupt(vcpu); | |
2395 | intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD); | |
2396 | idtv_info_field = vmx->idt_vectoring_info; | |
2397 | if (intr_info_field & INTR_INFO_VALID_MASK) { | |
2398 | if (idtv_info_field & INTR_INFO_VALID_MASK) { | |
2399 | /* TODO: fault when IDT_Vectoring */ | |
2400 | if (printk_ratelimit()) | |
2401 | printk(KERN_ERR "Fault when IDT_Vectoring\n"); | |
2402 | } | |
2403 | if (has_ext_irq) | |
2404 | enable_irq_window(vcpu); | |
2405 | return; | |
2406 | } | |
2407 | if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) { | |
2408 | if ((idtv_info_field & VECTORING_INFO_TYPE_MASK) | |
2409 | == INTR_TYPE_EXT_INTR | |
2410 | && vcpu->arch.rmode.active) { | |
2411 | u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK; | |
2412 | ||
2413 | vmx_inject_irq(vcpu, vect); | |
2414 | if (unlikely(has_ext_irq)) | |
2415 | enable_irq_window(vcpu); | |
2416 | return; | |
2417 | } | |
2418 | ||
2419 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field); | |
2420 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
2421 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); | |
2422 | ||
2423 | if (unlikely(idtv_info_field & INTR_INFO_DELIVER_CODE_MASK)) | |
2424 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, | |
2425 | vmcs_read32(IDT_VECTORING_ERROR_CODE)); | |
2426 | if (unlikely(has_ext_irq)) | |
2427 | enable_irq_window(vcpu); | |
2428 | return; | |
2429 | } | |
2430 | if (!has_ext_irq) | |
2431 | return; | |
2432 | interrupt_window_open = | |
2433 | ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && | |
2434 | (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0); | |
2435 | if (interrupt_window_open) { | |
2436 | vector = kvm_cpu_get_interrupt(vcpu); | |
2437 | vmx_inject_irq(vcpu, vector); | |
2438 | kvm_timer_intr_post(vcpu, vector); | |
2439 | } else | |
2440 | enable_irq_window(vcpu); | |
2441 | } | |
2442 | ||
2443 | /* | |
2444 | * Failure to inject an interrupt should give us the information | |
2445 | * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs | |
2446 | * when fetching the interrupt redirection bitmap in the real-mode | |
2447 | * tss, this doesn't happen. So we do it ourselves. | |
2448 | */ | |
2449 | static void fixup_rmode_irq(struct vcpu_vmx *vmx) | |
2450 | { | |
2451 | vmx->rmode.irq.pending = 0; | |
2452 | if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip) | |
2453 | return; | |
2454 | vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip); | |
2455 | if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) { | |
2456 | vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK; | |
2457 | vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR; | |
2458 | return; | |
2459 | } | |
2460 | vmx->idt_vectoring_info = | |
2461 | VECTORING_INFO_VALID_MASK | |
2462 | | INTR_TYPE_EXT_INTR | |
2463 | | vmx->rmode.irq.vector; | |
2464 | } | |
2465 | ||
2466 | static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2467 | { | |
2468 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
2469 | u32 intr_info; | |
2470 | ||
2471 | /* | |
2472 | * Loading guest fpu may have cleared host cr0.ts | |
2473 | */ | |
2474 | vmcs_writel(HOST_CR0, read_cr0()); | |
2475 | ||
2476 | asm( | |
2477 | /* Store host registers */ | |
2478 | #ifdef CONFIG_X86_64 | |
2479 | "push %%rdx; push %%rbp;" | |
2480 | "push %%rcx \n\t" | |
2481 | #else | |
2482 | "push %%edx; push %%ebp;" | |
2483 | "push %%ecx \n\t" | |
2484 | #endif | |
2485 | ASM_VMX_VMWRITE_RSP_RDX "\n\t" | |
2486 | /* Check if vmlaunch of vmresume is needed */ | |
2487 | "cmpl $0, %c[launched](%0) \n\t" | |
2488 | /* Load guest registers. Don't clobber flags. */ | |
2489 | #ifdef CONFIG_X86_64 | |
2490 | "mov %c[cr2](%0), %%rax \n\t" | |
2491 | "mov %%rax, %%cr2 \n\t" | |
2492 | "mov %c[rax](%0), %%rax \n\t" | |
2493 | "mov %c[rbx](%0), %%rbx \n\t" | |
2494 | "mov %c[rdx](%0), %%rdx \n\t" | |
2495 | "mov %c[rsi](%0), %%rsi \n\t" | |
2496 | "mov %c[rdi](%0), %%rdi \n\t" | |
2497 | "mov %c[rbp](%0), %%rbp \n\t" | |
2498 | "mov %c[r8](%0), %%r8 \n\t" | |
2499 | "mov %c[r9](%0), %%r9 \n\t" | |
2500 | "mov %c[r10](%0), %%r10 \n\t" | |
2501 | "mov %c[r11](%0), %%r11 \n\t" | |
2502 | "mov %c[r12](%0), %%r12 \n\t" | |
2503 | "mov %c[r13](%0), %%r13 \n\t" | |
2504 | "mov %c[r14](%0), %%r14 \n\t" | |
2505 | "mov %c[r15](%0), %%r15 \n\t" | |
2506 | "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */ | |
2507 | #else | |
2508 | "mov %c[cr2](%0), %%eax \n\t" | |
2509 | "mov %%eax, %%cr2 \n\t" | |
2510 | "mov %c[rax](%0), %%eax \n\t" | |
2511 | "mov %c[rbx](%0), %%ebx \n\t" | |
2512 | "mov %c[rdx](%0), %%edx \n\t" | |
2513 | "mov %c[rsi](%0), %%esi \n\t" | |
2514 | "mov %c[rdi](%0), %%edi \n\t" | |
2515 | "mov %c[rbp](%0), %%ebp \n\t" | |
2516 | "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */ | |
2517 | #endif | |
2518 | /* Enter guest mode */ | |
2519 | "jne .Llaunched \n\t" | |
2520 | ASM_VMX_VMLAUNCH "\n\t" | |
2521 | "jmp .Lkvm_vmx_return \n\t" | |
2522 | ".Llaunched: " ASM_VMX_VMRESUME "\n\t" | |
2523 | ".Lkvm_vmx_return: " | |
2524 | /* Save guest registers, load host registers, keep flags */ | |
2525 | #ifdef CONFIG_X86_64 | |
2526 | "xchg %0, (%%rsp) \n\t" | |
2527 | "mov %%rax, %c[rax](%0) \n\t" | |
2528 | "mov %%rbx, %c[rbx](%0) \n\t" | |
2529 | "pushq (%%rsp); popq %c[rcx](%0) \n\t" | |
2530 | "mov %%rdx, %c[rdx](%0) \n\t" | |
2531 | "mov %%rsi, %c[rsi](%0) \n\t" | |
2532 | "mov %%rdi, %c[rdi](%0) \n\t" | |
2533 | "mov %%rbp, %c[rbp](%0) \n\t" | |
2534 | "mov %%r8, %c[r8](%0) \n\t" | |
2535 | "mov %%r9, %c[r9](%0) \n\t" | |
2536 | "mov %%r10, %c[r10](%0) \n\t" | |
2537 | "mov %%r11, %c[r11](%0) \n\t" | |
2538 | "mov %%r12, %c[r12](%0) \n\t" | |
2539 | "mov %%r13, %c[r13](%0) \n\t" | |
2540 | "mov %%r14, %c[r14](%0) \n\t" | |
2541 | "mov %%r15, %c[r15](%0) \n\t" | |
2542 | "mov %%cr2, %%rax \n\t" | |
2543 | "mov %%rax, %c[cr2](%0) \n\t" | |
2544 | ||
2545 | "pop %%rbp; pop %%rbp; pop %%rdx \n\t" | |
2546 | #else | |
2547 | "xchg %0, (%%esp) \n\t" | |
2548 | "mov %%eax, %c[rax](%0) \n\t" | |
2549 | "mov %%ebx, %c[rbx](%0) \n\t" | |
2550 | "pushl (%%esp); popl %c[rcx](%0) \n\t" | |
2551 | "mov %%edx, %c[rdx](%0) \n\t" | |
2552 | "mov %%esi, %c[rsi](%0) \n\t" | |
2553 | "mov %%edi, %c[rdi](%0) \n\t" | |
2554 | "mov %%ebp, %c[rbp](%0) \n\t" | |
2555 | "mov %%cr2, %%eax \n\t" | |
2556 | "mov %%eax, %c[cr2](%0) \n\t" | |
2557 | ||
2558 | "pop %%ebp; pop %%ebp; pop %%edx \n\t" | |
2559 | #endif | |
2560 | "setbe %c[fail](%0) \n\t" | |
2561 | : : "c"(vmx), "d"((unsigned long)HOST_RSP), | |
2562 | [launched]"i"(offsetof(struct vcpu_vmx, launched)), | |
2563 | [fail]"i"(offsetof(struct vcpu_vmx, fail)), | |
2564 | [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])), | |
2565 | [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])), | |
2566 | [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])), | |
2567 | [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])), | |
2568 | [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])), | |
2569 | [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])), | |
2570 | [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])), | |
2571 | #ifdef CONFIG_X86_64 | |
2572 | [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])), | |
2573 | [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])), | |
2574 | [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])), | |
2575 | [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])), | |
2576 | [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])), | |
2577 | [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])), | |
2578 | [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])), | |
2579 | [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])), | |
2580 | #endif | |
2581 | [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)) | |
2582 | : "cc", "memory" | |
2583 | #ifdef CONFIG_X86_64 | |
2584 | , "rbx", "rdi", "rsi" | |
2585 | , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
2586 | #else | |
2587 | , "ebx", "edi", "rsi" | |
2588 | #endif | |
2589 | ); | |
2590 | ||
2591 | vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); | |
2592 | if (vmx->rmode.irq.pending) | |
2593 | fixup_rmode_irq(vmx); | |
2594 | ||
2595 | vcpu->arch.interrupt_window_open = | |
2596 | (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0; | |
2597 | ||
2598 | asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS)); | |
2599 | vmx->launched = 1; | |
2600 | ||
2601 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
2602 | ||
2603 | /* We need to handle NMIs before interrupts are enabled */ | |
2604 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */ | |
2605 | asm("int $2"); | |
2606 | } | |
2607 | ||
2608 | static void vmx_free_vmcs(struct kvm_vcpu *vcpu) | |
2609 | { | |
2610 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
2611 | ||
2612 | if (vmx->vmcs) { | |
2613 | on_each_cpu(__vcpu_clear, vmx, 0, 1); | |
2614 | free_vmcs(vmx->vmcs); | |
2615 | vmx->vmcs = NULL; | |
2616 | } | |
2617 | } | |
2618 | ||
2619 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) | |
2620 | { | |
2621 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
2622 | ||
2623 | spin_lock(&vmx_vpid_lock); | |
2624 | if (vmx->vpid != 0) | |
2625 | __clear_bit(vmx->vpid, vmx_vpid_bitmap); | |
2626 | spin_unlock(&vmx_vpid_lock); | |
2627 | vmx_free_vmcs(vcpu); | |
2628 | kfree(vmx->host_msrs); | |
2629 | kfree(vmx->guest_msrs); | |
2630 | kvm_vcpu_uninit(vcpu); | |
2631 | kmem_cache_free(kvm_vcpu_cache, vmx); | |
2632 | } | |
2633 | ||
2634 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) | |
2635 | { | |
2636 | int err; | |
2637 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); | |
2638 | int cpu; | |
2639 | ||
2640 | if (!vmx) | |
2641 | return ERR_PTR(-ENOMEM); | |
2642 | ||
2643 | allocate_vpid(vmx); | |
2644 | ||
2645 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); | |
2646 | if (err) | |
2647 | goto free_vcpu; | |
2648 | ||
2649 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); | |
2650 | if (!vmx->guest_msrs) { | |
2651 | err = -ENOMEM; | |
2652 | goto uninit_vcpu; | |
2653 | } | |
2654 | ||
2655 | vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); | |
2656 | if (!vmx->host_msrs) | |
2657 | goto free_guest_msrs; | |
2658 | ||
2659 | vmx->vmcs = alloc_vmcs(); | |
2660 | if (!vmx->vmcs) | |
2661 | goto free_msrs; | |
2662 | ||
2663 | vmcs_clear(vmx->vmcs); | |
2664 | ||
2665 | cpu = get_cpu(); | |
2666 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
2667 | err = vmx_vcpu_setup(vmx); | |
2668 | vmx_vcpu_put(&vmx->vcpu); | |
2669 | put_cpu(); | |
2670 | if (err) | |
2671 | goto free_vmcs; | |
2672 | if (vm_need_virtualize_apic_accesses(kvm)) | |
2673 | if (alloc_apic_access_page(kvm) != 0) | |
2674 | goto free_vmcs; | |
2675 | ||
2676 | return &vmx->vcpu; | |
2677 | ||
2678 | free_vmcs: | |
2679 | free_vmcs(vmx->vmcs); | |
2680 | free_msrs: | |
2681 | kfree(vmx->host_msrs); | |
2682 | free_guest_msrs: | |
2683 | kfree(vmx->guest_msrs); | |
2684 | uninit_vcpu: | |
2685 | kvm_vcpu_uninit(&vmx->vcpu); | |
2686 | free_vcpu: | |
2687 | kmem_cache_free(kvm_vcpu_cache, vmx); | |
2688 | return ERR_PTR(err); | |
2689 | } | |
2690 | ||
2691 | static void __init vmx_check_processor_compat(void *rtn) | |
2692 | { | |
2693 | struct vmcs_config vmcs_conf; | |
2694 | ||
2695 | *(int *)rtn = 0; | |
2696 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
2697 | *(int *)rtn = -EIO; | |
2698 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { | |
2699 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
2700 | smp_processor_id()); | |
2701 | *(int *)rtn = -EIO; | |
2702 | } | |
2703 | } | |
2704 | ||
2705 | static struct kvm_x86_ops vmx_x86_ops = { | |
2706 | .cpu_has_kvm_support = cpu_has_kvm_support, | |
2707 | .disabled_by_bios = vmx_disabled_by_bios, | |
2708 | .hardware_setup = hardware_setup, | |
2709 | .hardware_unsetup = hardware_unsetup, | |
2710 | .check_processor_compatibility = vmx_check_processor_compat, | |
2711 | .hardware_enable = hardware_enable, | |
2712 | .hardware_disable = hardware_disable, | |
2713 | .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses, | |
2714 | ||
2715 | .vcpu_create = vmx_create_vcpu, | |
2716 | .vcpu_free = vmx_free_vcpu, | |
2717 | .vcpu_reset = vmx_vcpu_reset, | |
2718 | ||
2719 | .prepare_guest_switch = vmx_save_host_state, | |
2720 | .vcpu_load = vmx_vcpu_load, | |
2721 | .vcpu_put = vmx_vcpu_put, | |
2722 | .vcpu_decache = vmx_vcpu_decache, | |
2723 | ||
2724 | .set_guest_debug = set_guest_debug, | |
2725 | .guest_debug_pre = kvm_guest_debug_pre, | |
2726 | .get_msr = vmx_get_msr, | |
2727 | .set_msr = vmx_set_msr, | |
2728 | .get_segment_base = vmx_get_segment_base, | |
2729 | .get_segment = vmx_get_segment, | |
2730 | .set_segment = vmx_set_segment, | |
2731 | .get_cpl = vmx_get_cpl, | |
2732 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, | |
2733 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, | |
2734 | .set_cr0 = vmx_set_cr0, | |
2735 | .set_cr3 = vmx_set_cr3, | |
2736 | .set_cr4 = vmx_set_cr4, | |
2737 | .set_efer = vmx_set_efer, | |
2738 | .get_idt = vmx_get_idt, | |
2739 | .set_idt = vmx_set_idt, | |
2740 | .get_gdt = vmx_get_gdt, | |
2741 | .set_gdt = vmx_set_gdt, | |
2742 | .cache_regs = vcpu_load_rsp_rip, | |
2743 | .decache_regs = vcpu_put_rsp_rip, | |
2744 | .get_rflags = vmx_get_rflags, | |
2745 | .set_rflags = vmx_set_rflags, | |
2746 | ||
2747 | .tlb_flush = vmx_flush_tlb, | |
2748 | ||
2749 | .run = vmx_vcpu_run, | |
2750 | .handle_exit = kvm_handle_exit, | |
2751 | .skip_emulated_instruction = skip_emulated_instruction, | |
2752 | .patch_hypercall = vmx_patch_hypercall, | |
2753 | .get_irq = vmx_get_irq, | |
2754 | .set_irq = vmx_inject_irq, | |
2755 | .queue_exception = vmx_queue_exception, | |
2756 | .exception_injected = vmx_exception_injected, | |
2757 | .inject_pending_irq = vmx_intr_assist, | |
2758 | .inject_pending_vectors = do_interrupt_requests, | |
2759 | ||
2760 | .set_tss_addr = vmx_set_tss_addr, | |
2761 | }; | |
2762 | ||
2763 | static int __init vmx_init(void) | |
2764 | { | |
2765 | void *va; | |
2766 | int r; | |
2767 | ||
2768 | vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); | |
2769 | if (!vmx_io_bitmap_a) | |
2770 | return -ENOMEM; | |
2771 | ||
2772 | vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); | |
2773 | if (!vmx_io_bitmap_b) { | |
2774 | r = -ENOMEM; | |
2775 | goto out; | |
2776 | } | |
2777 | ||
2778 | vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); | |
2779 | if (!vmx_msr_bitmap) { | |
2780 | r = -ENOMEM; | |
2781 | goto out1; | |
2782 | } | |
2783 | ||
2784 | /* | |
2785 | * Allow direct access to the PC debug port (it is often used for I/O | |
2786 | * delays, but the vmexits simply slow things down). | |
2787 | */ | |
2788 | va = kmap(vmx_io_bitmap_a); | |
2789 | memset(va, 0xff, PAGE_SIZE); | |
2790 | clear_bit(0x80, va); | |
2791 | kunmap(vmx_io_bitmap_a); | |
2792 | ||
2793 | va = kmap(vmx_io_bitmap_b); | |
2794 | memset(va, 0xff, PAGE_SIZE); | |
2795 | kunmap(vmx_io_bitmap_b); | |
2796 | ||
2797 | va = kmap(vmx_msr_bitmap); | |
2798 | memset(va, 0xff, PAGE_SIZE); | |
2799 | kunmap(vmx_msr_bitmap); | |
2800 | ||
2801 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ | |
2802 | ||
2803 | r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE); | |
2804 | if (r) | |
2805 | goto out2; | |
2806 | ||
2807 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE); | |
2808 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE); | |
2809 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS); | |
2810 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP); | |
2811 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP); | |
2812 | ||
2813 | if (bypass_guest_pf) | |
2814 | kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull); | |
2815 | ||
2816 | return 0; | |
2817 | ||
2818 | out2: | |
2819 | __free_page(vmx_msr_bitmap); | |
2820 | out1: | |
2821 | __free_page(vmx_io_bitmap_b); | |
2822 | out: | |
2823 | __free_page(vmx_io_bitmap_a); | |
2824 | return r; | |
2825 | } | |
2826 | ||
2827 | static void __exit vmx_exit(void) | |
2828 | { | |
2829 | __free_page(vmx_msr_bitmap); | |
2830 | __free_page(vmx_io_bitmap_b); | |
2831 | __free_page(vmx_io_bitmap_a); | |
2832 | ||
2833 | kvm_exit(); | |
2834 | } | |
2835 | ||
2836 | module_init(vmx_init) | |
2837 | module_exit(vmx_exit) |