]>
Commit | Line | Data |
---|---|---|
1 | /* | |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * derived from drivers/kvm/kvm_main.c | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * Copyright (C) 2008 Qumranet, Inc. | |
8 | * Copyright IBM Corporation, 2008 | |
9 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. | |
10 | * | |
11 | * Authors: | |
12 | * Avi Kivity <avi@qumranet.com> | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Amit Shah <amit.shah@qumranet.com> | |
15 | * Ben-Ami Yassour <benami@il.ibm.com> | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <linux/kvm_host.h> | |
23 | #include "irq.h" | |
24 | #include "mmu.h" | |
25 | #include "i8254.h" | |
26 | #include "tss.h" | |
27 | #include "kvm_cache_regs.h" | |
28 | #include "x86.h" | |
29 | #include "cpuid.h" | |
30 | ||
31 | #include <linux/clocksource.h> | |
32 | #include <linux/interrupt.h> | |
33 | #include <linux/kvm.h> | |
34 | #include <linux/fs.h> | |
35 | #include <linux/vmalloc.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/mman.h> | |
38 | #include <linux/highmem.h> | |
39 | #include <linux/iommu.h> | |
40 | #include <linux/intel-iommu.h> | |
41 | #include <linux/cpufreq.h> | |
42 | #include <linux/user-return-notifier.h> | |
43 | #include <linux/srcu.h> | |
44 | #include <linux/slab.h> | |
45 | #include <linux/perf_event.h> | |
46 | #include <linux/uaccess.h> | |
47 | #include <linux/hash.h> | |
48 | #include <linux/pci.h> | |
49 | #include <linux/timekeeper_internal.h> | |
50 | #include <linux/pvclock_gtod.h> | |
51 | #include <trace/events/kvm.h> | |
52 | ||
53 | #define CREATE_TRACE_POINTS | |
54 | #include "trace.h" | |
55 | ||
56 | #include <asm/debugreg.h> | |
57 | #include <asm/msr.h> | |
58 | #include <asm/desc.h> | |
59 | #include <asm/mtrr.h> | |
60 | #include <asm/mce.h> | |
61 | #include <asm/i387.h> | |
62 | #include <asm/fpu-internal.h> /* Ugh! */ | |
63 | #include <asm/xcr.h> | |
64 | #include <asm/pvclock.h> | |
65 | #include <asm/div64.h> | |
66 | ||
67 | #define MAX_IO_MSRS 256 | |
68 | #define KVM_MAX_MCE_BANKS 32 | |
69 | #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P) | |
70 | ||
71 | #define emul_to_vcpu(ctxt) \ | |
72 | container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) | |
73 | ||
74 | /* EFER defaults: | |
75 | * - enable syscall per default because its emulated by KVM | |
76 | * - enable LME and LMA per default on 64 bit KVM | |
77 | */ | |
78 | #ifdef CONFIG_X86_64 | |
79 | static | |
80 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
81 | #else | |
82 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); | |
83 | #endif | |
84 | ||
85 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM | |
86 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
87 | ||
88 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); | |
89 | static void process_nmi(struct kvm_vcpu *vcpu); | |
90 | ||
91 | struct kvm_x86_ops *kvm_x86_ops; | |
92 | EXPORT_SYMBOL_GPL(kvm_x86_ops); | |
93 | ||
94 | static bool ignore_msrs = 0; | |
95 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); | |
96 | ||
97 | bool kvm_has_tsc_control; | |
98 | EXPORT_SYMBOL_GPL(kvm_has_tsc_control); | |
99 | u32 kvm_max_guest_tsc_khz; | |
100 | EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); | |
101 | ||
102 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ | |
103 | static u32 tsc_tolerance_ppm = 250; | |
104 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); | |
105 | ||
106 | #define KVM_NR_SHARED_MSRS 16 | |
107 | ||
108 | struct kvm_shared_msrs_global { | |
109 | int nr; | |
110 | u32 msrs[KVM_NR_SHARED_MSRS]; | |
111 | }; | |
112 | ||
113 | struct kvm_shared_msrs { | |
114 | struct user_return_notifier urn; | |
115 | bool registered; | |
116 | struct kvm_shared_msr_values { | |
117 | u64 host; | |
118 | u64 curr; | |
119 | } values[KVM_NR_SHARED_MSRS]; | |
120 | }; | |
121 | ||
122 | static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; | |
123 | static struct kvm_shared_msrs __percpu *shared_msrs; | |
124 | ||
125 | struct kvm_stats_debugfs_item debugfs_entries[] = { | |
126 | { "pf_fixed", VCPU_STAT(pf_fixed) }, | |
127 | { "pf_guest", VCPU_STAT(pf_guest) }, | |
128 | { "tlb_flush", VCPU_STAT(tlb_flush) }, | |
129 | { "invlpg", VCPU_STAT(invlpg) }, | |
130 | { "exits", VCPU_STAT(exits) }, | |
131 | { "io_exits", VCPU_STAT(io_exits) }, | |
132 | { "mmio_exits", VCPU_STAT(mmio_exits) }, | |
133 | { "signal_exits", VCPU_STAT(signal_exits) }, | |
134 | { "irq_window", VCPU_STAT(irq_window_exits) }, | |
135 | { "nmi_window", VCPU_STAT(nmi_window_exits) }, | |
136 | { "halt_exits", VCPU_STAT(halt_exits) }, | |
137 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, | |
138 | { "hypercalls", VCPU_STAT(hypercalls) }, | |
139 | { "request_irq", VCPU_STAT(request_irq_exits) }, | |
140 | { "irq_exits", VCPU_STAT(irq_exits) }, | |
141 | { "host_state_reload", VCPU_STAT(host_state_reload) }, | |
142 | { "efer_reload", VCPU_STAT(efer_reload) }, | |
143 | { "fpu_reload", VCPU_STAT(fpu_reload) }, | |
144 | { "insn_emulation", VCPU_STAT(insn_emulation) }, | |
145 | { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, | |
146 | { "irq_injections", VCPU_STAT(irq_injections) }, | |
147 | { "nmi_injections", VCPU_STAT(nmi_injections) }, | |
148 | { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, | |
149 | { "mmu_pte_write", VM_STAT(mmu_pte_write) }, | |
150 | { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, | |
151 | { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, | |
152 | { "mmu_flooded", VM_STAT(mmu_flooded) }, | |
153 | { "mmu_recycled", VM_STAT(mmu_recycled) }, | |
154 | { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, | |
155 | { "mmu_unsync", VM_STAT(mmu_unsync) }, | |
156 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, | |
157 | { "largepages", VM_STAT(lpages) }, | |
158 | { NULL } | |
159 | }; | |
160 | ||
161 | u64 __read_mostly host_xcr0; | |
162 | ||
163 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); | |
164 | ||
165 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) | |
166 | { | |
167 | int i; | |
168 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) | |
169 | vcpu->arch.apf.gfns[i] = ~0; | |
170 | } | |
171 | ||
172 | static void kvm_on_user_return(struct user_return_notifier *urn) | |
173 | { | |
174 | unsigned slot; | |
175 | struct kvm_shared_msrs *locals | |
176 | = container_of(urn, struct kvm_shared_msrs, urn); | |
177 | struct kvm_shared_msr_values *values; | |
178 | ||
179 | for (slot = 0; slot < shared_msrs_global.nr; ++slot) { | |
180 | values = &locals->values[slot]; | |
181 | if (values->host != values->curr) { | |
182 | wrmsrl(shared_msrs_global.msrs[slot], values->host); | |
183 | values->curr = values->host; | |
184 | } | |
185 | } | |
186 | locals->registered = false; | |
187 | user_return_notifier_unregister(urn); | |
188 | } | |
189 | ||
190 | static void shared_msr_update(unsigned slot, u32 msr) | |
191 | { | |
192 | u64 value; | |
193 | unsigned int cpu = smp_processor_id(); | |
194 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
195 | ||
196 | /* only read, and nobody should modify it at this time, | |
197 | * so don't need lock */ | |
198 | if (slot >= shared_msrs_global.nr) { | |
199 | printk(KERN_ERR "kvm: invalid MSR slot!"); | |
200 | return; | |
201 | } | |
202 | rdmsrl_safe(msr, &value); | |
203 | smsr->values[slot].host = value; | |
204 | smsr->values[slot].curr = value; | |
205 | } | |
206 | ||
207 | void kvm_define_shared_msr(unsigned slot, u32 msr) | |
208 | { | |
209 | if (slot >= shared_msrs_global.nr) | |
210 | shared_msrs_global.nr = slot + 1; | |
211 | shared_msrs_global.msrs[slot] = msr; | |
212 | /* we need ensured the shared_msr_global have been updated */ | |
213 | smp_wmb(); | |
214 | } | |
215 | EXPORT_SYMBOL_GPL(kvm_define_shared_msr); | |
216 | ||
217 | static void kvm_shared_msr_cpu_online(void) | |
218 | { | |
219 | unsigned i; | |
220 | ||
221 | for (i = 0; i < shared_msrs_global.nr; ++i) | |
222 | shared_msr_update(i, shared_msrs_global.msrs[i]); | |
223 | } | |
224 | ||
225 | void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) | |
226 | { | |
227 | unsigned int cpu = smp_processor_id(); | |
228 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
229 | ||
230 | if (((value ^ smsr->values[slot].curr) & mask) == 0) | |
231 | return; | |
232 | smsr->values[slot].curr = value; | |
233 | wrmsrl(shared_msrs_global.msrs[slot], value); | |
234 | if (!smsr->registered) { | |
235 | smsr->urn.on_user_return = kvm_on_user_return; | |
236 | user_return_notifier_register(&smsr->urn); | |
237 | smsr->registered = true; | |
238 | } | |
239 | } | |
240 | EXPORT_SYMBOL_GPL(kvm_set_shared_msr); | |
241 | ||
242 | static void drop_user_return_notifiers(void *ignore) | |
243 | { | |
244 | unsigned int cpu = smp_processor_id(); | |
245 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
246 | ||
247 | if (smsr->registered) | |
248 | kvm_on_user_return(&smsr->urn); | |
249 | } | |
250 | ||
251 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) | |
252 | { | |
253 | return vcpu->arch.apic_base; | |
254 | } | |
255 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
256 | ||
257 | void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data) | |
258 | { | |
259 | /* TODO: reserve bits check */ | |
260 | kvm_lapic_set_base(vcpu, data); | |
261 | } | |
262 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
263 | ||
264 | asmlinkage void kvm_spurious_fault(void) | |
265 | { | |
266 | /* Fault while not rebooting. We want the trace. */ | |
267 | BUG(); | |
268 | } | |
269 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
270 | ||
271 | #define EXCPT_BENIGN 0 | |
272 | #define EXCPT_CONTRIBUTORY 1 | |
273 | #define EXCPT_PF 2 | |
274 | ||
275 | static int exception_class(int vector) | |
276 | { | |
277 | switch (vector) { | |
278 | case PF_VECTOR: | |
279 | return EXCPT_PF; | |
280 | case DE_VECTOR: | |
281 | case TS_VECTOR: | |
282 | case NP_VECTOR: | |
283 | case SS_VECTOR: | |
284 | case GP_VECTOR: | |
285 | return EXCPT_CONTRIBUTORY; | |
286 | default: | |
287 | break; | |
288 | } | |
289 | return EXCPT_BENIGN; | |
290 | } | |
291 | ||
292 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, | |
293 | unsigned nr, bool has_error, u32 error_code, | |
294 | bool reinject) | |
295 | { | |
296 | u32 prev_nr; | |
297 | int class1, class2; | |
298 | ||
299 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
300 | ||
301 | if (!vcpu->arch.exception.pending) { | |
302 | queue: | |
303 | vcpu->arch.exception.pending = true; | |
304 | vcpu->arch.exception.has_error_code = has_error; | |
305 | vcpu->arch.exception.nr = nr; | |
306 | vcpu->arch.exception.error_code = error_code; | |
307 | vcpu->arch.exception.reinject = reinject; | |
308 | return; | |
309 | } | |
310 | ||
311 | /* to check exception */ | |
312 | prev_nr = vcpu->arch.exception.nr; | |
313 | if (prev_nr == DF_VECTOR) { | |
314 | /* triple fault -> shutdown */ | |
315 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
316 | return; | |
317 | } | |
318 | class1 = exception_class(prev_nr); | |
319 | class2 = exception_class(nr); | |
320 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
321 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
322 | /* generate double fault per SDM Table 5-5 */ | |
323 | vcpu->arch.exception.pending = true; | |
324 | vcpu->arch.exception.has_error_code = true; | |
325 | vcpu->arch.exception.nr = DF_VECTOR; | |
326 | vcpu->arch.exception.error_code = 0; | |
327 | } else | |
328 | /* replace previous exception with a new one in a hope | |
329 | that instruction re-execution will regenerate lost | |
330 | exception */ | |
331 | goto queue; | |
332 | } | |
333 | ||
334 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) | |
335 | { | |
336 | kvm_multiple_exception(vcpu, nr, false, 0, false); | |
337 | } | |
338 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
339 | ||
340 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) | |
341 | { | |
342 | kvm_multiple_exception(vcpu, nr, false, 0, true); | |
343 | } | |
344 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
345 | ||
346 | void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) | |
347 | { | |
348 | if (err) | |
349 | kvm_inject_gp(vcpu, 0); | |
350 | else | |
351 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
352 | } | |
353 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
354 | ||
355 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) | |
356 | { | |
357 | ++vcpu->stat.pf_guest; | |
358 | vcpu->arch.cr2 = fault->address; | |
359 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); | |
360 | } | |
361 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); | |
362 | ||
363 | void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) | |
364 | { | |
365 | if (mmu_is_nested(vcpu) && !fault->nested_page_fault) | |
366 | vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); | |
367 | else | |
368 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); | |
369 | } | |
370 | ||
371 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) | |
372 | { | |
373 | atomic_inc(&vcpu->arch.nmi_queued); | |
374 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
375 | } | |
376 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
377 | ||
378 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) | |
379 | { | |
380 | kvm_multiple_exception(vcpu, nr, true, error_code, false); | |
381 | } | |
382 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
383 | ||
384 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) | |
385 | { | |
386 | kvm_multiple_exception(vcpu, nr, true, error_code, true); | |
387 | } | |
388 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
389 | ||
390 | /* | |
391 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
392 | * a #GP and return false. | |
393 | */ | |
394 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
395 | { | |
396 | if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) | |
397 | return true; | |
398 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
399 | return false; | |
400 | } | |
401 | EXPORT_SYMBOL_GPL(kvm_require_cpl); | |
402 | ||
403 | /* | |
404 | * This function will be used to read from the physical memory of the currently | |
405 | * running guest. The difference to kvm_read_guest_page is that this function | |
406 | * can read from guest physical or from the guest's guest physical memory. | |
407 | */ | |
408 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
409 | gfn_t ngfn, void *data, int offset, int len, | |
410 | u32 access) | |
411 | { | |
412 | gfn_t real_gfn; | |
413 | gpa_t ngpa; | |
414 | ||
415 | ngpa = gfn_to_gpa(ngfn); | |
416 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access); | |
417 | if (real_gfn == UNMAPPED_GVA) | |
418 | return -EFAULT; | |
419 | ||
420 | real_gfn = gpa_to_gfn(real_gfn); | |
421 | ||
422 | return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len); | |
423 | } | |
424 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
425 | ||
426 | int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, | |
427 | void *data, int offset, int len, u32 access) | |
428 | { | |
429 | return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, | |
430 | data, offset, len, access); | |
431 | } | |
432 | ||
433 | /* | |
434 | * Load the pae pdptrs. Return true is they are all valid. | |
435 | */ | |
436 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) | |
437 | { | |
438 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
439 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
440 | int i; | |
441 | int ret; | |
442 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; | |
443 | ||
444 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, | |
445 | offset * sizeof(u64), sizeof(pdpte), | |
446 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
447 | if (ret < 0) { | |
448 | ret = 0; | |
449 | goto out; | |
450 | } | |
451 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
452 | if (is_present_gpte(pdpte[i]) && | |
453 | (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) { | |
454 | ret = 0; | |
455 | goto out; | |
456 | } | |
457 | } | |
458 | ret = 1; | |
459 | ||
460 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); | |
461 | __set_bit(VCPU_EXREG_PDPTR, | |
462 | (unsigned long *)&vcpu->arch.regs_avail); | |
463 | __set_bit(VCPU_EXREG_PDPTR, | |
464 | (unsigned long *)&vcpu->arch.regs_dirty); | |
465 | out: | |
466 | ||
467 | return ret; | |
468 | } | |
469 | EXPORT_SYMBOL_GPL(load_pdptrs); | |
470 | ||
471 | static bool pdptrs_changed(struct kvm_vcpu *vcpu) | |
472 | { | |
473 | u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; | |
474 | bool changed = true; | |
475 | int offset; | |
476 | gfn_t gfn; | |
477 | int r; | |
478 | ||
479 | if (is_long_mode(vcpu) || !is_pae(vcpu)) | |
480 | return false; | |
481 | ||
482 | if (!test_bit(VCPU_EXREG_PDPTR, | |
483 | (unsigned long *)&vcpu->arch.regs_avail)) | |
484 | return true; | |
485 | ||
486 | gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; | |
487 | offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); | |
488 | r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), | |
489 | PFERR_USER_MASK | PFERR_WRITE_MASK); | |
490 | if (r < 0) | |
491 | goto out; | |
492 | changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; | |
493 | out: | |
494 | ||
495 | return changed; | |
496 | } | |
497 | ||
498 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) | |
499 | { | |
500 | unsigned long old_cr0 = kvm_read_cr0(vcpu); | |
501 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP | | |
502 | X86_CR0_CD | X86_CR0_NW; | |
503 | ||
504 | cr0 |= X86_CR0_ET; | |
505 | ||
506 | #ifdef CONFIG_X86_64 | |
507 | if (cr0 & 0xffffffff00000000UL) | |
508 | return 1; | |
509 | #endif | |
510 | ||
511 | cr0 &= ~CR0_RESERVED_BITS; | |
512 | ||
513 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) | |
514 | return 1; | |
515 | ||
516 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) | |
517 | return 1; | |
518 | ||
519 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
520 | #ifdef CONFIG_X86_64 | |
521 | if ((vcpu->arch.efer & EFER_LME)) { | |
522 | int cs_db, cs_l; | |
523 | ||
524 | if (!is_pae(vcpu)) | |
525 | return 1; | |
526 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
527 | if (cs_l) | |
528 | return 1; | |
529 | } else | |
530 | #endif | |
531 | if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, | |
532 | kvm_read_cr3(vcpu))) | |
533 | return 1; | |
534 | } | |
535 | ||
536 | if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) | |
537 | return 1; | |
538 | ||
539 | kvm_x86_ops->set_cr0(vcpu, cr0); | |
540 | ||
541 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { | |
542 | kvm_clear_async_pf_completion_queue(vcpu); | |
543 | kvm_async_pf_hash_reset(vcpu); | |
544 | } | |
545 | ||
546 | if ((cr0 ^ old_cr0) & update_bits) | |
547 | kvm_mmu_reset_context(vcpu); | |
548 | return 0; | |
549 | } | |
550 | EXPORT_SYMBOL_GPL(kvm_set_cr0); | |
551 | ||
552 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) | |
553 | { | |
554 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); | |
555 | } | |
556 | EXPORT_SYMBOL_GPL(kvm_lmsw); | |
557 | ||
558 | static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) | |
559 | { | |
560 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && | |
561 | !vcpu->guest_xcr0_loaded) { | |
562 | /* kvm_set_xcr() also depends on this */ | |
563 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
564 | vcpu->guest_xcr0_loaded = 1; | |
565 | } | |
566 | } | |
567 | ||
568 | static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) | |
569 | { | |
570 | if (vcpu->guest_xcr0_loaded) { | |
571 | if (vcpu->arch.xcr0 != host_xcr0) | |
572 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
573 | vcpu->guest_xcr0_loaded = 0; | |
574 | } | |
575 | } | |
576 | ||
577 | int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) | |
578 | { | |
579 | u64 xcr0; | |
580 | u64 valid_bits; | |
581 | ||
582 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
583 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
584 | return 1; | |
585 | xcr0 = xcr; | |
586 | if (!(xcr0 & XSTATE_FP)) | |
587 | return 1; | |
588 | if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE)) | |
589 | return 1; | |
590 | ||
591 | /* | |
592 | * Do not allow the guest to set bits that we do not support | |
593 | * saving. However, xcr0 bit 0 is always set, even if the | |
594 | * emulated CPU does not support XSAVE (see fx_init). | |
595 | */ | |
596 | valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP; | |
597 | if (xcr0 & ~valid_bits) | |
598 | return 1; | |
599 | ||
600 | kvm_put_guest_xcr0(vcpu); | |
601 | vcpu->arch.xcr0 = xcr0; | |
602 | return 0; | |
603 | } | |
604 | ||
605 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) | |
606 | { | |
607 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || | |
608 | __kvm_set_xcr(vcpu, index, xcr)) { | |
609 | kvm_inject_gp(vcpu, 0); | |
610 | return 1; | |
611 | } | |
612 | return 0; | |
613 | } | |
614 | EXPORT_SYMBOL_GPL(kvm_set_xcr); | |
615 | ||
616 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
617 | { | |
618 | unsigned long old_cr4 = kvm_read_cr4(vcpu); | |
619 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | | |
620 | X86_CR4_PAE | X86_CR4_SMEP; | |
621 | if (cr4 & CR4_RESERVED_BITS) | |
622 | return 1; | |
623 | ||
624 | if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) | |
625 | return 1; | |
626 | ||
627 | if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP)) | |
628 | return 1; | |
629 | ||
630 | if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE)) | |
631 | return 1; | |
632 | ||
633 | if (is_long_mode(vcpu)) { | |
634 | if (!(cr4 & X86_CR4_PAE)) | |
635 | return 1; | |
636 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) | |
637 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
638 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, | |
639 | kvm_read_cr3(vcpu))) | |
640 | return 1; | |
641 | ||
642 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { | |
643 | if (!guest_cpuid_has_pcid(vcpu)) | |
644 | return 1; | |
645 | ||
646 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ | |
647 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
648 | return 1; | |
649 | } | |
650 | ||
651 | if (kvm_x86_ops->set_cr4(vcpu, cr4)) | |
652 | return 1; | |
653 | ||
654 | if (((cr4 ^ old_cr4) & pdptr_bits) || | |
655 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) | |
656 | kvm_mmu_reset_context(vcpu); | |
657 | ||
658 | if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE) | |
659 | kvm_update_cpuid(vcpu); | |
660 | ||
661 | return 0; | |
662 | } | |
663 | EXPORT_SYMBOL_GPL(kvm_set_cr4); | |
664 | ||
665 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) | |
666 | { | |
667 | if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { | |
668 | kvm_mmu_sync_roots(vcpu); | |
669 | kvm_mmu_flush_tlb(vcpu); | |
670 | return 0; | |
671 | } | |
672 | ||
673 | if (is_long_mode(vcpu)) { | |
674 | if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) { | |
675 | if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS) | |
676 | return 1; | |
677 | } else | |
678 | if (cr3 & CR3_L_MODE_RESERVED_BITS) | |
679 | return 1; | |
680 | } else { | |
681 | if (is_pae(vcpu)) { | |
682 | if (cr3 & CR3_PAE_RESERVED_BITS) | |
683 | return 1; | |
684 | if (is_paging(vcpu) && | |
685 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
686 | return 1; | |
687 | } | |
688 | /* | |
689 | * We don't check reserved bits in nonpae mode, because | |
690 | * this isn't enforced, and VMware depends on this. | |
691 | */ | |
692 | } | |
693 | ||
694 | vcpu->arch.cr3 = cr3; | |
695 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); | |
696 | kvm_mmu_new_cr3(vcpu); | |
697 | return 0; | |
698 | } | |
699 | EXPORT_SYMBOL_GPL(kvm_set_cr3); | |
700 | ||
701 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) | |
702 | { | |
703 | if (cr8 & CR8_RESERVED_BITS) | |
704 | return 1; | |
705 | if (irqchip_in_kernel(vcpu->kvm)) | |
706 | kvm_lapic_set_tpr(vcpu, cr8); | |
707 | else | |
708 | vcpu->arch.cr8 = cr8; | |
709 | return 0; | |
710 | } | |
711 | EXPORT_SYMBOL_GPL(kvm_set_cr8); | |
712 | ||
713 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) | |
714 | { | |
715 | if (irqchip_in_kernel(vcpu->kvm)) | |
716 | return kvm_lapic_get_cr8(vcpu); | |
717 | else | |
718 | return vcpu->arch.cr8; | |
719 | } | |
720 | EXPORT_SYMBOL_GPL(kvm_get_cr8); | |
721 | ||
722 | static void kvm_update_dr7(struct kvm_vcpu *vcpu) | |
723 | { | |
724 | unsigned long dr7; | |
725 | ||
726 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
727 | dr7 = vcpu->arch.guest_debug_dr7; | |
728 | else | |
729 | dr7 = vcpu->arch.dr7; | |
730 | kvm_x86_ops->set_dr7(vcpu, dr7); | |
731 | vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK); | |
732 | } | |
733 | ||
734 | static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) | |
735 | { | |
736 | switch (dr) { | |
737 | case 0 ... 3: | |
738 | vcpu->arch.db[dr] = val; | |
739 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
740 | vcpu->arch.eff_db[dr] = val; | |
741 | break; | |
742 | case 4: | |
743 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
744 | return 1; /* #UD */ | |
745 | /* fall through */ | |
746 | case 6: | |
747 | if (val & 0xffffffff00000000ULL) | |
748 | return -1; /* #GP */ | |
749 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1; | |
750 | break; | |
751 | case 5: | |
752 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
753 | return 1; /* #UD */ | |
754 | /* fall through */ | |
755 | default: /* 7 */ | |
756 | if (val & 0xffffffff00000000ULL) | |
757 | return -1; /* #GP */ | |
758 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; | |
759 | kvm_update_dr7(vcpu); | |
760 | break; | |
761 | } | |
762 | ||
763 | return 0; | |
764 | } | |
765 | ||
766 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) | |
767 | { | |
768 | int res; | |
769 | ||
770 | res = __kvm_set_dr(vcpu, dr, val); | |
771 | if (res > 0) | |
772 | kvm_queue_exception(vcpu, UD_VECTOR); | |
773 | else if (res < 0) | |
774 | kvm_inject_gp(vcpu, 0); | |
775 | ||
776 | return res; | |
777 | } | |
778 | EXPORT_SYMBOL_GPL(kvm_set_dr); | |
779 | ||
780 | static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) | |
781 | { | |
782 | switch (dr) { | |
783 | case 0 ... 3: | |
784 | *val = vcpu->arch.db[dr]; | |
785 | break; | |
786 | case 4: | |
787 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
788 | return 1; | |
789 | /* fall through */ | |
790 | case 6: | |
791 | *val = vcpu->arch.dr6; | |
792 | break; | |
793 | case 5: | |
794 | if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
795 | return 1; | |
796 | /* fall through */ | |
797 | default: /* 7 */ | |
798 | *val = vcpu->arch.dr7; | |
799 | break; | |
800 | } | |
801 | ||
802 | return 0; | |
803 | } | |
804 | ||
805 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) | |
806 | { | |
807 | if (_kvm_get_dr(vcpu, dr, val)) { | |
808 | kvm_queue_exception(vcpu, UD_VECTOR); | |
809 | return 1; | |
810 | } | |
811 | return 0; | |
812 | } | |
813 | EXPORT_SYMBOL_GPL(kvm_get_dr); | |
814 | ||
815 | bool kvm_rdpmc(struct kvm_vcpu *vcpu) | |
816 | { | |
817 | u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
818 | u64 data; | |
819 | int err; | |
820 | ||
821 | err = kvm_pmu_read_pmc(vcpu, ecx, &data); | |
822 | if (err) | |
823 | return err; | |
824 | kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); | |
825 | kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); | |
826 | return err; | |
827 | } | |
828 | EXPORT_SYMBOL_GPL(kvm_rdpmc); | |
829 | ||
830 | /* | |
831 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
832 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
833 | * | |
834 | * This list is modified at module load time to reflect the | |
835 | * capabilities of the host cpu. This capabilities test skips MSRs that are | |
836 | * kvm-specific. Those are put in the beginning of the list. | |
837 | */ | |
838 | ||
839 | #define KVM_SAVE_MSRS_BEGIN 10 | |
840 | static u32 msrs_to_save[] = { | |
841 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, | |
842 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, | |
843 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, | |
844 | HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, | |
845 | MSR_KVM_PV_EOI_EN, | |
846 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
847 | MSR_STAR, | |
848 | #ifdef CONFIG_X86_64 | |
849 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
850 | #endif | |
851 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, | |
852 | MSR_IA32_FEATURE_CONTROL | |
853 | }; | |
854 | ||
855 | static unsigned num_msrs_to_save; | |
856 | ||
857 | static const u32 emulated_msrs[] = { | |
858 | MSR_IA32_TSC_ADJUST, | |
859 | MSR_IA32_TSCDEADLINE, | |
860 | MSR_IA32_MISC_ENABLE, | |
861 | MSR_IA32_MCG_STATUS, | |
862 | MSR_IA32_MCG_CTL, | |
863 | }; | |
864 | ||
865 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) | |
866 | { | |
867 | if (efer & efer_reserved_bits) | |
868 | return false; | |
869 | ||
870 | if (efer & EFER_FFXSR) { | |
871 | struct kvm_cpuid_entry2 *feat; | |
872 | ||
873 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
874 | if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) | |
875 | return false; | |
876 | } | |
877 | ||
878 | if (efer & EFER_SVME) { | |
879 | struct kvm_cpuid_entry2 *feat; | |
880 | ||
881 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
882 | if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) | |
883 | return false; | |
884 | } | |
885 | ||
886 | return true; | |
887 | } | |
888 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
889 | ||
890 | static int set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
891 | { | |
892 | u64 old_efer = vcpu->arch.efer; | |
893 | ||
894 | if (!kvm_valid_efer(vcpu, efer)) | |
895 | return 1; | |
896 | ||
897 | if (is_paging(vcpu) | |
898 | && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
899 | return 1; | |
900 | ||
901 | efer &= ~EFER_LMA; | |
902 | efer |= vcpu->arch.efer & EFER_LMA; | |
903 | ||
904 | kvm_x86_ops->set_efer(vcpu, efer); | |
905 | ||
906 | /* Update reserved bits */ | |
907 | if ((efer ^ old_efer) & EFER_NX) | |
908 | kvm_mmu_reset_context(vcpu); | |
909 | ||
910 | return 0; | |
911 | } | |
912 | ||
913 | void kvm_enable_efer_bits(u64 mask) | |
914 | { | |
915 | efer_reserved_bits &= ~mask; | |
916 | } | |
917 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
918 | ||
919 | ||
920 | /* | |
921 | * Writes msr value into into the appropriate "register". | |
922 | * Returns 0 on success, non-0 otherwise. | |
923 | * Assumes vcpu_load() was already called. | |
924 | */ | |
925 | int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) | |
926 | { | |
927 | return kvm_x86_ops->set_msr(vcpu, msr); | |
928 | } | |
929 | ||
930 | /* | |
931 | * Adapt set_msr() to msr_io()'s calling convention | |
932 | */ | |
933 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
934 | { | |
935 | struct msr_data msr; | |
936 | ||
937 | msr.data = *data; | |
938 | msr.index = index; | |
939 | msr.host_initiated = true; | |
940 | return kvm_set_msr(vcpu, &msr); | |
941 | } | |
942 | ||
943 | #ifdef CONFIG_X86_64 | |
944 | struct pvclock_gtod_data { | |
945 | seqcount_t seq; | |
946 | ||
947 | struct { /* extract of a clocksource struct */ | |
948 | int vclock_mode; | |
949 | cycle_t cycle_last; | |
950 | cycle_t mask; | |
951 | u32 mult; | |
952 | u32 shift; | |
953 | } clock; | |
954 | ||
955 | /* open coded 'struct timespec' */ | |
956 | u64 monotonic_time_snsec; | |
957 | time_t monotonic_time_sec; | |
958 | }; | |
959 | ||
960 | static struct pvclock_gtod_data pvclock_gtod_data; | |
961 | ||
962 | static void update_pvclock_gtod(struct timekeeper *tk) | |
963 | { | |
964 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
965 | ||
966 | write_seqcount_begin(&vdata->seq); | |
967 | ||
968 | /* copy pvclock gtod data */ | |
969 | vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode; | |
970 | vdata->clock.cycle_last = tk->clock->cycle_last; | |
971 | vdata->clock.mask = tk->clock->mask; | |
972 | vdata->clock.mult = tk->mult; | |
973 | vdata->clock.shift = tk->shift; | |
974 | ||
975 | vdata->monotonic_time_sec = tk->xtime_sec | |
976 | + tk->wall_to_monotonic.tv_sec; | |
977 | vdata->monotonic_time_snsec = tk->xtime_nsec | |
978 | + (tk->wall_to_monotonic.tv_nsec | |
979 | << tk->shift); | |
980 | while (vdata->monotonic_time_snsec >= | |
981 | (((u64)NSEC_PER_SEC) << tk->shift)) { | |
982 | vdata->monotonic_time_snsec -= | |
983 | ((u64)NSEC_PER_SEC) << tk->shift; | |
984 | vdata->monotonic_time_sec++; | |
985 | } | |
986 | ||
987 | write_seqcount_end(&vdata->seq); | |
988 | } | |
989 | #endif | |
990 | ||
991 | ||
992 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) | |
993 | { | |
994 | int version; | |
995 | int r; | |
996 | struct pvclock_wall_clock wc; | |
997 | struct timespec boot; | |
998 | ||
999 | if (!wall_clock) | |
1000 | return; | |
1001 | ||
1002 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); | |
1003 | if (r) | |
1004 | return; | |
1005 | ||
1006 | if (version & 1) | |
1007 | ++version; /* first time write, random junk */ | |
1008 | ||
1009 | ++version; | |
1010 | ||
1011 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
1012 | ||
1013 | /* | |
1014 | * The guest calculates current wall clock time by adding | |
1015 | * system time (updated by kvm_guest_time_update below) to the | |
1016 | * wall clock specified here. guest system time equals host | |
1017 | * system time for us, thus we must fill in host boot time here. | |
1018 | */ | |
1019 | getboottime(&boot); | |
1020 | ||
1021 | if (kvm->arch.kvmclock_offset) { | |
1022 | struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset); | |
1023 | boot = timespec_sub(boot, ts); | |
1024 | } | |
1025 | wc.sec = boot.tv_sec; | |
1026 | wc.nsec = boot.tv_nsec; | |
1027 | wc.version = version; | |
1028 | ||
1029 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
1030 | ||
1031 | version++; | |
1032 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
1033 | } | |
1034 | ||
1035 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) | |
1036 | { | |
1037 | uint32_t quotient, remainder; | |
1038 | ||
1039 | /* Don't try to replace with do_div(), this one calculates | |
1040 | * "(dividend << 32) / divisor" */ | |
1041 | __asm__ ( "divl %4" | |
1042 | : "=a" (quotient), "=d" (remainder) | |
1043 | : "0" (0), "1" (dividend), "r" (divisor) ); | |
1044 | return quotient; | |
1045 | } | |
1046 | ||
1047 | static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz, | |
1048 | s8 *pshift, u32 *pmultiplier) | |
1049 | { | |
1050 | uint64_t scaled64; | |
1051 | int32_t shift = 0; | |
1052 | uint64_t tps64; | |
1053 | uint32_t tps32; | |
1054 | ||
1055 | tps64 = base_khz * 1000LL; | |
1056 | scaled64 = scaled_khz * 1000LL; | |
1057 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { | |
1058 | tps64 >>= 1; | |
1059 | shift--; | |
1060 | } | |
1061 | ||
1062 | tps32 = (uint32_t)tps64; | |
1063 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { | |
1064 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
1065 | scaled64 >>= 1; | |
1066 | else | |
1067 | tps32 <<= 1; | |
1068 | shift++; | |
1069 | } | |
1070 | ||
1071 | *pshift = shift; | |
1072 | *pmultiplier = div_frac(scaled64, tps32); | |
1073 | ||
1074 | pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n", | |
1075 | __func__, base_khz, scaled_khz, shift, *pmultiplier); | |
1076 | } | |
1077 | ||
1078 | static inline u64 get_kernel_ns(void) | |
1079 | { | |
1080 | struct timespec ts; | |
1081 | ||
1082 | WARN_ON(preemptible()); | |
1083 | ktime_get_ts(&ts); | |
1084 | monotonic_to_bootbased(&ts); | |
1085 | return timespec_to_ns(&ts); | |
1086 | } | |
1087 | ||
1088 | #ifdef CONFIG_X86_64 | |
1089 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); | |
1090 | #endif | |
1091 | ||
1092 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); | |
1093 | unsigned long max_tsc_khz; | |
1094 | ||
1095 | static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) | |
1096 | { | |
1097 | return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, | |
1098 | vcpu->arch.virtual_tsc_shift); | |
1099 | } | |
1100 | ||
1101 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) | |
1102 | { | |
1103 | u64 v = (u64)khz * (1000000 + ppm); | |
1104 | do_div(v, 1000000); | |
1105 | return v; | |
1106 | } | |
1107 | ||
1108 | static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz) | |
1109 | { | |
1110 | u32 thresh_lo, thresh_hi; | |
1111 | int use_scaling = 0; | |
1112 | ||
1113 | /* tsc_khz can be zero if TSC calibration fails */ | |
1114 | if (this_tsc_khz == 0) | |
1115 | return; | |
1116 | ||
1117 | /* Compute a scale to convert nanoseconds in TSC cycles */ | |
1118 | kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000, | |
1119 | &vcpu->arch.virtual_tsc_shift, | |
1120 | &vcpu->arch.virtual_tsc_mult); | |
1121 | vcpu->arch.virtual_tsc_khz = this_tsc_khz; | |
1122 | ||
1123 | /* | |
1124 | * Compute the variation in TSC rate which is acceptable | |
1125 | * within the range of tolerance and decide if the | |
1126 | * rate being applied is within that bounds of the hardware | |
1127 | * rate. If so, no scaling or compensation need be done. | |
1128 | */ | |
1129 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
1130 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
1131 | if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) { | |
1132 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi); | |
1133 | use_scaling = 1; | |
1134 | } | |
1135 | kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling); | |
1136 | } | |
1137 | ||
1138 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
1139 | { | |
1140 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, | |
1141 | vcpu->arch.virtual_tsc_mult, | |
1142 | vcpu->arch.virtual_tsc_shift); | |
1143 | tsc += vcpu->arch.this_tsc_write; | |
1144 | return tsc; | |
1145 | } | |
1146 | ||
1147 | void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) | |
1148 | { | |
1149 | #ifdef CONFIG_X86_64 | |
1150 | bool vcpus_matched; | |
1151 | bool do_request = false; | |
1152 | struct kvm_arch *ka = &vcpu->kvm->arch; | |
1153 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1154 | ||
1155 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
1156 | atomic_read(&vcpu->kvm->online_vcpus)); | |
1157 | ||
1158 | if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC) | |
1159 | if (!ka->use_master_clock) | |
1160 | do_request = 1; | |
1161 | ||
1162 | if (!vcpus_matched && ka->use_master_clock) | |
1163 | do_request = 1; | |
1164 | ||
1165 | if (do_request) | |
1166 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); | |
1167 | ||
1168 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
1169 | atomic_read(&vcpu->kvm->online_vcpus), | |
1170 | ka->use_master_clock, gtod->clock.vclock_mode); | |
1171 | #endif | |
1172 | } | |
1173 | ||
1174 | static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) | |
1175 | { | |
1176 | u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu); | |
1177 | vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; | |
1178 | } | |
1179 | ||
1180 | void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) | |
1181 | { | |
1182 | struct kvm *kvm = vcpu->kvm; | |
1183 | u64 offset, ns, elapsed; | |
1184 | unsigned long flags; | |
1185 | s64 usdiff; | |
1186 | bool matched; | |
1187 | u64 data = msr->data; | |
1188 | ||
1189 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); | |
1190 | offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); | |
1191 | ns = get_kernel_ns(); | |
1192 | elapsed = ns - kvm->arch.last_tsc_nsec; | |
1193 | ||
1194 | if (vcpu->arch.virtual_tsc_khz) { | |
1195 | int faulted = 0; | |
1196 | ||
1197 | /* n.b - signed multiplication and division required */ | |
1198 | usdiff = data - kvm->arch.last_tsc_write; | |
1199 | #ifdef CONFIG_X86_64 | |
1200 | usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz; | |
1201 | #else | |
1202 | /* do_div() only does unsigned */ | |
1203 | asm("1: idivl %[divisor]\n" | |
1204 | "2: xor %%edx, %%edx\n" | |
1205 | " movl $0, %[faulted]\n" | |
1206 | "3:\n" | |
1207 | ".section .fixup,\"ax\"\n" | |
1208 | "4: movl $1, %[faulted]\n" | |
1209 | " jmp 3b\n" | |
1210 | ".previous\n" | |
1211 | ||
1212 | _ASM_EXTABLE(1b, 4b) | |
1213 | ||
1214 | : "=A"(usdiff), [faulted] "=r" (faulted) | |
1215 | : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz)); | |
1216 | ||
1217 | #endif | |
1218 | do_div(elapsed, 1000); | |
1219 | usdiff -= elapsed; | |
1220 | if (usdiff < 0) | |
1221 | usdiff = -usdiff; | |
1222 | ||
1223 | /* idivl overflow => difference is larger than USEC_PER_SEC */ | |
1224 | if (faulted) | |
1225 | usdiff = USEC_PER_SEC; | |
1226 | } else | |
1227 | usdiff = USEC_PER_SEC; /* disable TSC match window below */ | |
1228 | ||
1229 | /* | |
1230 | * Special case: TSC write with a small delta (1 second) of virtual | |
1231 | * cycle time against real time is interpreted as an attempt to | |
1232 | * synchronize the CPU. | |
1233 | * | |
1234 | * For a reliable TSC, we can match TSC offsets, and for an unstable | |
1235 | * TSC, we add elapsed time in this computation. We could let the | |
1236 | * compensation code attempt to catch up if we fall behind, but | |
1237 | * it's better to try to match offsets from the beginning. | |
1238 | */ | |
1239 | if (usdiff < USEC_PER_SEC && | |
1240 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { | |
1241 | if (!check_tsc_unstable()) { | |
1242 | offset = kvm->arch.cur_tsc_offset; | |
1243 | pr_debug("kvm: matched tsc offset for %llu\n", data); | |
1244 | } else { | |
1245 | u64 delta = nsec_to_cycles(vcpu, elapsed); | |
1246 | data += delta; | |
1247 | offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); | |
1248 | pr_debug("kvm: adjusted tsc offset by %llu\n", delta); | |
1249 | } | |
1250 | matched = true; | |
1251 | } else { | |
1252 | /* | |
1253 | * We split periods of matched TSC writes into generations. | |
1254 | * For each generation, we track the original measured | |
1255 | * nanosecond time, offset, and write, so if TSCs are in | |
1256 | * sync, we can match exact offset, and if not, we can match | |
1257 | * exact software computation in compute_guest_tsc() | |
1258 | * | |
1259 | * These values are tracked in kvm->arch.cur_xxx variables. | |
1260 | */ | |
1261 | kvm->arch.cur_tsc_generation++; | |
1262 | kvm->arch.cur_tsc_nsec = ns; | |
1263 | kvm->arch.cur_tsc_write = data; | |
1264 | kvm->arch.cur_tsc_offset = offset; | |
1265 | matched = false; | |
1266 | pr_debug("kvm: new tsc generation %u, clock %llu\n", | |
1267 | kvm->arch.cur_tsc_generation, data); | |
1268 | } | |
1269 | ||
1270 | /* | |
1271 | * We also track th most recent recorded KHZ, write and time to | |
1272 | * allow the matching interval to be extended at each write. | |
1273 | */ | |
1274 | kvm->arch.last_tsc_nsec = ns; | |
1275 | kvm->arch.last_tsc_write = data; | |
1276 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; | |
1277 | ||
1278 | /* Reset of TSC must disable overshoot protection below */ | |
1279 | vcpu->arch.hv_clock.tsc_timestamp = 0; | |
1280 | vcpu->arch.last_guest_tsc = data; | |
1281 | ||
1282 | /* Keep track of which generation this VCPU has synchronized to */ | |
1283 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
1284 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
1285 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
1286 | ||
1287 | if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated) | |
1288 | update_ia32_tsc_adjust_msr(vcpu, offset); | |
1289 | kvm_x86_ops->write_tsc_offset(vcpu, offset); | |
1290 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); | |
1291 | ||
1292 | spin_lock(&kvm->arch.pvclock_gtod_sync_lock); | |
1293 | if (matched) | |
1294 | kvm->arch.nr_vcpus_matched_tsc++; | |
1295 | else | |
1296 | kvm->arch.nr_vcpus_matched_tsc = 0; | |
1297 | ||
1298 | kvm_track_tsc_matching(vcpu); | |
1299 | spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); | |
1300 | } | |
1301 | ||
1302 | EXPORT_SYMBOL_GPL(kvm_write_tsc); | |
1303 | ||
1304 | #ifdef CONFIG_X86_64 | |
1305 | ||
1306 | static cycle_t read_tsc(void) | |
1307 | { | |
1308 | cycle_t ret; | |
1309 | u64 last; | |
1310 | ||
1311 | /* | |
1312 | * Empirically, a fence (of type that depends on the CPU) | |
1313 | * before rdtsc is enough to ensure that rdtsc is ordered | |
1314 | * with respect to loads. The various CPU manuals are unclear | |
1315 | * as to whether rdtsc can be reordered with later loads, | |
1316 | * but no one has ever seen it happen. | |
1317 | */ | |
1318 | rdtsc_barrier(); | |
1319 | ret = (cycle_t)vget_cycles(); | |
1320 | ||
1321 | last = pvclock_gtod_data.clock.cycle_last; | |
1322 | ||
1323 | if (likely(ret >= last)) | |
1324 | return ret; | |
1325 | ||
1326 | /* | |
1327 | * GCC likes to generate cmov here, but this branch is extremely | |
1328 | * predictable (it's just a funciton of time and the likely is | |
1329 | * very likely) and there's a data dependence, so force GCC | |
1330 | * to generate a branch instead. I don't barrier() because | |
1331 | * we don't actually need a barrier, and if this function | |
1332 | * ever gets inlined it will generate worse code. | |
1333 | */ | |
1334 | asm volatile (""); | |
1335 | return last; | |
1336 | } | |
1337 | ||
1338 | static inline u64 vgettsc(cycle_t *cycle_now) | |
1339 | { | |
1340 | long v; | |
1341 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1342 | ||
1343 | *cycle_now = read_tsc(); | |
1344 | ||
1345 | v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask; | |
1346 | return v * gtod->clock.mult; | |
1347 | } | |
1348 | ||
1349 | static int do_monotonic(struct timespec *ts, cycle_t *cycle_now) | |
1350 | { | |
1351 | unsigned long seq; | |
1352 | u64 ns; | |
1353 | int mode; | |
1354 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1355 | ||
1356 | ts->tv_nsec = 0; | |
1357 | do { | |
1358 | seq = read_seqcount_begin(>od->seq); | |
1359 | mode = gtod->clock.vclock_mode; | |
1360 | ts->tv_sec = gtod->monotonic_time_sec; | |
1361 | ns = gtod->monotonic_time_snsec; | |
1362 | ns += vgettsc(cycle_now); | |
1363 | ns >>= gtod->clock.shift; | |
1364 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); | |
1365 | timespec_add_ns(ts, ns); | |
1366 | ||
1367 | return mode; | |
1368 | } | |
1369 | ||
1370 | /* returns true if host is using tsc clocksource */ | |
1371 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now) | |
1372 | { | |
1373 | struct timespec ts; | |
1374 | ||
1375 | /* checked again under seqlock below */ | |
1376 | if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) | |
1377 | return false; | |
1378 | ||
1379 | if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC) | |
1380 | return false; | |
1381 | ||
1382 | monotonic_to_bootbased(&ts); | |
1383 | *kernel_ns = timespec_to_ns(&ts); | |
1384 | ||
1385 | return true; | |
1386 | } | |
1387 | #endif | |
1388 | ||
1389 | /* | |
1390 | * | |
1391 | * Assuming a stable TSC across physical CPUS, and a stable TSC | |
1392 | * across virtual CPUs, the following condition is possible. | |
1393 | * Each numbered line represents an event visible to both | |
1394 | * CPUs at the next numbered event. | |
1395 | * | |
1396 | * "timespecX" represents host monotonic time. "tscX" represents | |
1397 | * RDTSC value. | |
1398 | * | |
1399 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
1400 | * | |
1401 | * 1. read timespec0,tsc0 | |
1402 | * 2. | timespec1 = timespec0 + N | |
1403 | * | tsc1 = tsc0 + M | |
1404 | * 3. transition to guest | transition to guest | |
1405 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
1406 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
1407 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
1408 | * | |
1409 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
1410 | * | |
1411 | * - ret0 < ret1 | |
1412 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
1413 | * ... | |
1414 | * - 0 < N - M => M < N | |
1415 | * | |
1416 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
1417 | * always the case (the difference between two distinct xtime instances | |
1418 | * might be smaller then the difference between corresponding TSC reads, | |
1419 | * when updating guest vcpus pvclock areas). | |
1420 | * | |
1421 | * To avoid that problem, do not allow visibility of distinct | |
1422 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
1423 | * copy of host monotonic time values. Update that master copy | |
1424 | * in lockstep. | |
1425 | * | |
1426 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. | |
1427 | * | |
1428 | */ | |
1429 | ||
1430 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
1431 | { | |
1432 | #ifdef CONFIG_X86_64 | |
1433 | struct kvm_arch *ka = &kvm->arch; | |
1434 | int vclock_mode; | |
1435 | bool host_tsc_clocksource, vcpus_matched; | |
1436 | ||
1437 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
1438 | atomic_read(&kvm->online_vcpus)); | |
1439 | ||
1440 | /* | |
1441 | * If the host uses TSC clock, then passthrough TSC as stable | |
1442 | * to the guest. | |
1443 | */ | |
1444 | host_tsc_clocksource = kvm_get_time_and_clockread( | |
1445 | &ka->master_kernel_ns, | |
1446 | &ka->master_cycle_now); | |
1447 | ||
1448 | ka->use_master_clock = host_tsc_clocksource & vcpus_matched; | |
1449 | ||
1450 | if (ka->use_master_clock) | |
1451 | atomic_set(&kvm_guest_has_master_clock, 1); | |
1452 | ||
1453 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
1454 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, | |
1455 | vcpus_matched); | |
1456 | #endif | |
1457 | } | |
1458 | ||
1459 | static void kvm_gen_update_masterclock(struct kvm *kvm) | |
1460 | { | |
1461 | #ifdef CONFIG_X86_64 | |
1462 | int i; | |
1463 | struct kvm_vcpu *vcpu; | |
1464 | struct kvm_arch *ka = &kvm->arch; | |
1465 | ||
1466 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
1467 | kvm_make_mclock_inprogress_request(kvm); | |
1468 | /* no guest entries from this point */ | |
1469 | pvclock_update_vm_gtod_copy(kvm); | |
1470 | ||
1471 | kvm_for_each_vcpu(i, vcpu, kvm) | |
1472 | set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests); | |
1473 | ||
1474 | /* guest entries allowed */ | |
1475 | kvm_for_each_vcpu(i, vcpu, kvm) | |
1476 | clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests); | |
1477 | ||
1478 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
1479 | #endif | |
1480 | } | |
1481 | ||
1482 | static int kvm_guest_time_update(struct kvm_vcpu *v) | |
1483 | { | |
1484 | unsigned long flags, this_tsc_khz; | |
1485 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
1486 | struct kvm_arch *ka = &v->kvm->arch; | |
1487 | s64 kernel_ns, max_kernel_ns; | |
1488 | u64 tsc_timestamp, host_tsc; | |
1489 | struct pvclock_vcpu_time_info guest_hv_clock; | |
1490 | u8 pvclock_flags; | |
1491 | bool use_master_clock; | |
1492 | ||
1493 | kernel_ns = 0; | |
1494 | host_tsc = 0; | |
1495 | ||
1496 | /* | |
1497 | * If the host uses TSC clock, then passthrough TSC as stable | |
1498 | * to the guest. | |
1499 | */ | |
1500 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
1501 | use_master_clock = ka->use_master_clock; | |
1502 | if (use_master_clock) { | |
1503 | host_tsc = ka->master_cycle_now; | |
1504 | kernel_ns = ka->master_kernel_ns; | |
1505 | } | |
1506 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
1507 | ||
1508 | /* Keep irq disabled to prevent changes to the clock */ | |
1509 | local_irq_save(flags); | |
1510 | this_tsc_khz = __get_cpu_var(cpu_tsc_khz); | |
1511 | if (unlikely(this_tsc_khz == 0)) { | |
1512 | local_irq_restore(flags); | |
1513 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
1514 | return 1; | |
1515 | } | |
1516 | if (!use_master_clock) { | |
1517 | host_tsc = native_read_tsc(); | |
1518 | kernel_ns = get_kernel_ns(); | |
1519 | } | |
1520 | ||
1521 | tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc); | |
1522 | ||
1523 | /* | |
1524 | * We may have to catch up the TSC to match elapsed wall clock | |
1525 | * time for two reasons, even if kvmclock is used. | |
1526 | * 1) CPU could have been running below the maximum TSC rate | |
1527 | * 2) Broken TSC compensation resets the base at each VCPU | |
1528 | * entry to avoid unknown leaps of TSC even when running | |
1529 | * again on the same CPU. This may cause apparent elapsed | |
1530 | * time to disappear, and the guest to stand still or run | |
1531 | * very slowly. | |
1532 | */ | |
1533 | if (vcpu->tsc_catchup) { | |
1534 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
1535 | if (tsc > tsc_timestamp) { | |
1536 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); | |
1537 | tsc_timestamp = tsc; | |
1538 | } | |
1539 | } | |
1540 | ||
1541 | local_irq_restore(flags); | |
1542 | ||
1543 | if (!vcpu->pv_time_enabled) | |
1544 | return 0; | |
1545 | ||
1546 | /* | |
1547 | * Time as measured by the TSC may go backwards when resetting the base | |
1548 | * tsc_timestamp. The reason for this is that the TSC resolution is | |
1549 | * higher than the resolution of the other clock scales. Thus, many | |
1550 | * possible measurments of the TSC correspond to one measurement of any | |
1551 | * other clock, and so a spread of values is possible. This is not a | |
1552 | * problem for the computation of the nanosecond clock; with TSC rates | |
1553 | * around 1GHZ, there can only be a few cycles which correspond to one | |
1554 | * nanosecond value, and any path through this code will inevitably | |
1555 | * take longer than that. However, with the kernel_ns value itself, | |
1556 | * the precision may be much lower, down to HZ granularity. If the | |
1557 | * first sampling of TSC against kernel_ns ends in the low part of the | |
1558 | * range, and the second in the high end of the range, we can get: | |
1559 | * | |
1560 | * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new | |
1561 | * | |
1562 | * As the sampling errors potentially range in the thousands of cycles, | |
1563 | * it is possible such a time value has already been observed by the | |
1564 | * guest. To protect against this, we must compute the system time as | |
1565 | * observed by the guest and ensure the new system time is greater. | |
1566 | */ | |
1567 | max_kernel_ns = 0; | |
1568 | if (vcpu->hv_clock.tsc_timestamp) { | |
1569 | max_kernel_ns = vcpu->last_guest_tsc - | |
1570 | vcpu->hv_clock.tsc_timestamp; | |
1571 | max_kernel_ns = pvclock_scale_delta(max_kernel_ns, | |
1572 | vcpu->hv_clock.tsc_to_system_mul, | |
1573 | vcpu->hv_clock.tsc_shift); | |
1574 | max_kernel_ns += vcpu->last_kernel_ns; | |
1575 | } | |
1576 | ||
1577 | if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) { | |
1578 | kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz, | |
1579 | &vcpu->hv_clock.tsc_shift, | |
1580 | &vcpu->hv_clock.tsc_to_system_mul); | |
1581 | vcpu->hw_tsc_khz = this_tsc_khz; | |
1582 | } | |
1583 | ||
1584 | /* with a master <monotonic time, tsc value> tuple, | |
1585 | * pvclock clock reads always increase at the (scaled) rate | |
1586 | * of guest TSC - no need to deal with sampling errors. | |
1587 | */ | |
1588 | if (!use_master_clock) { | |
1589 | if (max_kernel_ns > kernel_ns) | |
1590 | kernel_ns = max_kernel_ns; | |
1591 | } | |
1592 | /* With all the info we got, fill in the values */ | |
1593 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; | |
1594 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; | |
1595 | vcpu->last_kernel_ns = kernel_ns; | |
1596 | vcpu->last_guest_tsc = tsc_timestamp; | |
1597 | ||
1598 | /* | |
1599 | * The interface expects us to write an even number signaling that the | |
1600 | * update is finished. Since the guest won't see the intermediate | |
1601 | * state, we just increase by 2 at the end. | |
1602 | */ | |
1603 | vcpu->hv_clock.version += 2; | |
1604 | ||
1605 | if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, | |
1606 | &guest_hv_clock, sizeof(guest_hv_clock)))) | |
1607 | return 0; | |
1608 | ||
1609 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
1610 | pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); | |
1611 | ||
1612 | if (vcpu->pvclock_set_guest_stopped_request) { | |
1613 | pvclock_flags |= PVCLOCK_GUEST_STOPPED; | |
1614 | vcpu->pvclock_set_guest_stopped_request = false; | |
1615 | } | |
1616 | ||
1617 | /* If the host uses TSC clocksource, then it is stable */ | |
1618 | if (use_master_clock) | |
1619 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
1620 | ||
1621 | vcpu->hv_clock.flags = pvclock_flags; | |
1622 | ||
1623 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, | |
1624 | &vcpu->hv_clock, | |
1625 | sizeof(vcpu->hv_clock)); | |
1626 | return 0; | |
1627 | } | |
1628 | ||
1629 | /* | |
1630 | * kvmclock updates which are isolated to a given vcpu, such as | |
1631 | * vcpu->cpu migration, should not allow system_timestamp from | |
1632 | * the rest of the vcpus to remain static. Otherwise ntp frequency | |
1633 | * correction applies to one vcpu's system_timestamp but not | |
1634 | * the others. | |
1635 | * | |
1636 | * So in those cases, request a kvmclock update for all vcpus. | |
1637 | * The worst case for a remote vcpu to update its kvmclock | |
1638 | * is then bounded by maximum nohz sleep latency. | |
1639 | */ | |
1640 | ||
1641 | static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) | |
1642 | { | |
1643 | int i; | |
1644 | struct kvm *kvm = v->kvm; | |
1645 | struct kvm_vcpu *vcpu; | |
1646 | ||
1647 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
1648 | set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests); | |
1649 | kvm_vcpu_kick(vcpu); | |
1650 | } | |
1651 | } | |
1652 | ||
1653 | static bool msr_mtrr_valid(unsigned msr) | |
1654 | { | |
1655 | switch (msr) { | |
1656 | case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1: | |
1657 | case MSR_MTRRfix64K_00000: | |
1658 | case MSR_MTRRfix16K_80000: | |
1659 | case MSR_MTRRfix16K_A0000: | |
1660 | case MSR_MTRRfix4K_C0000: | |
1661 | case MSR_MTRRfix4K_C8000: | |
1662 | case MSR_MTRRfix4K_D0000: | |
1663 | case MSR_MTRRfix4K_D8000: | |
1664 | case MSR_MTRRfix4K_E0000: | |
1665 | case MSR_MTRRfix4K_E8000: | |
1666 | case MSR_MTRRfix4K_F0000: | |
1667 | case MSR_MTRRfix4K_F8000: | |
1668 | case MSR_MTRRdefType: | |
1669 | case MSR_IA32_CR_PAT: | |
1670 | return true; | |
1671 | case 0x2f8: | |
1672 | return true; | |
1673 | } | |
1674 | return false; | |
1675 | } | |
1676 | ||
1677 | static bool valid_pat_type(unsigned t) | |
1678 | { | |
1679 | return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */ | |
1680 | } | |
1681 | ||
1682 | static bool valid_mtrr_type(unsigned t) | |
1683 | { | |
1684 | return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */ | |
1685 | } | |
1686 | ||
1687 | static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1688 | { | |
1689 | int i; | |
1690 | ||
1691 | if (!msr_mtrr_valid(msr)) | |
1692 | return false; | |
1693 | ||
1694 | if (msr == MSR_IA32_CR_PAT) { | |
1695 | for (i = 0; i < 8; i++) | |
1696 | if (!valid_pat_type((data >> (i * 8)) & 0xff)) | |
1697 | return false; | |
1698 | return true; | |
1699 | } else if (msr == MSR_MTRRdefType) { | |
1700 | if (data & ~0xcff) | |
1701 | return false; | |
1702 | return valid_mtrr_type(data & 0xff); | |
1703 | } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) { | |
1704 | for (i = 0; i < 8 ; i++) | |
1705 | if (!valid_mtrr_type((data >> (i * 8)) & 0xff)) | |
1706 | return false; | |
1707 | return true; | |
1708 | } | |
1709 | ||
1710 | /* variable MTRRs */ | |
1711 | return valid_mtrr_type(data & 0xff); | |
1712 | } | |
1713 | ||
1714 | static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1715 | { | |
1716 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; | |
1717 | ||
1718 | if (!mtrr_valid(vcpu, msr, data)) | |
1719 | return 1; | |
1720 | ||
1721 | if (msr == MSR_MTRRdefType) { | |
1722 | vcpu->arch.mtrr_state.def_type = data; | |
1723 | vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10; | |
1724 | } else if (msr == MSR_MTRRfix64K_00000) | |
1725 | p[0] = data; | |
1726 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
1727 | p[1 + msr - MSR_MTRRfix16K_80000] = data; | |
1728 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
1729 | p[3 + msr - MSR_MTRRfix4K_C0000] = data; | |
1730 | else if (msr == MSR_IA32_CR_PAT) | |
1731 | vcpu->arch.pat = data; | |
1732 | else { /* Variable MTRRs */ | |
1733 | int idx, is_mtrr_mask; | |
1734 | u64 *pt; | |
1735 | ||
1736 | idx = (msr - 0x200) / 2; | |
1737 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
1738 | if (!is_mtrr_mask) | |
1739 | pt = | |
1740 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
1741 | else | |
1742 | pt = | |
1743 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
1744 | *pt = data; | |
1745 | } | |
1746 | ||
1747 | kvm_mmu_reset_context(vcpu); | |
1748 | return 0; | |
1749 | } | |
1750 | ||
1751 | static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1752 | { | |
1753 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
1754 | unsigned bank_num = mcg_cap & 0xff; | |
1755 | ||
1756 | switch (msr) { | |
1757 | case MSR_IA32_MCG_STATUS: | |
1758 | vcpu->arch.mcg_status = data; | |
1759 | break; | |
1760 | case MSR_IA32_MCG_CTL: | |
1761 | if (!(mcg_cap & MCG_CTL_P)) | |
1762 | return 1; | |
1763 | if (data != 0 && data != ~(u64)0) | |
1764 | return -1; | |
1765 | vcpu->arch.mcg_ctl = data; | |
1766 | break; | |
1767 | default: | |
1768 | if (msr >= MSR_IA32_MC0_CTL && | |
1769 | msr < MSR_IA32_MC0_CTL + 4 * bank_num) { | |
1770 | u32 offset = msr - MSR_IA32_MC0_CTL; | |
1771 | /* only 0 or all 1s can be written to IA32_MCi_CTL | |
1772 | * some Linux kernels though clear bit 10 in bank 4 to | |
1773 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
1774 | * this to avoid an uncatched #GP in the guest | |
1775 | */ | |
1776 | if ((offset & 0x3) == 0 && | |
1777 | data != 0 && (data | (1 << 10)) != ~(u64)0) | |
1778 | return -1; | |
1779 | vcpu->arch.mce_banks[offset] = data; | |
1780 | break; | |
1781 | } | |
1782 | return 1; | |
1783 | } | |
1784 | return 0; | |
1785 | } | |
1786 | ||
1787 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) | |
1788 | { | |
1789 | struct kvm *kvm = vcpu->kvm; | |
1790 | int lm = is_long_mode(vcpu); | |
1791 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
1792 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
1793 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
1794 | : kvm->arch.xen_hvm_config.blob_size_32; | |
1795 | u32 page_num = data & ~PAGE_MASK; | |
1796 | u64 page_addr = data & PAGE_MASK; | |
1797 | u8 *page; | |
1798 | int r; | |
1799 | ||
1800 | r = -E2BIG; | |
1801 | if (page_num >= blob_size) | |
1802 | goto out; | |
1803 | r = -ENOMEM; | |
1804 | page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); | |
1805 | if (IS_ERR(page)) { | |
1806 | r = PTR_ERR(page); | |
1807 | goto out; | |
1808 | } | |
1809 | if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE)) | |
1810 | goto out_free; | |
1811 | r = 0; | |
1812 | out_free: | |
1813 | kfree(page); | |
1814 | out: | |
1815 | return r; | |
1816 | } | |
1817 | ||
1818 | static bool kvm_hv_hypercall_enabled(struct kvm *kvm) | |
1819 | { | |
1820 | return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE; | |
1821 | } | |
1822 | ||
1823 | static bool kvm_hv_msr_partition_wide(u32 msr) | |
1824 | { | |
1825 | bool r = false; | |
1826 | switch (msr) { | |
1827 | case HV_X64_MSR_GUEST_OS_ID: | |
1828 | case HV_X64_MSR_HYPERCALL: | |
1829 | r = true; | |
1830 | break; | |
1831 | } | |
1832 | ||
1833 | return r; | |
1834 | } | |
1835 | ||
1836 | static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1837 | { | |
1838 | struct kvm *kvm = vcpu->kvm; | |
1839 | ||
1840 | switch (msr) { | |
1841 | case HV_X64_MSR_GUEST_OS_ID: | |
1842 | kvm->arch.hv_guest_os_id = data; | |
1843 | /* setting guest os id to zero disables hypercall page */ | |
1844 | if (!kvm->arch.hv_guest_os_id) | |
1845 | kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE; | |
1846 | break; | |
1847 | case HV_X64_MSR_HYPERCALL: { | |
1848 | u64 gfn; | |
1849 | unsigned long addr; | |
1850 | u8 instructions[4]; | |
1851 | ||
1852 | /* if guest os id is not set hypercall should remain disabled */ | |
1853 | if (!kvm->arch.hv_guest_os_id) | |
1854 | break; | |
1855 | if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) { | |
1856 | kvm->arch.hv_hypercall = data; | |
1857 | break; | |
1858 | } | |
1859 | gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT; | |
1860 | addr = gfn_to_hva(kvm, gfn); | |
1861 | if (kvm_is_error_hva(addr)) | |
1862 | return 1; | |
1863 | kvm_x86_ops->patch_hypercall(vcpu, instructions); | |
1864 | ((unsigned char *)instructions)[3] = 0xc3; /* ret */ | |
1865 | if (__copy_to_user((void __user *)addr, instructions, 4)) | |
1866 | return 1; | |
1867 | kvm->arch.hv_hypercall = data; | |
1868 | break; | |
1869 | } | |
1870 | default: | |
1871 | vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " | |
1872 | "data 0x%llx\n", msr, data); | |
1873 | return 1; | |
1874 | } | |
1875 | return 0; | |
1876 | } | |
1877 | ||
1878 | static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1879 | { | |
1880 | switch (msr) { | |
1881 | case HV_X64_MSR_APIC_ASSIST_PAGE: { | |
1882 | unsigned long addr; | |
1883 | ||
1884 | if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) { | |
1885 | vcpu->arch.hv_vapic = data; | |
1886 | break; | |
1887 | } | |
1888 | addr = gfn_to_hva(vcpu->kvm, data >> | |
1889 | HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT); | |
1890 | if (kvm_is_error_hva(addr)) | |
1891 | return 1; | |
1892 | if (__clear_user((void __user *)addr, PAGE_SIZE)) | |
1893 | return 1; | |
1894 | vcpu->arch.hv_vapic = data; | |
1895 | break; | |
1896 | } | |
1897 | case HV_X64_MSR_EOI: | |
1898 | return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data); | |
1899 | case HV_X64_MSR_ICR: | |
1900 | return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data); | |
1901 | case HV_X64_MSR_TPR: | |
1902 | return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data); | |
1903 | default: | |
1904 | vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " | |
1905 | "data 0x%llx\n", msr, data); | |
1906 | return 1; | |
1907 | } | |
1908 | ||
1909 | return 0; | |
1910 | } | |
1911 | ||
1912 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) | |
1913 | { | |
1914 | gpa_t gpa = data & ~0x3f; | |
1915 | ||
1916 | /* Bits 2:5 are reserved, Should be zero */ | |
1917 | if (data & 0x3c) | |
1918 | return 1; | |
1919 | ||
1920 | vcpu->arch.apf.msr_val = data; | |
1921 | ||
1922 | if (!(data & KVM_ASYNC_PF_ENABLED)) { | |
1923 | kvm_clear_async_pf_completion_queue(vcpu); | |
1924 | kvm_async_pf_hash_reset(vcpu); | |
1925 | return 0; | |
1926 | } | |
1927 | ||
1928 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, | |
1929 | sizeof(u32))) | |
1930 | return 1; | |
1931 | ||
1932 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); | |
1933 | kvm_async_pf_wakeup_all(vcpu); | |
1934 | return 0; | |
1935 | } | |
1936 | ||
1937 | static void kvmclock_reset(struct kvm_vcpu *vcpu) | |
1938 | { | |
1939 | vcpu->arch.pv_time_enabled = false; | |
1940 | } | |
1941 | ||
1942 | static void accumulate_steal_time(struct kvm_vcpu *vcpu) | |
1943 | { | |
1944 | u64 delta; | |
1945 | ||
1946 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) | |
1947 | return; | |
1948 | ||
1949 | delta = current->sched_info.run_delay - vcpu->arch.st.last_steal; | |
1950 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
1951 | vcpu->arch.st.accum_steal = delta; | |
1952 | } | |
1953 | ||
1954 | static void record_steal_time(struct kvm_vcpu *vcpu) | |
1955 | { | |
1956 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) | |
1957 | return; | |
1958 | ||
1959 | if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, | |
1960 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) | |
1961 | return; | |
1962 | ||
1963 | vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal; | |
1964 | vcpu->arch.st.steal.version += 2; | |
1965 | vcpu->arch.st.accum_steal = 0; | |
1966 | ||
1967 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, | |
1968 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); | |
1969 | } | |
1970 | ||
1971 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) | |
1972 | { | |
1973 | bool pr = false; | |
1974 | u32 msr = msr_info->index; | |
1975 | u64 data = msr_info->data; | |
1976 | ||
1977 | switch (msr) { | |
1978 | case MSR_AMD64_NB_CFG: | |
1979 | case MSR_IA32_UCODE_REV: | |
1980 | case MSR_IA32_UCODE_WRITE: | |
1981 | case MSR_VM_HSAVE_PA: | |
1982 | case MSR_AMD64_PATCH_LOADER: | |
1983 | case MSR_AMD64_BU_CFG2: | |
1984 | break; | |
1985 | ||
1986 | case MSR_EFER: | |
1987 | return set_efer(vcpu, data); | |
1988 | case MSR_K7_HWCR: | |
1989 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
1990 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ | |
1991 | data &= ~(u64)0x8; /* ignore TLB cache disable */ | |
1992 | if (data != 0) { | |
1993 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", | |
1994 | data); | |
1995 | return 1; | |
1996 | } | |
1997 | break; | |
1998 | case MSR_FAM10H_MMIO_CONF_BASE: | |
1999 | if (data != 0) { | |
2000 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " | |
2001 | "0x%llx\n", data); | |
2002 | return 1; | |
2003 | } | |
2004 | break; | |
2005 | case MSR_IA32_DEBUGCTLMSR: | |
2006 | if (!data) { | |
2007 | /* We support the non-activated case already */ | |
2008 | break; | |
2009 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
2010 | /* Values other than LBR and BTF are vendor-specific, | |
2011 | thus reserved and should throw a #GP */ | |
2012 | return 1; | |
2013 | } | |
2014 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", | |
2015 | __func__, data); | |
2016 | break; | |
2017 | case 0x200 ... 0x2ff: | |
2018 | return set_msr_mtrr(vcpu, msr, data); | |
2019 | case MSR_IA32_APICBASE: | |
2020 | kvm_set_apic_base(vcpu, data); | |
2021 | break; | |
2022 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: | |
2023 | return kvm_x2apic_msr_write(vcpu, msr, data); | |
2024 | case MSR_IA32_TSCDEADLINE: | |
2025 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
2026 | break; | |
2027 | case MSR_IA32_TSC_ADJUST: | |
2028 | if (guest_cpuid_has_tsc_adjust(vcpu)) { | |
2029 | if (!msr_info->host_initiated) { | |
2030 | u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; | |
2031 | kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true); | |
2032 | } | |
2033 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
2034 | } | |
2035 | break; | |
2036 | case MSR_IA32_MISC_ENABLE: | |
2037 | vcpu->arch.ia32_misc_enable_msr = data; | |
2038 | break; | |
2039 | case MSR_KVM_WALL_CLOCK_NEW: | |
2040 | case MSR_KVM_WALL_CLOCK: | |
2041 | vcpu->kvm->arch.wall_clock = data; | |
2042 | kvm_write_wall_clock(vcpu->kvm, data); | |
2043 | break; | |
2044 | case MSR_KVM_SYSTEM_TIME_NEW: | |
2045 | case MSR_KVM_SYSTEM_TIME: { | |
2046 | u64 gpa_offset; | |
2047 | kvmclock_reset(vcpu); | |
2048 | ||
2049 | vcpu->arch.time = data; | |
2050 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); | |
2051 | ||
2052 | /* we verify if the enable bit is set... */ | |
2053 | if (!(data & 1)) | |
2054 | break; | |
2055 | ||
2056 | gpa_offset = data & ~(PAGE_MASK | 1); | |
2057 | ||
2058 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, | |
2059 | &vcpu->arch.pv_time, data & ~1ULL, | |
2060 | sizeof(struct pvclock_vcpu_time_info))) | |
2061 | vcpu->arch.pv_time_enabled = false; | |
2062 | else | |
2063 | vcpu->arch.pv_time_enabled = true; | |
2064 | ||
2065 | break; | |
2066 | } | |
2067 | case MSR_KVM_ASYNC_PF_EN: | |
2068 | if (kvm_pv_enable_async_pf(vcpu, data)) | |
2069 | return 1; | |
2070 | break; | |
2071 | case MSR_KVM_STEAL_TIME: | |
2072 | ||
2073 | if (unlikely(!sched_info_on())) | |
2074 | return 1; | |
2075 | ||
2076 | if (data & KVM_STEAL_RESERVED_MASK) | |
2077 | return 1; | |
2078 | ||
2079 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, | |
2080 | data & KVM_STEAL_VALID_BITS, | |
2081 | sizeof(struct kvm_steal_time))) | |
2082 | return 1; | |
2083 | ||
2084 | vcpu->arch.st.msr_val = data; | |
2085 | ||
2086 | if (!(data & KVM_MSR_ENABLED)) | |
2087 | break; | |
2088 | ||
2089 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
2090 | ||
2091 | preempt_disable(); | |
2092 | accumulate_steal_time(vcpu); | |
2093 | preempt_enable(); | |
2094 | ||
2095 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); | |
2096 | ||
2097 | break; | |
2098 | case MSR_KVM_PV_EOI_EN: | |
2099 | if (kvm_lapic_enable_pv_eoi(vcpu, data)) | |
2100 | return 1; | |
2101 | break; | |
2102 | ||
2103 | case MSR_IA32_MCG_CTL: | |
2104 | case MSR_IA32_MCG_STATUS: | |
2105 | case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: | |
2106 | return set_msr_mce(vcpu, msr, data); | |
2107 | ||
2108 | /* Performance counters are not protected by a CPUID bit, | |
2109 | * so we should check all of them in the generic path for the sake of | |
2110 | * cross vendor migration. | |
2111 | * Writing a zero into the event select MSRs disables them, | |
2112 | * which we perfectly emulate ;-). Any other value should be at least | |
2113 | * reported, some guests depend on them. | |
2114 | */ | |
2115 | case MSR_K7_EVNTSEL0: | |
2116 | case MSR_K7_EVNTSEL1: | |
2117 | case MSR_K7_EVNTSEL2: | |
2118 | case MSR_K7_EVNTSEL3: | |
2119 | if (data != 0) | |
2120 | vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " | |
2121 | "0x%x data 0x%llx\n", msr, data); | |
2122 | break; | |
2123 | /* at least RHEL 4 unconditionally writes to the perfctr registers, | |
2124 | * so we ignore writes to make it happy. | |
2125 | */ | |
2126 | case MSR_K7_PERFCTR0: | |
2127 | case MSR_K7_PERFCTR1: | |
2128 | case MSR_K7_PERFCTR2: | |
2129 | case MSR_K7_PERFCTR3: | |
2130 | vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " | |
2131 | "0x%x data 0x%llx\n", msr, data); | |
2132 | break; | |
2133 | case MSR_P6_PERFCTR0: | |
2134 | case MSR_P6_PERFCTR1: | |
2135 | pr = true; | |
2136 | case MSR_P6_EVNTSEL0: | |
2137 | case MSR_P6_EVNTSEL1: | |
2138 | if (kvm_pmu_msr(vcpu, msr)) | |
2139 | return kvm_pmu_set_msr(vcpu, msr_info); | |
2140 | ||
2141 | if (pr || data != 0) | |
2142 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " | |
2143 | "0x%x data 0x%llx\n", msr, data); | |
2144 | break; | |
2145 | case MSR_K7_CLK_CTL: | |
2146 | /* | |
2147 | * Ignore all writes to this no longer documented MSR. | |
2148 | * Writes are only relevant for old K7 processors, | |
2149 | * all pre-dating SVM, but a recommended workaround from | |
2150 | * AMD for these chips. It is possible to specify the | |
2151 | * affected processor models on the command line, hence | |
2152 | * the need to ignore the workaround. | |
2153 | */ | |
2154 | break; | |
2155 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: | |
2156 | if (kvm_hv_msr_partition_wide(msr)) { | |
2157 | int r; | |
2158 | mutex_lock(&vcpu->kvm->lock); | |
2159 | r = set_msr_hyperv_pw(vcpu, msr, data); | |
2160 | mutex_unlock(&vcpu->kvm->lock); | |
2161 | return r; | |
2162 | } else | |
2163 | return set_msr_hyperv(vcpu, msr, data); | |
2164 | break; | |
2165 | case MSR_IA32_BBL_CR_CTL3: | |
2166 | /* Drop writes to this legacy MSR -- see rdmsr | |
2167 | * counterpart for further detail. | |
2168 | */ | |
2169 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data); | |
2170 | break; | |
2171 | case MSR_AMD64_OSVW_ID_LENGTH: | |
2172 | if (!guest_cpuid_has_osvw(vcpu)) | |
2173 | return 1; | |
2174 | vcpu->arch.osvw.length = data; | |
2175 | break; | |
2176 | case MSR_AMD64_OSVW_STATUS: | |
2177 | if (!guest_cpuid_has_osvw(vcpu)) | |
2178 | return 1; | |
2179 | vcpu->arch.osvw.status = data; | |
2180 | break; | |
2181 | default: | |
2182 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) | |
2183 | return xen_hvm_config(vcpu, data); | |
2184 | if (kvm_pmu_msr(vcpu, msr)) | |
2185 | return kvm_pmu_set_msr(vcpu, msr_info); | |
2186 | if (!ignore_msrs) { | |
2187 | vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", | |
2188 | msr, data); | |
2189 | return 1; | |
2190 | } else { | |
2191 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", | |
2192 | msr, data); | |
2193 | break; | |
2194 | } | |
2195 | } | |
2196 | return 0; | |
2197 | } | |
2198 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
2199 | ||
2200 | ||
2201 | /* | |
2202 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
2203 | * Returns 0 on success, non-0 otherwise. | |
2204 | * Assumes vcpu_load() was already called. | |
2205 | */ | |
2206 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
2207 | { | |
2208 | return kvm_x86_ops->get_msr(vcpu, msr_index, pdata); | |
2209 | } | |
2210 | ||
2211 | static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) | |
2212 | { | |
2213 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; | |
2214 | ||
2215 | if (!msr_mtrr_valid(msr)) | |
2216 | return 1; | |
2217 | ||
2218 | if (msr == MSR_MTRRdefType) | |
2219 | *pdata = vcpu->arch.mtrr_state.def_type + | |
2220 | (vcpu->arch.mtrr_state.enabled << 10); | |
2221 | else if (msr == MSR_MTRRfix64K_00000) | |
2222 | *pdata = p[0]; | |
2223 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
2224 | *pdata = p[1 + msr - MSR_MTRRfix16K_80000]; | |
2225 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
2226 | *pdata = p[3 + msr - MSR_MTRRfix4K_C0000]; | |
2227 | else if (msr == MSR_IA32_CR_PAT) | |
2228 | *pdata = vcpu->arch.pat; | |
2229 | else { /* Variable MTRRs */ | |
2230 | int idx, is_mtrr_mask; | |
2231 | u64 *pt; | |
2232 | ||
2233 | idx = (msr - 0x200) / 2; | |
2234 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
2235 | if (!is_mtrr_mask) | |
2236 | pt = | |
2237 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
2238 | else | |
2239 | pt = | |
2240 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
2241 | *pdata = *pt; | |
2242 | } | |
2243 | ||
2244 | return 0; | |
2245 | } | |
2246 | ||
2247 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) | |
2248 | { | |
2249 | u64 data; | |
2250 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
2251 | unsigned bank_num = mcg_cap & 0xff; | |
2252 | ||
2253 | switch (msr) { | |
2254 | case MSR_IA32_P5_MC_ADDR: | |
2255 | case MSR_IA32_P5_MC_TYPE: | |
2256 | data = 0; | |
2257 | break; | |
2258 | case MSR_IA32_MCG_CAP: | |
2259 | data = vcpu->arch.mcg_cap; | |
2260 | break; | |
2261 | case MSR_IA32_MCG_CTL: | |
2262 | if (!(mcg_cap & MCG_CTL_P)) | |
2263 | return 1; | |
2264 | data = vcpu->arch.mcg_ctl; | |
2265 | break; | |
2266 | case MSR_IA32_MCG_STATUS: | |
2267 | data = vcpu->arch.mcg_status; | |
2268 | break; | |
2269 | default: | |
2270 | if (msr >= MSR_IA32_MC0_CTL && | |
2271 | msr < MSR_IA32_MC0_CTL + 4 * bank_num) { | |
2272 | u32 offset = msr - MSR_IA32_MC0_CTL; | |
2273 | data = vcpu->arch.mce_banks[offset]; | |
2274 | break; | |
2275 | } | |
2276 | return 1; | |
2277 | } | |
2278 | *pdata = data; | |
2279 | return 0; | |
2280 | } | |
2281 | ||
2282 | static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) | |
2283 | { | |
2284 | u64 data = 0; | |
2285 | struct kvm *kvm = vcpu->kvm; | |
2286 | ||
2287 | switch (msr) { | |
2288 | case HV_X64_MSR_GUEST_OS_ID: | |
2289 | data = kvm->arch.hv_guest_os_id; | |
2290 | break; | |
2291 | case HV_X64_MSR_HYPERCALL: | |
2292 | data = kvm->arch.hv_hypercall; | |
2293 | break; | |
2294 | default: | |
2295 | vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); | |
2296 | return 1; | |
2297 | } | |
2298 | ||
2299 | *pdata = data; | |
2300 | return 0; | |
2301 | } | |
2302 | ||
2303 | static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) | |
2304 | { | |
2305 | u64 data = 0; | |
2306 | ||
2307 | switch (msr) { | |
2308 | case HV_X64_MSR_VP_INDEX: { | |
2309 | int r; | |
2310 | struct kvm_vcpu *v; | |
2311 | kvm_for_each_vcpu(r, v, vcpu->kvm) | |
2312 | if (v == vcpu) | |
2313 | data = r; | |
2314 | break; | |
2315 | } | |
2316 | case HV_X64_MSR_EOI: | |
2317 | return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata); | |
2318 | case HV_X64_MSR_ICR: | |
2319 | return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata); | |
2320 | case HV_X64_MSR_TPR: | |
2321 | return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata); | |
2322 | case HV_X64_MSR_APIC_ASSIST_PAGE: | |
2323 | data = vcpu->arch.hv_vapic; | |
2324 | break; | |
2325 | default: | |
2326 | vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); | |
2327 | return 1; | |
2328 | } | |
2329 | *pdata = data; | |
2330 | return 0; | |
2331 | } | |
2332 | ||
2333 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) | |
2334 | { | |
2335 | u64 data; | |
2336 | ||
2337 | switch (msr) { | |
2338 | case MSR_IA32_PLATFORM_ID: | |
2339 | case MSR_IA32_EBL_CR_POWERON: | |
2340 | case MSR_IA32_DEBUGCTLMSR: | |
2341 | case MSR_IA32_LASTBRANCHFROMIP: | |
2342 | case MSR_IA32_LASTBRANCHTOIP: | |
2343 | case MSR_IA32_LASTINTFROMIP: | |
2344 | case MSR_IA32_LASTINTTOIP: | |
2345 | case MSR_K8_SYSCFG: | |
2346 | case MSR_K7_HWCR: | |
2347 | case MSR_VM_HSAVE_PA: | |
2348 | case MSR_K7_EVNTSEL0: | |
2349 | case MSR_K7_PERFCTR0: | |
2350 | case MSR_K8_INT_PENDING_MSG: | |
2351 | case MSR_AMD64_NB_CFG: | |
2352 | case MSR_FAM10H_MMIO_CONF_BASE: | |
2353 | case MSR_AMD64_BU_CFG2: | |
2354 | data = 0; | |
2355 | break; | |
2356 | case MSR_P6_PERFCTR0: | |
2357 | case MSR_P6_PERFCTR1: | |
2358 | case MSR_P6_EVNTSEL0: | |
2359 | case MSR_P6_EVNTSEL1: | |
2360 | if (kvm_pmu_msr(vcpu, msr)) | |
2361 | return kvm_pmu_get_msr(vcpu, msr, pdata); | |
2362 | data = 0; | |
2363 | break; | |
2364 | case MSR_IA32_UCODE_REV: | |
2365 | data = 0x100000000ULL; | |
2366 | break; | |
2367 | case MSR_MTRRcap: | |
2368 | data = 0x500 | KVM_NR_VAR_MTRR; | |
2369 | break; | |
2370 | case 0x200 ... 0x2ff: | |
2371 | return get_msr_mtrr(vcpu, msr, pdata); | |
2372 | case 0xcd: /* fsb frequency */ | |
2373 | data = 3; | |
2374 | break; | |
2375 | /* | |
2376 | * MSR_EBC_FREQUENCY_ID | |
2377 | * Conservative value valid for even the basic CPU models. | |
2378 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
2379 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
2380 | * and 266MHz for model 3, or 4. Set Core Clock | |
2381 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
2382 | * 31:24) even though these are only valid for CPU | |
2383 | * models > 2, however guests may end up dividing or | |
2384 | * multiplying by zero otherwise. | |
2385 | */ | |
2386 | case MSR_EBC_FREQUENCY_ID: | |
2387 | data = 1 << 24; | |
2388 | break; | |
2389 | case MSR_IA32_APICBASE: | |
2390 | data = kvm_get_apic_base(vcpu); | |
2391 | break; | |
2392 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: | |
2393 | return kvm_x2apic_msr_read(vcpu, msr, pdata); | |
2394 | break; | |
2395 | case MSR_IA32_TSCDEADLINE: | |
2396 | data = kvm_get_lapic_tscdeadline_msr(vcpu); | |
2397 | break; | |
2398 | case MSR_IA32_TSC_ADJUST: | |
2399 | data = (u64)vcpu->arch.ia32_tsc_adjust_msr; | |
2400 | break; | |
2401 | case MSR_IA32_MISC_ENABLE: | |
2402 | data = vcpu->arch.ia32_misc_enable_msr; | |
2403 | break; | |
2404 | case MSR_IA32_PERF_STATUS: | |
2405 | /* TSC increment by tick */ | |
2406 | data = 1000ULL; | |
2407 | /* CPU multiplier */ | |
2408 | data |= (((uint64_t)4ULL) << 40); | |
2409 | break; | |
2410 | case MSR_EFER: | |
2411 | data = vcpu->arch.efer; | |
2412 | break; | |
2413 | case MSR_KVM_WALL_CLOCK: | |
2414 | case MSR_KVM_WALL_CLOCK_NEW: | |
2415 | data = vcpu->kvm->arch.wall_clock; | |
2416 | break; | |
2417 | case MSR_KVM_SYSTEM_TIME: | |
2418 | case MSR_KVM_SYSTEM_TIME_NEW: | |
2419 | data = vcpu->arch.time; | |
2420 | break; | |
2421 | case MSR_KVM_ASYNC_PF_EN: | |
2422 | data = vcpu->arch.apf.msr_val; | |
2423 | break; | |
2424 | case MSR_KVM_STEAL_TIME: | |
2425 | data = vcpu->arch.st.msr_val; | |
2426 | break; | |
2427 | case MSR_KVM_PV_EOI_EN: | |
2428 | data = vcpu->arch.pv_eoi.msr_val; | |
2429 | break; | |
2430 | case MSR_IA32_P5_MC_ADDR: | |
2431 | case MSR_IA32_P5_MC_TYPE: | |
2432 | case MSR_IA32_MCG_CAP: | |
2433 | case MSR_IA32_MCG_CTL: | |
2434 | case MSR_IA32_MCG_STATUS: | |
2435 | case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: | |
2436 | return get_msr_mce(vcpu, msr, pdata); | |
2437 | case MSR_K7_CLK_CTL: | |
2438 | /* | |
2439 | * Provide expected ramp-up count for K7. All other | |
2440 | * are set to zero, indicating minimum divisors for | |
2441 | * every field. | |
2442 | * | |
2443 | * This prevents guest kernels on AMD host with CPU | |
2444 | * type 6, model 8 and higher from exploding due to | |
2445 | * the rdmsr failing. | |
2446 | */ | |
2447 | data = 0x20000000; | |
2448 | break; | |
2449 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: | |
2450 | if (kvm_hv_msr_partition_wide(msr)) { | |
2451 | int r; | |
2452 | mutex_lock(&vcpu->kvm->lock); | |
2453 | r = get_msr_hyperv_pw(vcpu, msr, pdata); | |
2454 | mutex_unlock(&vcpu->kvm->lock); | |
2455 | return r; | |
2456 | } else | |
2457 | return get_msr_hyperv(vcpu, msr, pdata); | |
2458 | break; | |
2459 | case MSR_IA32_BBL_CR_CTL3: | |
2460 | /* This legacy MSR exists but isn't fully documented in current | |
2461 | * silicon. It is however accessed by winxp in very narrow | |
2462 | * scenarios where it sets bit #19, itself documented as | |
2463 | * a "reserved" bit. Best effort attempt to source coherent | |
2464 | * read data here should the balance of the register be | |
2465 | * interpreted by the guest: | |
2466 | * | |
2467 | * L2 cache control register 3: 64GB range, 256KB size, | |
2468 | * enabled, latency 0x1, configured | |
2469 | */ | |
2470 | data = 0xbe702111; | |
2471 | break; | |
2472 | case MSR_AMD64_OSVW_ID_LENGTH: | |
2473 | if (!guest_cpuid_has_osvw(vcpu)) | |
2474 | return 1; | |
2475 | data = vcpu->arch.osvw.length; | |
2476 | break; | |
2477 | case MSR_AMD64_OSVW_STATUS: | |
2478 | if (!guest_cpuid_has_osvw(vcpu)) | |
2479 | return 1; | |
2480 | data = vcpu->arch.osvw.status; | |
2481 | break; | |
2482 | default: | |
2483 | if (kvm_pmu_msr(vcpu, msr)) | |
2484 | return kvm_pmu_get_msr(vcpu, msr, pdata); | |
2485 | if (!ignore_msrs) { | |
2486 | vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr); | |
2487 | return 1; | |
2488 | } else { | |
2489 | vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr); | |
2490 | data = 0; | |
2491 | } | |
2492 | break; | |
2493 | } | |
2494 | *pdata = data; | |
2495 | return 0; | |
2496 | } | |
2497 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
2498 | ||
2499 | /* | |
2500 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
2501 | * | |
2502 | * @return number of msrs set successfully. | |
2503 | */ | |
2504 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
2505 | struct kvm_msr_entry *entries, | |
2506 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
2507 | unsigned index, u64 *data)) | |
2508 | { | |
2509 | int i, idx; | |
2510 | ||
2511 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
2512 | for (i = 0; i < msrs->nmsrs; ++i) | |
2513 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
2514 | break; | |
2515 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
2516 | ||
2517 | return i; | |
2518 | } | |
2519 | ||
2520 | /* | |
2521 | * Read or write a bunch of msrs. Parameters are user addresses. | |
2522 | * | |
2523 | * @return number of msrs set successfully. | |
2524 | */ | |
2525 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
2526 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
2527 | unsigned index, u64 *data), | |
2528 | int writeback) | |
2529 | { | |
2530 | struct kvm_msrs msrs; | |
2531 | struct kvm_msr_entry *entries; | |
2532 | int r, n; | |
2533 | unsigned size; | |
2534 | ||
2535 | r = -EFAULT; | |
2536 | if (copy_from_user(&msrs, user_msrs, sizeof msrs)) | |
2537 | goto out; | |
2538 | ||
2539 | r = -E2BIG; | |
2540 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
2541 | goto out; | |
2542 | ||
2543 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; | |
2544 | entries = memdup_user(user_msrs->entries, size); | |
2545 | if (IS_ERR(entries)) { | |
2546 | r = PTR_ERR(entries); | |
2547 | goto out; | |
2548 | } | |
2549 | ||
2550 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
2551 | if (r < 0) | |
2552 | goto out_free; | |
2553 | ||
2554 | r = -EFAULT; | |
2555 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
2556 | goto out_free; | |
2557 | ||
2558 | r = n; | |
2559 | ||
2560 | out_free: | |
2561 | kfree(entries); | |
2562 | out: | |
2563 | return r; | |
2564 | } | |
2565 | ||
2566 | int kvm_dev_ioctl_check_extension(long ext) | |
2567 | { | |
2568 | int r; | |
2569 | ||
2570 | switch (ext) { | |
2571 | case KVM_CAP_IRQCHIP: | |
2572 | case KVM_CAP_HLT: | |
2573 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
2574 | case KVM_CAP_SET_TSS_ADDR: | |
2575 | case KVM_CAP_EXT_CPUID: | |
2576 | case KVM_CAP_EXT_EMUL_CPUID: | |
2577 | case KVM_CAP_CLOCKSOURCE: | |
2578 | case KVM_CAP_PIT: | |
2579 | case KVM_CAP_NOP_IO_DELAY: | |
2580 | case KVM_CAP_MP_STATE: | |
2581 | case KVM_CAP_SYNC_MMU: | |
2582 | case KVM_CAP_USER_NMI: | |
2583 | case KVM_CAP_REINJECT_CONTROL: | |
2584 | case KVM_CAP_IRQ_INJECT_STATUS: | |
2585 | case KVM_CAP_IRQFD: | |
2586 | case KVM_CAP_IOEVENTFD: | |
2587 | case KVM_CAP_PIT2: | |
2588 | case KVM_CAP_PIT_STATE2: | |
2589 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: | |
2590 | case KVM_CAP_XEN_HVM: | |
2591 | case KVM_CAP_ADJUST_CLOCK: | |
2592 | case KVM_CAP_VCPU_EVENTS: | |
2593 | case KVM_CAP_HYPERV: | |
2594 | case KVM_CAP_HYPERV_VAPIC: | |
2595 | case KVM_CAP_HYPERV_SPIN: | |
2596 | case KVM_CAP_PCI_SEGMENT: | |
2597 | case KVM_CAP_DEBUGREGS: | |
2598 | case KVM_CAP_X86_ROBUST_SINGLESTEP: | |
2599 | case KVM_CAP_XSAVE: | |
2600 | case KVM_CAP_ASYNC_PF: | |
2601 | case KVM_CAP_GET_TSC_KHZ: | |
2602 | case KVM_CAP_KVMCLOCK_CTRL: | |
2603 | case KVM_CAP_READONLY_MEM: | |
2604 | #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT | |
2605 | case KVM_CAP_ASSIGN_DEV_IRQ: | |
2606 | case KVM_CAP_PCI_2_3: | |
2607 | #endif | |
2608 | r = 1; | |
2609 | break; | |
2610 | case KVM_CAP_COALESCED_MMIO: | |
2611 | r = KVM_COALESCED_MMIO_PAGE_OFFSET; | |
2612 | break; | |
2613 | case KVM_CAP_VAPIC: | |
2614 | r = !kvm_x86_ops->cpu_has_accelerated_tpr(); | |
2615 | break; | |
2616 | case KVM_CAP_NR_VCPUS: | |
2617 | r = KVM_SOFT_MAX_VCPUS; | |
2618 | break; | |
2619 | case KVM_CAP_MAX_VCPUS: | |
2620 | r = KVM_MAX_VCPUS; | |
2621 | break; | |
2622 | case KVM_CAP_NR_MEMSLOTS: | |
2623 | r = KVM_USER_MEM_SLOTS; | |
2624 | break; | |
2625 | case KVM_CAP_PV_MMU: /* obsolete */ | |
2626 | r = 0; | |
2627 | break; | |
2628 | #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT | |
2629 | case KVM_CAP_IOMMU: | |
2630 | r = iommu_present(&pci_bus_type); | |
2631 | break; | |
2632 | #endif | |
2633 | case KVM_CAP_MCE: | |
2634 | r = KVM_MAX_MCE_BANKS; | |
2635 | break; | |
2636 | case KVM_CAP_XCRS: | |
2637 | r = cpu_has_xsave; | |
2638 | break; | |
2639 | case KVM_CAP_TSC_CONTROL: | |
2640 | r = kvm_has_tsc_control; | |
2641 | break; | |
2642 | case KVM_CAP_TSC_DEADLINE_TIMER: | |
2643 | r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER); | |
2644 | break; | |
2645 | default: | |
2646 | r = 0; | |
2647 | break; | |
2648 | } | |
2649 | return r; | |
2650 | ||
2651 | } | |
2652 | ||
2653 | long kvm_arch_dev_ioctl(struct file *filp, | |
2654 | unsigned int ioctl, unsigned long arg) | |
2655 | { | |
2656 | void __user *argp = (void __user *)arg; | |
2657 | long r; | |
2658 | ||
2659 | switch (ioctl) { | |
2660 | case KVM_GET_MSR_INDEX_LIST: { | |
2661 | struct kvm_msr_list __user *user_msr_list = argp; | |
2662 | struct kvm_msr_list msr_list; | |
2663 | unsigned n; | |
2664 | ||
2665 | r = -EFAULT; | |
2666 | if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) | |
2667 | goto out; | |
2668 | n = msr_list.nmsrs; | |
2669 | msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs); | |
2670 | if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) | |
2671 | goto out; | |
2672 | r = -E2BIG; | |
2673 | if (n < msr_list.nmsrs) | |
2674 | goto out; | |
2675 | r = -EFAULT; | |
2676 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
2677 | num_msrs_to_save * sizeof(u32))) | |
2678 | goto out; | |
2679 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, | |
2680 | &emulated_msrs, | |
2681 | ARRAY_SIZE(emulated_msrs) * sizeof(u32))) | |
2682 | goto out; | |
2683 | r = 0; | |
2684 | break; | |
2685 | } | |
2686 | case KVM_GET_SUPPORTED_CPUID: | |
2687 | case KVM_GET_EMULATED_CPUID: { | |
2688 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2689 | struct kvm_cpuid2 cpuid; | |
2690 | ||
2691 | r = -EFAULT; | |
2692 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2693 | goto out; | |
2694 | ||
2695 | r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, | |
2696 | ioctl); | |
2697 | if (r) | |
2698 | goto out; | |
2699 | ||
2700 | r = -EFAULT; | |
2701 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
2702 | goto out; | |
2703 | r = 0; | |
2704 | break; | |
2705 | } | |
2706 | case KVM_X86_GET_MCE_CAP_SUPPORTED: { | |
2707 | u64 mce_cap; | |
2708 | ||
2709 | mce_cap = KVM_MCE_CAP_SUPPORTED; | |
2710 | r = -EFAULT; | |
2711 | if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) | |
2712 | goto out; | |
2713 | r = 0; | |
2714 | break; | |
2715 | } | |
2716 | default: | |
2717 | r = -EINVAL; | |
2718 | } | |
2719 | out: | |
2720 | return r; | |
2721 | } | |
2722 | ||
2723 | static void wbinvd_ipi(void *garbage) | |
2724 | { | |
2725 | wbinvd(); | |
2726 | } | |
2727 | ||
2728 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
2729 | { | |
2730 | return kvm_arch_has_noncoherent_dma(vcpu->kvm); | |
2731 | } | |
2732 | ||
2733 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) | |
2734 | { | |
2735 | /* Address WBINVD may be executed by guest */ | |
2736 | if (need_emulate_wbinvd(vcpu)) { | |
2737 | if (kvm_x86_ops->has_wbinvd_exit()) | |
2738 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
2739 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
2740 | smp_call_function_single(vcpu->cpu, | |
2741 | wbinvd_ipi, NULL, 1); | |
2742 | } | |
2743 | ||
2744 | kvm_x86_ops->vcpu_load(vcpu, cpu); | |
2745 | ||
2746 | /* Apply any externally detected TSC adjustments (due to suspend) */ | |
2747 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
2748 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
2749 | vcpu->arch.tsc_offset_adjustment = 0; | |
2750 | set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests); | |
2751 | } | |
2752 | ||
2753 | if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { | |
2754 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : | |
2755 | native_read_tsc() - vcpu->arch.last_host_tsc; | |
2756 | if (tsc_delta < 0) | |
2757 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
2758 | if (check_tsc_unstable()) { | |
2759 | u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu, | |
2760 | vcpu->arch.last_guest_tsc); | |
2761 | kvm_x86_ops->write_tsc_offset(vcpu, offset); | |
2762 | vcpu->arch.tsc_catchup = 1; | |
2763 | } | |
2764 | /* | |
2765 | * On a host with synchronized TSC, there is no need to update | |
2766 | * kvmclock on vcpu->cpu migration | |
2767 | */ | |
2768 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
2769 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); | |
2770 | if (vcpu->cpu != cpu) | |
2771 | kvm_migrate_timers(vcpu); | |
2772 | vcpu->cpu = cpu; | |
2773 | } | |
2774 | ||
2775 | accumulate_steal_time(vcpu); | |
2776 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); | |
2777 | } | |
2778 | ||
2779 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) | |
2780 | { | |
2781 | kvm_x86_ops->vcpu_put(vcpu); | |
2782 | kvm_put_guest_fpu(vcpu); | |
2783 | vcpu->arch.last_host_tsc = native_read_tsc(); | |
2784 | } | |
2785 | ||
2786 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, | |
2787 | struct kvm_lapic_state *s) | |
2788 | { | |
2789 | kvm_x86_ops->sync_pir_to_irr(vcpu); | |
2790 | memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); | |
2791 | ||
2792 | return 0; | |
2793 | } | |
2794 | ||
2795 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
2796 | struct kvm_lapic_state *s) | |
2797 | { | |
2798 | kvm_apic_post_state_restore(vcpu, s); | |
2799 | update_cr8_intercept(vcpu); | |
2800 | ||
2801 | return 0; | |
2802 | } | |
2803 | ||
2804 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, | |
2805 | struct kvm_interrupt *irq) | |
2806 | { | |
2807 | if (irq->irq >= KVM_NR_INTERRUPTS) | |
2808 | return -EINVAL; | |
2809 | if (irqchip_in_kernel(vcpu->kvm)) | |
2810 | return -ENXIO; | |
2811 | ||
2812 | kvm_queue_interrupt(vcpu, irq->irq, false); | |
2813 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
2814 | ||
2815 | return 0; | |
2816 | } | |
2817 | ||
2818 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) | |
2819 | { | |
2820 | kvm_inject_nmi(vcpu); | |
2821 | ||
2822 | return 0; | |
2823 | } | |
2824 | ||
2825 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, | |
2826 | struct kvm_tpr_access_ctl *tac) | |
2827 | { | |
2828 | if (tac->flags) | |
2829 | return -EINVAL; | |
2830 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
2831 | return 0; | |
2832 | } | |
2833 | ||
2834 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, | |
2835 | u64 mcg_cap) | |
2836 | { | |
2837 | int r; | |
2838 | unsigned bank_num = mcg_cap & 0xff, bank; | |
2839 | ||
2840 | r = -EINVAL; | |
2841 | if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) | |
2842 | goto out; | |
2843 | if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) | |
2844 | goto out; | |
2845 | r = 0; | |
2846 | vcpu->arch.mcg_cap = mcg_cap; | |
2847 | /* Init IA32_MCG_CTL to all 1s */ | |
2848 | if (mcg_cap & MCG_CTL_P) | |
2849 | vcpu->arch.mcg_ctl = ~(u64)0; | |
2850 | /* Init IA32_MCi_CTL to all 1s */ | |
2851 | for (bank = 0; bank < bank_num; bank++) | |
2852 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
2853 | out: | |
2854 | return r; | |
2855 | } | |
2856 | ||
2857 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
2858 | struct kvm_x86_mce *mce) | |
2859 | { | |
2860 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
2861 | unsigned bank_num = mcg_cap & 0xff; | |
2862 | u64 *banks = vcpu->arch.mce_banks; | |
2863 | ||
2864 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
2865 | return -EINVAL; | |
2866 | /* | |
2867 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
2868 | * reporting is disabled | |
2869 | */ | |
2870 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
2871 | vcpu->arch.mcg_ctl != ~(u64)0) | |
2872 | return 0; | |
2873 | banks += 4 * mce->bank; | |
2874 | /* | |
2875 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
2876 | * reporting is disabled for the bank | |
2877 | */ | |
2878 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
2879 | return 0; | |
2880 | if (mce->status & MCI_STATUS_UC) { | |
2881 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
2882 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { | |
2883 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
2884 | return 0; | |
2885 | } | |
2886 | if (banks[1] & MCI_STATUS_VAL) | |
2887 | mce->status |= MCI_STATUS_OVER; | |
2888 | banks[2] = mce->addr; | |
2889 | banks[3] = mce->misc; | |
2890 | vcpu->arch.mcg_status = mce->mcg_status; | |
2891 | banks[1] = mce->status; | |
2892 | kvm_queue_exception(vcpu, MC_VECTOR); | |
2893 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
2894 | || !(banks[1] & MCI_STATUS_UC)) { | |
2895 | if (banks[1] & MCI_STATUS_VAL) | |
2896 | mce->status |= MCI_STATUS_OVER; | |
2897 | banks[2] = mce->addr; | |
2898 | banks[3] = mce->misc; | |
2899 | banks[1] = mce->status; | |
2900 | } else | |
2901 | banks[1] |= MCI_STATUS_OVER; | |
2902 | return 0; | |
2903 | } | |
2904 | ||
2905 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, | |
2906 | struct kvm_vcpu_events *events) | |
2907 | { | |
2908 | process_nmi(vcpu); | |
2909 | events->exception.injected = | |
2910 | vcpu->arch.exception.pending && | |
2911 | !kvm_exception_is_soft(vcpu->arch.exception.nr); | |
2912 | events->exception.nr = vcpu->arch.exception.nr; | |
2913 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
2914 | events->exception.pad = 0; | |
2915 | events->exception.error_code = vcpu->arch.exception.error_code; | |
2916 | ||
2917 | events->interrupt.injected = | |
2918 | vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; | |
2919 | events->interrupt.nr = vcpu->arch.interrupt.nr; | |
2920 | events->interrupt.soft = 0; | |
2921 | events->interrupt.shadow = | |
2922 | kvm_x86_ops->get_interrupt_shadow(vcpu, | |
2923 | KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI); | |
2924 | ||
2925 | events->nmi.injected = vcpu->arch.nmi_injected; | |
2926 | events->nmi.pending = vcpu->arch.nmi_pending != 0; | |
2927 | events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); | |
2928 | events->nmi.pad = 0; | |
2929 | ||
2930 | events->sipi_vector = 0; /* never valid when reporting to user space */ | |
2931 | ||
2932 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING | |
2933 | | KVM_VCPUEVENT_VALID_SHADOW); | |
2934 | memset(&events->reserved, 0, sizeof(events->reserved)); | |
2935 | } | |
2936 | ||
2937 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, | |
2938 | struct kvm_vcpu_events *events) | |
2939 | { | |
2940 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING | |
2941 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR | |
2942 | | KVM_VCPUEVENT_VALID_SHADOW)) | |
2943 | return -EINVAL; | |
2944 | ||
2945 | process_nmi(vcpu); | |
2946 | vcpu->arch.exception.pending = events->exception.injected; | |
2947 | vcpu->arch.exception.nr = events->exception.nr; | |
2948 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
2949 | vcpu->arch.exception.error_code = events->exception.error_code; | |
2950 | ||
2951 | vcpu->arch.interrupt.pending = events->interrupt.injected; | |
2952 | vcpu->arch.interrupt.nr = events->interrupt.nr; | |
2953 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
2954 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) | |
2955 | kvm_x86_ops->set_interrupt_shadow(vcpu, | |
2956 | events->interrupt.shadow); | |
2957 | ||
2958 | vcpu->arch.nmi_injected = events->nmi.injected; | |
2959 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) | |
2960 | vcpu->arch.nmi_pending = events->nmi.pending; | |
2961 | kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); | |
2962 | ||
2963 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && | |
2964 | kvm_vcpu_has_lapic(vcpu)) | |
2965 | vcpu->arch.apic->sipi_vector = events->sipi_vector; | |
2966 | ||
2967 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
2968 | ||
2969 | return 0; | |
2970 | } | |
2971 | ||
2972 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, | |
2973 | struct kvm_debugregs *dbgregs) | |
2974 | { | |
2975 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); | |
2976 | dbgregs->dr6 = vcpu->arch.dr6; | |
2977 | dbgregs->dr7 = vcpu->arch.dr7; | |
2978 | dbgregs->flags = 0; | |
2979 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); | |
2980 | } | |
2981 | ||
2982 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
2983 | struct kvm_debugregs *dbgregs) | |
2984 | { | |
2985 | if (dbgregs->flags) | |
2986 | return -EINVAL; | |
2987 | ||
2988 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); | |
2989 | vcpu->arch.dr6 = dbgregs->dr6; | |
2990 | vcpu->arch.dr7 = dbgregs->dr7; | |
2991 | ||
2992 | return 0; | |
2993 | } | |
2994 | ||
2995 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, | |
2996 | struct kvm_xsave *guest_xsave) | |
2997 | { | |
2998 | if (cpu_has_xsave) { | |
2999 | memcpy(guest_xsave->region, | |
3000 | &vcpu->arch.guest_fpu.state->xsave, | |
3001 | vcpu->arch.guest_xstate_size); | |
3002 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &= | |
3003 | vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE; | |
3004 | } else { | |
3005 | memcpy(guest_xsave->region, | |
3006 | &vcpu->arch.guest_fpu.state->fxsave, | |
3007 | sizeof(struct i387_fxsave_struct)); | |
3008 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = | |
3009 | XSTATE_FPSSE; | |
3010 | } | |
3011 | } | |
3012 | ||
3013 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, | |
3014 | struct kvm_xsave *guest_xsave) | |
3015 | { | |
3016 | u64 xstate_bv = | |
3017 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
3018 | ||
3019 | if (cpu_has_xsave) { | |
3020 | /* | |
3021 | * Here we allow setting states that are not present in | |
3022 | * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility | |
3023 | * with old userspace. | |
3024 | */ | |
3025 | if (xstate_bv & ~KVM_SUPPORTED_XCR0) | |
3026 | return -EINVAL; | |
3027 | if (xstate_bv & ~host_xcr0) | |
3028 | return -EINVAL; | |
3029 | memcpy(&vcpu->arch.guest_fpu.state->xsave, | |
3030 | guest_xsave->region, vcpu->arch.guest_xstate_size); | |
3031 | } else { | |
3032 | if (xstate_bv & ~XSTATE_FPSSE) | |
3033 | return -EINVAL; | |
3034 | memcpy(&vcpu->arch.guest_fpu.state->fxsave, | |
3035 | guest_xsave->region, sizeof(struct i387_fxsave_struct)); | |
3036 | } | |
3037 | return 0; | |
3038 | } | |
3039 | ||
3040 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
3041 | struct kvm_xcrs *guest_xcrs) | |
3042 | { | |
3043 | if (!cpu_has_xsave) { | |
3044 | guest_xcrs->nr_xcrs = 0; | |
3045 | return; | |
3046 | } | |
3047 | ||
3048 | guest_xcrs->nr_xcrs = 1; | |
3049 | guest_xcrs->flags = 0; | |
3050 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
3051 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
3052 | } | |
3053 | ||
3054 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
3055 | struct kvm_xcrs *guest_xcrs) | |
3056 | { | |
3057 | int i, r = 0; | |
3058 | ||
3059 | if (!cpu_has_xsave) | |
3060 | return -EINVAL; | |
3061 | ||
3062 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
3063 | return -EINVAL; | |
3064 | ||
3065 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
3066 | /* Only support XCR0 currently */ | |
3067 | if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { | |
3068 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, | |
3069 | guest_xcrs->xcrs[i].value); | |
3070 | break; | |
3071 | } | |
3072 | if (r) | |
3073 | r = -EINVAL; | |
3074 | return r; | |
3075 | } | |
3076 | ||
3077 | /* | |
3078 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
3079 | * stopped by the hypervisor. This function will be called from the host only. | |
3080 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
3081 | * does not support pv clocks. | |
3082 | */ | |
3083 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
3084 | { | |
3085 | if (!vcpu->arch.pv_time_enabled) | |
3086 | return -EINVAL; | |
3087 | vcpu->arch.pvclock_set_guest_stopped_request = true; | |
3088 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
3089 | return 0; | |
3090 | } | |
3091 | ||
3092 | long kvm_arch_vcpu_ioctl(struct file *filp, | |
3093 | unsigned int ioctl, unsigned long arg) | |
3094 | { | |
3095 | struct kvm_vcpu *vcpu = filp->private_data; | |
3096 | void __user *argp = (void __user *)arg; | |
3097 | int r; | |
3098 | union { | |
3099 | struct kvm_lapic_state *lapic; | |
3100 | struct kvm_xsave *xsave; | |
3101 | struct kvm_xcrs *xcrs; | |
3102 | void *buffer; | |
3103 | } u; | |
3104 | ||
3105 | u.buffer = NULL; | |
3106 | switch (ioctl) { | |
3107 | case KVM_GET_LAPIC: { | |
3108 | r = -EINVAL; | |
3109 | if (!vcpu->arch.apic) | |
3110 | goto out; | |
3111 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); | |
3112 | ||
3113 | r = -ENOMEM; | |
3114 | if (!u.lapic) | |
3115 | goto out; | |
3116 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); | |
3117 | if (r) | |
3118 | goto out; | |
3119 | r = -EFAULT; | |
3120 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) | |
3121 | goto out; | |
3122 | r = 0; | |
3123 | break; | |
3124 | } | |
3125 | case KVM_SET_LAPIC: { | |
3126 | r = -EINVAL; | |
3127 | if (!vcpu->arch.apic) | |
3128 | goto out; | |
3129 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); | |
3130 | if (IS_ERR(u.lapic)) | |
3131 | return PTR_ERR(u.lapic); | |
3132 | ||
3133 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); | |
3134 | break; | |
3135 | } | |
3136 | case KVM_INTERRUPT: { | |
3137 | struct kvm_interrupt irq; | |
3138 | ||
3139 | r = -EFAULT; | |
3140 | if (copy_from_user(&irq, argp, sizeof irq)) | |
3141 | goto out; | |
3142 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
3143 | break; | |
3144 | } | |
3145 | case KVM_NMI: { | |
3146 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
3147 | break; | |
3148 | } | |
3149 | case KVM_SET_CPUID: { | |
3150 | struct kvm_cpuid __user *cpuid_arg = argp; | |
3151 | struct kvm_cpuid cpuid; | |
3152 | ||
3153 | r = -EFAULT; | |
3154 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3155 | goto out; | |
3156 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
3157 | break; | |
3158 | } | |
3159 | case KVM_SET_CPUID2: { | |
3160 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
3161 | struct kvm_cpuid2 cpuid; | |
3162 | ||
3163 | r = -EFAULT; | |
3164 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3165 | goto out; | |
3166 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
3167 | cpuid_arg->entries); | |
3168 | break; | |
3169 | } | |
3170 | case KVM_GET_CPUID2: { | |
3171 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
3172 | struct kvm_cpuid2 cpuid; | |
3173 | ||
3174 | r = -EFAULT; | |
3175 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
3176 | goto out; | |
3177 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
3178 | cpuid_arg->entries); | |
3179 | if (r) | |
3180 | goto out; | |
3181 | r = -EFAULT; | |
3182 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
3183 | goto out; | |
3184 | r = 0; | |
3185 | break; | |
3186 | } | |
3187 | case KVM_GET_MSRS: | |
3188 | r = msr_io(vcpu, argp, kvm_get_msr, 1); | |
3189 | break; | |
3190 | case KVM_SET_MSRS: | |
3191 | r = msr_io(vcpu, argp, do_set_msr, 0); | |
3192 | break; | |
3193 | case KVM_TPR_ACCESS_REPORTING: { | |
3194 | struct kvm_tpr_access_ctl tac; | |
3195 | ||
3196 | r = -EFAULT; | |
3197 | if (copy_from_user(&tac, argp, sizeof tac)) | |
3198 | goto out; | |
3199 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
3200 | if (r) | |
3201 | goto out; | |
3202 | r = -EFAULT; | |
3203 | if (copy_to_user(argp, &tac, sizeof tac)) | |
3204 | goto out; | |
3205 | r = 0; | |
3206 | break; | |
3207 | }; | |
3208 | case KVM_SET_VAPIC_ADDR: { | |
3209 | struct kvm_vapic_addr va; | |
3210 | ||
3211 | r = -EINVAL; | |
3212 | if (!irqchip_in_kernel(vcpu->kvm)) | |
3213 | goto out; | |
3214 | r = -EFAULT; | |
3215 | if (copy_from_user(&va, argp, sizeof va)) | |
3216 | goto out; | |
3217 | r = 0; | |
3218 | kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); | |
3219 | break; | |
3220 | } | |
3221 | case KVM_X86_SETUP_MCE: { | |
3222 | u64 mcg_cap; | |
3223 | ||
3224 | r = -EFAULT; | |
3225 | if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) | |
3226 | goto out; | |
3227 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
3228 | break; | |
3229 | } | |
3230 | case KVM_X86_SET_MCE: { | |
3231 | struct kvm_x86_mce mce; | |
3232 | ||
3233 | r = -EFAULT; | |
3234 | if (copy_from_user(&mce, argp, sizeof mce)) | |
3235 | goto out; | |
3236 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
3237 | break; | |
3238 | } | |
3239 | case KVM_GET_VCPU_EVENTS: { | |
3240 | struct kvm_vcpu_events events; | |
3241 | ||
3242 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
3243 | ||
3244 | r = -EFAULT; | |
3245 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
3246 | break; | |
3247 | r = 0; | |
3248 | break; | |
3249 | } | |
3250 | case KVM_SET_VCPU_EVENTS: { | |
3251 | struct kvm_vcpu_events events; | |
3252 | ||
3253 | r = -EFAULT; | |
3254 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
3255 | break; | |
3256 | ||
3257 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
3258 | break; | |
3259 | } | |
3260 | case KVM_GET_DEBUGREGS: { | |
3261 | struct kvm_debugregs dbgregs; | |
3262 | ||
3263 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
3264 | ||
3265 | r = -EFAULT; | |
3266 | if (copy_to_user(argp, &dbgregs, | |
3267 | sizeof(struct kvm_debugregs))) | |
3268 | break; | |
3269 | r = 0; | |
3270 | break; | |
3271 | } | |
3272 | case KVM_SET_DEBUGREGS: { | |
3273 | struct kvm_debugregs dbgregs; | |
3274 | ||
3275 | r = -EFAULT; | |
3276 | if (copy_from_user(&dbgregs, argp, | |
3277 | sizeof(struct kvm_debugregs))) | |
3278 | break; | |
3279 | ||
3280 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
3281 | break; | |
3282 | } | |
3283 | case KVM_GET_XSAVE: { | |
3284 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); | |
3285 | r = -ENOMEM; | |
3286 | if (!u.xsave) | |
3287 | break; | |
3288 | ||
3289 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); | |
3290 | ||
3291 | r = -EFAULT; | |
3292 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) | |
3293 | break; | |
3294 | r = 0; | |
3295 | break; | |
3296 | } | |
3297 | case KVM_SET_XSAVE: { | |
3298 | u.xsave = memdup_user(argp, sizeof(*u.xsave)); | |
3299 | if (IS_ERR(u.xsave)) | |
3300 | return PTR_ERR(u.xsave); | |
3301 | ||
3302 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); | |
3303 | break; | |
3304 | } | |
3305 | case KVM_GET_XCRS: { | |
3306 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); | |
3307 | r = -ENOMEM; | |
3308 | if (!u.xcrs) | |
3309 | break; | |
3310 | ||
3311 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); | |
3312 | ||
3313 | r = -EFAULT; | |
3314 | if (copy_to_user(argp, u.xcrs, | |
3315 | sizeof(struct kvm_xcrs))) | |
3316 | break; | |
3317 | r = 0; | |
3318 | break; | |
3319 | } | |
3320 | case KVM_SET_XCRS: { | |
3321 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); | |
3322 | if (IS_ERR(u.xcrs)) | |
3323 | return PTR_ERR(u.xcrs); | |
3324 | ||
3325 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); | |
3326 | break; | |
3327 | } | |
3328 | case KVM_SET_TSC_KHZ: { | |
3329 | u32 user_tsc_khz; | |
3330 | ||
3331 | r = -EINVAL; | |
3332 | user_tsc_khz = (u32)arg; | |
3333 | ||
3334 | if (user_tsc_khz >= kvm_max_guest_tsc_khz) | |
3335 | goto out; | |
3336 | ||
3337 | if (user_tsc_khz == 0) | |
3338 | user_tsc_khz = tsc_khz; | |
3339 | ||
3340 | kvm_set_tsc_khz(vcpu, user_tsc_khz); | |
3341 | ||
3342 | r = 0; | |
3343 | goto out; | |
3344 | } | |
3345 | case KVM_GET_TSC_KHZ: { | |
3346 | r = vcpu->arch.virtual_tsc_khz; | |
3347 | goto out; | |
3348 | } | |
3349 | case KVM_KVMCLOCK_CTRL: { | |
3350 | r = kvm_set_guest_paused(vcpu); | |
3351 | goto out; | |
3352 | } | |
3353 | default: | |
3354 | r = -EINVAL; | |
3355 | } | |
3356 | out: | |
3357 | kfree(u.buffer); | |
3358 | return r; | |
3359 | } | |
3360 | ||
3361 | int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) | |
3362 | { | |
3363 | return VM_FAULT_SIGBUS; | |
3364 | } | |
3365 | ||
3366 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) | |
3367 | { | |
3368 | int ret; | |
3369 | ||
3370 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
3371 | return -EINVAL; | |
3372 | ret = kvm_x86_ops->set_tss_addr(kvm, addr); | |
3373 | return ret; | |
3374 | } | |
3375 | ||
3376 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, | |
3377 | u64 ident_addr) | |
3378 | { | |
3379 | kvm->arch.ept_identity_map_addr = ident_addr; | |
3380 | return 0; | |
3381 | } | |
3382 | ||
3383 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, | |
3384 | u32 kvm_nr_mmu_pages) | |
3385 | { | |
3386 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
3387 | return -EINVAL; | |
3388 | ||
3389 | mutex_lock(&kvm->slots_lock); | |
3390 | ||
3391 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
3392 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; | |
3393 | ||
3394 | mutex_unlock(&kvm->slots_lock); | |
3395 | return 0; | |
3396 | } | |
3397 | ||
3398 | static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) | |
3399 | { | |
3400 | return kvm->arch.n_max_mmu_pages; | |
3401 | } | |
3402 | ||
3403 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
3404 | { | |
3405 | int r; | |
3406 | ||
3407 | r = 0; | |
3408 | switch (chip->chip_id) { | |
3409 | case KVM_IRQCHIP_PIC_MASTER: | |
3410 | memcpy(&chip->chip.pic, | |
3411 | &pic_irqchip(kvm)->pics[0], | |
3412 | sizeof(struct kvm_pic_state)); | |
3413 | break; | |
3414 | case KVM_IRQCHIP_PIC_SLAVE: | |
3415 | memcpy(&chip->chip.pic, | |
3416 | &pic_irqchip(kvm)->pics[1], | |
3417 | sizeof(struct kvm_pic_state)); | |
3418 | break; | |
3419 | case KVM_IRQCHIP_IOAPIC: | |
3420 | r = kvm_get_ioapic(kvm, &chip->chip.ioapic); | |
3421 | break; | |
3422 | default: | |
3423 | r = -EINVAL; | |
3424 | break; | |
3425 | } | |
3426 | return r; | |
3427 | } | |
3428 | ||
3429 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
3430 | { | |
3431 | int r; | |
3432 | ||
3433 | r = 0; | |
3434 | switch (chip->chip_id) { | |
3435 | case KVM_IRQCHIP_PIC_MASTER: | |
3436 | spin_lock(&pic_irqchip(kvm)->lock); | |
3437 | memcpy(&pic_irqchip(kvm)->pics[0], | |
3438 | &chip->chip.pic, | |
3439 | sizeof(struct kvm_pic_state)); | |
3440 | spin_unlock(&pic_irqchip(kvm)->lock); | |
3441 | break; | |
3442 | case KVM_IRQCHIP_PIC_SLAVE: | |
3443 | spin_lock(&pic_irqchip(kvm)->lock); | |
3444 | memcpy(&pic_irqchip(kvm)->pics[1], | |
3445 | &chip->chip.pic, | |
3446 | sizeof(struct kvm_pic_state)); | |
3447 | spin_unlock(&pic_irqchip(kvm)->lock); | |
3448 | break; | |
3449 | case KVM_IRQCHIP_IOAPIC: | |
3450 | r = kvm_set_ioapic(kvm, &chip->chip.ioapic); | |
3451 | break; | |
3452 | default: | |
3453 | r = -EINVAL; | |
3454 | break; | |
3455 | } | |
3456 | kvm_pic_update_irq(pic_irqchip(kvm)); | |
3457 | return r; | |
3458 | } | |
3459 | ||
3460 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
3461 | { | |
3462 | int r = 0; | |
3463 | ||
3464 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3465 | memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); | |
3466 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
3467 | return r; | |
3468 | } | |
3469 | ||
3470 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
3471 | { | |
3472 | int r = 0; | |
3473 | ||
3474 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3475 | memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); | |
3476 | kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0); | |
3477 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
3478 | return r; | |
3479 | } | |
3480 | ||
3481 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3482 | { | |
3483 | int r = 0; | |
3484 | ||
3485 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3486 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
3487 | sizeof(ps->channels)); | |
3488 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
3489 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
3490 | memset(&ps->reserved, 0, sizeof(ps->reserved)); | |
3491 | return r; | |
3492 | } | |
3493 | ||
3494 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
3495 | { | |
3496 | int r = 0, start = 0; | |
3497 | u32 prev_legacy, cur_legacy; | |
3498 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3499 | prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3500 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
3501 | if (!prev_legacy && cur_legacy) | |
3502 | start = 1; | |
3503 | memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, | |
3504 | sizeof(kvm->arch.vpit->pit_state.channels)); | |
3505 | kvm->arch.vpit->pit_state.flags = ps->flags; | |
3506 | kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start); | |
3507 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
3508 | return r; | |
3509 | } | |
3510 | ||
3511 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, | |
3512 | struct kvm_reinject_control *control) | |
3513 | { | |
3514 | if (!kvm->arch.vpit) | |
3515 | return -ENXIO; | |
3516 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
3517 | kvm->arch.vpit->pit_state.reinject = control->pit_reinject; | |
3518 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
3519 | return 0; | |
3520 | } | |
3521 | ||
3522 | /** | |
3523 | * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot | |
3524 | * @kvm: kvm instance | |
3525 | * @log: slot id and address to which we copy the log | |
3526 | * | |
3527 | * We need to keep it in mind that VCPU threads can write to the bitmap | |
3528 | * concurrently. So, to avoid losing data, we keep the following order for | |
3529 | * each bit: | |
3530 | * | |
3531 | * 1. Take a snapshot of the bit and clear it if needed. | |
3532 | * 2. Write protect the corresponding page. | |
3533 | * 3. Flush TLB's if needed. | |
3534 | * 4. Copy the snapshot to the userspace. | |
3535 | * | |
3536 | * Between 2 and 3, the guest may write to the page using the remaining TLB | |
3537 | * entry. This is not a problem because the page will be reported dirty at | |
3538 | * step 4 using the snapshot taken before and step 3 ensures that successive | |
3539 | * writes will be logged for the next call. | |
3540 | */ | |
3541 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) | |
3542 | { | |
3543 | int r; | |
3544 | struct kvm_memory_slot *memslot; | |
3545 | unsigned long n, i; | |
3546 | unsigned long *dirty_bitmap; | |
3547 | unsigned long *dirty_bitmap_buffer; | |
3548 | bool is_dirty = false; | |
3549 | ||
3550 | mutex_lock(&kvm->slots_lock); | |
3551 | ||
3552 | r = -EINVAL; | |
3553 | if (log->slot >= KVM_USER_MEM_SLOTS) | |
3554 | goto out; | |
3555 | ||
3556 | memslot = id_to_memslot(kvm->memslots, log->slot); | |
3557 | ||
3558 | dirty_bitmap = memslot->dirty_bitmap; | |
3559 | r = -ENOENT; | |
3560 | if (!dirty_bitmap) | |
3561 | goto out; | |
3562 | ||
3563 | n = kvm_dirty_bitmap_bytes(memslot); | |
3564 | ||
3565 | dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long); | |
3566 | memset(dirty_bitmap_buffer, 0, n); | |
3567 | ||
3568 | spin_lock(&kvm->mmu_lock); | |
3569 | ||
3570 | for (i = 0; i < n / sizeof(long); i++) { | |
3571 | unsigned long mask; | |
3572 | gfn_t offset; | |
3573 | ||
3574 | if (!dirty_bitmap[i]) | |
3575 | continue; | |
3576 | ||
3577 | is_dirty = true; | |
3578 | ||
3579 | mask = xchg(&dirty_bitmap[i], 0); | |
3580 | dirty_bitmap_buffer[i] = mask; | |
3581 | ||
3582 | offset = i * BITS_PER_LONG; | |
3583 | kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask); | |
3584 | } | |
3585 | if (is_dirty) | |
3586 | kvm_flush_remote_tlbs(kvm); | |
3587 | ||
3588 | spin_unlock(&kvm->mmu_lock); | |
3589 | ||
3590 | r = -EFAULT; | |
3591 | if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n)) | |
3592 | goto out; | |
3593 | ||
3594 | r = 0; | |
3595 | out: | |
3596 | mutex_unlock(&kvm->slots_lock); | |
3597 | return r; | |
3598 | } | |
3599 | ||
3600 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, | |
3601 | bool line_status) | |
3602 | { | |
3603 | if (!irqchip_in_kernel(kvm)) | |
3604 | return -ENXIO; | |
3605 | ||
3606 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
3607 | irq_event->irq, irq_event->level, | |
3608 | line_status); | |
3609 | return 0; | |
3610 | } | |
3611 | ||
3612 | long kvm_arch_vm_ioctl(struct file *filp, | |
3613 | unsigned int ioctl, unsigned long arg) | |
3614 | { | |
3615 | struct kvm *kvm = filp->private_data; | |
3616 | void __user *argp = (void __user *)arg; | |
3617 | int r = -ENOTTY; | |
3618 | /* | |
3619 | * This union makes it completely explicit to gcc-3.x | |
3620 | * that these two variables' stack usage should be | |
3621 | * combined, not added together. | |
3622 | */ | |
3623 | union { | |
3624 | struct kvm_pit_state ps; | |
3625 | struct kvm_pit_state2 ps2; | |
3626 | struct kvm_pit_config pit_config; | |
3627 | } u; | |
3628 | ||
3629 | switch (ioctl) { | |
3630 | case KVM_SET_TSS_ADDR: | |
3631 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
3632 | break; | |
3633 | case KVM_SET_IDENTITY_MAP_ADDR: { | |
3634 | u64 ident_addr; | |
3635 | ||
3636 | r = -EFAULT; | |
3637 | if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) | |
3638 | goto out; | |
3639 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); | |
3640 | break; | |
3641 | } | |
3642 | case KVM_SET_NR_MMU_PAGES: | |
3643 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
3644 | break; | |
3645 | case KVM_GET_NR_MMU_PAGES: | |
3646 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
3647 | break; | |
3648 | case KVM_CREATE_IRQCHIP: { | |
3649 | struct kvm_pic *vpic; | |
3650 | ||
3651 | mutex_lock(&kvm->lock); | |
3652 | r = -EEXIST; | |
3653 | if (kvm->arch.vpic) | |
3654 | goto create_irqchip_unlock; | |
3655 | r = -EINVAL; | |
3656 | if (atomic_read(&kvm->online_vcpus)) | |
3657 | goto create_irqchip_unlock; | |
3658 | r = -ENOMEM; | |
3659 | vpic = kvm_create_pic(kvm); | |
3660 | if (vpic) { | |
3661 | r = kvm_ioapic_init(kvm); | |
3662 | if (r) { | |
3663 | mutex_lock(&kvm->slots_lock); | |
3664 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, | |
3665 | &vpic->dev_master); | |
3666 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, | |
3667 | &vpic->dev_slave); | |
3668 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, | |
3669 | &vpic->dev_eclr); | |
3670 | mutex_unlock(&kvm->slots_lock); | |
3671 | kfree(vpic); | |
3672 | goto create_irqchip_unlock; | |
3673 | } | |
3674 | } else | |
3675 | goto create_irqchip_unlock; | |
3676 | smp_wmb(); | |
3677 | kvm->arch.vpic = vpic; | |
3678 | smp_wmb(); | |
3679 | r = kvm_setup_default_irq_routing(kvm); | |
3680 | if (r) { | |
3681 | mutex_lock(&kvm->slots_lock); | |
3682 | mutex_lock(&kvm->irq_lock); | |
3683 | kvm_ioapic_destroy(kvm); | |
3684 | kvm_destroy_pic(kvm); | |
3685 | mutex_unlock(&kvm->irq_lock); | |
3686 | mutex_unlock(&kvm->slots_lock); | |
3687 | } | |
3688 | create_irqchip_unlock: | |
3689 | mutex_unlock(&kvm->lock); | |
3690 | break; | |
3691 | } | |
3692 | case KVM_CREATE_PIT: | |
3693 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; | |
3694 | goto create_pit; | |
3695 | case KVM_CREATE_PIT2: | |
3696 | r = -EFAULT; | |
3697 | if (copy_from_user(&u.pit_config, argp, | |
3698 | sizeof(struct kvm_pit_config))) | |
3699 | goto out; | |
3700 | create_pit: | |
3701 | mutex_lock(&kvm->slots_lock); | |
3702 | r = -EEXIST; | |
3703 | if (kvm->arch.vpit) | |
3704 | goto create_pit_unlock; | |
3705 | r = -ENOMEM; | |
3706 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); | |
3707 | if (kvm->arch.vpit) | |
3708 | r = 0; | |
3709 | create_pit_unlock: | |
3710 | mutex_unlock(&kvm->slots_lock); | |
3711 | break; | |
3712 | case KVM_GET_IRQCHIP: { | |
3713 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
3714 | struct kvm_irqchip *chip; | |
3715 | ||
3716 | chip = memdup_user(argp, sizeof(*chip)); | |
3717 | if (IS_ERR(chip)) { | |
3718 | r = PTR_ERR(chip); | |
3719 | goto out; | |
3720 | } | |
3721 | ||
3722 | r = -ENXIO; | |
3723 | if (!irqchip_in_kernel(kvm)) | |
3724 | goto get_irqchip_out; | |
3725 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
3726 | if (r) | |
3727 | goto get_irqchip_out; | |
3728 | r = -EFAULT; | |
3729 | if (copy_to_user(argp, chip, sizeof *chip)) | |
3730 | goto get_irqchip_out; | |
3731 | r = 0; | |
3732 | get_irqchip_out: | |
3733 | kfree(chip); | |
3734 | break; | |
3735 | } | |
3736 | case KVM_SET_IRQCHIP: { | |
3737 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
3738 | struct kvm_irqchip *chip; | |
3739 | ||
3740 | chip = memdup_user(argp, sizeof(*chip)); | |
3741 | if (IS_ERR(chip)) { | |
3742 | r = PTR_ERR(chip); | |
3743 | goto out; | |
3744 | } | |
3745 | ||
3746 | r = -ENXIO; | |
3747 | if (!irqchip_in_kernel(kvm)) | |
3748 | goto set_irqchip_out; | |
3749 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
3750 | if (r) | |
3751 | goto set_irqchip_out; | |
3752 | r = 0; | |
3753 | set_irqchip_out: | |
3754 | kfree(chip); | |
3755 | break; | |
3756 | } | |
3757 | case KVM_GET_PIT: { | |
3758 | r = -EFAULT; | |
3759 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) | |
3760 | goto out; | |
3761 | r = -ENXIO; | |
3762 | if (!kvm->arch.vpit) | |
3763 | goto out; | |
3764 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); | |
3765 | if (r) | |
3766 | goto out; | |
3767 | r = -EFAULT; | |
3768 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) | |
3769 | goto out; | |
3770 | r = 0; | |
3771 | break; | |
3772 | } | |
3773 | case KVM_SET_PIT: { | |
3774 | r = -EFAULT; | |
3775 | if (copy_from_user(&u.ps, argp, sizeof u.ps)) | |
3776 | goto out; | |
3777 | r = -ENXIO; | |
3778 | if (!kvm->arch.vpit) | |
3779 | goto out; | |
3780 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); | |
3781 | break; | |
3782 | } | |
3783 | case KVM_GET_PIT2: { | |
3784 | r = -ENXIO; | |
3785 | if (!kvm->arch.vpit) | |
3786 | goto out; | |
3787 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
3788 | if (r) | |
3789 | goto out; | |
3790 | r = -EFAULT; | |
3791 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
3792 | goto out; | |
3793 | r = 0; | |
3794 | break; | |
3795 | } | |
3796 | case KVM_SET_PIT2: { | |
3797 | r = -EFAULT; | |
3798 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
3799 | goto out; | |
3800 | r = -ENXIO; | |
3801 | if (!kvm->arch.vpit) | |
3802 | goto out; | |
3803 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); | |
3804 | break; | |
3805 | } | |
3806 | case KVM_REINJECT_CONTROL: { | |
3807 | struct kvm_reinject_control control; | |
3808 | r = -EFAULT; | |
3809 | if (copy_from_user(&control, argp, sizeof(control))) | |
3810 | goto out; | |
3811 | r = kvm_vm_ioctl_reinject(kvm, &control); | |
3812 | break; | |
3813 | } | |
3814 | case KVM_XEN_HVM_CONFIG: { | |
3815 | r = -EFAULT; | |
3816 | if (copy_from_user(&kvm->arch.xen_hvm_config, argp, | |
3817 | sizeof(struct kvm_xen_hvm_config))) | |
3818 | goto out; | |
3819 | r = -EINVAL; | |
3820 | if (kvm->arch.xen_hvm_config.flags) | |
3821 | goto out; | |
3822 | r = 0; | |
3823 | break; | |
3824 | } | |
3825 | case KVM_SET_CLOCK: { | |
3826 | struct kvm_clock_data user_ns; | |
3827 | u64 now_ns; | |
3828 | s64 delta; | |
3829 | ||
3830 | r = -EFAULT; | |
3831 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
3832 | goto out; | |
3833 | ||
3834 | r = -EINVAL; | |
3835 | if (user_ns.flags) | |
3836 | goto out; | |
3837 | ||
3838 | r = 0; | |
3839 | local_irq_disable(); | |
3840 | now_ns = get_kernel_ns(); | |
3841 | delta = user_ns.clock - now_ns; | |
3842 | local_irq_enable(); | |
3843 | kvm->arch.kvmclock_offset = delta; | |
3844 | kvm_gen_update_masterclock(kvm); | |
3845 | break; | |
3846 | } | |
3847 | case KVM_GET_CLOCK: { | |
3848 | struct kvm_clock_data user_ns; | |
3849 | u64 now_ns; | |
3850 | ||
3851 | local_irq_disable(); | |
3852 | now_ns = get_kernel_ns(); | |
3853 | user_ns.clock = kvm->arch.kvmclock_offset + now_ns; | |
3854 | local_irq_enable(); | |
3855 | user_ns.flags = 0; | |
3856 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); | |
3857 | ||
3858 | r = -EFAULT; | |
3859 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
3860 | goto out; | |
3861 | r = 0; | |
3862 | break; | |
3863 | } | |
3864 | ||
3865 | default: | |
3866 | ; | |
3867 | } | |
3868 | out: | |
3869 | return r; | |
3870 | } | |
3871 | ||
3872 | static void kvm_init_msr_list(void) | |
3873 | { | |
3874 | u32 dummy[2]; | |
3875 | unsigned i, j; | |
3876 | ||
3877 | /* skip the first msrs in the list. KVM-specific */ | |
3878 | for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) { | |
3879 | if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) | |
3880 | continue; | |
3881 | if (j < i) | |
3882 | msrs_to_save[j] = msrs_to_save[i]; | |
3883 | j++; | |
3884 | } | |
3885 | num_msrs_to_save = j; | |
3886 | } | |
3887 | ||
3888 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, | |
3889 | const void *v) | |
3890 | { | |
3891 | int handled = 0; | |
3892 | int n; | |
3893 | ||
3894 | do { | |
3895 | n = min(len, 8); | |
3896 | if (!(vcpu->arch.apic && | |
3897 | !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v)) | |
3898 | && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v)) | |
3899 | break; | |
3900 | handled += n; | |
3901 | addr += n; | |
3902 | len -= n; | |
3903 | v += n; | |
3904 | } while (len); | |
3905 | ||
3906 | return handled; | |
3907 | } | |
3908 | ||
3909 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) | |
3910 | { | |
3911 | int handled = 0; | |
3912 | int n; | |
3913 | ||
3914 | do { | |
3915 | n = min(len, 8); | |
3916 | if (!(vcpu->arch.apic && | |
3917 | !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v)) | |
3918 | && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v)) | |
3919 | break; | |
3920 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); | |
3921 | handled += n; | |
3922 | addr += n; | |
3923 | len -= n; | |
3924 | v += n; | |
3925 | } while (len); | |
3926 | ||
3927 | return handled; | |
3928 | } | |
3929 | ||
3930 | static void kvm_set_segment(struct kvm_vcpu *vcpu, | |
3931 | struct kvm_segment *var, int seg) | |
3932 | { | |
3933 | kvm_x86_ops->set_segment(vcpu, var, seg); | |
3934 | } | |
3935 | ||
3936 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
3937 | struct kvm_segment *var, int seg) | |
3938 | { | |
3939 | kvm_x86_ops->get_segment(vcpu, var, seg); | |
3940 | } | |
3941 | ||
3942 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access) | |
3943 | { | |
3944 | gpa_t t_gpa; | |
3945 | struct x86_exception exception; | |
3946 | ||
3947 | BUG_ON(!mmu_is_nested(vcpu)); | |
3948 | ||
3949 | /* NPT walks are always user-walks */ | |
3950 | access |= PFERR_USER_MASK; | |
3951 | t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception); | |
3952 | ||
3953 | return t_gpa; | |
3954 | } | |
3955 | ||
3956 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, | |
3957 | struct x86_exception *exception) | |
3958 | { | |
3959 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3960 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); | |
3961 | } | |
3962 | ||
3963 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, | |
3964 | struct x86_exception *exception) | |
3965 | { | |
3966 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3967 | access |= PFERR_FETCH_MASK; | |
3968 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); | |
3969 | } | |
3970 | ||
3971 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, | |
3972 | struct x86_exception *exception) | |
3973 | { | |
3974 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
3975 | access |= PFERR_WRITE_MASK; | |
3976 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); | |
3977 | } | |
3978 | ||
3979 | /* uses this to access any guest's mapped memory without checking CPL */ | |
3980 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, | |
3981 | struct x86_exception *exception) | |
3982 | { | |
3983 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); | |
3984 | } | |
3985 | ||
3986 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
3987 | struct kvm_vcpu *vcpu, u32 access, | |
3988 | struct x86_exception *exception) | |
3989 | { | |
3990 | void *data = val; | |
3991 | int r = X86EMUL_CONTINUE; | |
3992 | ||
3993 | while (bytes) { | |
3994 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, | |
3995 | exception); | |
3996 | unsigned offset = addr & (PAGE_SIZE-1); | |
3997 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); | |
3998 | int ret; | |
3999 | ||
4000 | if (gpa == UNMAPPED_GVA) | |
4001 | return X86EMUL_PROPAGATE_FAULT; | |
4002 | ret = kvm_read_guest(vcpu->kvm, gpa, data, toread); | |
4003 | if (ret < 0) { | |
4004 | r = X86EMUL_IO_NEEDED; | |
4005 | goto out; | |
4006 | } | |
4007 | ||
4008 | bytes -= toread; | |
4009 | data += toread; | |
4010 | addr += toread; | |
4011 | } | |
4012 | out: | |
4013 | return r; | |
4014 | } | |
4015 | ||
4016 | /* used for instruction fetching */ | |
4017 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, | |
4018 | gva_t addr, void *val, unsigned int bytes, | |
4019 | struct x86_exception *exception) | |
4020 | { | |
4021 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4022 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
4023 | ||
4024 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, | |
4025 | access | PFERR_FETCH_MASK, | |
4026 | exception); | |
4027 | } | |
4028 | ||
4029 | int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, | |
4030 | gva_t addr, void *val, unsigned int bytes, | |
4031 | struct x86_exception *exception) | |
4032 | { | |
4033 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4034 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
4035 | ||
4036 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, | |
4037 | exception); | |
4038 | } | |
4039 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); | |
4040 | ||
4041 | static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, | |
4042 | gva_t addr, void *val, unsigned int bytes, | |
4043 | struct x86_exception *exception) | |
4044 | { | |
4045 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4046 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); | |
4047 | } | |
4048 | ||
4049 | int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, | |
4050 | gva_t addr, void *val, | |
4051 | unsigned int bytes, | |
4052 | struct x86_exception *exception) | |
4053 | { | |
4054 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4055 | void *data = val; | |
4056 | int r = X86EMUL_CONTINUE; | |
4057 | ||
4058 | while (bytes) { | |
4059 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, | |
4060 | PFERR_WRITE_MASK, | |
4061 | exception); | |
4062 | unsigned offset = addr & (PAGE_SIZE-1); | |
4063 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
4064 | int ret; | |
4065 | ||
4066 | if (gpa == UNMAPPED_GVA) | |
4067 | return X86EMUL_PROPAGATE_FAULT; | |
4068 | ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite); | |
4069 | if (ret < 0) { | |
4070 | r = X86EMUL_IO_NEEDED; | |
4071 | goto out; | |
4072 | } | |
4073 | ||
4074 | bytes -= towrite; | |
4075 | data += towrite; | |
4076 | addr += towrite; | |
4077 | } | |
4078 | out: | |
4079 | return r; | |
4080 | } | |
4081 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); | |
4082 | ||
4083 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, | |
4084 | gpa_t *gpa, struct x86_exception *exception, | |
4085 | bool write) | |
4086 | { | |
4087 | u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) | |
4088 | | (write ? PFERR_WRITE_MASK : 0); | |
4089 | ||
4090 | if (vcpu_match_mmio_gva(vcpu, gva) | |
4091 | && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) { | |
4092 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | | |
4093 | (gva & (PAGE_SIZE - 1)); | |
4094 | trace_vcpu_match_mmio(gva, *gpa, write, false); | |
4095 | return 1; | |
4096 | } | |
4097 | ||
4098 | *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); | |
4099 | ||
4100 | if (*gpa == UNMAPPED_GVA) | |
4101 | return -1; | |
4102 | ||
4103 | /* For APIC access vmexit */ | |
4104 | if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
4105 | return 1; | |
4106 | ||
4107 | if (vcpu_match_mmio_gpa(vcpu, *gpa)) { | |
4108 | trace_vcpu_match_mmio(gva, *gpa, write, true); | |
4109 | return 1; | |
4110 | } | |
4111 | ||
4112 | return 0; | |
4113 | } | |
4114 | ||
4115 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4116 | const void *val, int bytes) | |
4117 | { | |
4118 | int ret; | |
4119 | ||
4120 | ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes); | |
4121 | if (ret < 0) | |
4122 | return 0; | |
4123 | kvm_mmu_pte_write(vcpu, gpa, val, bytes); | |
4124 | return 1; | |
4125 | } | |
4126 | ||
4127 | struct read_write_emulator_ops { | |
4128 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
4129 | int bytes); | |
4130 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4131 | void *val, int bytes); | |
4132 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4133 | int bytes, void *val); | |
4134 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4135 | void *val, int bytes); | |
4136 | bool write; | |
4137 | }; | |
4138 | ||
4139 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
4140 | { | |
4141 | if (vcpu->mmio_read_completed) { | |
4142 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, | |
4143 | vcpu->mmio_fragments[0].gpa, *(u64 *)val); | |
4144 | vcpu->mmio_read_completed = 0; | |
4145 | return 1; | |
4146 | } | |
4147 | ||
4148 | return 0; | |
4149 | } | |
4150 | ||
4151 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4152 | void *val, int bytes) | |
4153 | { | |
4154 | return !kvm_read_guest(vcpu->kvm, gpa, val, bytes); | |
4155 | } | |
4156 | ||
4157 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4158 | void *val, int bytes) | |
4159 | { | |
4160 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
4161 | } | |
4162 | ||
4163 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
4164 | { | |
4165 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); | |
4166 | return vcpu_mmio_write(vcpu, gpa, bytes, val); | |
4167 | } | |
4168 | ||
4169 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4170 | void *val, int bytes) | |
4171 | { | |
4172 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); | |
4173 | return X86EMUL_IO_NEEDED; | |
4174 | } | |
4175 | ||
4176 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
4177 | void *val, int bytes) | |
4178 | { | |
4179 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; | |
4180 | ||
4181 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); | |
4182 | return X86EMUL_CONTINUE; | |
4183 | } | |
4184 | ||
4185 | static const struct read_write_emulator_ops read_emultor = { | |
4186 | .read_write_prepare = read_prepare, | |
4187 | .read_write_emulate = read_emulate, | |
4188 | .read_write_mmio = vcpu_mmio_read, | |
4189 | .read_write_exit_mmio = read_exit_mmio, | |
4190 | }; | |
4191 | ||
4192 | static const struct read_write_emulator_ops write_emultor = { | |
4193 | .read_write_emulate = write_emulate, | |
4194 | .read_write_mmio = write_mmio, | |
4195 | .read_write_exit_mmio = write_exit_mmio, | |
4196 | .write = true, | |
4197 | }; | |
4198 | ||
4199 | static int emulator_read_write_onepage(unsigned long addr, void *val, | |
4200 | unsigned int bytes, | |
4201 | struct x86_exception *exception, | |
4202 | struct kvm_vcpu *vcpu, | |
4203 | const struct read_write_emulator_ops *ops) | |
4204 | { | |
4205 | gpa_t gpa; | |
4206 | int handled, ret; | |
4207 | bool write = ops->write; | |
4208 | struct kvm_mmio_fragment *frag; | |
4209 | ||
4210 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); | |
4211 | ||
4212 | if (ret < 0) | |
4213 | return X86EMUL_PROPAGATE_FAULT; | |
4214 | ||
4215 | /* For APIC access vmexit */ | |
4216 | if (ret) | |
4217 | goto mmio; | |
4218 | ||
4219 | if (ops->read_write_emulate(vcpu, gpa, val, bytes)) | |
4220 | return X86EMUL_CONTINUE; | |
4221 | ||
4222 | mmio: | |
4223 | /* | |
4224 | * Is this MMIO handled locally? | |
4225 | */ | |
4226 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); | |
4227 | if (handled == bytes) | |
4228 | return X86EMUL_CONTINUE; | |
4229 | ||
4230 | gpa += handled; | |
4231 | bytes -= handled; | |
4232 | val += handled; | |
4233 | ||
4234 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); | |
4235 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
4236 | frag->gpa = gpa; | |
4237 | frag->data = val; | |
4238 | frag->len = bytes; | |
4239 | return X86EMUL_CONTINUE; | |
4240 | } | |
4241 | ||
4242 | int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr, | |
4243 | void *val, unsigned int bytes, | |
4244 | struct x86_exception *exception, | |
4245 | const struct read_write_emulator_ops *ops) | |
4246 | { | |
4247 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4248 | gpa_t gpa; | |
4249 | int rc; | |
4250 | ||
4251 | if (ops->read_write_prepare && | |
4252 | ops->read_write_prepare(vcpu, val, bytes)) | |
4253 | return X86EMUL_CONTINUE; | |
4254 | ||
4255 | vcpu->mmio_nr_fragments = 0; | |
4256 | ||
4257 | /* Crossing a page boundary? */ | |
4258 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
4259 | int now; | |
4260 | ||
4261 | now = -addr & ~PAGE_MASK; | |
4262 | rc = emulator_read_write_onepage(addr, val, now, exception, | |
4263 | vcpu, ops); | |
4264 | ||
4265 | if (rc != X86EMUL_CONTINUE) | |
4266 | return rc; | |
4267 | addr += now; | |
4268 | val += now; | |
4269 | bytes -= now; | |
4270 | } | |
4271 | ||
4272 | rc = emulator_read_write_onepage(addr, val, bytes, exception, | |
4273 | vcpu, ops); | |
4274 | if (rc != X86EMUL_CONTINUE) | |
4275 | return rc; | |
4276 | ||
4277 | if (!vcpu->mmio_nr_fragments) | |
4278 | return rc; | |
4279 | ||
4280 | gpa = vcpu->mmio_fragments[0].gpa; | |
4281 | ||
4282 | vcpu->mmio_needed = 1; | |
4283 | vcpu->mmio_cur_fragment = 0; | |
4284 | ||
4285 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); | |
4286 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; | |
4287 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
4288 | vcpu->run->mmio.phys_addr = gpa; | |
4289 | ||
4290 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
4291 | } | |
4292 | ||
4293 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
4294 | unsigned long addr, | |
4295 | void *val, | |
4296 | unsigned int bytes, | |
4297 | struct x86_exception *exception) | |
4298 | { | |
4299 | return emulator_read_write(ctxt, addr, val, bytes, | |
4300 | exception, &read_emultor); | |
4301 | } | |
4302 | ||
4303 | int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, | |
4304 | unsigned long addr, | |
4305 | const void *val, | |
4306 | unsigned int bytes, | |
4307 | struct x86_exception *exception) | |
4308 | { | |
4309 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
4310 | exception, &write_emultor); | |
4311 | } | |
4312 | ||
4313 | #define CMPXCHG_TYPE(t, ptr, old, new) \ | |
4314 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
4315 | ||
4316 | #ifdef CONFIG_X86_64 | |
4317 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
4318 | #else | |
4319 | # define CMPXCHG64(ptr, old, new) \ | |
4320 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) | |
4321 | #endif | |
4322 | ||
4323 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, | |
4324 | unsigned long addr, | |
4325 | const void *old, | |
4326 | const void *new, | |
4327 | unsigned int bytes, | |
4328 | struct x86_exception *exception) | |
4329 | { | |
4330 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4331 | gpa_t gpa; | |
4332 | struct page *page; | |
4333 | char *kaddr; | |
4334 | bool exchanged; | |
4335 | ||
4336 | /* guests cmpxchg8b have to be emulated atomically */ | |
4337 | if (bytes > 8 || (bytes & (bytes - 1))) | |
4338 | goto emul_write; | |
4339 | ||
4340 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); | |
4341 | ||
4342 | if (gpa == UNMAPPED_GVA || | |
4343 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
4344 | goto emul_write; | |
4345 | ||
4346 | if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) | |
4347 | goto emul_write; | |
4348 | ||
4349 | page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); | |
4350 | if (is_error_page(page)) | |
4351 | goto emul_write; | |
4352 | ||
4353 | kaddr = kmap_atomic(page); | |
4354 | kaddr += offset_in_page(gpa); | |
4355 | switch (bytes) { | |
4356 | case 1: | |
4357 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
4358 | break; | |
4359 | case 2: | |
4360 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
4361 | break; | |
4362 | case 4: | |
4363 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
4364 | break; | |
4365 | case 8: | |
4366 | exchanged = CMPXCHG64(kaddr, old, new); | |
4367 | break; | |
4368 | default: | |
4369 | BUG(); | |
4370 | } | |
4371 | kunmap_atomic(kaddr); | |
4372 | kvm_release_page_dirty(page); | |
4373 | ||
4374 | if (!exchanged) | |
4375 | return X86EMUL_CMPXCHG_FAILED; | |
4376 | ||
4377 | kvm_mmu_pte_write(vcpu, gpa, new, bytes); | |
4378 | ||
4379 | return X86EMUL_CONTINUE; | |
4380 | ||
4381 | emul_write: | |
4382 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); | |
4383 | ||
4384 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); | |
4385 | } | |
4386 | ||
4387 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) | |
4388 | { | |
4389 | /* TODO: String I/O for in kernel device */ | |
4390 | int r; | |
4391 | ||
4392 | if (vcpu->arch.pio.in) | |
4393 | r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port, | |
4394 | vcpu->arch.pio.size, pd); | |
4395 | else | |
4396 | r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS, | |
4397 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
4398 | pd); | |
4399 | return r; | |
4400 | } | |
4401 | ||
4402 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, | |
4403 | unsigned short port, void *val, | |
4404 | unsigned int count, bool in) | |
4405 | { | |
4406 | trace_kvm_pio(!in, port, size, count); | |
4407 | ||
4408 | vcpu->arch.pio.port = port; | |
4409 | vcpu->arch.pio.in = in; | |
4410 | vcpu->arch.pio.count = count; | |
4411 | vcpu->arch.pio.size = size; | |
4412 | ||
4413 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
4414 | vcpu->arch.pio.count = 0; | |
4415 | return 1; | |
4416 | } | |
4417 | ||
4418 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
4419 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; | |
4420 | vcpu->run->io.size = size; | |
4421 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
4422 | vcpu->run->io.count = count; | |
4423 | vcpu->run->io.port = port; | |
4424 | ||
4425 | return 0; | |
4426 | } | |
4427 | ||
4428 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, | |
4429 | int size, unsigned short port, void *val, | |
4430 | unsigned int count) | |
4431 | { | |
4432 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4433 | int ret; | |
4434 | ||
4435 | if (vcpu->arch.pio.count) | |
4436 | goto data_avail; | |
4437 | ||
4438 | ret = emulator_pio_in_out(vcpu, size, port, val, count, true); | |
4439 | if (ret) { | |
4440 | data_avail: | |
4441 | memcpy(val, vcpu->arch.pio_data, size * count); | |
4442 | vcpu->arch.pio.count = 0; | |
4443 | return 1; | |
4444 | } | |
4445 | ||
4446 | return 0; | |
4447 | } | |
4448 | ||
4449 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, | |
4450 | int size, unsigned short port, | |
4451 | const void *val, unsigned int count) | |
4452 | { | |
4453 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4454 | ||
4455 | memcpy(vcpu->arch.pio_data, val, size * count); | |
4456 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); | |
4457 | } | |
4458 | ||
4459 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
4460 | { | |
4461 | return kvm_x86_ops->get_segment_base(vcpu, seg); | |
4462 | } | |
4463 | ||
4464 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) | |
4465 | { | |
4466 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); | |
4467 | } | |
4468 | ||
4469 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
4470 | { | |
4471 | if (!need_emulate_wbinvd(vcpu)) | |
4472 | return X86EMUL_CONTINUE; | |
4473 | ||
4474 | if (kvm_x86_ops->has_wbinvd_exit()) { | |
4475 | int cpu = get_cpu(); | |
4476 | ||
4477 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
4478 | smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, | |
4479 | wbinvd_ipi, NULL, 1); | |
4480 | put_cpu(); | |
4481 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); | |
4482 | } else | |
4483 | wbinvd(); | |
4484 | return X86EMUL_CONTINUE; | |
4485 | } | |
4486 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); | |
4487 | ||
4488 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) | |
4489 | { | |
4490 | kvm_emulate_wbinvd(emul_to_vcpu(ctxt)); | |
4491 | } | |
4492 | ||
4493 | int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest) | |
4494 | { | |
4495 | return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); | |
4496 | } | |
4497 | ||
4498 | int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value) | |
4499 | { | |
4500 | ||
4501 | return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); | |
4502 | } | |
4503 | ||
4504 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) | |
4505 | { | |
4506 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; | |
4507 | } | |
4508 | ||
4509 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) | |
4510 | { | |
4511 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4512 | unsigned long value; | |
4513 | ||
4514 | switch (cr) { | |
4515 | case 0: | |
4516 | value = kvm_read_cr0(vcpu); | |
4517 | break; | |
4518 | case 2: | |
4519 | value = vcpu->arch.cr2; | |
4520 | break; | |
4521 | case 3: | |
4522 | value = kvm_read_cr3(vcpu); | |
4523 | break; | |
4524 | case 4: | |
4525 | value = kvm_read_cr4(vcpu); | |
4526 | break; | |
4527 | case 8: | |
4528 | value = kvm_get_cr8(vcpu); | |
4529 | break; | |
4530 | default: | |
4531 | kvm_err("%s: unexpected cr %u\n", __func__, cr); | |
4532 | return 0; | |
4533 | } | |
4534 | ||
4535 | return value; | |
4536 | } | |
4537 | ||
4538 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) | |
4539 | { | |
4540 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4541 | int res = 0; | |
4542 | ||
4543 | switch (cr) { | |
4544 | case 0: | |
4545 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); | |
4546 | break; | |
4547 | case 2: | |
4548 | vcpu->arch.cr2 = val; | |
4549 | break; | |
4550 | case 3: | |
4551 | res = kvm_set_cr3(vcpu, val); | |
4552 | break; | |
4553 | case 4: | |
4554 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); | |
4555 | break; | |
4556 | case 8: | |
4557 | res = kvm_set_cr8(vcpu, val); | |
4558 | break; | |
4559 | default: | |
4560 | kvm_err("%s: unexpected cr %u\n", __func__, cr); | |
4561 | res = -1; | |
4562 | } | |
4563 | ||
4564 | return res; | |
4565 | } | |
4566 | ||
4567 | static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val) | |
4568 | { | |
4569 | kvm_set_rflags(emul_to_vcpu(ctxt), val); | |
4570 | } | |
4571 | ||
4572 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) | |
4573 | { | |
4574 | return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); | |
4575 | } | |
4576 | ||
4577 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
4578 | { | |
4579 | kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); | |
4580 | } | |
4581 | ||
4582 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
4583 | { | |
4584 | kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); | |
4585 | } | |
4586 | ||
4587 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
4588 | { | |
4589 | kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); | |
4590 | } | |
4591 | ||
4592 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
4593 | { | |
4594 | kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); | |
4595 | } | |
4596 | ||
4597 | static unsigned long emulator_get_cached_segment_base( | |
4598 | struct x86_emulate_ctxt *ctxt, int seg) | |
4599 | { | |
4600 | return get_segment_base(emul_to_vcpu(ctxt), seg); | |
4601 | } | |
4602 | ||
4603 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, | |
4604 | struct desc_struct *desc, u32 *base3, | |
4605 | int seg) | |
4606 | { | |
4607 | struct kvm_segment var; | |
4608 | ||
4609 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); | |
4610 | *selector = var.selector; | |
4611 | ||
4612 | if (var.unusable) { | |
4613 | memset(desc, 0, sizeof(*desc)); | |
4614 | return false; | |
4615 | } | |
4616 | ||
4617 | if (var.g) | |
4618 | var.limit >>= 12; | |
4619 | set_desc_limit(desc, var.limit); | |
4620 | set_desc_base(desc, (unsigned long)var.base); | |
4621 | #ifdef CONFIG_X86_64 | |
4622 | if (base3) | |
4623 | *base3 = var.base >> 32; | |
4624 | #endif | |
4625 | desc->type = var.type; | |
4626 | desc->s = var.s; | |
4627 | desc->dpl = var.dpl; | |
4628 | desc->p = var.present; | |
4629 | desc->avl = var.avl; | |
4630 | desc->l = var.l; | |
4631 | desc->d = var.db; | |
4632 | desc->g = var.g; | |
4633 | ||
4634 | return true; | |
4635 | } | |
4636 | ||
4637 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, | |
4638 | struct desc_struct *desc, u32 base3, | |
4639 | int seg) | |
4640 | { | |
4641 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4642 | struct kvm_segment var; | |
4643 | ||
4644 | var.selector = selector; | |
4645 | var.base = get_desc_base(desc); | |
4646 | #ifdef CONFIG_X86_64 | |
4647 | var.base |= ((u64)base3) << 32; | |
4648 | #endif | |
4649 | var.limit = get_desc_limit(desc); | |
4650 | if (desc->g) | |
4651 | var.limit = (var.limit << 12) | 0xfff; | |
4652 | var.type = desc->type; | |
4653 | var.present = desc->p; | |
4654 | var.dpl = desc->dpl; | |
4655 | var.db = desc->d; | |
4656 | var.s = desc->s; | |
4657 | var.l = desc->l; | |
4658 | var.g = desc->g; | |
4659 | var.avl = desc->avl; | |
4660 | var.present = desc->p; | |
4661 | var.unusable = !var.present; | |
4662 | var.padding = 0; | |
4663 | ||
4664 | kvm_set_segment(vcpu, &var, seg); | |
4665 | return; | |
4666 | } | |
4667 | ||
4668 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, | |
4669 | u32 msr_index, u64 *pdata) | |
4670 | { | |
4671 | return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); | |
4672 | } | |
4673 | ||
4674 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
4675 | u32 msr_index, u64 data) | |
4676 | { | |
4677 | struct msr_data msr; | |
4678 | ||
4679 | msr.data = data; | |
4680 | msr.index = msr_index; | |
4681 | msr.host_initiated = false; | |
4682 | return kvm_set_msr(emul_to_vcpu(ctxt), &msr); | |
4683 | } | |
4684 | ||
4685 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, | |
4686 | u32 pmc, u64 *pdata) | |
4687 | { | |
4688 | return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata); | |
4689 | } | |
4690 | ||
4691 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) | |
4692 | { | |
4693 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
4694 | } | |
4695 | ||
4696 | static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) | |
4697 | { | |
4698 | preempt_disable(); | |
4699 | kvm_load_guest_fpu(emul_to_vcpu(ctxt)); | |
4700 | /* | |
4701 | * CR0.TS may reference the host fpu state, not the guest fpu state, | |
4702 | * so it may be clear at this point. | |
4703 | */ | |
4704 | clts(); | |
4705 | } | |
4706 | ||
4707 | static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) | |
4708 | { | |
4709 | preempt_enable(); | |
4710 | } | |
4711 | ||
4712 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, | |
4713 | struct x86_instruction_info *info, | |
4714 | enum x86_intercept_stage stage) | |
4715 | { | |
4716 | return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); | |
4717 | } | |
4718 | ||
4719 | static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, | |
4720 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) | |
4721 | { | |
4722 | kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx); | |
4723 | } | |
4724 | ||
4725 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) | |
4726 | { | |
4727 | return kvm_register_read(emul_to_vcpu(ctxt), reg); | |
4728 | } | |
4729 | ||
4730 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
4731 | { | |
4732 | kvm_register_write(emul_to_vcpu(ctxt), reg, val); | |
4733 | } | |
4734 | ||
4735 | static const struct x86_emulate_ops emulate_ops = { | |
4736 | .read_gpr = emulator_read_gpr, | |
4737 | .write_gpr = emulator_write_gpr, | |
4738 | .read_std = kvm_read_guest_virt_system, | |
4739 | .write_std = kvm_write_guest_virt_system, | |
4740 | .fetch = kvm_fetch_guest_virt, | |
4741 | .read_emulated = emulator_read_emulated, | |
4742 | .write_emulated = emulator_write_emulated, | |
4743 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
4744 | .invlpg = emulator_invlpg, | |
4745 | .pio_in_emulated = emulator_pio_in_emulated, | |
4746 | .pio_out_emulated = emulator_pio_out_emulated, | |
4747 | .get_segment = emulator_get_segment, | |
4748 | .set_segment = emulator_set_segment, | |
4749 | .get_cached_segment_base = emulator_get_cached_segment_base, | |
4750 | .get_gdt = emulator_get_gdt, | |
4751 | .get_idt = emulator_get_idt, | |
4752 | .set_gdt = emulator_set_gdt, | |
4753 | .set_idt = emulator_set_idt, | |
4754 | .get_cr = emulator_get_cr, | |
4755 | .set_cr = emulator_set_cr, | |
4756 | .set_rflags = emulator_set_rflags, | |
4757 | .cpl = emulator_get_cpl, | |
4758 | .get_dr = emulator_get_dr, | |
4759 | .set_dr = emulator_set_dr, | |
4760 | .set_msr = emulator_set_msr, | |
4761 | .get_msr = emulator_get_msr, | |
4762 | .read_pmc = emulator_read_pmc, | |
4763 | .halt = emulator_halt, | |
4764 | .wbinvd = emulator_wbinvd, | |
4765 | .fix_hypercall = emulator_fix_hypercall, | |
4766 | .get_fpu = emulator_get_fpu, | |
4767 | .put_fpu = emulator_put_fpu, | |
4768 | .intercept = emulator_intercept, | |
4769 | .get_cpuid = emulator_get_cpuid, | |
4770 | }; | |
4771 | ||
4772 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) | |
4773 | { | |
4774 | u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask); | |
4775 | /* | |
4776 | * an sti; sti; sequence only disable interrupts for the first | |
4777 | * instruction. So, if the last instruction, be it emulated or | |
4778 | * not, left the system with the INT_STI flag enabled, it | |
4779 | * means that the last instruction is an sti. We should not | |
4780 | * leave the flag on in this case. The same goes for mov ss | |
4781 | */ | |
4782 | if (!(int_shadow & mask)) | |
4783 | kvm_x86_ops->set_interrupt_shadow(vcpu, mask); | |
4784 | } | |
4785 | ||
4786 | static void inject_emulated_exception(struct kvm_vcpu *vcpu) | |
4787 | { | |
4788 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; | |
4789 | if (ctxt->exception.vector == PF_VECTOR) | |
4790 | kvm_propagate_fault(vcpu, &ctxt->exception); | |
4791 | else if (ctxt->exception.error_code_valid) | |
4792 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, | |
4793 | ctxt->exception.error_code); | |
4794 | else | |
4795 | kvm_queue_exception(vcpu, ctxt->exception.vector); | |
4796 | } | |
4797 | ||
4798 | static void init_decode_cache(struct x86_emulate_ctxt *ctxt) | |
4799 | { | |
4800 | memset(&ctxt->opcode_len, 0, | |
4801 | (void *)&ctxt->_regs - (void *)&ctxt->opcode_len); | |
4802 | ||
4803 | ctxt->fetch.start = 0; | |
4804 | ctxt->fetch.end = 0; | |
4805 | ctxt->io_read.pos = 0; | |
4806 | ctxt->io_read.end = 0; | |
4807 | ctxt->mem_read.pos = 0; | |
4808 | ctxt->mem_read.end = 0; | |
4809 | } | |
4810 | ||
4811 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) | |
4812 | { | |
4813 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; | |
4814 | int cs_db, cs_l; | |
4815 | ||
4816 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
4817 | ||
4818 | ctxt->eflags = kvm_get_rflags(vcpu); | |
4819 | ctxt->eip = kvm_rip_read(vcpu); | |
4820 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
4821 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
4822 | cs_l ? X86EMUL_MODE_PROT64 : | |
4823 | cs_db ? X86EMUL_MODE_PROT32 : | |
4824 | X86EMUL_MODE_PROT16; | |
4825 | ctxt->guest_mode = is_guest_mode(vcpu); | |
4826 | ||
4827 | init_decode_cache(ctxt); | |
4828 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
4829 | } | |
4830 | ||
4831 | int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) | |
4832 | { | |
4833 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; | |
4834 | int ret; | |
4835 | ||
4836 | init_emulate_ctxt(vcpu); | |
4837 | ||
4838 | ctxt->op_bytes = 2; | |
4839 | ctxt->ad_bytes = 2; | |
4840 | ctxt->_eip = ctxt->eip + inc_eip; | |
4841 | ret = emulate_int_real(ctxt, irq); | |
4842 | ||
4843 | if (ret != X86EMUL_CONTINUE) | |
4844 | return EMULATE_FAIL; | |
4845 | ||
4846 | ctxt->eip = ctxt->_eip; | |
4847 | kvm_rip_write(vcpu, ctxt->eip); | |
4848 | kvm_set_rflags(vcpu, ctxt->eflags); | |
4849 | ||
4850 | if (irq == NMI_VECTOR) | |
4851 | vcpu->arch.nmi_pending = 0; | |
4852 | else | |
4853 | vcpu->arch.interrupt.pending = false; | |
4854 | ||
4855 | return EMULATE_DONE; | |
4856 | } | |
4857 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
4858 | ||
4859 | static int handle_emulation_failure(struct kvm_vcpu *vcpu) | |
4860 | { | |
4861 | int r = EMULATE_DONE; | |
4862 | ||
4863 | ++vcpu->stat.insn_emulation_fail; | |
4864 | trace_kvm_emulate_insn_failed(vcpu); | |
4865 | if (!is_guest_mode(vcpu)) { | |
4866 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
4867 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
4868 | vcpu->run->internal.ndata = 0; | |
4869 | r = EMULATE_FAIL; | |
4870 | } | |
4871 | kvm_queue_exception(vcpu, UD_VECTOR); | |
4872 | ||
4873 | return r; | |
4874 | } | |
4875 | ||
4876 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, | |
4877 | bool write_fault_to_shadow_pgtable, | |
4878 | int emulation_type) | |
4879 | { | |
4880 | gpa_t gpa = cr2; | |
4881 | pfn_t pfn; | |
4882 | ||
4883 | if (emulation_type & EMULTYPE_NO_REEXECUTE) | |
4884 | return false; | |
4885 | ||
4886 | if (!vcpu->arch.mmu.direct_map) { | |
4887 | /* | |
4888 | * Write permission should be allowed since only | |
4889 | * write access need to be emulated. | |
4890 | */ | |
4891 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); | |
4892 | ||
4893 | /* | |
4894 | * If the mapping is invalid in guest, let cpu retry | |
4895 | * it to generate fault. | |
4896 | */ | |
4897 | if (gpa == UNMAPPED_GVA) | |
4898 | return true; | |
4899 | } | |
4900 | ||
4901 | /* | |
4902 | * Do not retry the unhandleable instruction if it faults on the | |
4903 | * readonly host memory, otherwise it will goto a infinite loop: | |
4904 | * retry instruction -> write #PF -> emulation fail -> retry | |
4905 | * instruction -> ... | |
4906 | */ | |
4907 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
4908 | ||
4909 | /* | |
4910 | * If the instruction failed on the error pfn, it can not be fixed, | |
4911 | * report the error to userspace. | |
4912 | */ | |
4913 | if (is_error_noslot_pfn(pfn)) | |
4914 | return false; | |
4915 | ||
4916 | kvm_release_pfn_clean(pfn); | |
4917 | ||
4918 | /* The instructions are well-emulated on direct mmu. */ | |
4919 | if (vcpu->arch.mmu.direct_map) { | |
4920 | unsigned int indirect_shadow_pages; | |
4921 | ||
4922 | spin_lock(&vcpu->kvm->mmu_lock); | |
4923 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; | |
4924 | spin_unlock(&vcpu->kvm->mmu_lock); | |
4925 | ||
4926 | if (indirect_shadow_pages) | |
4927 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
4928 | ||
4929 | return true; | |
4930 | } | |
4931 | ||
4932 | /* | |
4933 | * if emulation was due to access to shadowed page table | |
4934 | * and it failed try to unshadow page and re-enter the | |
4935 | * guest to let CPU execute the instruction. | |
4936 | */ | |
4937 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
4938 | ||
4939 | /* | |
4940 | * If the access faults on its page table, it can not | |
4941 | * be fixed by unprotecting shadow page and it should | |
4942 | * be reported to userspace. | |
4943 | */ | |
4944 | return !write_fault_to_shadow_pgtable; | |
4945 | } | |
4946 | ||
4947 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, | |
4948 | unsigned long cr2, int emulation_type) | |
4949 | { | |
4950 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
4951 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2; | |
4952 | ||
4953 | last_retry_eip = vcpu->arch.last_retry_eip; | |
4954 | last_retry_addr = vcpu->arch.last_retry_addr; | |
4955 | ||
4956 | /* | |
4957 | * If the emulation is caused by #PF and it is non-page_table | |
4958 | * writing instruction, it means the VM-EXIT is caused by shadow | |
4959 | * page protected, we can zap the shadow page and retry this | |
4960 | * instruction directly. | |
4961 | * | |
4962 | * Note: if the guest uses a non-page-table modifying instruction | |
4963 | * on the PDE that points to the instruction, then we will unmap | |
4964 | * the instruction and go to an infinite loop. So, we cache the | |
4965 | * last retried eip and the last fault address, if we meet the eip | |
4966 | * and the address again, we can break out of the potential infinite | |
4967 | * loop. | |
4968 | */ | |
4969 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
4970 | ||
4971 | if (!(emulation_type & EMULTYPE_RETRY)) | |
4972 | return false; | |
4973 | ||
4974 | if (x86_page_table_writing_insn(ctxt)) | |
4975 | return false; | |
4976 | ||
4977 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) | |
4978 | return false; | |
4979 | ||
4980 | vcpu->arch.last_retry_eip = ctxt->eip; | |
4981 | vcpu->arch.last_retry_addr = cr2; | |
4982 | ||
4983 | if (!vcpu->arch.mmu.direct_map) | |
4984 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); | |
4985 | ||
4986 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
4987 | ||
4988 | return true; | |
4989 | } | |
4990 | ||
4991 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); | |
4992 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
4993 | ||
4994 | static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, | |
4995 | unsigned long *db) | |
4996 | { | |
4997 | u32 dr6 = 0; | |
4998 | int i; | |
4999 | u32 enable, rwlen; | |
5000 | ||
5001 | enable = dr7; | |
5002 | rwlen = dr7 >> 16; | |
5003 | for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) | |
5004 | if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) | |
5005 | dr6 |= (1 << i); | |
5006 | return dr6; | |
5007 | } | |
5008 | ||
5009 | static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r) | |
5010 | { | |
5011 | struct kvm_run *kvm_run = vcpu->run; | |
5012 | ||
5013 | /* | |
5014 | * Use the "raw" value to see if TF was passed to the processor. | |
5015 | * Note that the new value of the flags has not been saved yet. | |
5016 | * | |
5017 | * This is correct even for TF set by the guest, because "the | |
5018 | * processor will not generate this exception after the instruction | |
5019 | * that sets the TF flag". | |
5020 | */ | |
5021 | unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); | |
5022 | ||
5023 | if (unlikely(rflags & X86_EFLAGS_TF)) { | |
5024 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { | |
5025 | kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1; | |
5026 | kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; | |
5027 | kvm_run->debug.arch.exception = DB_VECTOR; | |
5028 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
5029 | *r = EMULATE_USER_EXIT; | |
5030 | } else { | |
5031 | vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF; | |
5032 | /* | |
5033 | * "Certain debug exceptions may clear bit 0-3. The | |
5034 | * remaining contents of the DR6 register are never | |
5035 | * cleared by the processor". | |
5036 | */ | |
5037 | vcpu->arch.dr6 &= ~15; | |
5038 | vcpu->arch.dr6 |= DR6_BS; | |
5039 | kvm_queue_exception(vcpu, DB_VECTOR); | |
5040 | } | |
5041 | } | |
5042 | } | |
5043 | ||
5044 | static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) | |
5045 | { | |
5046 | struct kvm_run *kvm_run = vcpu->run; | |
5047 | unsigned long eip = vcpu->arch.emulate_ctxt.eip; | |
5048 | u32 dr6 = 0; | |
5049 | ||
5050 | if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && | |
5051 | (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { | |
5052 | dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
5053 | vcpu->arch.guest_debug_dr7, | |
5054 | vcpu->arch.eff_db); | |
5055 | ||
5056 | if (dr6 != 0) { | |
5057 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; | |
5058 | kvm_run->debug.arch.pc = kvm_rip_read(vcpu) + | |
5059 | get_segment_base(vcpu, VCPU_SREG_CS); | |
5060 | ||
5061 | kvm_run->debug.arch.exception = DB_VECTOR; | |
5062 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
5063 | *r = EMULATE_USER_EXIT; | |
5064 | return true; | |
5065 | } | |
5066 | } | |
5067 | ||
5068 | if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) { | |
5069 | dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
5070 | vcpu->arch.dr7, | |
5071 | vcpu->arch.db); | |
5072 | ||
5073 | if (dr6 != 0) { | |
5074 | vcpu->arch.dr6 &= ~15; | |
5075 | vcpu->arch.dr6 |= dr6; | |
5076 | kvm_queue_exception(vcpu, DB_VECTOR); | |
5077 | *r = EMULATE_DONE; | |
5078 | return true; | |
5079 | } | |
5080 | } | |
5081 | ||
5082 | return false; | |
5083 | } | |
5084 | ||
5085 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, | |
5086 | unsigned long cr2, | |
5087 | int emulation_type, | |
5088 | void *insn, | |
5089 | int insn_len) | |
5090 | { | |
5091 | int r; | |
5092 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; | |
5093 | bool writeback = true; | |
5094 | bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; | |
5095 | ||
5096 | /* | |
5097 | * Clear write_fault_to_shadow_pgtable here to ensure it is | |
5098 | * never reused. | |
5099 | */ | |
5100 | vcpu->arch.write_fault_to_shadow_pgtable = false; | |
5101 | kvm_clear_exception_queue(vcpu); | |
5102 | ||
5103 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { | |
5104 | init_emulate_ctxt(vcpu); | |
5105 | ||
5106 | /* | |
5107 | * We will reenter on the same instruction since | |
5108 | * we do not set complete_userspace_io. This does not | |
5109 | * handle watchpoints yet, those would be handled in | |
5110 | * the emulate_ops. | |
5111 | */ | |
5112 | if (kvm_vcpu_check_breakpoint(vcpu, &r)) | |
5113 | return r; | |
5114 | ||
5115 | ctxt->interruptibility = 0; | |
5116 | ctxt->have_exception = false; | |
5117 | ctxt->perm_ok = false; | |
5118 | ||
5119 | ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; | |
5120 | ||
5121 | r = x86_decode_insn(ctxt, insn, insn_len); | |
5122 | ||
5123 | trace_kvm_emulate_insn_start(vcpu); | |
5124 | ++vcpu->stat.insn_emulation; | |
5125 | if (r != EMULATION_OK) { | |
5126 | if (emulation_type & EMULTYPE_TRAP_UD) | |
5127 | return EMULATE_FAIL; | |
5128 | if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, | |
5129 | emulation_type)) | |
5130 | return EMULATE_DONE; | |
5131 | if (emulation_type & EMULTYPE_SKIP) | |
5132 | return EMULATE_FAIL; | |
5133 | return handle_emulation_failure(vcpu); | |
5134 | } | |
5135 | } | |
5136 | ||
5137 | if (emulation_type & EMULTYPE_SKIP) { | |
5138 | kvm_rip_write(vcpu, ctxt->_eip); | |
5139 | return EMULATE_DONE; | |
5140 | } | |
5141 | ||
5142 | if (retry_instruction(ctxt, cr2, emulation_type)) | |
5143 | return EMULATE_DONE; | |
5144 | ||
5145 | /* this is needed for vmware backdoor interface to work since it | |
5146 | changes registers values during IO operation */ | |
5147 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { | |
5148 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
5149 | emulator_invalidate_register_cache(ctxt); | |
5150 | } | |
5151 | ||
5152 | restart: | |
5153 | r = x86_emulate_insn(ctxt); | |
5154 | ||
5155 | if (r == EMULATION_INTERCEPTED) | |
5156 | return EMULATE_DONE; | |
5157 | ||
5158 | if (r == EMULATION_FAILED) { | |
5159 | if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, | |
5160 | emulation_type)) | |
5161 | return EMULATE_DONE; | |
5162 | ||
5163 | return handle_emulation_failure(vcpu); | |
5164 | } | |
5165 | ||
5166 | if (ctxt->have_exception) { | |
5167 | inject_emulated_exception(vcpu); | |
5168 | r = EMULATE_DONE; | |
5169 | } else if (vcpu->arch.pio.count) { | |
5170 | if (!vcpu->arch.pio.in) { | |
5171 | /* FIXME: return into emulator if single-stepping. */ | |
5172 | vcpu->arch.pio.count = 0; | |
5173 | } else { | |
5174 | writeback = false; | |
5175 | vcpu->arch.complete_userspace_io = complete_emulated_pio; | |
5176 | } | |
5177 | r = EMULATE_USER_EXIT; | |
5178 | } else if (vcpu->mmio_needed) { | |
5179 | if (!vcpu->mmio_is_write) | |
5180 | writeback = false; | |
5181 | r = EMULATE_USER_EXIT; | |
5182 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
5183 | } else if (r == EMULATION_RESTART) | |
5184 | goto restart; | |
5185 | else | |
5186 | r = EMULATE_DONE; | |
5187 | ||
5188 | if (writeback) { | |
5189 | toggle_interruptibility(vcpu, ctxt->interruptibility); | |
5190 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
5191 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
5192 | kvm_rip_write(vcpu, ctxt->eip); | |
5193 | if (r == EMULATE_DONE) | |
5194 | kvm_vcpu_check_singlestep(vcpu, &r); | |
5195 | kvm_set_rflags(vcpu, ctxt->eflags); | |
5196 | } else | |
5197 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
5198 | ||
5199 | return r; | |
5200 | } | |
5201 | EXPORT_SYMBOL_GPL(x86_emulate_instruction); | |
5202 | ||
5203 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) | |
5204 | { | |
5205 | unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); | |
5206 | int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, | |
5207 | size, port, &val, 1); | |
5208 | /* do not return to emulator after return from userspace */ | |
5209 | vcpu->arch.pio.count = 0; | |
5210 | return ret; | |
5211 | } | |
5212 | EXPORT_SYMBOL_GPL(kvm_fast_pio_out); | |
5213 | ||
5214 | static void tsc_bad(void *info) | |
5215 | { | |
5216 | __this_cpu_write(cpu_tsc_khz, 0); | |
5217 | } | |
5218 | ||
5219 | static void tsc_khz_changed(void *data) | |
5220 | { | |
5221 | struct cpufreq_freqs *freq = data; | |
5222 | unsigned long khz = 0; | |
5223 | ||
5224 | if (data) | |
5225 | khz = freq->new; | |
5226 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
5227 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
5228 | if (!khz) | |
5229 | khz = tsc_khz; | |
5230 | __this_cpu_write(cpu_tsc_khz, khz); | |
5231 | } | |
5232 | ||
5233 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
5234 | void *data) | |
5235 | { | |
5236 | struct cpufreq_freqs *freq = data; | |
5237 | struct kvm *kvm; | |
5238 | struct kvm_vcpu *vcpu; | |
5239 | int i, send_ipi = 0; | |
5240 | ||
5241 | /* | |
5242 | * We allow guests to temporarily run on slowing clocks, | |
5243 | * provided we notify them after, or to run on accelerating | |
5244 | * clocks, provided we notify them before. Thus time never | |
5245 | * goes backwards. | |
5246 | * | |
5247 | * However, we have a problem. We can't atomically update | |
5248 | * the frequency of a given CPU from this function; it is | |
5249 | * merely a notifier, which can be called from any CPU. | |
5250 | * Changing the TSC frequency at arbitrary points in time | |
5251 | * requires a recomputation of local variables related to | |
5252 | * the TSC for each VCPU. We must flag these local variables | |
5253 | * to be updated and be sure the update takes place with the | |
5254 | * new frequency before any guests proceed. | |
5255 | * | |
5256 | * Unfortunately, the combination of hotplug CPU and frequency | |
5257 | * change creates an intractable locking scenario; the order | |
5258 | * of when these callouts happen is undefined with respect to | |
5259 | * CPU hotplug, and they can race with each other. As such, | |
5260 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
5261 | * undefined; you can actually have a CPU frequency change take | |
5262 | * place in between the computation of X and the setting of the | |
5263 | * variable. To protect against this problem, all updates of | |
5264 | * the per_cpu tsc_khz variable are done in an interrupt | |
5265 | * protected IPI, and all callers wishing to update the value | |
5266 | * must wait for a synchronous IPI to complete (which is trivial | |
5267 | * if the caller is on the CPU already). This establishes the | |
5268 | * necessary total order on variable updates. | |
5269 | * | |
5270 | * Note that because a guest time update may take place | |
5271 | * anytime after the setting of the VCPU's request bit, the | |
5272 | * correct TSC value must be set before the request. However, | |
5273 | * to ensure the update actually makes it to any guest which | |
5274 | * starts running in hardware virtualization between the set | |
5275 | * and the acquisition of the spinlock, we must also ping the | |
5276 | * CPU after setting the request bit. | |
5277 | * | |
5278 | */ | |
5279 | ||
5280 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) | |
5281 | return 0; | |
5282 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
5283 | return 0; | |
5284 | ||
5285 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); | |
5286 | ||
5287 | spin_lock(&kvm_lock); | |
5288 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
5289 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
5290 | if (vcpu->cpu != freq->cpu) | |
5291 | continue; | |
5292 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
5293 | if (vcpu->cpu != smp_processor_id()) | |
5294 | send_ipi = 1; | |
5295 | } | |
5296 | } | |
5297 | spin_unlock(&kvm_lock); | |
5298 | ||
5299 | if (freq->old < freq->new && send_ipi) { | |
5300 | /* | |
5301 | * We upscale the frequency. Must make the guest | |
5302 | * doesn't see old kvmclock values while running with | |
5303 | * the new frequency, otherwise we risk the guest sees | |
5304 | * time go backwards. | |
5305 | * | |
5306 | * In case we update the frequency for another cpu | |
5307 | * (which might be in guest context) send an interrupt | |
5308 | * to kick the cpu out of guest context. Next time | |
5309 | * guest context is entered kvmclock will be updated, | |
5310 | * so the guest will not see stale values. | |
5311 | */ | |
5312 | smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); | |
5313 | } | |
5314 | return 0; | |
5315 | } | |
5316 | ||
5317 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
5318 | .notifier_call = kvmclock_cpufreq_notifier | |
5319 | }; | |
5320 | ||
5321 | static int kvmclock_cpu_notifier(struct notifier_block *nfb, | |
5322 | unsigned long action, void *hcpu) | |
5323 | { | |
5324 | unsigned int cpu = (unsigned long)hcpu; | |
5325 | ||
5326 | switch (action) { | |
5327 | case CPU_ONLINE: | |
5328 | case CPU_DOWN_FAILED: | |
5329 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
5330 | break; | |
5331 | case CPU_DOWN_PREPARE: | |
5332 | smp_call_function_single(cpu, tsc_bad, NULL, 1); | |
5333 | break; | |
5334 | } | |
5335 | return NOTIFY_OK; | |
5336 | } | |
5337 | ||
5338 | static struct notifier_block kvmclock_cpu_notifier_block = { | |
5339 | .notifier_call = kvmclock_cpu_notifier, | |
5340 | .priority = -INT_MAX | |
5341 | }; | |
5342 | ||
5343 | static void kvm_timer_init(void) | |
5344 | { | |
5345 | int cpu; | |
5346 | ||
5347 | max_tsc_khz = tsc_khz; | |
5348 | register_hotcpu_notifier(&kvmclock_cpu_notifier_block); | |
5349 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { | |
5350 | #ifdef CONFIG_CPU_FREQ | |
5351 | struct cpufreq_policy policy; | |
5352 | memset(&policy, 0, sizeof(policy)); | |
5353 | cpu = get_cpu(); | |
5354 | cpufreq_get_policy(&policy, cpu); | |
5355 | if (policy.cpuinfo.max_freq) | |
5356 | max_tsc_khz = policy.cpuinfo.max_freq; | |
5357 | put_cpu(); | |
5358 | #endif | |
5359 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, | |
5360 | CPUFREQ_TRANSITION_NOTIFIER); | |
5361 | } | |
5362 | pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); | |
5363 | for_each_online_cpu(cpu) | |
5364 | smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); | |
5365 | } | |
5366 | ||
5367 | static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); | |
5368 | ||
5369 | int kvm_is_in_guest(void) | |
5370 | { | |
5371 | return __this_cpu_read(current_vcpu) != NULL; | |
5372 | } | |
5373 | ||
5374 | static int kvm_is_user_mode(void) | |
5375 | { | |
5376 | int user_mode = 3; | |
5377 | ||
5378 | if (__this_cpu_read(current_vcpu)) | |
5379 | user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); | |
5380 | ||
5381 | return user_mode != 0; | |
5382 | } | |
5383 | ||
5384 | static unsigned long kvm_get_guest_ip(void) | |
5385 | { | |
5386 | unsigned long ip = 0; | |
5387 | ||
5388 | if (__this_cpu_read(current_vcpu)) | |
5389 | ip = kvm_rip_read(__this_cpu_read(current_vcpu)); | |
5390 | ||
5391 | return ip; | |
5392 | } | |
5393 | ||
5394 | static struct perf_guest_info_callbacks kvm_guest_cbs = { | |
5395 | .is_in_guest = kvm_is_in_guest, | |
5396 | .is_user_mode = kvm_is_user_mode, | |
5397 | .get_guest_ip = kvm_get_guest_ip, | |
5398 | }; | |
5399 | ||
5400 | void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) | |
5401 | { | |
5402 | __this_cpu_write(current_vcpu, vcpu); | |
5403 | } | |
5404 | EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); | |
5405 | ||
5406 | void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) | |
5407 | { | |
5408 | __this_cpu_write(current_vcpu, NULL); | |
5409 | } | |
5410 | EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); | |
5411 | ||
5412 | static void kvm_set_mmio_spte_mask(void) | |
5413 | { | |
5414 | u64 mask; | |
5415 | int maxphyaddr = boot_cpu_data.x86_phys_bits; | |
5416 | ||
5417 | /* | |
5418 | * Set the reserved bits and the present bit of an paging-structure | |
5419 | * entry to generate page fault with PFER.RSV = 1. | |
5420 | */ | |
5421 | /* Mask the reserved physical address bits. */ | |
5422 | mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr; | |
5423 | ||
5424 | /* Bit 62 is always reserved for 32bit host. */ | |
5425 | mask |= 0x3ull << 62; | |
5426 | ||
5427 | /* Set the present bit. */ | |
5428 | mask |= 1ull; | |
5429 | ||
5430 | #ifdef CONFIG_X86_64 | |
5431 | /* | |
5432 | * If reserved bit is not supported, clear the present bit to disable | |
5433 | * mmio page fault. | |
5434 | */ | |
5435 | if (maxphyaddr == 52) | |
5436 | mask &= ~1ull; | |
5437 | #endif | |
5438 | ||
5439 | kvm_mmu_set_mmio_spte_mask(mask); | |
5440 | } | |
5441 | ||
5442 | #ifdef CONFIG_X86_64 | |
5443 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
5444 | { | |
5445 | struct kvm *kvm; | |
5446 | ||
5447 | struct kvm_vcpu *vcpu; | |
5448 | int i; | |
5449 | ||
5450 | spin_lock(&kvm_lock); | |
5451 | list_for_each_entry(kvm, &vm_list, vm_list) | |
5452 | kvm_for_each_vcpu(i, vcpu, kvm) | |
5453 | set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests); | |
5454 | atomic_set(&kvm_guest_has_master_clock, 0); | |
5455 | spin_unlock(&kvm_lock); | |
5456 | } | |
5457 | ||
5458 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
5459 | ||
5460 | /* | |
5461 | * Notification about pvclock gtod data update. | |
5462 | */ | |
5463 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
5464 | void *priv) | |
5465 | { | |
5466 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
5467 | struct timekeeper *tk = priv; | |
5468 | ||
5469 | update_pvclock_gtod(tk); | |
5470 | ||
5471 | /* disable master clock if host does not trust, or does not | |
5472 | * use, TSC clocksource | |
5473 | */ | |
5474 | if (gtod->clock.vclock_mode != VCLOCK_TSC && | |
5475 | atomic_read(&kvm_guest_has_master_clock) != 0) | |
5476 | queue_work(system_long_wq, &pvclock_gtod_work); | |
5477 | ||
5478 | return 0; | |
5479 | } | |
5480 | ||
5481 | static struct notifier_block pvclock_gtod_notifier = { | |
5482 | .notifier_call = pvclock_gtod_notify, | |
5483 | }; | |
5484 | #endif | |
5485 | ||
5486 | int kvm_arch_init(void *opaque) | |
5487 | { | |
5488 | int r; | |
5489 | struct kvm_x86_ops *ops = opaque; | |
5490 | ||
5491 | if (kvm_x86_ops) { | |
5492 | printk(KERN_ERR "kvm: already loaded the other module\n"); | |
5493 | r = -EEXIST; | |
5494 | goto out; | |
5495 | } | |
5496 | ||
5497 | if (!ops->cpu_has_kvm_support()) { | |
5498 | printk(KERN_ERR "kvm: no hardware support\n"); | |
5499 | r = -EOPNOTSUPP; | |
5500 | goto out; | |
5501 | } | |
5502 | if (ops->disabled_by_bios()) { | |
5503 | printk(KERN_ERR "kvm: disabled by bios\n"); | |
5504 | r = -EOPNOTSUPP; | |
5505 | goto out; | |
5506 | } | |
5507 | ||
5508 | r = -ENOMEM; | |
5509 | shared_msrs = alloc_percpu(struct kvm_shared_msrs); | |
5510 | if (!shared_msrs) { | |
5511 | printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); | |
5512 | goto out; | |
5513 | } | |
5514 | ||
5515 | r = kvm_mmu_module_init(); | |
5516 | if (r) | |
5517 | goto out_free_percpu; | |
5518 | ||
5519 | kvm_set_mmio_spte_mask(); | |
5520 | kvm_init_msr_list(); | |
5521 | ||
5522 | kvm_x86_ops = ops; | |
5523 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, | |
5524 | PT_DIRTY_MASK, PT64_NX_MASK, 0); | |
5525 | ||
5526 | kvm_timer_init(); | |
5527 | ||
5528 | perf_register_guest_info_callbacks(&kvm_guest_cbs); | |
5529 | ||
5530 | if (cpu_has_xsave) | |
5531 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); | |
5532 | ||
5533 | kvm_lapic_init(); | |
5534 | #ifdef CONFIG_X86_64 | |
5535 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
5536 | #endif | |
5537 | ||
5538 | return 0; | |
5539 | ||
5540 | out_free_percpu: | |
5541 | free_percpu(shared_msrs); | |
5542 | out: | |
5543 | return r; | |
5544 | } | |
5545 | ||
5546 | void kvm_arch_exit(void) | |
5547 | { | |
5548 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); | |
5549 | ||
5550 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
5551 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
5552 | CPUFREQ_TRANSITION_NOTIFIER); | |
5553 | unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); | |
5554 | #ifdef CONFIG_X86_64 | |
5555 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
5556 | #endif | |
5557 | kvm_x86_ops = NULL; | |
5558 | kvm_mmu_module_exit(); | |
5559 | free_percpu(shared_msrs); | |
5560 | } | |
5561 | ||
5562 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) | |
5563 | { | |
5564 | ++vcpu->stat.halt_exits; | |
5565 | if (irqchip_in_kernel(vcpu->kvm)) { | |
5566 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; | |
5567 | return 1; | |
5568 | } else { | |
5569 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
5570 | return 0; | |
5571 | } | |
5572 | } | |
5573 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); | |
5574 | ||
5575 | int kvm_hv_hypercall(struct kvm_vcpu *vcpu) | |
5576 | { | |
5577 | u64 param, ingpa, outgpa, ret; | |
5578 | uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0; | |
5579 | bool fast, longmode; | |
5580 | int cs_db, cs_l; | |
5581 | ||
5582 | /* | |
5583 | * hypercall generates UD from non zero cpl and real mode | |
5584 | * per HYPER-V spec | |
5585 | */ | |
5586 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) { | |
5587 | kvm_queue_exception(vcpu, UD_VECTOR); | |
5588 | return 0; | |
5589 | } | |
5590 | ||
5591 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
5592 | longmode = is_long_mode(vcpu) && cs_l == 1; | |
5593 | ||
5594 | if (!longmode) { | |
5595 | param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) | | |
5596 | (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff); | |
5597 | ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) | | |
5598 | (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff); | |
5599 | outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) | | |
5600 | (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff); | |
5601 | } | |
5602 | #ifdef CONFIG_X86_64 | |
5603 | else { | |
5604 | param = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5605 | ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
5606 | outgpa = kvm_register_read(vcpu, VCPU_REGS_R8); | |
5607 | } | |
5608 | #endif | |
5609 | ||
5610 | code = param & 0xffff; | |
5611 | fast = (param >> 16) & 0x1; | |
5612 | rep_cnt = (param >> 32) & 0xfff; | |
5613 | rep_idx = (param >> 48) & 0xfff; | |
5614 | ||
5615 | trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa); | |
5616 | ||
5617 | switch (code) { | |
5618 | case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT: | |
5619 | kvm_vcpu_on_spin(vcpu); | |
5620 | break; | |
5621 | default: | |
5622 | res = HV_STATUS_INVALID_HYPERCALL_CODE; | |
5623 | break; | |
5624 | } | |
5625 | ||
5626 | ret = res | (((u64)rep_done & 0xfff) << 32); | |
5627 | if (longmode) { | |
5628 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); | |
5629 | } else { | |
5630 | kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32); | |
5631 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff); | |
5632 | } | |
5633 | ||
5634 | return 1; | |
5635 | } | |
5636 | ||
5637 | /* | |
5638 | * kvm_pv_kick_cpu_op: Kick a vcpu. | |
5639 | * | |
5640 | * @apicid - apicid of vcpu to be kicked. | |
5641 | */ | |
5642 | static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) | |
5643 | { | |
5644 | struct kvm_lapic_irq lapic_irq; | |
5645 | ||
5646 | lapic_irq.shorthand = 0; | |
5647 | lapic_irq.dest_mode = 0; | |
5648 | lapic_irq.dest_id = apicid; | |
5649 | ||
5650 | lapic_irq.delivery_mode = APIC_DM_REMRD; | |
5651 | kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL); | |
5652 | } | |
5653 | ||
5654 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) | |
5655 | { | |
5656 | unsigned long nr, a0, a1, a2, a3, ret; | |
5657 | int r = 1; | |
5658 | ||
5659 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) | |
5660 | return kvm_hv_hypercall(vcpu); | |
5661 | ||
5662 | nr = kvm_register_read(vcpu, VCPU_REGS_RAX); | |
5663 | a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
5664 | a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5665 | a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
5666 | a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
5667 | ||
5668 | trace_kvm_hypercall(nr, a0, a1, a2, a3); | |
5669 | ||
5670 | if (!is_long_mode(vcpu)) { | |
5671 | nr &= 0xFFFFFFFF; | |
5672 | a0 &= 0xFFFFFFFF; | |
5673 | a1 &= 0xFFFFFFFF; | |
5674 | a2 &= 0xFFFFFFFF; | |
5675 | a3 &= 0xFFFFFFFF; | |
5676 | } | |
5677 | ||
5678 | if (kvm_x86_ops->get_cpl(vcpu) != 0) { | |
5679 | ret = -KVM_EPERM; | |
5680 | goto out; | |
5681 | } | |
5682 | ||
5683 | switch (nr) { | |
5684 | case KVM_HC_VAPIC_POLL_IRQ: | |
5685 | ret = 0; | |
5686 | break; | |
5687 | case KVM_HC_KICK_CPU: | |
5688 | kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); | |
5689 | ret = 0; | |
5690 | break; | |
5691 | default: | |
5692 | ret = -KVM_ENOSYS; | |
5693 | break; | |
5694 | } | |
5695 | out: | |
5696 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); | |
5697 | ++vcpu->stat.hypercalls; | |
5698 | return r; | |
5699 | } | |
5700 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
5701 | ||
5702 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) | |
5703 | { | |
5704 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
5705 | char instruction[3]; | |
5706 | unsigned long rip = kvm_rip_read(vcpu); | |
5707 | ||
5708 | kvm_x86_ops->patch_hypercall(vcpu, instruction); | |
5709 | ||
5710 | return emulator_write_emulated(ctxt, rip, instruction, 3, NULL); | |
5711 | } | |
5712 | ||
5713 | /* | |
5714 | * Check if userspace requested an interrupt window, and that the | |
5715 | * interrupt window is open. | |
5716 | * | |
5717 | * No need to exit to userspace if we already have an interrupt queued. | |
5718 | */ | |
5719 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) | |
5720 | { | |
5721 | return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) && | |
5722 | vcpu->run->request_interrupt_window && | |
5723 | kvm_arch_interrupt_allowed(vcpu)); | |
5724 | } | |
5725 | ||
5726 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) | |
5727 | { | |
5728 | struct kvm_run *kvm_run = vcpu->run; | |
5729 | ||
5730 | kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; | |
5731 | kvm_run->cr8 = kvm_get_cr8(vcpu); | |
5732 | kvm_run->apic_base = kvm_get_apic_base(vcpu); | |
5733 | if (irqchip_in_kernel(vcpu->kvm)) | |
5734 | kvm_run->ready_for_interrupt_injection = 1; | |
5735 | else | |
5736 | kvm_run->ready_for_interrupt_injection = | |
5737 | kvm_arch_interrupt_allowed(vcpu) && | |
5738 | !kvm_cpu_has_interrupt(vcpu) && | |
5739 | !kvm_event_needs_reinjection(vcpu); | |
5740 | } | |
5741 | ||
5742 | static int vapic_enter(struct kvm_vcpu *vcpu) | |
5743 | { | |
5744 | struct kvm_lapic *apic = vcpu->arch.apic; | |
5745 | struct page *page; | |
5746 | ||
5747 | if (!apic || !apic->vapic_addr) | |
5748 | return 0; | |
5749 | ||
5750 | page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
5751 | if (is_error_page(page)) | |
5752 | return -EFAULT; | |
5753 | ||
5754 | vcpu->arch.apic->vapic_page = page; | |
5755 | return 0; | |
5756 | } | |
5757 | ||
5758 | static void vapic_exit(struct kvm_vcpu *vcpu) | |
5759 | { | |
5760 | struct kvm_lapic *apic = vcpu->arch.apic; | |
5761 | int idx; | |
5762 | ||
5763 | if (!apic || !apic->vapic_addr) | |
5764 | return; | |
5765 | ||
5766 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
5767 | kvm_release_page_dirty(apic->vapic_page); | |
5768 | mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
5769 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
5770 | } | |
5771 | ||
5772 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) | |
5773 | { | |
5774 | int max_irr, tpr; | |
5775 | ||
5776 | if (!kvm_x86_ops->update_cr8_intercept) | |
5777 | return; | |
5778 | ||
5779 | if (!vcpu->arch.apic) | |
5780 | return; | |
5781 | ||
5782 | if (!vcpu->arch.apic->vapic_addr) | |
5783 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
5784 | else | |
5785 | max_irr = -1; | |
5786 | ||
5787 | if (max_irr != -1) | |
5788 | max_irr >>= 4; | |
5789 | ||
5790 | tpr = kvm_lapic_get_cr8(vcpu); | |
5791 | ||
5792 | kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); | |
5793 | } | |
5794 | ||
5795 | static void inject_pending_event(struct kvm_vcpu *vcpu) | |
5796 | { | |
5797 | /* try to reinject previous events if any */ | |
5798 | if (vcpu->arch.exception.pending) { | |
5799 | trace_kvm_inj_exception(vcpu->arch.exception.nr, | |
5800 | vcpu->arch.exception.has_error_code, | |
5801 | vcpu->arch.exception.error_code); | |
5802 | kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, | |
5803 | vcpu->arch.exception.has_error_code, | |
5804 | vcpu->arch.exception.error_code, | |
5805 | vcpu->arch.exception.reinject); | |
5806 | return; | |
5807 | } | |
5808 | ||
5809 | if (vcpu->arch.nmi_injected) { | |
5810 | kvm_x86_ops->set_nmi(vcpu); | |
5811 | return; | |
5812 | } | |
5813 | ||
5814 | if (vcpu->arch.interrupt.pending) { | |
5815 | kvm_x86_ops->set_irq(vcpu); | |
5816 | return; | |
5817 | } | |
5818 | ||
5819 | /* try to inject new event if pending */ | |
5820 | if (vcpu->arch.nmi_pending) { | |
5821 | if (kvm_x86_ops->nmi_allowed(vcpu)) { | |
5822 | --vcpu->arch.nmi_pending; | |
5823 | vcpu->arch.nmi_injected = true; | |
5824 | kvm_x86_ops->set_nmi(vcpu); | |
5825 | } | |
5826 | } else if (kvm_cpu_has_injectable_intr(vcpu)) { | |
5827 | if (kvm_x86_ops->interrupt_allowed(vcpu)) { | |
5828 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), | |
5829 | false); | |
5830 | kvm_x86_ops->set_irq(vcpu); | |
5831 | } | |
5832 | } | |
5833 | } | |
5834 | ||
5835 | static void process_nmi(struct kvm_vcpu *vcpu) | |
5836 | { | |
5837 | unsigned limit = 2; | |
5838 | ||
5839 | /* | |
5840 | * x86 is limited to one NMI running, and one NMI pending after it. | |
5841 | * If an NMI is already in progress, limit further NMIs to just one. | |
5842 | * Otherwise, allow two (and we'll inject the first one immediately). | |
5843 | */ | |
5844 | if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) | |
5845 | limit = 1; | |
5846 | ||
5847 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
5848 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
5849 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
5850 | } | |
5851 | ||
5852 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) | |
5853 | { | |
5854 | u64 eoi_exit_bitmap[4]; | |
5855 | u32 tmr[8]; | |
5856 | ||
5857 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) | |
5858 | return; | |
5859 | ||
5860 | memset(eoi_exit_bitmap, 0, 32); | |
5861 | memset(tmr, 0, 32); | |
5862 | ||
5863 | kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr); | |
5864 | kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); | |
5865 | kvm_apic_update_tmr(vcpu, tmr); | |
5866 | } | |
5867 | ||
5868 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) | |
5869 | { | |
5870 | int r; | |
5871 | bool req_int_win = !irqchip_in_kernel(vcpu->kvm) && | |
5872 | vcpu->run->request_interrupt_window; | |
5873 | bool req_immediate_exit = false; | |
5874 | ||
5875 | if (vcpu->requests) { | |
5876 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) | |
5877 | kvm_mmu_unload(vcpu); | |
5878 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) | |
5879 | __kvm_migrate_timers(vcpu); | |
5880 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) | |
5881 | kvm_gen_update_masterclock(vcpu->kvm); | |
5882 | if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) | |
5883 | kvm_gen_kvmclock_update(vcpu); | |
5884 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { | |
5885 | r = kvm_guest_time_update(vcpu); | |
5886 | if (unlikely(r)) | |
5887 | goto out; | |
5888 | } | |
5889 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) | |
5890 | kvm_mmu_sync_roots(vcpu); | |
5891 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) | |
5892 | kvm_x86_ops->tlb_flush(vcpu); | |
5893 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { | |
5894 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; | |
5895 | r = 0; | |
5896 | goto out; | |
5897 | } | |
5898 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { | |
5899 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; | |
5900 | r = 0; | |
5901 | goto out; | |
5902 | } | |
5903 | if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { | |
5904 | vcpu->fpu_active = 0; | |
5905 | kvm_x86_ops->fpu_deactivate(vcpu); | |
5906 | } | |
5907 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { | |
5908 | /* Page is swapped out. Do synthetic halt */ | |
5909 | vcpu->arch.apf.halted = true; | |
5910 | r = 1; | |
5911 | goto out; | |
5912 | } | |
5913 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) | |
5914 | record_steal_time(vcpu); | |
5915 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) | |
5916 | process_nmi(vcpu); | |
5917 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) | |
5918 | kvm_handle_pmu_event(vcpu); | |
5919 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) | |
5920 | kvm_deliver_pmi(vcpu); | |
5921 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) | |
5922 | vcpu_scan_ioapic(vcpu); | |
5923 | } | |
5924 | ||
5925 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { | |
5926 | kvm_apic_accept_events(vcpu); | |
5927 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { | |
5928 | r = 1; | |
5929 | goto out; | |
5930 | } | |
5931 | ||
5932 | inject_pending_event(vcpu); | |
5933 | ||
5934 | /* enable NMI/IRQ window open exits if needed */ | |
5935 | if (vcpu->arch.nmi_pending) | |
5936 | req_immediate_exit = | |
5937 | kvm_x86_ops->enable_nmi_window(vcpu) != 0; | |
5938 | else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) | |
5939 | req_immediate_exit = | |
5940 | kvm_x86_ops->enable_irq_window(vcpu) != 0; | |
5941 | ||
5942 | if (kvm_lapic_enabled(vcpu)) { | |
5943 | /* | |
5944 | * Update architecture specific hints for APIC | |
5945 | * virtual interrupt delivery. | |
5946 | */ | |
5947 | if (kvm_x86_ops->hwapic_irr_update) | |
5948 | kvm_x86_ops->hwapic_irr_update(vcpu, | |
5949 | kvm_lapic_find_highest_irr(vcpu)); | |
5950 | update_cr8_intercept(vcpu); | |
5951 | kvm_lapic_sync_to_vapic(vcpu); | |
5952 | } | |
5953 | } | |
5954 | ||
5955 | r = kvm_mmu_reload(vcpu); | |
5956 | if (unlikely(r)) { | |
5957 | goto cancel_injection; | |
5958 | } | |
5959 | ||
5960 | preempt_disable(); | |
5961 | ||
5962 | kvm_x86_ops->prepare_guest_switch(vcpu); | |
5963 | if (vcpu->fpu_active) | |
5964 | kvm_load_guest_fpu(vcpu); | |
5965 | kvm_load_guest_xcr0(vcpu); | |
5966 | ||
5967 | vcpu->mode = IN_GUEST_MODE; | |
5968 | ||
5969 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); | |
5970 | ||
5971 | /* We should set ->mode before check ->requests, | |
5972 | * see the comment in make_all_cpus_request. | |
5973 | */ | |
5974 | smp_mb__after_srcu_read_unlock(); | |
5975 | ||
5976 | local_irq_disable(); | |
5977 | ||
5978 | if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests | |
5979 | || need_resched() || signal_pending(current)) { | |
5980 | vcpu->mode = OUTSIDE_GUEST_MODE; | |
5981 | smp_wmb(); | |
5982 | local_irq_enable(); | |
5983 | preempt_enable(); | |
5984 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); | |
5985 | r = 1; | |
5986 | goto cancel_injection; | |
5987 | } | |
5988 | ||
5989 | if (req_immediate_exit) | |
5990 | smp_send_reschedule(vcpu->cpu); | |
5991 | ||
5992 | kvm_guest_enter(); | |
5993 | ||
5994 | if (unlikely(vcpu->arch.switch_db_regs)) { | |
5995 | set_debugreg(0, 7); | |
5996 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
5997 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
5998 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
5999 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
6000 | } | |
6001 | ||
6002 | trace_kvm_entry(vcpu->vcpu_id); | |
6003 | kvm_x86_ops->run(vcpu); | |
6004 | ||
6005 | /* | |
6006 | * If the guest has used debug registers, at least dr7 | |
6007 | * will be disabled while returning to the host. | |
6008 | * If we don't have active breakpoints in the host, we don't | |
6009 | * care about the messed up debug address registers. But if | |
6010 | * we have some of them active, restore the old state. | |
6011 | */ | |
6012 | if (hw_breakpoint_active()) | |
6013 | hw_breakpoint_restore(); | |
6014 | ||
6015 | vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, | |
6016 | native_read_tsc()); | |
6017 | ||
6018 | vcpu->mode = OUTSIDE_GUEST_MODE; | |
6019 | smp_wmb(); | |
6020 | ||
6021 | /* Interrupt is enabled by handle_external_intr() */ | |
6022 | kvm_x86_ops->handle_external_intr(vcpu); | |
6023 | ||
6024 | ++vcpu->stat.exits; | |
6025 | ||
6026 | /* | |
6027 | * We must have an instruction between local_irq_enable() and | |
6028 | * kvm_guest_exit(), so the timer interrupt isn't delayed by | |
6029 | * the interrupt shadow. The stat.exits increment will do nicely. | |
6030 | * But we need to prevent reordering, hence this barrier(): | |
6031 | */ | |
6032 | barrier(); | |
6033 | ||
6034 | kvm_guest_exit(); | |
6035 | ||
6036 | preempt_enable(); | |
6037 | ||
6038 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); | |
6039 | ||
6040 | /* | |
6041 | * Profile KVM exit RIPs: | |
6042 | */ | |
6043 | if (unlikely(prof_on == KVM_PROFILING)) { | |
6044 | unsigned long rip = kvm_rip_read(vcpu); | |
6045 | profile_hit(KVM_PROFILING, (void *)rip); | |
6046 | } | |
6047 | ||
6048 | if (unlikely(vcpu->arch.tsc_always_catchup)) | |
6049 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
6050 | ||
6051 | if (vcpu->arch.apic_attention) | |
6052 | kvm_lapic_sync_from_vapic(vcpu); | |
6053 | ||
6054 | r = kvm_x86_ops->handle_exit(vcpu); | |
6055 | return r; | |
6056 | ||
6057 | cancel_injection: | |
6058 | kvm_x86_ops->cancel_injection(vcpu); | |
6059 | if (unlikely(vcpu->arch.apic_attention)) | |
6060 | kvm_lapic_sync_from_vapic(vcpu); | |
6061 | out: | |
6062 | return r; | |
6063 | } | |
6064 | ||
6065 | ||
6066 | static int __vcpu_run(struct kvm_vcpu *vcpu) | |
6067 | { | |
6068 | int r; | |
6069 | struct kvm *kvm = vcpu->kvm; | |
6070 | ||
6071 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); | |
6072 | r = vapic_enter(vcpu); | |
6073 | if (r) { | |
6074 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); | |
6075 | return r; | |
6076 | } | |
6077 | ||
6078 | r = 1; | |
6079 | while (r > 0) { | |
6080 | if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && | |
6081 | !vcpu->arch.apf.halted) | |
6082 | r = vcpu_enter_guest(vcpu); | |
6083 | else { | |
6084 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); | |
6085 | kvm_vcpu_block(vcpu); | |
6086 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); | |
6087 | if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) { | |
6088 | kvm_apic_accept_events(vcpu); | |
6089 | switch(vcpu->arch.mp_state) { | |
6090 | case KVM_MP_STATE_HALTED: | |
6091 | vcpu->arch.pv.pv_unhalted = false; | |
6092 | vcpu->arch.mp_state = | |
6093 | KVM_MP_STATE_RUNNABLE; | |
6094 | case KVM_MP_STATE_RUNNABLE: | |
6095 | vcpu->arch.apf.halted = false; | |
6096 | break; | |
6097 | case KVM_MP_STATE_INIT_RECEIVED: | |
6098 | break; | |
6099 | default: | |
6100 | r = -EINTR; | |
6101 | break; | |
6102 | } | |
6103 | } | |
6104 | } | |
6105 | ||
6106 | if (r <= 0) | |
6107 | break; | |
6108 | ||
6109 | clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); | |
6110 | if (kvm_cpu_has_pending_timer(vcpu)) | |
6111 | kvm_inject_pending_timer_irqs(vcpu); | |
6112 | ||
6113 | if (dm_request_for_irq_injection(vcpu)) { | |
6114 | r = -EINTR; | |
6115 | vcpu->run->exit_reason = KVM_EXIT_INTR; | |
6116 | ++vcpu->stat.request_irq_exits; | |
6117 | } | |
6118 | ||
6119 | kvm_check_async_pf_completion(vcpu); | |
6120 | ||
6121 | if (signal_pending(current)) { | |
6122 | r = -EINTR; | |
6123 | vcpu->run->exit_reason = KVM_EXIT_INTR; | |
6124 | ++vcpu->stat.signal_exits; | |
6125 | } | |
6126 | if (need_resched()) { | |
6127 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); | |
6128 | kvm_resched(vcpu); | |
6129 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); | |
6130 | } | |
6131 | } | |
6132 | ||
6133 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); | |
6134 | ||
6135 | vapic_exit(vcpu); | |
6136 | ||
6137 | return r; | |
6138 | } | |
6139 | ||
6140 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) | |
6141 | { | |
6142 | int r; | |
6143 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); | |
6144 | r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); | |
6145 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); | |
6146 | if (r != EMULATE_DONE) | |
6147 | return 0; | |
6148 | return 1; | |
6149 | } | |
6150 | ||
6151 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
6152 | { | |
6153 | BUG_ON(!vcpu->arch.pio.count); | |
6154 | ||
6155 | return complete_emulated_io(vcpu); | |
6156 | } | |
6157 | ||
6158 | /* | |
6159 | * Implements the following, as a state machine: | |
6160 | * | |
6161 | * read: | |
6162 | * for each fragment | |
6163 | * for each mmio piece in the fragment | |
6164 | * write gpa, len | |
6165 | * exit | |
6166 | * copy data | |
6167 | * execute insn | |
6168 | * | |
6169 | * write: | |
6170 | * for each fragment | |
6171 | * for each mmio piece in the fragment | |
6172 | * write gpa, len | |
6173 | * copy data | |
6174 | * exit | |
6175 | */ | |
6176 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) | |
6177 | { | |
6178 | struct kvm_run *run = vcpu->run; | |
6179 | struct kvm_mmio_fragment *frag; | |
6180 | unsigned len; | |
6181 | ||
6182 | BUG_ON(!vcpu->mmio_needed); | |
6183 | ||
6184 | /* Complete previous fragment */ | |
6185 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; | |
6186 | len = min(8u, frag->len); | |
6187 | if (!vcpu->mmio_is_write) | |
6188 | memcpy(frag->data, run->mmio.data, len); | |
6189 | ||
6190 | if (frag->len <= 8) { | |
6191 | /* Switch to the next fragment. */ | |
6192 | frag++; | |
6193 | vcpu->mmio_cur_fragment++; | |
6194 | } else { | |
6195 | /* Go forward to the next mmio piece. */ | |
6196 | frag->data += len; | |
6197 | frag->gpa += len; | |
6198 | frag->len -= len; | |
6199 | } | |
6200 | ||
6201 | if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) { | |
6202 | vcpu->mmio_needed = 0; | |
6203 | ||
6204 | /* FIXME: return into emulator if single-stepping. */ | |
6205 | if (vcpu->mmio_is_write) | |
6206 | return 1; | |
6207 | vcpu->mmio_read_completed = 1; | |
6208 | return complete_emulated_io(vcpu); | |
6209 | } | |
6210 | ||
6211 | run->exit_reason = KVM_EXIT_MMIO; | |
6212 | run->mmio.phys_addr = frag->gpa; | |
6213 | if (vcpu->mmio_is_write) | |
6214 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); | |
6215 | run->mmio.len = min(8u, frag->len); | |
6216 | run->mmio.is_write = vcpu->mmio_is_write; | |
6217 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
6218 | return 0; | |
6219 | } | |
6220 | ||
6221 | ||
6222 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
6223 | { | |
6224 | int r; | |
6225 | sigset_t sigsaved; | |
6226 | ||
6227 | if (!tsk_used_math(current) && init_fpu(current)) | |
6228 | return -ENOMEM; | |
6229 | ||
6230 | if (vcpu->sigset_active) | |
6231 | sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); | |
6232 | ||
6233 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { | |
6234 | kvm_vcpu_block(vcpu); | |
6235 | kvm_apic_accept_events(vcpu); | |
6236 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); | |
6237 | r = -EAGAIN; | |
6238 | goto out; | |
6239 | } | |
6240 | ||
6241 | /* re-sync apic's tpr */ | |
6242 | if (!irqchip_in_kernel(vcpu->kvm)) { | |
6243 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { | |
6244 | r = -EINVAL; | |
6245 | goto out; | |
6246 | } | |
6247 | } | |
6248 | ||
6249 | if (unlikely(vcpu->arch.complete_userspace_io)) { | |
6250 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
6251 | vcpu->arch.complete_userspace_io = NULL; | |
6252 | r = cui(vcpu); | |
6253 | if (r <= 0) | |
6254 | goto out; | |
6255 | } else | |
6256 | WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); | |
6257 | ||
6258 | r = __vcpu_run(vcpu); | |
6259 | ||
6260 | out: | |
6261 | post_kvm_run_save(vcpu); | |
6262 | if (vcpu->sigset_active) | |
6263 | sigprocmask(SIG_SETMASK, &sigsaved, NULL); | |
6264 | ||
6265 | return r; | |
6266 | } | |
6267 | ||
6268 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
6269 | { | |
6270 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { | |
6271 | /* | |
6272 | * We are here if userspace calls get_regs() in the middle of | |
6273 | * instruction emulation. Registers state needs to be copied | |
6274 | * back from emulation context to vcpu. Userspace shouldn't do | |
6275 | * that usually, but some bad designed PV devices (vmware | |
6276 | * backdoor interface) need this to work | |
6277 | */ | |
6278 | emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); | |
6279 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
6280 | } | |
6281 | regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); | |
6282 | regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
6283 | regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
6284 | regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
6285 | regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
6286 | regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
6287 | regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
6288 | regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
6289 | #ifdef CONFIG_X86_64 | |
6290 | regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); | |
6291 | regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); | |
6292 | regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); | |
6293 | regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); | |
6294 | regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); | |
6295 | regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); | |
6296 | regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); | |
6297 | regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); | |
6298 | #endif | |
6299 | ||
6300 | regs->rip = kvm_rip_read(vcpu); | |
6301 | regs->rflags = kvm_get_rflags(vcpu); | |
6302 | ||
6303 | return 0; | |
6304 | } | |
6305 | ||
6306 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
6307 | { | |
6308 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; | |
6309 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
6310 | ||
6311 | kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); | |
6312 | kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); | |
6313 | kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); | |
6314 | kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); | |
6315 | kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); | |
6316 | kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); | |
6317 | kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); | |
6318 | kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); | |
6319 | #ifdef CONFIG_X86_64 | |
6320 | kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); | |
6321 | kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); | |
6322 | kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); | |
6323 | kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); | |
6324 | kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); | |
6325 | kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); | |
6326 | kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); | |
6327 | kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); | |
6328 | #endif | |
6329 | ||
6330 | kvm_rip_write(vcpu, regs->rip); | |
6331 | kvm_set_rflags(vcpu, regs->rflags); | |
6332 | ||
6333 | vcpu->arch.exception.pending = false; | |
6334 | ||
6335 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
6336 | ||
6337 | return 0; | |
6338 | } | |
6339 | ||
6340 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) | |
6341 | { | |
6342 | struct kvm_segment cs; | |
6343 | ||
6344 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
6345 | *db = cs.db; | |
6346 | *l = cs.l; | |
6347 | } | |
6348 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
6349 | ||
6350 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, | |
6351 | struct kvm_sregs *sregs) | |
6352 | { | |
6353 | struct desc_ptr dt; | |
6354 | ||
6355 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); | |
6356 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
6357 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
6358 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
6359 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
6360 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
6361 | ||
6362 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); | |
6363 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
6364 | ||
6365 | kvm_x86_ops->get_idt(vcpu, &dt); | |
6366 | sregs->idt.limit = dt.size; | |
6367 | sregs->idt.base = dt.address; | |
6368 | kvm_x86_ops->get_gdt(vcpu, &dt); | |
6369 | sregs->gdt.limit = dt.size; | |
6370 | sregs->gdt.base = dt.address; | |
6371 | ||
6372 | sregs->cr0 = kvm_read_cr0(vcpu); | |
6373 | sregs->cr2 = vcpu->arch.cr2; | |
6374 | sregs->cr3 = kvm_read_cr3(vcpu); | |
6375 | sregs->cr4 = kvm_read_cr4(vcpu); | |
6376 | sregs->cr8 = kvm_get_cr8(vcpu); | |
6377 | sregs->efer = vcpu->arch.efer; | |
6378 | sregs->apic_base = kvm_get_apic_base(vcpu); | |
6379 | ||
6380 | memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); | |
6381 | ||
6382 | if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) | |
6383 | set_bit(vcpu->arch.interrupt.nr, | |
6384 | (unsigned long *)sregs->interrupt_bitmap); | |
6385 | ||
6386 | return 0; | |
6387 | } | |
6388 | ||
6389 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, | |
6390 | struct kvm_mp_state *mp_state) | |
6391 | { | |
6392 | kvm_apic_accept_events(vcpu); | |
6393 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && | |
6394 | vcpu->arch.pv.pv_unhalted) | |
6395 | mp_state->mp_state = KVM_MP_STATE_RUNNABLE; | |
6396 | else | |
6397 | mp_state->mp_state = vcpu->arch.mp_state; | |
6398 | ||
6399 | return 0; | |
6400 | } | |
6401 | ||
6402 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
6403 | struct kvm_mp_state *mp_state) | |
6404 | { | |
6405 | if (!kvm_vcpu_has_lapic(vcpu) && | |
6406 | mp_state->mp_state != KVM_MP_STATE_RUNNABLE) | |
6407 | return -EINVAL; | |
6408 | ||
6409 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { | |
6410 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
6411 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
6412 | } else | |
6413 | vcpu->arch.mp_state = mp_state->mp_state; | |
6414 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
6415 | return 0; | |
6416 | } | |
6417 | ||
6418 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, | |
6419 | int reason, bool has_error_code, u32 error_code) | |
6420 | { | |
6421 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; | |
6422 | int ret; | |
6423 | ||
6424 | init_emulate_ctxt(vcpu); | |
6425 | ||
6426 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, | |
6427 | has_error_code, error_code); | |
6428 | ||
6429 | if (ret) | |
6430 | return EMULATE_FAIL; | |
6431 | ||
6432 | kvm_rip_write(vcpu, ctxt->eip); | |
6433 | kvm_set_rflags(vcpu, ctxt->eflags); | |
6434 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
6435 | return EMULATE_DONE; | |
6436 | } | |
6437 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
6438 | ||
6439 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, | |
6440 | struct kvm_sregs *sregs) | |
6441 | { | |
6442 | int mmu_reset_needed = 0; | |
6443 | int pending_vec, max_bits, idx; | |
6444 | struct desc_ptr dt; | |
6445 | ||
6446 | if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE)) | |
6447 | return -EINVAL; | |
6448 | ||
6449 | dt.size = sregs->idt.limit; | |
6450 | dt.address = sregs->idt.base; | |
6451 | kvm_x86_ops->set_idt(vcpu, &dt); | |
6452 | dt.size = sregs->gdt.limit; | |
6453 | dt.address = sregs->gdt.base; | |
6454 | kvm_x86_ops->set_gdt(vcpu, &dt); | |
6455 | ||
6456 | vcpu->arch.cr2 = sregs->cr2; | |
6457 | mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; | |
6458 | vcpu->arch.cr3 = sregs->cr3; | |
6459 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); | |
6460 | ||
6461 | kvm_set_cr8(vcpu, sregs->cr8); | |
6462 | ||
6463 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; | |
6464 | kvm_x86_ops->set_efer(vcpu, sregs->efer); | |
6465 | kvm_set_apic_base(vcpu, sregs->apic_base); | |
6466 | ||
6467 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; | |
6468 | kvm_x86_ops->set_cr0(vcpu, sregs->cr0); | |
6469 | vcpu->arch.cr0 = sregs->cr0; | |
6470 | ||
6471 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; | |
6472 | kvm_x86_ops->set_cr4(vcpu, sregs->cr4); | |
6473 | if (sregs->cr4 & X86_CR4_OSXSAVE) | |
6474 | kvm_update_cpuid(vcpu); | |
6475 | ||
6476 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
6477 | if (!is_long_mode(vcpu) && is_pae(vcpu)) { | |
6478 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); | |
6479 | mmu_reset_needed = 1; | |
6480 | } | |
6481 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
6482 | ||
6483 | if (mmu_reset_needed) | |
6484 | kvm_mmu_reset_context(vcpu); | |
6485 | ||
6486 | max_bits = KVM_NR_INTERRUPTS; | |
6487 | pending_vec = find_first_bit( | |
6488 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
6489 | if (pending_vec < max_bits) { | |
6490 | kvm_queue_interrupt(vcpu, pending_vec, false); | |
6491 | pr_debug("Set back pending irq %d\n", pending_vec); | |
6492 | } | |
6493 | ||
6494 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); | |
6495 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
6496 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
6497 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
6498 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
6499 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
6500 | ||
6501 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); | |
6502 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
6503 | ||
6504 | update_cr8_intercept(vcpu); | |
6505 | ||
6506 | /* Older userspace won't unhalt the vcpu on reset. */ | |
6507 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && | |
6508 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && | |
6509 | !is_protmode(vcpu)) | |
6510 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
6511 | ||
6512 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
6513 | ||
6514 | return 0; | |
6515 | } | |
6516 | ||
6517 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, | |
6518 | struct kvm_guest_debug *dbg) | |
6519 | { | |
6520 | unsigned long rflags; | |
6521 | int i, r; | |
6522 | ||
6523 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { | |
6524 | r = -EBUSY; | |
6525 | if (vcpu->arch.exception.pending) | |
6526 | goto out; | |
6527 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) | |
6528 | kvm_queue_exception(vcpu, DB_VECTOR); | |
6529 | else | |
6530 | kvm_queue_exception(vcpu, BP_VECTOR); | |
6531 | } | |
6532 | ||
6533 | /* | |
6534 | * Read rflags as long as potentially injected trace flags are still | |
6535 | * filtered out. | |
6536 | */ | |
6537 | rflags = kvm_get_rflags(vcpu); | |
6538 | ||
6539 | vcpu->guest_debug = dbg->control; | |
6540 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
6541 | vcpu->guest_debug = 0; | |
6542 | ||
6543 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
6544 | for (i = 0; i < KVM_NR_DB_REGS; ++i) | |
6545 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
6546 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; | |
6547 | } else { | |
6548 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
6549 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
6550 | } | |
6551 | kvm_update_dr7(vcpu); | |
6552 | ||
6553 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
6554 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + | |
6555 | get_segment_base(vcpu, VCPU_SREG_CS); | |
6556 | ||
6557 | /* | |
6558 | * Trigger an rflags update that will inject or remove the trace | |
6559 | * flags. | |
6560 | */ | |
6561 | kvm_set_rflags(vcpu, rflags); | |
6562 | ||
6563 | kvm_x86_ops->update_db_bp_intercept(vcpu); | |
6564 | ||
6565 | r = 0; | |
6566 | ||
6567 | out: | |
6568 | ||
6569 | return r; | |
6570 | } | |
6571 | ||
6572 | /* | |
6573 | * Translate a guest virtual address to a guest physical address. | |
6574 | */ | |
6575 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
6576 | struct kvm_translation *tr) | |
6577 | { | |
6578 | unsigned long vaddr = tr->linear_address; | |
6579 | gpa_t gpa; | |
6580 | int idx; | |
6581 | ||
6582 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
6583 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); | |
6584 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
6585 | tr->physical_address = gpa; | |
6586 | tr->valid = gpa != UNMAPPED_GVA; | |
6587 | tr->writeable = 1; | |
6588 | tr->usermode = 0; | |
6589 | ||
6590 | return 0; | |
6591 | } | |
6592 | ||
6593 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
6594 | { | |
6595 | struct i387_fxsave_struct *fxsave = | |
6596 | &vcpu->arch.guest_fpu.state->fxsave; | |
6597 | ||
6598 | memcpy(fpu->fpr, fxsave->st_space, 128); | |
6599 | fpu->fcw = fxsave->cwd; | |
6600 | fpu->fsw = fxsave->swd; | |
6601 | fpu->ftwx = fxsave->twd; | |
6602 | fpu->last_opcode = fxsave->fop; | |
6603 | fpu->last_ip = fxsave->rip; | |
6604 | fpu->last_dp = fxsave->rdp; | |
6605 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); | |
6606 | ||
6607 | return 0; | |
6608 | } | |
6609 | ||
6610 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
6611 | { | |
6612 | struct i387_fxsave_struct *fxsave = | |
6613 | &vcpu->arch.guest_fpu.state->fxsave; | |
6614 | ||
6615 | memcpy(fxsave->st_space, fpu->fpr, 128); | |
6616 | fxsave->cwd = fpu->fcw; | |
6617 | fxsave->swd = fpu->fsw; | |
6618 | fxsave->twd = fpu->ftwx; | |
6619 | fxsave->fop = fpu->last_opcode; | |
6620 | fxsave->rip = fpu->last_ip; | |
6621 | fxsave->rdp = fpu->last_dp; | |
6622 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); | |
6623 | ||
6624 | return 0; | |
6625 | } | |
6626 | ||
6627 | int fx_init(struct kvm_vcpu *vcpu) | |
6628 | { | |
6629 | int err; | |
6630 | ||
6631 | err = fpu_alloc(&vcpu->arch.guest_fpu); | |
6632 | if (err) | |
6633 | return err; | |
6634 | ||
6635 | fpu_finit(&vcpu->arch.guest_fpu); | |
6636 | ||
6637 | /* | |
6638 | * Ensure guest xcr0 is valid for loading | |
6639 | */ | |
6640 | vcpu->arch.xcr0 = XSTATE_FP; | |
6641 | ||
6642 | vcpu->arch.cr0 |= X86_CR0_ET; | |
6643 | ||
6644 | return 0; | |
6645 | } | |
6646 | EXPORT_SYMBOL_GPL(fx_init); | |
6647 | ||
6648 | static void fx_free(struct kvm_vcpu *vcpu) | |
6649 | { | |
6650 | fpu_free(&vcpu->arch.guest_fpu); | |
6651 | } | |
6652 | ||
6653 | void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) | |
6654 | { | |
6655 | if (vcpu->guest_fpu_loaded) | |
6656 | return; | |
6657 | ||
6658 | /* | |
6659 | * Restore all possible states in the guest, | |
6660 | * and assume host would use all available bits. | |
6661 | * Guest xcr0 would be loaded later. | |
6662 | */ | |
6663 | kvm_put_guest_xcr0(vcpu); | |
6664 | vcpu->guest_fpu_loaded = 1; | |
6665 | __kernel_fpu_begin(); | |
6666 | fpu_restore_checking(&vcpu->arch.guest_fpu); | |
6667 | trace_kvm_fpu(1); | |
6668 | } | |
6669 | ||
6670 | void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
6671 | { | |
6672 | kvm_put_guest_xcr0(vcpu); | |
6673 | ||
6674 | if (!vcpu->guest_fpu_loaded) | |
6675 | return; | |
6676 | ||
6677 | vcpu->guest_fpu_loaded = 0; | |
6678 | fpu_save_init(&vcpu->arch.guest_fpu); | |
6679 | __kernel_fpu_end(); | |
6680 | ++vcpu->stat.fpu_reload; | |
6681 | kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); | |
6682 | trace_kvm_fpu(0); | |
6683 | } | |
6684 | ||
6685 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) | |
6686 | { | |
6687 | kvmclock_reset(vcpu); | |
6688 | ||
6689 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); | |
6690 | fx_free(vcpu); | |
6691 | kvm_x86_ops->vcpu_free(vcpu); | |
6692 | } | |
6693 | ||
6694 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, | |
6695 | unsigned int id) | |
6696 | { | |
6697 | if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) | |
6698 | printk_once(KERN_WARNING | |
6699 | "kvm: SMP vm created on host with unstable TSC; " | |
6700 | "guest TSC will not be reliable\n"); | |
6701 | return kvm_x86_ops->vcpu_create(kvm, id); | |
6702 | } | |
6703 | ||
6704 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) | |
6705 | { | |
6706 | int r; | |
6707 | ||
6708 | vcpu->arch.mtrr_state.have_fixed = 1; | |
6709 | r = vcpu_load(vcpu); | |
6710 | if (r) | |
6711 | return r; | |
6712 | kvm_vcpu_reset(vcpu); | |
6713 | kvm_mmu_setup(vcpu); | |
6714 | vcpu_put(vcpu); | |
6715 | ||
6716 | return r; | |
6717 | } | |
6718 | ||
6719 | int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) | |
6720 | { | |
6721 | int r; | |
6722 | struct msr_data msr; | |
6723 | ||
6724 | r = vcpu_load(vcpu); | |
6725 | if (r) | |
6726 | return r; | |
6727 | msr.data = 0x0; | |
6728 | msr.index = MSR_IA32_TSC; | |
6729 | msr.host_initiated = true; | |
6730 | kvm_write_tsc(vcpu, &msr); | |
6731 | vcpu_put(vcpu); | |
6732 | ||
6733 | return r; | |
6734 | } | |
6735 | ||
6736 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) | |
6737 | { | |
6738 | int r; | |
6739 | vcpu->arch.apf.msr_val = 0; | |
6740 | ||
6741 | r = vcpu_load(vcpu); | |
6742 | BUG_ON(r); | |
6743 | kvm_mmu_unload(vcpu); | |
6744 | vcpu_put(vcpu); | |
6745 | ||
6746 | fx_free(vcpu); | |
6747 | kvm_x86_ops->vcpu_free(vcpu); | |
6748 | } | |
6749 | ||
6750 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu) | |
6751 | { | |
6752 | atomic_set(&vcpu->arch.nmi_queued, 0); | |
6753 | vcpu->arch.nmi_pending = 0; | |
6754 | vcpu->arch.nmi_injected = false; | |
6755 | ||
6756 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); | |
6757 | vcpu->arch.dr6 = DR6_FIXED_1; | |
6758 | vcpu->arch.dr7 = DR7_FIXED_1; | |
6759 | kvm_update_dr7(vcpu); | |
6760 | ||
6761 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
6762 | vcpu->arch.apf.msr_val = 0; | |
6763 | vcpu->arch.st.msr_val = 0; | |
6764 | ||
6765 | kvmclock_reset(vcpu); | |
6766 | ||
6767 | kvm_clear_async_pf_completion_queue(vcpu); | |
6768 | kvm_async_pf_hash_reset(vcpu); | |
6769 | vcpu->arch.apf.halted = false; | |
6770 | ||
6771 | kvm_pmu_reset(vcpu); | |
6772 | ||
6773 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); | |
6774 | vcpu->arch.regs_avail = ~0; | |
6775 | vcpu->arch.regs_dirty = ~0; | |
6776 | ||
6777 | kvm_x86_ops->vcpu_reset(vcpu); | |
6778 | } | |
6779 | ||
6780 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector) | |
6781 | { | |
6782 | struct kvm_segment cs; | |
6783 | ||
6784 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
6785 | cs.selector = vector << 8; | |
6786 | cs.base = vector << 12; | |
6787 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
6788 | kvm_rip_write(vcpu, 0); | |
6789 | } | |
6790 | ||
6791 | int kvm_arch_hardware_enable(void *garbage) | |
6792 | { | |
6793 | struct kvm *kvm; | |
6794 | struct kvm_vcpu *vcpu; | |
6795 | int i; | |
6796 | int ret; | |
6797 | u64 local_tsc; | |
6798 | u64 max_tsc = 0; | |
6799 | bool stable, backwards_tsc = false; | |
6800 | ||
6801 | kvm_shared_msr_cpu_online(); | |
6802 | ret = kvm_x86_ops->hardware_enable(garbage); | |
6803 | if (ret != 0) | |
6804 | return ret; | |
6805 | ||
6806 | local_tsc = native_read_tsc(); | |
6807 | stable = !check_tsc_unstable(); | |
6808 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
6809 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
6810 | if (!stable && vcpu->cpu == smp_processor_id()) | |
6811 | set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests); | |
6812 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { | |
6813 | backwards_tsc = true; | |
6814 | if (vcpu->arch.last_host_tsc > max_tsc) | |
6815 | max_tsc = vcpu->arch.last_host_tsc; | |
6816 | } | |
6817 | } | |
6818 | } | |
6819 | ||
6820 | /* | |
6821 | * Sometimes, even reliable TSCs go backwards. This happens on | |
6822 | * platforms that reset TSC during suspend or hibernate actions, but | |
6823 | * maintain synchronization. We must compensate. Fortunately, we can | |
6824 | * detect that condition here, which happens early in CPU bringup, | |
6825 | * before any KVM threads can be running. Unfortunately, we can't | |
6826 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
6827 | * enough into CPU bringup that we know how much real time has actually | |
6828 | * elapsed; our helper function, get_kernel_ns() will be using boot | |
6829 | * variables that haven't been updated yet. | |
6830 | * | |
6831 | * So we simply find the maximum observed TSC above, then record the | |
6832 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
6833 | * the adjustment will be applied. Note that we accumulate | |
6834 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
6835 | * gets a chance to run again. In the event that no KVM threads get a | |
6836 | * chance to run, we will miss the entire elapsed period, as we'll have | |
6837 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
6838 | * loose cycle time. This isn't too big a deal, since the loss will be | |
6839 | * uniform across all VCPUs (not to mention the scenario is extremely | |
6840 | * unlikely). It is possible that a second hibernate recovery happens | |
6841 | * much faster than a first, causing the observed TSC here to be | |
6842 | * smaller; this would require additional padding adjustment, which is | |
6843 | * why we set last_host_tsc to the local tsc observed here. | |
6844 | * | |
6845 | * N.B. - this code below runs only on platforms with reliable TSC, | |
6846 | * as that is the only way backwards_tsc is set above. Also note | |
6847 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
6848 | * have the same delta_cyc adjustment applied if backwards_tsc | |
6849 | * is detected. Note further, this adjustment is only done once, | |
6850 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
6851 | * called multiple times (one for each physical CPU bringup). | |
6852 | * | |
6853 | * Platforms with unreliable TSCs don't have to deal with this, they | |
6854 | * will be compensated by the logic in vcpu_load, which sets the TSC to | |
6855 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
6856 | * guarantee that they stay in perfect synchronization. | |
6857 | */ | |
6858 | if (backwards_tsc) { | |
6859 | u64 delta_cyc = max_tsc - local_tsc; | |
6860 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
6861 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
6862 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
6863 | vcpu->arch.last_host_tsc = local_tsc; | |
6864 | set_bit(KVM_REQ_MASTERCLOCK_UPDATE, | |
6865 | &vcpu->requests); | |
6866 | } | |
6867 | ||
6868 | /* | |
6869 | * We have to disable TSC offset matching.. if you were | |
6870 | * booting a VM while issuing an S4 host suspend.... | |
6871 | * you may have some problem. Solving this issue is | |
6872 | * left as an exercise to the reader. | |
6873 | */ | |
6874 | kvm->arch.last_tsc_nsec = 0; | |
6875 | kvm->arch.last_tsc_write = 0; | |
6876 | } | |
6877 | ||
6878 | } | |
6879 | return 0; | |
6880 | } | |
6881 | ||
6882 | void kvm_arch_hardware_disable(void *garbage) | |
6883 | { | |
6884 | kvm_x86_ops->hardware_disable(garbage); | |
6885 | drop_user_return_notifiers(garbage); | |
6886 | } | |
6887 | ||
6888 | int kvm_arch_hardware_setup(void) | |
6889 | { | |
6890 | return kvm_x86_ops->hardware_setup(); | |
6891 | } | |
6892 | ||
6893 | void kvm_arch_hardware_unsetup(void) | |
6894 | { | |
6895 | kvm_x86_ops->hardware_unsetup(); | |
6896 | } | |
6897 | ||
6898 | void kvm_arch_check_processor_compat(void *rtn) | |
6899 | { | |
6900 | kvm_x86_ops->check_processor_compatibility(rtn); | |
6901 | } | |
6902 | ||
6903 | bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu) | |
6904 | { | |
6905 | return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL); | |
6906 | } | |
6907 | ||
6908 | struct static_key kvm_no_apic_vcpu __read_mostly; | |
6909 | ||
6910 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) | |
6911 | { | |
6912 | struct page *page; | |
6913 | struct kvm *kvm; | |
6914 | int r; | |
6915 | ||
6916 | BUG_ON(vcpu->kvm == NULL); | |
6917 | kvm = vcpu->kvm; | |
6918 | ||
6919 | vcpu->arch.pv.pv_unhalted = false; | |
6920 | vcpu->arch.emulate_ctxt.ops = &emulate_ops; | |
6921 | if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu)) | |
6922 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
6923 | else | |
6924 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; | |
6925 | ||
6926 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
6927 | if (!page) { | |
6928 | r = -ENOMEM; | |
6929 | goto fail; | |
6930 | } | |
6931 | vcpu->arch.pio_data = page_address(page); | |
6932 | ||
6933 | kvm_set_tsc_khz(vcpu, max_tsc_khz); | |
6934 | ||
6935 | r = kvm_mmu_create(vcpu); | |
6936 | if (r < 0) | |
6937 | goto fail_free_pio_data; | |
6938 | ||
6939 | if (irqchip_in_kernel(kvm)) { | |
6940 | r = kvm_create_lapic(vcpu); | |
6941 | if (r < 0) | |
6942 | goto fail_mmu_destroy; | |
6943 | } else | |
6944 | static_key_slow_inc(&kvm_no_apic_vcpu); | |
6945 | ||
6946 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, | |
6947 | GFP_KERNEL); | |
6948 | if (!vcpu->arch.mce_banks) { | |
6949 | r = -ENOMEM; | |
6950 | goto fail_free_lapic; | |
6951 | } | |
6952 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
6953 | ||
6954 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { | |
6955 | r = -ENOMEM; | |
6956 | goto fail_free_mce_banks; | |
6957 | } | |
6958 | ||
6959 | r = fx_init(vcpu); | |
6960 | if (r) | |
6961 | goto fail_free_wbinvd_dirty_mask; | |
6962 | ||
6963 | vcpu->arch.ia32_tsc_adjust_msr = 0x0; | |
6964 | vcpu->arch.pv_time_enabled = false; | |
6965 | ||
6966 | vcpu->arch.guest_supported_xcr0 = 0; | |
6967 | vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; | |
6968 | ||
6969 | kvm_async_pf_hash_reset(vcpu); | |
6970 | kvm_pmu_init(vcpu); | |
6971 | ||
6972 | return 0; | |
6973 | fail_free_wbinvd_dirty_mask: | |
6974 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); | |
6975 | fail_free_mce_banks: | |
6976 | kfree(vcpu->arch.mce_banks); | |
6977 | fail_free_lapic: | |
6978 | kvm_free_lapic(vcpu); | |
6979 | fail_mmu_destroy: | |
6980 | kvm_mmu_destroy(vcpu); | |
6981 | fail_free_pio_data: | |
6982 | free_page((unsigned long)vcpu->arch.pio_data); | |
6983 | fail: | |
6984 | return r; | |
6985 | } | |
6986 | ||
6987 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
6988 | { | |
6989 | int idx; | |
6990 | ||
6991 | kvm_pmu_destroy(vcpu); | |
6992 | kfree(vcpu->arch.mce_banks); | |
6993 | kvm_free_lapic(vcpu); | |
6994 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
6995 | kvm_mmu_destroy(vcpu); | |
6996 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
6997 | free_page((unsigned long)vcpu->arch.pio_data); | |
6998 | if (!irqchip_in_kernel(vcpu->kvm)) | |
6999 | static_key_slow_dec(&kvm_no_apic_vcpu); | |
7000 | } | |
7001 | ||
7002 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) | |
7003 | { | |
7004 | if (type) | |
7005 | return -EINVAL; | |
7006 | ||
7007 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); | |
7008 | INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); | |
7009 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); | |
7010 | atomic_set(&kvm->arch.noncoherent_dma_count, 0); | |
7011 | ||
7012 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ | |
7013 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7014 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ | |
7015 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
7016 | &kvm->arch.irq_sources_bitmap); | |
7017 | ||
7018 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); | |
7019 | mutex_init(&kvm->arch.apic_map_lock); | |
7020 | spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); | |
7021 | ||
7022 | pvclock_update_vm_gtod_copy(kvm); | |
7023 | ||
7024 | return 0; | |
7025 | } | |
7026 | ||
7027 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) | |
7028 | { | |
7029 | int r; | |
7030 | r = vcpu_load(vcpu); | |
7031 | BUG_ON(r); | |
7032 | kvm_mmu_unload(vcpu); | |
7033 | vcpu_put(vcpu); | |
7034 | } | |
7035 | ||
7036 | static void kvm_free_vcpus(struct kvm *kvm) | |
7037 | { | |
7038 | unsigned int i; | |
7039 | struct kvm_vcpu *vcpu; | |
7040 | ||
7041 | /* | |
7042 | * Unpin any mmu pages first. | |
7043 | */ | |
7044 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
7045 | kvm_clear_async_pf_completion_queue(vcpu); | |
7046 | kvm_unload_vcpu_mmu(vcpu); | |
7047 | } | |
7048 | kvm_for_each_vcpu(i, vcpu, kvm) | |
7049 | kvm_arch_vcpu_free(vcpu); | |
7050 | ||
7051 | mutex_lock(&kvm->lock); | |
7052 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
7053 | kvm->vcpus[i] = NULL; | |
7054 | ||
7055 | atomic_set(&kvm->online_vcpus, 0); | |
7056 | mutex_unlock(&kvm->lock); | |
7057 | } | |
7058 | ||
7059 | void kvm_arch_sync_events(struct kvm *kvm) | |
7060 | { | |
7061 | kvm_free_all_assigned_devices(kvm); | |
7062 | kvm_free_pit(kvm); | |
7063 | } | |
7064 | ||
7065 | void kvm_arch_destroy_vm(struct kvm *kvm) | |
7066 | { | |
7067 | if (current->mm == kvm->mm) { | |
7068 | /* | |
7069 | * Free memory regions allocated on behalf of userspace, | |
7070 | * unless the the memory map has changed due to process exit | |
7071 | * or fd copying. | |
7072 | */ | |
7073 | struct kvm_userspace_memory_region mem; | |
7074 | memset(&mem, 0, sizeof(mem)); | |
7075 | mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; | |
7076 | kvm_set_memory_region(kvm, &mem); | |
7077 | ||
7078 | mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT; | |
7079 | kvm_set_memory_region(kvm, &mem); | |
7080 | ||
7081 | mem.slot = TSS_PRIVATE_MEMSLOT; | |
7082 | kvm_set_memory_region(kvm, &mem); | |
7083 | } | |
7084 | kvm_iommu_unmap_guest(kvm); | |
7085 | kfree(kvm->arch.vpic); | |
7086 | kfree(kvm->arch.vioapic); | |
7087 | kvm_free_vcpus(kvm); | |
7088 | if (kvm->arch.apic_access_page) | |
7089 | put_page(kvm->arch.apic_access_page); | |
7090 | if (kvm->arch.ept_identity_pagetable) | |
7091 | put_page(kvm->arch.ept_identity_pagetable); | |
7092 | kfree(rcu_dereference_check(kvm->arch.apic_map, 1)); | |
7093 | } | |
7094 | ||
7095 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, | |
7096 | struct kvm_memory_slot *dont) | |
7097 | { | |
7098 | int i; | |
7099 | ||
7100 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { | |
7101 | if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { | |
7102 | kvm_kvfree(free->arch.rmap[i]); | |
7103 | free->arch.rmap[i] = NULL; | |
7104 | } | |
7105 | if (i == 0) | |
7106 | continue; | |
7107 | ||
7108 | if (!dont || free->arch.lpage_info[i - 1] != | |
7109 | dont->arch.lpage_info[i - 1]) { | |
7110 | kvm_kvfree(free->arch.lpage_info[i - 1]); | |
7111 | free->arch.lpage_info[i - 1] = NULL; | |
7112 | } | |
7113 | } | |
7114 | } | |
7115 | ||
7116 | int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, | |
7117 | unsigned long npages) | |
7118 | { | |
7119 | int i; | |
7120 | ||
7121 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { | |
7122 | unsigned long ugfn; | |
7123 | int lpages; | |
7124 | int level = i + 1; | |
7125 | ||
7126 | lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
7127 | slot->base_gfn, level) + 1; | |
7128 | ||
7129 | slot->arch.rmap[i] = | |
7130 | kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i])); | |
7131 | if (!slot->arch.rmap[i]) | |
7132 | goto out_free; | |
7133 | if (i == 0) | |
7134 | continue; | |
7135 | ||
7136 | slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages * | |
7137 | sizeof(*slot->arch.lpage_info[i - 1])); | |
7138 | if (!slot->arch.lpage_info[i - 1]) | |
7139 | goto out_free; | |
7140 | ||
7141 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) | |
7142 | slot->arch.lpage_info[i - 1][0].write_count = 1; | |
7143 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) | |
7144 | slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1; | |
7145 | ugfn = slot->userspace_addr >> PAGE_SHIFT; | |
7146 | /* | |
7147 | * If the gfn and userspace address are not aligned wrt each | |
7148 | * other, or if explicitly asked to, disable large page | |
7149 | * support for this slot | |
7150 | */ | |
7151 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || | |
7152 | !kvm_largepages_enabled()) { | |
7153 | unsigned long j; | |
7154 | ||
7155 | for (j = 0; j < lpages; ++j) | |
7156 | slot->arch.lpage_info[i - 1][j].write_count = 1; | |
7157 | } | |
7158 | } | |
7159 | ||
7160 | return 0; | |
7161 | ||
7162 | out_free: | |
7163 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { | |
7164 | kvm_kvfree(slot->arch.rmap[i]); | |
7165 | slot->arch.rmap[i] = NULL; | |
7166 | if (i == 0) | |
7167 | continue; | |
7168 | ||
7169 | kvm_kvfree(slot->arch.lpage_info[i - 1]); | |
7170 | slot->arch.lpage_info[i - 1] = NULL; | |
7171 | } | |
7172 | return -ENOMEM; | |
7173 | } | |
7174 | ||
7175 | void kvm_arch_memslots_updated(struct kvm *kvm) | |
7176 | { | |
7177 | /* | |
7178 | * memslots->generation has been incremented. | |
7179 | * mmio generation may have reached its maximum value. | |
7180 | */ | |
7181 | kvm_mmu_invalidate_mmio_sptes(kvm); | |
7182 | } | |
7183 | ||
7184 | int kvm_arch_prepare_memory_region(struct kvm *kvm, | |
7185 | struct kvm_memory_slot *memslot, | |
7186 | struct kvm_userspace_memory_region *mem, | |
7187 | enum kvm_mr_change change) | |
7188 | { | |
7189 | /* | |
7190 | * Only private memory slots need to be mapped here since | |
7191 | * KVM_SET_MEMORY_REGION ioctl is no longer supported. | |
7192 | */ | |
7193 | if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) { | |
7194 | unsigned long userspace_addr; | |
7195 | ||
7196 | /* | |
7197 | * MAP_SHARED to prevent internal slot pages from being moved | |
7198 | * by fork()/COW. | |
7199 | */ | |
7200 | userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE, | |
7201 | PROT_READ | PROT_WRITE, | |
7202 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
7203 | ||
7204 | if (IS_ERR((void *)userspace_addr)) | |
7205 | return PTR_ERR((void *)userspace_addr); | |
7206 | ||
7207 | memslot->userspace_addr = userspace_addr; | |
7208 | } | |
7209 | ||
7210 | return 0; | |
7211 | } | |
7212 | ||
7213 | void kvm_arch_commit_memory_region(struct kvm *kvm, | |
7214 | struct kvm_userspace_memory_region *mem, | |
7215 | const struct kvm_memory_slot *old, | |
7216 | enum kvm_mr_change change) | |
7217 | { | |
7218 | ||
7219 | int nr_mmu_pages = 0; | |
7220 | ||
7221 | if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) { | |
7222 | int ret; | |
7223 | ||
7224 | ret = vm_munmap(old->userspace_addr, | |
7225 | old->npages * PAGE_SIZE); | |
7226 | if (ret < 0) | |
7227 | printk(KERN_WARNING | |
7228 | "kvm_vm_ioctl_set_memory_region: " | |
7229 | "failed to munmap memory\n"); | |
7230 | } | |
7231 | ||
7232 | if (!kvm->arch.n_requested_mmu_pages) | |
7233 | nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); | |
7234 | ||
7235 | if (nr_mmu_pages) | |
7236 | kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); | |
7237 | /* | |
7238 | * Write protect all pages for dirty logging. | |
7239 | * Existing largepage mappings are destroyed here and new ones will | |
7240 | * not be created until the end of the logging. | |
7241 | */ | |
7242 | if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES)) | |
7243 | kvm_mmu_slot_remove_write_access(kvm, mem->slot); | |
7244 | } | |
7245 | ||
7246 | void kvm_arch_flush_shadow_all(struct kvm *kvm) | |
7247 | { | |
7248 | kvm_mmu_invalidate_zap_all_pages(kvm); | |
7249 | } | |
7250 | ||
7251 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, | |
7252 | struct kvm_memory_slot *slot) | |
7253 | { | |
7254 | kvm_mmu_invalidate_zap_all_pages(kvm); | |
7255 | } | |
7256 | ||
7257 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) | |
7258 | { | |
7259 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && | |
7260 | !vcpu->arch.apf.halted) | |
7261 | || !list_empty_careful(&vcpu->async_pf.done) | |
7262 | || kvm_apic_has_events(vcpu) | |
7263 | || vcpu->arch.pv.pv_unhalted | |
7264 | || atomic_read(&vcpu->arch.nmi_queued) || | |
7265 | (kvm_arch_interrupt_allowed(vcpu) && | |
7266 | kvm_cpu_has_interrupt(vcpu)); | |
7267 | } | |
7268 | ||
7269 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) | |
7270 | { | |
7271 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; | |
7272 | } | |
7273 | ||
7274 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
7275 | { | |
7276 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
7277 | } | |
7278 | ||
7279 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) | |
7280 | { | |
7281 | unsigned long current_rip = kvm_rip_read(vcpu) + | |
7282 | get_segment_base(vcpu, VCPU_SREG_CS); | |
7283 | ||
7284 | return current_rip == linear_rip; | |
7285 | } | |
7286 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
7287 | ||
7288 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) | |
7289 | { | |
7290 | unsigned long rflags; | |
7291 | ||
7292 | rflags = kvm_x86_ops->get_rflags(vcpu); | |
7293 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
7294 | rflags &= ~X86_EFLAGS_TF; | |
7295 | return rflags; | |
7296 | } | |
7297 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
7298 | ||
7299 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
7300 | { | |
7301 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
7302 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) | |
7303 | rflags |= X86_EFLAGS_TF; | |
7304 | kvm_x86_ops->set_rflags(vcpu, rflags); | |
7305 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7306 | } | |
7307 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
7308 | ||
7309 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) | |
7310 | { | |
7311 | int r; | |
7312 | ||
7313 | if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || | |
7314 | work->wakeup_all) | |
7315 | return; | |
7316 | ||
7317 | r = kvm_mmu_reload(vcpu); | |
7318 | if (unlikely(r)) | |
7319 | return; | |
7320 | ||
7321 | if (!vcpu->arch.mmu.direct_map && | |
7322 | work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) | |
7323 | return; | |
7324 | ||
7325 | vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); | |
7326 | } | |
7327 | ||
7328 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) | |
7329 | { | |
7330 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); | |
7331 | } | |
7332 | ||
7333 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
7334 | { | |
7335 | return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); | |
7336 | } | |
7337 | ||
7338 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
7339 | { | |
7340 | u32 key = kvm_async_pf_hash_fn(gfn); | |
7341 | ||
7342 | while (vcpu->arch.apf.gfns[key] != ~0) | |
7343 | key = kvm_async_pf_next_probe(key); | |
7344 | ||
7345 | vcpu->arch.apf.gfns[key] = gfn; | |
7346 | } | |
7347 | ||
7348 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
7349 | { | |
7350 | int i; | |
7351 | u32 key = kvm_async_pf_hash_fn(gfn); | |
7352 | ||
7353 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && | |
7354 | (vcpu->arch.apf.gfns[key] != gfn && | |
7355 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
7356 | key = kvm_async_pf_next_probe(key); | |
7357 | ||
7358 | return key; | |
7359 | } | |
7360 | ||
7361 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
7362 | { | |
7363 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
7364 | } | |
7365 | ||
7366 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
7367 | { | |
7368 | u32 i, j, k; | |
7369 | ||
7370 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
7371 | while (true) { | |
7372 | vcpu->arch.apf.gfns[i] = ~0; | |
7373 | do { | |
7374 | j = kvm_async_pf_next_probe(j); | |
7375 | if (vcpu->arch.apf.gfns[j] == ~0) | |
7376 | return; | |
7377 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
7378 | /* | |
7379 | * k lies cyclically in ]i,j] | |
7380 | * | i.k.j | | |
7381 | * |....j i.k.| or |.k..j i...| | |
7382 | */ | |
7383 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
7384 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
7385 | i = j; | |
7386 | } | |
7387 | } | |
7388 | ||
7389 | static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) | |
7390 | { | |
7391 | ||
7392 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, | |
7393 | sizeof(val)); | |
7394 | } | |
7395 | ||
7396 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, | |
7397 | struct kvm_async_pf *work) | |
7398 | { | |
7399 | struct x86_exception fault; | |
7400 | ||
7401 | trace_kvm_async_pf_not_present(work->arch.token, work->gva); | |
7402 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); | |
7403 | ||
7404 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || | |
7405 | (vcpu->arch.apf.send_user_only && | |
7406 | kvm_x86_ops->get_cpl(vcpu) == 0)) | |
7407 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
7408 | else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { | |
7409 | fault.vector = PF_VECTOR; | |
7410 | fault.error_code_valid = true; | |
7411 | fault.error_code = 0; | |
7412 | fault.nested_page_fault = false; | |
7413 | fault.address = work->arch.token; | |
7414 | kvm_inject_page_fault(vcpu, &fault); | |
7415 | } | |
7416 | } | |
7417 | ||
7418 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
7419 | struct kvm_async_pf *work) | |
7420 | { | |
7421 | struct x86_exception fault; | |
7422 | ||
7423 | trace_kvm_async_pf_ready(work->arch.token, work->gva); | |
7424 | if (work->wakeup_all) | |
7425 | work->arch.token = ~0; /* broadcast wakeup */ | |
7426 | else | |
7427 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
7428 | ||
7429 | if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && | |
7430 | !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { | |
7431 | fault.vector = PF_VECTOR; | |
7432 | fault.error_code_valid = true; | |
7433 | fault.error_code = 0; | |
7434 | fault.nested_page_fault = false; | |
7435 | fault.address = work->arch.token; | |
7436 | kvm_inject_page_fault(vcpu, &fault); | |
7437 | } | |
7438 | vcpu->arch.apf.halted = false; | |
7439 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
7440 | } | |
7441 | ||
7442 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) | |
7443 | { | |
7444 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) | |
7445 | return true; | |
7446 | else | |
7447 | return !kvm_event_needs_reinjection(vcpu) && | |
7448 | kvm_x86_ops->interrupt_allowed(vcpu); | |
7449 | } | |
7450 | ||
7451 | void kvm_arch_register_noncoherent_dma(struct kvm *kvm) | |
7452 | { | |
7453 | atomic_inc(&kvm->arch.noncoherent_dma_count); | |
7454 | } | |
7455 | EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); | |
7456 | ||
7457 | void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) | |
7458 | { | |
7459 | atomic_dec(&kvm->arch.noncoherent_dma_count); | |
7460 | } | |
7461 | EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); | |
7462 | ||
7463 | bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) | |
7464 | { | |
7465 | return atomic_read(&kvm->arch.noncoherent_dma_count); | |
7466 | } | |
7467 | EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); | |
7468 | ||
7469 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); | |
7470 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); | |
7471 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
7472 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
7473 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
7474 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); | |
7475 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); | |
7476 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); | |
7477 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); | |
7478 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); | |
7479 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); | |
7480 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); | |
7481 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); |