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KVM: x86: Refactor up kvm_{g,s}et_msr() to simplify callers
[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kvm / x86.c
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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * derived from drivers/kvm/kvm_main.c
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 *
12 * Authors:
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
17 */
18
19#include <linux/kvm_host.h>
20#include "irq.h"
21#include "mmu.h"
22#include "i8254.h"
23#include "tss.h"
24#include "kvm_cache_regs.h"
25#include "x86.h"
26#include "cpuid.h"
27#include "pmu.h"
28#include "hyperv.h"
29
30#include <linux/clocksource.h>
31#include <linux/interrupt.h>
32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
35#include <linux/export.h>
36#include <linux/moduleparam.h>
37#include <linux/mman.h>
38#include <linux/highmem.h>
39#include <linux/iommu.h>
40#include <linux/intel-iommu.h>
41#include <linux/cpufreq.h>
42#include <linux/user-return-notifier.h>
43#include <linux/srcu.h>
44#include <linux/slab.h>
45#include <linux/perf_event.h>
46#include <linux/uaccess.h>
47#include <linux/hash.h>
48#include <linux/pci.h>
49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
51#include <linux/kvm_irqfd.h>
52#include <linux/irqbypass.h>
53#include <linux/sched/stat.h>
54#include <linux/sched/isolation.h>
55#include <linux/mem_encrypt.h>
56
57#include <trace/events/kvm.h>
58
59#include <asm/debugreg.h>
60#include <asm/msr.h>
61#include <asm/desc.h>
62#include <asm/mce.h>
63#include <linux/kernel_stat.h>
64#include <asm/fpu/internal.h> /* Ugh! */
65#include <asm/pvclock.h>
66#include <asm/div64.h>
67#include <asm/irq_remapping.h>
68#include <asm/mshyperv.h>
69#include <asm/hypervisor.h>
70#include <asm/intel_pt.h>
71#include <clocksource/hyperv_timer.h>
72
73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
76#define MAX_IO_MSRS 256
77#define KVM_MAX_MCE_BANKS 32
78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
80
81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
91#else
92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
93#endif
94
95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
97
98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
100
101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
102static void process_nmi(struct kvm_vcpu *vcpu);
103static void enter_smm(struct kvm_vcpu *vcpu);
104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
107
108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
109EXPORT_SYMBOL_GPL(kvm_x86_ops);
110
111static bool __read_mostly ignore_msrs = 0;
112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
113
114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
117unsigned int min_timer_period_us = 200;
118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
123bool __read_mostly kvm_has_tsc_control;
124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
125u32 __read_mostly kvm_max_guest_tsc_khz;
126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
133
134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
135static u32 __read_mostly tsc_tolerance_ppm = 250;
136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
138/*
139 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
140 * adaptive tuning starting from default advancment of 1000ns. '0' disables
141 * advancement entirely. Any other value is used as-is and disables adaptive
142 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
143 */
144static int __read_mostly lapic_timer_advance_ns = -1;
145module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
146
147static bool __read_mostly vector_hashing = true;
148module_param(vector_hashing, bool, S_IRUGO);
149
150bool __read_mostly enable_vmware_backdoor = false;
151module_param(enable_vmware_backdoor, bool, S_IRUGO);
152EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
153
154static bool __read_mostly force_emulation_prefix = false;
155module_param(force_emulation_prefix, bool, S_IRUGO);
156
157int __read_mostly pi_inject_timer = -1;
158module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
159
160#define KVM_NR_SHARED_MSRS 16
161
162struct kvm_shared_msrs_global {
163 int nr;
164 u32 msrs[KVM_NR_SHARED_MSRS];
165};
166
167struct kvm_shared_msrs {
168 struct user_return_notifier urn;
169 bool registered;
170 struct kvm_shared_msr_values {
171 u64 host;
172 u64 curr;
173 } values[KVM_NR_SHARED_MSRS];
174};
175
176static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
177static struct kvm_shared_msrs __percpu *shared_msrs;
178
179struct kvm_stats_debugfs_item debugfs_entries[] = {
180 { "pf_fixed", VCPU_STAT(pf_fixed) },
181 { "pf_guest", VCPU_STAT(pf_guest) },
182 { "tlb_flush", VCPU_STAT(tlb_flush) },
183 { "invlpg", VCPU_STAT(invlpg) },
184 { "exits", VCPU_STAT(exits) },
185 { "io_exits", VCPU_STAT(io_exits) },
186 { "mmio_exits", VCPU_STAT(mmio_exits) },
187 { "signal_exits", VCPU_STAT(signal_exits) },
188 { "irq_window", VCPU_STAT(irq_window_exits) },
189 { "nmi_window", VCPU_STAT(nmi_window_exits) },
190 { "halt_exits", VCPU_STAT(halt_exits) },
191 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
192 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
193 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
194 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
195 { "hypercalls", VCPU_STAT(hypercalls) },
196 { "request_irq", VCPU_STAT(request_irq_exits) },
197 { "irq_exits", VCPU_STAT(irq_exits) },
198 { "host_state_reload", VCPU_STAT(host_state_reload) },
199 { "fpu_reload", VCPU_STAT(fpu_reload) },
200 { "insn_emulation", VCPU_STAT(insn_emulation) },
201 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
202 { "irq_injections", VCPU_STAT(irq_injections) },
203 { "nmi_injections", VCPU_STAT(nmi_injections) },
204 { "req_event", VCPU_STAT(req_event) },
205 { "l1d_flush", VCPU_STAT(l1d_flush) },
206 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
207 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
208 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
209 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
210 { "mmu_flooded", VM_STAT(mmu_flooded) },
211 { "mmu_recycled", VM_STAT(mmu_recycled) },
212 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
213 { "mmu_unsync", VM_STAT(mmu_unsync) },
214 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
215 { "largepages", VM_STAT(lpages) },
216 { "max_mmu_page_hash_collisions",
217 VM_STAT(max_mmu_page_hash_collisions) },
218 { NULL }
219};
220
221u64 __read_mostly host_xcr0;
222
223struct kmem_cache *x86_fpu_cache;
224EXPORT_SYMBOL_GPL(x86_fpu_cache);
225
226static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
227
228static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
229{
230 int i;
231 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
232 vcpu->arch.apf.gfns[i] = ~0;
233}
234
235static void kvm_on_user_return(struct user_return_notifier *urn)
236{
237 unsigned slot;
238 struct kvm_shared_msrs *locals
239 = container_of(urn, struct kvm_shared_msrs, urn);
240 struct kvm_shared_msr_values *values;
241 unsigned long flags;
242
243 /*
244 * Disabling irqs at this point since the following code could be
245 * interrupted and executed through kvm_arch_hardware_disable()
246 */
247 local_irq_save(flags);
248 if (locals->registered) {
249 locals->registered = false;
250 user_return_notifier_unregister(urn);
251 }
252 local_irq_restore(flags);
253 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
254 values = &locals->values[slot];
255 if (values->host != values->curr) {
256 wrmsrl(shared_msrs_global.msrs[slot], values->host);
257 values->curr = values->host;
258 }
259 }
260}
261
262static void shared_msr_update(unsigned slot, u32 msr)
263{
264 u64 value;
265 unsigned int cpu = smp_processor_id();
266 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
267
268 /* only read, and nobody should modify it at this time,
269 * so don't need lock */
270 if (slot >= shared_msrs_global.nr) {
271 printk(KERN_ERR "kvm: invalid MSR slot!");
272 return;
273 }
274 rdmsrl_safe(msr, &value);
275 smsr->values[slot].host = value;
276 smsr->values[slot].curr = value;
277}
278
279void kvm_define_shared_msr(unsigned slot, u32 msr)
280{
281 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
282 shared_msrs_global.msrs[slot] = msr;
283 if (slot >= shared_msrs_global.nr)
284 shared_msrs_global.nr = slot + 1;
285}
286EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
287
288static void kvm_shared_msr_cpu_online(void)
289{
290 unsigned i;
291
292 for (i = 0; i < shared_msrs_global.nr; ++i)
293 shared_msr_update(i, shared_msrs_global.msrs[i]);
294}
295
296int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
297{
298 unsigned int cpu = smp_processor_id();
299 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
300 int err;
301
302 if (((value ^ smsr->values[slot].curr) & mask) == 0)
303 return 0;
304 smsr->values[slot].curr = value;
305 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
306 if (err)
307 return 1;
308
309 if (!smsr->registered) {
310 smsr->urn.on_user_return = kvm_on_user_return;
311 user_return_notifier_register(&smsr->urn);
312 smsr->registered = true;
313 }
314 return 0;
315}
316EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
317
318static void drop_user_return_notifiers(void)
319{
320 unsigned int cpu = smp_processor_id();
321 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
322
323 if (smsr->registered)
324 kvm_on_user_return(&smsr->urn);
325}
326
327u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
328{
329 return vcpu->arch.apic_base;
330}
331EXPORT_SYMBOL_GPL(kvm_get_apic_base);
332
333enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
334{
335 return kvm_apic_mode(kvm_get_apic_base(vcpu));
336}
337EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
338
339int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
340{
341 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
342 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
343 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
344 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
345
346 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
347 return 1;
348 if (!msr_info->host_initiated) {
349 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
350 return 1;
351 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
352 return 1;
353 }
354
355 kvm_lapic_set_base(vcpu, msr_info->data);
356 return 0;
357}
358EXPORT_SYMBOL_GPL(kvm_set_apic_base);
359
360asmlinkage __visible void kvm_spurious_fault(void)
361{
362 /* Fault while not rebooting. We want the trace. */
363 BUG();
364}
365EXPORT_SYMBOL_GPL(kvm_spurious_fault);
366
367#define EXCPT_BENIGN 0
368#define EXCPT_CONTRIBUTORY 1
369#define EXCPT_PF 2
370
371static int exception_class(int vector)
372{
373 switch (vector) {
374 case PF_VECTOR:
375 return EXCPT_PF;
376 case DE_VECTOR:
377 case TS_VECTOR:
378 case NP_VECTOR:
379 case SS_VECTOR:
380 case GP_VECTOR:
381 return EXCPT_CONTRIBUTORY;
382 default:
383 break;
384 }
385 return EXCPT_BENIGN;
386}
387
388#define EXCPT_FAULT 0
389#define EXCPT_TRAP 1
390#define EXCPT_ABORT 2
391#define EXCPT_INTERRUPT 3
392
393static int exception_type(int vector)
394{
395 unsigned int mask;
396
397 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
398 return EXCPT_INTERRUPT;
399
400 mask = 1 << vector;
401
402 /* #DB is trap, as instruction watchpoints are handled elsewhere */
403 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
404 return EXCPT_TRAP;
405
406 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
407 return EXCPT_ABORT;
408
409 /* Reserved exceptions will result in fault */
410 return EXCPT_FAULT;
411}
412
413void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
414{
415 unsigned nr = vcpu->arch.exception.nr;
416 bool has_payload = vcpu->arch.exception.has_payload;
417 unsigned long payload = vcpu->arch.exception.payload;
418
419 if (!has_payload)
420 return;
421
422 switch (nr) {
423 case DB_VECTOR:
424 /*
425 * "Certain debug exceptions may clear bit 0-3. The
426 * remaining contents of the DR6 register are never
427 * cleared by the processor".
428 */
429 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
430 /*
431 * DR6.RTM is set by all #DB exceptions that don't clear it.
432 */
433 vcpu->arch.dr6 |= DR6_RTM;
434 vcpu->arch.dr6 |= payload;
435 /*
436 * Bit 16 should be set in the payload whenever the #DB
437 * exception should clear DR6.RTM. This makes the payload
438 * compatible with the pending debug exceptions under VMX.
439 * Though not currently documented in the SDM, this also
440 * makes the payload compatible with the exit qualification
441 * for #DB exceptions under VMX.
442 */
443 vcpu->arch.dr6 ^= payload & DR6_RTM;
444 break;
445 case PF_VECTOR:
446 vcpu->arch.cr2 = payload;
447 break;
448 }
449
450 vcpu->arch.exception.has_payload = false;
451 vcpu->arch.exception.payload = 0;
452}
453EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
454
455static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
456 unsigned nr, bool has_error, u32 error_code,
457 bool has_payload, unsigned long payload, bool reinject)
458{
459 u32 prev_nr;
460 int class1, class2;
461
462 kvm_make_request(KVM_REQ_EVENT, vcpu);
463
464 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
465 queue:
466 if (has_error && !is_protmode(vcpu))
467 has_error = false;
468 if (reinject) {
469 /*
470 * On vmentry, vcpu->arch.exception.pending is only
471 * true if an event injection was blocked by
472 * nested_run_pending. In that case, however,
473 * vcpu_enter_guest requests an immediate exit,
474 * and the guest shouldn't proceed far enough to
475 * need reinjection.
476 */
477 WARN_ON_ONCE(vcpu->arch.exception.pending);
478 vcpu->arch.exception.injected = true;
479 if (WARN_ON_ONCE(has_payload)) {
480 /*
481 * A reinjected event has already
482 * delivered its payload.
483 */
484 has_payload = false;
485 payload = 0;
486 }
487 } else {
488 vcpu->arch.exception.pending = true;
489 vcpu->arch.exception.injected = false;
490 }
491 vcpu->arch.exception.has_error_code = has_error;
492 vcpu->arch.exception.nr = nr;
493 vcpu->arch.exception.error_code = error_code;
494 vcpu->arch.exception.has_payload = has_payload;
495 vcpu->arch.exception.payload = payload;
496 /*
497 * In guest mode, payload delivery should be deferred,
498 * so that the L1 hypervisor can intercept #PF before
499 * CR2 is modified (or intercept #DB before DR6 is
500 * modified under nVMX). However, for ABI
501 * compatibility with KVM_GET_VCPU_EVENTS and
502 * KVM_SET_VCPU_EVENTS, we can't delay payload
503 * delivery unless userspace has enabled this
504 * functionality via the per-VM capability,
505 * KVM_CAP_EXCEPTION_PAYLOAD.
506 */
507 if (!vcpu->kvm->arch.exception_payload_enabled ||
508 !is_guest_mode(vcpu))
509 kvm_deliver_exception_payload(vcpu);
510 return;
511 }
512
513 /* to check exception */
514 prev_nr = vcpu->arch.exception.nr;
515 if (prev_nr == DF_VECTOR) {
516 /* triple fault -> shutdown */
517 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
518 return;
519 }
520 class1 = exception_class(prev_nr);
521 class2 = exception_class(nr);
522 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
523 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
524 /*
525 * Generate double fault per SDM Table 5-5. Set
526 * exception.pending = true so that the double fault
527 * can trigger a nested vmexit.
528 */
529 vcpu->arch.exception.pending = true;
530 vcpu->arch.exception.injected = false;
531 vcpu->arch.exception.has_error_code = true;
532 vcpu->arch.exception.nr = DF_VECTOR;
533 vcpu->arch.exception.error_code = 0;
534 vcpu->arch.exception.has_payload = false;
535 vcpu->arch.exception.payload = 0;
536 } else
537 /* replace previous exception with a new one in a hope
538 that instruction re-execution will regenerate lost
539 exception */
540 goto queue;
541}
542
543void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
544{
545 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
546}
547EXPORT_SYMBOL_GPL(kvm_queue_exception);
548
549void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
550{
551 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
552}
553EXPORT_SYMBOL_GPL(kvm_requeue_exception);
554
555static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
556 unsigned long payload)
557{
558 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
559}
560
561static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
562 u32 error_code, unsigned long payload)
563{
564 kvm_multiple_exception(vcpu, nr, true, error_code,
565 true, payload, false);
566}
567
568int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
569{
570 if (err)
571 kvm_inject_gp(vcpu, 0);
572 else
573 return kvm_skip_emulated_instruction(vcpu);
574
575 return 1;
576}
577EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
578
579void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
580{
581 ++vcpu->stat.pf_guest;
582 vcpu->arch.exception.nested_apf =
583 is_guest_mode(vcpu) && fault->async_page_fault;
584 if (vcpu->arch.exception.nested_apf) {
585 vcpu->arch.apf.nested_apf_token = fault->address;
586 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
587 } else {
588 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
589 fault->address);
590 }
591}
592EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
593
594static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
595{
596 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
597 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
598 else
599 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
600
601 return fault->nested_page_fault;
602}
603
604void kvm_inject_nmi(struct kvm_vcpu *vcpu)
605{
606 atomic_inc(&vcpu->arch.nmi_queued);
607 kvm_make_request(KVM_REQ_NMI, vcpu);
608}
609EXPORT_SYMBOL_GPL(kvm_inject_nmi);
610
611void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
612{
613 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
614}
615EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
616
617void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
618{
619 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
620}
621EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
622
623/*
624 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
625 * a #GP and return false.
626 */
627bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
628{
629 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
630 return true;
631 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
632 return false;
633}
634EXPORT_SYMBOL_GPL(kvm_require_cpl);
635
636bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
637{
638 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
639 return true;
640
641 kvm_queue_exception(vcpu, UD_VECTOR);
642 return false;
643}
644EXPORT_SYMBOL_GPL(kvm_require_dr);
645
646/*
647 * This function will be used to read from the physical memory of the currently
648 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
649 * can read from guest physical or from the guest's guest physical memory.
650 */
651int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
652 gfn_t ngfn, void *data, int offset, int len,
653 u32 access)
654{
655 struct x86_exception exception;
656 gfn_t real_gfn;
657 gpa_t ngpa;
658
659 ngpa = gfn_to_gpa(ngfn);
660 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
661 if (real_gfn == UNMAPPED_GVA)
662 return -EFAULT;
663
664 real_gfn = gpa_to_gfn(real_gfn);
665
666 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
667}
668EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
669
670static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
671 void *data, int offset, int len, u32 access)
672{
673 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
674 data, offset, len, access);
675}
676
677static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
678{
679 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
680 rsvd_bits(1, 2);
681}
682
683/*
684 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
685 */
686int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
687{
688 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
689 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
690 int i;
691 int ret;
692 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
693
694 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
695 offset * sizeof(u64), sizeof(pdpte),
696 PFERR_USER_MASK|PFERR_WRITE_MASK);
697 if (ret < 0) {
698 ret = 0;
699 goto out;
700 }
701 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
702 if ((pdpte[i] & PT_PRESENT_MASK) &&
703 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
704 ret = 0;
705 goto out;
706 }
707 }
708 ret = 1;
709
710 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
711 __set_bit(VCPU_EXREG_PDPTR,
712 (unsigned long *)&vcpu->arch.regs_avail);
713 __set_bit(VCPU_EXREG_PDPTR,
714 (unsigned long *)&vcpu->arch.regs_dirty);
715out:
716
717 return ret;
718}
719EXPORT_SYMBOL_GPL(load_pdptrs);
720
721bool pdptrs_changed(struct kvm_vcpu *vcpu)
722{
723 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
724 bool changed = true;
725 int offset;
726 gfn_t gfn;
727 int r;
728
729 if (!is_pae_paging(vcpu))
730 return false;
731
732 if (!test_bit(VCPU_EXREG_PDPTR,
733 (unsigned long *)&vcpu->arch.regs_avail))
734 return true;
735
736 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
737 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
738 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
739 PFERR_USER_MASK | PFERR_WRITE_MASK);
740 if (r < 0)
741 goto out;
742 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
743out:
744
745 return changed;
746}
747EXPORT_SYMBOL_GPL(pdptrs_changed);
748
749int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
750{
751 unsigned long old_cr0 = kvm_read_cr0(vcpu);
752 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
753
754 cr0 |= X86_CR0_ET;
755
756#ifdef CONFIG_X86_64
757 if (cr0 & 0xffffffff00000000UL)
758 return 1;
759#endif
760
761 cr0 &= ~CR0_RESERVED_BITS;
762
763 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
764 return 1;
765
766 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
767 return 1;
768
769 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
770#ifdef CONFIG_X86_64
771 if ((vcpu->arch.efer & EFER_LME)) {
772 int cs_db, cs_l;
773
774 if (!is_pae(vcpu))
775 return 1;
776 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
777 if (cs_l)
778 return 1;
779 } else
780#endif
781 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
782 kvm_read_cr3(vcpu)))
783 return 1;
784 }
785
786 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
787 return 1;
788
789 kvm_x86_ops->set_cr0(vcpu, cr0);
790
791 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
792 kvm_clear_async_pf_completion_queue(vcpu);
793 kvm_async_pf_hash_reset(vcpu);
794 }
795
796 if ((cr0 ^ old_cr0) & update_bits)
797 kvm_mmu_reset_context(vcpu);
798
799 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
800 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
801 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
802 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
803
804 return 0;
805}
806EXPORT_SYMBOL_GPL(kvm_set_cr0);
807
808void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
809{
810 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
811}
812EXPORT_SYMBOL_GPL(kvm_lmsw);
813
814void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
815{
816 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
817 !vcpu->guest_xcr0_loaded) {
818 /* kvm_set_xcr() also depends on this */
819 if (vcpu->arch.xcr0 != host_xcr0)
820 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
821 vcpu->guest_xcr0_loaded = 1;
822 }
823}
824EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0);
825
826void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
827{
828 if (vcpu->guest_xcr0_loaded) {
829 if (vcpu->arch.xcr0 != host_xcr0)
830 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
831 vcpu->guest_xcr0_loaded = 0;
832 }
833}
834EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0);
835
836static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
837{
838 u64 xcr0 = xcr;
839 u64 old_xcr0 = vcpu->arch.xcr0;
840 u64 valid_bits;
841
842 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
843 if (index != XCR_XFEATURE_ENABLED_MASK)
844 return 1;
845 if (!(xcr0 & XFEATURE_MASK_FP))
846 return 1;
847 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
848 return 1;
849
850 /*
851 * Do not allow the guest to set bits that we do not support
852 * saving. However, xcr0 bit 0 is always set, even if the
853 * emulated CPU does not support XSAVE (see fx_init).
854 */
855 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
856 if (xcr0 & ~valid_bits)
857 return 1;
858
859 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
860 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
861 return 1;
862
863 if (xcr0 & XFEATURE_MASK_AVX512) {
864 if (!(xcr0 & XFEATURE_MASK_YMM))
865 return 1;
866 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
867 return 1;
868 }
869 vcpu->arch.xcr0 = xcr0;
870
871 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
872 kvm_update_cpuid(vcpu);
873 return 0;
874}
875
876int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
877{
878 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
879 __kvm_set_xcr(vcpu, index, xcr)) {
880 kvm_inject_gp(vcpu, 0);
881 return 1;
882 }
883 return 0;
884}
885EXPORT_SYMBOL_GPL(kvm_set_xcr);
886
887int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
888{
889 unsigned long old_cr4 = kvm_read_cr4(vcpu);
890 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
891 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
892
893 if (cr4 & CR4_RESERVED_BITS)
894 return 1;
895
896 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
897 return 1;
898
899 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
900 return 1;
901
902 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
903 return 1;
904
905 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
906 return 1;
907
908 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
909 return 1;
910
911 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
912 return 1;
913
914 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
915 return 1;
916
917 if (is_long_mode(vcpu)) {
918 if (!(cr4 & X86_CR4_PAE))
919 return 1;
920 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
921 && ((cr4 ^ old_cr4) & pdptr_bits)
922 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
923 kvm_read_cr3(vcpu)))
924 return 1;
925
926 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
927 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
928 return 1;
929
930 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
931 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
932 return 1;
933 }
934
935 if (kvm_x86_ops->set_cr4(vcpu, cr4))
936 return 1;
937
938 if (((cr4 ^ old_cr4) & pdptr_bits) ||
939 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
940 kvm_mmu_reset_context(vcpu);
941
942 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
943 kvm_update_cpuid(vcpu);
944
945 return 0;
946}
947EXPORT_SYMBOL_GPL(kvm_set_cr4);
948
949int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
950{
951 bool skip_tlb_flush = false;
952#ifdef CONFIG_X86_64
953 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
954
955 if (pcid_enabled) {
956 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
957 cr3 &= ~X86_CR3_PCID_NOFLUSH;
958 }
959#endif
960
961 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
962 if (!skip_tlb_flush) {
963 kvm_mmu_sync_roots(vcpu);
964 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
965 }
966 return 0;
967 }
968
969 if (is_long_mode(vcpu) &&
970 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
971 return 1;
972 else if (is_pae_paging(vcpu) &&
973 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
974 return 1;
975
976 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
977 vcpu->arch.cr3 = cr3;
978 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
979
980 return 0;
981}
982EXPORT_SYMBOL_GPL(kvm_set_cr3);
983
984int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
985{
986 if (cr8 & CR8_RESERVED_BITS)
987 return 1;
988 if (lapic_in_kernel(vcpu))
989 kvm_lapic_set_tpr(vcpu, cr8);
990 else
991 vcpu->arch.cr8 = cr8;
992 return 0;
993}
994EXPORT_SYMBOL_GPL(kvm_set_cr8);
995
996unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
997{
998 if (lapic_in_kernel(vcpu))
999 return kvm_lapic_get_cr8(vcpu);
1000 else
1001 return vcpu->arch.cr8;
1002}
1003EXPORT_SYMBOL_GPL(kvm_get_cr8);
1004
1005static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1006{
1007 int i;
1008
1009 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1010 for (i = 0; i < KVM_NR_DB_REGS; i++)
1011 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1012 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1013 }
1014}
1015
1016static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1017{
1018 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1019 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1020}
1021
1022static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1023{
1024 unsigned long dr7;
1025
1026 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1027 dr7 = vcpu->arch.guest_debug_dr7;
1028 else
1029 dr7 = vcpu->arch.dr7;
1030 kvm_x86_ops->set_dr7(vcpu, dr7);
1031 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1032 if (dr7 & DR7_BP_EN_MASK)
1033 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1034}
1035
1036static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1037{
1038 u64 fixed = DR6_FIXED_1;
1039
1040 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1041 fixed |= DR6_RTM;
1042 return fixed;
1043}
1044
1045static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1046{
1047 switch (dr) {
1048 case 0 ... 3:
1049 vcpu->arch.db[dr] = val;
1050 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1051 vcpu->arch.eff_db[dr] = val;
1052 break;
1053 case 4:
1054 /* fall through */
1055 case 6:
1056 if (val & 0xffffffff00000000ULL)
1057 return -1; /* #GP */
1058 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1059 kvm_update_dr6(vcpu);
1060 break;
1061 case 5:
1062 /* fall through */
1063 default: /* 7 */
1064 if (val & 0xffffffff00000000ULL)
1065 return -1; /* #GP */
1066 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1067 kvm_update_dr7(vcpu);
1068 break;
1069 }
1070
1071 return 0;
1072}
1073
1074int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1075{
1076 if (__kvm_set_dr(vcpu, dr, val)) {
1077 kvm_inject_gp(vcpu, 0);
1078 return 1;
1079 }
1080 return 0;
1081}
1082EXPORT_SYMBOL_GPL(kvm_set_dr);
1083
1084int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1085{
1086 switch (dr) {
1087 case 0 ... 3:
1088 *val = vcpu->arch.db[dr];
1089 break;
1090 case 4:
1091 /* fall through */
1092 case 6:
1093 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1094 *val = vcpu->arch.dr6;
1095 else
1096 *val = kvm_x86_ops->get_dr6(vcpu);
1097 break;
1098 case 5:
1099 /* fall through */
1100 default: /* 7 */
1101 *val = vcpu->arch.dr7;
1102 break;
1103 }
1104 return 0;
1105}
1106EXPORT_SYMBOL_GPL(kvm_get_dr);
1107
1108bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1109{
1110 u32 ecx = kvm_rcx_read(vcpu);
1111 u64 data;
1112 int err;
1113
1114 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1115 if (err)
1116 return err;
1117 kvm_rax_write(vcpu, (u32)data);
1118 kvm_rdx_write(vcpu, data >> 32);
1119 return err;
1120}
1121EXPORT_SYMBOL_GPL(kvm_rdpmc);
1122
1123/*
1124 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1125 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1126 *
1127 * This list is modified at module load time to reflect the
1128 * capabilities of the host cpu. This capabilities test skips MSRs that are
1129 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1130 * may depend on host virtualization features rather than host cpu features.
1131 */
1132
1133static u32 msrs_to_save[] = {
1134 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1135 MSR_STAR,
1136#ifdef CONFIG_X86_64
1137 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1138#endif
1139 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1140 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1141 MSR_IA32_SPEC_CTRL,
1142 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1143 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1144 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1145 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1146 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1147 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1148};
1149
1150static unsigned num_msrs_to_save;
1151
1152static u32 emulated_msrs[] = {
1153 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1154 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1155 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1156 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1157 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1158 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1159 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1160 HV_X64_MSR_RESET,
1161 HV_X64_MSR_VP_INDEX,
1162 HV_X64_MSR_VP_RUNTIME,
1163 HV_X64_MSR_SCONTROL,
1164 HV_X64_MSR_STIMER0_CONFIG,
1165 HV_X64_MSR_VP_ASSIST_PAGE,
1166 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1167 HV_X64_MSR_TSC_EMULATION_STATUS,
1168
1169 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1170 MSR_KVM_PV_EOI_EN,
1171
1172 MSR_IA32_TSC_ADJUST,
1173 MSR_IA32_TSCDEADLINE,
1174 MSR_IA32_ARCH_CAPABILITIES,
1175 MSR_IA32_MISC_ENABLE,
1176 MSR_IA32_MCG_STATUS,
1177 MSR_IA32_MCG_CTL,
1178 MSR_IA32_MCG_EXT_CTL,
1179 MSR_IA32_SMBASE,
1180 MSR_SMI_COUNT,
1181 MSR_PLATFORM_INFO,
1182 MSR_MISC_FEATURES_ENABLES,
1183 MSR_AMD64_VIRT_SPEC_CTRL,
1184 MSR_IA32_POWER_CTL,
1185
1186 /*
1187 * The following list leaves out MSRs whose values are determined
1188 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1189 * We always support the "true" VMX control MSRs, even if the host
1190 * processor does not, so I am putting these registers here rather
1191 * than in msrs_to_save.
1192 */
1193 MSR_IA32_VMX_BASIC,
1194 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1195 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1196 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1197 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1198 MSR_IA32_VMX_MISC,
1199 MSR_IA32_VMX_CR0_FIXED0,
1200 MSR_IA32_VMX_CR4_FIXED0,
1201 MSR_IA32_VMX_VMCS_ENUM,
1202 MSR_IA32_VMX_PROCBASED_CTLS2,
1203 MSR_IA32_VMX_EPT_VPID_CAP,
1204 MSR_IA32_VMX_VMFUNC,
1205
1206 MSR_K7_HWCR,
1207 MSR_KVM_POLL_CONTROL,
1208};
1209
1210static unsigned num_emulated_msrs;
1211
1212/*
1213 * List of msr numbers which are used to expose MSR-based features that
1214 * can be used by a hypervisor to validate requested CPU features.
1215 */
1216static u32 msr_based_features[] = {
1217 MSR_IA32_VMX_BASIC,
1218 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1219 MSR_IA32_VMX_PINBASED_CTLS,
1220 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1221 MSR_IA32_VMX_PROCBASED_CTLS,
1222 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1223 MSR_IA32_VMX_EXIT_CTLS,
1224 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1225 MSR_IA32_VMX_ENTRY_CTLS,
1226 MSR_IA32_VMX_MISC,
1227 MSR_IA32_VMX_CR0_FIXED0,
1228 MSR_IA32_VMX_CR0_FIXED1,
1229 MSR_IA32_VMX_CR4_FIXED0,
1230 MSR_IA32_VMX_CR4_FIXED1,
1231 MSR_IA32_VMX_VMCS_ENUM,
1232 MSR_IA32_VMX_PROCBASED_CTLS2,
1233 MSR_IA32_VMX_EPT_VPID_CAP,
1234 MSR_IA32_VMX_VMFUNC,
1235
1236 MSR_F10H_DECFG,
1237 MSR_IA32_UCODE_REV,
1238 MSR_IA32_ARCH_CAPABILITIES,
1239};
1240
1241static unsigned int num_msr_based_features;
1242
1243static u64 kvm_get_arch_capabilities(void)
1244{
1245 u64 data = 0;
1246
1247 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1248 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1249
1250 /*
1251 * If we're doing cache flushes (either "always" or "cond")
1252 * we will do one whenever the guest does a vmlaunch/vmresume.
1253 * If an outer hypervisor is doing the cache flush for us
1254 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1255 * capability to the guest too, and if EPT is disabled we're not
1256 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1257 * require a nested hypervisor to do a flush of its own.
1258 */
1259 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1260 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1261
1262 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1263 data |= ARCH_CAP_RDCL_NO;
1264 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1265 data |= ARCH_CAP_SSB_NO;
1266 if (!boot_cpu_has_bug(X86_BUG_MDS))
1267 data |= ARCH_CAP_MDS_NO;
1268
1269 return data;
1270}
1271
1272static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1273{
1274 switch (msr->index) {
1275 case MSR_IA32_ARCH_CAPABILITIES:
1276 msr->data = kvm_get_arch_capabilities();
1277 break;
1278 case MSR_IA32_UCODE_REV:
1279 rdmsrl_safe(msr->index, &msr->data);
1280 break;
1281 default:
1282 if (kvm_x86_ops->get_msr_feature(msr))
1283 return 1;
1284 }
1285 return 0;
1286}
1287
1288static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1289{
1290 struct kvm_msr_entry msr;
1291 int r;
1292
1293 msr.index = index;
1294 r = kvm_get_msr_feature(&msr);
1295 if (r)
1296 return r;
1297
1298 *data = msr.data;
1299
1300 return 0;
1301}
1302
1303static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1304{
1305 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1306 return false;
1307
1308 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1309 return false;
1310
1311 if (efer & (EFER_LME | EFER_LMA) &&
1312 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1313 return false;
1314
1315 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1316 return false;
1317
1318 return true;
1319
1320}
1321bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1322{
1323 if (efer & efer_reserved_bits)
1324 return false;
1325
1326 return __kvm_valid_efer(vcpu, efer);
1327}
1328EXPORT_SYMBOL_GPL(kvm_valid_efer);
1329
1330static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1331{
1332 u64 old_efer = vcpu->arch.efer;
1333 u64 efer = msr_info->data;
1334
1335 if (efer & efer_reserved_bits)
1336 return 1;
1337
1338 if (!msr_info->host_initiated) {
1339 if (!__kvm_valid_efer(vcpu, efer))
1340 return 1;
1341
1342 if (is_paging(vcpu) &&
1343 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1344 return 1;
1345 }
1346
1347 efer &= ~EFER_LMA;
1348 efer |= vcpu->arch.efer & EFER_LMA;
1349
1350 kvm_x86_ops->set_efer(vcpu, efer);
1351
1352 /* Update reserved bits */
1353 if ((efer ^ old_efer) & EFER_NX)
1354 kvm_mmu_reset_context(vcpu);
1355
1356 return 0;
1357}
1358
1359void kvm_enable_efer_bits(u64 mask)
1360{
1361 efer_reserved_bits &= ~mask;
1362}
1363EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1364
1365/*
1366 * Write @data into the MSR specified by @index. Select MSR specific fault
1367 * checks are bypassed if @host_initiated is %true.
1368 * Returns 0 on success, non-0 otherwise.
1369 * Assumes vcpu_load() was already called.
1370 */
1371static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1372 bool host_initiated)
1373{
1374 struct msr_data msr;
1375
1376 switch (index) {
1377 case MSR_FS_BASE:
1378 case MSR_GS_BASE:
1379 case MSR_KERNEL_GS_BASE:
1380 case MSR_CSTAR:
1381 case MSR_LSTAR:
1382 if (is_noncanonical_address(data, vcpu))
1383 return 1;
1384 break;
1385 case MSR_IA32_SYSENTER_EIP:
1386 case MSR_IA32_SYSENTER_ESP:
1387 /*
1388 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1389 * non-canonical address is written on Intel but not on
1390 * AMD (which ignores the top 32-bits, because it does
1391 * not implement 64-bit SYSENTER).
1392 *
1393 * 64-bit code should hence be able to write a non-canonical
1394 * value on AMD. Making the address canonical ensures that
1395 * vmentry does not fail on Intel after writing a non-canonical
1396 * value, and that something deterministic happens if the guest
1397 * invokes 64-bit SYSENTER.
1398 */
1399 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1400 }
1401
1402 msr.data = data;
1403 msr.index = index;
1404 msr.host_initiated = host_initiated;
1405
1406 return kvm_x86_ops->set_msr(vcpu, &msr);
1407}
1408
1409/*
1410 * Read the MSR specified by @index into @data. Select MSR specific fault
1411 * checks are bypassed if @host_initiated is %true.
1412 * Returns 0 on success, non-0 otherwise.
1413 * Assumes vcpu_load() was already called.
1414 */
1415static int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1416 bool host_initiated)
1417{
1418 struct msr_data msr;
1419 int ret;
1420
1421 msr.index = index;
1422 msr.host_initiated = host_initiated;
1423
1424 ret = kvm_x86_ops->get_msr(vcpu, &msr);
1425 if (!ret)
1426 *data = msr.data;
1427 return ret;
1428}
1429
1430int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1431{
1432 return __kvm_get_msr(vcpu, index, data, false);
1433}
1434EXPORT_SYMBOL_GPL(kvm_get_msr);
1435
1436int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1437{
1438 return __kvm_set_msr(vcpu, index, data, false);
1439}
1440EXPORT_SYMBOL_GPL(kvm_set_msr);
1441
1442/*
1443 * Adapt set_msr() to msr_io()'s calling convention
1444 */
1445static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1446{
1447 return __kvm_get_msr(vcpu, index, data, true);
1448}
1449
1450static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1451{
1452 return __kvm_set_msr(vcpu, index, *data, true);
1453}
1454
1455#ifdef CONFIG_X86_64
1456struct pvclock_gtod_data {
1457 seqcount_t seq;
1458
1459 struct { /* extract of a clocksource struct */
1460 int vclock_mode;
1461 u64 cycle_last;
1462 u64 mask;
1463 u32 mult;
1464 u32 shift;
1465 } clock;
1466
1467 u64 boot_ns;
1468 u64 nsec_base;
1469 u64 wall_time_sec;
1470};
1471
1472static struct pvclock_gtod_data pvclock_gtod_data;
1473
1474static void update_pvclock_gtod(struct timekeeper *tk)
1475{
1476 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1477 u64 boot_ns;
1478
1479 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1480
1481 write_seqcount_begin(&vdata->seq);
1482
1483 /* copy pvclock gtod data */
1484 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1485 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1486 vdata->clock.mask = tk->tkr_mono.mask;
1487 vdata->clock.mult = tk->tkr_mono.mult;
1488 vdata->clock.shift = tk->tkr_mono.shift;
1489
1490 vdata->boot_ns = boot_ns;
1491 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1492
1493 vdata->wall_time_sec = tk->xtime_sec;
1494
1495 write_seqcount_end(&vdata->seq);
1496}
1497#endif
1498
1499void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1500{
1501 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1502 kvm_vcpu_kick(vcpu);
1503}
1504
1505static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1506{
1507 int version;
1508 int r;
1509 struct pvclock_wall_clock wc;
1510 struct timespec64 boot;
1511
1512 if (!wall_clock)
1513 return;
1514
1515 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1516 if (r)
1517 return;
1518
1519 if (version & 1)
1520 ++version; /* first time write, random junk */
1521
1522 ++version;
1523
1524 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1525 return;
1526
1527 /*
1528 * The guest calculates current wall clock time by adding
1529 * system time (updated by kvm_guest_time_update below) to the
1530 * wall clock specified here. guest system time equals host
1531 * system time for us, thus we must fill in host boot time here.
1532 */
1533 getboottime64(&boot);
1534
1535 if (kvm->arch.kvmclock_offset) {
1536 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1537 boot = timespec64_sub(boot, ts);
1538 }
1539 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1540 wc.nsec = boot.tv_nsec;
1541 wc.version = version;
1542
1543 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1544
1545 version++;
1546 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1547}
1548
1549static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1550{
1551 do_shl32_div32(dividend, divisor);
1552 return dividend;
1553}
1554
1555static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1556 s8 *pshift, u32 *pmultiplier)
1557{
1558 uint64_t scaled64;
1559 int32_t shift = 0;
1560 uint64_t tps64;
1561 uint32_t tps32;
1562
1563 tps64 = base_hz;
1564 scaled64 = scaled_hz;
1565 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1566 tps64 >>= 1;
1567 shift--;
1568 }
1569
1570 tps32 = (uint32_t)tps64;
1571 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1572 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1573 scaled64 >>= 1;
1574 else
1575 tps32 <<= 1;
1576 shift++;
1577 }
1578
1579 *pshift = shift;
1580 *pmultiplier = div_frac(scaled64, tps32);
1581}
1582
1583#ifdef CONFIG_X86_64
1584static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1585#endif
1586
1587static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1588static unsigned long max_tsc_khz;
1589
1590static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1591{
1592 u64 v = (u64)khz * (1000000 + ppm);
1593 do_div(v, 1000000);
1594 return v;
1595}
1596
1597static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1598{
1599 u64 ratio;
1600
1601 /* Guest TSC same frequency as host TSC? */
1602 if (!scale) {
1603 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1604 return 0;
1605 }
1606
1607 /* TSC scaling supported? */
1608 if (!kvm_has_tsc_control) {
1609 if (user_tsc_khz > tsc_khz) {
1610 vcpu->arch.tsc_catchup = 1;
1611 vcpu->arch.tsc_always_catchup = 1;
1612 return 0;
1613 } else {
1614 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
1615 return -1;
1616 }
1617 }
1618
1619 /* TSC scaling required - calculate ratio */
1620 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1621 user_tsc_khz, tsc_khz);
1622
1623 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1624 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1625 user_tsc_khz);
1626 return -1;
1627 }
1628
1629 vcpu->arch.tsc_scaling_ratio = ratio;
1630 return 0;
1631}
1632
1633static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1634{
1635 u32 thresh_lo, thresh_hi;
1636 int use_scaling = 0;
1637
1638 /* tsc_khz can be zero if TSC calibration fails */
1639 if (user_tsc_khz == 0) {
1640 /* set tsc_scaling_ratio to a safe value */
1641 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1642 return -1;
1643 }
1644
1645 /* Compute a scale to convert nanoseconds in TSC cycles */
1646 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1647 &vcpu->arch.virtual_tsc_shift,
1648 &vcpu->arch.virtual_tsc_mult);
1649 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1650
1651 /*
1652 * Compute the variation in TSC rate which is acceptable
1653 * within the range of tolerance and decide if the
1654 * rate being applied is within that bounds of the hardware
1655 * rate. If so, no scaling or compensation need be done.
1656 */
1657 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1658 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1659 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1660 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1661 use_scaling = 1;
1662 }
1663 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1664}
1665
1666static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1667{
1668 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1669 vcpu->arch.virtual_tsc_mult,
1670 vcpu->arch.virtual_tsc_shift);
1671 tsc += vcpu->arch.this_tsc_write;
1672 return tsc;
1673}
1674
1675static inline int gtod_is_based_on_tsc(int mode)
1676{
1677 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1678}
1679
1680static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1681{
1682#ifdef CONFIG_X86_64
1683 bool vcpus_matched;
1684 struct kvm_arch *ka = &vcpu->kvm->arch;
1685 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1686
1687 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1688 atomic_read(&vcpu->kvm->online_vcpus));
1689
1690 /*
1691 * Once the masterclock is enabled, always perform request in
1692 * order to update it.
1693 *
1694 * In order to enable masterclock, the host clocksource must be TSC
1695 * and the vcpus need to have matched TSCs. When that happens,
1696 * perform request to enable masterclock.
1697 */
1698 if (ka->use_master_clock ||
1699 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1700 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1701
1702 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1703 atomic_read(&vcpu->kvm->online_vcpus),
1704 ka->use_master_clock, gtod->clock.vclock_mode);
1705#endif
1706}
1707
1708static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1709{
1710 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1711 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1712}
1713
1714/*
1715 * Multiply tsc by a fixed point number represented by ratio.
1716 *
1717 * The most significant 64-N bits (mult) of ratio represent the
1718 * integral part of the fixed point number; the remaining N bits
1719 * (frac) represent the fractional part, ie. ratio represents a fixed
1720 * point number (mult + frac * 2^(-N)).
1721 *
1722 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1723 */
1724static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1725{
1726 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1727}
1728
1729u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1730{
1731 u64 _tsc = tsc;
1732 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1733
1734 if (ratio != kvm_default_tsc_scaling_ratio)
1735 _tsc = __scale_tsc(ratio, tsc);
1736
1737 return _tsc;
1738}
1739EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1740
1741static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1742{
1743 u64 tsc;
1744
1745 tsc = kvm_scale_tsc(vcpu, rdtsc());
1746
1747 return target_tsc - tsc;
1748}
1749
1750u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1751{
1752 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1753
1754 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1755}
1756EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1757
1758static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1759{
1760 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
1761}
1762
1763static inline bool kvm_check_tsc_unstable(void)
1764{
1765#ifdef CONFIG_X86_64
1766 /*
1767 * TSC is marked unstable when we're running on Hyper-V,
1768 * 'TSC page' clocksource is good.
1769 */
1770 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1771 return false;
1772#endif
1773 return check_tsc_unstable();
1774}
1775
1776void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1777{
1778 struct kvm *kvm = vcpu->kvm;
1779 u64 offset, ns, elapsed;
1780 unsigned long flags;
1781 bool matched;
1782 bool already_matched;
1783 u64 data = msr->data;
1784 bool synchronizing = false;
1785
1786 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1787 offset = kvm_compute_tsc_offset(vcpu, data);
1788 ns = ktime_get_boottime_ns();
1789 elapsed = ns - kvm->arch.last_tsc_nsec;
1790
1791 if (vcpu->arch.virtual_tsc_khz) {
1792 if (data == 0 && msr->host_initiated) {
1793 /*
1794 * detection of vcpu initialization -- need to sync
1795 * with other vCPUs. This particularly helps to keep
1796 * kvm_clock stable after CPU hotplug
1797 */
1798 synchronizing = true;
1799 } else {
1800 u64 tsc_exp = kvm->arch.last_tsc_write +
1801 nsec_to_cycles(vcpu, elapsed);
1802 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1803 /*
1804 * Special case: TSC write with a small delta (1 second)
1805 * of virtual cycle time against real time is
1806 * interpreted as an attempt to synchronize the CPU.
1807 */
1808 synchronizing = data < tsc_exp + tsc_hz &&
1809 data + tsc_hz > tsc_exp;
1810 }
1811 }
1812
1813 /*
1814 * For a reliable TSC, we can match TSC offsets, and for an unstable
1815 * TSC, we add elapsed time in this computation. We could let the
1816 * compensation code attempt to catch up if we fall behind, but
1817 * it's better to try to match offsets from the beginning.
1818 */
1819 if (synchronizing &&
1820 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1821 if (!kvm_check_tsc_unstable()) {
1822 offset = kvm->arch.cur_tsc_offset;
1823 } else {
1824 u64 delta = nsec_to_cycles(vcpu, elapsed);
1825 data += delta;
1826 offset = kvm_compute_tsc_offset(vcpu, data);
1827 }
1828 matched = true;
1829 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1830 } else {
1831 /*
1832 * We split periods of matched TSC writes into generations.
1833 * For each generation, we track the original measured
1834 * nanosecond time, offset, and write, so if TSCs are in
1835 * sync, we can match exact offset, and if not, we can match
1836 * exact software computation in compute_guest_tsc()
1837 *
1838 * These values are tracked in kvm->arch.cur_xxx variables.
1839 */
1840 kvm->arch.cur_tsc_generation++;
1841 kvm->arch.cur_tsc_nsec = ns;
1842 kvm->arch.cur_tsc_write = data;
1843 kvm->arch.cur_tsc_offset = offset;
1844 matched = false;
1845 }
1846
1847 /*
1848 * We also track th most recent recorded KHZ, write and time to
1849 * allow the matching interval to be extended at each write.
1850 */
1851 kvm->arch.last_tsc_nsec = ns;
1852 kvm->arch.last_tsc_write = data;
1853 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1854
1855 vcpu->arch.last_guest_tsc = data;
1856
1857 /* Keep track of which generation this VCPU has synchronized to */
1858 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1859 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1860 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1861
1862 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
1863 update_ia32_tsc_adjust_msr(vcpu, offset);
1864
1865 kvm_vcpu_write_tsc_offset(vcpu, offset);
1866 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1867
1868 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1869 if (!matched) {
1870 kvm->arch.nr_vcpus_matched_tsc = 0;
1871 } else if (!already_matched) {
1872 kvm->arch.nr_vcpus_matched_tsc++;
1873 }
1874
1875 kvm_track_tsc_matching(vcpu);
1876 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1877}
1878
1879EXPORT_SYMBOL_GPL(kvm_write_tsc);
1880
1881static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1882 s64 adjustment)
1883{
1884 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1885 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
1886}
1887
1888static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1889{
1890 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1891 WARN_ON(adjustment < 0);
1892 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1893 adjust_tsc_offset_guest(vcpu, adjustment);
1894}
1895
1896#ifdef CONFIG_X86_64
1897
1898static u64 read_tsc(void)
1899{
1900 u64 ret = (u64)rdtsc_ordered();
1901 u64 last = pvclock_gtod_data.clock.cycle_last;
1902
1903 if (likely(ret >= last))
1904 return ret;
1905
1906 /*
1907 * GCC likes to generate cmov here, but this branch is extremely
1908 * predictable (it's just a function of time and the likely is
1909 * very likely) and there's a data dependence, so force GCC
1910 * to generate a branch instead. I don't barrier() because
1911 * we don't actually need a barrier, and if this function
1912 * ever gets inlined it will generate worse code.
1913 */
1914 asm volatile ("");
1915 return last;
1916}
1917
1918static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
1919{
1920 long v;
1921 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1922 u64 tsc_pg_val;
1923
1924 switch (gtod->clock.vclock_mode) {
1925 case VCLOCK_HVCLOCK:
1926 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1927 tsc_timestamp);
1928 if (tsc_pg_val != U64_MAX) {
1929 /* TSC page valid */
1930 *mode = VCLOCK_HVCLOCK;
1931 v = (tsc_pg_val - gtod->clock.cycle_last) &
1932 gtod->clock.mask;
1933 } else {
1934 /* TSC page invalid */
1935 *mode = VCLOCK_NONE;
1936 }
1937 break;
1938 case VCLOCK_TSC:
1939 *mode = VCLOCK_TSC;
1940 *tsc_timestamp = read_tsc();
1941 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1942 gtod->clock.mask;
1943 break;
1944 default:
1945 *mode = VCLOCK_NONE;
1946 }
1947
1948 if (*mode == VCLOCK_NONE)
1949 *tsc_timestamp = v = 0;
1950
1951 return v * gtod->clock.mult;
1952}
1953
1954static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
1955{
1956 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1957 unsigned long seq;
1958 int mode;
1959 u64 ns;
1960
1961 do {
1962 seq = read_seqcount_begin(&gtod->seq);
1963 ns = gtod->nsec_base;
1964 ns += vgettsc(tsc_timestamp, &mode);
1965 ns >>= gtod->clock.shift;
1966 ns += gtod->boot_ns;
1967 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1968 *t = ns;
1969
1970 return mode;
1971}
1972
1973static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
1974{
1975 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1976 unsigned long seq;
1977 int mode;
1978 u64 ns;
1979
1980 do {
1981 seq = read_seqcount_begin(&gtod->seq);
1982 ts->tv_sec = gtod->wall_time_sec;
1983 ns = gtod->nsec_base;
1984 ns += vgettsc(tsc_timestamp, &mode);
1985 ns >>= gtod->clock.shift;
1986 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1987
1988 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1989 ts->tv_nsec = ns;
1990
1991 return mode;
1992}
1993
1994/* returns true if host is using TSC based clocksource */
1995static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
1996{
1997 /* checked again under seqlock below */
1998 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
1999 return false;
2000
2001 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
2002 tsc_timestamp));
2003}
2004
2005/* returns true if host is using TSC based clocksource */
2006static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2007 u64 *tsc_timestamp)
2008{
2009 /* checked again under seqlock below */
2010 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2011 return false;
2012
2013 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2014}
2015#endif
2016
2017/*
2018 *
2019 * Assuming a stable TSC across physical CPUS, and a stable TSC
2020 * across virtual CPUs, the following condition is possible.
2021 * Each numbered line represents an event visible to both
2022 * CPUs at the next numbered event.
2023 *
2024 * "timespecX" represents host monotonic time. "tscX" represents
2025 * RDTSC value.
2026 *
2027 * VCPU0 on CPU0 | VCPU1 on CPU1
2028 *
2029 * 1. read timespec0,tsc0
2030 * 2. | timespec1 = timespec0 + N
2031 * | tsc1 = tsc0 + M
2032 * 3. transition to guest | transition to guest
2033 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2034 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2035 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2036 *
2037 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2038 *
2039 * - ret0 < ret1
2040 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2041 * ...
2042 * - 0 < N - M => M < N
2043 *
2044 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2045 * always the case (the difference between two distinct xtime instances
2046 * might be smaller then the difference between corresponding TSC reads,
2047 * when updating guest vcpus pvclock areas).
2048 *
2049 * To avoid that problem, do not allow visibility of distinct
2050 * system_timestamp/tsc_timestamp values simultaneously: use a master
2051 * copy of host monotonic time values. Update that master copy
2052 * in lockstep.
2053 *
2054 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2055 *
2056 */
2057
2058static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2059{
2060#ifdef CONFIG_X86_64
2061 struct kvm_arch *ka = &kvm->arch;
2062 int vclock_mode;
2063 bool host_tsc_clocksource, vcpus_matched;
2064
2065 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2066 atomic_read(&kvm->online_vcpus));
2067
2068 /*
2069 * If the host uses TSC clock, then passthrough TSC as stable
2070 * to the guest.
2071 */
2072 host_tsc_clocksource = kvm_get_time_and_clockread(
2073 &ka->master_kernel_ns,
2074 &ka->master_cycle_now);
2075
2076 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2077 && !ka->backwards_tsc_observed
2078 && !ka->boot_vcpu_runs_old_kvmclock;
2079
2080 if (ka->use_master_clock)
2081 atomic_set(&kvm_guest_has_master_clock, 1);
2082
2083 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2084 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2085 vcpus_matched);
2086#endif
2087}
2088
2089void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2090{
2091 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2092}
2093
2094static void kvm_gen_update_masterclock(struct kvm *kvm)
2095{
2096#ifdef CONFIG_X86_64
2097 int i;
2098 struct kvm_vcpu *vcpu;
2099 struct kvm_arch *ka = &kvm->arch;
2100
2101 spin_lock(&ka->pvclock_gtod_sync_lock);
2102 kvm_make_mclock_inprogress_request(kvm);
2103 /* no guest entries from this point */
2104 pvclock_update_vm_gtod_copy(kvm);
2105
2106 kvm_for_each_vcpu(i, vcpu, kvm)
2107 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2108
2109 /* guest entries allowed */
2110 kvm_for_each_vcpu(i, vcpu, kvm)
2111 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2112
2113 spin_unlock(&ka->pvclock_gtod_sync_lock);
2114#endif
2115}
2116
2117u64 get_kvmclock_ns(struct kvm *kvm)
2118{
2119 struct kvm_arch *ka = &kvm->arch;
2120 struct pvclock_vcpu_time_info hv_clock;
2121 u64 ret;
2122
2123 spin_lock(&ka->pvclock_gtod_sync_lock);
2124 if (!ka->use_master_clock) {
2125 spin_unlock(&ka->pvclock_gtod_sync_lock);
2126 return ktime_get_boottime_ns() + ka->kvmclock_offset;
2127 }
2128
2129 hv_clock.tsc_timestamp = ka->master_cycle_now;
2130 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2131 spin_unlock(&ka->pvclock_gtod_sync_lock);
2132
2133 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2134 get_cpu();
2135
2136 if (__this_cpu_read(cpu_tsc_khz)) {
2137 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2138 &hv_clock.tsc_shift,
2139 &hv_clock.tsc_to_system_mul);
2140 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2141 } else
2142 ret = ktime_get_boottime_ns() + ka->kvmclock_offset;
2143
2144 put_cpu();
2145
2146 return ret;
2147}
2148
2149static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2150{
2151 struct kvm_vcpu_arch *vcpu = &v->arch;
2152 struct pvclock_vcpu_time_info guest_hv_clock;
2153
2154 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2155 &guest_hv_clock, sizeof(guest_hv_clock))))
2156 return;
2157
2158 /* This VCPU is paused, but it's legal for a guest to read another
2159 * VCPU's kvmclock, so we really have to follow the specification where
2160 * it says that version is odd if data is being modified, and even after
2161 * it is consistent.
2162 *
2163 * Version field updates must be kept separate. This is because
2164 * kvm_write_guest_cached might use a "rep movs" instruction, and
2165 * writes within a string instruction are weakly ordered. So there
2166 * are three writes overall.
2167 *
2168 * As a small optimization, only write the version field in the first
2169 * and third write. The vcpu->pv_time cache is still valid, because the
2170 * version field is the first in the struct.
2171 */
2172 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2173
2174 if (guest_hv_clock.version & 1)
2175 ++guest_hv_clock.version; /* first time write, random junk */
2176
2177 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2178 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2179 &vcpu->hv_clock,
2180 sizeof(vcpu->hv_clock.version));
2181
2182 smp_wmb();
2183
2184 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2185 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2186
2187 if (vcpu->pvclock_set_guest_stopped_request) {
2188 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2189 vcpu->pvclock_set_guest_stopped_request = false;
2190 }
2191
2192 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2193
2194 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2195 &vcpu->hv_clock,
2196 sizeof(vcpu->hv_clock));
2197
2198 smp_wmb();
2199
2200 vcpu->hv_clock.version++;
2201 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2202 &vcpu->hv_clock,
2203 sizeof(vcpu->hv_clock.version));
2204}
2205
2206static int kvm_guest_time_update(struct kvm_vcpu *v)
2207{
2208 unsigned long flags, tgt_tsc_khz;
2209 struct kvm_vcpu_arch *vcpu = &v->arch;
2210 struct kvm_arch *ka = &v->kvm->arch;
2211 s64 kernel_ns;
2212 u64 tsc_timestamp, host_tsc;
2213 u8 pvclock_flags;
2214 bool use_master_clock;
2215
2216 kernel_ns = 0;
2217 host_tsc = 0;
2218
2219 /*
2220 * If the host uses TSC clock, then passthrough TSC as stable
2221 * to the guest.
2222 */
2223 spin_lock(&ka->pvclock_gtod_sync_lock);
2224 use_master_clock = ka->use_master_clock;
2225 if (use_master_clock) {
2226 host_tsc = ka->master_cycle_now;
2227 kernel_ns = ka->master_kernel_ns;
2228 }
2229 spin_unlock(&ka->pvclock_gtod_sync_lock);
2230
2231 /* Keep irq disabled to prevent changes to the clock */
2232 local_irq_save(flags);
2233 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2234 if (unlikely(tgt_tsc_khz == 0)) {
2235 local_irq_restore(flags);
2236 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2237 return 1;
2238 }
2239 if (!use_master_clock) {
2240 host_tsc = rdtsc();
2241 kernel_ns = ktime_get_boottime_ns();
2242 }
2243
2244 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2245
2246 /*
2247 * We may have to catch up the TSC to match elapsed wall clock
2248 * time for two reasons, even if kvmclock is used.
2249 * 1) CPU could have been running below the maximum TSC rate
2250 * 2) Broken TSC compensation resets the base at each VCPU
2251 * entry to avoid unknown leaps of TSC even when running
2252 * again on the same CPU. This may cause apparent elapsed
2253 * time to disappear, and the guest to stand still or run
2254 * very slowly.
2255 */
2256 if (vcpu->tsc_catchup) {
2257 u64 tsc = compute_guest_tsc(v, kernel_ns);
2258 if (tsc > tsc_timestamp) {
2259 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2260 tsc_timestamp = tsc;
2261 }
2262 }
2263
2264 local_irq_restore(flags);
2265
2266 /* With all the info we got, fill in the values */
2267
2268 if (kvm_has_tsc_control)
2269 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2270
2271 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2272 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2273 &vcpu->hv_clock.tsc_shift,
2274 &vcpu->hv_clock.tsc_to_system_mul);
2275 vcpu->hw_tsc_khz = tgt_tsc_khz;
2276 }
2277
2278 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2279 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2280 vcpu->last_guest_tsc = tsc_timestamp;
2281
2282 /* If the host uses TSC clocksource, then it is stable */
2283 pvclock_flags = 0;
2284 if (use_master_clock)
2285 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2286
2287 vcpu->hv_clock.flags = pvclock_flags;
2288
2289 if (vcpu->pv_time_enabled)
2290 kvm_setup_pvclock_page(v);
2291 if (v == kvm_get_vcpu(v->kvm, 0))
2292 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2293 return 0;
2294}
2295
2296/*
2297 * kvmclock updates which are isolated to a given vcpu, such as
2298 * vcpu->cpu migration, should not allow system_timestamp from
2299 * the rest of the vcpus to remain static. Otherwise ntp frequency
2300 * correction applies to one vcpu's system_timestamp but not
2301 * the others.
2302 *
2303 * So in those cases, request a kvmclock update for all vcpus.
2304 * We need to rate-limit these requests though, as they can
2305 * considerably slow guests that have a large number of vcpus.
2306 * The time for a remote vcpu to update its kvmclock is bound
2307 * by the delay we use to rate-limit the updates.
2308 */
2309
2310#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2311
2312static void kvmclock_update_fn(struct work_struct *work)
2313{
2314 int i;
2315 struct delayed_work *dwork = to_delayed_work(work);
2316 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2317 kvmclock_update_work);
2318 struct kvm *kvm = container_of(ka, struct kvm, arch);
2319 struct kvm_vcpu *vcpu;
2320
2321 kvm_for_each_vcpu(i, vcpu, kvm) {
2322 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2323 kvm_vcpu_kick(vcpu);
2324 }
2325}
2326
2327static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2328{
2329 struct kvm *kvm = v->kvm;
2330
2331 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2332 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2333 KVMCLOCK_UPDATE_DELAY);
2334}
2335
2336#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2337
2338static void kvmclock_sync_fn(struct work_struct *work)
2339{
2340 struct delayed_work *dwork = to_delayed_work(work);
2341 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2342 kvmclock_sync_work);
2343 struct kvm *kvm = container_of(ka, struct kvm, arch);
2344
2345 if (!kvmclock_periodic_sync)
2346 return;
2347
2348 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2349 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2350 KVMCLOCK_SYNC_PERIOD);
2351}
2352
2353/*
2354 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2355 */
2356static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2357{
2358 /* McStatusWrEn enabled? */
2359 if (guest_cpuid_is_amd(vcpu))
2360 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2361
2362 return false;
2363}
2364
2365static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2366{
2367 u64 mcg_cap = vcpu->arch.mcg_cap;
2368 unsigned bank_num = mcg_cap & 0xff;
2369 u32 msr = msr_info->index;
2370 u64 data = msr_info->data;
2371
2372 switch (msr) {
2373 case MSR_IA32_MCG_STATUS:
2374 vcpu->arch.mcg_status = data;
2375 break;
2376 case MSR_IA32_MCG_CTL:
2377 if (!(mcg_cap & MCG_CTL_P) &&
2378 (data || !msr_info->host_initiated))
2379 return 1;
2380 if (data != 0 && data != ~(u64)0)
2381 return 1;
2382 vcpu->arch.mcg_ctl = data;
2383 break;
2384 default:
2385 if (msr >= MSR_IA32_MC0_CTL &&
2386 msr < MSR_IA32_MCx_CTL(bank_num)) {
2387 u32 offset = msr - MSR_IA32_MC0_CTL;
2388 /* only 0 or all 1s can be written to IA32_MCi_CTL
2389 * some Linux kernels though clear bit 10 in bank 4 to
2390 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2391 * this to avoid an uncatched #GP in the guest
2392 */
2393 if ((offset & 0x3) == 0 &&
2394 data != 0 && (data | (1 << 10)) != ~(u64)0)
2395 return -1;
2396
2397 /* MCi_STATUS */
2398 if (!msr_info->host_initiated &&
2399 (offset & 0x3) == 1 && data != 0) {
2400 if (!can_set_mci_status(vcpu))
2401 return -1;
2402 }
2403
2404 vcpu->arch.mce_banks[offset] = data;
2405 break;
2406 }
2407 return 1;
2408 }
2409 return 0;
2410}
2411
2412static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2413{
2414 struct kvm *kvm = vcpu->kvm;
2415 int lm = is_long_mode(vcpu);
2416 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2417 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2418 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2419 : kvm->arch.xen_hvm_config.blob_size_32;
2420 u32 page_num = data & ~PAGE_MASK;
2421 u64 page_addr = data & PAGE_MASK;
2422 u8 *page;
2423 int r;
2424
2425 r = -E2BIG;
2426 if (page_num >= blob_size)
2427 goto out;
2428 r = -ENOMEM;
2429 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2430 if (IS_ERR(page)) {
2431 r = PTR_ERR(page);
2432 goto out;
2433 }
2434 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2435 goto out_free;
2436 r = 0;
2437out_free:
2438 kfree(page);
2439out:
2440 return r;
2441}
2442
2443static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2444{
2445 gpa_t gpa = data & ~0x3f;
2446
2447 /* Bits 3:5 are reserved, Should be zero */
2448 if (data & 0x38)
2449 return 1;
2450
2451 vcpu->arch.apf.msr_val = data;
2452
2453 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2454 kvm_clear_async_pf_completion_queue(vcpu);
2455 kvm_async_pf_hash_reset(vcpu);
2456 return 0;
2457 }
2458
2459 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2460 sizeof(u32)))
2461 return 1;
2462
2463 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2464 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2465 kvm_async_pf_wakeup_all(vcpu);
2466 return 0;
2467}
2468
2469static void kvmclock_reset(struct kvm_vcpu *vcpu)
2470{
2471 vcpu->arch.pv_time_enabled = false;
2472}
2473
2474static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2475{
2476 ++vcpu->stat.tlb_flush;
2477 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2478}
2479
2480static void record_steal_time(struct kvm_vcpu *vcpu)
2481{
2482 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2483 return;
2484
2485 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2486 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2487 return;
2488
2489 /*
2490 * Doing a TLB flush here, on the guest's behalf, can avoid
2491 * expensive IPIs.
2492 */
2493 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2494 vcpu->arch.st.steal.preempted & KVM_VCPU_FLUSH_TLB);
2495 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2496 kvm_vcpu_flush_tlb(vcpu, false);
2497
2498 if (vcpu->arch.st.steal.version & 1)
2499 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2500
2501 vcpu->arch.st.steal.version += 1;
2502
2503 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2504 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2505
2506 smp_wmb();
2507
2508 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2509 vcpu->arch.st.last_steal;
2510 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2511
2512 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2513 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2514
2515 smp_wmb();
2516
2517 vcpu->arch.st.steal.version += 1;
2518
2519 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2520 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2521}
2522
2523int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2524{
2525 bool pr = false;
2526 u32 msr = msr_info->index;
2527 u64 data = msr_info->data;
2528
2529 switch (msr) {
2530 case MSR_AMD64_NB_CFG:
2531 case MSR_IA32_UCODE_WRITE:
2532 case MSR_VM_HSAVE_PA:
2533 case MSR_AMD64_PATCH_LOADER:
2534 case MSR_AMD64_BU_CFG2:
2535 case MSR_AMD64_DC_CFG:
2536 case MSR_F15H_EX_CFG:
2537 break;
2538
2539 case MSR_IA32_UCODE_REV:
2540 if (msr_info->host_initiated)
2541 vcpu->arch.microcode_version = data;
2542 break;
2543 case MSR_IA32_ARCH_CAPABILITIES:
2544 if (!msr_info->host_initiated)
2545 return 1;
2546 vcpu->arch.arch_capabilities = data;
2547 break;
2548 case MSR_EFER:
2549 return set_efer(vcpu, msr_info);
2550 case MSR_K7_HWCR:
2551 data &= ~(u64)0x40; /* ignore flush filter disable */
2552 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2553 data &= ~(u64)0x8; /* ignore TLB cache disable */
2554
2555 /* Handle McStatusWrEn */
2556 if (data == BIT_ULL(18)) {
2557 vcpu->arch.msr_hwcr = data;
2558 } else if (data != 0) {
2559 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2560 data);
2561 return 1;
2562 }
2563 break;
2564 case MSR_FAM10H_MMIO_CONF_BASE:
2565 if (data != 0) {
2566 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2567 "0x%llx\n", data);
2568 return 1;
2569 }
2570 break;
2571 case MSR_IA32_DEBUGCTLMSR:
2572 if (!data) {
2573 /* We support the non-activated case already */
2574 break;
2575 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2576 /* Values other than LBR and BTF are vendor-specific,
2577 thus reserved and should throw a #GP */
2578 return 1;
2579 }
2580 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2581 __func__, data);
2582 break;
2583 case 0x200 ... 0x2ff:
2584 return kvm_mtrr_set_msr(vcpu, msr, data);
2585 case MSR_IA32_APICBASE:
2586 return kvm_set_apic_base(vcpu, msr_info);
2587 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2588 return kvm_x2apic_msr_write(vcpu, msr, data);
2589 case MSR_IA32_TSCDEADLINE:
2590 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2591 break;
2592 case MSR_IA32_TSC_ADJUST:
2593 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2594 if (!msr_info->host_initiated) {
2595 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2596 adjust_tsc_offset_guest(vcpu, adj);
2597 }
2598 vcpu->arch.ia32_tsc_adjust_msr = data;
2599 }
2600 break;
2601 case MSR_IA32_MISC_ENABLE:
2602 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2603 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2604 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2605 return 1;
2606 vcpu->arch.ia32_misc_enable_msr = data;
2607 kvm_update_cpuid(vcpu);
2608 } else {
2609 vcpu->arch.ia32_misc_enable_msr = data;
2610 }
2611 break;
2612 case MSR_IA32_SMBASE:
2613 if (!msr_info->host_initiated)
2614 return 1;
2615 vcpu->arch.smbase = data;
2616 break;
2617 case MSR_IA32_POWER_CTL:
2618 vcpu->arch.msr_ia32_power_ctl = data;
2619 break;
2620 case MSR_IA32_TSC:
2621 kvm_write_tsc(vcpu, msr_info);
2622 break;
2623 case MSR_SMI_COUNT:
2624 if (!msr_info->host_initiated)
2625 return 1;
2626 vcpu->arch.smi_count = data;
2627 break;
2628 case MSR_KVM_WALL_CLOCK_NEW:
2629 case MSR_KVM_WALL_CLOCK:
2630 vcpu->kvm->arch.wall_clock = data;
2631 kvm_write_wall_clock(vcpu->kvm, data);
2632 break;
2633 case MSR_KVM_SYSTEM_TIME_NEW:
2634 case MSR_KVM_SYSTEM_TIME: {
2635 struct kvm_arch *ka = &vcpu->kvm->arch;
2636
2637 kvmclock_reset(vcpu);
2638
2639 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2640 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2641
2642 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2643 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2644
2645 ka->boot_vcpu_runs_old_kvmclock = tmp;
2646 }
2647
2648 vcpu->arch.time = data;
2649 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2650
2651 /* we verify if the enable bit is set... */
2652 if (!(data & 1))
2653 break;
2654
2655 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2656 &vcpu->arch.pv_time, data & ~1ULL,
2657 sizeof(struct pvclock_vcpu_time_info)))
2658 vcpu->arch.pv_time_enabled = false;
2659 else
2660 vcpu->arch.pv_time_enabled = true;
2661
2662 break;
2663 }
2664 case MSR_KVM_ASYNC_PF_EN:
2665 if (kvm_pv_enable_async_pf(vcpu, data))
2666 return 1;
2667 break;
2668 case MSR_KVM_STEAL_TIME:
2669
2670 if (unlikely(!sched_info_on()))
2671 return 1;
2672
2673 if (data & KVM_STEAL_RESERVED_MASK)
2674 return 1;
2675
2676 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2677 data & KVM_STEAL_VALID_BITS,
2678 sizeof(struct kvm_steal_time)))
2679 return 1;
2680
2681 vcpu->arch.st.msr_val = data;
2682
2683 if (!(data & KVM_MSR_ENABLED))
2684 break;
2685
2686 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2687
2688 break;
2689 case MSR_KVM_PV_EOI_EN:
2690 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2691 return 1;
2692 break;
2693
2694 case MSR_KVM_POLL_CONTROL:
2695 /* only enable bit supported */
2696 if (data & (-1ULL << 1))
2697 return 1;
2698
2699 vcpu->arch.msr_kvm_poll_control = data;
2700 break;
2701
2702 case MSR_IA32_MCG_CTL:
2703 case MSR_IA32_MCG_STATUS:
2704 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2705 return set_msr_mce(vcpu, msr_info);
2706
2707 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2708 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2709 pr = true; /* fall through */
2710 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2711 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2712 if (kvm_pmu_is_valid_msr(vcpu, msr))
2713 return kvm_pmu_set_msr(vcpu, msr_info);
2714
2715 if (pr || data != 0)
2716 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2717 "0x%x data 0x%llx\n", msr, data);
2718 break;
2719 case MSR_K7_CLK_CTL:
2720 /*
2721 * Ignore all writes to this no longer documented MSR.
2722 * Writes are only relevant for old K7 processors,
2723 * all pre-dating SVM, but a recommended workaround from
2724 * AMD for these chips. It is possible to specify the
2725 * affected processor models on the command line, hence
2726 * the need to ignore the workaround.
2727 */
2728 break;
2729 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2730 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2731 case HV_X64_MSR_CRASH_CTL:
2732 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2733 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2734 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2735 case HV_X64_MSR_TSC_EMULATION_STATUS:
2736 return kvm_hv_set_msr_common(vcpu, msr, data,
2737 msr_info->host_initiated);
2738 case MSR_IA32_BBL_CR_CTL3:
2739 /* Drop writes to this legacy MSR -- see rdmsr
2740 * counterpart for further detail.
2741 */
2742 if (report_ignored_msrs)
2743 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2744 msr, data);
2745 break;
2746 case MSR_AMD64_OSVW_ID_LENGTH:
2747 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2748 return 1;
2749 vcpu->arch.osvw.length = data;
2750 break;
2751 case MSR_AMD64_OSVW_STATUS:
2752 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2753 return 1;
2754 vcpu->arch.osvw.status = data;
2755 break;
2756 case MSR_PLATFORM_INFO:
2757 if (!msr_info->host_initiated ||
2758 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2759 cpuid_fault_enabled(vcpu)))
2760 return 1;
2761 vcpu->arch.msr_platform_info = data;
2762 break;
2763 case MSR_MISC_FEATURES_ENABLES:
2764 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2765 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2766 !supports_cpuid_fault(vcpu)))
2767 return 1;
2768 vcpu->arch.msr_misc_features_enables = data;
2769 break;
2770 default:
2771 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2772 return xen_hvm_config(vcpu, data);
2773 if (kvm_pmu_is_valid_msr(vcpu, msr))
2774 return kvm_pmu_set_msr(vcpu, msr_info);
2775 if (!ignore_msrs) {
2776 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2777 msr, data);
2778 return 1;
2779 } else {
2780 if (report_ignored_msrs)
2781 vcpu_unimpl(vcpu,
2782 "ignored wrmsr: 0x%x data 0x%llx\n",
2783 msr, data);
2784 break;
2785 }
2786 }
2787 return 0;
2788}
2789EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2790
2791static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
2792{
2793 u64 data;
2794 u64 mcg_cap = vcpu->arch.mcg_cap;
2795 unsigned bank_num = mcg_cap & 0xff;
2796
2797 switch (msr) {
2798 case MSR_IA32_P5_MC_ADDR:
2799 case MSR_IA32_P5_MC_TYPE:
2800 data = 0;
2801 break;
2802 case MSR_IA32_MCG_CAP:
2803 data = vcpu->arch.mcg_cap;
2804 break;
2805 case MSR_IA32_MCG_CTL:
2806 if (!(mcg_cap & MCG_CTL_P) && !host)
2807 return 1;
2808 data = vcpu->arch.mcg_ctl;
2809 break;
2810 case MSR_IA32_MCG_STATUS:
2811 data = vcpu->arch.mcg_status;
2812 break;
2813 default:
2814 if (msr >= MSR_IA32_MC0_CTL &&
2815 msr < MSR_IA32_MCx_CTL(bank_num)) {
2816 u32 offset = msr - MSR_IA32_MC0_CTL;
2817 data = vcpu->arch.mce_banks[offset];
2818 break;
2819 }
2820 return 1;
2821 }
2822 *pdata = data;
2823 return 0;
2824}
2825
2826int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2827{
2828 switch (msr_info->index) {
2829 case MSR_IA32_PLATFORM_ID:
2830 case MSR_IA32_EBL_CR_POWERON:
2831 case MSR_IA32_DEBUGCTLMSR:
2832 case MSR_IA32_LASTBRANCHFROMIP:
2833 case MSR_IA32_LASTBRANCHTOIP:
2834 case MSR_IA32_LASTINTFROMIP:
2835 case MSR_IA32_LASTINTTOIP:
2836 case MSR_K8_SYSCFG:
2837 case MSR_K8_TSEG_ADDR:
2838 case MSR_K8_TSEG_MASK:
2839 case MSR_VM_HSAVE_PA:
2840 case MSR_K8_INT_PENDING_MSG:
2841 case MSR_AMD64_NB_CFG:
2842 case MSR_FAM10H_MMIO_CONF_BASE:
2843 case MSR_AMD64_BU_CFG2:
2844 case MSR_IA32_PERF_CTL:
2845 case MSR_AMD64_DC_CFG:
2846 case MSR_F15H_EX_CFG:
2847 msr_info->data = 0;
2848 break;
2849 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
2850 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2851 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2852 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2853 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2854 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2855 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2856 msr_info->data = 0;
2857 break;
2858 case MSR_IA32_UCODE_REV:
2859 msr_info->data = vcpu->arch.microcode_version;
2860 break;
2861 case MSR_IA32_ARCH_CAPABILITIES:
2862 if (!msr_info->host_initiated &&
2863 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
2864 return 1;
2865 msr_info->data = vcpu->arch.arch_capabilities;
2866 break;
2867 case MSR_IA32_POWER_CTL:
2868 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
2869 break;
2870 case MSR_IA32_TSC:
2871 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2872 break;
2873 case MSR_MTRRcap:
2874 case 0x200 ... 0x2ff:
2875 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2876 case 0xcd: /* fsb frequency */
2877 msr_info->data = 3;
2878 break;
2879 /*
2880 * MSR_EBC_FREQUENCY_ID
2881 * Conservative value valid for even the basic CPU models.
2882 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2883 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2884 * and 266MHz for model 3, or 4. Set Core Clock
2885 * Frequency to System Bus Frequency Ratio to 1 (bits
2886 * 31:24) even though these are only valid for CPU
2887 * models > 2, however guests may end up dividing or
2888 * multiplying by zero otherwise.
2889 */
2890 case MSR_EBC_FREQUENCY_ID:
2891 msr_info->data = 1 << 24;
2892 break;
2893 case MSR_IA32_APICBASE:
2894 msr_info->data = kvm_get_apic_base(vcpu);
2895 break;
2896 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2897 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2898 break;
2899 case MSR_IA32_TSCDEADLINE:
2900 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2901 break;
2902 case MSR_IA32_TSC_ADJUST:
2903 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2904 break;
2905 case MSR_IA32_MISC_ENABLE:
2906 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2907 break;
2908 case MSR_IA32_SMBASE:
2909 if (!msr_info->host_initiated)
2910 return 1;
2911 msr_info->data = vcpu->arch.smbase;
2912 break;
2913 case MSR_SMI_COUNT:
2914 msr_info->data = vcpu->arch.smi_count;
2915 break;
2916 case MSR_IA32_PERF_STATUS:
2917 /* TSC increment by tick */
2918 msr_info->data = 1000ULL;
2919 /* CPU multiplier */
2920 msr_info->data |= (((uint64_t)4ULL) << 40);
2921 break;
2922 case MSR_EFER:
2923 msr_info->data = vcpu->arch.efer;
2924 break;
2925 case MSR_KVM_WALL_CLOCK:
2926 case MSR_KVM_WALL_CLOCK_NEW:
2927 msr_info->data = vcpu->kvm->arch.wall_clock;
2928 break;
2929 case MSR_KVM_SYSTEM_TIME:
2930 case MSR_KVM_SYSTEM_TIME_NEW:
2931 msr_info->data = vcpu->arch.time;
2932 break;
2933 case MSR_KVM_ASYNC_PF_EN:
2934 msr_info->data = vcpu->arch.apf.msr_val;
2935 break;
2936 case MSR_KVM_STEAL_TIME:
2937 msr_info->data = vcpu->arch.st.msr_val;
2938 break;
2939 case MSR_KVM_PV_EOI_EN:
2940 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2941 break;
2942 case MSR_KVM_POLL_CONTROL:
2943 msr_info->data = vcpu->arch.msr_kvm_poll_control;
2944 break;
2945 case MSR_IA32_P5_MC_ADDR:
2946 case MSR_IA32_P5_MC_TYPE:
2947 case MSR_IA32_MCG_CAP:
2948 case MSR_IA32_MCG_CTL:
2949 case MSR_IA32_MCG_STATUS:
2950 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2951 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2952 msr_info->host_initiated);
2953 case MSR_K7_CLK_CTL:
2954 /*
2955 * Provide expected ramp-up count for K7. All other
2956 * are set to zero, indicating minimum divisors for
2957 * every field.
2958 *
2959 * This prevents guest kernels on AMD host with CPU
2960 * type 6, model 8 and higher from exploding due to
2961 * the rdmsr failing.
2962 */
2963 msr_info->data = 0x20000000;
2964 break;
2965 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2966 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2967 case HV_X64_MSR_CRASH_CTL:
2968 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2969 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2970 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2971 case HV_X64_MSR_TSC_EMULATION_STATUS:
2972 return kvm_hv_get_msr_common(vcpu,
2973 msr_info->index, &msr_info->data,
2974 msr_info->host_initiated);
2975 break;
2976 case MSR_IA32_BBL_CR_CTL3:
2977 /* This legacy MSR exists but isn't fully documented in current
2978 * silicon. It is however accessed by winxp in very narrow
2979 * scenarios where it sets bit #19, itself documented as
2980 * a "reserved" bit. Best effort attempt to source coherent
2981 * read data here should the balance of the register be
2982 * interpreted by the guest:
2983 *
2984 * L2 cache control register 3: 64GB range, 256KB size,
2985 * enabled, latency 0x1, configured
2986 */
2987 msr_info->data = 0xbe702111;
2988 break;
2989 case MSR_AMD64_OSVW_ID_LENGTH:
2990 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2991 return 1;
2992 msr_info->data = vcpu->arch.osvw.length;
2993 break;
2994 case MSR_AMD64_OSVW_STATUS:
2995 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2996 return 1;
2997 msr_info->data = vcpu->arch.osvw.status;
2998 break;
2999 case MSR_PLATFORM_INFO:
3000 if (!msr_info->host_initiated &&
3001 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3002 return 1;
3003 msr_info->data = vcpu->arch.msr_platform_info;
3004 break;
3005 case MSR_MISC_FEATURES_ENABLES:
3006 msr_info->data = vcpu->arch.msr_misc_features_enables;
3007 break;
3008 case MSR_K7_HWCR:
3009 msr_info->data = vcpu->arch.msr_hwcr;
3010 break;
3011 default:
3012 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3013 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3014 if (!ignore_msrs) {
3015 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
3016 msr_info->index);
3017 return 1;
3018 } else {
3019 if (report_ignored_msrs)
3020 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3021 msr_info->index);
3022 msr_info->data = 0;
3023 }
3024 break;
3025 }
3026 return 0;
3027}
3028EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3029
3030/*
3031 * Read or write a bunch of msrs. All parameters are kernel addresses.
3032 *
3033 * @return number of msrs set successfully.
3034 */
3035static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3036 struct kvm_msr_entry *entries,
3037 int (*do_msr)(struct kvm_vcpu *vcpu,
3038 unsigned index, u64 *data))
3039{
3040 int i;
3041
3042 for (i = 0; i < msrs->nmsrs; ++i)
3043 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3044 break;
3045
3046 return i;
3047}
3048
3049/*
3050 * Read or write a bunch of msrs. Parameters are user addresses.
3051 *
3052 * @return number of msrs set successfully.
3053 */
3054static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3055 int (*do_msr)(struct kvm_vcpu *vcpu,
3056 unsigned index, u64 *data),
3057 int writeback)
3058{
3059 struct kvm_msrs msrs;
3060 struct kvm_msr_entry *entries;
3061 int r, n;
3062 unsigned size;
3063
3064 r = -EFAULT;
3065 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3066 goto out;
3067
3068 r = -E2BIG;
3069 if (msrs.nmsrs >= MAX_IO_MSRS)
3070 goto out;
3071
3072 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3073 entries = memdup_user(user_msrs->entries, size);
3074 if (IS_ERR(entries)) {
3075 r = PTR_ERR(entries);
3076 goto out;
3077 }
3078
3079 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3080 if (r < 0)
3081 goto out_free;
3082
3083 r = -EFAULT;
3084 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3085 goto out_free;
3086
3087 r = n;
3088
3089out_free:
3090 kfree(entries);
3091out:
3092 return r;
3093}
3094
3095static inline bool kvm_can_mwait_in_guest(void)
3096{
3097 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3098 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3099 boot_cpu_has(X86_FEATURE_ARAT);
3100}
3101
3102int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3103{
3104 int r = 0;
3105
3106 switch (ext) {
3107 case KVM_CAP_IRQCHIP:
3108 case KVM_CAP_HLT:
3109 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3110 case KVM_CAP_SET_TSS_ADDR:
3111 case KVM_CAP_EXT_CPUID:
3112 case KVM_CAP_EXT_EMUL_CPUID:
3113 case KVM_CAP_CLOCKSOURCE:
3114 case KVM_CAP_PIT:
3115 case KVM_CAP_NOP_IO_DELAY:
3116 case KVM_CAP_MP_STATE:
3117 case KVM_CAP_SYNC_MMU:
3118 case KVM_CAP_USER_NMI:
3119 case KVM_CAP_REINJECT_CONTROL:
3120 case KVM_CAP_IRQ_INJECT_STATUS:
3121 case KVM_CAP_IOEVENTFD:
3122 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3123 case KVM_CAP_PIT2:
3124 case KVM_CAP_PIT_STATE2:
3125 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3126 case KVM_CAP_XEN_HVM:
3127 case KVM_CAP_VCPU_EVENTS:
3128 case KVM_CAP_HYPERV:
3129 case KVM_CAP_HYPERV_VAPIC:
3130 case KVM_CAP_HYPERV_SPIN:
3131 case KVM_CAP_HYPERV_SYNIC:
3132 case KVM_CAP_HYPERV_SYNIC2:
3133 case KVM_CAP_HYPERV_VP_INDEX:
3134 case KVM_CAP_HYPERV_EVENTFD:
3135 case KVM_CAP_HYPERV_TLBFLUSH:
3136 case KVM_CAP_HYPERV_SEND_IPI:
3137 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3138 case KVM_CAP_HYPERV_CPUID:
3139 case KVM_CAP_PCI_SEGMENT:
3140 case KVM_CAP_DEBUGREGS:
3141 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3142 case KVM_CAP_XSAVE:
3143 case KVM_CAP_ASYNC_PF:
3144 case KVM_CAP_GET_TSC_KHZ:
3145 case KVM_CAP_KVMCLOCK_CTRL:
3146 case KVM_CAP_READONLY_MEM:
3147 case KVM_CAP_HYPERV_TIME:
3148 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3149 case KVM_CAP_TSC_DEADLINE_TIMER:
3150 case KVM_CAP_DISABLE_QUIRKS:
3151 case KVM_CAP_SET_BOOT_CPU_ID:
3152 case KVM_CAP_SPLIT_IRQCHIP:
3153 case KVM_CAP_IMMEDIATE_EXIT:
3154 case KVM_CAP_PMU_EVENT_FILTER:
3155 case KVM_CAP_GET_MSR_FEATURES:
3156 case KVM_CAP_MSR_PLATFORM_INFO:
3157 case KVM_CAP_EXCEPTION_PAYLOAD:
3158 r = 1;
3159 break;
3160 case KVM_CAP_SYNC_REGS:
3161 r = KVM_SYNC_X86_VALID_FIELDS;
3162 break;
3163 case KVM_CAP_ADJUST_CLOCK:
3164 r = KVM_CLOCK_TSC_STABLE;
3165 break;
3166 case KVM_CAP_X86_DISABLE_EXITS:
3167 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3168 KVM_X86_DISABLE_EXITS_CSTATE;
3169 if(kvm_can_mwait_in_guest())
3170 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3171 break;
3172 case KVM_CAP_X86_SMM:
3173 /* SMBASE is usually relocated above 1M on modern chipsets,
3174 * and SMM handlers might indeed rely on 4G segment limits,
3175 * so do not report SMM to be available if real mode is
3176 * emulated via vm86 mode. Still, do not go to great lengths
3177 * to avoid userspace's usage of the feature, because it is a
3178 * fringe case that is not enabled except via specific settings
3179 * of the module parameters.
3180 */
3181 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
3182 break;
3183 case KVM_CAP_VAPIC:
3184 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3185 break;
3186 case KVM_CAP_NR_VCPUS:
3187 r = KVM_SOFT_MAX_VCPUS;
3188 break;
3189 case KVM_CAP_MAX_VCPUS:
3190 r = KVM_MAX_VCPUS;
3191 break;
3192 case KVM_CAP_MAX_VCPU_ID:
3193 r = KVM_MAX_VCPU_ID;
3194 break;
3195 case KVM_CAP_PV_MMU: /* obsolete */
3196 r = 0;
3197 break;
3198 case KVM_CAP_MCE:
3199 r = KVM_MAX_MCE_BANKS;
3200 break;
3201 case KVM_CAP_XCRS:
3202 r = boot_cpu_has(X86_FEATURE_XSAVE);
3203 break;
3204 case KVM_CAP_TSC_CONTROL:
3205 r = kvm_has_tsc_control;
3206 break;
3207 case KVM_CAP_X2APIC_API:
3208 r = KVM_X2APIC_API_VALID_FLAGS;
3209 break;
3210 case KVM_CAP_NESTED_STATE:
3211 r = kvm_x86_ops->get_nested_state ?
3212 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
3213 break;
3214 default:
3215 break;
3216 }
3217 return r;
3218
3219}
3220
3221long kvm_arch_dev_ioctl(struct file *filp,
3222 unsigned int ioctl, unsigned long arg)
3223{
3224 void __user *argp = (void __user *)arg;
3225 long r;
3226
3227 switch (ioctl) {
3228 case KVM_GET_MSR_INDEX_LIST: {
3229 struct kvm_msr_list __user *user_msr_list = argp;
3230 struct kvm_msr_list msr_list;
3231 unsigned n;
3232
3233 r = -EFAULT;
3234 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3235 goto out;
3236 n = msr_list.nmsrs;
3237 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3238 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3239 goto out;
3240 r = -E2BIG;
3241 if (n < msr_list.nmsrs)
3242 goto out;
3243 r = -EFAULT;
3244 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3245 num_msrs_to_save * sizeof(u32)))
3246 goto out;
3247 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3248 &emulated_msrs,
3249 num_emulated_msrs * sizeof(u32)))
3250 goto out;
3251 r = 0;
3252 break;
3253 }
3254 case KVM_GET_SUPPORTED_CPUID:
3255 case KVM_GET_EMULATED_CPUID: {
3256 struct kvm_cpuid2 __user *cpuid_arg = argp;
3257 struct kvm_cpuid2 cpuid;
3258
3259 r = -EFAULT;
3260 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3261 goto out;
3262
3263 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3264 ioctl);
3265 if (r)
3266 goto out;
3267
3268 r = -EFAULT;
3269 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3270 goto out;
3271 r = 0;
3272 break;
3273 }
3274 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
3275 r = -EFAULT;
3276 if (copy_to_user(argp, &kvm_mce_cap_supported,
3277 sizeof(kvm_mce_cap_supported)))
3278 goto out;
3279 r = 0;
3280 break;
3281 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3282 struct kvm_msr_list __user *user_msr_list = argp;
3283 struct kvm_msr_list msr_list;
3284 unsigned int n;
3285
3286 r = -EFAULT;
3287 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3288 goto out;
3289 n = msr_list.nmsrs;
3290 msr_list.nmsrs = num_msr_based_features;
3291 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3292 goto out;
3293 r = -E2BIG;
3294 if (n < msr_list.nmsrs)
3295 goto out;
3296 r = -EFAULT;
3297 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3298 num_msr_based_features * sizeof(u32)))
3299 goto out;
3300 r = 0;
3301 break;
3302 }
3303 case KVM_GET_MSRS:
3304 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3305 break;
3306 }
3307 default:
3308 r = -EINVAL;
3309 }
3310out:
3311 return r;
3312}
3313
3314static void wbinvd_ipi(void *garbage)
3315{
3316 wbinvd();
3317}
3318
3319static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3320{
3321 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3322}
3323
3324void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3325{
3326 /* Address WBINVD may be executed by guest */
3327 if (need_emulate_wbinvd(vcpu)) {
3328 if (kvm_x86_ops->has_wbinvd_exit())
3329 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3330 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3331 smp_call_function_single(vcpu->cpu,
3332 wbinvd_ipi, NULL, 1);
3333 }
3334
3335 kvm_x86_ops->vcpu_load(vcpu, cpu);
3336
3337 fpregs_assert_state_consistent();
3338 if (test_thread_flag(TIF_NEED_FPU_LOAD))
3339 switch_fpu_return();
3340
3341 /* Apply any externally detected TSC adjustments (due to suspend) */
3342 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3343 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3344 vcpu->arch.tsc_offset_adjustment = 0;
3345 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3346 }
3347
3348 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3349 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3350 rdtsc() - vcpu->arch.last_host_tsc;
3351 if (tsc_delta < 0)
3352 mark_tsc_unstable("KVM discovered backwards TSC");
3353
3354 if (kvm_check_tsc_unstable()) {
3355 u64 offset = kvm_compute_tsc_offset(vcpu,
3356 vcpu->arch.last_guest_tsc);
3357 kvm_vcpu_write_tsc_offset(vcpu, offset);
3358 vcpu->arch.tsc_catchup = 1;
3359 }
3360
3361 if (kvm_lapic_hv_timer_in_use(vcpu))
3362 kvm_lapic_restart_hv_timer(vcpu);
3363
3364 /*
3365 * On a host with synchronized TSC, there is no need to update
3366 * kvmclock on vcpu->cpu migration
3367 */
3368 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3369 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3370 if (vcpu->cpu != cpu)
3371 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3372 vcpu->cpu = cpu;
3373 }
3374
3375 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3376}
3377
3378static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3379{
3380 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3381 return;
3382
3383 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
3384
3385 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
3386 &vcpu->arch.st.steal.preempted,
3387 offsetof(struct kvm_steal_time, preempted),
3388 sizeof(vcpu->arch.st.steal.preempted));
3389}
3390
3391void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3392{
3393 int idx;
3394
3395 if (vcpu->preempted)
3396 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3397
3398 /*
3399 * Disable page faults because we're in atomic context here.
3400 * kvm_write_guest_offset_cached() would call might_fault()
3401 * that relies on pagefault_disable() to tell if there's a
3402 * bug. NOTE: the write to guest memory may not go through if
3403 * during postcopy live migration or if there's heavy guest
3404 * paging.
3405 */
3406 pagefault_disable();
3407 /*
3408 * kvm_memslots() will be called by
3409 * kvm_write_guest_offset_cached() so take the srcu lock.
3410 */
3411 idx = srcu_read_lock(&vcpu->kvm->srcu);
3412 kvm_steal_time_set_preempted(vcpu);
3413 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3414 pagefault_enable();
3415 kvm_x86_ops->vcpu_put(vcpu);
3416 vcpu->arch.last_host_tsc = rdtsc();
3417 /*
3418 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3419 * on every vmexit, but if not, we might have a stale dr6 from the
3420 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3421 */
3422 set_debugreg(0, 6);
3423}
3424
3425static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3426 struct kvm_lapic_state *s)
3427{
3428 if (vcpu->arch.apicv_active)
3429 kvm_x86_ops->sync_pir_to_irr(vcpu);
3430
3431 return kvm_apic_get_state(vcpu, s);
3432}
3433
3434static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3435 struct kvm_lapic_state *s)
3436{
3437 int r;
3438
3439 r = kvm_apic_set_state(vcpu, s);
3440 if (r)
3441 return r;
3442 update_cr8_intercept(vcpu);
3443
3444 return 0;
3445}
3446
3447static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3448{
3449 return (!lapic_in_kernel(vcpu) ||
3450 kvm_apic_accept_pic_intr(vcpu));
3451}
3452
3453/*
3454 * if userspace requested an interrupt window, check that the
3455 * interrupt window is open.
3456 *
3457 * No need to exit to userspace if we already have an interrupt queued.
3458 */
3459static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3460{
3461 return kvm_arch_interrupt_allowed(vcpu) &&
3462 !kvm_cpu_has_interrupt(vcpu) &&
3463 !kvm_event_needs_reinjection(vcpu) &&
3464 kvm_cpu_accept_dm_intr(vcpu);
3465}
3466
3467static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3468 struct kvm_interrupt *irq)
3469{
3470 if (irq->irq >= KVM_NR_INTERRUPTS)
3471 return -EINVAL;
3472
3473 if (!irqchip_in_kernel(vcpu->kvm)) {
3474 kvm_queue_interrupt(vcpu, irq->irq, false);
3475 kvm_make_request(KVM_REQ_EVENT, vcpu);
3476 return 0;
3477 }
3478
3479 /*
3480 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3481 * fail for in-kernel 8259.
3482 */
3483 if (pic_in_kernel(vcpu->kvm))
3484 return -ENXIO;
3485
3486 if (vcpu->arch.pending_external_vector != -1)
3487 return -EEXIST;
3488
3489 vcpu->arch.pending_external_vector = irq->irq;
3490 kvm_make_request(KVM_REQ_EVENT, vcpu);
3491 return 0;
3492}
3493
3494static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3495{
3496 kvm_inject_nmi(vcpu);
3497
3498 return 0;
3499}
3500
3501static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3502{
3503 kvm_make_request(KVM_REQ_SMI, vcpu);
3504
3505 return 0;
3506}
3507
3508static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3509 struct kvm_tpr_access_ctl *tac)
3510{
3511 if (tac->flags)
3512 return -EINVAL;
3513 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3514 return 0;
3515}
3516
3517static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3518 u64 mcg_cap)
3519{
3520 int r;
3521 unsigned bank_num = mcg_cap & 0xff, bank;
3522
3523 r = -EINVAL;
3524 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3525 goto out;
3526 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3527 goto out;
3528 r = 0;
3529 vcpu->arch.mcg_cap = mcg_cap;
3530 /* Init IA32_MCG_CTL to all 1s */
3531 if (mcg_cap & MCG_CTL_P)
3532 vcpu->arch.mcg_ctl = ~(u64)0;
3533 /* Init IA32_MCi_CTL to all 1s */
3534 for (bank = 0; bank < bank_num; bank++)
3535 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3536
3537 kvm_x86_ops->setup_mce(vcpu);
3538out:
3539 return r;
3540}
3541
3542static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3543 struct kvm_x86_mce *mce)
3544{
3545 u64 mcg_cap = vcpu->arch.mcg_cap;
3546 unsigned bank_num = mcg_cap & 0xff;
3547 u64 *banks = vcpu->arch.mce_banks;
3548
3549 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3550 return -EINVAL;
3551 /*
3552 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3553 * reporting is disabled
3554 */
3555 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3556 vcpu->arch.mcg_ctl != ~(u64)0)
3557 return 0;
3558 banks += 4 * mce->bank;
3559 /*
3560 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3561 * reporting is disabled for the bank
3562 */
3563 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3564 return 0;
3565 if (mce->status & MCI_STATUS_UC) {
3566 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3567 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3568 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3569 return 0;
3570 }
3571 if (banks[1] & MCI_STATUS_VAL)
3572 mce->status |= MCI_STATUS_OVER;
3573 banks[2] = mce->addr;
3574 banks[3] = mce->misc;
3575 vcpu->arch.mcg_status = mce->mcg_status;
3576 banks[1] = mce->status;
3577 kvm_queue_exception(vcpu, MC_VECTOR);
3578 } else if (!(banks[1] & MCI_STATUS_VAL)
3579 || !(banks[1] & MCI_STATUS_UC)) {
3580 if (banks[1] & MCI_STATUS_VAL)
3581 mce->status |= MCI_STATUS_OVER;
3582 banks[2] = mce->addr;
3583 banks[3] = mce->misc;
3584 banks[1] = mce->status;
3585 } else
3586 banks[1] |= MCI_STATUS_OVER;
3587 return 0;
3588}
3589
3590static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3591 struct kvm_vcpu_events *events)
3592{
3593 process_nmi(vcpu);
3594
3595 /*
3596 * The API doesn't provide the instruction length for software
3597 * exceptions, so don't report them. As long as the guest RIP
3598 * isn't advanced, we should expect to encounter the exception
3599 * again.
3600 */
3601 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3602 events->exception.injected = 0;
3603 events->exception.pending = 0;
3604 } else {
3605 events->exception.injected = vcpu->arch.exception.injected;
3606 events->exception.pending = vcpu->arch.exception.pending;
3607 /*
3608 * For ABI compatibility, deliberately conflate
3609 * pending and injected exceptions when
3610 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3611 */
3612 if (!vcpu->kvm->arch.exception_payload_enabled)
3613 events->exception.injected |=
3614 vcpu->arch.exception.pending;
3615 }
3616 events->exception.nr = vcpu->arch.exception.nr;
3617 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3618 events->exception.error_code = vcpu->arch.exception.error_code;
3619 events->exception_has_payload = vcpu->arch.exception.has_payload;
3620 events->exception_payload = vcpu->arch.exception.payload;
3621
3622 events->interrupt.injected =
3623 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3624 events->interrupt.nr = vcpu->arch.interrupt.nr;
3625 events->interrupt.soft = 0;
3626 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3627
3628 events->nmi.injected = vcpu->arch.nmi_injected;
3629 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3630 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3631 events->nmi.pad = 0;
3632
3633 events->sipi_vector = 0; /* never valid when reporting to user space */
3634
3635 events->smi.smm = is_smm(vcpu);
3636 events->smi.pending = vcpu->arch.smi_pending;
3637 events->smi.smm_inside_nmi =
3638 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3639 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3640
3641 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3642 | KVM_VCPUEVENT_VALID_SHADOW
3643 | KVM_VCPUEVENT_VALID_SMM);
3644 if (vcpu->kvm->arch.exception_payload_enabled)
3645 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3646
3647 memset(&events->reserved, 0, sizeof(events->reserved));
3648}
3649
3650static void kvm_smm_changed(struct kvm_vcpu *vcpu);
3651
3652static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3653 struct kvm_vcpu_events *events)
3654{
3655 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3656 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3657 | KVM_VCPUEVENT_VALID_SHADOW
3658 | KVM_VCPUEVENT_VALID_SMM
3659 | KVM_VCPUEVENT_VALID_PAYLOAD))
3660 return -EINVAL;
3661
3662 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3663 if (!vcpu->kvm->arch.exception_payload_enabled)
3664 return -EINVAL;
3665 if (events->exception.pending)
3666 events->exception.injected = 0;
3667 else
3668 events->exception_has_payload = 0;
3669 } else {
3670 events->exception.pending = 0;
3671 events->exception_has_payload = 0;
3672 }
3673
3674 if ((events->exception.injected || events->exception.pending) &&
3675 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3676 return -EINVAL;
3677
3678 /* INITs are latched while in SMM */
3679 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3680 (events->smi.smm || events->smi.pending) &&
3681 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3682 return -EINVAL;
3683
3684 process_nmi(vcpu);
3685 vcpu->arch.exception.injected = events->exception.injected;
3686 vcpu->arch.exception.pending = events->exception.pending;
3687 vcpu->arch.exception.nr = events->exception.nr;
3688 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3689 vcpu->arch.exception.error_code = events->exception.error_code;
3690 vcpu->arch.exception.has_payload = events->exception_has_payload;
3691 vcpu->arch.exception.payload = events->exception_payload;
3692
3693 vcpu->arch.interrupt.injected = events->interrupt.injected;
3694 vcpu->arch.interrupt.nr = events->interrupt.nr;
3695 vcpu->arch.interrupt.soft = events->interrupt.soft;
3696 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3697 kvm_x86_ops->set_interrupt_shadow(vcpu,
3698 events->interrupt.shadow);
3699
3700 vcpu->arch.nmi_injected = events->nmi.injected;
3701 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3702 vcpu->arch.nmi_pending = events->nmi.pending;
3703 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3704
3705 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3706 lapic_in_kernel(vcpu))
3707 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3708
3709 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3710 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3711 if (events->smi.smm)
3712 vcpu->arch.hflags |= HF_SMM_MASK;
3713 else
3714 vcpu->arch.hflags &= ~HF_SMM_MASK;
3715 kvm_smm_changed(vcpu);
3716 }
3717
3718 vcpu->arch.smi_pending = events->smi.pending;
3719
3720 if (events->smi.smm) {
3721 if (events->smi.smm_inside_nmi)
3722 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3723 else
3724 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3725 if (lapic_in_kernel(vcpu)) {
3726 if (events->smi.latched_init)
3727 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3728 else
3729 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3730 }
3731 }
3732 }
3733
3734 kvm_make_request(KVM_REQ_EVENT, vcpu);
3735
3736 return 0;
3737}
3738
3739static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3740 struct kvm_debugregs *dbgregs)
3741{
3742 unsigned long val;
3743
3744 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3745 kvm_get_dr(vcpu, 6, &val);
3746 dbgregs->dr6 = val;
3747 dbgregs->dr7 = vcpu->arch.dr7;
3748 dbgregs->flags = 0;
3749 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3750}
3751
3752static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3753 struct kvm_debugregs *dbgregs)
3754{
3755 if (dbgregs->flags)
3756 return -EINVAL;
3757
3758 if (dbgregs->dr6 & ~0xffffffffull)
3759 return -EINVAL;
3760 if (dbgregs->dr7 & ~0xffffffffull)
3761 return -EINVAL;
3762
3763 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3764 kvm_update_dr0123(vcpu);
3765 vcpu->arch.dr6 = dbgregs->dr6;
3766 kvm_update_dr6(vcpu);
3767 vcpu->arch.dr7 = dbgregs->dr7;
3768 kvm_update_dr7(vcpu);
3769
3770 return 0;
3771}
3772
3773#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3774
3775static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3776{
3777 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3778 u64 xstate_bv = xsave->header.xfeatures;
3779 u64 valid;
3780
3781 /*
3782 * Copy legacy XSAVE area, to avoid complications with CPUID
3783 * leaves 0 and 1 in the loop below.
3784 */
3785 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3786
3787 /* Set XSTATE_BV */
3788 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3789 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3790
3791 /*
3792 * Copy each region from the possibly compacted offset to the
3793 * non-compacted offset.
3794 */
3795 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3796 while (valid) {
3797 u64 xfeature_mask = valid & -valid;
3798 int xfeature_nr = fls64(xfeature_mask) - 1;
3799 void *src = get_xsave_addr(xsave, xfeature_nr);
3800
3801 if (src) {
3802 u32 size, offset, ecx, edx;
3803 cpuid_count(XSTATE_CPUID, xfeature_nr,
3804 &size, &offset, &ecx, &edx);
3805 if (xfeature_nr == XFEATURE_PKRU)
3806 memcpy(dest + offset, &vcpu->arch.pkru,
3807 sizeof(vcpu->arch.pkru));
3808 else
3809 memcpy(dest + offset, src, size);
3810
3811 }
3812
3813 valid -= xfeature_mask;
3814 }
3815}
3816
3817static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3818{
3819 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3820 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3821 u64 valid;
3822
3823 /*
3824 * Copy legacy XSAVE area, to avoid complications with CPUID
3825 * leaves 0 and 1 in the loop below.
3826 */
3827 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3828
3829 /* Set XSTATE_BV and possibly XCOMP_BV. */
3830 xsave->header.xfeatures = xstate_bv;
3831 if (boot_cpu_has(X86_FEATURE_XSAVES))
3832 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3833
3834 /*
3835 * Copy each region from the non-compacted offset to the
3836 * possibly compacted offset.
3837 */
3838 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3839 while (valid) {
3840 u64 xfeature_mask = valid & -valid;
3841 int xfeature_nr = fls64(xfeature_mask) - 1;
3842 void *dest = get_xsave_addr(xsave, xfeature_nr);
3843
3844 if (dest) {
3845 u32 size, offset, ecx, edx;
3846 cpuid_count(XSTATE_CPUID, xfeature_nr,
3847 &size, &offset, &ecx, &edx);
3848 if (xfeature_nr == XFEATURE_PKRU)
3849 memcpy(&vcpu->arch.pkru, src + offset,
3850 sizeof(vcpu->arch.pkru));
3851 else
3852 memcpy(dest, src + offset, size);
3853 }
3854
3855 valid -= xfeature_mask;
3856 }
3857}
3858
3859static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3860 struct kvm_xsave *guest_xsave)
3861{
3862 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3863 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3864 fill_xsave((u8 *) guest_xsave->region, vcpu);
3865 } else {
3866 memcpy(guest_xsave->region,
3867 &vcpu->arch.guest_fpu->state.fxsave,
3868 sizeof(struct fxregs_state));
3869 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3870 XFEATURE_MASK_FPSSE;
3871 }
3872}
3873
3874#define XSAVE_MXCSR_OFFSET 24
3875
3876static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3877 struct kvm_xsave *guest_xsave)
3878{
3879 u64 xstate_bv =
3880 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3881 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3882
3883 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3884 /*
3885 * Here we allow setting states that are not present in
3886 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3887 * with old userspace.
3888 */
3889 if (xstate_bv & ~kvm_supported_xcr0() ||
3890 mxcsr & ~mxcsr_feature_mask)
3891 return -EINVAL;
3892 load_xsave(vcpu, (u8 *)guest_xsave->region);
3893 } else {
3894 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3895 mxcsr & ~mxcsr_feature_mask)
3896 return -EINVAL;
3897 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
3898 guest_xsave->region, sizeof(struct fxregs_state));
3899 }
3900 return 0;
3901}
3902
3903static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3904 struct kvm_xcrs *guest_xcrs)
3905{
3906 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3907 guest_xcrs->nr_xcrs = 0;
3908 return;
3909 }
3910
3911 guest_xcrs->nr_xcrs = 1;
3912 guest_xcrs->flags = 0;
3913 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3914 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3915}
3916
3917static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3918 struct kvm_xcrs *guest_xcrs)
3919{
3920 int i, r = 0;
3921
3922 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3923 return -EINVAL;
3924
3925 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3926 return -EINVAL;
3927
3928 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3929 /* Only support XCR0 currently */
3930 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3931 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3932 guest_xcrs->xcrs[i].value);
3933 break;
3934 }
3935 if (r)
3936 r = -EINVAL;
3937 return r;
3938}
3939
3940/*
3941 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3942 * stopped by the hypervisor. This function will be called from the host only.
3943 * EINVAL is returned when the host attempts to set the flag for a guest that
3944 * does not support pv clocks.
3945 */
3946static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3947{
3948 if (!vcpu->arch.pv_time_enabled)
3949 return -EINVAL;
3950 vcpu->arch.pvclock_set_guest_stopped_request = true;
3951 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3952 return 0;
3953}
3954
3955static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3956 struct kvm_enable_cap *cap)
3957{
3958 int r;
3959 uint16_t vmcs_version;
3960 void __user *user_ptr;
3961
3962 if (cap->flags)
3963 return -EINVAL;
3964
3965 switch (cap->cap) {
3966 case KVM_CAP_HYPERV_SYNIC2:
3967 if (cap->args[0])
3968 return -EINVAL;
3969 /* fall through */
3970
3971 case KVM_CAP_HYPERV_SYNIC:
3972 if (!irqchip_in_kernel(vcpu->kvm))
3973 return -EINVAL;
3974 return kvm_hv_activate_synic(vcpu, cap->cap ==
3975 KVM_CAP_HYPERV_SYNIC2);
3976 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3977 if (!kvm_x86_ops->nested_enable_evmcs)
3978 return -ENOTTY;
3979 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
3980 if (!r) {
3981 user_ptr = (void __user *)(uintptr_t)cap->args[0];
3982 if (copy_to_user(user_ptr, &vmcs_version,
3983 sizeof(vmcs_version)))
3984 r = -EFAULT;
3985 }
3986 return r;
3987
3988 default:
3989 return -EINVAL;
3990 }
3991}
3992
3993long kvm_arch_vcpu_ioctl(struct file *filp,
3994 unsigned int ioctl, unsigned long arg)
3995{
3996 struct kvm_vcpu *vcpu = filp->private_data;
3997 void __user *argp = (void __user *)arg;
3998 int r;
3999 union {
4000 struct kvm_lapic_state *lapic;
4001 struct kvm_xsave *xsave;
4002 struct kvm_xcrs *xcrs;
4003 void *buffer;
4004 } u;
4005
4006 vcpu_load(vcpu);
4007
4008 u.buffer = NULL;
4009 switch (ioctl) {
4010 case KVM_GET_LAPIC: {
4011 r = -EINVAL;
4012 if (!lapic_in_kernel(vcpu))
4013 goto out;
4014 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4015 GFP_KERNEL_ACCOUNT);
4016
4017 r = -ENOMEM;
4018 if (!u.lapic)
4019 goto out;
4020 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4021 if (r)
4022 goto out;
4023 r = -EFAULT;
4024 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4025 goto out;
4026 r = 0;
4027 break;
4028 }
4029 case KVM_SET_LAPIC: {
4030 r = -EINVAL;
4031 if (!lapic_in_kernel(vcpu))
4032 goto out;
4033 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4034 if (IS_ERR(u.lapic)) {
4035 r = PTR_ERR(u.lapic);
4036 goto out_nofree;
4037 }
4038
4039 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4040 break;
4041 }
4042 case KVM_INTERRUPT: {
4043 struct kvm_interrupt irq;
4044
4045 r = -EFAULT;
4046 if (copy_from_user(&irq, argp, sizeof(irq)))
4047 goto out;
4048 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4049 break;
4050 }
4051 case KVM_NMI: {
4052 r = kvm_vcpu_ioctl_nmi(vcpu);
4053 break;
4054 }
4055 case KVM_SMI: {
4056 r = kvm_vcpu_ioctl_smi(vcpu);
4057 break;
4058 }
4059 case KVM_SET_CPUID: {
4060 struct kvm_cpuid __user *cpuid_arg = argp;
4061 struct kvm_cpuid cpuid;
4062
4063 r = -EFAULT;
4064 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4065 goto out;
4066 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4067 break;
4068 }
4069 case KVM_SET_CPUID2: {
4070 struct kvm_cpuid2 __user *cpuid_arg = argp;
4071 struct kvm_cpuid2 cpuid;
4072
4073 r = -EFAULT;
4074 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4075 goto out;
4076 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4077 cpuid_arg->entries);
4078 break;
4079 }
4080 case KVM_GET_CPUID2: {
4081 struct kvm_cpuid2 __user *cpuid_arg = argp;
4082 struct kvm_cpuid2 cpuid;
4083
4084 r = -EFAULT;
4085 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4086 goto out;
4087 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4088 cpuid_arg->entries);
4089 if (r)
4090 goto out;
4091 r = -EFAULT;
4092 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4093 goto out;
4094 r = 0;
4095 break;
4096 }
4097 case KVM_GET_MSRS: {
4098 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4099 r = msr_io(vcpu, argp, do_get_msr, 1);
4100 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4101 break;
4102 }
4103 case KVM_SET_MSRS: {
4104 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4105 r = msr_io(vcpu, argp, do_set_msr, 0);
4106 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4107 break;
4108 }
4109 case KVM_TPR_ACCESS_REPORTING: {
4110 struct kvm_tpr_access_ctl tac;
4111
4112 r = -EFAULT;
4113 if (copy_from_user(&tac, argp, sizeof(tac)))
4114 goto out;
4115 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4116 if (r)
4117 goto out;
4118 r = -EFAULT;
4119 if (copy_to_user(argp, &tac, sizeof(tac)))
4120 goto out;
4121 r = 0;
4122 break;
4123 };
4124 case KVM_SET_VAPIC_ADDR: {
4125 struct kvm_vapic_addr va;
4126 int idx;
4127
4128 r = -EINVAL;
4129 if (!lapic_in_kernel(vcpu))
4130 goto out;
4131 r = -EFAULT;
4132 if (copy_from_user(&va, argp, sizeof(va)))
4133 goto out;
4134 idx = srcu_read_lock(&vcpu->kvm->srcu);
4135 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4136 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4137 break;
4138 }
4139 case KVM_X86_SETUP_MCE: {
4140 u64 mcg_cap;
4141
4142 r = -EFAULT;
4143 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4144 goto out;
4145 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4146 break;
4147 }
4148 case KVM_X86_SET_MCE: {
4149 struct kvm_x86_mce mce;
4150
4151 r = -EFAULT;
4152 if (copy_from_user(&mce, argp, sizeof(mce)))
4153 goto out;
4154 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4155 break;
4156 }
4157 case KVM_GET_VCPU_EVENTS: {
4158 struct kvm_vcpu_events events;
4159
4160 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4161
4162 r = -EFAULT;
4163 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4164 break;
4165 r = 0;
4166 break;
4167 }
4168 case KVM_SET_VCPU_EVENTS: {
4169 struct kvm_vcpu_events events;
4170
4171 r = -EFAULT;
4172 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4173 break;
4174
4175 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4176 break;
4177 }
4178 case KVM_GET_DEBUGREGS: {
4179 struct kvm_debugregs dbgregs;
4180
4181 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4182
4183 r = -EFAULT;
4184 if (copy_to_user(argp, &dbgregs,
4185 sizeof(struct kvm_debugregs)))
4186 break;
4187 r = 0;
4188 break;
4189 }
4190 case KVM_SET_DEBUGREGS: {
4191 struct kvm_debugregs dbgregs;
4192
4193 r = -EFAULT;
4194 if (copy_from_user(&dbgregs, argp,
4195 sizeof(struct kvm_debugregs)))
4196 break;
4197
4198 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4199 break;
4200 }
4201 case KVM_GET_XSAVE: {
4202 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4203 r = -ENOMEM;
4204 if (!u.xsave)
4205 break;
4206
4207 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4208
4209 r = -EFAULT;
4210 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4211 break;
4212 r = 0;
4213 break;
4214 }
4215 case KVM_SET_XSAVE: {
4216 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4217 if (IS_ERR(u.xsave)) {
4218 r = PTR_ERR(u.xsave);
4219 goto out_nofree;
4220 }
4221
4222 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4223 break;
4224 }
4225 case KVM_GET_XCRS: {
4226 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4227 r = -ENOMEM;
4228 if (!u.xcrs)
4229 break;
4230
4231 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4232
4233 r = -EFAULT;
4234 if (copy_to_user(argp, u.xcrs,
4235 sizeof(struct kvm_xcrs)))
4236 break;
4237 r = 0;
4238 break;
4239 }
4240 case KVM_SET_XCRS: {
4241 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4242 if (IS_ERR(u.xcrs)) {
4243 r = PTR_ERR(u.xcrs);
4244 goto out_nofree;
4245 }
4246
4247 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4248 break;
4249 }
4250 case KVM_SET_TSC_KHZ: {
4251 u32 user_tsc_khz;
4252
4253 r = -EINVAL;
4254 user_tsc_khz = (u32)arg;
4255
4256 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4257 goto out;
4258
4259 if (user_tsc_khz == 0)
4260 user_tsc_khz = tsc_khz;
4261
4262 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4263 r = 0;
4264
4265 goto out;
4266 }
4267 case KVM_GET_TSC_KHZ: {
4268 r = vcpu->arch.virtual_tsc_khz;
4269 goto out;
4270 }
4271 case KVM_KVMCLOCK_CTRL: {
4272 r = kvm_set_guest_paused(vcpu);
4273 goto out;
4274 }
4275 case KVM_ENABLE_CAP: {
4276 struct kvm_enable_cap cap;
4277
4278 r = -EFAULT;
4279 if (copy_from_user(&cap, argp, sizeof(cap)))
4280 goto out;
4281 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4282 break;
4283 }
4284 case KVM_GET_NESTED_STATE: {
4285 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4286 u32 user_data_size;
4287
4288 r = -EINVAL;
4289 if (!kvm_x86_ops->get_nested_state)
4290 break;
4291
4292 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4293 r = -EFAULT;
4294 if (get_user(user_data_size, &user_kvm_nested_state->size))
4295 break;
4296
4297 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4298 user_data_size);
4299 if (r < 0)
4300 break;
4301
4302 if (r > user_data_size) {
4303 if (put_user(r, &user_kvm_nested_state->size))
4304 r = -EFAULT;
4305 else
4306 r = -E2BIG;
4307 break;
4308 }
4309
4310 r = 0;
4311 break;
4312 }
4313 case KVM_SET_NESTED_STATE: {
4314 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4315 struct kvm_nested_state kvm_state;
4316
4317 r = -EINVAL;
4318 if (!kvm_x86_ops->set_nested_state)
4319 break;
4320
4321 r = -EFAULT;
4322 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4323 break;
4324
4325 r = -EINVAL;
4326 if (kvm_state.size < sizeof(kvm_state))
4327 break;
4328
4329 if (kvm_state.flags &
4330 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4331 | KVM_STATE_NESTED_EVMCS))
4332 break;
4333
4334 /* nested_run_pending implies guest_mode. */
4335 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4336 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4337 break;
4338
4339 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4340 break;
4341 }
4342 case KVM_GET_SUPPORTED_HV_CPUID: {
4343 struct kvm_cpuid2 __user *cpuid_arg = argp;
4344 struct kvm_cpuid2 cpuid;
4345
4346 r = -EFAULT;
4347 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4348 goto out;
4349
4350 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4351 cpuid_arg->entries);
4352 if (r)
4353 goto out;
4354
4355 r = -EFAULT;
4356 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4357 goto out;
4358 r = 0;
4359 break;
4360 }
4361 default:
4362 r = -EINVAL;
4363 }
4364out:
4365 kfree(u.buffer);
4366out_nofree:
4367 vcpu_put(vcpu);
4368 return r;
4369}
4370
4371vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4372{
4373 return VM_FAULT_SIGBUS;
4374}
4375
4376static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4377{
4378 int ret;
4379
4380 if (addr > (unsigned int)(-3 * PAGE_SIZE))
4381 return -EINVAL;
4382 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4383 return ret;
4384}
4385
4386static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4387 u64 ident_addr)
4388{
4389 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
4390}
4391
4392static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4393 unsigned long kvm_nr_mmu_pages)
4394{
4395 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4396 return -EINVAL;
4397
4398 mutex_lock(&kvm->slots_lock);
4399
4400 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4401 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4402
4403 mutex_unlock(&kvm->slots_lock);
4404 return 0;
4405}
4406
4407static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4408{
4409 return kvm->arch.n_max_mmu_pages;
4410}
4411
4412static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4413{
4414 struct kvm_pic *pic = kvm->arch.vpic;
4415 int r;
4416
4417 r = 0;
4418 switch (chip->chip_id) {
4419 case KVM_IRQCHIP_PIC_MASTER:
4420 memcpy(&chip->chip.pic, &pic->pics[0],
4421 sizeof(struct kvm_pic_state));
4422 break;
4423 case KVM_IRQCHIP_PIC_SLAVE:
4424 memcpy(&chip->chip.pic, &pic->pics[1],
4425 sizeof(struct kvm_pic_state));
4426 break;
4427 case KVM_IRQCHIP_IOAPIC:
4428 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4429 break;
4430 default:
4431 r = -EINVAL;
4432 break;
4433 }
4434 return r;
4435}
4436
4437static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4438{
4439 struct kvm_pic *pic = kvm->arch.vpic;
4440 int r;
4441
4442 r = 0;
4443 switch (chip->chip_id) {
4444 case KVM_IRQCHIP_PIC_MASTER:
4445 spin_lock(&pic->lock);
4446 memcpy(&pic->pics[0], &chip->chip.pic,
4447 sizeof(struct kvm_pic_state));
4448 spin_unlock(&pic->lock);
4449 break;
4450 case KVM_IRQCHIP_PIC_SLAVE:
4451 spin_lock(&pic->lock);
4452 memcpy(&pic->pics[1], &chip->chip.pic,
4453 sizeof(struct kvm_pic_state));
4454 spin_unlock(&pic->lock);
4455 break;
4456 case KVM_IRQCHIP_IOAPIC:
4457 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4458 break;
4459 default:
4460 r = -EINVAL;
4461 break;
4462 }
4463 kvm_pic_update_irq(pic);
4464 return r;
4465}
4466
4467static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4468{
4469 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4470
4471 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4472
4473 mutex_lock(&kps->lock);
4474 memcpy(ps, &kps->channels, sizeof(*ps));
4475 mutex_unlock(&kps->lock);
4476 return 0;
4477}
4478
4479static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4480{
4481 int i;
4482 struct kvm_pit *pit = kvm->arch.vpit;
4483
4484 mutex_lock(&pit->pit_state.lock);
4485 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4486 for (i = 0; i < 3; i++)
4487 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4488 mutex_unlock(&pit->pit_state.lock);
4489 return 0;
4490}
4491
4492static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4493{
4494 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4495 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4496 sizeof(ps->channels));
4497 ps->flags = kvm->arch.vpit->pit_state.flags;
4498 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4499 memset(&ps->reserved, 0, sizeof(ps->reserved));
4500 return 0;
4501}
4502
4503static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4504{
4505 int start = 0;
4506 int i;
4507 u32 prev_legacy, cur_legacy;
4508 struct kvm_pit *pit = kvm->arch.vpit;
4509
4510 mutex_lock(&pit->pit_state.lock);
4511 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4512 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4513 if (!prev_legacy && cur_legacy)
4514 start = 1;
4515 memcpy(&pit->pit_state.channels, &ps->channels,
4516 sizeof(pit->pit_state.channels));
4517 pit->pit_state.flags = ps->flags;
4518 for (i = 0; i < 3; i++)
4519 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4520 start && i == 0);
4521 mutex_unlock(&pit->pit_state.lock);
4522 return 0;
4523}
4524
4525static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4526 struct kvm_reinject_control *control)
4527{
4528 struct kvm_pit *pit = kvm->arch.vpit;
4529
4530 if (!pit)
4531 return -ENXIO;
4532
4533 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4534 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4535 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4536 */
4537 mutex_lock(&pit->pit_state.lock);
4538 kvm_pit_set_reinject(pit, control->pit_reinject);
4539 mutex_unlock(&pit->pit_state.lock);
4540
4541 return 0;
4542}
4543
4544/**
4545 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4546 * @kvm: kvm instance
4547 * @log: slot id and address to which we copy the log
4548 *
4549 * Steps 1-4 below provide general overview of dirty page logging. See
4550 * kvm_get_dirty_log_protect() function description for additional details.
4551 *
4552 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4553 * always flush the TLB (step 4) even if previous step failed and the dirty
4554 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4555 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4556 * writes will be marked dirty for next log read.
4557 *
4558 * 1. Take a snapshot of the bit and clear it if needed.
4559 * 2. Write protect the corresponding page.
4560 * 3. Copy the snapshot to the userspace.
4561 * 4. Flush TLB's if needed.
4562 */
4563int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
4564{
4565 bool flush = false;
4566 int r;
4567
4568 mutex_lock(&kvm->slots_lock);
4569
4570 /*
4571 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4572 */
4573 if (kvm_x86_ops->flush_log_dirty)
4574 kvm_x86_ops->flush_log_dirty(kvm);
4575
4576 r = kvm_get_dirty_log_protect(kvm, log, &flush);
4577
4578 /*
4579 * All the TLBs can be flushed out of mmu lock, see the comments in
4580 * kvm_mmu_slot_remove_write_access().
4581 */
4582 lockdep_assert_held(&kvm->slots_lock);
4583 if (flush)
4584 kvm_flush_remote_tlbs(kvm);
4585
4586 mutex_unlock(&kvm->slots_lock);
4587 return r;
4588}
4589
4590int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4591{
4592 bool flush = false;
4593 int r;
4594
4595 mutex_lock(&kvm->slots_lock);
4596
4597 /*
4598 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4599 */
4600 if (kvm_x86_ops->flush_log_dirty)
4601 kvm_x86_ops->flush_log_dirty(kvm);
4602
4603 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4604
4605 /*
4606 * All the TLBs can be flushed out of mmu lock, see the comments in
4607 * kvm_mmu_slot_remove_write_access().
4608 */
4609 lockdep_assert_held(&kvm->slots_lock);
4610 if (flush)
4611 kvm_flush_remote_tlbs(kvm);
4612
4613 mutex_unlock(&kvm->slots_lock);
4614 return r;
4615}
4616
4617int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4618 bool line_status)
4619{
4620 if (!irqchip_in_kernel(kvm))
4621 return -ENXIO;
4622
4623 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4624 irq_event->irq, irq_event->level,
4625 line_status);
4626 return 0;
4627}
4628
4629int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4630 struct kvm_enable_cap *cap)
4631{
4632 int r;
4633
4634 if (cap->flags)
4635 return -EINVAL;
4636
4637 switch (cap->cap) {
4638 case KVM_CAP_DISABLE_QUIRKS:
4639 kvm->arch.disabled_quirks = cap->args[0];
4640 r = 0;
4641 break;
4642 case KVM_CAP_SPLIT_IRQCHIP: {
4643 mutex_lock(&kvm->lock);
4644 r = -EINVAL;
4645 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4646 goto split_irqchip_unlock;
4647 r = -EEXIST;
4648 if (irqchip_in_kernel(kvm))
4649 goto split_irqchip_unlock;
4650 if (kvm->created_vcpus)
4651 goto split_irqchip_unlock;
4652 r = kvm_setup_empty_irq_routing(kvm);
4653 if (r)
4654 goto split_irqchip_unlock;
4655 /* Pairs with irqchip_in_kernel. */
4656 smp_wmb();
4657 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4658 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4659 r = 0;
4660split_irqchip_unlock:
4661 mutex_unlock(&kvm->lock);
4662 break;
4663 }
4664 case KVM_CAP_X2APIC_API:
4665 r = -EINVAL;
4666 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4667 break;
4668
4669 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4670 kvm->arch.x2apic_format = true;
4671 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4672 kvm->arch.x2apic_broadcast_quirk_disabled = true;
4673
4674 r = 0;
4675 break;
4676 case KVM_CAP_X86_DISABLE_EXITS:
4677 r = -EINVAL;
4678 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4679 break;
4680
4681 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4682 kvm_can_mwait_in_guest())
4683 kvm->arch.mwait_in_guest = true;
4684 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4685 kvm->arch.hlt_in_guest = true;
4686 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4687 kvm->arch.pause_in_guest = true;
4688 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4689 kvm->arch.cstate_in_guest = true;
4690 r = 0;
4691 break;
4692 case KVM_CAP_MSR_PLATFORM_INFO:
4693 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4694 r = 0;
4695 break;
4696 case KVM_CAP_EXCEPTION_PAYLOAD:
4697 kvm->arch.exception_payload_enabled = cap->args[0];
4698 r = 0;
4699 break;
4700 default:
4701 r = -EINVAL;
4702 break;
4703 }
4704 return r;
4705}
4706
4707long kvm_arch_vm_ioctl(struct file *filp,
4708 unsigned int ioctl, unsigned long arg)
4709{
4710 struct kvm *kvm = filp->private_data;
4711 void __user *argp = (void __user *)arg;
4712 int r = -ENOTTY;
4713 /*
4714 * This union makes it completely explicit to gcc-3.x
4715 * that these two variables' stack usage should be
4716 * combined, not added together.
4717 */
4718 union {
4719 struct kvm_pit_state ps;
4720 struct kvm_pit_state2 ps2;
4721 struct kvm_pit_config pit_config;
4722 } u;
4723
4724 switch (ioctl) {
4725 case KVM_SET_TSS_ADDR:
4726 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4727 break;
4728 case KVM_SET_IDENTITY_MAP_ADDR: {
4729 u64 ident_addr;
4730
4731 mutex_lock(&kvm->lock);
4732 r = -EINVAL;
4733 if (kvm->created_vcpus)
4734 goto set_identity_unlock;
4735 r = -EFAULT;
4736 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
4737 goto set_identity_unlock;
4738 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4739set_identity_unlock:
4740 mutex_unlock(&kvm->lock);
4741 break;
4742 }
4743 case KVM_SET_NR_MMU_PAGES:
4744 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4745 break;
4746 case KVM_GET_NR_MMU_PAGES:
4747 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4748 break;
4749 case KVM_CREATE_IRQCHIP: {
4750 mutex_lock(&kvm->lock);
4751
4752 r = -EEXIST;
4753 if (irqchip_in_kernel(kvm))
4754 goto create_irqchip_unlock;
4755
4756 r = -EINVAL;
4757 if (kvm->created_vcpus)
4758 goto create_irqchip_unlock;
4759
4760 r = kvm_pic_init(kvm);
4761 if (r)
4762 goto create_irqchip_unlock;
4763
4764 r = kvm_ioapic_init(kvm);
4765 if (r) {
4766 kvm_pic_destroy(kvm);
4767 goto create_irqchip_unlock;
4768 }
4769
4770 r = kvm_setup_default_irq_routing(kvm);
4771 if (r) {
4772 kvm_ioapic_destroy(kvm);
4773 kvm_pic_destroy(kvm);
4774 goto create_irqchip_unlock;
4775 }
4776 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4777 smp_wmb();
4778 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4779 create_irqchip_unlock:
4780 mutex_unlock(&kvm->lock);
4781 break;
4782 }
4783 case KVM_CREATE_PIT:
4784 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4785 goto create_pit;
4786 case KVM_CREATE_PIT2:
4787 r = -EFAULT;
4788 if (copy_from_user(&u.pit_config, argp,
4789 sizeof(struct kvm_pit_config)))
4790 goto out;
4791 create_pit:
4792 mutex_lock(&kvm->lock);
4793 r = -EEXIST;
4794 if (kvm->arch.vpit)
4795 goto create_pit_unlock;
4796 r = -ENOMEM;
4797 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4798 if (kvm->arch.vpit)
4799 r = 0;
4800 create_pit_unlock:
4801 mutex_unlock(&kvm->lock);
4802 break;
4803 case KVM_GET_IRQCHIP: {
4804 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4805 struct kvm_irqchip *chip;
4806
4807 chip = memdup_user(argp, sizeof(*chip));
4808 if (IS_ERR(chip)) {
4809 r = PTR_ERR(chip);
4810 goto out;
4811 }
4812
4813 r = -ENXIO;
4814 if (!irqchip_kernel(kvm))
4815 goto get_irqchip_out;
4816 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4817 if (r)
4818 goto get_irqchip_out;
4819 r = -EFAULT;
4820 if (copy_to_user(argp, chip, sizeof(*chip)))
4821 goto get_irqchip_out;
4822 r = 0;
4823 get_irqchip_out:
4824 kfree(chip);
4825 break;
4826 }
4827 case KVM_SET_IRQCHIP: {
4828 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4829 struct kvm_irqchip *chip;
4830
4831 chip = memdup_user(argp, sizeof(*chip));
4832 if (IS_ERR(chip)) {
4833 r = PTR_ERR(chip);
4834 goto out;
4835 }
4836
4837 r = -ENXIO;
4838 if (!irqchip_kernel(kvm))
4839 goto set_irqchip_out;
4840 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4841 if (r)
4842 goto set_irqchip_out;
4843 r = 0;
4844 set_irqchip_out:
4845 kfree(chip);
4846 break;
4847 }
4848 case KVM_GET_PIT: {
4849 r = -EFAULT;
4850 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4851 goto out;
4852 r = -ENXIO;
4853 if (!kvm->arch.vpit)
4854 goto out;
4855 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4856 if (r)
4857 goto out;
4858 r = -EFAULT;
4859 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4860 goto out;
4861 r = 0;
4862 break;
4863 }
4864 case KVM_SET_PIT: {
4865 r = -EFAULT;
4866 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
4867 goto out;
4868 r = -ENXIO;
4869 if (!kvm->arch.vpit)
4870 goto out;
4871 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4872 break;
4873 }
4874 case KVM_GET_PIT2: {
4875 r = -ENXIO;
4876 if (!kvm->arch.vpit)
4877 goto out;
4878 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4879 if (r)
4880 goto out;
4881 r = -EFAULT;
4882 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4883 goto out;
4884 r = 0;
4885 break;
4886 }
4887 case KVM_SET_PIT2: {
4888 r = -EFAULT;
4889 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4890 goto out;
4891 r = -ENXIO;
4892 if (!kvm->arch.vpit)
4893 goto out;
4894 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4895 break;
4896 }
4897 case KVM_REINJECT_CONTROL: {
4898 struct kvm_reinject_control control;
4899 r = -EFAULT;
4900 if (copy_from_user(&control, argp, sizeof(control)))
4901 goto out;
4902 r = kvm_vm_ioctl_reinject(kvm, &control);
4903 break;
4904 }
4905 case KVM_SET_BOOT_CPU_ID:
4906 r = 0;
4907 mutex_lock(&kvm->lock);
4908 if (kvm->created_vcpus)
4909 r = -EBUSY;
4910 else
4911 kvm->arch.bsp_vcpu_id = arg;
4912 mutex_unlock(&kvm->lock);
4913 break;
4914 case KVM_XEN_HVM_CONFIG: {
4915 struct kvm_xen_hvm_config xhc;
4916 r = -EFAULT;
4917 if (copy_from_user(&xhc, argp, sizeof(xhc)))
4918 goto out;
4919 r = -EINVAL;
4920 if (xhc.flags)
4921 goto out;
4922 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
4923 r = 0;
4924 break;
4925 }
4926 case KVM_SET_CLOCK: {
4927 struct kvm_clock_data user_ns;
4928 u64 now_ns;
4929
4930 r = -EFAULT;
4931 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4932 goto out;
4933
4934 r = -EINVAL;
4935 if (user_ns.flags)
4936 goto out;
4937
4938 r = 0;
4939 /*
4940 * TODO: userspace has to take care of races with VCPU_RUN, so
4941 * kvm_gen_update_masterclock() can be cut down to locked
4942 * pvclock_update_vm_gtod_copy().
4943 */
4944 kvm_gen_update_masterclock(kvm);
4945 now_ns = get_kvmclock_ns(kvm);
4946 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4947 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
4948 break;
4949 }
4950 case KVM_GET_CLOCK: {
4951 struct kvm_clock_data user_ns;
4952 u64 now_ns;
4953
4954 now_ns = get_kvmclock_ns(kvm);
4955 user_ns.clock = now_ns;
4956 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4957 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4958
4959 r = -EFAULT;
4960 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4961 goto out;
4962 r = 0;
4963 break;
4964 }
4965 case KVM_MEMORY_ENCRYPT_OP: {
4966 r = -ENOTTY;
4967 if (kvm_x86_ops->mem_enc_op)
4968 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4969 break;
4970 }
4971 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4972 struct kvm_enc_region region;
4973
4974 r = -EFAULT;
4975 if (copy_from_user(&region, argp, sizeof(region)))
4976 goto out;
4977
4978 r = -ENOTTY;
4979 if (kvm_x86_ops->mem_enc_reg_region)
4980 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4981 break;
4982 }
4983 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4984 struct kvm_enc_region region;
4985
4986 r = -EFAULT;
4987 if (copy_from_user(&region, argp, sizeof(region)))
4988 goto out;
4989
4990 r = -ENOTTY;
4991 if (kvm_x86_ops->mem_enc_unreg_region)
4992 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4993 break;
4994 }
4995 case KVM_HYPERV_EVENTFD: {
4996 struct kvm_hyperv_eventfd hvevfd;
4997
4998 r = -EFAULT;
4999 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5000 goto out;
5001 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5002 break;
5003 }
5004 case KVM_SET_PMU_EVENT_FILTER:
5005 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5006 break;
5007 default:
5008 r = -ENOTTY;
5009 }
5010out:
5011 return r;
5012}
5013
5014static void kvm_init_msr_list(void)
5015{
5016 u32 dummy[2];
5017 unsigned i, j;
5018
5019 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
5020 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
5021 continue;
5022
5023 /*
5024 * Even MSRs that are valid in the host may not be exposed
5025 * to the guests in some cases.
5026 */
5027 switch (msrs_to_save[i]) {
5028 case MSR_IA32_BNDCFGS:
5029 if (!kvm_mpx_supported())
5030 continue;
5031 break;
5032 case MSR_TSC_AUX:
5033 if (!kvm_x86_ops->rdtscp_supported())
5034 continue;
5035 break;
5036 case MSR_IA32_RTIT_CTL:
5037 case MSR_IA32_RTIT_STATUS:
5038 if (!kvm_x86_ops->pt_supported())
5039 continue;
5040 break;
5041 case MSR_IA32_RTIT_CR3_MATCH:
5042 if (!kvm_x86_ops->pt_supported() ||
5043 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5044 continue;
5045 break;
5046 case MSR_IA32_RTIT_OUTPUT_BASE:
5047 case MSR_IA32_RTIT_OUTPUT_MASK:
5048 if (!kvm_x86_ops->pt_supported() ||
5049 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5050 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5051 continue;
5052 break;
5053 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5054 if (!kvm_x86_ops->pt_supported() ||
5055 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
5056 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5057 continue;
5058 break;
5059 }
5060 default:
5061 break;
5062 }
5063
5064 if (j < i)
5065 msrs_to_save[j] = msrs_to_save[i];
5066 j++;
5067 }
5068 num_msrs_to_save = j;
5069
5070 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
5071 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
5072 continue;
5073
5074 if (j < i)
5075 emulated_msrs[j] = emulated_msrs[i];
5076 j++;
5077 }
5078 num_emulated_msrs = j;
5079
5080 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
5081 struct kvm_msr_entry msr;
5082
5083 msr.index = msr_based_features[i];
5084 if (kvm_get_msr_feature(&msr))
5085 continue;
5086
5087 if (j < i)
5088 msr_based_features[j] = msr_based_features[i];
5089 j++;
5090 }
5091 num_msr_based_features = j;
5092}
5093
5094static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5095 const void *v)
5096{
5097 int handled = 0;
5098 int n;
5099
5100 do {
5101 n = min(len, 8);
5102 if (!(lapic_in_kernel(vcpu) &&
5103 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5104 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5105 break;
5106 handled += n;
5107 addr += n;
5108 len -= n;
5109 v += n;
5110 } while (len);
5111
5112 return handled;
5113}
5114
5115static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5116{
5117 int handled = 0;
5118 int n;
5119
5120 do {
5121 n = min(len, 8);
5122 if (!(lapic_in_kernel(vcpu) &&
5123 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5124 addr, n, v))
5125 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5126 break;
5127 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5128 handled += n;
5129 addr += n;
5130 len -= n;
5131 v += n;
5132 } while (len);
5133
5134 return handled;
5135}
5136
5137static void kvm_set_segment(struct kvm_vcpu *vcpu,
5138 struct kvm_segment *var, int seg)
5139{
5140 kvm_x86_ops->set_segment(vcpu, var, seg);
5141}
5142
5143void kvm_get_segment(struct kvm_vcpu *vcpu,
5144 struct kvm_segment *var, int seg)
5145{
5146 kvm_x86_ops->get_segment(vcpu, var, seg);
5147}
5148
5149gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5150 struct x86_exception *exception)
5151{
5152 gpa_t t_gpa;
5153
5154 BUG_ON(!mmu_is_nested(vcpu));
5155
5156 /* NPT walks are always user-walks */
5157 access |= PFERR_USER_MASK;
5158 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5159
5160 return t_gpa;
5161}
5162
5163gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5164 struct x86_exception *exception)
5165{
5166 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5167 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5168}
5169
5170 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5171 struct x86_exception *exception)
5172{
5173 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5174 access |= PFERR_FETCH_MASK;
5175 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5176}
5177
5178gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5179 struct x86_exception *exception)
5180{
5181 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5182 access |= PFERR_WRITE_MASK;
5183 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5184}
5185
5186/* uses this to access any guest's mapped memory without checking CPL */
5187gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5188 struct x86_exception *exception)
5189{
5190 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5191}
5192
5193static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5194 struct kvm_vcpu *vcpu, u32 access,
5195 struct x86_exception *exception)
5196{
5197 void *data = val;
5198 int r = X86EMUL_CONTINUE;
5199
5200 while (bytes) {
5201 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5202 exception);
5203 unsigned offset = addr & (PAGE_SIZE-1);
5204 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5205 int ret;
5206
5207 if (gpa == UNMAPPED_GVA)
5208 return X86EMUL_PROPAGATE_FAULT;
5209 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5210 offset, toread);
5211 if (ret < 0) {
5212 r = X86EMUL_IO_NEEDED;
5213 goto out;
5214 }
5215
5216 bytes -= toread;
5217 data += toread;
5218 addr += toread;
5219 }
5220out:
5221 return r;
5222}
5223
5224/* used for instruction fetching */
5225static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5226 gva_t addr, void *val, unsigned int bytes,
5227 struct x86_exception *exception)
5228{
5229 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5230 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5231 unsigned offset;
5232 int ret;
5233
5234 /* Inline kvm_read_guest_virt_helper for speed. */
5235 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5236 exception);
5237 if (unlikely(gpa == UNMAPPED_GVA))
5238 return X86EMUL_PROPAGATE_FAULT;
5239
5240 offset = addr & (PAGE_SIZE-1);
5241 if (WARN_ON(offset + bytes > PAGE_SIZE))
5242 bytes = (unsigned)PAGE_SIZE - offset;
5243 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5244 offset, bytes);
5245 if (unlikely(ret < 0))
5246 return X86EMUL_IO_NEEDED;
5247
5248 return X86EMUL_CONTINUE;
5249}
5250
5251int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5252 gva_t addr, void *val, unsigned int bytes,
5253 struct x86_exception *exception)
5254{
5255 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5256
5257 /*
5258 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5259 * is returned, but our callers are not ready for that and they blindly
5260 * call kvm_inject_page_fault. Ensure that they at least do not leak
5261 * uninitialized kernel stack memory into cr2 and error code.
5262 */
5263 memset(exception, 0, sizeof(*exception));
5264 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5265 exception);
5266}
5267EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5268
5269static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5270 gva_t addr, void *val, unsigned int bytes,
5271 struct x86_exception *exception, bool system)
5272{
5273 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5274 u32 access = 0;
5275
5276 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5277 access |= PFERR_USER_MASK;
5278
5279 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5280}
5281
5282static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5283 unsigned long addr, void *val, unsigned int bytes)
5284{
5285 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5286 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5287
5288 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5289}
5290
5291static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5292 struct kvm_vcpu *vcpu, u32 access,
5293 struct x86_exception *exception)
5294{
5295 void *data = val;
5296 int r = X86EMUL_CONTINUE;
5297
5298 while (bytes) {
5299 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5300 access,
5301 exception);
5302 unsigned offset = addr & (PAGE_SIZE-1);
5303 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5304 int ret;
5305
5306 if (gpa == UNMAPPED_GVA)
5307 return X86EMUL_PROPAGATE_FAULT;
5308 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5309 if (ret < 0) {
5310 r = X86EMUL_IO_NEEDED;
5311 goto out;
5312 }
5313
5314 bytes -= towrite;
5315 data += towrite;
5316 addr += towrite;
5317 }
5318out:
5319 return r;
5320}
5321
5322static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5323 unsigned int bytes, struct x86_exception *exception,
5324 bool system)
5325{
5326 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5327 u32 access = PFERR_WRITE_MASK;
5328
5329 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5330 access |= PFERR_USER_MASK;
5331
5332 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5333 access, exception);
5334}
5335
5336int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5337 unsigned int bytes, struct x86_exception *exception)
5338{
5339 /* kvm_write_guest_virt_system can pull in tons of pages. */
5340 vcpu->arch.l1tf_flush_l1d = true;
5341
5342 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5343 PFERR_WRITE_MASK, exception);
5344}
5345EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5346
5347int handle_ud(struct kvm_vcpu *vcpu)
5348{
5349 int emul_type = EMULTYPE_TRAP_UD;
5350 enum emulation_result er;
5351 char sig[5]; /* ud2; .ascii "kvm" */
5352 struct x86_exception e;
5353
5354 if (force_emulation_prefix &&
5355 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5356 sig, sizeof(sig), &e) == 0 &&
5357 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5358 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5359 emul_type = 0;
5360 }
5361
5362 er = kvm_emulate_instruction(vcpu, emul_type);
5363 if (er == EMULATE_USER_EXIT)
5364 return 0;
5365 if (er != EMULATE_DONE)
5366 kvm_queue_exception(vcpu, UD_VECTOR);
5367 return 1;
5368}
5369EXPORT_SYMBOL_GPL(handle_ud);
5370
5371static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5372 gpa_t gpa, bool write)
5373{
5374 /* For APIC access vmexit */
5375 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5376 return 1;
5377
5378 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5379 trace_vcpu_match_mmio(gva, gpa, write, true);
5380 return 1;
5381 }
5382
5383 return 0;
5384}
5385
5386static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5387 gpa_t *gpa, struct x86_exception *exception,
5388 bool write)
5389{
5390 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5391 | (write ? PFERR_WRITE_MASK : 0);
5392
5393 /*
5394 * currently PKRU is only applied to ept enabled guest so
5395 * there is no pkey in EPT page table for L1 guest or EPT
5396 * shadow page table for L2 guest.
5397 */
5398 if (vcpu_match_mmio_gva(vcpu, gva)
5399 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5400 vcpu->arch.mmio_access, 0, access)) {
5401 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5402 (gva & (PAGE_SIZE - 1));
5403 trace_vcpu_match_mmio(gva, *gpa, write, false);
5404 return 1;
5405 }
5406
5407 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5408
5409 if (*gpa == UNMAPPED_GVA)
5410 return -1;
5411
5412 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5413}
5414
5415int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5416 const void *val, int bytes)
5417{
5418 int ret;
5419
5420 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5421 if (ret < 0)
5422 return 0;
5423 kvm_page_track_write(vcpu, gpa, val, bytes);
5424 return 1;
5425}
5426
5427struct read_write_emulator_ops {
5428 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5429 int bytes);
5430 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5431 void *val, int bytes);
5432 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5433 int bytes, void *val);
5434 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5435 void *val, int bytes);
5436 bool write;
5437};
5438
5439static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5440{
5441 if (vcpu->mmio_read_completed) {
5442 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5443 vcpu->mmio_fragments[0].gpa, val);
5444 vcpu->mmio_read_completed = 0;
5445 return 1;
5446 }
5447
5448 return 0;
5449}
5450
5451static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5452 void *val, int bytes)
5453{
5454 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5455}
5456
5457static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5458 void *val, int bytes)
5459{
5460 return emulator_write_phys(vcpu, gpa, val, bytes);
5461}
5462
5463static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5464{
5465 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5466 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5467}
5468
5469static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5470 void *val, int bytes)
5471{
5472 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5473 return X86EMUL_IO_NEEDED;
5474}
5475
5476static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5477 void *val, int bytes)
5478{
5479 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5480
5481 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5482 return X86EMUL_CONTINUE;
5483}
5484
5485static const struct read_write_emulator_ops read_emultor = {
5486 .read_write_prepare = read_prepare,
5487 .read_write_emulate = read_emulate,
5488 .read_write_mmio = vcpu_mmio_read,
5489 .read_write_exit_mmio = read_exit_mmio,
5490};
5491
5492static const struct read_write_emulator_ops write_emultor = {
5493 .read_write_emulate = write_emulate,
5494 .read_write_mmio = write_mmio,
5495 .read_write_exit_mmio = write_exit_mmio,
5496 .write = true,
5497};
5498
5499static int emulator_read_write_onepage(unsigned long addr, void *val,
5500 unsigned int bytes,
5501 struct x86_exception *exception,
5502 struct kvm_vcpu *vcpu,
5503 const struct read_write_emulator_ops *ops)
5504{
5505 gpa_t gpa;
5506 int handled, ret;
5507 bool write = ops->write;
5508 struct kvm_mmio_fragment *frag;
5509 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5510
5511 /*
5512 * If the exit was due to a NPF we may already have a GPA.
5513 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5514 * Note, this cannot be used on string operations since string
5515 * operation using rep will only have the initial GPA from the NPF
5516 * occurred.
5517 */
5518 if (vcpu->arch.gpa_available &&
5519 emulator_can_use_gpa(ctxt) &&
5520 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5521 gpa = vcpu->arch.gpa_val;
5522 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5523 } else {
5524 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5525 if (ret < 0)
5526 return X86EMUL_PROPAGATE_FAULT;
5527 }
5528
5529 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5530 return X86EMUL_CONTINUE;
5531
5532 /*
5533 * Is this MMIO handled locally?
5534 */
5535 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5536 if (handled == bytes)
5537 return X86EMUL_CONTINUE;
5538
5539 gpa += handled;
5540 bytes -= handled;
5541 val += handled;
5542
5543 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5544 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5545 frag->gpa = gpa;
5546 frag->data = val;
5547 frag->len = bytes;
5548 return X86EMUL_CONTINUE;
5549}
5550
5551static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5552 unsigned long addr,
5553 void *val, unsigned int bytes,
5554 struct x86_exception *exception,
5555 const struct read_write_emulator_ops *ops)
5556{
5557 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5558 gpa_t gpa;
5559 int rc;
5560
5561 if (ops->read_write_prepare &&
5562 ops->read_write_prepare(vcpu, val, bytes))
5563 return X86EMUL_CONTINUE;
5564
5565 vcpu->mmio_nr_fragments = 0;
5566
5567 /* Crossing a page boundary? */
5568 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5569 int now;
5570
5571 now = -addr & ~PAGE_MASK;
5572 rc = emulator_read_write_onepage(addr, val, now, exception,
5573 vcpu, ops);
5574
5575 if (rc != X86EMUL_CONTINUE)
5576 return rc;
5577 addr += now;
5578 if (ctxt->mode != X86EMUL_MODE_PROT64)
5579 addr = (u32)addr;
5580 val += now;
5581 bytes -= now;
5582 }
5583
5584 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5585 vcpu, ops);
5586 if (rc != X86EMUL_CONTINUE)
5587 return rc;
5588
5589 if (!vcpu->mmio_nr_fragments)
5590 return rc;
5591
5592 gpa = vcpu->mmio_fragments[0].gpa;
5593
5594 vcpu->mmio_needed = 1;
5595 vcpu->mmio_cur_fragment = 0;
5596
5597 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5598 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5599 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5600 vcpu->run->mmio.phys_addr = gpa;
5601
5602 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5603}
5604
5605static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5606 unsigned long addr,
5607 void *val,
5608 unsigned int bytes,
5609 struct x86_exception *exception)
5610{
5611 return emulator_read_write(ctxt, addr, val, bytes,
5612 exception, &read_emultor);
5613}
5614
5615static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5616 unsigned long addr,
5617 const void *val,
5618 unsigned int bytes,
5619 struct x86_exception *exception)
5620{
5621 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5622 exception, &write_emultor);
5623}
5624
5625#define CMPXCHG_TYPE(t, ptr, old, new) \
5626 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5627
5628#ifdef CONFIG_X86_64
5629# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5630#else
5631# define CMPXCHG64(ptr, old, new) \
5632 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5633#endif
5634
5635static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5636 unsigned long addr,
5637 const void *old,
5638 const void *new,
5639 unsigned int bytes,
5640 struct x86_exception *exception)
5641{
5642 struct kvm_host_map map;
5643 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5644 gpa_t gpa;
5645 char *kaddr;
5646 bool exchanged;
5647
5648 /* guests cmpxchg8b have to be emulated atomically */
5649 if (bytes > 8 || (bytes & (bytes - 1)))
5650 goto emul_write;
5651
5652 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5653
5654 if (gpa == UNMAPPED_GVA ||
5655 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5656 goto emul_write;
5657
5658 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5659 goto emul_write;
5660
5661 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
5662 goto emul_write;
5663
5664 kaddr = map.hva + offset_in_page(gpa);
5665
5666 switch (bytes) {
5667 case 1:
5668 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5669 break;
5670 case 2:
5671 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5672 break;
5673 case 4:
5674 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5675 break;
5676 case 8:
5677 exchanged = CMPXCHG64(kaddr, old, new);
5678 break;
5679 default:
5680 BUG();
5681 }
5682
5683 kvm_vcpu_unmap(vcpu, &map, true);
5684
5685 if (!exchanged)
5686 return X86EMUL_CMPXCHG_FAILED;
5687
5688 kvm_page_track_write(vcpu, gpa, new, bytes);
5689
5690 return X86EMUL_CONTINUE;
5691
5692emul_write:
5693 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5694
5695 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5696}
5697
5698static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5699{
5700 int r = 0, i;
5701
5702 for (i = 0; i < vcpu->arch.pio.count; i++) {
5703 if (vcpu->arch.pio.in)
5704 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5705 vcpu->arch.pio.size, pd);
5706 else
5707 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5708 vcpu->arch.pio.port, vcpu->arch.pio.size,
5709 pd);
5710 if (r)
5711 break;
5712 pd += vcpu->arch.pio.size;
5713 }
5714 return r;
5715}
5716
5717static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5718 unsigned short port, void *val,
5719 unsigned int count, bool in)
5720{
5721 vcpu->arch.pio.port = port;
5722 vcpu->arch.pio.in = in;
5723 vcpu->arch.pio.count = count;
5724 vcpu->arch.pio.size = size;
5725
5726 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5727 vcpu->arch.pio.count = 0;
5728 return 1;
5729 }
5730
5731 vcpu->run->exit_reason = KVM_EXIT_IO;
5732 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5733 vcpu->run->io.size = size;
5734 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5735 vcpu->run->io.count = count;
5736 vcpu->run->io.port = port;
5737
5738 return 0;
5739}
5740
5741static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5742 int size, unsigned short port, void *val,
5743 unsigned int count)
5744{
5745 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5746 int ret;
5747
5748 if (vcpu->arch.pio.count)
5749 goto data_avail;
5750
5751 memset(vcpu->arch.pio_data, 0, size * count);
5752
5753 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5754 if (ret) {
5755data_avail:
5756 memcpy(val, vcpu->arch.pio_data, size * count);
5757 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5758 vcpu->arch.pio.count = 0;
5759 return 1;
5760 }
5761
5762 return 0;
5763}
5764
5765static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5766 int size, unsigned short port,
5767 const void *val, unsigned int count)
5768{
5769 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5770
5771 memcpy(vcpu->arch.pio_data, val, size * count);
5772 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5773 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5774}
5775
5776static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5777{
5778 return kvm_x86_ops->get_segment_base(vcpu, seg);
5779}
5780
5781static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
5782{
5783 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
5784}
5785
5786static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
5787{
5788 if (!need_emulate_wbinvd(vcpu))
5789 return X86EMUL_CONTINUE;
5790
5791 if (kvm_x86_ops->has_wbinvd_exit()) {
5792 int cpu = get_cpu();
5793
5794 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
5795 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5796 wbinvd_ipi, NULL, 1);
5797 put_cpu();
5798 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
5799 } else
5800 wbinvd();
5801 return X86EMUL_CONTINUE;
5802}
5803
5804int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5805{
5806 kvm_emulate_wbinvd_noskip(vcpu);
5807 return kvm_skip_emulated_instruction(vcpu);
5808}
5809EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5810
5811
5812
5813static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5814{
5815 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
5816}
5817
5818static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5819 unsigned long *dest)
5820{
5821 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
5822}
5823
5824static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5825 unsigned long value)
5826{
5827
5828 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
5829}
5830
5831static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5832{
5833 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5834}
5835
5836static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
5837{
5838 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5839 unsigned long value;
5840
5841 switch (cr) {
5842 case 0:
5843 value = kvm_read_cr0(vcpu);
5844 break;
5845 case 2:
5846 value = vcpu->arch.cr2;
5847 break;
5848 case 3:
5849 value = kvm_read_cr3(vcpu);
5850 break;
5851 case 4:
5852 value = kvm_read_cr4(vcpu);
5853 break;
5854 case 8:
5855 value = kvm_get_cr8(vcpu);
5856 break;
5857 default:
5858 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5859 return 0;
5860 }
5861
5862 return value;
5863}
5864
5865static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5866{
5867 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5868 int res = 0;
5869
5870 switch (cr) {
5871 case 0:
5872 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5873 break;
5874 case 2:
5875 vcpu->arch.cr2 = val;
5876 break;
5877 case 3:
5878 res = kvm_set_cr3(vcpu, val);
5879 break;
5880 case 4:
5881 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5882 break;
5883 case 8:
5884 res = kvm_set_cr8(vcpu, val);
5885 break;
5886 default:
5887 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5888 res = -1;
5889 }
5890
5891 return res;
5892}
5893
5894static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5895{
5896 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5897}
5898
5899static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5900{
5901 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5902}
5903
5904static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5905{
5906 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
5907}
5908
5909static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5910{
5911 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5912}
5913
5914static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5915{
5916 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5917}
5918
5919static unsigned long emulator_get_cached_segment_base(
5920 struct x86_emulate_ctxt *ctxt, int seg)
5921{
5922 return get_segment_base(emul_to_vcpu(ctxt), seg);
5923}
5924
5925static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5926 struct desc_struct *desc, u32 *base3,
5927 int seg)
5928{
5929 struct kvm_segment var;
5930
5931 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
5932 *selector = var.selector;
5933
5934 if (var.unusable) {
5935 memset(desc, 0, sizeof(*desc));
5936 if (base3)
5937 *base3 = 0;
5938 return false;
5939 }
5940
5941 if (var.g)
5942 var.limit >>= 12;
5943 set_desc_limit(desc, var.limit);
5944 set_desc_base(desc, (unsigned long)var.base);
5945#ifdef CONFIG_X86_64
5946 if (base3)
5947 *base3 = var.base >> 32;
5948#endif
5949 desc->type = var.type;
5950 desc->s = var.s;
5951 desc->dpl = var.dpl;
5952 desc->p = var.present;
5953 desc->avl = var.avl;
5954 desc->l = var.l;
5955 desc->d = var.db;
5956 desc->g = var.g;
5957
5958 return true;
5959}
5960
5961static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5962 struct desc_struct *desc, u32 base3,
5963 int seg)
5964{
5965 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5966 struct kvm_segment var;
5967
5968 var.selector = selector;
5969 var.base = get_desc_base(desc);
5970#ifdef CONFIG_X86_64
5971 var.base |= ((u64)base3) << 32;
5972#endif
5973 var.limit = get_desc_limit(desc);
5974 if (desc->g)
5975 var.limit = (var.limit << 12) | 0xfff;
5976 var.type = desc->type;
5977 var.dpl = desc->dpl;
5978 var.db = desc->d;
5979 var.s = desc->s;
5980 var.l = desc->l;
5981 var.g = desc->g;
5982 var.avl = desc->avl;
5983 var.present = desc->p;
5984 var.unusable = !var.present;
5985 var.padding = 0;
5986
5987 kvm_set_segment(vcpu, &var, seg);
5988 return;
5989}
5990
5991static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5992 u32 msr_index, u64 *pdata)
5993{
5994 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
5995}
5996
5997static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5998 u32 msr_index, u64 data)
5999{
6000 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
6001}
6002
6003static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6004{
6005 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6006
6007 return vcpu->arch.smbase;
6008}
6009
6010static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6011{
6012 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6013
6014 vcpu->arch.smbase = smbase;
6015}
6016
6017static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6018 u32 pmc)
6019{
6020 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
6021}
6022
6023static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6024 u32 pmc, u64 *pdata)
6025{
6026 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6027}
6028
6029static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6030{
6031 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6032}
6033
6034static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6035 struct x86_instruction_info *info,
6036 enum x86_intercept_stage stage)
6037{
6038 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
6039}
6040
6041static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6042 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
6043{
6044 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
6045}
6046
6047static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6048{
6049 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6050}
6051
6052static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6053{
6054 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6055}
6056
6057static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6058{
6059 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6060}
6061
6062static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6063{
6064 return emul_to_vcpu(ctxt)->arch.hflags;
6065}
6066
6067static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6068{
6069 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6070}
6071
6072static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6073 const char *smstate)
6074{
6075 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6076}
6077
6078static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6079{
6080 kvm_smm_changed(emul_to_vcpu(ctxt));
6081}
6082
6083static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6084{
6085 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6086}
6087
6088static const struct x86_emulate_ops emulate_ops = {
6089 .read_gpr = emulator_read_gpr,
6090 .write_gpr = emulator_write_gpr,
6091 .read_std = emulator_read_std,
6092 .write_std = emulator_write_std,
6093 .read_phys = kvm_read_guest_phys_system,
6094 .fetch = kvm_fetch_guest_virt,
6095 .read_emulated = emulator_read_emulated,
6096 .write_emulated = emulator_write_emulated,
6097 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6098 .invlpg = emulator_invlpg,
6099 .pio_in_emulated = emulator_pio_in_emulated,
6100 .pio_out_emulated = emulator_pio_out_emulated,
6101 .get_segment = emulator_get_segment,
6102 .set_segment = emulator_set_segment,
6103 .get_cached_segment_base = emulator_get_cached_segment_base,
6104 .get_gdt = emulator_get_gdt,
6105 .get_idt = emulator_get_idt,
6106 .set_gdt = emulator_set_gdt,
6107 .set_idt = emulator_set_idt,
6108 .get_cr = emulator_get_cr,
6109 .set_cr = emulator_set_cr,
6110 .cpl = emulator_get_cpl,
6111 .get_dr = emulator_get_dr,
6112 .set_dr = emulator_set_dr,
6113 .get_smbase = emulator_get_smbase,
6114 .set_smbase = emulator_set_smbase,
6115 .set_msr = emulator_set_msr,
6116 .get_msr = emulator_get_msr,
6117 .check_pmc = emulator_check_pmc,
6118 .read_pmc = emulator_read_pmc,
6119 .halt = emulator_halt,
6120 .wbinvd = emulator_wbinvd,
6121 .fix_hypercall = emulator_fix_hypercall,
6122 .intercept = emulator_intercept,
6123 .get_cpuid = emulator_get_cpuid,
6124 .set_nmi_mask = emulator_set_nmi_mask,
6125 .get_hflags = emulator_get_hflags,
6126 .set_hflags = emulator_set_hflags,
6127 .pre_leave_smm = emulator_pre_leave_smm,
6128 .post_leave_smm = emulator_post_leave_smm,
6129 .set_xcr = emulator_set_xcr,
6130};
6131
6132static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6133{
6134 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
6135 /*
6136 * an sti; sti; sequence only disable interrupts for the first
6137 * instruction. So, if the last instruction, be it emulated or
6138 * not, left the system with the INT_STI flag enabled, it
6139 * means that the last instruction is an sti. We should not
6140 * leave the flag on in this case. The same goes for mov ss
6141 */
6142 if (int_shadow & mask)
6143 mask = 0;
6144 if (unlikely(int_shadow || mask)) {
6145 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6146 if (!mask)
6147 kvm_make_request(KVM_REQ_EVENT, vcpu);
6148 }
6149}
6150
6151static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6152{
6153 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6154 if (ctxt->exception.vector == PF_VECTOR)
6155 return kvm_propagate_fault(vcpu, &ctxt->exception);
6156
6157 if (ctxt->exception.error_code_valid)
6158 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6159 ctxt->exception.error_code);
6160 else
6161 kvm_queue_exception(vcpu, ctxt->exception.vector);
6162 return false;
6163}
6164
6165static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6166{
6167 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6168 int cs_db, cs_l;
6169
6170 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6171
6172 ctxt->eflags = kvm_get_rflags(vcpu);
6173 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6174
6175 ctxt->eip = kvm_rip_read(vcpu);
6176 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6177 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
6178 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
6179 cs_db ? X86EMUL_MODE_PROT32 :
6180 X86EMUL_MODE_PROT16;
6181 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6182 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6183 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6184
6185 init_decode_cache(ctxt);
6186 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6187}
6188
6189int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6190{
6191 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6192 int ret;
6193
6194 init_emulate_ctxt(vcpu);
6195
6196 ctxt->op_bytes = 2;
6197 ctxt->ad_bytes = 2;
6198 ctxt->_eip = ctxt->eip + inc_eip;
6199 ret = emulate_int_real(ctxt, irq);
6200
6201 if (ret != X86EMUL_CONTINUE)
6202 return EMULATE_FAIL;
6203
6204 ctxt->eip = ctxt->_eip;
6205 kvm_rip_write(vcpu, ctxt->eip);
6206 kvm_set_rflags(vcpu, ctxt->eflags);
6207
6208 return EMULATE_DONE;
6209}
6210EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6211
6212static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6213{
6214 int r = EMULATE_DONE;
6215
6216 ++vcpu->stat.insn_emulation_fail;
6217 trace_kvm_emulate_insn_failed(vcpu);
6218
6219 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
6220 return EMULATE_FAIL;
6221
6222 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
6223 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6224 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6225 vcpu->run->internal.ndata = 0;
6226 r = EMULATE_USER_EXIT;
6227 }
6228
6229 kvm_queue_exception(vcpu, UD_VECTOR);
6230
6231 return r;
6232}
6233
6234static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
6235 bool write_fault_to_shadow_pgtable,
6236 int emulation_type)
6237{
6238 gpa_t gpa = cr2;
6239 kvm_pfn_t pfn;
6240
6241 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6242 return false;
6243
6244 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6245 return false;
6246
6247 if (!vcpu->arch.mmu->direct_map) {
6248 /*
6249 * Write permission should be allowed since only
6250 * write access need to be emulated.
6251 */
6252 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6253
6254 /*
6255 * If the mapping is invalid in guest, let cpu retry
6256 * it to generate fault.
6257 */
6258 if (gpa == UNMAPPED_GVA)
6259 return true;
6260 }
6261
6262 /*
6263 * Do not retry the unhandleable instruction if it faults on the
6264 * readonly host memory, otherwise it will goto a infinite loop:
6265 * retry instruction -> write #PF -> emulation fail -> retry
6266 * instruction -> ...
6267 */
6268 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6269
6270 /*
6271 * If the instruction failed on the error pfn, it can not be fixed,
6272 * report the error to userspace.
6273 */
6274 if (is_error_noslot_pfn(pfn))
6275 return false;
6276
6277 kvm_release_pfn_clean(pfn);
6278
6279 /* The instructions are well-emulated on direct mmu. */
6280 if (vcpu->arch.mmu->direct_map) {
6281 unsigned int indirect_shadow_pages;
6282
6283 spin_lock(&vcpu->kvm->mmu_lock);
6284 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6285 spin_unlock(&vcpu->kvm->mmu_lock);
6286
6287 if (indirect_shadow_pages)
6288 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6289
6290 return true;
6291 }
6292
6293 /*
6294 * if emulation was due to access to shadowed page table
6295 * and it failed try to unshadow page and re-enter the
6296 * guest to let CPU execute the instruction.
6297 */
6298 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6299
6300 /*
6301 * If the access faults on its page table, it can not
6302 * be fixed by unprotecting shadow page and it should
6303 * be reported to userspace.
6304 */
6305 return !write_fault_to_shadow_pgtable;
6306}
6307
6308static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6309 unsigned long cr2, int emulation_type)
6310{
6311 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6312 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6313
6314 last_retry_eip = vcpu->arch.last_retry_eip;
6315 last_retry_addr = vcpu->arch.last_retry_addr;
6316
6317 /*
6318 * If the emulation is caused by #PF and it is non-page_table
6319 * writing instruction, it means the VM-EXIT is caused by shadow
6320 * page protected, we can zap the shadow page and retry this
6321 * instruction directly.
6322 *
6323 * Note: if the guest uses a non-page-table modifying instruction
6324 * on the PDE that points to the instruction, then we will unmap
6325 * the instruction and go to an infinite loop. So, we cache the
6326 * last retried eip and the last fault address, if we meet the eip
6327 * and the address again, we can break out of the potential infinite
6328 * loop.
6329 */
6330 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6331
6332 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6333 return false;
6334
6335 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6336 return false;
6337
6338 if (x86_page_table_writing_insn(ctxt))
6339 return false;
6340
6341 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6342 return false;
6343
6344 vcpu->arch.last_retry_eip = ctxt->eip;
6345 vcpu->arch.last_retry_addr = cr2;
6346
6347 if (!vcpu->arch.mmu->direct_map)
6348 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6349
6350 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6351
6352 return true;
6353}
6354
6355static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6356static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6357
6358static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6359{
6360 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6361 /* This is a good place to trace that we are exiting SMM. */
6362 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6363
6364 /* Process a latched INIT or SMI, if any. */
6365 kvm_make_request(KVM_REQ_EVENT, vcpu);
6366 }
6367
6368 kvm_mmu_reset_context(vcpu);
6369}
6370
6371static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6372 unsigned long *db)
6373{
6374 u32 dr6 = 0;
6375 int i;
6376 u32 enable, rwlen;
6377
6378 enable = dr7;
6379 rwlen = dr7 >> 16;
6380 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6381 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6382 dr6 |= (1 << i);
6383 return dr6;
6384}
6385
6386static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
6387{
6388 struct kvm_run *kvm_run = vcpu->run;
6389
6390 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6391 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6392 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6393 kvm_run->debug.arch.exception = DB_VECTOR;
6394 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6395 *r = EMULATE_USER_EXIT;
6396 } else {
6397 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6398 }
6399}
6400
6401int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6402{
6403 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6404 int r;
6405
6406 r = kvm_x86_ops->skip_emulated_instruction(vcpu);
6407 if (unlikely(r != EMULATE_DONE))
6408 return 0;
6409
6410 /*
6411 * rflags is the old, "raw" value of the flags. The new value has
6412 * not been saved yet.
6413 *
6414 * This is correct even for TF set by the guest, because "the
6415 * processor will not generate this exception after the instruction
6416 * that sets the TF flag".
6417 */
6418 if (unlikely(rflags & X86_EFLAGS_TF))
6419 kvm_vcpu_do_singlestep(vcpu, &r);
6420 return r == EMULATE_DONE;
6421}
6422EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6423
6424static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6425{
6426 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6427 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6428 struct kvm_run *kvm_run = vcpu->run;
6429 unsigned long eip = kvm_get_linear_rip(vcpu);
6430 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6431 vcpu->arch.guest_debug_dr7,
6432 vcpu->arch.eff_db);
6433
6434 if (dr6 != 0) {
6435 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6436 kvm_run->debug.arch.pc = eip;
6437 kvm_run->debug.arch.exception = DB_VECTOR;
6438 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6439 *r = EMULATE_USER_EXIT;
6440 return true;
6441 }
6442 }
6443
6444 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6445 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6446 unsigned long eip = kvm_get_linear_rip(vcpu);
6447 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6448 vcpu->arch.dr7,
6449 vcpu->arch.db);
6450
6451 if (dr6 != 0) {
6452 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6453 vcpu->arch.dr6 |= dr6 | DR6_RTM;
6454 kvm_queue_exception(vcpu, DB_VECTOR);
6455 *r = EMULATE_DONE;
6456 return true;
6457 }
6458 }
6459
6460 return false;
6461}
6462
6463static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6464{
6465 switch (ctxt->opcode_len) {
6466 case 1:
6467 switch (ctxt->b) {
6468 case 0xe4: /* IN */
6469 case 0xe5:
6470 case 0xec:
6471 case 0xed:
6472 case 0xe6: /* OUT */
6473 case 0xe7:
6474 case 0xee:
6475 case 0xef:
6476 case 0x6c: /* INS */
6477 case 0x6d:
6478 case 0x6e: /* OUTS */
6479 case 0x6f:
6480 return true;
6481 }
6482 break;
6483 case 2:
6484 switch (ctxt->b) {
6485 case 0x33: /* RDPMC */
6486 return true;
6487 }
6488 break;
6489 }
6490
6491 return false;
6492}
6493
6494int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6495 unsigned long cr2,
6496 int emulation_type,
6497 void *insn,
6498 int insn_len)
6499{
6500 int r;
6501 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6502 bool writeback = true;
6503 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6504
6505 vcpu->arch.l1tf_flush_l1d = true;
6506
6507 /*
6508 * Clear write_fault_to_shadow_pgtable here to ensure it is
6509 * never reused.
6510 */
6511 vcpu->arch.write_fault_to_shadow_pgtable = false;
6512 kvm_clear_exception_queue(vcpu);
6513
6514 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6515 init_emulate_ctxt(vcpu);
6516
6517 /*
6518 * We will reenter on the same instruction since
6519 * we do not set complete_userspace_io. This does not
6520 * handle watchpoints yet, those would be handled in
6521 * the emulate_ops.
6522 */
6523 if (!(emulation_type & EMULTYPE_SKIP) &&
6524 kvm_vcpu_check_breakpoint(vcpu, &r))
6525 return r;
6526
6527 ctxt->interruptibility = 0;
6528 ctxt->have_exception = false;
6529 ctxt->exception.vector = -1;
6530 ctxt->perm_ok = false;
6531
6532 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6533
6534 r = x86_decode_insn(ctxt, insn, insn_len);
6535
6536 trace_kvm_emulate_insn_start(vcpu);
6537 ++vcpu->stat.insn_emulation;
6538 if (r != EMULATION_OK) {
6539 if (emulation_type & EMULTYPE_TRAP_UD)
6540 return EMULATE_FAIL;
6541 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6542 emulation_type))
6543 return EMULATE_DONE;
6544 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6545 return EMULATE_DONE;
6546 if (emulation_type & EMULTYPE_SKIP)
6547 return EMULATE_FAIL;
6548 return handle_emulation_failure(vcpu, emulation_type);
6549 }
6550 }
6551
6552 if ((emulation_type & EMULTYPE_VMWARE) &&
6553 !is_vmware_backdoor_opcode(ctxt))
6554 return EMULATE_FAIL;
6555
6556 if (emulation_type & EMULTYPE_SKIP) {
6557 kvm_rip_write(vcpu, ctxt->_eip);
6558 if (ctxt->eflags & X86_EFLAGS_RF)
6559 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6560 kvm_x86_ops->set_interrupt_shadow(vcpu, 0);
6561 return EMULATE_DONE;
6562 }
6563
6564 if (retry_instruction(ctxt, cr2, emulation_type))
6565 return EMULATE_DONE;
6566
6567 /* this is needed for vmware backdoor interface to work since it
6568 changes registers values during IO operation */
6569 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6570 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6571 emulator_invalidate_register_cache(ctxt);
6572 }
6573
6574restart:
6575 /* Save the faulting GPA (cr2) in the address field */
6576 ctxt->exception.address = cr2;
6577
6578 r = x86_emulate_insn(ctxt);
6579
6580 if (r == EMULATION_INTERCEPTED)
6581 return EMULATE_DONE;
6582
6583 if (r == EMULATION_FAILED) {
6584 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6585 emulation_type))
6586 return EMULATE_DONE;
6587
6588 return handle_emulation_failure(vcpu, emulation_type);
6589 }
6590
6591 if (ctxt->have_exception) {
6592 r = EMULATE_DONE;
6593 if (inject_emulated_exception(vcpu))
6594 return r;
6595 } else if (vcpu->arch.pio.count) {
6596 if (!vcpu->arch.pio.in) {
6597 /* FIXME: return into emulator if single-stepping. */
6598 vcpu->arch.pio.count = 0;
6599 } else {
6600 writeback = false;
6601 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6602 }
6603 r = EMULATE_USER_EXIT;
6604 } else if (vcpu->mmio_needed) {
6605 if (!vcpu->mmio_is_write)
6606 writeback = false;
6607 r = EMULATE_USER_EXIT;
6608 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6609 } else if (r == EMULATION_RESTART)
6610 goto restart;
6611 else
6612 r = EMULATE_DONE;
6613
6614 if (writeback) {
6615 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6616 toggle_interruptibility(vcpu, ctxt->interruptibility);
6617 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6618 kvm_rip_write(vcpu, ctxt->eip);
6619 if (r == EMULATE_DONE && ctxt->tf)
6620 kvm_vcpu_do_singlestep(vcpu, &r);
6621 if (!ctxt->have_exception ||
6622 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6623 __kvm_set_rflags(vcpu, ctxt->eflags);
6624
6625 /*
6626 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6627 * do nothing, and it will be requested again as soon as
6628 * the shadow expires. But we still need to check here,
6629 * because POPF has no interrupt shadow.
6630 */
6631 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6632 kvm_make_request(KVM_REQ_EVENT, vcpu);
6633 } else
6634 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6635
6636 return r;
6637}
6638
6639int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6640{
6641 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6642}
6643EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6644
6645int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6646 void *insn, int insn_len)
6647{
6648 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6649}
6650EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
6651
6652static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6653{
6654 vcpu->arch.pio.count = 0;
6655 return 1;
6656}
6657
6658static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6659{
6660 vcpu->arch.pio.count = 0;
6661
6662 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6663 return 1;
6664
6665 return kvm_skip_emulated_instruction(vcpu);
6666}
6667
6668static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6669 unsigned short port)
6670{
6671 unsigned long val = kvm_rax_read(vcpu);
6672 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6673 size, port, &val, 1);
6674 if (ret)
6675 return ret;
6676
6677 /*
6678 * Workaround userspace that relies on old KVM behavior of %rip being
6679 * incremented prior to exiting to userspace to handle "OUT 0x7e".
6680 */
6681 if (port == 0x7e &&
6682 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6683 vcpu->arch.complete_userspace_io =
6684 complete_fast_pio_out_port_0x7e;
6685 kvm_skip_emulated_instruction(vcpu);
6686 } else {
6687 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6688 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6689 }
6690 return 0;
6691}
6692
6693static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6694{
6695 unsigned long val;
6696
6697 /* We should only ever be called with arch.pio.count equal to 1 */
6698 BUG_ON(vcpu->arch.pio.count != 1);
6699
6700 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6701 vcpu->arch.pio.count = 0;
6702 return 1;
6703 }
6704
6705 /* For size less than 4 we merge, else we zero extend */
6706 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
6707
6708 /*
6709 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6710 * the copy and tracing
6711 */
6712 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6713 vcpu->arch.pio.port, &val, 1);
6714 kvm_rax_write(vcpu, val);
6715
6716 return kvm_skip_emulated_instruction(vcpu);
6717}
6718
6719static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6720 unsigned short port)
6721{
6722 unsigned long val;
6723 int ret;
6724
6725 /* For size less than 4 we merge, else we zero extend */
6726 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
6727
6728 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6729 &val, 1);
6730 if (ret) {
6731 kvm_rax_write(vcpu, val);
6732 return ret;
6733 }
6734
6735 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6736 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6737
6738 return 0;
6739}
6740
6741int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6742{
6743 int ret;
6744
6745 if (in)
6746 ret = kvm_fast_pio_in(vcpu, size, port);
6747 else
6748 ret = kvm_fast_pio_out(vcpu, size, port);
6749 return ret && kvm_skip_emulated_instruction(vcpu);
6750}
6751EXPORT_SYMBOL_GPL(kvm_fast_pio);
6752
6753static int kvmclock_cpu_down_prep(unsigned int cpu)
6754{
6755 __this_cpu_write(cpu_tsc_khz, 0);
6756 return 0;
6757}
6758
6759static void tsc_khz_changed(void *data)
6760{
6761 struct cpufreq_freqs *freq = data;
6762 unsigned long khz = 0;
6763
6764 if (data)
6765 khz = freq->new;
6766 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6767 khz = cpufreq_quick_get(raw_smp_processor_id());
6768 if (!khz)
6769 khz = tsc_khz;
6770 __this_cpu_write(cpu_tsc_khz, khz);
6771}
6772
6773#ifdef CONFIG_X86_64
6774static void kvm_hyperv_tsc_notifier(void)
6775{
6776 struct kvm *kvm;
6777 struct kvm_vcpu *vcpu;
6778 int cpu;
6779
6780 mutex_lock(&kvm_lock);
6781 list_for_each_entry(kvm, &vm_list, vm_list)
6782 kvm_make_mclock_inprogress_request(kvm);
6783
6784 hyperv_stop_tsc_emulation();
6785
6786 /* TSC frequency always matches when on Hyper-V */
6787 for_each_present_cpu(cpu)
6788 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6789 kvm_max_guest_tsc_khz = tsc_khz;
6790
6791 list_for_each_entry(kvm, &vm_list, vm_list) {
6792 struct kvm_arch *ka = &kvm->arch;
6793
6794 spin_lock(&ka->pvclock_gtod_sync_lock);
6795
6796 pvclock_update_vm_gtod_copy(kvm);
6797
6798 kvm_for_each_vcpu(cpu, vcpu, kvm)
6799 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6800
6801 kvm_for_each_vcpu(cpu, vcpu, kvm)
6802 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6803
6804 spin_unlock(&ka->pvclock_gtod_sync_lock);
6805 }
6806 mutex_unlock(&kvm_lock);
6807}
6808#endif
6809
6810static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
6811{
6812 struct kvm *kvm;
6813 struct kvm_vcpu *vcpu;
6814 int i, send_ipi = 0;
6815
6816 /*
6817 * We allow guests to temporarily run on slowing clocks,
6818 * provided we notify them after, or to run on accelerating
6819 * clocks, provided we notify them before. Thus time never
6820 * goes backwards.
6821 *
6822 * However, we have a problem. We can't atomically update
6823 * the frequency of a given CPU from this function; it is
6824 * merely a notifier, which can be called from any CPU.
6825 * Changing the TSC frequency at arbitrary points in time
6826 * requires a recomputation of local variables related to
6827 * the TSC for each VCPU. We must flag these local variables
6828 * to be updated and be sure the update takes place with the
6829 * new frequency before any guests proceed.
6830 *
6831 * Unfortunately, the combination of hotplug CPU and frequency
6832 * change creates an intractable locking scenario; the order
6833 * of when these callouts happen is undefined with respect to
6834 * CPU hotplug, and they can race with each other. As such,
6835 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6836 * undefined; you can actually have a CPU frequency change take
6837 * place in between the computation of X and the setting of the
6838 * variable. To protect against this problem, all updates of
6839 * the per_cpu tsc_khz variable are done in an interrupt
6840 * protected IPI, and all callers wishing to update the value
6841 * must wait for a synchronous IPI to complete (which is trivial
6842 * if the caller is on the CPU already). This establishes the
6843 * necessary total order on variable updates.
6844 *
6845 * Note that because a guest time update may take place
6846 * anytime after the setting of the VCPU's request bit, the
6847 * correct TSC value must be set before the request. However,
6848 * to ensure the update actually makes it to any guest which
6849 * starts running in hardware virtualization between the set
6850 * and the acquisition of the spinlock, we must also ping the
6851 * CPU after setting the request bit.
6852 *
6853 */
6854
6855 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
6856
6857 mutex_lock(&kvm_lock);
6858 list_for_each_entry(kvm, &vm_list, vm_list) {
6859 kvm_for_each_vcpu(i, vcpu, kvm) {
6860 if (vcpu->cpu != cpu)
6861 continue;
6862 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6863 if (vcpu->cpu != raw_smp_processor_id())
6864 send_ipi = 1;
6865 }
6866 }
6867 mutex_unlock(&kvm_lock);
6868
6869 if (freq->old < freq->new && send_ipi) {
6870 /*
6871 * We upscale the frequency. Must make the guest
6872 * doesn't see old kvmclock values while running with
6873 * the new frequency, otherwise we risk the guest sees
6874 * time go backwards.
6875 *
6876 * In case we update the frequency for another cpu
6877 * (which might be in guest context) send an interrupt
6878 * to kick the cpu out of guest context. Next time
6879 * guest context is entered kvmclock will be updated,
6880 * so the guest will not see stale values.
6881 */
6882 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
6883 }
6884}
6885
6886static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6887 void *data)
6888{
6889 struct cpufreq_freqs *freq = data;
6890 int cpu;
6891
6892 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6893 return 0;
6894 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6895 return 0;
6896
6897 for_each_cpu(cpu, freq->policy->cpus)
6898 __kvmclock_cpufreq_notifier(freq, cpu);
6899
6900 return 0;
6901}
6902
6903static struct notifier_block kvmclock_cpufreq_notifier_block = {
6904 .notifier_call = kvmclock_cpufreq_notifier
6905};
6906
6907static int kvmclock_cpu_online(unsigned int cpu)
6908{
6909 tsc_khz_changed(NULL);
6910 return 0;
6911}
6912
6913static void kvm_timer_init(void)
6914{
6915 max_tsc_khz = tsc_khz;
6916
6917 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
6918#ifdef CONFIG_CPU_FREQ
6919 struct cpufreq_policy policy;
6920 int cpu;
6921
6922 memset(&policy, 0, sizeof(policy));
6923 cpu = get_cpu();
6924 cpufreq_get_policy(&policy, cpu);
6925 if (policy.cpuinfo.max_freq)
6926 max_tsc_khz = policy.cpuinfo.max_freq;
6927 put_cpu();
6928#endif
6929 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6930 CPUFREQ_TRANSITION_NOTIFIER);
6931 }
6932
6933 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
6934 kvmclock_cpu_online, kvmclock_cpu_down_prep);
6935}
6936
6937DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6938EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
6939
6940int kvm_is_in_guest(void)
6941{
6942 return __this_cpu_read(current_vcpu) != NULL;
6943}
6944
6945static int kvm_is_user_mode(void)
6946{
6947 int user_mode = 3;
6948
6949 if (__this_cpu_read(current_vcpu))
6950 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
6951
6952 return user_mode != 0;
6953}
6954
6955static unsigned long kvm_get_guest_ip(void)
6956{
6957 unsigned long ip = 0;
6958
6959 if (__this_cpu_read(current_vcpu))
6960 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
6961
6962 return ip;
6963}
6964
6965static void kvm_handle_intel_pt_intr(void)
6966{
6967 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
6968
6969 kvm_make_request(KVM_REQ_PMI, vcpu);
6970 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
6971 (unsigned long *)&vcpu->arch.pmu.global_status);
6972}
6973
6974static struct perf_guest_info_callbacks kvm_guest_cbs = {
6975 .is_in_guest = kvm_is_in_guest,
6976 .is_user_mode = kvm_is_user_mode,
6977 .get_guest_ip = kvm_get_guest_ip,
6978 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
6979};
6980
6981#ifdef CONFIG_X86_64
6982static void pvclock_gtod_update_fn(struct work_struct *work)
6983{
6984 struct kvm *kvm;
6985
6986 struct kvm_vcpu *vcpu;
6987 int i;
6988
6989 mutex_lock(&kvm_lock);
6990 list_for_each_entry(kvm, &vm_list, vm_list)
6991 kvm_for_each_vcpu(i, vcpu, kvm)
6992 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
6993 atomic_set(&kvm_guest_has_master_clock, 0);
6994 mutex_unlock(&kvm_lock);
6995}
6996
6997static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6998
6999/*
7000 * Notification about pvclock gtod data update.
7001 */
7002static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7003 void *priv)
7004{
7005 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7006 struct timekeeper *tk = priv;
7007
7008 update_pvclock_gtod(tk);
7009
7010 /* disable master clock if host does not trust, or does not
7011 * use, TSC based clocksource.
7012 */
7013 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7014 atomic_read(&kvm_guest_has_master_clock) != 0)
7015 queue_work(system_long_wq, &pvclock_gtod_work);
7016
7017 return 0;
7018}
7019
7020static struct notifier_block pvclock_gtod_notifier = {
7021 .notifier_call = pvclock_gtod_notify,
7022};
7023#endif
7024
7025int kvm_arch_init(void *opaque)
7026{
7027 int r;
7028 struct kvm_x86_ops *ops = opaque;
7029
7030 if (kvm_x86_ops) {
7031 printk(KERN_ERR "kvm: already loaded the other module\n");
7032 r = -EEXIST;
7033 goto out;
7034 }
7035
7036 if (!ops->cpu_has_kvm_support()) {
7037 printk(KERN_ERR "kvm: no hardware support\n");
7038 r = -EOPNOTSUPP;
7039 goto out;
7040 }
7041 if (ops->disabled_by_bios()) {
7042 printk(KERN_ERR "kvm: disabled by bios\n");
7043 r = -EOPNOTSUPP;
7044 goto out;
7045 }
7046
7047 /*
7048 * KVM explicitly assumes that the guest has an FPU and
7049 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7050 * vCPU's FPU state as a fxregs_state struct.
7051 */
7052 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7053 printk(KERN_ERR "kvm: inadequate fpu\n");
7054 r = -EOPNOTSUPP;
7055 goto out;
7056 }
7057
7058 r = -ENOMEM;
7059 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7060 __alignof__(struct fpu), SLAB_ACCOUNT,
7061 NULL);
7062 if (!x86_fpu_cache) {
7063 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7064 goto out;
7065 }
7066
7067 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7068 if (!shared_msrs) {
7069 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
7070 goto out_free_x86_fpu_cache;
7071 }
7072
7073 r = kvm_mmu_module_init();
7074 if (r)
7075 goto out_free_percpu;
7076
7077 kvm_x86_ops = ops;
7078
7079 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7080 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7081 PT_PRESENT_MASK, 0, sme_me_mask);
7082 kvm_timer_init();
7083
7084 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7085
7086 if (boot_cpu_has(X86_FEATURE_XSAVE))
7087 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7088
7089 kvm_lapic_init();
7090 if (pi_inject_timer == -1)
7091 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7092#ifdef CONFIG_X86_64
7093 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7094
7095 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7096 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7097#endif
7098
7099 return 0;
7100
7101out_free_percpu:
7102 free_percpu(shared_msrs);
7103out_free_x86_fpu_cache:
7104 kmem_cache_destroy(x86_fpu_cache);
7105out:
7106 return r;
7107}
7108
7109void kvm_arch_exit(void)
7110{
7111#ifdef CONFIG_X86_64
7112 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7113 clear_hv_tscchange_cb();
7114#endif
7115 kvm_lapic_exit();
7116 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7117
7118 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7119 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7120 CPUFREQ_TRANSITION_NOTIFIER);
7121 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7122#ifdef CONFIG_X86_64
7123 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7124#endif
7125 kvm_x86_ops = NULL;
7126 kvm_mmu_module_exit();
7127 free_percpu(shared_msrs);
7128 kmem_cache_destroy(x86_fpu_cache);
7129}
7130
7131int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7132{
7133 ++vcpu->stat.halt_exits;
7134 if (lapic_in_kernel(vcpu)) {
7135 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7136 return 1;
7137 } else {
7138 vcpu->run->exit_reason = KVM_EXIT_HLT;
7139 return 0;
7140 }
7141}
7142EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7143
7144int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7145{
7146 int ret = kvm_skip_emulated_instruction(vcpu);
7147 /*
7148 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7149 * KVM_EXIT_DEBUG here.
7150 */
7151 return kvm_vcpu_halt(vcpu) && ret;
7152}
7153EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7154
7155#ifdef CONFIG_X86_64
7156static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7157 unsigned long clock_type)
7158{
7159 struct kvm_clock_pairing clock_pairing;
7160 struct timespec64 ts;
7161 u64 cycle;
7162 int ret;
7163
7164 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7165 return -KVM_EOPNOTSUPP;
7166
7167 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7168 return -KVM_EOPNOTSUPP;
7169
7170 clock_pairing.sec = ts.tv_sec;
7171 clock_pairing.nsec = ts.tv_nsec;
7172 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7173 clock_pairing.flags = 0;
7174 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7175
7176 ret = 0;
7177 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7178 sizeof(struct kvm_clock_pairing)))
7179 ret = -KVM_EFAULT;
7180
7181 return ret;
7182}
7183#endif
7184
7185/*
7186 * kvm_pv_kick_cpu_op: Kick a vcpu.
7187 *
7188 * @apicid - apicid of vcpu to be kicked.
7189 */
7190static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7191{
7192 struct kvm_lapic_irq lapic_irq;
7193
7194 lapic_irq.shorthand = 0;
7195 lapic_irq.dest_mode = 0;
7196 lapic_irq.level = 0;
7197 lapic_irq.dest_id = apicid;
7198 lapic_irq.msi_redir_hint = false;
7199
7200 lapic_irq.delivery_mode = APIC_DM_REMRD;
7201 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7202}
7203
7204void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7205{
7206 if (!lapic_in_kernel(vcpu)) {
7207 WARN_ON_ONCE(vcpu->arch.apicv_active);
7208 return;
7209 }
7210 if (!vcpu->arch.apicv_active)
7211 return;
7212
7213 vcpu->arch.apicv_active = false;
7214 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7215}
7216
7217static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7218{
7219 struct kvm_vcpu *target = NULL;
7220 struct kvm_apic_map *map;
7221
7222 rcu_read_lock();
7223 map = rcu_dereference(kvm->arch.apic_map);
7224
7225 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7226 target = map->phys_map[dest_id]->vcpu;
7227
7228 rcu_read_unlock();
7229
7230 if (target && READ_ONCE(target->ready))
7231 kvm_vcpu_yield_to(target);
7232}
7233
7234int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7235{
7236 unsigned long nr, a0, a1, a2, a3, ret;
7237 int op_64_bit;
7238
7239 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7240 return kvm_hv_hypercall(vcpu);
7241
7242 nr = kvm_rax_read(vcpu);
7243 a0 = kvm_rbx_read(vcpu);
7244 a1 = kvm_rcx_read(vcpu);
7245 a2 = kvm_rdx_read(vcpu);
7246 a3 = kvm_rsi_read(vcpu);
7247
7248 trace_kvm_hypercall(nr, a0, a1, a2, a3);
7249
7250 op_64_bit = is_64_bit_mode(vcpu);
7251 if (!op_64_bit) {
7252 nr &= 0xFFFFFFFF;
7253 a0 &= 0xFFFFFFFF;
7254 a1 &= 0xFFFFFFFF;
7255 a2 &= 0xFFFFFFFF;
7256 a3 &= 0xFFFFFFFF;
7257 }
7258
7259 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7260 ret = -KVM_EPERM;
7261 goto out;
7262 }
7263
7264 switch (nr) {
7265 case KVM_HC_VAPIC_POLL_IRQ:
7266 ret = 0;
7267 break;
7268 case KVM_HC_KICK_CPU:
7269 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7270 kvm_sched_yield(vcpu->kvm, a1);
7271 ret = 0;
7272 break;
7273#ifdef CONFIG_X86_64
7274 case KVM_HC_CLOCK_PAIRING:
7275 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7276 break;
7277#endif
7278 case KVM_HC_SEND_IPI:
7279 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7280 break;
7281 case KVM_HC_SCHED_YIELD:
7282 kvm_sched_yield(vcpu->kvm, a0);
7283 ret = 0;
7284 break;
7285 default:
7286 ret = -KVM_ENOSYS;
7287 break;
7288 }
7289out:
7290 if (!op_64_bit)
7291 ret = (u32)ret;
7292 kvm_rax_write(vcpu, ret);
7293
7294 ++vcpu->stat.hypercalls;
7295 return kvm_skip_emulated_instruction(vcpu);
7296}
7297EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7298
7299static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7300{
7301 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7302 char instruction[3];
7303 unsigned long rip = kvm_rip_read(vcpu);
7304
7305 kvm_x86_ops->patch_hypercall(vcpu, instruction);
7306
7307 return emulator_write_emulated(ctxt, rip, instruction, 3,
7308 &ctxt->exception);
7309}
7310
7311static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7312{
7313 return vcpu->run->request_interrupt_window &&
7314 likely(!pic_in_kernel(vcpu->kvm));
7315}
7316
7317static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7318{
7319 struct kvm_run *kvm_run = vcpu->run;
7320
7321 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7322 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7323 kvm_run->cr8 = kvm_get_cr8(vcpu);
7324 kvm_run->apic_base = kvm_get_apic_base(vcpu);
7325 kvm_run->ready_for_interrupt_injection =
7326 pic_in_kernel(vcpu->kvm) ||
7327 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7328}
7329
7330static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7331{
7332 int max_irr, tpr;
7333
7334 if (!kvm_x86_ops->update_cr8_intercept)
7335 return;
7336
7337 if (!lapic_in_kernel(vcpu))
7338 return;
7339
7340 if (vcpu->arch.apicv_active)
7341 return;
7342
7343 if (!vcpu->arch.apic->vapic_addr)
7344 max_irr = kvm_lapic_find_highest_irr(vcpu);
7345 else
7346 max_irr = -1;
7347
7348 if (max_irr != -1)
7349 max_irr >>= 4;
7350
7351 tpr = kvm_lapic_get_cr8(vcpu);
7352
7353 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7354}
7355
7356static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
7357{
7358 int r;
7359
7360 /* try to reinject previous events if any */
7361
7362 if (vcpu->arch.exception.injected)
7363 kvm_x86_ops->queue_exception(vcpu);
7364 /*
7365 * Do not inject an NMI or interrupt if there is a pending
7366 * exception. Exceptions and interrupts are recognized at
7367 * instruction boundaries, i.e. the start of an instruction.
7368 * Trap-like exceptions, e.g. #DB, have higher priority than
7369 * NMIs and interrupts, i.e. traps are recognized before an
7370 * NMI/interrupt that's pending on the same instruction.
7371 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7372 * priority, but are only generated (pended) during instruction
7373 * execution, i.e. a pending fault-like exception means the
7374 * fault occurred on the *previous* instruction and must be
7375 * serviced prior to recognizing any new events in order to
7376 * fully complete the previous instruction.
7377 */
7378 else if (!vcpu->arch.exception.pending) {
7379 if (vcpu->arch.nmi_injected)
7380 kvm_x86_ops->set_nmi(vcpu);
7381 else if (vcpu->arch.interrupt.injected)
7382 kvm_x86_ops->set_irq(vcpu);
7383 }
7384
7385 /*
7386 * Call check_nested_events() even if we reinjected a previous event
7387 * in order for caller to determine if it should require immediate-exit
7388 * from L2 to L1 due to pending L1 events which require exit
7389 * from L2 to L1.
7390 */
7391 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7392 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7393 if (r != 0)
7394 return r;
7395 }
7396
7397 /* try to inject new event if pending */
7398 if (vcpu->arch.exception.pending) {
7399 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7400 vcpu->arch.exception.has_error_code,
7401 vcpu->arch.exception.error_code);
7402
7403 WARN_ON_ONCE(vcpu->arch.exception.injected);
7404 vcpu->arch.exception.pending = false;
7405 vcpu->arch.exception.injected = true;
7406
7407 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7408 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7409 X86_EFLAGS_RF);
7410
7411 if (vcpu->arch.exception.nr == DB_VECTOR) {
7412 /*
7413 * This code assumes that nSVM doesn't use
7414 * check_nested_events(). If it does, the
7415 * DR6/DR7 changes should happen before L1
7416 * gets a #VMEXIT for an intercepted #DB in
7417 * L2. (Under VMX, on the other hand, the
7418 * DR6/DR7 changes should not happen in the
7419 * event of a VM-exit to L1 for an intercepted
7420 * #DB in L2.)
7421 */
7422 kvm_deliver_exception_payload(vcpu);
7423 if (vcpu->arch.dr7 & DR7_GD) {
7424 vcpu->arch.dr7 &= ~DR7_GD;
7425 kvm_update_dr7(vcpu);
7426 }
7427 }
7428
7429 kvm_x86_ops->queue_exception(vcpu);
7430 }
7431
7432 /* Don't consider new event if we re-injected an event */
7433 if (kvm_event_needs_reinjection(vcpu))
7434 return 0;
7435
7436 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7437 kvm_x86_ops->smi_allowed(vcpu)) {
7438 vcpu->arch.smi_pending = false;
7439 ++vcpu->arch.smi_count;
7440 enter_smm(vcpu);
7441 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
7442 --vcpu->arch.nmi_pending;
7443 vcpu->arch.nmi_injected = true;
7444 kvm_x86_ops->set_nmi(vcpu);
7445 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
7446 /*
7447 * Because interrupts can be injected asynchronously, we are
7448 * calling check_nested_events again here to avoid a race condition.
7449 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7450 * proposal and current concerns. Perhaps we should be setting
7451 * KVM_REQ_EVENT only on certain events and not unconditionally?
7452 */
7453 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7454 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7455 if (r != 0)
7456 return r;
7457 }
7458 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
7459 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7460 false);
7461 kvm_x86_ops->set_irq(vcpu);
7462 }
7463 }
7464
7465 return 0;
7466}
7467
7468static void process_nmi(struct kvm_vcpu *vcpu)
7469{
7470 unsigned limit = 2;
7471
7472 /*
7473 * x86 is limited to one NMI running, and one NMI pending after it.
7474 * If an NMI is already in progress, limit further NMIs to just one.
7475 * Otherwise, allow two (and we'll inject the first one immediately).
7476 */
7477 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7478 limit = 1;
7479
7480 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7481 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7482 kvm_make_request(KVM_REQ_EVENT, vcpu);
7483}
7484
7485static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7486{
7487 u32 flags = 0;
7488 flags |= seg->g << 23;
7489 flags |= seg->db << 22;
7490 flags |= seg->l << 21;
7491 flags |= seg->avl << 20;
7492 flags |= seg->present << 15;
7493 flags |= seg->dpl << 13;
7494 flags |= seg->s << 12;
7495 flags |= seg->type << 8;
7496 return flags;
7497}
7498
7499static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7500{
7501 struct kvm_segment seg;
7502 int offset;
7503
7504 kvm_get_segment(vcpu, &seg, n);
7505 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7506
7507 if (n < 3)
7508 offset = 0x7f84 + n * 12;
7509 else
7510 offset = 0x7f2c + (n - 3) * 12;
7511
7512 put_smstate(u32, buf, offset + 8, seg.base);
7513 put_smstate(u32, buf, offset + 4, seg.limit);
7514 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7515}
7516
7517#ifdef CONFIG_X86_64
7518static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7519{
7520 struct kvm_segment seg;
7521 int offset;
7522 u16 flags;
7523
7524 kvm_get_segment(vcpu, &seg, n);
7525 offset = 0x7e00 + n * 16;
7526
7527 flags = enter_smm_get_segment_flags(&seg) >> 8;
7528 put_smstate(u16, buf, offset, seg.selector);
7529 put_smstate(u16, buf, offset + 2, flags);
7530 put_smstate(u32, buf, offset + 4, seg.limit);
7531 put_smstate(u64, buf, offset + 8, seg.base);
7532}
7533#endif
7534
7535static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7536{
7537 struct desc_ptr dt;
7538 struct kvm_segment seg;
7539 unsigned long val;
7540 int i;
7541
7542 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7543 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7544 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7545 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7546
7547 for (i = 0; i < 8; i++)
7548 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7549
7550 kvm_get_dr(vcpu, 6, &val);
7551 put_smstate(u32, buf, 0x7fcc, (u32)val);
7552 kvm_get_dr(vcpu, 7, &val);
7553 put_smstate(u32, buf, 0x7fc8, (u32)val);
7554
7555 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7556 put_smstate(u32, buf, 0x7fc4, seg.selector);
7557 put_smstate(u32, buf, 0x7f64, seg.base);
7558 put_smstate(u32, buf, 0x7f60, seg.limit);
7559 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7560
7561 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7562 put_smstate(u32, buf, 0x7fc0, seg.selector);
7563 put_smstate(u32, buf, 0x7f80, seg.base);
7564 put_smstate(u32, buf, 0x7f7c, seg.limit);
7565 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7566
7567 kvm_x86_ops->get_gdt(vcpu, &dt);
7568 put_smstate(u32, buf, 0x7f74, dt.address);
7569 put_smstate(u32, buf, 0x7f70, dt.size);
7570
7571 kvm_x86_ops->get_idt(vcpu, &dt);
7572 put_smstate(u32, buf, 0x7f58, dt.address);
7573 put_smstate(u32, buf, 0x7f54, dt.size);
7574
7575 for (i = 0; i < 6; i++)
7576 enter_smm_save_seg_32(vcpu, buf, i);
7577
7578 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7579
7580 /* revision id */
7581 put_smstate(u32, buf, 0x7efc, 0x00020000);
7582 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7583}
7584
7585#ifdef CONFIG_X86_64
7586static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7587{
7588 struct desc_ptr dt;
7589 struct kvm_segment seg;
7590 unsigned long val;
7591 int i;
7592
7593 for (i = 0; i < 16; i++)
7594 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7595
7596 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7597 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7598
7599 kvm_get_dr(vcpu, 6, &val);
7600 put_smstate(u64, buf, 0x7f68, val);
7601 kvm_get_dr(vcpu, 7, &val);
7602 put_smstate(u64, buf, 0x7f60, val);
7603
7604 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7605 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7606 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7607
7608 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7609
7610 /* revision id */
7611 put_smstate(u32, buf, 0x7efc, 0x00020064);
7612
7613 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7614
7615 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7616 put_smstate(u16, buf, 0x7e90, seg.selector);
7617 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7618 put_smstate(u32, buf, 0x7e94, seg.limit);
7619 put_smstate(u64, buf, 0x7e98, seg.base);
7620
7621 kvm_x86_ops->get_idt(vcpu, &dt);
7622 put_smstate(u32, buf, 0x7e84, dt.size);
7623 put_smstate(u64, buf, 0x7e88, dt.address);
7624
7625 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7626 put_smstate(u16, buf, 0x7e70, seg.selector);
7627 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7628 put_smstate(u32, buf, 0x7e74, seg.limit);
7629 put_smstate(u64, buf, 0x7e78, seg.base);
7630
7631 kvm_x86_ops->get_gdt(vcpu, &dt);
7632 put_smstate(u32, buf, 0x7e64, dt.size);
7633 put_smstate(u64, buf, 0x7e68, dt.address);
7634
7635 for (i = 0; i < 6; i++)
7636 enter_smm_save_seg_64(vcpu, buf, i);
7637}
7638#endif
7639
7640static void enter_smm(struct kvm_vcpu *vcpu)
7641{
7642 struct kvm_segment cs, ds;
7643 struct desc_ptr dt;
7644 char buf[512];
7645 u32 cr0;
7646
7647 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7648 memset(buf, 0, 512);
7649#ifdef CONFIG_X86_64
7650 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7651 enter_smm_save_state_64(vcpu, buf);
7652 else
7653#endif
7654 enter_smm_save_state_32(vcpu, buf);
7655
7656 /*
7657 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7658 * vCPU state (e.g. leave guest mode) after we've saved the state into
7659 * the SMM state-save area.
7660 */
7661 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7662
7663 vcpu->arch.hflags |= HF_SMM_MASK;
7664 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7665
7666 if (kvm_x86_ops->get_nmi_mask(vcpu))
7667 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7668 else
7669 kvm_x86_ops->set_nmi_mask(vcpu, true);
7670
7671 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7672 kvm_rip_write(vcpu, 0x8000);
7673
7674 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7675 kvm_x86_ops->set_cr0(vcpu, cr0);
7676 vcpu->arch.cr0 = cr0;
7677
7678 kvm_x86_ops->set_cr4(vcpu, 0);
7679
7680 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7681 dt.address = dt.size = 0;
7682 kvm_x86_ops->set_idt(vcpu, &dt);
7683
7684 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7685
7686 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7687 cs.base = vcpu->arch.smbase;
7688
7689 ds.selector = 0;
7690 ds.base = 0;
7691
7692 cs.limit = ds.limit = 0xffffffff;
7693 cs.type = ds.type = 0x3;
7694 cs.dpl = ds.dpl = 0;
7695 cs.db = ds.db = 0;
7696 cs.s = ds.s = 1;
7697 cs.l = ds.l = 0;
7698 cs.g = ds.g = 1;
7699 cs.avl = ds.avl = 0;
7700 cs.present = ds.present = 1;
7701 cs.unusable = ds.unusable = 0;
7702 cs.padding = ds.padding = 0;
7703
7704 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7705 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7706 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7707 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7708 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7709 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7710
7711#ifdef CONFIG_X86_64
7712 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7713 kvm_x86_ops->set_efer(vcpu, 0);
7714#endif
7715
7716 kvm_update_cpuid(vcpu);
7717 kvm_mmu_reset_context(vcpu);
7718}
7719
7720static void process_smi(struct kvm_vcpu *vcpu)
7721{
7722 vcpu->arch.smi_pending = true;
7723 kvm_make_request(KVM_REQ_EVENT, vcpu);
7724}
7725
7726void kvm_make_scan_ioapic_request(struct kvm *kvm)
7727{
7728 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7729}
7730
7731static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
7732{
7733 if (!kvm_apic_present(vcpu))
7734 return;
7735
7736 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
7737
7738 if (irqchip_split(vcpu->kvm))
7739 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
7740 else {
7741 if (vcpu->arch.apicv_active)
7742 kvm_x86_ops->sync_pir_to_irr(vcpu);
7743 if (ioapic_in_kernel(vcpu->kvm))
7744 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
7745 }
7746
7747 if (is_guest_mode(vcpu))
7748 vcpu->arch.load_eoi_exitmap_pending = true;
7749 else
7750 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7751}
7752
7753static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7754{
7755 u64 eoi_exit_bitmap[4];
7756
7757 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7758 return;
7759
7760 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7761 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7762 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
7763}
7764
7765int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7766 unsigned long start, unsigned long end,
7767 bool blockable)
7768{
7769 unsigned long apic_address;
7770
7771 /*
7772 * The physical address of apic access page is stored in the VMCS.
7773 * Update it when it becomes invalid.
7774 */
7775 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7776 if (start <= apic_address && apic_address < end)
7777 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7778
7779 return 0;
7780}
7781
7782void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7783{
7784 struct page *page = NULL;
7785
7786 if (!lapic_in_kernel(vcpu))
7787 return;
7788
7789 if (!kvm_x86_ops->set_apic_access_page_addr)
7790 return;
7791
7792 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7793 if (is_error_page(page))
7794 return;
7795 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7796
7797 /*
7798 * Do not pin apic access page in memory, the MMU notifier
7799 * will call us again if it is migrated or swapped out.
7800 */
7801 put_page(page);
7802}
7803EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7804
7805void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7806{
7807 smp_send_reschedule(vcpu->cpu);
7808}
7809EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7810
7811/*
7812 * Returns 1 to let vcpu_run() continue the guest execution loop without
7813 * exiting to the userspace. Otherwise, the value will be returned to the
7814 * userspace.
7815 */
7816static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
7817{
7818 int r;
7819 bool req_int_win =
7820 dm_request_for_irq_injection(vcpu) &&
7821 kvm_cpu_accept_dm_intr(vcpu);
7822
7823 bool req_immediate_exit = false;
7824
7825 if (kvm_request_pending(vcpu)) {
7826 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7827 kvm_x86_ops->get_vmcs12_pages(vcpu);
7828 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
7829 kvm_mmu_unload(vcpu);
7830 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
7831 __kvm_migrate_timers(vcpu);
7832 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7833 kvm_gen_update_masterclock(vcpu->kvm);
7834 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7835 kvm_gen_kvmclock_update(vcpu);
7836 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7837 r = kvm_guest_time_update(vcpu);
7838 if (unlikely(r))
7839 goto out;
7840 }
7841 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
7842 kvm_mmu_sync_roots(vcpu);
7843 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7844 kvm_mmu_load_cr3(vcpu);
7845 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
7846 kvm_vcpu_flush_tlb(vcpu, true);
7847 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
7848 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
7849 r = 0;
7850 goto out;
7851 }
7852 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
7853 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
7854 vcpu->mmio_needed = 0;
7855 r = 0;
7856 goto out;
7857 }
7858 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7859 /* Page is swapped out. Do synthetic halt */
7860 vcpu->arch.apf.halted = true;
7861 r = 1;
7862 goto out;
7863 }
7864 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7865 record_steal_time(vcpu);
7866 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7867 process_smi(vcpu);
7868 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7869 process_nmi(vcpu);
7870 if (kvm_check_request(KVM_REQ_PMU, vcpu))
7871 kvm_pmu_handle_event(vcpu);
7872 if (kvm_check_request(KVM_REQ_PMI, vcpu))
7873 kvm_pmu_deliver_pmi(vcpu);
7874 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7875 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7876 if (test_bit(vcpu->arch.pending_ioapic_eoi,
7877 vcpu->arch.ioapic_handled_vectors)) {
7878 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7879 vcpu->run->eoi.vector =
7880 vcpu->arch.pending_ioapic_eoi;
7881 r = 0;
7882 goto out;
7883 }
7884 }
7885 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7886 vcpu_scan_ioapic(vcpu);
7887 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7888 vcpu_load_eoi_exitmap(vcpu);
7889 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7890 kvm_vcpu_reload_apic_access_page(vcpu);
7891 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7892 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7893 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7894 r = 0;
7895 goto out;
7896 }
7897 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7898 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7899 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7900 r = 0;
7901 goto out;
7902 }
7903 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7904 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7905 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7906 r = 0;
7907 goto out;
7908 }
7909
7910 /*
7911 * KVM_REQ_HV_STIMER has to be processed after
7912 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7913 * depend on the guest clock being up-to-date
7914 */
7915 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7916 kvm_hv_process_stimers(vcpu);
7917 }
7918
7919 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
7920 ++vcpu->stat.req_event;
7921 kvm_apic_accept_events(vcpu);
7922 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7923 r = 1;
7924 goto out;
7925 }
7926
7927 if (inject_pending_event(vcpu, req_int_win) != 0)
7928 req_immediate_exit = true;
7929 else {
7930 /* Enable SMI/NMI/IRQ window open exits if needed.
7931 *
7932 * SMIs have three cases:
7933 * 1) They can be nested, and then there is nothing to
7934 * do here because RSM will cause a vmexit anyway.
7935 * 2) There is an ISA-specific reason why SMI cannot be
7936 * injected, and the moment when this changes can be
7937 * intercepted.
7938 * 3) Or the SMI can be pending because
7939 * inject_pending_event has completed the injection
7940 * of an IRQ or NMI from the previous vmexit, and
7941 * then we request an immediate exit to inject the
7942 * SMI.
7943 */
7944 if (vcpu->arch.smi_pending && !is_smm(vcpu))
7945 if (!kvm_x86_ops->enable_smi_window(vcpu))
7946 req_immediate_exit = true;
7947 if (vcpu->arch.nmi_pending)
7948 kvm_x86_ops->enable_nmi_window(vcpu);
7949 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7950 kvm_x86_ops->enable_irq_window(vcpu);
7951 WARN_ON(vcpu->arch.exception.pending);
7952 }
7953
7954 if (kvm_lapic_enabled(vcpu)) {
7955 update_cr8_intercept(vcpu);
7956 kvm_lapic_sync_to_vapic(vcpu);
7957 }
7958 }
7959
7960 r = kvm_mmu_reload(vcpu);
7961 if (unlikely(r)) {
7962 goto cancel_injection;
7963 }
7964
7965 preempt_disable();
7966
7967 kvm_x86_ops->prepare_guest_switch(vcpu);
7968
7969 /*
7970 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7971 * IPI are then delayed after guest entry, which ensures that they
7972 * result in virtual interrupt delivery.
7973 */
7974 local_irq_disable();
7975 vcpu->mode = IN_GUEST_MODE;
7976
7977 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7978
7979 /*
7980 * 1) We should set ->mode before checking ->requests. Please see
7981 * the comment in kvm_vcpu_exiting_guest_mode().
7982 *
7983 * 2) For APICv, we should set ->mode before checking PID.ON. This
7984 * pairs with the memory barrier implicit in pi_test_and_set_on
7985 * (see vmx_deliver_posted_interrupt).
7986 *
7987 * 3) This also orders the write to mode from any reads to the page
7988 * tables done while the VCPU is running. Please see the comment
7989 * in kvm_flush_remote_tlbs.
7990 */
7991 smp_mb__after_srcu_read_unlock();
7992
7993 /*
7994 * This handles the case where a posted interrupt was
7995 * notified with kvm_vcpu_kick.
7996 */
7997 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7998 kvm_x86_ops->sync_pir_to_irr(vcpu);
7999
8000 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
8001 || need_resched() || signal_pending(current)) {
8002 vcpu->mode = OUTSIDE_GUEST_MODE;
8003 smp_wmb();
8004 local_irq_enable();
8005 preempt_enable();
8006 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8007 r = 1;
8008 goto cancel_injection;
8009 }
8010
8011 if (req_immediate_exit) {
8012 kvm_make_request(KVM_REQ_EVENT, vcpu);
8013 kvm_x86_ops->request_immediate_exit(vcpu);
8014 }
8015
8016 trace_kvm_entry(vcpu->vcpu_id);
8017 guest_enter_irqoff();
8018
8019 /* The preempt notifier should have taken care of the FPU already. */
8020 WARN_ON_ONCE(test_thread_flag(TIF_NEED_FPU_LOAD));
8021
8022 if (unlikely(vcpu->arch.switch_db_regs)) {
8023 set_debugreg(0, 7);
8024 set_debugreg(vcpu->arch.eff_db[0], 0);
8025 set_debugreg(vcpu->arch.eff_db[1], 1);
8026 set_debugreg(vcpu->arch.eff_db[2], 2);
8027 set_debugreg(vcpu->arch.eff_db[3], 3);
8028 set_debugreg(vcpu->arch.dr6, 6);
8029 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8030 }
8031
8032 kvm_x86_ops->run(vcpu);
8033
8034 /*
8035 * Do this here before restoring debug registers on the host. And
8036 * since we do this before handling the vmexit, a DR access vmexit
8037 * can (a) read the correct value of the debug registers, (b) set
8038 * KVM_DEBUGREG_WONT_EXIT again.
8039 */
8040 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8041 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8042 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
8043 kvm_update_dr0123(vcpu);
8044 kvm_update_dr6(vcpu);
8045 kvm_update_dr7(vcpu);
8046 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8047 }
8048
8049 /*
8050 * If the guest has used debug registers, at least dr7
8051 * will be disabled while returning to the host.
8052 * If we don't have active breakpoints in the host, we don't
8053 * care about the messed up debug address registers. But if
8054 * we have some of them active, restore the old state.
8055 */
8056 if (hw_breakpoint_active())
8057 hw_breakpoint_restore();
8058
8059 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8060
8061 vcpu->mode = OUTSIDE_GUEST_MODE;
8062 smp_wmb();
8063
8064 kvm_x86_ops->handle_exit_irqoff(vcpu);
8065
8066 /*
8067 * Consume any pending interrupts, including the possible source of
8068 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8069 * An instruction is required after local_irq_enable() to fully unblock
8070 * interrupts on processors that implement an interrupt shadow, the
8071 * stat.exits increment will do nicely.
8072 */
8073 kvm_before_interrupt(vcpu);
8074 local_irq_enable();
8075 ++vcpu->stat.exits;
8076 local_irq_disable();
8077 kvm_after_interrupt(vcpu);
8078
8079 guest_exit_irqoff();
8080 if (lapic_in_kernel(vcpu)) {
8081 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8082 if (delta != S64_MIN) {
8083 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8084 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8085 }
8086 }
8087
8088 local_irq_enable();
8089 preempt_enable();
8090
8091 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8092
8093 /*
8094 * Profile KVM exit RIPs:
8095 */
8096 if (unlikely(prof_on == KVM_PROFILING)) {
8097 unsigned long rip = kvm_rip_read(vcpu);
8098 profile_hit(KVM_PROFILING, (void *)rip);
8099 }
8100
8101 if (unlikely(vcpu->arch.tsc_always_catchup))
8102 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8103
8104 if (vcpu->arch.apic_attention)
8105 kvm_lapic_sync_from_vapic(vcpu);
8106
8107 vcpu->arch.gpa_available = false;
8108 r = kvm_x86_ops->handle_exit(vcpu);
8109 return r;
8110
8111cancel_injection:
8112 kvm_x86_ops->cancel_injection(vcpu);
8113 if (unlikely(vcpu->arch.apic_attention))
8114 kvm_lapic_sync_from_vapic(vcpu);
8115out:
8116 return r;
8117}
8118
8119static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8120{
8121 if (!kvm_arch_vcpu_runnable(vcpu) &&
8122 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
8123 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8124 kvm_vcpu_block(vcpu);
8125 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8126
8127 if (kvm_x86_ops->post_block)
8128 kvm_x86_ops->post_block(vcpu);
8129
8130 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8131 return 1;
8132 }
8133
8134 kvm_apic_accept_events(vcpu);
8135 switch(vcpu->arch.mp_state) {
8136 case KVM_MP_STATE_HALTED:
8137 vcpu->arch.pv.pv_unhalted = false;
8138 vcpu->arch.mp_state =
8139 KVM_MP_STATE_RUNNABLE;
8140 /* fall through */
8141 case KVM_MP_STATE_RUNNABLE:
8142 vcpu->arch.apf.halted = false;
8143 break;
8144 case KVM_MP_STATE_INIT_RECEIVED:
8145 break;
8146 default:
8147 return -EINTR;
8148 break;
8149 }
8150 return 1;
8151}
8152
8153static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8154{
8155 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8156 kvm_x86_ops->check_nested_events(vcpu, false);
8157
8158 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8159 !vcpu->arch.apf.halted);
8160}
8161
8162static int vcpu_run(struct kvm_vcpu *vcpu)
8163{
8164 int r;
8165 struct kvm *kvm = vcpu->kvm;
8166
8167 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8168 vcpu->arch.l1tf_flush_l1d = true;
8169
8170 for (;;) {
8171 if (kvm_vcpu_running(vcpu)) {
8172 r = vcpu_enter_guest(vcpu);
8173 } else {
8174 r = vcpu_block(kvm, vcpu);
8175 }
8176
8177 if (r <= 0)
8178 break;
8179
8180 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8181 if (kvm_cpu_has_pending_timer(vcpu))
8182 kvm_inject_pending_timer_irqs(vcpu);
8183
8184 if (dm_request_for_irq_injection(vcpu) &&
8185 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8186 r = 0;
8187 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8188 ++vcpu->stat.request_irq_exits;
8189 break;
8190 }
8191
8192 kvm_check_async_pf_completion(vcpu);
8193
8194 if (signal_pending(current)) {
8195 r = -EINTR;
8196 vcpu->run->exit_reason = KVM_EXIT_INTR;
8197 ++vcpu->stat.signal_exits;
8198 break;
8199 }
8200 if (need_resched()) {
8201 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8202 cond_resched();
8203 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8204 }
8205 }
8206
8207 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8208
8209 return r;
8210}
8211
8212static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8213{
8214 int r;
8215 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8216 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8217 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8218 if (r != EMULATE_DONE)
8219 return 0;
8220 return 1;
8221}
8222
8223static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8224{
8225 BUG_ON(!vcpu->arch.pio.count);
8226
8227 return complete_emulated_io(vcpu);
8228}
8229
8230/*
8231 * Implements the following, as a state machine:
8232 *
8233 * read:
8234 * for each fragment
8235 * for each mmio piece in the fragment
8236 * write gpa, len
8237 * exit
8238 * copy data
8239 * execute insn
8240 *
8241 * write:
8242 * for each fragment
8243 * for each mmio piece in the fragment
8244 * write gpa, len
8245 * copy data
8246 * exit
8247 */
8248static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8249{
8250 struct kvm_run *run = vcpu->run;
8251 struct kvm_mmio_fragment *frag;
8252 unsigned len;
8253
8254 BUG_ON(!vcpu->mmio_needed);
8255
8256 /* Complete previous fragment */
8257 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8258 len = min(8u, frag->len);
8259 if (!vcpu->mmio_is_write)
8260 memcpy(frag->data, run->mmio.data, len);
8261
8262 if (frag->len <= 8) {
8263 /* Switch to the next fragment. */
8264 frag++;
8265 vcpu->mmio_cur_fragment++;
8266 } else {
8267 /* Go forward to the next mmio piece. */
8268 frag->data += len;
8269 frag->gpa += len;
8270 frag->len -= len;
8271 }
8272
8273 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8274 vcpu->mmio_needed = 0;
8275
8276 /* FIXME: return into emulator if single-stepping. */
8277 if (vcpu->mmio_is_write)
8278 return 1;
8279 vcpu->mmio_read_completed = 1;
8280 return complete_emulated_io(vcpu);
8281 }
8282
8283 run->exit_reason = KVM_EXIT_MMIO;
8284 run->mmio.phys_addr = frag->gpa;
8285 if (vcpu->mmio_is_write)
8286 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8287 run->mmio.len = min(8u, frag->len);
8288 run->mmio.is_write = vcpu->mmio_is_write;
8289 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8290 return 0;
8291}
8292
8293/* Swap (qemu) user FPU context for the guest FPU context. */
8294static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8295{
8296 fpregs_lock();
8297
8298 copy_fpregs_to_fpstate(vcpu->arch.user_fpu);
8299 /* PKRU is separately restored in kvm_x86_ops->run. */
8300 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8301 ~XFEATURE_MASK_PKRU);
8302
8303 fpregs_mark_activate();
8304 fpregs_unlock();
8305
8306 trace_kvm_fpu(1);
8307}
8308
8309/* When vcpu_run ends, restore user space FPU context. */
8310static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8311{
8312 fpregs_lock();
8313
8314 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
8315 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
8316
8317 fpregs_mark_activate();
8318 fpregs_unlock();
8319
8320 ++vcpu->stat.fpu_reload;
8321 trace_kvm_fpu(0);
8322}
8323
8324int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8325{
8326 int r;
8327
8328 vcpu_load(vcpu);
8329 kvm_sigset_activate(vcpu);
8330 kvm_load_guest_fpu(vcpu);
8331
8332 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8333 if (kvm_run->immediate_exit) {
8334 r = -EINTR;
8335 goto out;
8336 }
8337 kvm_vcpu_block(vcpu);
8338 kvm_apic_accept_events(vcpu);
8339 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8340 r = -EAGAIN;
8341 if (signal_pending(current)) {
8342 r = -EINTR;
8343 vcpu->run->exit_reason = KVM_EXIT_INTR;
8344 ++vcpu->stat.signal_exits;
8345 }
8346 goto out;
8347 }
8348
8349 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8350 r = -EINVAL;
8351 goto out;
8352 }
8353
8354 if (vcpu->run->kvm_dirty_regs) {
8355 r = sync_regs(vcpu);
8356 if (r != 0)
8357 goto out;
8358 }
8359
8360 /* re-sync apic's tpr */
8361 if (!lapic_in_kernel(vcpu)) {
8362 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8363 r = -EINVAL;
8364 goto out;
8365 }
8366 }
8367
8368 if (unlikely(vcpu->arch.complete_userspace_io)) {
8369 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8370 vcpu->arch.complete_userspace_io = NULL;
8371 r = cui(vcpu);
8372 if (r <= 0)
8373 goto out;
8374 } else
8375 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8376
8377 if (kvm_run->immediate_exit)
8378 r = -EINTR;
8379 else
8380 r = vcpu_run(vcpu);
8381
8382out:
8383 kvm_put_guest_fpu(vcpu);
8384 if (vcpu->run->kvm_valid_regs)
8385 store_regs(vcpu);
8386 post_kvm_run_save(vcpu);
8387 kvm_sigset_deactivate(vcpu);
8388
8389 vcpu_put(vcpu);
8390 return r;
8391}
8392
8393static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8394{
8395 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8396 /*
8397 * We are here if userspace calls get_regs() in the middle of
8398 * instruction emulation. Registers state needs to be copied
8399 * back from emulation context to vcpu. Userspace shouldn't do
8400 * that usually, but some bad designed PV devices (vmware
8401 * backdoor interface) need this to work
8402 */
8403 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
8404 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8405 }
8406 regs->rax = kvm_rax_read(vcpu);
8407 regs->rbx = kvm_rbx_read(vcpu);
8408 regs->rcx = kvm_rcx_read(vcpu);
8409 regs->rdx = kvm_rdx_read(vcpu);
8410 regs->rsi = kvm_rsi_read(vcpu);
8411 regs->rdi = kvm_rdi_read(vcpu);
8412 regs->rsp = kvm_rsp_read(vcpu);
8413 regs->rbp = kvm_rbp_read(vcpu);
8414#ifdef CONFIG_X86_64
8415 regs->r8 = kvm_r8_read(vcpu);
8416 regs->r9 = kvm_r9_read(vcpu);
8417 regs->r10 = kvm_r10_read(vcpu);
8418 regs->r11 = kvm_r11_read(vcpu);
8419 regs->r12 = kvm_r12_read(vcpu);
8420 regs->r13 = kvm_r13_read(vcpu);
8421 regs->r14 = kvm_r14_read(vcpu);
8422 regs->r15 = kvm_r15_read(vcpu);
8423#endif
8424
8425 regs->rip = kvm_rip_read(vcpu);
8426 regs->rflags = kvm_get_rflags(vcpu);
8427}
8428
8429int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8430{
8431 vcpu_load(vcpu);
8432 __get_regs(vcpu, regs);
8433 vcpu_put(vcpu);
8434 return 0;
8435}
8436
8437static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8438{
8439 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8440 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8441
8442 kvm_rax_write(vcpu, regs->rax);
8443 kvm_rbx_write(vcpu, regs->rbx);
8444 kvm_rcx_write(vcpu, regs->rcx);
8445 kvm_rdx_write(vcpu, regs->rdx);
8446 kvm_rsi_write(vcpu, regs->rsi);
8447 kvm_rdi_write(vcpu, regs->rdi);
8448 kvm_rsp_write(vcpu, regs->rsp);
8449 kvm_rbp_write(vcpu, regs->rbp);
8450#ifdef CONFIG_X86_64
8451 kvm_r8_write(vcpu, regs->r8);
8452 kvm_r9_write(vcpu, regs->r9);
8453 kvm_r10_write(vcpu, regs->r10);
8454 kvm_r11_write(vcpu, regs->r11);
8455 kvm_r12_write(vcpu, regs->r12);
8456 kvm_r13_write(vcpu, regs->r13);
8457 kvm_r14_write(vcpu, regs->r14);
8458 kvm_r15_write(vcpu, regs->r15);
8459#endif
8460
8461 kvm_rip_write(vcpu, regs->rip);
8462 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
8463
8464 vcpu->arch.exception.pending = false;
8465
8466 kvm_make_request(KVM_REQ_EVENT, vcpu);
8467}
8468
8469int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8470{
8471 vcpu_load(vcpu);
8472 __set_regs(vcpu, regs);
8473 vcpu_put(vcpu);
8474 return 0;
8475}
8476
8477void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8478{
8479 struct kvm_segment cs;
8480
8481 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8482 *db = cs.db;
8483 *l = cs.l;
8484}
8485EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8486
8487static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8488{
8489 struct desc_ptr dt;
8490
8491 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8492 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8493 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8494 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8495 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8496 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8497
8498 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8499 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8500
8501 kvm_x86_ops->get_idt(vcpu, &dt);
8502 sregs->idt.limit = dt.size;
8503 sregs->idt.base = dt.address;
8504 kvm_x86_ops->get_gdt(vcpu, &dt);
8505 sregs->gdt.limit = dt.size;
8506 sregs->gdt.base = dt.address;
8507
8508 sregs->cr0 = kvm_read_cr0(vcpu);
8509 sregs->cr2 = vcpu->arch.cr2;
8510 sregs->cr3 = kvm_read_cr3(vcpu);
8511 sregs->cr4 = kvm_read_cr4(vcpu);
8512 sregs->cr8 = kvm_get_cr8(vcpu);
8513 sregs->efer = vcpu->arch.efer;
8514 sregs->apic_base = kvm_get_apic_base(vcpu);
8515
8516 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
8517
8518 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
8519 set_bit(vcpu->arch.interrupt.nr,
8520 (unsigned long *)sregs->interrupt_bitmap);
8521}
8522
8523int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8524 struct kvm_sregs *sregs)
8525{
8526 vcpu_load(vcpu);
8527 __get_sregs(vcpu, sregs);
8528 vcpu_put(vcpu);
8529 return 0;
8530}
8531
8532int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8533 struct kvm_mp_state *mp_state)
8534{
8535 vcpu_load(vcpu);
8536
8537 kvm_apic_accept_events(vcpu);
8538 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8539 vcpu->arch.pv.pv_unhalted)
8540 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8541 else
8542 mp_state->mp_state = vcpu->arch.mp_state;
8543
8544 vcpu_put(vcpu);
8545 return 0;
8546}
8547
8548int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8549 struct kvm_mp_state *mp_state)
8550{
8551 int ret = -EINVAL;
8552
8553 vcpu_load(vcpu);
8554
8555 if (!lapic_in_kernel(vcpu) &&
8556 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
8557 goto out;
8558
8559 /* INITs are latched while in SMM */
8560 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8561 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8562 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
8563 goto out;
8564
8565 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8566 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8567 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8568 } else
8569 vcpu->arch.mp_state = mp_state->mp_state;
8570 kvm_make_request(KVM_REQ_EVENT, vcpu);
8571
8572 ret = 0;
8573out:
8574 vcpu_put(vcpu);
8575 return ret;
8576}
8577
8578int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8579 int reason, bool has_error_code, u32 error_code)
8580{
8581 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8582 int ret;
8583
8584 init_emulate_ctxt(vcpu);
8585
8586 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
8587 has_error_code, error_code);
8588
8589 if (ret)
8590 return EMULATE_FAIL;
8591
8592 kvm_rip_write(vcpu, ctxt->eip);
8593 kvm_set_rflags(vcpu, ctxt->eflags);
8594 kvm_make_request(KVM_REQ_EVENT, vcpu);
8595 return EMULATE_DONE;
8596}
8597EXPORT_SYMBOL_GPL(kvm_task_switch);
8598
8599static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8600{
8601 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8602 (sregs->cr4 & X86_CR4_OSXSAVE))
8603 return -EINVAL;
8604
8605 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
8606 /*
8607 * When EFER.LME and CR0.PG are set, the processor is in
8608 * 64-bit mode (though maybe in a 32-bit code segment).
8609 * CR4.PAE and EFER.LMA must be set.
8610 */
8611 if (!(sregs->cr4 & X86_CR4_PAE)
8612 || !(sregs->efer & EFER_LMA))
8613 return -EINVAL;
8614 } else {
8615 /*
8616 * Not in 64-bit mode: EFER.LMA is clear and the code
8617 * segment cannot be 64-bit.
8618 */
8619 if (sregs->efer & EFER_LMA || sregs->cs.l)
8620 return -EINVAL;
8621 }
8622
8623 return 0;
8624}
8625
8626static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8627{
8628 struct msr_data apic_base_msr;
8629 int mmu_reset_needed = 0;
8630 int cpuid_update_needed = 0;
8631 int pending_vec, max_bits, idx;
8632 struct desc_ptr dt;
8633 int ret = -EINVAL;
8634
8635 if (kvm_valid_sregs(vcpu, sregs))
8636 goto out;
8637
8638 apic_base_msr.data = sregs->apic_base;
8639 apic_base_msr.host_initiated = true;
8640 if (kvm_set_apic_base(vcpu, &apic_base_msr))
8641 goto out;
8642
8643 dt.size = sregs->idt.limit;
8644 dt.address = sregs->idt.base;
8645 kvm_x86_ops->set_idt(vcpu, &dt);
8646 dt.size = sregs->gdt.limit;
8647 dt.address = sregs->gdt.base;
8648 kvm_x86_ops->set_gdt(vcpu, &dt);
8649
8650 vcpu->arch.cr2 = sregs->cr2;
8651 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
8652 vcpu->arch.cr3 = sregs->cr3;
8653 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
8654
8655 kvm_set_cr8(vcpu, sregs->cr8);
8656
8657 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
8658 kvm_x86_ops->set_efer(vcpu, sregs->efer);
8659
8660 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
8661 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
8662 vcpu->arch.cr0 = sregs->cr0;
8663
8664 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
8665 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8666 (X86_CR4_OSXSAVE | X86_CR4_PKE));
8667 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
8668 if (cpuid_update_needed)
8669 kvm_update_cpuid(vcpu);
8670
8671 idx = srcu_read_lock(&vcpu->kvm->srcu);
8672 if (is_pae_paging(vcpu)) {
8673 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
8674 mmu_reset_needed = 1;
8675 }
8676 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8677
8678 if (mmu_reset_needed)
8679 kvm_mmu_reset_context(vcpu);
8680
8681 max_bits = KVM_NR_INTERRUPTS;
8682 pending_vec = find_first_bit(
8683 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8684 if (pending_vec < max_bits) {
8685 kvm_queue_interrupt(vcpu, pending_vec, false);
8686 pr_debug("Set back pending irq %d\n", pending_vec);
8687 }
8688
8689 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8690 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8691 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8692 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8693 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8694 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8695
8696 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8697 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8698
8699 update_cr8_intercept(vcpu);
8700
8701 /* Older userspace won't unhalt the vcpu on reset. */
8702 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
8703 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
8704 !is_protmode(vcpu))
8705 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8706
8707 kvm_make_request(KVM_REQ_EVENT, vcpu);
8708
8709 ret = 0;
8710out:
8711 return ret;
8712}
8713
8714int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8715 struct kvm_sregs *sregs)
8716{
8717 int ret;
8718
8719 vcpu_load(vcpu);
8720 ret = __set_sregs(vcpu, sregs);
8721 vcpu_put(vcpu);
8722 return ret;
8723}
8724
8725int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8726 struct kvm_guest_debug *dbg)
8727{
8728 unsigned long rflags;
8729 int i, r;
8730
8731 vcpu_load(vcpu);
8732
8733 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8734 r = -EBUSY;
8735 if (vcpu->arch.exception.pending)
8736 goto out;
8737 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8738 kvm_queue_exception(vcpu, DB_VECTOR);
8739 else
8740 kvm_queue_exception(vcpu, BP_VECTOR);
8741 }
8742
8743 /*
8744 * Read rflags as long as potentially injected trace flags are still
8745 * filtered out.
8746 */
8747 rflags = kvm_get_rflags(vcpu);
8748
8749 vcpu->guest_debug = dbg->control;
8750 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8751 vcpu->guest_debug = 0;
8752
8753 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
8754 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8755 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
8756 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
8757 } else {
8758 for (i = 0; i < KVM_NR_DB_REGS; i++)
8759 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
8760 }
8761 kvm_update_dr7(vcpu);
8762
8763 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8764 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8765 get_segment_base(vcpu, VCPU_SREG_CS);
8766
8767 /*
8768 * Trigger an rflags update that will inject or remove the trace
8769 * flags.
8770 */
8771 kvm_set_rflags(vcpu, rflags);
8772
8773 kvm_x86_ops->update_bp_intercept(vcpu);
8774
8775 r = 0;
8776
8777out:
8778 vcpu_put(vcpu);
8779 return r;
8780}
8781
8782/*
8783 * Translate a guest virtual address to a guest physical address.
8784 */
8785int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8786 struct kvm_translation *tr)
8787{
8788 unsigned long vaddr = tr->linear_address;
8789 gpa_t gpa;
8790 int idx;
8791
8792 vcpu_load(vcpu);
8793
8794 idx = srcu_read_lock(&vcpu->kvm->srcu);
8795 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
8796 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8797 tr->physical_address = gpa;
8798 tr->valid = gpa != UNMAPPED_GVA;
8799 tr->writeable = 1;
8800 tr->usermode = 0;
8801
8802 vcpu_put(vcpu);
8803 return 0;
8804}
8805
8806int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8807{
8808 struct fxregs_state *fxsave;
8809
8810 vcpu_load(vcpu);
8811
8812 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8813 memcpy(fpu->fpr, fxsave->st_space, 128);
8814 fpu->fcw = fxsave->cwd;
8815 fpu->fsw = fxsave->swd;
8816 fpu->ftwx = fxsave->twd;
8817 fpu->last_opcode = fxsave->fop;
8818 fpu->last_ip = fxsave->rip;
8819 fpu->last_dp = fxsave->rdp;
8820 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
8821
8822 vcpu_put(vcpu);
8823 return 0;
8824}
8825
8826int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8827{
8828 struct fxregs_state *fxsave;
8829
8830 vcpu_load(vcpu);
8831
8832 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8833
8834 memcpy(fxsave->st_space, fpu->fpr, 128);
8835 fxsave->cwd = fpu->fcw;
8836 fxsave->swd = fpu->fsw;
8837 fxsave->twd = fpu->ftwx;
8838 fxsave->fop = fpu->last_opcode;
8839 fxsave->rip = fpu->last_ip;
8840 fxsave->rdp = fpu->last_dp;
8841 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
8842
8843 vcpu_put(vcpu);
8844 return 0;
8845}
8846
8847static void store_regs(struct kvm_vcpu *vcpu)
8848{
8849 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8850
8851 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8852 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8853
8854 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8855 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8856
8857 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8858 kvm_vcpu_ioctl_x86_get_vcpu_events(
8859 vcpu, &vcpu->run->s.regs.events);
8860}
8861
8862static int sync_regs(struct kvm_vcpu *vcpu)
8863{
8864 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8865 return -EINVAL;
8866
8867 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8868 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8869 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8870 }
8871 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8872 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8873 return -EINVAL;
8874 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8875 }
8876 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8877 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8878 vcpu, &vcpu->run->s.regs.events))
8879 return -EINVAL;
8880 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8881 }
8882
8883 return 0;
8884}
8885
8886static void fx_init(struct kvm_vcpu *vcpu)
8887{
8888 fpstate_init(&vcpu->arch.guest_fpu->state);
8889 if (boot_cpu_has(X86_FEATURE_XSAVES))
8890 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
8891 host_xcr0 | XSTATE_COMPACTION_ENABLED;
8892
8893 /*
8894 * Ensure guest xcr0 is valid for loading
8895 */
8896 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
8897
8898 vcpu->arch.cr0 |= X86_CR0_ET;
8899}
8900
8901void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8902{
8903 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8904
8905 kvmclock_reset(vcpu);
8906
8907 kvm_x86_ops->vcpu_free(vcpu);
8908 free_cpumask_var(wbinvd_dirty_mask);
8909}
8910
8911struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8912 unsigned int id)
8913{
8914 struct kvm_vcpu *vcpu;
8915
8916 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
8917 printk_once(KERN_WARNING
8918 "kvm: SMP vm created on host with unstable TSC; "
8919 "guest TSC will not be reliable\n");
8920
8921 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8922
8923 return vcpu;
8924}
8925
8926int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8927{
8928 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
8929 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8930 kvm_vcpu_mtrr_init(vcpu);
8931 vcpu_load(vcpu);
8932 kvm_vcpu_reset(vcpu, false);
8933 kvm_init_mmu(vcpu, false);
8934 vcpu_put(vcpu);
8935 return 0;
8936}
8937
8938void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
8939{
8940 struct msr_data msr;
8941 struct kvm *kvm = vcpu->kvm;
8942
8943 kvm_hv_vcpu_postcreate(vcpu);
8944
8945 if (mutex_lock_killable(&vcpu->mutex))
8946 return;
8947 vcpu_load(vcpu);
8948 msr.data = 0x0;
8949 msr.index = MSR_IA32_TSC;
8950 msr.host_initiated = true;
8951 kvm_write_tsc(vcpu, &msr);
8952 vcpu_put(vcpu);
8953
8954 /* poll control enabled by default */
8955 vcpu->arch.msr_kvm_poll_control = 1;
8956
8957 mutex_unlock(&vcpu->mutex);
8958
8959 if (!kvmclock_periodic_sync)
8960 return;
8961
8962 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8963 KVMCLOCK_SYNC_PERIOD);
8964}
8965
8966void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
8967{
8968 vcpu->arch.apf.msr_val = 0;
8969
8970 vcpu_load(vcpu);
8971 kvm_mmu_unload(vcpu);
8972 vcpu_put(vcpu);
8973
8974 kvm_x86_ops->vcpu_free(vcpu);
8975}
8976
8977void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
8978{
8979 kvm_lapic_reset(vcpu, init_event);
8980
8981 vcpu->arch.hflags = 0;
8982
8983 vcpu->arch.smi_pending = 0;
8984 vcpu->arch.smi_count = 0;
8985 atomic_set(&vcpu->arch.nmi_queued, 0);
8986 vcpu->arch.nmi_pending = 0;
8987 vcpu->arch.nmi_injected = false;
8988 kvm_clear_interrupt_queue(vcpu);
8989 kvm_clear_exception_queue(vcpu);
8990 vcpu->arch.exception.pending = false;
8991
8992 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
8993 kvm_update_dr0123(vcpu);
8994 vcpu->arch.dr6 = DR6_INIT;
8995 kvm_update_dr6(vcpu);
8996 vcpu->arch.dr7 = DR7_FIXED_1;
8997 kvm_update_dr7(vcpu);
8998
8999 vcpu->arch.cr2 = 0;
9000
9001 kvm_make_request(KVM_REQ_EVENT, vcpu);
9002 vcpu->arch.apf.msr_val = 0;
9003 vcpu->arch.st.msr_val = 0;
9004
9005 kvmclock_reset(vcpu);
9006
9007 kvm_clear_async_pf_completion_queue(vcpu);
9008 kvm_async_pf_hash_reset(vcpu);
9009 vcpu->arch.apf.halted = false;
9010
9011 if (kvm_mpx_supported()) {
9012 void *mpx_state_buffer;
9013
9014 /*
9015 * To avoid have the INIT path from kvm_apic_has_events() that be
9016 * called with loaded FPU and does not let userspace fix the state.
9017 */
9018 if (init_event)
9019 kvm_put_guest_fpu(vcpu);
9020 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9021 XFEATURE_BNDREGS);
9022 if (mpx_state_buffer)
9023 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
9024 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9025 XFEATURE_BNDCSR);
9026 if (mpx_state_buffer)
9027 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
9028 if (init_event)
9029 kvm_load_guest_fpu(vcpu);
9030 }
9031
9032 if (!init_event) {
9033 kvm_pmu_reset(vcpu);
9034 vcpu->arch.smbase = 0x30000;
9035
9036 vcpu->arch.msr_misc_features_enables = 0;
9037
9038 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9039 }
9040
9041 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9042 vcpu->arch.regs_avail = ~0;
9043 vcpu->arch.regs_dirty = ~0;
9044
9045 vcpu->arch.ia32_xss = 0;
9046
9047 kvm_x86_ops->vcpu_reset(vcpu, init_event);
9048}
9049
9050void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
9051{
9052 struct kvm_segment cs;
9053
9054 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9055 cs.selector = vector << 8;
9056 cs.base = vector << 12;
9057 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9058 kvm_rip_write(vcpu, 0);
9059}
9060
9061int kvm_arch_hardware_enable(void)
9062{
9063 struct kvm *kvm;
9064 struct kvm_vcpu *vcpu;
9065 int i;
9066 int ret;
9067 u64 local_tsc;
9068 u64 max_tsc = 0;
9069 bool stable, backwards_tsc = false;
9070
9071 kvm_shared_msr_cpu_online();
9072 ret = kvm_x86_ops->hardware_enable();
9073 if (ret != 0)
9074 return ret;
9075
9076 local_tsc = rdtsc();
9077 stable = !kvm_check_tsc_unstable();
9078 list_for_each_entry(kvm, &vm_list, vm_list) {
9079 kvm_for_each_vcpu(i, vcpu, kvm) {
9080 if (!stable && vcpu->cpu == smp_processor_id())
9081 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9082 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9083 backwards_tsc = true;
9084 if (vcpu->arch.last_host_tsc > max_tsc)
9085 max_tsc = vcpu->arch.last_host_tsc;
9086 }
9087 }
9088 }
9089
9090 /*
9091 * Sometimes, even reliable TSCs go backwards. This happens on
9092 * platforms that reset TSC during suspend or hibernate actions, but
9093 * maintain synchronization. We must compensate. Fortunately, we can
9094 * detect that condition here, which happens early in CPU bringup,
9095 * before any KVM threads can be running. Unfortunately, we can't
9096 * bring the TSCs fully up to date with real time, as we aren't yet far
9097 * enough into CPU bringup that we know how much real time has actually
9098 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
9099 * variables that haven't been updated yet.
9100 *
9101 * So we simply find the maximum observed TSC above, then record the
9102 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9103 * the adjustment will be applied. Note that we accumulate
9104 * adjustments, in case multiple suspend cycles happen before some VCPU
9105 * gets a chance to run again. In the event that no KVM threads get a
9106 * chance to run, we will miss the entire elapsed period, as we'll have
9107 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9108 * loose cycle time. This isn't too big a deal, since the loss will be
9109 * uniform across all VCPUs (not to mention the scenario is extremely
9110 * unlikely). It is possible that a second hibernate recovery happens
9111 * much faster than a first, causing the observed TSC here to be
9112 * smaller; this would require additional padding adjustment, which is
9113 * why we set last_host_tsc to the local tsc observed here.
9114 *
9115 * N.B. - this code below runs only on platforms with reliable TSC,
9116 * as that is the only way backwards_tsc is set above. Also note
9117 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9118 * have the same delta_cyc adjustment applied if backwards_tsc
9119 * is detected. Note further, this adjustment is only done once,
9120 * as we reset last_host_tsc on all VCPUs to stop this from being
9121 * called multiple times (one for each physical CPU bringup).
9122 *
9123 * Platforms with unreliable TSCs don't have to deal with this, they
9124 * will be compensated by the logic in vcpu_load, which sets the TSC to
9125 * catchup mode. This will catchup all VCPUs to real time, but cannot
9126 * guarantee that they stay in perfect synchronization.
9127 */
9128 if (backwards_tsc) {
9129 u64 delta_cyc = max_tsc - local_tsc;
9130 list_for_each_entry(kvm, &vm_list, vm_list) {
9131 kvm->arch.backwards_tsc_observed = true;
9132 kvm_for_each_vcpu(i, vcpu, kvm) {
9133 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9134 vcpu->arch.last_host_tsc = local_tsc;
9135 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9136 }
9137
9138 /*
9139 * We have to disable TSC offset matching.. if you were
9140 * booting a VM while issuing an S4 host suspend....
9141 * you may have some problem. Solving this issue is
9142 * left as an exercise to the reader.
9143 */
9144 kvm->arch.last_tsc_nsec = 0;
9145 kvm->arch.last_tsc_write = 0;
9146 }
9147
9148 }
9149 return 0;
9150}
9151
9152void kvm_arch_hardware_disable(void)
9153{
9154 kvm_x86_ops->hardware_disable();
9155 drop_user_return_notifiers();
9156}
9157
9158int kvm_arch_hardware_setup(void)
9159{
9160 int r;
9161
9162 r = kvm_x86_ops->hardware_setup();
9163 if (r != 0)
9164 return r;
9165
9166 if (kvm_has_tsc_control) {
9167 /*
9168 * Make sure the user can only configure tsc_khz values that
9169 * fit into a signed integer.
9170 * A min value is not calculated because it will always
9171 * be 1 on all machines.
9172 */
9173 u64 max = min(0x7fffffffULL,
9174 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9175 kvm_max_guest_tsc_khz = max;
9176
9177 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9178 }
9179
9180 kvm_init_msr_list();
9181 return 0;
9182}
9183
9184void kvm_arch_hardware_unsetup(void)
9185{
9186 kvm_x86_ops->hardware_unsetup();
9187}
9188
9189int kvm_arch_check_processor_compat(void)
9190{
9191 return kvm_x86_ops->check_processor_compatibility();
9192}
9193
9194bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9195{
9196 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9197}
9198EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9199
9200bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9201{
9202 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9203}
9204
9205struct static_key kvm_no_apic_vcpu __read_mostly;
9206EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9207
9208int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
9209{
9210 struct page *page;
9211 int r;
9212
9213 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
9214 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9215 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9216 else
9217 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9218
9219 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9220 if (!page) {
9221 r = -ENOMEM;
9222 goto fail;
9223 }
9224 vcpu->arch.pio_data = page_address(page);
9225
9226 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9227
9228 r = kvm_mmu_create(vcpu);
9229 if (r < 0)
9230 goto fail_free_pio_data;
9231
9232 if (irqchip_in_kernel(vcpu->kvm)) {
9233 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9234 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9235 if (r < 0)
9236 goto fail_mmu_destroy;
9237 } else
9238 static_key_slow_inc(&kvm_no_apic_vcpu);
9239
9240 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9241 GFP_KERNEL_ACCOUNT);
9242 if (!vcpu->arch.mce_banks) {
9243 r = -ENOMEM;
9244 goto fail_free_lapic;
9245 }
9246 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9247
9248 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9249 GFP_KERNEL_ACCOUNT)) {
9250 r = -ENOMEM;
9251 goto fail_free_mce_banks;
9252 }
9253
9254 fx_init(vcpu);
9255
9256 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
9257
9258 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9259
9260 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9261
9262 kvm_async_pf_hash_reset(vcpu);
9263 kvm_pmu_init(vcpu);
9264
9265 vcpu->arch.pending_external_vector = -1;
9266 vcpu->arch.preempted_in_kernel = false;
9267
9268 kvm_hv_vcpu_init(vcpu);
9269
9270 return 0;
9271
9272fail_free_mce_banks:
9273 kfree(vcpu->arch.mce_banks);
9274fail_free_lapic:
9275 kvm_free_lapic(vcpu);
9276fail_mmu_destroy:
9277 kvm_mmu_destroy(vcpu);
9278fail_free_pio_data:
9279 free_page((unsigned long)vcpu->arch.pio_data);
9280fail:
9281 return r;
9282}
9283
9284void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9285{
9286 int idx;
9287
9288 kvm_hv_vcpu_uninit(vcpu);
9289 kvm_pmu_destroy(vcpu);
9290 kfree(vcpu->arch.mce_banks);
9291 kvm_free_lapic(vcpu);
9292 idx = srcu_read_lock(&vcpu->kvm->srcu);
9293 kvm_mmu_destroy(vcpu);
9294 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9295 free_page((unsigned long)vcpu->arch.pio_data);
9296 if (!lapic_in_kernel(vcpu))
9297 static_key_slow_dec(&kvm_no_apic_vcpu);
9298}
9299
9300void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9301{
9302 vcpu->arch.l1tf_flush_l1d = true;
9303 kvm_x86_ops->sched_in(vcpu, cpu);
9304}
9305
9306int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9307{
9308 if (type)
9309 return -EINVAL;
9310
9311 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9312 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9313 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9314 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9315
9316 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9317 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9318 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9319 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9320 &kvm->arch.irq_sources_bitmap);
9321
9322 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9323 mutex_init(&kvm->arch.apic_map_lock);
9324 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9325
9326 kvm->arch.kvmclock_offset = -ktime_get_boottime_ns();
9327 pvclock_update_vm_gtod_copy(kvm);
9328
9329 kvm->arch.guest_can_read_msr_platform_info = true;
9330
9331 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9332 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9333
9334 kvm_hv_init_vm(kvm);
9335 kvm_page_track_init(kvm);
9336 kvm_mmu_init_vm(kvm);
9337
9338 return kvm_x86_ops->vm_init(kvm);
9339}
9340
9341static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9342{
9343 vcpu_load(vcpu);
9344 kvm_mmu_unload(vcpu);
9345 vcpu_put(vcpu);
9346}
9347
9348static void kvm_free_vcpus(struct kvm *kvm)
9349{
9350 unsigned int i;
9351 struct kvm_vcpu *vcpu;
9352
9353 /*
9354 * Unpin any mmu pages first.
9355 */
9356 kvm_for_each_vcpu(i, vcpu, kvm) {
9357 kvm_clear_async_pf_completion_queue(vcpu);
9358 kvm_unload_vcpu_mmu(vcpu);
9359 }
9360 kvm_for_each_vcpu(i, vcpu, kvm)
9361 kvm_arch_vcpu_free(vcpu);
9362
9363 mutex_lock(&kvm->lock);
9364 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9365 kvm->vcpus[i] = NULL;
9366
9367 atomic_set(&kvm->online_vcpus, 0);
9368 mutex_unlock(&kvm->lock);
9369}
9370
9371void kvm_arch_sync_events(struct kvm *kvm)
9372{
9373 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9374 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9375 kvm_free_pit(kvm);
9376}
9377
9378int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9379{
9380 int i, r;
9381 unsigned long hva;
9382 struct kvm_memslots *slots = kvm_memslots(kvm);
9383 struct kvm_memory_slot *slot, old;
9384
9385 /* Called with kvm->slots_lock held. */
9386 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9387 return -EINVAL;
9388
9389 slot = id_to_memslot(slots, id);
9390 if (size) {
9391 if (slot->npages)
9392 return -EEXIST;
9393
9394 /*
9395 * MAP_SHARED to prevent internal slot pages from being moved
9396 * by fork()/COW.
9397 */
9398 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9399 MAP_SHARED | MAP_ANONYMOUS, 0);
9400 if (IS_ERR((void *)hva))
9401 return PTR_ERR((void *)hva);
9402 } else {
9403 if (!slot->npages)
9404 return 0;
9405
9406 hva = 0;
9407 }
9408
9409 old = *slot;
9410 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9411 struct kvm_userspace_memory_region m;
9412
9413 m.slot = id | (i << 16);
9414 m.flags = 0;
9415 m.guest_phys_addr = gpa;
9416 m.userspace_addr = hva;
9417 m.memory_size = size;
9418 r = __kvm_set_memory_region(kvm, &m);
9419 if (r < 0)
9420 return r;
9421 }
9422
9423 if (!size)
9424 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
9425
9426 return 0;
9427}
9428EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9429
9430int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9431{
9432 int r;
9433
9434 mutex_lock(&kvm->slots_lock);
9435 r = __x86_set_memory_region(kvm, id, gpa, size);
9436 mutex_unlock(&kvm->slots_lock);
9437
9438 return r;
9439}
9440EXPORT_SYMBOL_GPL(x86_set_memory_region);
9441
9442void kvm_arch_destroy_vm(struct kvm *kvm)
9443{
9444 if (current->mm == kvm->mm) {
9445 /*
9446 * Free memory regions allocated on behalf of userspace,
9447 * unless the the memory map has changed due to process exit
9448 * or fd copying.
9449 */
9450 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9451 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9452 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
9453 }
9454 if (kvm_x86_ops->vm_destroy)
9455 kvm_x86_ops->vm_destroy(kvm);
9456 kvm_pic_destroy(kvm);
9457 kvm_ioapic_destroy(kvm);
9458 kvm_free_vcpus(kvm);
9459 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
9460 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
9461 kvm_mmu_uninit_vm(kvm);
9462 kvm_page_track_cleanup(kvm);
9463 kvm_hv_destroy_vm(kvm);
9464}
9465
9466void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
9467 struct kvm_memory_slot *dont)
9468{
9469 int i;
9470
9471 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9472 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
9473 kvfree(free->arch.rmap[i]);
9474 free->arch.rmap[i] = NULL;
9475 }
9476 if (i == 0)
9477 continue;
9478
9479 if (!dont || free->arch.lpage_info[i - 1] !=
9480 dont->arch.lpage_info[i - 1]) {
9481 kvfree(free->arch.lpage_info[i - 1]);
9482 free->arch.lpage_info[i - 1] = NULL;
9483 }
9484 }
9485
9486 kvm_page_track_free_memslot(free, dont);
9487}
9488
9489int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9490 unsigned long npages)
9491{
9492 int i;
9493
9494 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9495 struct kvm_lpage_info *linfo;
9496 unsigned long ugfn;
9497 int lpages;
9498 int level = i + 1;
9499
9500 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9501 slot->base_gfn, level) + 1;
9502
9503 slot->arch.rmap[i] =
9504 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9505 GFP_KERNEL_ACCOUNT);
9506 if (!slot->arch.rmap[i])
9507 goto out_free;
9508 if (i == 0)
9509 continue;
9510
9511 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
9512 if (!linfo)
9513 goto out_free;
9514
9515 slot->arch.lpage_info[i - 1] = linfo;
9516
9517 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
9518 linfo[0].disallow_lpage = 1;
9519 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
9520 linfo[lpages - 1].disallow_lpage = 1;
9521 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9522 /*
9523 * If the gfn and userspace address are not aligned wrt each
9524 * other, or if explicitly asked to, disable large page
9525 * support for this slot
9526 */
9527 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9528 !kvm_largepages_enabled()) {
9529 unsigned long j;
9530
9531 for (j = 0; j < lpages; ++j)
9532 linfo[j].disallow_lpage = 1;
9533 }
9534 }
9535
9536 if (kvm_page_track_create_memslot(slot, npages))
9537 goto out_free;
9538
9539 return 0;
9540
9541out_free:
9542 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9543 kvfree(slot->arch.rmap[i]);
9544 slot->arch.rmap[i] = NULL;
9545 if (i == 0)
9546 continue;
9547
9548 kvfree(slot->arch.lpage_info[i - 1]);
9549 slot->arch.lpage_info[i - 1] = NULL;
9550 }
9551 return -ENOMEM;
9552}
9553
9554void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
9555{
9556 /*
9557 * memslots->generation has been incremented.
9558 * mmio generation may have reached its maximum value.
9559 */
9560 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
9561}
9562
9563int kvm_arch_prepare_memory_region(struct kvm *kvm,
9564 struct kvm_memory_slot *memslot,
9565 const struct kvm_userspace_memory_region *mem,
9566 enum kvm_mr_change change)
9567{
9568 return 0;
9569}
9570
9571static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9572 struct kvm_memory_slot *new)
9573{
9574 /* Still write protect RO slot */
9575 if (new->flags & KVM_MEM_READONLY) {
9576 kvm_mmu_slot_remove_write_access(kvm, new);
9577 return;
9578 }
9579
9580 /*
9581 * Call kvm_x86_ops dirty logging hooks when they are valid.
9582 *
9583 * kvm_x86_ops->slot_disable_log_dirty is called when:
9584 *
9585 * - KVM_MR_CREATE with dirty logging is disabled
9586 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9587 *
9588 * The reason is, in case of PML, we need to set D-bit for any slots
9589 * with dirty logging disabled in order to eliminate unnecessary GPA
9590 * logging in PML buffer (and potential PML buffer full VMEXT). This
9591 * guarantees leaving PML enabled during guest's lifetime won't have
9592 * any additional overhead from PML when guest is running with dirty
9593 * logging disabled for memory slots.
9594 *
9595 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9596 * to dirty logging mode.
9597 *
9598 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9599 *
9600 * In case of write protect:
9601 *
9602 * Write protect all pages for dirty logging.
9603 *
9604 * All the sptes including the large sptes which point to this
9605 * slot are set to readonly. We can not create any new large
9606 * spte on this slot until the end of the logging.
9607 *
9608 * See the comments in fast_page_fault().
9609 */
9610 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9611 if (kvm_x86_ops->slot_enable_log_dirty)
9612 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9613 else
9614 kvm_mmu_slot_remove_write_access(kvm, new);
9615 } else {
9616 if (kvm_x86_ops->slot_disable_log_dirty)
9617 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9618 }
9619}
9620
9621void kvm_arch_commit_memory_region(struct kvm *kvm,
9622 const struct kvm_userspace_memory_region *mem,
9623 const struct kvm_memory_slot *old,
9624 const struct kvm_memory_slot *new,
9625 enum kvm_mr_change change)
9626{
9627 if (!kvm->arch.n_requested_mmu_pages)
9628 kvm_mmu_change_mmu_pages(kvm,
9629 kvm_mmu_calculate_default_mmu_pages(kvm));
9630
9631 /*
9632 * Dirty logging tracks sptes in 4k granularity, meaning that large
9633 * sptes have to be split. If live migration is successful, the guest
9634 * in the source machine will be destroyed and large sptes will be
9635 * created in the destination. However, if the guest continues to run
9636 * in the source machine (for example if live migration fails), small
9637 * sptes will remain around and cause bad performance.
9638 *
9639 * Scan sptes if dirty logging has been stopped, dropping those
9640 * which can be collapsed into a single large-page spte. Later
9641 * page faults will create the large-page sptes.
9642 */
9643 if ((change != KVM_MR_DELETE) &&
9644 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9645 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9646 kvm_mmu_zap_collapsible_sptes(kvm, new);
9647
9648 /*
9649 * Set up write protection and/or dirty logging for the new slot.
9650 *
9651 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9652 * been zapped so no dirty logging staff is needed for old slot. For
9653 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9654 * new and it's also covered when dealing with the new slot.
9655 *
9656 * FIXME: const-ify all uses of struct kvm_memory_slot.
9657 */
9658 if (change != KVM_MR_DELETE)
9659 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
9660}
9661
9662void kvm_arch_flush_shadow_all(struct kvm *kvm)
9663{
9664 kvm_mmu_zap_all(kvm);
9665}
9666
9667void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9668 struct kvm_memory_slot *slot)
9669{
9670 kvm_page_track_flush_slot(kvm, slot);
9671}
9672
9673static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9674{
9675 return (is_guest_mode(vcpu) &&
9676 kvm_x86_ops->guest_apic_has_interrupt &&
9677 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9678}
9679
9680static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9681{
9682 if (!list_empty_careful(&vcpu->async_pf.done))
9683 return true;
9684
9685 if (kvm_apic_has_events(vcpu))
9686 return true;
9687
9688 if (vcpu->arch.pv.pv_unhalted)
9689 return true;
9690
9691 if (vcpu->arch.exception.pending)
9692 return true;
9693
9694 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9695 (vcpu->arch.nmi_pending &&
9696 kvm_x86_ops->nmi_allowed(vcpu)))
9697 return true;
9698
9699 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9700 (vcpu->arch.smi_pending && !is_smm(vcpu)))
9701 return true;
9702
9703 if (kvm_arch_interrupt_allowed(vcpu) &&
9704 (kvm_cpu_has_interrupt(vcpu) ||
9705 kvm_guest_apic_has_interrupt(vcpu)))
9706 return true;
9707
9708 if (kvm_hv_has_stimer_pending(vcpu))
9709 return true;
9710
9711 return false;
9712}
9713
9714int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9715{
9716 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
9717}
9718
9719bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
9720{
9721 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
9722 return true;
9723
9724 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9725 kvm_test_request(KVM_REQ_SMI, vcpu) ||
9726 kvm_test_request(KVM_REQ_EVENT, vcpu))
9727 return true;
9728
9729 if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu))
9730 return true;
9731
9732 return false;
9733}
9734
9735bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9736{
9737 return vcpu->arch.preempted_in_kernel;
9738}
9739
9740int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
9741{
9742 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
9743}
9744
9745int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9746{
9747 return kvm_x86_ops->interrupt_allowed(vcpu);
9748}
9749
9750unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
9751{
9752 if (is_64_bit_mode(vcpu))
9753 return kvm_rip_read(vcpu);
9754 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9755 kvm_rip_read(vcpu));
9756}
9757EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
9758
9759bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9760{
9761 return kvm_get_linear_rip(vcpu) == linear_rip;
9762}
9763EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9764
9765unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9766{
9767 unsigned long rflags;
9768
9769 rflags = kvm_x86_ops->get_rflags(vcpu);
9770 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9771 rflags &= ~X86_EFLAGS_TF;
9772 return rflags;
9773}
9774EXPORT_SYMBOL_GPL(kvm_get_rflags);
9775
9776static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9777{
9778 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
9779 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
9780 rflags |= X86_EFLAGS_TF;
9781 kvm_x86_ops->set_rflags(vcpu, rflags);
9782}
9783
9784void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9785{
9786 __kvm_set_rflags(vcpu, rflags);
9787 kvm_make_request(KVM_REQ_EVENT, vcpu);
9788}
9789EXPORT_SYMBOL_GPL(kvm_set_rflags);
9790
9791void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9792{
9793 int r;
9794
9795 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
9796 work->wakeup_all)
9797 return;
9798
9799 r = kvm_mmu_reload(vcpu);
9800 if (unlikely(r))
9801 return;
9802
9803 if (!vcpu->arch.mmu->direct_map &&
9804 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
9805 return;
9806
9807 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
9808}
9809
9810static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9811{
9812 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9813}
9814
9815static inline u32 kvm_async_pf_next_probe(u32 key)
9816{
9817 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9818}
9819
9820static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9821{
9822 u32 key = kvm_async_pf_hash_fn(gfn);
9823
9824 while (vcpu->arch.apf.gfns[key] != ~0)
9825 key = kvm_async_pf_next_probe(key);
9826
9827 vcpu->arch.apf.gfns[key] = gfn;
9828}
9829
9830static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9831{
9832 int i;
9833 u32 key = kvm_async_pf_hash_fn(gfn);
9834
9835 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
9836 (vcpu->arch.apf.gfns[key] != gfn &&
9837 vcpu->arch.apf.gfns[key] != ~0); i++)
9838 key = kvm_async_pf_next_probe(key);
9839
9840 return key;
9841}
9842
9843bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9844{
9845 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9846}
9847
9848static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9849{
9850 u32 i, j, k;
9851
9852 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9853 while (true) {
9854 vcpu->arch.apf.gfns[i] = ~0;
9855 do {
9856 j = kvm_async_pf_next_probe(j);
9857 if (vcpu->arch.apf.gfns[j] == ~0)
9858 return;
9859 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9860 /*
9861 * k lies cyclically in ]i,j]
9862 * | i.k.j |
9863 * |....j i.k.| or |.k..j i...|
9864 */
9865 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9866 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9867 i = j;
9868 }
9869}
9870
9871static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9872{
9873
9874 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9875 sizeof(val));
9876}
9877
9878static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9879{
9880
9881 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9882 sizeof(u32));
9883}
9884
9885static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
9886{
9887 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
9888 return false;
9889
9890 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
9891 (vcpu->arch.apf.send_user_only &&
9892 kvm_x86_ops->get_cpl(vcpu) == 0))
9893 return false;
9894
9895 return true;
9896}
9897
9898bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
9899{
9900 if (unlikely(!lapic_in_kernel(vcpu) ||
9901 kvm_event_needs_reinjection(vcpu) ||
9902 vcpu->arch.exception.pending))
9903 return false;
9904
9905 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
9906 return false;
9907
9908 /*
9909 * If interrupts are off we cannot even use an artificial
9910 * halt state.
9911 */
9912 return kvm_x86_ops->interrupt_allowed(vcpu);
9913}
9914
9915void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9916 struct kvm_async_pf *work)
9917{
9918 struct x86_exception fault;
9919
9920 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
9921 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
9922
9923 if (kvm_can_deliver_async_pf(vcpu) &&
9924 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
9925 fault.vector = PF_VECTOR;
9926 fault.error_code_valid = true;
9927 fault.error_code = 0;
9928 fault.nested_page_fault = false;
9929 fault.address = work->arch.token;
9930 fault.async_page_fault = true;
9931 kvm_inject_page_fault(vcpu, &fault);
9932 } else {
9933 /*
9934 * It is not possible to deliver a paravirtualized asynchronous
9935 * page fault, but putting the guest in an artificial halt state
9936 * can be beneficial nevertheless: if an interrupt arrives, we
9937 * can deliver it timely and perhaps the guest will schedule
9938 * another process. When the instruction that triggered a page
9939 * fault is retried, hopefully the page will be ready in the host.
9940 */
9941 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9942 }
9943}
9944
9945void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9946 struct kvm_async_pf *work)
9947{
9948 struct x86_exception fault;
9949 u32 val;
9950
9951 if (work->wakeup_all)
9952 work->arch.token = ~0; /* broadcast wakeup */
9953 else
9954 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
9955 trace_kvm_async_pf_ready(work->arch.token, work->gva);
9956
9957 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9958 !apf_get_user(vcpu, &val)) {
9959 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9960 vcpu->arch.exception.pending &&
9961 vcpu->arch.exception.nr == PF_VECTOR &&
9962 !apf_put_user(vcpu, 0)) {
9963 vcpu->arch.exception.injected = false;
9964 vcpu->arch.exception.pending = false;
9965 vcpu->arch.exception.nr = 0;
9966 vcpu->arch.exception.has_error_code = false;
9967 vcpu->arch.exception.error_code = 0;
9968 vcpu->arch.exception.has_payload = false;
9969 vcpu->arch.exception.payload = 0;
9970 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9971 fault.vector = PF_VECTOR;
9972 fault.error_code_valid = true;
9973 fault.error_code = 0;
9974 fault.nested_page_fault = false;
9975 fault.address = work->arch.token;
9976 fault.async_page_fault = true;
9977 kvm_inject_page_fault(vcpu, &fault);
9978 }
9979 }
9980 vcpu->arch.apf.halted = false;
9981 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9982}
9983
9984bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9985{
9986 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9987 return true;
9988 else
9989 return kvm_can_do_async_pf(vcpu);
9990}
9991
9992void kvm_arch_start_assignment(struct kvm *kvm)
9993{
9994 atomic_inc(&kvm->arch.assigned_device_count);
9995}
9996EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9997
9998void kvm_arch_end_assignment(struct kvm *kvm)
9999{
10000 atomic_dec(&kvm->arch.assigned_device_count);
10001}
10002EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10003
10004bool kvm_arch_has_assigned_device(struct kvm *kvm)
10005{
10006 return atomic_read(&kvm->arch.assigned_device_count);
10007}
10008EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10009
10010void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10011{
10012 atomic_inc(&kvm->arch.noncoherent_dma_count);
10013}
10014EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10015
10016void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10017{
10018 atomic_dec(&kvm->arch.noncoherent_dma_count);
10019}
10020EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10021
10022bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10023{
10024 return atomic_read(&kvm->arch.noncoherent_dma_count);
10025}
10026EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10027
10028bool kvm_arch_has_irq_bypass(void)
10029{
10030 return true;
10031}
10032
10033int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10034 struct irq_bypass_producer *prod)
10035{
10036 struct kvm_kernel_irqfd *irqfd =
10037 container_of(cons, struct kvm_kernel_irqfd, consumer);
10038
10039 irqfd->producer = prod;
10040
10041 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
10042 prod->irq, irqfd->gsi, 1);
10043}
10044
10045void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10046 struct irq_bypass_producer *prod)
10047{
10048 int ret;
10049 struct kvm_kernel_irqfd *irqfd =
10050 container_of(cons, struct kvm_kernel_irqfd, consumer);
10051
10052 WARN_ON(irqfd->producer != prod);
10053 irqfd->producer = NULL;
10054
10055 /*
10056 * When producer of consumer is unregistered, we change back to
10057 * remapped mode, so we can re-use the current implementation
10058 * when the irq is masked/disabled or the consumer side (KVM
10059 * int this case doesn't want to receive the interrupts.
10060 */
10061 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10062 if (ret)
10063 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10064 " fails: %d\n", irqfd->consumer.token, ret);
10065}
10066
10067int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10068 uint32_t guest_irq, bool set)
10069{
10070 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
10071}
10072
10073bool kvm_vector_hashing_enabled(void)
10074{
10075 return vector_hashing;
10076}
10077EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
10078
10079bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10080{
10081 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10082}
10083EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10084
10085
10086EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
10087EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
10088EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10089EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10090EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10091EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
10092EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
10093EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
10094EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
10095EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
10096EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
10097EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
10098EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
10099EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
10100EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
10101EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
10102EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
10103EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10104EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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