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NVMe: fail pci initialization if the device doesn't have any BARs
[mirror_ubuntu-bionic-kernel.git] / drivers / block / nvme-core.c
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CommitLineData
1/*
2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/nvme.h>
16#include <linux/bitops.h>
17#include <linux/blkdev.h>
18#include <linux/blk-mq.h>
19#include <linux/cpu.h>
20#include <linux/delay.h>
21#include <linux/errno.h>
22#include <linux/fs.h>
23#include <linux/genhd.h>
24#include <linux/hdreg.h>
25#include <linux/idr.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kdev_t.h>
30#include <linux/kthread.h>
31#include <linux/kernel.h>
32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/pci.h>
36#include <linux/poison.h>
37#include <linux/ptrace.h>
38#include <linux/sched.h>
39#include <linux/slab.h>
40#include <linux/types.h>
41#include <scsi/sg.h>
42#include <asm-generic/io-64-nonatomic-lo-hi.h>
43
44#define NVME_Q_DEPTH 1024
45#define NVME_AQ_DEPTH 64
46#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
47#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
48#define ADMIN_TIMEOUT (admin_timeout * HZ)
49#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
50#define IOD_TIMEOUT (retry_time * HZ)
51
52static unsigned char admin_timeout = 60;
53module_param(admin_timeout, byte, 0644);
54MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
55
56unsigned char nvme_io_timeout = 30;
57module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
58MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
59
60static unsigned char retry_time = 30;
61module_param(retry_time, byte, 0644);
62MODULE_PARM_DESC(retry_time, "time in seconds to retry failed I/O");
63
64static unsigned char shutdown_timeout = 5;
65module_param(shutdown_timeout, byte, 0644);
66MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
67
68static int nvme_major;
69module_param(nvme_major, int, 0);
70
71static int use_threaded_interrupts;
72module_param(use_threaded_interrupts, int, 0);
73
74static DEFINE_SPINLOCK(dev_list_lock);
75static LIST_HEAD(dev_list);
76static struct task_struct *nvme_thread;
77static struct workqueue_struct *nvme_workq;
78static wait_queue_head_t nvme_kthread_wait;
79static struct notifier_block nvme_nb;
80
81static void nvme_reset_failed_dev(struct work_struct *ws);
82static int nvme_process_cq(struct nvme_queue *nvmeq);
83
84struct async_cmd_info {
85 struct kthread_work work;
86 struct kthread_worker *worker;
87 struct request *req;
88 u32 result;
89 int status;
90 void *ctx;
91};
92
93/*
94 * An NVM Express queue. Each device has at least two (one for admin
95 * commands and one for I/O commands).
96 */
97struct nvme_queue {
98 struct llist_node node;
99 struct device *q_dmadev;
100 struct nvme_dev *dev;
101 char irqname[24]; /* nvme4294967295-65535\0 */
102 spinlock_t q_lock;
103 struct nvme_command *sq_cmds;
104 volatile struct nvme_completion *cqes;
105 dma_addr_t sq_dma_addr;
106 dma_addr_t cq_dma_addr;
107 u32 __iomem *q_db;
108 u16 q_depth;
109 u16 cq_vector;
110 u16 sq_head;
111 u16 sq_tail;
112 u16 cq_head;
113 u16 qid;
114 u8 cq_phase;
115 u8 cqe_seen;
116 struct async_cmd_info cmdinfo;
117 struct blk_mq_hw_ctx *hctx;
118};
119
120/*
121 * Check we didin't inadvertently grow the command struct
122 */
123static inline void _nvme_check_size(void)
124{
125 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
126 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
127 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
130 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
131 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
132 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
133 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
134 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
135 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
136 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
137}
138
139typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
140 struct nvme_completion *);
141
142struct nvme_cmd_info {
143 nvme_completion_fn fn;
144 void *ctx;
145 int aborted;
146 struct nvme_queue *nvmeq;
147};
148
149static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
150 unsigned int hctx_idx)
151{
152 struct nvme_dev *dev = data;
153 struct nvme_queue *nvmeq = dev->queues[0];
154
155 WARN_ON(nvmeq->hctx);
156 nvmeq->hctx = hctx;
157 hctx->driver_data = nvmeq;
158 return 0;
159}
160
161static int nvme_admin_init_request(void *data, struct request *req,
162 unsigned int hctx_idx, unsigned int rq_idx,
163 unsigned int numa_node)
164{
165 struct nvme_dev *dev = data;
166 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
167 struct nvme_queue *nvmeq = dev->queues[0];
168
169 BUG_ON(!nvmeq);
170 cmd->nvmeq = nvmeq;
171 return 0;
172}
173
174static void nvme_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
175{
176 struct nvme_queue *nvmeq = hctx->driver_data;
177
178 nvmeq->hctx = NULL;
179}
180
181static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
182 unsigned int hctx_idx)
183{
184 struct nvme_dev *dev = data;
185 struct nvme_queue *nvmeq = dev->queues[
186 (hctx_idx % dev->queue_count) + 1];
187
188 if (!nvmeq->hctx)
189 nvmeq->hctx = hctx;
190
191 /* nvmeq queues are shared between namespaces. We assume here that
192 * blk-mq map the tags so they match up with the nvme queue tags. */
193 WARN_ON(nvmeq->hctx->tags != hctx->tags);
194
195 hctx->driver_data = nvmeq;
196 return 0;
197}
198
199static int nvme_init_request(void *data, struct request *req,
200 unsigned int hctx_idx, unsigned int rq_idx,
201 unsigned int numa_node)
202{
203 struct nvme_dev *dev = data;
204 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
205 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
206
207 BUG_ON(!nvmeq);
208 cmd->nvmeq = nvmeq;
209 return 0;
210}
211
212static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
213 nvme_completion_fn handler)
214{
215 cmd->fn = handler;
216 cmd->ctx = ctx;
217 cmd->aborted = 0;
218}
219
220/* Special values must be less than 0x1000 */
221#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
222#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
223#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
224#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
225
226static void special_completion(struct nvme_queue *nvmeq, void *ctx,
227 struct nvme_completion *cqe)
228{
229 if (ctx == CMD_CTX_CANCELLED)
230 return;
231 if (ctx == CMD_CTX_COMPLETED) {
232 dev_warn(nvmeq->q_dmadev,
233 "completed id %d twice on queue %d\n",
234 cqe->command_id, le16_to_cpup(&cqe->sq_id));
235 return;
236 }
237 if (ctx == CMD_CTX_INVALID) {
238 dev_warn(nvmeq->q_dmadev,
239 "invalid id %d completed on queue %d\n",
240 cqe->command_id, le16_to_cpup(&cqe->sq_id));
241 return;
242 }
243 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
244}
245
246static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
247{
248 void *ctx;
249
250 if (fn)
251 *fn = cmd->fn;
252 ctx = cmd->ctx;
253 cmd->fn = special_completion;
254 cmd->ctx = CMD_CTX_CANCELLED;
255 return ctx;
256}
257
258static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
259 struct nvme_completion *cqe)
260{
261 struct request *req = ctx;
262
263 u32 result = le32_to_cpup(&cqe->result);
264 u16 status = le16_to_cpup(&cqe->status) >> 1;
265
266 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
267 ++nvmeq->dev->event_limit;
268 if (status == NVME_SC_SUCCESS)
269 dev_warn(nvmeq->q_dmadev,
270 "async event result %08x\n", result);
271
272 blk_mq_free_hctx_request(nvmeq->hctx, req);
273}
274
275static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
276 struct nvme_completion *cqe)
277{
278 struct request *req = ctx;
279
280 u16 status = le16_to_cpup(&cqe->status) >> 1;
281 u32 result = le32_to_cpup(&cqe->result);
282
283 blk_mq_free_hctx_request(nvmeq->hctx, req);
284
285 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
286 ++nvmeq->dev->abort_limit;
287}
288
289static void async_completion(struct nvme_queue *nvmeq, void *ctx,
290 struct nvme_completion *cqe)
291{
292 struct async_cmd_info *cmdinfo = ctx;
293 cmdinfo->result = le32_to_cpup(&cqe->result);
294 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
295 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
296 blk_mq_free_hctx_request(nvmeq->hctx, cmdinfo->req);
297}
298
299static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
300 unsigned int tag)
301{
302 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
303 struct request *req = blk_mq_tag_to_rq(hctx->tags, tag);
304
305 return blk_mq_rq_to_pdu(req);
306}
307
308/*
309 * Called with local interrupts disabled and the q_lock held. May not sleep.
310 */
311static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
312 nvme_completion_fn *fn)
313{
314 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
315 void *ctx;
316 if (tag >= nvmeq->q_depth) {
317 *fn = special_completion;
318 return CMD_CTX_INVALID;
319 }
320 if (fn)
321 *fn = cmd->fn;
322 ctx = cmd->ctx;
323 cmd->fn = special_completion;
324 cmd->ctx = CMD_CTX_COMPLETED;
325 return ctx;
326}
327
328/**
329 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
330 * @nvmeq: The queue to use
331 * @cmd: The command to send
332 *
333 * Safe to use from interrupt context
334 */
335static int __nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
336{
337 u16 tail = nvmeq->sq_tail;
338
339 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
340 if (++tail == nvmeq->q_depth)
341 tail = 0;
342 writel(tail, nvmeq->q_db);
343 nvmeq->sq_tail = tail;
344
345 return 0;
346}
347
348static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
349{
350 unsigned long flags;
351 int ret;
352 spin_lock_irqsave(&nvmeq->q_lock, flags);
353 ret = __nvme_submit_cmd(nvmeq, cmd);
354 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
355 return ret;
356}
357
358static __le64 **iod_list(struct nvme_iod *iod)
359{
360 return ((void *)iod) + iod->offset;
361}
362
363/*
364 * Will slightly overestimate the number of pages needed. This is OK
365 * as it only leads to a small amount of wasted memory for the lifetime of
366 * the I/O.
367 */
368static int nvme_npages(unsigned size, struct nvme_dev *dev)
369{
370 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
371 return DIV_ROUND_UP(8 * nprps, dev->page_size - 8);
372}
373
374static struct nvme_iod *
375nvme_alloc_iod(unsigned nseg, unsigned nbytes, struct nvme_dev *dev, gfp_t gfp)
376{
377 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
378 sizeof(__le64 *) * nvme_npages(nbytes, dev) +
379 sizeof(struct scatterlist) * nseg, gfp);
380
381 if (iod) {
382 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
383 iod->npages = -1;
384 iod->length = nbytes;
385 iod->nents = 0;
386 iod->first_dma = 0ULL;
387 }
388
389 return iod;
390}
391
392void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
393{
394 const int last_prp = dev->page_size / 8 - 1;
395 int i;
396 __le64 **list = iod_list(iod);
397 dma_addr_t prp_dma = iod->first_dma;
398
399 if (iod->npages == 0)
400 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
401 for (i = 0; i < iod->npages; i++) {
402 __le64 *prp_list = list[i];
403 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
404 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
405 prp_dma = next_prp_dma;
406 }
407 kfree(iod);
408}
409
410static int nvme_error_status(u16 status)
411{
412 switch (status & 0x7ff) {
413 case NVME_SC_SUCCESS:
414 return 0;
415 case NVME_SC_CAP_EXCEEDED:
416 return -ENOSPC;
417 default:
418 return -EIO;
419 }
420}
421
422static void req_completion(struct nvme_queue *nvmeq, void *ctx,
423 struct nvme_completion *cqe)
424{
425 struct nvme_iod *iod = ctx;
426 struct request *req = iod->private;
427 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
428
429 u16 status = le16_to_cpup(&cqe->status) >> 1;
430
431 if (unlikely(status)) {
432 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
433 && (jiffies - req->start_time) < req->timeout) {
434 blk_mq_requeue_request(req);
435 blk_mq_kick_requeue_list(req->q);
436 return;
437 }
438 req->errors = nvme_error_status(status);
439 } else
440 req->errors = 0;
441
442 if (cmd_rq->aborted)
443 dev_warn(&nvmeq->dev->pci_dev->dev,
444 "completing aborted command with status:%04x\n",
445 status);
446
447 if (iod->nents)
448 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg, iod->nents,
449 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
450 nvme_free_iod(nvmeq->dev, iod);
451
452 blk_mq_complete_request(req);
453}
454
455/* length is in bytes. gfp flags indicates whether we may sleep. */
456int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len,
457 gfp_t gfp)
458{
459 struct dma_pool *pool;
460 int length = total_len;
461 struct scatterlist *sg = iod->sg;
462 int dma_len = sg_dma_len(sg);
463 u64 dma_addr = sg_dma_address(sg);
464 int offset = offset_in_page(dma_addr);
465 __le64 *prp_list;
466 __le64 **list = iod_list(iod);
467 dma_addr_t prp_dma;
468 int nprps, i;
469 u32 page_size = dev->page_size;
470
471 length -= (page_size - offset);
472 if (length <= 0)
473 return total_len;
474
475 dma_len -= (page_size - offset);
476 if (dma_len) {
477 dma_addr += (page_size - offset);
478 } else {
479 sg = sg_next(sg);
480 dma_addr = sg_dma_address(sg);
481 dma_len = sg_dma_len(sg);
482 }
483
484 if (length <= page_size) {
485 iod->first_dma = dma_addr;
486 return total_len;
487 }
488
489 nprps = DIV_ROUND_UP(length, page_size);
490 if (nprps <= (256 / 8)) {
491 pool = dev->prp_small_pool;
492 iod->npages = 0;
493 } else {
494 pool = dev->prp_page_pool;
495 iod->npages = 1;
496 }
497
498 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
499 if (!prp_list) {
500 iod->first_dma = dma_addr;
501 iod->npages = -1;
502 return (total_len - length) + page_size;
503 }
504 list[0] = prp_list;
505 iod->first_dma = prp_dma;
506 i = 0;
507 for (;;) {
508 if (i == page_size >> 3) {
509 __le64 *old_prp_list = prp_list;
510 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
511 if (!prp_list)
512 return total_len - length;
513 list[iod->npages++] = prp_list;
514 prp_list[0] = old_prp_list[i - 1];
515 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
516 i = 1;
517 }
518 prp_list[i++] = cpu_to_le64(dma_addr);
519 dma_len -= page_size;
520 dma_addr += page_size;
521 length -= page_size;
522 if (length <= 0)
523 break;
524 if (dma_len > 0)
525 continue;
526 BUG_ON(dma_len < 0);
527 sg = sg_next(sg);
528 dma_addr = sg_dma_address(sg);
529 dma_len = sg_dma_len(sg);
530 }
531
532 return total_len;
533}
534
535/*
536 * We reuse the small pool to allocate the 16-byte range here as it is not
537 * worth having a special pool for these or additional cases to handle freeing
538 * the iod.
539 */
540static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
541 struct request *req, struct nvme_iod *iod)
542{
543 struct nvme_dsm_range *range =
544 (struct nvme_dsm_range *)iod_list(iod)[0];
545 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
546
547 range->cattr = cpu_to_le32(0);
548 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
549 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
550
551 memset(cmnd, 0, sizeof(*cmnd));
552 cmnd->dsm.opcode = nvme_cmd_dsm;
553 cmnd->dsm.command_id = req->tag;
554 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
555 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
556 cmnd->dsm.nr = 0;
557 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
558
559 if (++nvmeq->sq_tail == nvmeq->q_depth)
560 nvmeq->sq_tail = 0;
561 writel(nvmeq->sq_tail, nvmeq->q_db);
562}
563
564static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
565 int cmdid)
566{
567 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
568
569 memset(cmnd, 0, sizeof(*cmnd));
570 cmnd->common.opcode = nvme_cmd_flush;
571 cmnd->common.command_id = cmdid;
572 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
573
574 if (++nvmeq->sq_tail == nvmeq->q_depth)
575 nvmeq->sq_tail = 0;
576 writel(nvmeq->sq_tail, nvmeq->q_db);
577}
578
579static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
580 struct nvme_ns *ns)
581{
582 struct request *req = iod->private;
583 struct nvme_command *cmnd;
584 u16 control = 0;
585 u32 dsmgmt = 0;
586
587 if (req->cmd_flags & REQ_FUA)
588 control |= NVME_RW_FUA;
589 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
590 control |= NVME_RW_LR;
591
592 if (req->cmd_flags & REQ_RAHEAD)
593 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
594
595 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
596 memset(cmnd, 0, sizeof(*cmnd));
597
598 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
599 cmnd->rw.command_id = req->tag;
600 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
601 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
602 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
603 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
604 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
605 cmnd->rw.control = cpu_to_le16(control);
606 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
607
608 if (++nvmeq->sq_tail == nvmeq->q_depth)
609 nvmeq->sq_tail = 0;
610 writel(nvmeq->sq_tail, nvmeq->q_db);
611
612 return 0;
613}
614
615static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
616 const struct blk_mq_queue_data *bd)
617{
618 struct nvme_ns *ns = hctx->queue->queuedata;
619 struct nvme_queue *nvmeq = hctx->driver_data;
620 struct request *req = bd->rq;
621 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
622 struct nvme_iod *iod;
623 int psegs = req->nr_phys_segments;
624 int result = BLK_MQ_RQ_QUEUE_BUSY;
625 enum dma_data_direction dma_dir;
626 unsigned size = !(req->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(req) :
627 sizeof(struct nvme_dsm_range);
628
629 /*
630 * Requeued IO has already been prepped
631 */
632 iod = req->special;
633 if (iod)
634 goto submit_iod;
635
636 iod = nvme_alloc_iod(psegs, size, ns->dev, GFP_ATOMIC);
637 if (!iod)
638 return result;
639
640 iod->private = req;
641 req->special = iod;
642
643 nvme_set_info(cmd, iod, req_completion);
644
645 if (req->cmd_flags & REQ_DISCARD) {
646 void *range;
647 /*
648 * We reuse the small pool to allocate the 16-byte range here
649 * as it is not worth having a special pool for these or
650 * additional cases to handle freeing the iod.
651 */
652 range = dma_pool_alloc(nvmeq->dev->prp_small_pool,
653 GFP_ATOMIC,
654 &iod->first_dma);
655 if (!range)
656 goto finish_cmd;
657 iod_list(iod)[0] = (__le64 *)range;
658 iod->npages = 0;
659 } else if (psegs) {
660 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
661
662 sg_init_table(iod->sg, psegs);
663 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
664 if (!iod->nents) {
665 result = BLK_MQ_RQ_QUEUE_ERROR;
666 goto finish_cmd;
667 }
668
669 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
670 goto finish_cmd;
671
672 if (blk_rq_bytes(req) != nvme_setup_prps(nvmeq->dev, iod,
673 blk_rq_bytes(req), GFP_ATOMIC))
674 goto finish_cmd;
675 }
676
677 blk_mq_start_request(req);
678
679 submit_iod:
680 spin_lock_irq(&nvmeq->q_lock);
681 if (req->cmd_flags & REQ_DISCARD)
682 nvme_submit_discard(nvmeq, ns, req, iod);
683 else if (req->cmd_flags & REQ_FLUSH)
684 nvme_submit_flush(nvmeq, ns, req->tag);
685 else
686 nvme_submit_iod(nvmeq, iod, ns);
687
688 nvme_process_cq(nvmeq);
689 spin_unlock_irq(&nvmeq->q_lock);
690 return BLK_MQ_RQ_QUEUE_OK;
691
692 finish_cmd:
693 nvme_finish_cmd(nvmeq, req->tag, NULL);
694 nvme_free_iod(nvmeq->dev, iod);
695 return result;
696}
697
698static int nvme_process_cq(struct nvme_queue *nvmeq)
699{
700 u16 head, phase;
701
702 head = nvmeq->cq_head;
703 phase = nvmeq->cq_phase;
704
705 for (;;) {
706 void *ctx;
707 nvme_completion_fn fn;
708 struct nvme_completion cqe = nvmeq->cqes[head];
709 if ((le16_to_cpu(cqe.status) & 1) != phase)
710 break;
711 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
712 if (++head == nvmeq->q_depth) {
713 head = 0;
714 phase = !phase;
715 }
716 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
717 fn(nvmeq, ctx, &cqe);
718 }
719
720 /* If the controller ignores the cq head doorbell and continuously
721 * writes to the queue, it is theoretically possible to wrap around
722 * the queue twice and mistakenly return IRQ_NONE. Linux only
723 * requires that 0.1% of your interrupts are handled, so this isn't
724 * a big problem.
725 */
726 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
727 return 0;
728
729 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
730 nvmeq->cq_head = head;
731 nvmeq->cq_phase = phase;
732
733 nvmeq->cqe_seen = 1;
734 return 1;
735}
736
737/* Admin queue isn't initialized as a request queue. If at some point this
738 * happens anyway, make sure to notify the user */
739static int nvme_admin_queue_rq(struct blk_mq_hw_ctx *hctx,
740 const struct blk_mq_queue_data *bd)
741{
742 WARN_ON_ONCE(1);
743 return BLK_MQ_RQ_QUEUE_ERROR;
744}
745
746static irqreturn_t nvme_irq(int irq, void *data)
747{
748 irqreturn_t result;
749 struct nvme_queue *nvmeq = data;
750 spin_lock(&nvmeq->q_lock);
751 nvme_process_cq(nvmeq);
752 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
753 nvmeq->cqe_seen = 0;
754 spin_unlock(&nvmeq->q_lock);
755 return result;
756}
757
758static irqreturn_t nvme_irq_check(int irq, void *data)
759{
760 struct nvme_queue *nvmeq = data;
761 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
762 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
763 return IRQ_NONE;
764 return IRQ_WAKE_THREAD;
765}
766
767static void nvme_abort_cmd_info(struct nvme_queue *nvmeq, struct nvme_cmd_info *
768 cmd_info)
769{
770 spin_lock_irq(&nvmeq->q_lock);
771 cancel_cmd_info(cmd_info, NULL);
772 spin_unlock_irq(&nvmeq->q_lock);
773}
774
775struct sync_cmd_info {
776 struct task_struct *task;
777 u32 result;
778 int status;
779};
780
781static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
782 struct nvme_completion *cqe)
783{
784 struct sync_cmd_info *cmdinfo = ctx;
785 cmdinfo->result = le32_to_cpup(&cqe->result);
786 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
787 wake_up_process(cmdinfo->task);
788}
789
790/*
791 * Returns 0 on success. If the result is negative, it's a Linux error code;
792 * if the result is positive, it's an NVM Express status code
793 */
794static int nvme_submit_sync_cmd(struct request *req, struct nvme_command *cmd,
795 u32 *result, unsigned timeout)
796{
797 int ret;
798 struct sync_cmd_info cmdinfo;
799 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
800 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
801
802 cmdinfo.task = current;
803 cmdinfo.status = -EINTR;
804
805 cmd->common.command_id = req->tag;
806
807 nvme_set_info(cmd_rq, &cmdinfo, sync_completion);
808
809 set_current_state(TASK_KILLABLE);
810 ret = nvme_submit_cmd(nvmeq, cmd);
811 if (ret) {
812 nvme_finish_cmd(nvmeq, req->tag, NULL);
813 set_current_state(TASK_RUNNING);
814 }
815 schedule_timeout(timeout);
816
817 if (cmdinfo.status == -EINTR) {
818 nvme_abort_cmd_info(nvmeq, blk_mq_rq_to_pdu(req));
819 return -EINTR;
820 }
821
822 if (result)
823 *result = cmdinfo.result;
824
825 return cmdinfo.status;
826}
827
828static int nvme_submit_async_admin_req(struct nvme_dev *dev)
829{
830 struct nvme_queue *nvmeq = dev->queues[0];
831 struct nvme_command c;
832 struct nvme_cmd_info *cmd_info;
833 struct request *req;
834
835 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, false);
836 if (IS_ERR(req))
837 return PTR_ERR(req);
838
839 cmd_info = blk_mq_rq_to_pdu(req);
840 nvme_set_info(cmd_info, req, async_req_completion);
841
842 memset(&c, 0, sizeof(c));
843 c.common.opcode = nvme_admin_async_event;
844 c.common.command_id = req->tag;
845
846 return __nvme_submit_cmd(nvmeq, &c);
847}
848
849static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
850 struct nvme_command *cmd,
851 struct async_cmd_info *cmdinfo, unsigned timeout)
852{
853 struct nvme_queue *nvmeq = dev->queues[0];
854 struct request *req;
855 struct nvme_cmd_info *cmd_rq;
856
857 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
858 if (IS_ERR(req))
859 return PTR_ERR(req);
860
861 req->timeout = timeout;
862 cmd_rq = blk_mq_rq_to_pdu(req);
863 cmdinfo->req = req;
864 nvme_set_info(cmd_rq, cmdinfo, async_completion);
865 cmdinfo->status = -EINTR;
866
867 cmd->common.command_id = req->tag;
868
869 return nvme_submit_cmd(nvmeq, cmd);
870}
871
872static int __nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
873 u32 *result, unsigned timeout)
874{
875 int res;
876 struct request *req;
877
878 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
879 if (!req)
880 return -ENOMEM;
881 res = nvme_submit_sync_cmd(req, cmd, result, timeout);
882 blk_mq_free_request(req);
883 return res;
884}
885
886int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
887 u32 *result)
888{
889 return __nvme_submit_admin_cmd(dev, cmd, result, ADMIN_TIMEOUT);
890}
891
892int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
893 struct nvme_command *cmd, u32 *result)
894{
895 int res;
896 struct request *req;
897
898 req = blk_mq_alloc_request(ns->queue, WRITE, (GFP_KERNEL|__GFP_WAIT),
899 false);
900 if (!req)
901 return -ENOMEM;
902 res = nvme_submit_sync_cmd(req, cmd, result, NVME_IO_TIMEOUT);
903 blk_mq_free_request(req);
904 return res;
905}
906
907static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
908{
909 struct nvme_command c;
910
911 memset(&c, 0, sizeof(c));
912 c.delete_queue.opcode = opcode;
913 c.delete_queue.qid = cpu_to_le16(id);
914
915 return nvme_submit_admin_cmd(dev, &c, NULL);
916}
917
918static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
919 struct nvme_queue *nvmeq)
920{
921 struct nvme_command c;
922 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
923
924 memset(&c, 0, sizeof(c));
925 c.create_cq.opcode = nvme_admin_create_cq;
926 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
927 c.create_cq.cqid = cpu_to_le16(qid);
928 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
929 c.create_cq.cq_flags = cpu_to_le16(flags);
930 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
931
932 return nvme_submit_admin_cmd(dev, &c, NULL);
933}
934
935static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
936 struct nvme_queue *nvmeq)
937{
938 struct nvme_command c;
939 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
940
941 memset(&c, 0, sizeof(c));
942 c.create_sq.opcode = nvme_admin_create_sq;
943 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
944 c.create_sq.sqid = cpu_to_le16(qid);
945 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
946 c.create_sq.sq_flags = cpu_to_le16(flags);
947 c.create_sq.cqid = cpu_to_le16(qid);
948
949 return nvme_submit_admin_cmd(dev, &c, NULL);
950}
951
952static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
953{
954 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
955}
956
957static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
958{
959 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
960}
961
962int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
963 dma_addr_t dma_addr)
964{
965 struct nvme_command c;
966
967 memset(&c, 0, sizeof(c));
968 c.identify.opcode = nvme_admin_identify;
969 c.identify.nsid = cpu_to_le32(nsid);
970 c.identify.prp1 = cpu_to_le64(dma_addr);
971 c.identify.cns = cpu_to_le32(cns);
972
973 return nvme_submit_admin_cmd(dev, &c, NULL);
974}
975
976int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
977 dma_addr_t dma_addr, u32 *result)
978{
979 struct nvme_command c;
980
981 memset(&c, 0, sizeof(c));
982 c.features.opcode = nvme_admin_get_features;
983 c.features.nsid = cpu_to_le32(nsid);
984 c.features.prp1 = cpu_to_le64(dma_addr);
985 c.features.fid = cpu_to_le32(fid);
986
987 return nvme_submit_admin_cmd(dev, &c, result);
988}
989
990int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
991 dma_addr_t dma_addr, u32 *result)
992{
993 struct nvme_command c;
994
995 memset(&c, 0, sizeof(c));
996 c.features.opcode = nvme_admin_set_features;
997 c.features.prp1 = cpu_to_le64(dma_addr);
998 c.features.fid = cpu_to_le32(fid);
999 c.features.dword11 = cpu_to_le32(dword11);
1000
1001 return nvme_submit_admin_cmd(dev, &c, result);
1002}
1003
1004/**
1005 * nvme_abort_req - Attempt aborting a request
1006 *
1007 * Schedule controller reset if the command was already aborted once before and
1008 * still hasn't been returned to the driver, or if this is the admin queue.
1009 */
1010static void nvme_abort_req(struct request *req)
1011{
1012 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1013 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
1014 struct nvme_dev *dev = nvmeq->dev;
1015 struct request *abort_req;
1016 struct nvme_cmd_info *abort_cmd;
1017 struct nvme_command cmd;
1018
1019 if (!nvmeq->qid || cmd_rq->aborted) {
1020 if (work_busy(&dev->reset_work))
1021 return;
1022 list_del_init(&dev->node);
1023 dev_warn(&dev->pci_dev->dev,
1024 "I/O %d QID %d timeout, reset controller\n",
1025 req->tag, nvmeq->qid);
1026 dev->reset_workfn = nvme_reset_failed_dev;
1027 queue_work(nvme_workq, &dev->reset_work);
1028 return;
1029 }
1030
1031 if (!dev->abort_limit)
1032 return;
1033
1034 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1035 false);
1036 if (IS_ERR(abort_req))
1037 return;
1038
1039 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1040 nvme_set_info(abort_cmd, abort_req, abort_completion);
1041
1042 memset(&cmd, 0, sizeof(cmd));
1043 cmd.abort.opcode = nvme_admin_abort_cmd;
1044 cmd.abort.cid = req->tag;
1045 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1046 cmd.abort.command_id = abort_req->tag;
1047
1048 --dev->abort_limit;
1049 cmd_rq->aborted = 1;
1050
1051 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
1052 nvmeq->qid);
1053 if (nvme_submit_cmd(dev->queues[0], &cmd) < 0) {
1054 dev_warn(nvmeq->q_dmadev,
1055 "Could not abort I/O %d QID %d",
1056 req->tag, nvmeq->qid);
1057 blk_mq_free_request(req);
1058 }
1059}
1060
1061static void nvme_cancel_queue_ios(struct blk_mq_hw_ctx *hctx,
1062 struct request *req, void *data, bool reserved)
1063{
1064 struct nvme_queue *nvmeq = data;
1065 void *ctx;
1066 nvme_completion_fn fn;
1067 struct nvme_cmd_info *cmd;
1068 static struct nvme_completion cqe = {
1069 .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1),
1070 };
1071
1072 cmd = blk_mq_rq_to_pdu(req);
1073
1074 if (cmd->ctx == CMD_CTX_CANCELLED)
1075 return;
1076
1077 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1078 req->tag, nvmeq->qid);
1079 ctx = cancel_cmd_info(cmd, &fn);
1080 fn(nvmeq, ctx, &cqe);
1081}
1082
1083static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1084{
1085 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1086 struct nvme_queue *nvmeq = cmd->nvmeq;
1087
1088 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1089 nvmeq->qid);
1090 if (nvmeq->dev->initialized)
1091 nvme_abort_req(req);
1092
1093 /*
1094 * The aborted req will be completed on receiving the abort req.
1095 * We enable the timer again. If hit twice, it'll cause a device reset,
1096 * as the device then is in a faulty state.
1097 */
1098 return BLK_EH_RESET_TIMER;
1099}
1100
1101static void nvme_free_queue(struct nvme_queue *nvmeq)
1102{
1103 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1104 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1105 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1106 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1107 kfree(nvmeq);
1108}
1109
1110static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1111{
1112 LLIST_HEAD(q_list);
1113 struct nvme_queue *nvmeq, *next;
1114 struct llist_node *entry;
1115 int i;
1116
1117 for (i = dev->queue_count - 1; i >= lowest; i--) {
1118 struct nvme_queue *nvmeq = dev->queues[i];
1119 llist_add(&nvmeq->node, &q_list);
1120 dev->queue_count--;
1121 dev->queues[i] = NULL;
1122 }
1123 synchronize_rcu();
1124 entry = llist_del_all(&q_list);
1125 llist_for_each_entry_safe(nvmeq, next, entry, node)
1126 nvme_free_queue(nvmeq);
1127}
1128
1129/**
1130 * nvme_suspend_queue - put queue into suspended state
1131 * @nvmeq - queue to suspend
1132 */
1133static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1134{
1135 int vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1136
1137 spin_lock_irq(&nvmeq->q_lock);
1138 nvmeq->dev->online_queues--;
1139 spin_unlock_irq(&nvmeq->q_lock);
1140
1141 irq_set_affinity_hint(vector, NULL);
1142 free_irq(vector, nvmeq);
1143
1144 return 0;
1145}
1146
1147static void nvme_clear_queue(struct nvme_queue *nvmeq)
1148{
1149 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
1150
1151 spin_lock_irq(&nvmeq->q_lock);
1152 nvme_process_cq(nvmeq);
1153 if (hctx && hctx->tags)
1154 blk_mq_tag_busy_iter(hctx, nvme_cancel_queue_ios, nvmeq);
1155 spin_unlock_irq(&nvmeq->q_lock);
1156}
1157
1158static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1159{
1160 struct nvme_queue *nvmeq = dev->queues[qid];
1161
1162 if (!nvmeq)
1163 return;
1164 if (nvme_suspend_queue(nvmeq))
1165 return;
1166
1167 /* Don't tell the adapter to delete the admin queue.
1168 * Don't tell a removed adapter to delete IO queues. */
1169 if (qid && readl(&dev->bar->csts) != -1) {
1170 adapter_delete_sq(dev, qid);
1171 adapter_delete_cq(dev, qid);
1172 }
1173 nvme_clear_queue(nvmeq);
1174}
1175
1176static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1177 int depth, int vector)
1178{
1179 struct device *dmadev = &dev->pci_dev->dev;
1180 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1181 if (!nvmeq)
1182 return NULL;
1183
1184 nvmeq->cqes = dma_zalloc_coherent(dmadev, CQ_SIZE(depth),
1185 &nvmeq->cq_dma_addr, GFP_KERNEL);
1186 if (!nvmeq->cqes)
1187 goto free_nvmeq;
1188
1189 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1190 &nvmeq->sq_dma_addr, GFP_KERNEL);
1191 if (!nvmeq->sq_cmds)
1192 goto free_cqdma;
1193
1194 nvmeq->q_dmadev = dmadev;
1195 nvmeq->dev = dev;
1196 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1197 dev->instance, qid);
1198 spin_lock_init(&nvmeq->q_lock);
1199 nvmeq->cq_head = 0;
1200 nvmeq->cq_phase = 1;
1201 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1202 nvmeq->q_depth = depth;
1203 nvmeq->cq_vector = vector;
1204 nvmeq->qid = qid;
1205 dev->queue_count++;
1206 dev->queues[qid] = nvmeq;
1207
1208 return nvmeq;
1209
1210 free_cqdma:
1211 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1212 nvmeq->cq_dma_addr);
1213 free_nvmeq:
1214 kfree(nvmeq);
1215 return NULL;
1216}
1217
1218static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1219 const char *name)
1220{
1221 if (use_threaded_interrupts)
1222 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1223 nvme_irq_check, nvme_irq, IRQF_SHARED,
1224 name, nvmeq);
1225 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1226 IRQF_SHARED, name, nvmeq);
1227}
1228
1229static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1230{
1231 struct nvme_dev *dev = nvmeq->dev;
1232
1233 spin_lock_irq(&nvmeq->q_lock);
1234 nvmeq->sq_tail = 0;
1235 nvmeq->cq_head = 0;
1236 nvmeq->cq_phase = 1;
1237 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1238 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1239 dev->online_queues++;
1240 spin_unlock_irq(&nvmeq->q_lock);
1241}
1242
1243static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1244{
1245 struct nvme_dev *dev = nvmeq->dev;
1246 int result;
1247
1248 result = adapter_alloc_cq(dev, qid, nvmeq);
1249 if (result < 0)
1250 return result;
1251
1252 result = adapter_alloc_sq(dev, qid, nvmeq);
1253 if (result < 0)
1254 goto release_cq;
1255
1256 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1257 if (result < 0)
1258 goto release_sq;
1259
1260 nvme_init_queue(nvmeq, qid);
1261 return result;
1262
1263 release_sq:
1264 adapter_delete_sq(dev, qid);
1265 release_cq:
1266 adapter_delete_cq(dev, qid);
1267 return result;
1268}
1269
1270static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1271{
1272 unsigned long timeout;
1273 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1274
1275 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1276
1277 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1278 msleep(100);
1279 if (fatal_signal_pending(current))
1280 return -EINTR;
1281 if (time_after(jiffies, timeout)) {
1282 dev_err(&dev->pci_dev->dev,
1283 "Device not ready; aborting %s\n", enabled ?
1284 "initialisation" : "reset");
1285 return -ENODEV;
1286 }
1287 }
1288
1289 return 0;
1290}
1291
1292/*
1293 * If the device has been passed off to us in an enabled state, just clear
1294 * the enabled bit. The spec says we should set the 'shutdown notification
1295 * bits', but doing so may cause the device to complete commands to the
1296 * admin queue ... and we don't know what memory that might be pointing at!
1297 */
1298static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1299{
1300 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1301 dev->ctrl_config &= ~NVME_CC_ENABLE;
1302 writel(dev->ctrl_config, &dev->bar->cc);
1303
1304 return nvme_wait_ready(dev, cap, false);
1305}
1306
1307static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1308{
1309 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1310 dev->ctrl_config |= NVME_CC_ENABLE;
1311 writel(dev->ctrl_config, &dev->bar->cc);
1312
1313 return nvme_wait_ready(dev, cap, true);
1314}
1315
1316static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1317{
1318 unsigned long timeout;
1319
1320 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1321 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1322
1323 writel(dev->ctrl_config, &dev->bar->cc);
1324
1325 timeout = SHUTDOWN_TIMEOUT + jiffies;
1326 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1327 NVME_CSTS_SHST_CMPLT) {
1328 msleep(100);
1329 if (fatal_signal_pending(current))
1330 return -EINTR;
1331 if (time_after(jiffies, timeout)) {
1332 dev_err(&dev->pci_dev->dev,
1333 "Device shutdown incomplete; abort shutdown\n");
1334 return -ENODEV;
1335 }
1336 }
1337
1338 return 0;
1339}
1340
1341static struct blk_mq_ops nvme_mq_admin_ops = {
1342 .queue_rq = nvme_admin_queue_rq,
1343 .map_queue = blk_mq_map_queue,
1344 .init_hctx = nvme_admin_init_hctx,
1345 .exit_hctx = nvme_exit_hctx,
1346 .init_request = nvme_admin_init_request,
1347 .timeout = nvme_timeout,
1348};
1349
1350static struct blk_mq_ops nvme_mq_ops = {
1351 .queue_rq = nvme_queue_rq,
1352 .map_queue = blk_mq_map_queue,
1353 .init_hctx = nvme_init_hctx,
1354 .exit_hctx = nvme_exit_hctx,
1355 .init_request = nvme_init_request,
1356 .timeout = nvme_timeout,
1357};
1358
1359static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1360{
1361 if (!dev->admin_q) {
1362 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1363 dev->admin_tagset.nr_hw_queues = 1;
1364 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1365 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1366 dev->admin_tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
1367 dev->admin_tagset.cmd_size = sizeof(struct nvme_cmd_info);
1368 dev->admin_tagset.driver_data = dev;
1369
1370 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1371 return -ENOMEM;
1372
1373 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
1374 if (!dev->admin_q) {
1375 blk_mq_free_tag_set(&dev->admin_tagset);
1376 return -ENOMEM;
1377 }
1378 }
1379
1380 return 0;
1381}
1382
1383static void nvme_free_admin_tags(struct nvme_dev *dev)
1384{
1385 if (dev->admin_q)
1386 blk_mq_free_tag_set(&dev->admin_tagset);
1387}
1388
1389static int nvme_configure_admin_queue(struct nvme_dev *dev)
1390{
1391 int result;
1392 u32 aqa;
1393 u64 cap = readq(&dev->bar->cap);
1394 struct nvme_queue *nvmeq;
1395 unsigned page_shift = PAGE_SHIFT;
1396 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1397 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1398
1399 if (page_shift < dev_page_min) {
1400 dev_err(&dev->pci_dev->dev,
1401 "Minimum device page size (%u) too large for "
1402 "host (%u)\n", 1 << dev_page_min,
1403 1 << page_shift);
1404 return -ENODEV;
1405 }
1406 if (page_shift > dev_page_max) {
1407 dev_info(&dev->pci_dev->dev,
1408 "Device maximum page size (%u) smaller than "
1409 "host (%u); enabling work-around\n",
1410 1 << dev_page_max, 1 << page_shift);
1411 page_shift = dev_page_max;
1412 }
1413
1414 result = nvme_disable_ctrl(dev, cap);
1415 if (result < 0)
1416 return result;
1417
1418 nvmeq = dev->queues[0];
1419 if (!nvmeq) {
1420 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH, 0);
1421 if (!nvmeq)
1422 return -ENOMEM;
1423 }
1424
1425 aqa = nvmeq->q_depth - 1;
1426 aqa |= aqa << 16;
1427
1428 dev->page_size = 1 << page_shift;
1429
1430 dev->ctrl_config = NVME_CC_CSS_NVM;
1431 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
1432 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1433 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1434
1435 writel(aqa, &dev->bar->aqa);
1436 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1437 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1438
1439 result = nvme_enable_ctrl(dev, cap);
1440 if (result)
1441 goto free_nvmeq;
1442
1443 result = nvme_alloc_admin_tags(dev);
1444 if (result)
1445 goto free_nvmeq;
1446
1447 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1448 if (result)
1449 goto free_tags;
1450
1451 return result;
1452
1453 free_tags:
1454 nvme_free_admin_tags(dev);
1455 free_nvmeq:
1456 nvme_free_queues(dev, 0);
1457 return result;
1458}
1459
1460struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
1461 unsigned long addr, unsigned length)
1462{
1463 int i, err, count, nents, offset;
1464 struct scatterlist *sg;
1465 struct page **pages;
1466 struct nvme_iod *iod;
1467
1468 if (addr & 3)
1469 return ERR_PTR(-EINVAL);
1470 if (!length || length > INT_MAX - PAGE_SIZE)
1471 return ERR_PTR(-EINVAL);
1472
1473 offset = offset_in_page(addr);
1474 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1475 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
1476 if (!pages)
1477 return ERR_PTR(-ENOMEM);
1478
1479 err = get_user_pages_fast(addr, count, 1, pages);
1480 if (err < count) {
1481 count = err;
1482 err = -EFAULT;
1483 goto put_pages;
1484 }
1485
1486 err = -ENOMEM;
1487 iod = nvme_alloc_iod(count, length, dev, GFP_KERNEL);
1488 if (!iod)
1489 goto put_pages;
1490
1491 sg = iod->sg;
1492 sg_init_table(sg, count);
1493 for (i = 0; i < count; i++) {
1494 sg_set_page(&sg[i], pages[i],
1495 min_t(unsigned, length, PAGE_SIZE - offset),
1496 offset);
1497 length -= (PAGE_SIZE - offset);
1498 offset = 0;
1499 }
1500 sg_mark_end(&sg[i - 1]);
1501 iod->nents = count;
1502
1503 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1504 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1505 if (!nents)
1506 goto free_iod;
1507
1508 kfree(pages);
1509 return iod;
1510
1511 free_iod:
1512 kfree(iod);
1513 put_pages:
1514 for (i = 0; i < count; i++)
1515 put_page(pages[i]);
1516 kfree(pages);
1517 return ERR_PTR(err);
1518}
1519
1520void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1521 struct nvme_iod *iod)
1522{
1523 int i;
1524
1525 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1526 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1527
1528 for (i = 0; i < iod->nents; i++)
1529 put_page(sg_page(&iod->sg[i]));
1530}
1531
1532static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1533{
1534 struct nvme_dev *dev = ns->dev;
1535 struct nvme_user_io io;
1536 struct nvme_command c;
1537 unsigned length, meta_len;
1538 int status, i;
1539 struct nvme_iod *iod, *meta_iod = NULL;
1540 dma_addr_t meta_dma_addr;
1541 void *meta, *uninitialized_var(meta_mem);
1542
1543 if (copy_from_user(&io, uio, sizeof(io)))
1544 return -EFAULT;
1545 length = (io.nblocks + 1) << ns->lba_shift;
1546 meta_len = (io.nblocks + 1) * ns->ms;
1547
1548 if (meta_len && ((io.metadata & 3) || !io.metadata))
1549 return -EINVAL;
1550
1551 switch (io.opcode) {
1552 case nvme_cmd_write:
1553 case nvme_cmd_read:
1554 case nvme_cmd_compare:
1555 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
1556 break;
1557 default:
1558 return -EINVAL;
1559 }
1560
1561 if (IS_ERR(iod))
1562 return PTR_ERR(iod);
1563
1564 memset(&c, 0, sizeof(c));
1565 c.rw.opcode = io.opcode;
1566 c.rw.flags = io.flags;
1567 c.rw.nsid = cpu_to_le32(ns->ns_id);
1568 c.rw.slba = cpu_to_le64(io.slba);
1569 c.rw.length = cpu_to_le16(io.nblocks);
1570 c.rw.control = cpu_to_le16(io.control);
1571 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1572 c.rw.reftag = cpu_to_le32(io.reftag);
1573 c.rw.apptag = cpu_to_le16(io.apptag);
1574 c.rw.appmask = cpu_to_le16(io.appmask);
1575
1576 if (meta_len) {
1577 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1578 meta_len);
1579 if (IS_ERR(meta_iod)) {
1580 status = PTR_ERR(meta_iod);
1581 meta_iod = NULL;
1582 goto unmap;
1583 }
1584
1585 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1586 &meta_dma_addr, GFP_KERNEL);
1587 if (!meta_mem) {
1588 status = -ENOMEM;
1589 goto unmap;
1590 }
1591
1592 if (io.opcode & 1) {
1593 int meta_offset = 0;
1594
1595 for (i = 0; i < meta_iod->nents; i++) {
1596 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1597 meta_iod->sg[i].offset;
1598 memcpy(meta_mem + meta_offset, meta,
1599 meta_iod->sg[i].length);
1600 kunmap_atomic(meta);
1601 meta_offset += meta_iod->sg[i].length;
1602 }
1603 }
1604
1605 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1606 }
1607
1608 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1609 c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1610 c.rw.prp2 = cpu_to_le64(iod->first_dma);
1611
1612 if (length != (io.nblocks + 1) << ns->lba_shift)
1613 status = -ENOMEM;
1614 else
1615 status = nvme_submit_io_cmd(dev, ns, &c, NULL);
1616
1617 if (meta_len) {
1618 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1619 int meta_offset = 0;
1620
1621 for (i = 0; i < meta_iod->nents; i++) {
1622 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1623 meta_iod->sg[i].offset;
1624 memcpy(meta, meta_mem + meta_offset,
1625 meta_iod->sg[i].length);
1626 kunmap_atomic(meta);
1627 meta_offset += meta_iod->sg[i].length;
1628 }
1629 }
1630
1631 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1632 meta_dma_addr);
1633 }
1634
1635 unmap:
1636 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
1637 nvme_free_iod(dev, iod);
1638
1639 if (meta_iod) {
1640 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1641 nvme_free_iod(dev, meta_iod);
1642 }
1643
1644 return status;
1645}
1646
1647static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1648 struct nvme_passthru_cmd __user *ucmd)
1649{
1650 struct nvme_passthru_cmd cmd;
1651 struct nvme_command c;
1652 int status, length;
1653 struct nvme_iod *uninitialized_var(iod);
1654 unsigned timeout;
1655
1656 if (!capable(CAP_SYS_ADMIN))
1657 return -EACCES;
1658 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1659 return -EFAULT;
1660
1661 memset(&c, 0, sizeof(c));
1662 c.common.opcode = cmd.opcode;
1663 c.common.flags = cmd.flags;
1664 c.common.nsid = cpu_to_le32(cmd.nsid);
1665 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1666 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1667 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1668 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1669 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1670 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1671 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1672 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1673
1674 length = cmd.data_len;
1675 if (cmd.data_len) {
1676 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1677 length);
1678 if (IS_ERR(iod))
1679 return PTR_ERR(iod);
1680 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1681 c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1682 c.common.prp2 = cpu_to_le64(iod->first_dma);
1683 }
1684
1685 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1686 ADMIN_TIMEOUT;
1687
1688 if (length != cmd.data_len)
1689 status = -ENOMEM;
1690 else if (ns) {
1691 struct request *req;
1692
1693 req = blk_mq_alloc_request(ns->queue, WRITE,
1694 (GFP_KERNEL|__GFP_WAIT), false);
1695 if (!req)
1696 status = -ENOMEM;
1697 else {
1698 status = nvme_submit_sync_cmd(req, &c, &cmd.result,
1699 timeout);
1700 blk_mq_free_request(req);
1701 }
1702 } else
1703 status = __nvme_submit_admin_cmd(dev, &c, &cmd.result, timeout);
1704
1705 if (cmd.data_len) {
1706 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
1707 nvme_free_iod(dev, iod);
1708 }
1709
1710 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
1711 sizeof(cmd.result)))
1712 status = -EFAULT;
1713
1714 return status;
1715}
1716
1717static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1718 unsigned long arg)
1719{
1720 struct nvme_ns *ns = bdev->bd_disk->private_data;
1721
1722 switch (cmd) {
1723 case NVME_IOCTL_ID:
1724 force_successful_syscall_return();
1725 return ns->ns_id;
1726 case NVME_IOCTL_ADMIN_CMD:
1727 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
1728 case NVME_IOCTL_IO_CMD:
1729 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
1730 case NVME_IOCTL_SUBMIT_IO:
1731 return nvme_submit_io(ns, (void __user *)arg);
1732 case SG_GET_VERSION_NUM:
1733 return nvme_sg_get_version_num((void __user *)arg);
1734 case SG_IO:
1735 return nvme_sg_io(ns, (void __user *)arg);
1736 default:
1737 return -ENOTTY;
1738 }
1739}
1740
1741#ifdef CONFIG_COMPAT
1742static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1743 unsigned int cmd, unsigned long arg)
1744{
1745 switch (cmd) {
1746 case SG_IO:
1747 return -ENOIOCTLCMD;
1748 }
1749 return nvme_ioctl(bdev, mode, cmd, arg);
1750}
1751#else
1752#define nvme_compat_ioctl NULL
1753#endif
1754
1755static int nvme_open(struct block_device *bdev, fmode_t mode)
1756{
1757 int ret = 0;
1758 struct nvme_ns *ns;
1759
1760 spin_lock(&dev_list_lock);
1761 ns = bdev->bd_disk->private_data;
1762 if (!ns)
1763 ret = -ENXIO;
1764 else if (!kref_get_unless_zero(&ns->dev->kref))
1765 ret = -ENXIO;
1766 spin_unlock(&dev_list_lock);
1767
1768 return ret;
1769}
1770
1771static void nvme_free_dev(struct kref *kref);
1772
1773static void nvme_release(struct gendisk *disk, fmode_t mode)
1774{
1775 struct nvme_ns *ns = disk->private_data;
1776 struct nvme_dev *dev = ns->dev;
1777
1778 kref_put(&dev->kref, nvme_free_dev);
1779}
1780
1781static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1782{
1783 /* some standard values */
1784 geo->heads = 1 << 6;
1785 geo->sectors = 1 << 5;
1786 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1787 return 0;
1788}
1789
1790static int nvme_revalidate_disk(struct gendisk *disk)
1791{
1792 struct nvme_ns *ns = disk->private_data;
1793 struct nvme_dev *dev = ns->dev;
1794 struct nvme_id_ns *id;
1795 dma_addr_t dma_addr;
1796 int lbaf;
1797
1798 id = dma_alloc_coherent(&dev->pci_dev->dev, 4096, &dma_addr,
1799 GFP_KERNEL);
1800 if (!id) {
1801 dev_warn(&dev->pci_dev->dev, "%s: Memory alocation failure\n",
1802 __func__);
1803 return 0;
1804 }
1805
1806 if (nvme_identify(dev, ns->ns_id, 0, dma_addr))
1807 goto free;
1808
1809 lbaf = id->flbas & 0xf;
1810 ns->lba_shift = id->lbaf[lbaf].ds;
1811
1812 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
1813 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1814 free:
1815 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1816 return 0;
1817}
1818
1819static const struct block_device_operations nvme_fops = {
1820 .owner = THIS_MODULE,
1821 .ioctl = nvme_ioctl,
1822 .compat_ioctl = nvme_compat_ioctl,
1823 .open = nvme_open,
1824 .release = nvme_release,
1825 .getgeo = nvme_getgeo,
1826 .revalidate_disk= nvme_revalidate_disk,
1827};
1828
1829static int nvme_kthread(void *data)
1830{
1831 struct nvme_dev *dev, *next;
1832
1833 while (!kthread_should_stop()) {
1834 set_current_state(TASK_INTERRUPTIBLE);
1835 spin_lock(&dev_list_lock);
1836 list_for_each_entry_safe(dev, next, &dev_list, node) {
1837 int i;
1838 if (readl(&dev->bar->csts) & NVME_CSTS_CFS &&
1839 dev->initialized) {
1840 if (work_busy(&dev->reset_work))
1841 continue;
1842 list_del_init(&dev->node);
1843 dev_warn(&dev->pci_dev->dev,
1844 "Failed status: %x, reset controller\n",
1845 readl(&dev->bar->csts));
1846 dev->reset_workfn = nvme_reset_failed_dev;
1847 queue_work(nvme_workq, &dev->reset_work);
1848 continue;
1849 }
1850 for (i = 0; i < dev->queue_count; i++) {
1851 struct nvme_queue *nvmeq = dev->queues[i];
1852 if (!nvmeq)
1853 continue;
1854 spin_lock_irq(&nvmeq->q_lock);
1855 nvme_process_cq(nvmeq);
1856
1857 while ((i == 0) && (dev->event_limit > 0)) {
1858 if (nvme_submit_async_admin_req(dev))
1859 break;
1860 dev->event_limit--;
1861 }
1862 spin_unlock_irq(&nvmeq->q_lock);
1863 }
1864 }
1865 spin_unlock(&dev_list_lock);
1866 schedule_timeout(round_jiffies_relative(HZ));
1867 }
1868 return 0;
1869}
1870
1871static void nvme_config_discard(struct nvme_ns *ns)
1872{
1873 u32 logical_block_size = queue_logical_block_size(ns->queue);
1874 ns->queue->limits.discard_zeroes_data = 0;
1875 ns->queue->limits.discard_alignment = logical_block_size;
1876 ns->queue->limits.discard_granularity = logical_block_size;
1877 ns->queue->limits.max_discard_sectors = 0xffffffff;
1878 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1879}
1880
1881static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid,
1882 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1883{
1884 struct nvme_ns *ns;
1885 struct gendisk *disk;
1886 int node = dev_to_node(&dev->pci_dev->dev);
1887 int lbaf;
1888
1889 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1890 return NULL;
1891
1892 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
1893 if (!ns)
1894 return NULL;
1895 ns->queue = blk_mq_init_queue(&dev->tagset);
1896 if (IS_ERR(ns->queue))
1897 goto out_free_ns;
1898 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1899 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
1900 queue_flag_set_unlocked(QUEUE_FLAG_SG_GAPS, ns->queue);
1901 ns->dev = dev;
1902 ns->queue->queuedata = ns;
1903
1904 disk = alloc_disk_node(0, node);
1905 if (!disk)
1906 goto out_free_queue;
1907
1908 ns->ns_id = nsid;
1909 ns->disk = disk;
1910 lbaf = id->flbas & 0xf;
1911 ns->lba_shift = id->lbaf[lbaf].ds;
1912 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
1913 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
1914 if (dev->max_hw_sectors)
1915 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
1916 if (dev->stripe_size)
1917 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
1918 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
1919 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
1920
1921 disk->major = nvme_major;
1922 disk->first_minor = 0;
1923 disk->fops = &nvme_fops;
1924 disk->private_data = ns;
1925 disk->queue = ns->queue;
1926 disk->driverfs_dev = &dev->pci_dev->dev;
1927 disk->flags = GENHD_FL_EXT_DEVT;
1928 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
1929 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1930
1931 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1932 nvme_config_discard(ns);
1933
1934 return ns;
1935
1936 out_free_queue:
1937 blk_cleanup_queue(ns->queue);
1938 out_free_ns:
1939 kfree(ns);
1940 return NULL;
1941}
1942
1943static void nvme_create_io_queues(struct nvme_dev *dev)
1944{
1945 unsigned i;
1946
1947 for (i = dev->queue_count; i <= dev->max_qid; i++)
1948 if (!nvme_alloc_queue(dev, i, dev->q_depth, i - 1))
1949 break;
1950
1951 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
1952 if (nvme_create_queue(dev->queues[i], i))
1953 break;
1954}
1955
1956static int set_queue_count(struct nvme_dev *dev, int count)
1957{
1958 int status;
1959 u32 result;
1960 u32 q_count = (count - 1) | ((count - 1) << 16);
1961
1962 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
1963 &result);
1964 if (status < 0)
1965 return status;
1966 if (status > 0) {
1967 dev_err(&dev->pci_dev->dev, "Could not set queue count (%d)\n",
1968 status);
1969 return 0;
1970 }
1971 return min(result & 0xffff, result >> 16) + 1;
1972}
1973
1974static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1975{
1976 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1977}
1978
1979static int nvme_setup_io_queues(struct nvme_dev *dev)
1980{
1981 struct nvme_queue *adminq = dev->queues[0];
1982 struct pci_dev *pdev = dev->pci_dev;
1983 int result, i, vecs, nr_io_queues, size;
1984
1985 nr_io_queues = num_possible_cpus();
1986 result = set_queue_count(dev, nr_io_queues);
1987 if (result <= 0)
1988 return result;
1989 if (result < nr_io_queues)
1990 nr_io_queues = result;
1991
1992 size = db_bar_size(dev, nr_io_queues);
1993 if (size > 8192) {
1994 iounmap(dev->bar);
1995 do {
1996 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1997 if (dev->bar)
1998 break;
1999 if (!--nr_io_queues)
2000 return -ENOMEM;
2001 size = db_bar_size(dev, nr_io_queues);
2002 } while (1);
2003 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2004 adminq->q_db = dev->dbs;
2005 }
2006
2007 /* Deregister the admin queue's interrupt */
2008 free_irq(dev->entry[0].vector, adminq);
2009
2010 /*
2011 * If we enable msix early due to not intx, disable it again before
2012 * setting up the full range we need.
2013 */
2014 if (!pdev->irq)
2015 pci_disable_msix(pdev);
2016
2017 for (i = 0; i < nr_io_queues; i++)
2018 dev->entry[i].entry = i;
2019 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2020 if (vecs < 0) {
2021 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2022 if (vecs < 0) {
2023 vecs = 1;
2024 } else {
2025 for (i = 0; i < vecs; i++)
2026 dev->entry[i].vector = i + pdev->irq;
2027 }
2028 }
2029
2030 /*
2031 * Should investigate if there's a performance win from allocating
2032 * more queues than interrupt vectors; it might allow the submission
2033 * path to scale better, even if the receive path is limited by the
2034 * number of interrupts.
2035 */
2036 nr_io_queues = vecs;
2037 dev->max_qid = nr_io_queues;
2038
2039 result = queue_request_irq(dev, adminq, adminq->irqname);
2040 if (result)
2041 goto free_queues;
2042
2043 /* Free previously allocated queues that are no longer usable */
2044 nvme_free_queues(dev, nr_io_queues + 1);
2045 nvme_create_io_queues(dev);
2046
2047 return 0;
2048
2049 free_queues:
2050 nvme_free_queues(dev, 1);
2051 return result;
2052}
2053
2054/*
2055 * Return: error value if an error occurred setting up the queues or calling
2056 * Identify Device. 0 if these succeeded, even if adding some of the
2057 * namespaces failed. At the moment, these failures are silent. TBD which
2058 * failures should be reported.
2059 */
2060static int nvme_dev_add(struct nvme_dev *dev)
2061{
2062 struct pci_dev *pdev = dev->pci_dev;
2063 int res;
2064 unsigned nn, i;
2065 struct nvme_ns *ns;
2066 struct nvme_id_ctrl *ctrl;
2067 struct nvme_id_ns *id_ns;
2068 void *mem;
2069 dma_addr_t dma_addr;
2070 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
2071
2072 mem = dma_alloc_coherent(&pdev->dev, 8192, &dma_addr, GFP_KERNEL);
2073 if (!mem)
2074 return -ENOMEM;
2075
2076 res = nvme_identify(dev, 0, 1, dma_addr);
2077 if (res) {
2078 dev_err(&pdev->dev, "Identify Controller failed (%d)\n", res);
2079 res = -EIO;
2080 goto out;
2081 }
2082
2083 ctrl = mem;
2084 nn = le32_to_cpup(&ctrl->nn);
2085 dev->oncs = le16_to_cpup(&ctrl->oncs);
2086 dev->abort_limit = ctrl->acl + 1;
2087 dev->vwc = ctrl->vwc;
2088 dev->event_limit = min(ctrl->aerl + 1, 8);
2089 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2090 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2091 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
2092 if (ctrl->mdts)
2093 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
2094 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
2095 (pdev->device == 0x0953) && ctrl->vs[3]) {
2096 unsigned int max_hw_sectors;
2097
2098 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
2099 max_hw_sectors = dev->stripe_size >> (shift - 9);
2100 if (dev->max_hw_sectors) {
2101 dev->max_hw_sectors = min(max_hw_sectors,
2102 dev->max_hw_sectors);
2103 } else
2104 dev->max_hw_sectors = max_hw_sectors;
2105 }
2106
2107 dev->tagset.ops = &nvme_mq_ops;
2108 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2109 dev->tagset.timeout = NVME_IO_TIMEOUT;
2110 dev->tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
2111 dev->tagset.queue_depth =
2112 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2113 dev->tagset.cmd_size = sizeof(struct nvme_cmd_info);
2114 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2115 dev->tagset.driver_data = dev;
2116
2117 if (blk_mq_alloc_tag_set(&dev->tagset))
2118 goto out;
2119
2120 id_ns = mem;
2121 for (i = 1; i <= nn; i++) {
2122 res = nvme_identify(dev, i, 0, dma_addr);
2123 if (res)
2124 continue;
2125
2126 if (id_ns->ncap == 0)
2127 continue;
2128
2129 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
2130 dma_addr + 4096, NULL);
2131 if (res)
2132 memset(mem + 4096, 0, 4096);
2133
2134 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
2135 if (ns)
2136 list_add_tail(&ns->list, &dev->namespaces);
2137 }
2138 list_for_each_entry(ns, &dev->namespaces, list)
2139 add_disk(ns->disk);
2140 res = 0;
2141
2142 out:
2143 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
2144 return res;
2145}
2146
2147static int nvme_dev_map(struct nvme_dev *dev)
2148{
2149 u64 cap;
2150 int bars, result = -ENOMEM;
2151 struct pci_dev *pdev = dev->pci_dev;
2152
2153 if (pci_enable_device_mem(pdev))
2154 return result;
2155
2156 dev->entry[0].vector = pdev->irq;
2157 pci_set_master(pdev);
2158 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2159 if (!bars)
2160 goto disable_pci;
2161
2162 if (pci_request_selected_regions(pdev, bars, "nvme"))
2163 goto disable_pci;
2164
2165 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2166 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2167 goto disable;
2168
2169 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2170 if (!dev->bar)
2171 goto disable;
2172
2173 if (readl(&dev->bar->csts) == -1) {
2174 result = -ENODEV;
2175 goto unmap;
2176 }
2177
2178 /*
2179 * Some devices don't advertse INTx interrupts, pre-enable a single
2180 * MSIX vec for setup. We'll adjust this later.
2181 */
2182 if (!pdev->irq) {
2183 result = pci_enable_msix(pdev, dev->entry, 1);
2184 if (result < 0)
2185 goto unmap;
2186 }
2187
2188 cap = readq(&dev->bar->cap);
2189 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2190 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
2191 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2192
2193 return 0;
2194
2195 unmap:
2196 iounmap(dev->bar);
2197 dev->bar = NULL;
2198 disable:
2199 pci_release_regions(pdev);
2200 disable_pci:
2201 pci_disable_device(pdev);
2202 return result;
2203}
2204
2205static void nvme_dev_unmap(struct nvme_dev *dev)
2206{
2207 if (dev->pci_dev->msi_enabled)
2208 pci_disable_msi(dev->pci_dev);
2209 else if (dev->pci_dev->msix_enabled)
2210 pci_disable_msix(dev->pci_dev);
2211
2212 if (dev->bar) {
2213 iounmap(dev->bar);
2214 dev->bar = NULL;
2215 pci_release_regions(dev->pci_dev);
2216 }
2217
2218 if (pci_is_enabled(dev->pci_dev))
2219 pci_disable_device(dev->pci_dev);
2220}
2221
2222struct nvme_delq_ctx {
2223 struct task_struct *waiter;
2224 struct kthread_worker *worker;
2225 atomic_t refcount;
2226};
2227
2228static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2229{
2230 dq->waiter = current;
2231 mb();
2232
2233 for (;;) {
2234 set_current_state(TASK_KILLABLE);
2235 if (!atomic_read(&dq->refcount))
2236 break;
2237 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2238 fatal_signal_pending(current)) {
2239 set_current_state(TASK_RUNNING);
2240
2241 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
2242 nvme_disable_queue(dev, 0);
2243
2244 send_sig(SIGKILL, dq->worker->task, 1);
2245 flush_kthread_worker(dq->worker);
2246 return;
2247 }
2248 }
2249 set_current_state(TASK_RUNNING);
2250}
2251
2252static void nvme_put_dq(struct nvme_delq_ctx *dq)
2253{
2254 atomic_dec(&dq->refcount);
2255 if (dq->waiter)
2256 wake_up_process(dq->waiter);
2257}
2258
2259static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2260{
2261 atomic_inc(&dq->refcount);
2262 return dq;
2263}
2264
2265static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2266{
2267 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2268
2269 nvme_clear_queue(nvmeq);
2270 nvme_put_dq(dq);
2271}
2272
2273static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2274 kthread_work_func_t fn)
2275{
2276 struct nvme_command c;
2277
2278 memset(&c, 0, sizeof(c));
2279 c.delete_queue.opcode = opcode;
2280 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2281
2282 init_kthread_work(&nvmeq->cmdinfo.work, fn);
2283 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2284 ADMIN_TIMEOUT);
2285}
2286
2287static void nvme_del_cq_work_handler(struct kthread_work *work)
2288{
2289 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2290 cmdinfo.work);
2291 nvme_del_queue_end(nvmeq);
2292}
2293
2294static int nvme_delete_cq(struct nvme_queue *nvmeq)
2295{
2296 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2297 nvme_del_cq_work_handler);
2298}
2299
2300static void nvme_del_sq_work_handler(struct kthread_work *work)
2301{
2302 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2303 cmdinfo.work);
2304 int status = nvmeq->cmdinfo.status;
2305
2306 if (!status)
2307 status = nvme_delete_cq(nvmeq);
2308 if (status)
2309 nvme_del_queue_end(nvmeq);
2310}
2311
2312static int nvme_delete_sq(struct nvme_queue *nvmeq)
2313{
2314 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2315 nvme_del_sq_work_handler);
2316}
2317
2318static void nvme_del_queue_start(struct kthread_work *work)
2319{
2320 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2321 cmdinfo.work);
2322 allow_signal(SIGKILL);
2323 if (nvme_delete_sq(nvmeq))
2324 nvme_del_queue_end(nvmeq);
2325}
2326
2327static void nvme_disable_io_queues(struct nvme_dev *dev)
2328{
2329 int i;
2330 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2331 struct nvme_delq_ctx dq;
2332 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2333 &worker, "nvme%d", dev->instance);
2334
2335 if (IS_ERR(kworker_task)) {
2336 dev_err(&dev->pci_dev->dev,
2337 "Failed to create queue del task\n");
2338 for (i = dev->queue_count - 1; i > 0; i--)
2339 nvme_disable_queue(dev, i);
2340 return;
2341 }
2342
2343 dq.waiter = NULL;
2344 atomic_set(&dq.refcount, 0);
2345 dq.worker = &worker;
2346 for (i = dev->queue_count - 1; i > 0; i--) {
2347 struct nvme_queue *nvmeq = dev->queues[i];
2348
2349 if (nvme_suspend_queue(nvmeq))
2350 continue;
2351 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2352 nvmeq->cmdinfo.worker = dq.worker;
2353 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2354 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2355 }
2356 nvme_wait_dq(&dq, dev);
2357 kthread_stop(kworker_task);
2358}
2359
2360/*
2361* Remove the node from the device list and check
2362* for whether or not we need to stop the nvme_thread.
2363*/
2364static void nvme_dev_list_remove(struct nvme_dev *dev)
2365{
2366 struct task_struct *tmp = NULL;
2367
2368 spin_lock(&dev_list_lock);
2369 list_del_init(&dev->node);
2370 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2371 tmp = nvme_thread;
2372 nvme_thread = NULL;
2373 }
2374 spin_unlock(&dev_list_lock);
2375
2376 if (tmp)
2377 kthread_stop(tmp);
2378}
2379
2380static void nvme_dev_shutdown(struct nvme_dev *dev)
2381{
2382 int i;
2383 u32 csts = -1;
2384
2385 dev->initialized = 0;
2386 nvme_dev_list_remove(dev);
2387
2388 if (dev->bar)
2389 csts = readl(&dev->bar->csts);
2390 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
2391 for (i = dev->queue_count - 1; i >= 0; i--) {
2392 struct nvme_queue *nvmeq = dev->queues[i];
2393 nvme_suspend_queue(nvmeq);
2394 nvme_clear_queue(nvmeq);
2395 }
2396 } else {
2397 nvme_disable_io_queues(dev);
2398 nvme_shutdown_ctrl(dev);
2399 nvme_disable_queue(dev, 0);
2400 }
2401 nvme_dev_unmap(dev);
2402}
2403
2404static void nvme_dev_remove_admin(struct nvme_dev *dev)
2405{
2406 if (dev->admin_q && !blk_queue_dying(dev->admin_q))
2407 blk_cleanup_queue(dev->admin_q);
2408}
2409
2410static void nvme_dev_remove(struct nvme_dev *dev)
2411{
2412 struct nvme_ns *ns;
2413
2414 list_for_each_entry(ns, &dev->namespaces, list) {
2415 if (ns->disk->flags & GENHD_FL_UP)
2416 del_gendisk(ns->disk);
2417 if (!blk_queue_dying(ns->queue))
2418 blk_cleanup_queue(ns->queue);
2419 }
2420}
2421
2422static int nvme_setup_prp_pools(struct nvme_dev *dev)
2423{
2424 struct device *dmadev = &dev->pci_dev->dev;
2425 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2426 PAGE_SIZE, PAGE_SIZE, 0);
2427 if (!dev->prp_page_pool)
2428 return -ENOMEM;
2429
2430 /* Optimisation for I/Os between 4k and 128k */
2431 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2432 256, 256, 0);
2433 if (!dev->prp_small_pool) {
2434 dma_pool_destroy(dev->prp_page_pool);
2435 return -ENOMEM;
2436 }
2437 return 0;
2438}
2439
2440static void nvme_release_prp_pools(struct nvme_dev *dev)
2441{
2442 dma_pool_destroy(dev->prp_page_pool);
2443 dma_pool_destroy(dev->prp_small_pool);
2444}
2445
2446static DEFINE_IDA(nvme_instance_ida);
2447
2448static int nvme_set_instance(struct nvme_dev *dev)
2449{
2450 int instance, error;
2451
2452 do {
2453 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2454 return -ENODEV;
2455
2456 spin_lock(&dev_list_lock);
2457 error = ida_get_new(&nvme_instance_ida, &instance);
2458 spin_unlock(&dev_list_lock);
2459 } while (error == -EAGAIN);
2460
2461 if (error)
2462 return -ENODEV;
2463
2464 dev->instance = instance;
2465 return 0;
2466}
2467
2468static void nvme_release_instance(struct nvme_dev *dev)
2469{
2470 spin_lock(&dev_list_lock);
2471 ida_remove(&nvme_instance_ida, dev->instance);
2472 spin_unlock(&dev_list_lock);
2473}
2474
2475static void nvme_free_namespaces(struct nvme_dev *dev)
2476{
2477 struct nvme_ns *ns, *next;
2478
2479 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2480 list_del(&ns->list);
2481
2482 spin_lock(&dev_list_lock);
2483 ns->disk->private_data = NULL;
2484 spin_unlock(&dev_list_lock);
2485
2486 put_disk(ns->disk);
2487 kfree(ns);
2488 }
2489}
2490
2491static void nvme_free_dev(struct kref *kref)
2492{
2493 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
2494
2495 pci_dev_put(dev->pci_dev);
2496 nvme_free_namespaces(dev);
2497 blk_mq_free_tag_set(&dev->tagset);
2498 kfree(dev->queues);
2499 kfree(dev->entry);
2500 kfree(dev);
2501}
2502
2503static int nvme_dev_open(struct inode *inode, struct file *f)
2504{
2505 struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
2506 miscdev);
2507 kref_get(&dev->kref);
2508 f->private_data = dev;
2509 return 0;
2510}
2511
2512static int nvme_dev_release(struct inode *inode, struct file *f)
2513{
2514 struct nvme_dev *dev = f->private_data;
2515 kref_put(&dev->kref, nvme_free_dev);
2516 return 0;
2517}
2518
2519static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2520{
2521 struct nvme_dev *dev = f->private_data;
2522 struct nvme_ns *ns;
2523
2524 switch (cmd) {
2525 case NVME_IOCTL_ADMIN_CMD:
2526 return nvme_user_cmd(dev, NULL, (void __user *)arg);
2527 case NVME_IOCTL_IO_CMD:
2528 if (list_empty(&dev->namespaces))
2529 return -ENOTTY;
2530 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
2531 return nvme_user_cmd(dev, ns, (void __user *)arg);
2532 default:
2533 return -ENOTTY;
2534 }
2535}
2536
2537static const struct file_operations nvme_dev_fops = {
2538 .owner = THIS_MODULE,
2539 .open = nvme_dev_open,
2540 .release = nvme_dev_release,
2541 .unlocked_ioctl = nvme_dev_ioctl,
2542 .compat_ioctl = nvme_dev_ioctl,
2543};
2544
2545static void nvme_set_irq_hints(struct nvme_dev *dev)
2546{
2547 struct nvme_queue *nvmeq;
2548 int i;
2549
2550 for (i = 0; i < dev->online_queues; i++) {
2551 nvmeq = dev->queues[i];
2552
2553 if (!nvmeq->hctx)
2554 continue;
2555
2556 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2557 nvmeq->hctx->cpumask);
2558 }
2559}
2560
2561static int nvme_dev_start(struct nvme_dev *dev)
2562{
2563 int result;
2564 bool start_thread = false;
2565
2566 result = nvme_dev_map(dev);
2567 if (result)
2568 return result;
2569
2570 result = nvme_configure_admin_queue(dev);
2571 if (result)
2572 goto unmap;
2573
2574 spin_lock(&dev_list_lock);
2575 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2576 start_thread = true;
2577 nvme_thread = NULL;
2578 }
2579 list_add(&dev->node, &dev_list);
2580 spin_unlock(&dev_list_lock);
2581
2582 if (start_thread) {
2583 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2584 wake_up_all(&nvme_kthread_wait);
2585 } else
2586 wait_event_killable(nvme_kthread_wait, nvme_thread);
2587
2588 if (IS_ERR_OR_NULL(nvme_thread)) {
2589 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2590 goto disable;
2591 }
2592
2593 nvme_init_queue(dev->queues[0], 0);
2594
2595 result = nvme_setup_io_queues(dev);
2596 if (result)
2597 goto disable;
2598
2599 nvme_set_irq_hints(dev);
2600
2601 return result;
2602
2603 disable:
2604 nvme_disable_queue(dev, 0);
2605 nvme_dev_list_remove(dev);
2606 unmap:
2607 nvme_dev_unmap(dev);
2608 return result;
2609}
2610
2611static int nvme_remove_dead_ctrl(void *arg)
2612{
2613 struct nvme_dev *dev = (struct nvme_dev *)arg;
2614 struct pci_dev *pdev = dev->pci_dev;
2615
2616 if (pci_get_drvdata(pdev))
2617 pci_stop_and_remove_bus_device_locked(pdev);
2618 kref_put(&dev->kref, nvme_free_dev);
2619 return 0;
2620}
2621
2622static void nvme_remove_disks(struct work_struct *ws)
2623{
2624 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2625
2626 nvme_free_queues(dev, 1);
2627 nvme_dev_remove(dev);
2628}
2629
2630static int nvme_dev_resume(struct nvme_dev *dev)
2631{
2632 int ret;
2633
2634 ret = nvme_dev_start(dev);
2635 if (ret)
2636 return ret;
2637 if (dev->online_queues < 2) {
2638 spin_lock(&dev_list_lock);
2639 dev->reset_workfn = nvme_remove_disks;
2640 queue_work(nvme_workq, &dev->reset_work);
2641 spin_unlock(&dev_list_lock);
2642 }
2643 dev->initialized = 1;
2644 return 0;
2645}
2646
2647static void nvme_dev_reset(struct nvme_dev *dev)
2648{
2649 nvme_dev_shutdown(dev);
2650 if (nvme_dev_resume(dev)) {
2651 dev_warn(&dev->pci_dev->dev, "Device failed to resume\n");
2652 kref_get(&dev->kref);
2653 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2654 dev->instance))) {
2655 dev_err(&dev->pci_dev->dev,
2656 "Failed to start controller remove task\n");
2657 kref_put(&dev->kref, nvme_free_dev);
2658 }
2659 }
2660}
2661
2662static void nvme_reset_failed_dev(struct work_struct *ws)
2663{
2664 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2665 nvme_dev_reset(dev);
2666}
2667
2668static void nvme_reset_workfn(struct work_struct *work)
2669{
2670 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2671 dev->reset_workfn(work);
2672}
2673
2674static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2675{
2676 int node, result = -ENOMEM;
2677 struct nvme_dev *dev;
2678
2679 node = dev_to_node(&pdev->dev);
2680 if (node == NUMA_NO_NODE)
2681 set_dev_node(&pdev->dev, 0);
2682
2683 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2684 if (!dev)
2685 return -ENOMEM;
2686 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2687 GFP_KERNEL, node);
2688 if (!dev->entry)
2689 goto free;
2690 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2691 GFP_KERNEL, node);
2692 if (!dev->queues)
2693 goto free;
2694
2695 INIT_LIST_HEAD(&dev->namespaces);
2696 dev->reset_workfn = nvme_reset_failed_dev;
2697 INIT_WORK(&dev->reset_work, nvme_reset_workfn);
2698 dev->pci_dev = pci_dev_get(pdev);
2699 pci_set_drvdata(pdev, dev);
2700 result = nvme_set_instance(dev);
2701 if (result)
2702 goto put_pci;
2703
2704 result = nvme_setup_prp_pools(dev);
2705 if (result)
2706 goto release;
2707
2708 kref_init(&dev->kref);
2709 result = nvme_dev_start(dev);
2710 if (result)
2711 goto release_pools;
2712
2713 if (dev->online_queues > 1)
2714 result = nvme_dev_add(dev);
2715 if (result)
2716 goto shutdown;
2717
2718 scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
2719 dev->miscdev.minor = MISC_DYNAMIC_MINOR;
2720 dev->miscdev.parent = &pdev->dev;
2721 dev->miscdev.name = dev->name;
2722 dev->miscdev.fops = &nvme_dev_fops;
2723 result = misc_register(&dev->miscdev);
2724 if (result)
2725 goto remove;
2726
2727 nvme_set_irq_hints(dev);
2728
2729 dev->initialized = 1;
2730 return 0;
2731
2732 remove:
2733 nvme_dev_remove(dev);
2734 nvme_dev_remove_admin(dev);
2735 nvme_free_namespaces(dev);
2736 shutdown:
2737 nvme_dev_shutdown(dev);
2738 release_pools:
2739 nvme_free_queues(dev, 0);
2740 nvme_release_prp_pools(dev);
2741 release:
2742 nvme_release_instance(dev);
2743 put_pci:
2744 pci_dev_put(dev->pci_dev);
2745 free:
2746 kfree(dev->queues);
2747 kfree(dev->entry);
2748 kfree(dev);
2749 return result;
2750}
2751
2752static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2753{
2754 struct nvme_dev *dev = pci_get_drvdata(pdev);
2755
2756 if (prepare)
2757 nvme_dev_shutdown(dev);
2758 else
2759 nvme_dev_resume(dev);
2760}
2761
2762static void nvme_shutdown(struct pci_dev *pdev)
2763{
2764 struct nvme_dev *dev = pci_get_drvdata(pdev);
2765 nvme_dev_shutdown(dev);
2766}
2767
2768static void nvme_remove(struct pci_dev *pdev)
2769{
2770 struct nvme_dev *dev = pci_get_drvdata(pdev);
2771
2772 spin_lock(&dev_list_lock);
2773 list_del_init(&dev->node);
2774 spin_unlock(&dev_list_lock);
2775
2776 pci_set_drvdata(pdev, NULL);
2777 flush_work(&dev->reset_work);
2778 misc_deregister(&dev->miscdev);
2779 nvme_dev_remove(dev);
2780 nvme_dev_shutdown(dev);
2781 nvme_dev_remove_admin(dev);
2782 nvme_free_queues(dev, 0);
2783 nvme_free_admin_tags(dev);
2784 nvme_release_instance(dev);
2785 nvme_release_prp_pools(dev);
2786 kref_put(&dev->kref, nvme_free_dev);
2787}
2788
2789/* These functions are yet to be implemented */
2790#define nvme_error_detected NULL
2791#define nvme_dump_registers NULL
2792#define nvme_link_reset NULL
2793#define nvme_slot_reset NULL
2794#define nvme_error_resume NULL
2795
2796#ifdef CONFIG_PM_SLEEP
2797static int nvme_suspend(struct device *dev)
2798{
2799 struct pci_dev *pdev = to_pci_dev(dev);
2800 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2801
2802 nvme_dev_shutdown(ndev);
2803 return 0;
2804}
2805
2806static int nvme_resume(struct device *dev)
2807{
2808 struct pci_dev *pdev = to_pci_dev(dev);
2809 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2810
2811 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
2812 ndev->reset_workfn = nvme_reset_failed_dev;
2813 queue_work(nvme_workq, &ndev->reset_work);
2814 }
2815 return 0;
2816}
2817#endif
2818
2819static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2820
2821static const struct pci_error_handlers nvme_err_handler = {
2822 .error_detected = nvme_error_detected,
2823 .mmio_enabled = nvme_dump_registers,
2824 .link_reset = nvme_link_reset,
2825 .slot_reset = nvme_slot_reset,
2826 .resume = nvme_error_resume,
2827 .reset_notify = nvme_reset_notify,
2828};
2829
2830/* Move to pci_ids.h later */
2831#define PCI_CLASS_STORAGE_EXPRESS 0x010802
2832
2833static const struct pci_device_id nvme_id_table[] = {
2834 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2835 { 0, }
2836};
2837MODULE_DEVICE_TABLE(pci, nvme_id_table);
2838
2839static struct pci_driver nvme_driver = {
2840 .name = "nvme",
2841 .id_table = nvme_id_table,
2842 .probe = nvme_probe,
2843 .remove = nvme_remove,
2844 .shutdown = nvme_shutdown,
2845 .driver = {
2846 .pm = &nvme_dev_pm_ops,
2847 },
2848 .err_handler = &nvme_err_handler,
2849};
2850
2851static int __init nvme_init(void)
2852{
2853 int result;
2854
2855 init_waitqueue_head(&nvme_kthread_wait);
2856
2857 nvme_workq = create_singlethread_workqueue("nvme");
2858 if (!nvme_workq)
2859 return -ENOMEM;
2860
2861 result = register_blkdev(nvme_major, "nvme");
2862 if (result < 0)
2863 goto kill_workq;
2864 else if (result > 0)
2865 nvme_major = result;
2866
2867 result = pci_register_driver(&nvme_driver);
2868 if (result)
2869 goto unregister_blkdev;
2870 return 0;
2871
2872 unregister_blkdev:
2873 unregister_blkdev(nvme_major, "nvme");
2874 kill_workq:
2875 destroy_workqueue(nvme_workq);
2876 return result;
2877}
2878
2879static void __exit nvme_exit(void)
2880{
2881 pci_unregister_driver(&nvme_driver);
2882 unregister_hotcpu_notifier(&nvme_nb);
2883 unregister_blkdev(nvme_major, "nvme");
2884 destroy_workqueue(nvme_workq);
2885 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
2886 _nvme_check_size();
2887}
2888
2889MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2890MODULE_LICENSE("GPL");
2891MODULE_VERSION("0.9");
2892module_init(nvme_init);
2893module_exit(nvme_exit);
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