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1 | // SPDX-License-Identifier: GPL-2.0 | |
2 | /* | |
3 | * ti-sysc.c - Texas Instruments sysc interconnect target driver | |
4 | */ | |
5 | ||
6 | #include <linux/io.h> | |
7 | #include <linux/clk.h> | |
8 | #include <linux/clkdev.h> | |
9 | #include <linux/delay.h> | |
10 | #include <linux/list.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/platform_device.h> | |
13 | #include <linux/pm_domain.h> | |
14 | #include <linux/pm_runtime.h> | |
15 | #include <linux/reset.h> | |
16 | #include <linux/of_address.h> | |
17 | #include <linux/of_platform.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/sys_soc.h> | |
20 | #include <linux/iopoll.h> | |
21 | ||
22 | #include <linux/platform_data/ti-sysc.h> | |
23 | ||
24 | #include <dt-bindings/bus/ti-sysc.h> | |
25 | ||
26 | #define DIS_ISP BIT(2) | |
27 | #define DIS_IVA BIT(1) | |
28 | #define DIS_SGX BIT(0) | |
29 | ||
30 | #define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), } | |
31 | ||
32 | #define MAX_MODULE_SOFTRESET_WAIT 10000 | |
33 | ||
34 | enum sysc_soc { | |
35 | SOC_UNKNOWN, | |
36 | SOC_2420, | |
37 | SOC_2430, | |
38 | SOC_3430, | |
39 | SOC_3630, | |
40 | SOC_4430, | |
41 | SOC_4460, | |
42 | SOC_4470, | |
43 | SOC_5430, | |
44 | SOC_AM3, | |
45 | SOC_AM4, | |
46 | SOC_DRA7, | |
47 | }; | |
48 | ||
49 | struct sysc_address { | |
50 | unsigned long base; | |
51 | struct list_head node; | |
52 | }; | |
53 | ||
54 | struct sysc_soc_info { | |
55 | unsigned long general_purpose:1; | |
56 | enum sysc_soc soc; | |
57 | struct mutex list_lock; /* disabled modules list lock */ | |
58 | struct list_head disabled_modules; | |
59 | }; | |
60 | ||
61 | enum sysc_clocks { | |
62 | SYSC_FCK, | |
63 | SYSC_ICK, | |
64 | SYSC_OPTFCK0, | |
65 | SYSC_OPTFCK1, | |
66 | SYSC_OPTFCK2, | |
67 | SYSC_OPTFCK3, | |
68 | SYSC_OPTFCK4, | |
69 | SYSC_OPTFCK5, | |
70 | SYSC_OPTFCK6, | |
71 | SYSC_OPTFCK7, | |
72 | SYSC_MAX_CLOCKS, | |
73 | }; | |
74 | ||
75 | static struct sysc_soc_info *sysc_soc; | |
76 | static const char * const reg_names[] = { "rev", "sysc", "syss", }; | |
77 | static const char * const clock_names[SYSC_MAX_CLOCKS] = { | |
78 | "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4", | |
79 | "opt5", "opt6", "opt7", | |
80 | }; | |
81 | ||
82 | #define SYSC_IDLEMODE_MASK 3 | |
83 | #define SYSC_CLOCKACTIVITY_MASK 3 | |
84 | ||
85 | /** | |
86 | * struct sysc - TI sysc interconnect target module registers and capabilities | |
87 | * @dev: struct device pointer | |
88 | * @module_pa: physical address of the interconnect target module | |
89 | * @module_size: size of the interconnect target module | |
90 | * @module_va: virtual address of the interconnect target module | |
91 | * @offsets: register offsets from module base | |
92 | * @mdata: ti-sysc to hwmod translation data for a module | |
93 | * @clocks: clocks used by the interconnect target module | |
94 | * @clock_roles: clock role names for the found clocks | |
95 | * @nr_clocks: number of clocks used by the interconnect target module | |
96 | * @rsts: resets used by the interconnect target module | |
97 | * @legacy_mode: configured for legacy mode if set | |
98 | * @cap: interconnect target module capabilities | |
99 | * @cfg: interconnect target module configuration | |
100 | * @cookie: data used by legacy platform callbacks | |
101 | * @name: name if available | |
102 | * @revision: interconnect target module revision | |
103 | * @enabled: sysc runtime enabled status | |
104 | * @needs_resume: runtime resume needed on resume from suspend | |
105 | * @child_needs_resume: runtime resume needed for child on resume from suspend | |
106 | * @disable_on_idle: status flag used for disabling modules with resets | |
107 | * @idle_work: work structure used to perform delayed idle on a module | |
108 | * @pre_reset_quirk: module specific pre-reset quirk | |
109 | * @post_reset_quirk: module specific post-reset quirk | |
110 | * @reset_done_quirk: module specific reset done quirk | |
111 | * @module_enable_quirk: module specific enable quirk | |
112 | * @module_disable_quirk: module specific disable quirk | |
113 | * @module_unlock_quirk: module specific sysconfig unlock quirk | |
114 | * @module_lock_quirk: module specific sysconfig lock quirk | |
115 | */ | |
116 | struct sysc { | |
117 | struct device *dev; | |
118 | u64 module_pa; | |
119 | u32 module_size; | |
120 | void __iomem *module_va; | |
121 | int offsets[SYSC_MAX_REGS]; | |
122 | struct ti_sysc_module_data *mdata; | |
123 | struct clk **clocks; | |
124 | const char **clock_roles; | |
125 | int nr_clocks; | |
126 | struct reset_control *rsts; | |
127 | const char *legacy_mode; | |
128 | const struct sysc_capabilities *cap; | |
129 | struct sysc_config cfg; | |
130 | struct ti_sysc_cookie cookie; | |
131 | const char *name; | |
132 | u32 revision; | |
133 | unsigned int enabled:1; | |
134 | unsigned int needs_resume:1; | |
135 | unsigned int child_needs_resume:1; | |
136 | struct delayed_work idle_work; | |
137 | void (*pre_reset_quirk)(struct sysc *sysc); | |
138 | void (*post_reset_quirk)(struct sysc *sysc); | |
139 | void (*reset_done_quirk)(struct sysc *sysc); | |
140 | void (*module_enable_quirk)(struct sysc *sysc); | |
141 | void (*module_disable_quirk)(struct sysc *sysc); | |
142 | void (*module_unlock_quirk)(struct sysc *sysc); | |
143 | void (*module_lock_quirk)(struct sysc *sysc); | |
144 | }; | |
145 | ||
146 | static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, | |
147 | bool is_child); | |
148 | ||
149 | static void sysc_write(struct sysc *ddata, int offset, u32 value) | |
150 | { | |
151 | if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { | |
152 | writew_relaxed(value & 0xffff, ddata->module_va + offset); | |
153 | ||
154 | /* Only i2c revision has LO and HI register with stride of 4 */ | |
155 | if (ddata->offsets[SYSC_REVISION] >= 0 && | |
156 | offset == ddata->offsets[SYSC_REVISION]) { | |
157 | u16 hi = value >> 16; | |
158 | ||
159 | writew_relaxed(hi, ddata->module_va + offset + 4); | |
160 | } | |
161 | ||
162 | return; | |
163 | } | |
164 | ||
165 | writel_relaxed(value, ddata->module_va + offset); | |
166 | } | |
167 | ||
168 | static u32 sysc_read(struct sysc *ddata, int offset) | |
169 | { | |
170 | if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { | |
171 | u32 val; | |
172 | ||
173 | val = readw_relaxed(ddata->module_va + offset); | |
174 | ||
175 | /* Only i2c revision has LO and HI register with stride of 4 */ | |
176 | if (ddata->offsets[SYSC_REVISION] >= 0 && | |
177 | offset == ddata->offsets[SYSC_REVISION]) { | |
178 | u16 tmp = readw_relaxed(ddata->module_va + offset + 4); | |
179 | ||
180 | val |= tmp << 16; | |
181 | } | |
182 | ||
183 | return val; | |
184 | } | |
185 | ||
186 | return readl_relaxed(ddata->module_va + offset); | |
187 | } | |
188 | ||
189 | static bool sysc_opt_clks_needed(struct sysc *ddata) | |
190 | { | |
191 | return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED); | |
192 | } | |
193 | ||
194 | static u32 sysc_read_revision(struct sysc *ddata) | |
195 | { | |
196 | int offset = ddata->offsets[SYSC_REVISION]; | |
197 | ||
198 | if (offset < 0) | |
199 | return 0; | |
200 | ||
201 | return sysc_read(ddata, offset); | |
202 | } | |
203 | ||
204 | static u32 sysc_read_sysconfig(struct sysc *ddata) | |
205 | { | |
206 | int offset = ddata->offsets[SYSC_SYSCONFIG]; | |
207 | ||
208 | if (offset < 0) | |
209 | return 0; | |
210 | ||
211 | return sysc_read(ddata, offset); | |
212 | } | |
213 | ||
214 | static u32 sysc_read_sysstatus(struct sysc *ddata) | |
215 | { | |
216 | int offset = ddata->offsets[SYSC_SYSSTATUS]; | |
217 | ||
218 | if (offset < 0) | |
219 | return 0; | |
220 | ||
221 | return sysc_read(ddata, offset); | |
222 | } | |
223 | ||
224 | /* Poll on reset status */ | |
225 | static int sysc_wait_softreset(struct sysc *ddata) | |
226 | { | |
227 | u32 sysc_mask, syss_done, rstval; | |
228 | int syss_offset, error = 0; | |
229 | ||
230 | syss_offset = ddata->offsets[SYSC_SYSSTATUS]; | |
231 | sysc_mask = BIT(ddata->cap->regbits->srst_shift); | |
232 | ||
233 | if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED) | |
234 | syss_done = 0; | |
235 | else | |
236 | syss_done = ddata->cfg.syss_mask; | |
237 | ||
238 | if (syss_offset >= 0) { | |
239 | error = readx_poll_timeout(sysc_read_sysstatus, ddata, rstval, | |
240 | (rstval & ddata->cfg.syss_mask) == | |
241 | syss_done, | |
242 | 100, MAX_MODULE_SOFTRESET_WAIT); | |
243 | ||
244 | } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) { | |
245 | error = readx_poll_timeout(sysc_read_sysconfig, ddata, rstval, | |
246 | !(rstval & sysc_mask), | |
247 | 100, MAX_MODULE_SOFTRESET_WAIT); | |
248 | } | |
249 | ||
250 | return error; | |
251 | } | |
252 | ||
253 | static int sysc_add_named_clock_from_child(struct sysc *ddata, | |
254 | const char *name, | |
255 | const char *optfck_name) | |
256 | { | |
257 | struct device_node *np = ddata->dev->of_node; | |
258 | struct device_node *child; | |
259 | struct clk_lookup *cl; | |
260 | struct clk *clock; | |
261 | const char *n; | |
262 | ||
263 | if (name) | |
264 | n = name; | |
265 | else | |
266 | n = optfck_name; | |
267 | ||
268 | /* Does the clock alias already exist? */ | |
269 | clock = of_clk_get_by_name(np, n); | |
270 | if (!IS_ERR(clock)) { | |
271 | clk_put(clock); | |
272 | ||
273 | return 0; | |
274 | } | |
275 | ||
276 | child = of_get_next_available_child(np, NULL); | |
277 | if (!child) | |
278 | return -ENODEV; | |
279 | ||
280 | clock = devm_get_clk_from_child(ddata->dev, child, name); | |
281 | if (IS_ERR(clock)) | |
282 | return PTR_ERR(clock); | |
283 | ||
284 | /* | |
285 | * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID | |
286 | * limit for clk_get(). If cl ever needs to be freed, it should be done | |
287 | * with clkdev_drop(). | |
288 | */ | |
289 | cl = kcalloc(1, sizeof(*cl), GFP_KERNEL); | |
290 | if (!cl) | |
291 | return -ENOMEM; | |
292 | ||
293 | cl->con_id = n; | |
294 | cl->dev_id = dev_name(ddata->dev); | |
295 | cl->clk = clock; | |
296 | clkdev_add(cl); | |
297 | ||
298 | clk_put(clock); | |
299 | ||
300 | return 0; | |
301 | } | |
302 | ||
303 | static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name) | |
304 | { | |
305 | const char *optfck_name; | |
306 | int error, index; | |
307 | ||
308 | if (ddata->nr_clocks < SYSC_OPTFCK0) | |
309 | index = SYSC_OPTFCK0; | |
310 | else | |
311 | index = ddata->nr_clocks; | |
312 | ||
313 | if (name) | |
314 | optfck_name = name; | |
315 | else | |
316 | optfck_name = clock_names[index]; | |
317 | ||
318 | error = sysc_add_named_clock_from_child(ddata, name, optfck_name); | |
319 | if (error) | |
320 | return error; | |
321 | ||
322 | ddata->clock_roles[index] = optfck_name; | |
323 | ddata->nr_clocks++; | |
324 | ||
325 | return 0; | |
326 | } | |
327 | ||
328 | static int sysc_get_one_clock(struct sysc *ddata, const char *name) | |
329 | { | |
330 | int error, i, index = -ENODEV; | |
331 | ||
332 | if (!strncmp(clock_names[SYSC_FCK], name, 3)) | |
333 | index = SYSC_FCK; | |
334 | else if (!strncmp(clock_names[SYSC_ICK], name, 3)) | |
335 | index = SYSC_ICK; | |
336 | ||
337 | if (index < 0) { | |
338 | for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { | |
339 | if (!ddata->clocks[i]) { | |
340 | index = i; | |
341 | break; | |
342 | } | |
343 | } | |
344 | } | |
345 | ||
346 | if (index < 0) { | |
347 | dev_err(ddata->dev, "clock %s not added\n", name); | |
348 | return index; | |
349 | } | |
350 | ||
351 | ddata->clocks[index] = devm_clk_get(ddata->dev, name); | |
352 | if (IS_ERR(ddata->clocks[index])) { | |
353 | dev_err(ddata->dev, "clock get error for %s: %li\n", | |
354 | name, PTR_ERR(ddata->clocks[index])); | |
355 | ||
356 | return PTR_ERR(ddata->clocks[index]); | |
357 | } | |
358 | ||
359 | error = clk_prepare(ddata->clocks[index]); | |
360 | if (error) { | |
361 | dev_err(ddata->dev, "clock prepare error for %s: %i\n", | |
362 | name, error); | |
363 | ||
364 | return error; | |
365 | } | |
366 | ||
367 | return 0; | |
368 | } | |
369 | ||
370 | static int sysc_get_clocks(struct sysc *ddata) | |
371 | { | |
372 | struct device_node *np = ddata->dev->of_node; | |
373 | struct property *prop; | |
374 | const char *name; | |
375 | int nr_fck = 0, nr_ick = 0, i, error = 0; | |
376 | ||
377 | ddata->clock_roles = devm_kcalloc(ddata->dev, | |
378 | SYSC_MAX_CLOCKS, | |
379 | sizeof(*ddata->clock_roles), | |
380 | GFP_KERNEL); | |
381 | if (!ddata->clock_roles) | |
382 | return -ENOMEM; | |
383 | ||
384 | of_property_for_each_string(np, "clock-names", prop, name) { | |
385 | if (!strncmp(clock_names[SYSC_FCK], name, 3)) | |
386 | nr_fck++; | |
387 | if (!strncmp(clock_names[SYSC_ICK], name, 3)) | |
388 | nr_ick++; | |
389 | ddata->clock_roles[ddata->nr_clocks] = name; | |
390 | ddata->nr_clocks++; | |
391 | } | |
392 | ||
393 | if (ddata->nr_clocks < 1) | |
394 | return 0; | |
395 | ||
396 | if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) { | |
397 | error = sysc_init_ext_opt_clock(ddata, NULL); | |
398 | if (error) | |
399 | return error; | |
400 | } | |
401 | ||
402 | if (ddata->nr_clocks > SYSC_MAX_CLOCKS) { | |
403 | dev_err(ddata->dev, "too many clocks for %pOF\n", np); | |
404 | ||
405 | return -EINVAL; | |
406 | } | |
407 | ||
408 | if (nr_fck > 1 || nr_ick > 1) { | |
409 | dev_err(ddata->dev, "max one fck and ick for %pOF\n", np); | |
410 | ||
411 | return -EINVAL; | |
412 | } | |
413 | ||
414 | /* Always add a slot for main clocks fck and ick even if unused */ | |
415 | if (!nr_fck) | |
416 | ddata->nr_clocks++; | |
417 | if (!nr_ick) | |
418 | ddata->nr_clocks++; | |
419 | ||
420 | ddata->clocks = devm_kcalloc(ddata->dev, | |
421 | ddata->nr_clocks, sizeof(*ddata->clocks), | |
422 | GFP_KERNEL); | |
423 | if (!ddata->clocks) | |
424 | return -ENOMEM; | |
425 | ||
426 | for (i = 0; i < SYSC_MAX_CLOCKS; i++) { | |
427 | const char *name = ddata->clock_roles[i]; | |
428 | ||
429 | if (!name) | |
430 | continue; | |
431 | ||
432 | error = sysc_get_one_clock(ddata, name); | |
433 | if (error) | |
434 | return error; | |
435 | } | |
436 | ||
437 | return 0; | |
438 | } | |
439 | ||
440 | static int sysc_enable_main_clocks(struct sysc *ddata) | |
441 | { | |
442 | struct clk *clock; | |
443 | int i, error; | |
444 | ||
445 | if (!ddata->clocks) | |
446 | return 0; | |
447 | ||
448 | for (i = 0; i < SYSC_OPTFCK0; i++) { | |
449 | clock = ddata->clocks[i]; | |
450 | ||
451 | /* Main clocks may not have ick */ | |
452 | if (IS_ERR_OR_NULL(clock)) | |
453 | continue; | |
454 | ||
455 | error = clk_enable(clock); | |
456 | if (error) | |
457 | goto err_disable; | |
458 | } | |
459 | ||
460 | return 0; | |
461 | ||
462 | err_disable: | |
463 | for (i--; i >= 0; i--) { | |
464 | clock = ddata->clocks[i]; | |
465 | ||
466 | /* Main clocks may not have ick */ | |
467 | if (IS_ERR_OR_NULL(clock)) | |
468 | continue; | |
469 | ||
470 | clk_disable(clock); | |
471 | } | |
472 | ||
473 | return error; | |
474 | } | |
475 | ||
476 | static void sysc_disable_main_clocks(struct sysc *ddata) | |
477 | { | |
478 | struct clk *clock; | |
479 | int i; | |
480 | ||
481 | if (!ddata->clocks) | |
482 | return; | |
483 | ||
484 | for (i = 0; i < SYSC_OPTFCK0; i++) { | |
485 | clock = ddata->clocks[i]; | |
486 | if (IS_ERR_OR_NULL(clock)) | |
487 | continue; | |
488 | ||
489 | clk_disable(clock); | |
490 | } | |
491 | } | |
492 | ||
493 | static int sysc_enable_opt_clocks(struct sysc *ddata) | |
494 | { | |
495 | struct clk *clock; | |
496 | int i, error; | |
497 | ||
498 | if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1) | |
499 | return 0; | |
500 | ||
501 | for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { | |
502 | clock = ddata->clocks[i]; | |
503 | ||
504 | /* Assume no holes for opt clocks */ | |
505 | if (IS_ERR_OR_NULL(clock)) | |
506 | return 0; | |
507 | ||
508 | error = clk_enable(clock); | |
509 | if (error) | |
510 | goto err_disable; | |
511 | } | |
512 | ||
513 | return 0; | |
514 | ||
515 | err_disable: | |
516 | for (i--; i >= 0; i--) { | |
517 | clock = ddata->clocks[i]; | |
518 | if (IS_ERR_OR_NULL(clock)) | |
519 | continue; | |
520 | ||
521 | clk_disable(clock); | |
522 | } | |
523 | ||
524 | return error; | |
525 | } | |
526 | ||
527 | static void sysc_disable_opt_clocks(struct sysc *ddata) | |
528 | { | |
529 | struct clk *clock; | |
530 | int i; | |
531 | ||
532 | if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1) | |
533 | return; | |
534 | ||
535 | for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { | |
536 | clock = ddata->clocks[i]; | |
537 | ||
538 | /* Assume no holes for opt clocks */ | |
539 | if (IS_ERR_OR_NULL(clock)) | |
540 | return; | |
541 | ||
542 | clk_disable(clock); | |
543 | } | |
544 | } | |
545 | ||
546 | static void sysc_clkdm_deny_idle(struct sysc *ddata) | |
547 | { | |
548 | struct ti_sysc_platform_data *pdata; | |
549 | ||
550 | if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO)) | |
551 | return; | |
552 | ||
553 | pdata = dev_get_platdata(ddata->dev); | |
554 | if (pdata && pdata->clkdm_deny_idle) | |
555 | pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie); | |
556 | } | |
557 | ||
558 | static void sysc_clkdm_allow_idle(struct sysc *ddata) | |
559 | { | |
560 | struct ti_sysc_platform_data *pdata; | |
561 | ||
562 | if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO)) | |
563 | return; | |
564 | ||
565 | pdata = dev_get_platdata(ddata->dev); | |
566 | if (pdata && pdata->clkdm_allow_idle) | |
567 | pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie); | |
568 | } | |
569 | ||
570 | /** | |
571 | * sysc_init_resets - init rstctrl reset line if configured | |
572 | * @ddata: device driver data | |
573 | * | |
574 | * See sysc_rstctrl_reset_deassert(). | |
575 | */ | |
576 | static int sysc_init_resets(struct sysc *ddata) | |
577 | { | |
578 | ddata->rsts = | |
579 | devm_reset_control_get_optional_shared(ddata->dev, "rstctrl"); | |
580 | ||
581 | return PTR_ERR_OR_ZERO(ddata->rsts); | |
582 | } | |
583 | ||
584 | /** | |
585 | * sysc_parse_and_check_child_range - parses module IO region from ranges | |
586 | * @ddata: device driver data | |
587 | * | |
588 | * In general we only need rev, syss, and sysc registers and not the whole | |
589 | * module range. But we do want the offsets for these registers from the | |
590 | * module base. This allows us to check them against the legacy hwmod | |
591 | * platform data. Let's also check the ranges are configured properly. | |
592 | */ | |
593 | static int sysc_parse_and_check_child_range(struct sysc *ddata) | |
594 | { | |
595 | struct device_node *np = ddata->dev->of_node; | |
596 | const __be32 *ranges; | |
597 | u32 nr_addr, nr_size; | |
598 | int len, error; | |
599 | ||
600 | ranges = of_get_property(np, "ranges", &len); | |
601 | if (!ranges) { | |
602 | dev_err(ddata->dev, "missing ranges for %pOF\n", np); | |
603 | ||
604 | return -ENOENT; | |
605 | } | |
606 | ||
607 | len /= sizeof(*ranges); | |
608 | ||
609 | if (len < 3) { | |
610 | dev_err(ddata->dev, "incomplete ranges for %pOF\n", np); | |
611 | ||
612 | return -EINVAL; | |
613 | } | |
614 | ||
615 | error = of_property_read_u32(np, "#address-cells", &nr_addr); | |
616 | if (error) | |
617 | return -ENOENT; | |
618 | ||
619 | error = of_property_read_u32(np, "#size-cells", &nr_size); | |
620 | if (error) | |
621 | return -ENOENT; | |
622 | ||
623 | if (nr_addr != 1 || nr_size != 1) { | |
624 | dev_err(ddata->dev, "invalid ranges for %pOF\n", np); | |
625 | ||
626 | return -EINVAL; | |
627 | } | |
628 | ||
629 | ranges++; | |
630 | ddata->module_pa = of_translate_address(np, ranges++); | |
631 | ddata->module_size = be32_to_cpup(ranges); | |
632 | ||
633 | return 0; | |
634 | } | |
635 | ||
636 | static struct device_node *stdout_path; | |
637 | ||
638 | static void sysc_init_stdout_path(struct sysc *ddata) | |
639 | { | |
640 | struct device_node *np = NULL; | |
641 | const char *uart; | |
642 | ||
643 | if (IS_ERR(stdout_path)) | |
644 | return; | |
645 | ||
646 | if (stdout_path) | |
647 | return; | |
648 | ||
649 | np = of_find_node_by_path("/chosen"); | |
650 | if (!np) | |
651 | goto err; | |
652 | ||
653 | uart = of_get_property(np, "stdout-path", NULL); | |
654 | if (!uart) | |
655 | goto err; | |
656 | ||
657 | np = of_find_node_by_path(uart); | |
658 | if (!np) | |
659 | goto err; | |
660 | ||
661 | stdout_path = np; | |
662 | ||
663 | return; | |
664 | ||
665 | err: | |
666 | stdout_path = ERR_PTR(-ENODEV); | |
667 | } | |
668 | ||
669 | static void sysc_check_quirk_stdout(struct sysc *ddata, | |
670 | struct device_node *np) | |
671 | { | |
672 | sysc_init_stdout_path(ddata); | |
673 | if (np != stdout_path) | |
674 | return; | |
675 | ||
676 | ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT | | |
677 | SYSC_QUIRK_NO_RESET_ON_INIT; | |
678 | } | |
679 | ||
680 | /** | |
681 | * sysc_check_one_child - check child configuration | |
682 | * @ddata: device driver data | |
683 | * @np: child device node | |
684 | * | |
685 | * Let's avoid messy situations where we have new interconnect target | |
686 | * node but children have "ti,hwmods". These belong to the interconnect | |
687 | * target node and are managed by this driver. | |
688 | */ | |
689 | static void sysc_check_one_child(struct sysc *ddata, | |
690 | struct device_node *np) | |
691 | { | |
692 | const char *name; | |
693 | ||
694 | name = of_get_property(np, "ti,hwmods", NULL); | |
695 | if (name && !of_device_is_compatible(np, "ti,sysc")) | |
696 | dev_warn(ddata->dev, "really a child ti,hwmods property?"); | |
697 | ||
698 | sysc_check_quirk_stdout(ddata, np); | |
699 | sysc_parse_dts_quirks(ddata, np, true); | |
700 | } | |
701 | ||
702 | static void sysc_check_children(struct sysc *ddata) | |
703 | { | |
704 | struct device_node *child; | |
705 | ||
706 | for_each_child_of_node(ddata->dev->of_node, child) | |
707 | sysc_check_one_child(ddata, child); | |
708 | } | |
709 | ||
710 | /* | |
711 | * So far only I2C uses 16-bit read access with clockactivity with revision | |
712 | * in two registers with stride of 4. We can detect this based on the rev | |
713 | * register size to configure things far enough to be able to properly read | |
714 | * the revision register. | |
715 | */ | |
716 | static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res) | |
717 | { | |
718 | if (resource_size(res) == 8) | |
719 | ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT; | |
720 | } | |
721 | ||
722 | /** | |
723 | * sysc_parse_one - parses the interconnect target module registers | |
724 | * @ddata: device driver data | |
725 | * @reg: register to parse | |
726 | */ | |
727 | static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg) | |
728 | { | |
729 | struct resource *res; | |
730 | const char *name; | |
731 | ||
732 | switch (reg) { | |
733 | case SYSC_REVISION: | |
734 | case SYSC_SYSCONFIG: | |
735 | case SYSC_SYSSTATUS: | |
736 | name = reg_names[reg]; | |
737 | break; | |
738 | default: | |
739 | return -EINVAL; | |
740 | } | |
741 | ||
742 | res = platform_get_resource_byname(to_platform_device(ddata->dev), | |
743 | IORESOURCE_MEM, name); | |
744 | if (!res) { | |
745 | ddata->offsets[reg] = -ENODEV; | |
746 | ||
747 | return 0; | |
748 | } | |
749 | ||
750 | ddata->offsets[reg] = res->start - ddata->module_pa; | |
751 | if (reg == SYSC_REVISION) | |
752 | sysc_check_quirk_16bit(ddata, res); | |
753 | ||
754 | return 0; | |
755 | } | |
756 | ||
757 | static int sysc_parse_registers(struct sysc *ddata) | |
758 | { | |
759 | int i, error; | |
760 | ||
761 | for (i = 0; i < SYSC_MAX_REGS; i++) { | |
762 | error = sysc_parse_one(ddata, i); | |
763 | if (error) | |
764 | return error; | |
765 | } | |
766 | ||
767 | return 0; | |
768 | } | |
769 | ||
770 | /** | |
771 | * sysc_check_registers - check for misconfigured register overlaps | |
772 | * @ddata: device driver data | |
773 | */ | |
774 | static int sysc_check_registers(struct sysc *ddata) | |
775 | { | |
776 | int i, j, nr_regs = 0, nr_matches = 0; | |
777 | ||
778 | for (i = 0; i < SYSC_MAX_REGS; i++) { | |
779 | if (ddata->offsets[i] < 0) | |
780 | continue; | |
781 | ||
782 | if (ddata->offsets[i] > (ddata->module_size - 4)) { | |
783 | dev_err(ddata->dev, "register outside module range"); | |
784 | ||
785 | return -EINVAL; | |
786 | } | |
787 | ||
788 | for (j = 0; j < SYSC_MAX_REGS; j++) { | |
789 | if (ddata->offsets[j] < 0) | |
790 | continue; | |
791 | ||
792 | if (ddata->offsets[i] == ddata->offsets[j]) | |
793 | nr_matches++; | |
794 | } | |
795 | nr_regs++; | |
796 | } | |
797 | ||
798 | if (nr_matches > nr_regs) { | |
799 | dev_err(ddata->dev, "overlapping registers: (%i/%i)", | |
800 | nr_regs, nr_matches); | |
801 | ||
802 | return -EINVAL; | |
803 | } | |
804 | ||
805 | return 0; | |
806 | } | |
807 | ||
808 | /** | |
809 | * syc_ioremap - ioremap register space for the interconnect target module | |
810 | * @ddata: device driver data | |
811 | * | |
812 | * Note that the interconnect target module registers can be anywhere | |
813 | * within the interconnect target module range. For example, SGX has | |
814 | * them at offset 0x1fc00 in the 32MB module address space. And cpsw | |
815 | * has them at offset 0x1200 in the CPSW_WR child. Usually the | |
816 | * the interconnect target module registers are at the beginning of | |
817 | * the module range though. | |
818 | */ | |
819 | static int sysc_ioremap(struct sysc *ddata) | |
820 | { | |
821 | int size; | |
822 | ||
823 | if (ddata->offsets[SYSC_REVISION] < 0 && | |
824 | ddata->offsets[SYSC_SYSCONFIG] < 0 && | |
825 | ddata->offsets[SYSC_SYSSTATUS] < 0) { | |
826 | size = ddata->module_size; | |
827 | } else { | |
828 | size = max3(ddata->offsets[SYSC_REVISION], | |
829 | ddata->offsets[SYSC_SYSCONFIG], | |
830 | ddata->offsets[SYSC_SYSSTATUS]); | |
831 | ||
832 | if (size < SZ_1K) | |
833 | size = SZ_1K; | |
834 | ||
835 | if ((size + sizeof(u32)) > ddata->module_size) | |
836 | size = ddata->module_size; | |
837 | } | |
838 | ||
839 | ddata->module_va = devm_ioremap(ddata->dev, | |
840 | ddata->module_pa, | |
841 | size + sizeof(u32)); | |
842 | if (!ddata->module_va) | |
843 | return -EIO; | |
844 | ||
845 | return 0; | |
846 | } | |
847 | ||
848 | /** | |
849 | * sysc_map_and_check_registers - ioremap and check device registers | |
850 | * @ddata: device driver data | |
851 | */ | |
852 | static int sysc_map_and_check_registers(struct sysc *ddata) | |
853 | { | |
854 | int error; | |
855 | ||
856 | error = sysc_parse_and_check_child_range(ddata); | |
857 | if (error) | |
858 | return error; | |
859 | ||
860 | sysc_check_children(ddata); | |
861 | ||
862 | error = sysc_parse_registers(ddata); | |
863 | if (error) | |
864 | return error; | |
865 | ||
866 | error = sysc_ioremap(ddata); | |
867 | if (error) | |
868 | return error; | |
869 | ||
870 | error = sysc_check_registers(ddata); | |
871 | if (error) | |
872 | return error; | |
873 | ||
874 | return 0; | |
875 | } | |
876 | ||
877 | /** | |
878 | * sysc_show_rev - read and show interconnect target module revision | |
879 | * @bufp: buffer to print the information to | |
880 | * @ddata: device driver data | |
881 | */ | |
882 | static int sysc_show_rev(char *bufp, struct sysc *ddata) | |
883 | { | |
884 | int len; | |
885 | ||
886 | if (ddata->offsets[SYSC_REVISION] < 0) | |
887 | return sprintf(bufp, ":NA"); | |
888 | ||
889 | len = sprintf(bufp, ":%08x", ddata->revision); | |
890 | ||
891 | return len; | |
892 | } | |
893 | ||
894 | static int sysc_show_reg(struct sysc *ddata, | |
895 | char *bufp, enum sysc_registers reg) | |
896 | { | |
897 | if (ddata->offsets[reg] < 0) | |
898 | return sprintf(bufp, ":NA"); | |
899 | ||
900 | return sprintf(bufp, ":%x", ddata->offsets[reg]); | |
901 | } | |
902 | ||
903 | static int sysc_show_name(char *bufp, struct sysc *ddata) | |
904 | { | |
905 | if (!ddata->name) | |
906 | return 0; | |
907 | ||
908 | return sprintf(bufp, ":%s", ddata->name); | |
909 | } | |
910 | ||
911 | /** | |
912 | * sysc_show_registers - show information about interconnect target module | |
913 | * @ddata: device driver data | |
914 | */ | |
915 | static void sysc_show_registers(struct sysc *ddata) | |
916 | { | |
917 | char buf[128]; | |
918 | char *bufp = buf; | |
919 | int i; | |
920 | ||
921 | for (i = 0; i < SYSC_MAX_REGS; i++) | |
922 | bufp += sysc_show_reg(ddata, bufp, i); | |
923 | ||
924 | bufp += sysc_show_rev(bufp, ddata); | |
925 | bufp += sysc_show_name(bufp, ddata); | |
926 | ||
927 | dev_dbg(ddata->dev, "%llx:%x%s\n", | |
928 | ddata->module_pa, ddata->module_size, | |
929 | buf); | |
930 | } | |
931 | ||
932 | /** | |
933 | * sysc_write_sysconfig - handle sysconfig quirks for register write | |
934 | * @ddata: device driver data | |
935 | * @value: register value | |
936 | */ | |
937 | static void sysc_write_sysconfig(struct sysc *ddata, u32 value) | |
938 | { | |
939 | if (ddata->module_unlock_quirk) | |
940 | ddata->module_unlock_quirk(ddata); | |
941 | ||
942 | sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value); | |
943 | ||
944 | if (ddata->module_lock_quirk) | |
945 | ddata->module_lock_quirk(ddata); | |
946 | } | |
947 | ||
948 | #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1) | |
949 | #define SYSC_CLOCACT_ICK 2 | |
950 | ||
951 | /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ | |
952 | static int sysc_enable_module(struct device *dev) | |
953 | { | |
954 | struct sysc *ddata; | |
955 | const struct sysc_regbits *regbits; | |
956 | u32 reg, idlemodes, best_mode; | |
957 | int error; | |
958 | ||
959 | ddata = dev_get_drvdata(dev); | |
960 | ||
961 | /* | |
962 | * Some modules like DSS reset automatically on idle. Enable optional | |
963 | * reset clocks and wait for OCP softreset to complete. | |
964 | */ | |
965 | if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) { | |
966 | error = sysc_enable_opt_clocks(ddata); | |
967 | if (error) { | |
968 | dev_err(ddata->dev, | |
969 | "Optional clocks failed for enable: %i\n", | |
970 | error); | |
971 | return error; | |
972 | } | |
973 | } | |
974 | error = sysc_wait_softreset(ddata); | |
975 | if (error) | |
976 | dev_warn(ddata->dev, "OCP softreset timed out\n"); | |
977 | if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) | |
978 | sysc_disable_opt_clocks(ddata); | |
979 | ||
980 | /* | |
981 | * Some subsystem private interconnects, like DSS top level module, | |
982 | * need only the automatic OCP softreset handling with no sysconfig | |
983 | * register bits to configure. | |
984 | */ | |
985 | if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) | |
986 | return 0; | |
987 | ||
988 | regbits = ddata->cap->regbits; | |
989 | reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); | |
990 | ||
991 | /* | |
992 | * Set CLOCKACTIVITY, we only use it for ick. And we only configure it | |
993 | * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware | |
994 | * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag. | |
995 | */ | |
996 | if (regbits->clkact_shift >= 0 && | |
997 | (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT)) | |
998 | reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift; | |
999 | ||
1000 | /* Set SIDLE mode */ | |
1001 | idlemodes = ddata->cfg.sidlemodes; | |
1002 | if (!idlemodes || regbits->sidle_shift < 0) | |
1003 | goto set_midle; | |
1004 | ||
1005 | if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE | | |
1006 | SYSC_QUIRK_SWSUP_SIDLE_ACT)) { | |
1007 | best_mode = SYSC_IDLE_NO; | |
1008 | } else { | |
1009 | best_mode = fls(ddata->cfg.sidlemodes) - 1; | |
1010 | if (best_mode > SYSC_IDLE_MASK) { | |
1011 | dev_err(dev, "%s: invalid sidlemode\n", __func__); | |
1012 | return -EINVAL; | |
1013 | } | |
1014 | ||
1015 | /* Set WAKEUP */ | |
1016 | if (regbits->enwkup_shift >= 0 && | |
1017 | ddata->cfg.sysc_val & BIT(regbits->enwkup_shift)) | |
1018 | reg |= BIT(regbits->enwkup_shift); | |
1019 | } | |
1020 | ||
1021 | reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); | |
1022 | reg |= best_mode << regbits->sidle_shift; | |
1023 | sysc_write_sysconfig(ddata, reg); | |
1024 | ||
1025 | set_midle: | |
1026 | /* Set MIDLE mode */ | |
1027 | idlemodes = ddata->cfg.midlemodes; | |
1028 | if (!idlemodes || regbits->midle_shift < 0) | |
1029 | goto set_autoidle; | |
1030 | ||
1031 | best_mode = fls(ddata->cfg.midlemodes) - 1; | |
1032 | if (best_mode > SYSC_IDLE_MASK) { | |
1033 | dev_err(dev, "%s: invalid midlemode\n", __func__); | |
1034 | return -EINVAL; | |
1035 | } | |
1036 | ||
1037 | if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY) | |
1038 | best_mode = SYSC_IDLE_NO; | |
1039 | ||
1040 | reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); | |
1041 | reg |= best_mode << regbits->midle_shift; | |
1042 | sysc_write_sysconfig(ddata, reg); | |
1043 | ||
1044 | set_autoidle: | |
1045 | /* Autoidle bit must enabled separately if available */ | |
1046 | if (regbits->autoidle_shift >= 0 && | |
1047 | ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) { | |
1048 | reg |= 1 << regbits->autoidle_shift; | |
1049 | sysc_write_sysconfig(ddata, reg); | |
1050 | } | |
1051 | ||
1052 | /* Flush posted write */ | |
1053 | sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); | |
1054 | ||
1055 | if (ddata->module_enable_quirk) | |
1056 | ddata->module_enable_quirk(ddata); | |
1057 | ||
1058 | return 0; | |
1059 | } | |
1060 | ||
1061 | static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode) | |
1062 | { | |
1063 | if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP)) | |
1064 | *best_mode = SYSC_IDLE_SMART_WKUP; | |
1065 | else if (idlemodes & BIT(SYSC_IDLE_SMART)) | |
1066 | *best_mode = SYSC_IDLE_SMART; | |
1067 | else if (idlemodes & BIT(SYSC_IDLE_FORCE)) | |
1068 | *best_mode = SYSC_IDLE_FORCE; | |
1069 | else | |
1070 | return -EINVAL; | |
1071 | ||
1072 | return 0; | |
1073 | } | |
1074 | ||
1075 | /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ | |
1076 | static int sysc_disable_module(struct device *dev) | |
1077 | { | |
1078 | struct sysc *ddata; | |
1079 | const struct sysc_regbits *regbits; | |
1080 | u32 reg, idlemodes, best_mode; | |
1081 | int ret; | |
1082 | ||
1083 | ddata = dev_get_drvdata(dev); | |
1084 | if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) | |
1085 | return 0; | |
1086 | ||
1087 | if (ddata->module_disable_quirk) | |
1088 | ddata->module_disable_quirk(ddata); | |
1089 | ||
1090 | regbits = ddata->cap->regbits; | |
1091 | reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); | |
1092 | ||
1093 | /* Set MIDLE mode */ | |
1094 | idlemodes = ddata->cfg.midlemodes; | |
1095 | if (!idlemodes || regbits->midle_shift < 0) | |
1096 | goto set_sidle; | |
1097 | ||
1098 | ret = sysc_best_idle_mode(idlemodes, &best_mode); | |
1099 | if (ret) { | |
1100 | dev_err(dev, "%s: invalid midlemode\n", __func__); | |
1101 | return ret; | |
1102 | } | |
1103 | ||
1104 | if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) || | |
1105 | ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY)) | |
1106 | best_mode = SYSC_IDLE_FORCE; | |
1107 | ||
1108 | reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); | |
1109 | reg |= best_mode << regbits->midle_shift; | |
1110 | sysc_write_sysconfig(ddata, reg); | |
1111 | ||
1112 | set_sidle: | |
1113 | /* Set SIDLE mode */ | |
1114 | idlemodes = ddata->cfg.sidlemodes; | |
1115 | if (!idlemodes || regbits->sidle_shift < 0) | |
1116 | return 0; | |
1117 | ||
1118 | if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) { | |
1119 | best_mode = SYSC_IDLE_FORCE; | |
1120 | } else { | |
1121 | ret = sysc_best_idle_mode(idlemodes, &best_mode); | |
1122 | if (ret) { | |
1123 | dev_err(dev, "%s: invalid sidlemode\n", __func__); | |
1124 | return ret; | |
1125 | } | |
1126 | } | |
1127 | ||
1128 | reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); | |
1129 | reg |= best_mode << regbits->sidle_shift; | |
1130 | if (regbits->autoidle_shift >= 0 && | |
1131 | ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) | |
1132 | reg |= 1 << regbits->autoidle_shift; | |
1133 | sysc_write_sysconfig(ddata, reg); | |
1134 | ||
1135 | /* Flush posted write */ | |
1136 | sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); | |
1137 | ||
1138 | return 0; | |
1139 | } | |
1140 | ||
1141 | static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev, | |
1142 | struct sysc *ddata) | |
1143 | { | |
1144 | struct ti_sysc_platform_data *pdata; | |
1145 | int error; | |
1146 | ||
1147 | pdata = dev_get_platdata(ddata->dev); | |
1148 | if (!pdata) | |
1149 | return 0; | |
1150 | ||
1151 | if (!pdata->idle_module) | |
1152 | return -ENODEV; | |
1153 | ||
1154 | error = pdata->idle_module(dev, &ddata->cookie); | |
1155 | if (error) | |
1156 | dev_err(dev, "%s: could not idle: %i\n", | |
1157 | __func__, error); | |
1158 | ||
1159 | reset_control_assert(ddata->rsts); | |
1160 | ||
1161 | return 0; | |
1162 | } | |
1163 | ||
1164 | static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev, | |
1165 | struct sysc *ddata) | |
1166 | { | |
1167 | struct ti_sysc_platform_data *pdata; | |
1168 | int error; | |
1169 | ||
1170 | pdata = dev_get_platdata(ddata->dev); | |
1171 | if (!pdata) | |
1172 | return 0; | |
1173 | ||
1174 | if (!pdata->enable_module) | |
1175 | return -ENODEV; | |
1176 | ||
1177 | error = pdata->enable_module(dev, &ddata->cookie); | |
1178 | if (error) | |
1179 | dev_err(dev, "%s: could not enable: %i\n", | |
1180 | __func__, error); | |
1181 | ||
1182 | reset_control_deassert(ddata->rsts); | |
1183 | ||
1184 | return 0; | |
1185 | } | |
1186 | ||
1187 | static int __maybe_unused sysc_runtime_suspend(struct device *dev) | |
1188 | { | |
1189 | struct sysc *ddata; | |
1190 | int error = 0; | |
1191 | ||
1192 | ddata = dev_get_drvdata(dev); | |
1193 | ||
1194 | if (!ddata->enabled) | |
1195 | return 0; | |
1196 | ||
1197 | sysc_clkdm_deny_idle(ddata); | |
1198 | ||
1199 | if (ddata->legacy_mode) { | |
1200 | error = sysc_runtime_suspend_legacy(dev, ddata); | |
1201 | if (error) | |
1202 | goto err_allow_idle; | |
1203 | } else { | |
1204 | error = sysc_disable_module(dev); | |
1205 | if (error) | |
1206 | goto err_allow_idle; | |
1207 | } | |
1208 | ||
1209 | sysc_disable_main_clocks(ddata); | |
1210 | ||
1211 | if (sysc_opt_clks_needed(ddata)) | |
1212 | sysc_disable_opt_clocks(ddata); | |
1213 | ||
1214 | ddata->enabled = false; | |
1215 | ||
1216 | err_allow_idle: | |
1217 | reset_control_assert(ddata->rsts); | |
1218 | ||
1219 | sysc_clkdm_allow_idle(ddata); | |
1220 | ||
1221 | return error; | |
1222 | } | |
1223 | ||
1224 | static int __maybe_unused sysc_runtime_resume(struct device *dev) | |
1225 | { | |
1226 | struct sysc *ddata; | |
1227 | int error = 0; | |
1228 | ||
1229 | ddata = dev_get_drvdata(dev); | |
1230 | ||
1231 | if (ddata->enabled) | |
1232 | return 0; | |
1233 | ||
1234 | ||
1235 | sysc_clkdm_deny_idle(ddata); | |
1236 | ||
1237 | if (sysc_opt_clks_needed(ddata)) { | |
1238 | error = sysc_enable_opt_clocks(ddata); | |
1239 | if (error) | |
1240 | goto err_allow_idle; | |
1241 | } | |
1242 | ||
1243 | error = sysc_enable_main_clocks(ddata); | |
1244 | if (error) | |
1245 | goto err_opt_clocks; | |
1246 | ||
1247 | reset_control_deassert(ddata->rsts); | |
1248 | ||
1249 | if (ddata->legacy_mode) { | |
1250 | error = sysc_runtime_resume_legacy(dev, ddata); | |
1251 | if (error) | |
1252 | goto err_main_clocks; | |
1253 | } else { | |
1254 | error = sysc_enable_module(dev); | |
1255 | if (error) | |
1256 | goto err_main_clocks; | |
1257 | } | |
1258 | ||
1259 | ddata->enabled = true; | |
1260 | ||
1261 | sysc_clkdm_allow_idle(ddata); | |
1262 | ||
1263 | return 0; | |
1264 | ||
1265 | err_main_clocks: | |
1266 | sysc_disable_main_clocks(ddata); | |
1267 | err_opt_clocks: | |
1268 | if (sysc_opt_clks_needed(ddata)) | |
1269 | sysc_disable_opt_clocks(ddata); | |
1270 | err_allow_idle: | |
1271 | sysc_clkdm_allow_idle(ddata); | |
1272 | ||
1273 | return error; | |
1274 | } | |
1275 | ||
1276 | static int __maybe_unused sysc_noirq_suspend(struct device *dev) | |
1277 | { | |
1278 | struct sysc *ddata; | |
1279 | ||
1280 | ddata = dev_get_drvdata(dev); | |
1281 | ||
1282 | if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) | |
1283 | return 0; | |
1284 | ||
1285 | return pm_runtime_force_suspend(dev); | |
1286 | } | |
1287 | ||
1288 | static int __maybe_unused sysc_noirq_resume(struct device *dev) | |
1289 | { | |
1290 | struct sysc *ddata; | |
1291 | ||
1292 | ddata = dev_get_drvdata(dev); | |
1293 | ||
1294 | if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) | |
1295 | return 0; | |
1296 | ||
1297 | return pm_runtime_force_resume(dev); | |
1298 | } | |
1299 | ||
1300 | static const struct dev_pm_ops sysc_pm_ops = { | |
1301 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume) | |
1302 | SET_RUNTIME_PM_OPS(sysc_runtime_suspend, | |
1303 | sysc_runtime_resume, | |
1304 | NULL) | |
1305 | }; | |
1306 | ||
1307 | /* Module revision register based quirks */ | |
1308 | struct sysc_revision_quirk { | |
1309 | const char *name; | |
1310 | u32 base; | |
1311 | int rev_offset; | |
1312 | int sysc_offset; | |
1313 | int syss_offset; | |
1314 | u32 revision; | |
1315 | u32 revision_mask; | |
1316 | u32 quirks; | |
1317 | }; | |
1318 | ||
1319 | #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \ | |
1320 | optrev_val, optrevmask, optquirkmask) \ | |
1321 | { \ | |
1322 | .name = (optname), \ | |
1323 | .base = (optbase), \ | |
1324 | .rev_offset = (optrev), \ | |
1325 | .sysc_offset = (optsysc), \ | |
1326 | .syss_offset = (optsyss), \ | |
1327 | .revision = (optrev_val), \ | |
1328 | .revision_mask = (optrevmask), \ | |
1329 | .quirks = (optquirkmask), \ | |
1330 | } | |
1331 | ||
1332 | static const struct sysc_revision_quirk sysc_revision_quirks[] = { | |
1333 | /* These drivers need to be fixed to not use pm_runtime_irq_safe() */ | |
1334 | SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff, | |
1335 | SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET), | |
1336 | SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, | |
1337 | SYSC_QUIRK_LEGACY_IDLE), | |
1338 | SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff, | |
1339 | SYSC_QUIRK_LEGACY_IDLE), | |
1340 | SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff, | |
1341 | SYSC_QUIRK_LEGACY_IDLE), | |
1342 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff, | |
1343 | SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), | |
1344 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff, | |
1345 | SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), | |
1346 | /* Uarts on omap4 and later */ | |
1347 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff, | |
1348 | SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE), | |
1349 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff, | |
1350 | SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE), | |
1351 | ||
1352 | /* Quirks that need to be set based on the module address */ | |
1353 | SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff, | |
1354 | SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT | | |
1355 | SYSC_QUIRK_SWSUP_SIDLE), | |
1356 | ||
1357 | /* Quirks that need to be set based on detected module */ | |
1358 | SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff, | |
1359 | SYSC_MODULE_QUIRK_AESS), | |
1360 | SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, | |
1361 | SYSC_QUIRK_CLKDM_NOAUTO), | |
1362 | SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, | |
1363 | SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), | |
1364 | SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff, | |
1365 | SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), | |
1366 | SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff, | |
1367 | SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), | |
1368 | SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, | |
1369 | SYSC_QUIRK_CLKDM_NOAUTO), | |
1370 | SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, | |
1371 | SYSC_QUIRK_CLKDM_NOAUTO), | |
1372 | SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff, | |
1373 | SYSC_QUIRK_OPT_CLKS_NEEDED), | |
1374 | SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, | |
1375 | SYSC_MODULE_QUIRK_HDQ1W), | |
1376 | SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff, | |
1377 | SYSC_MODULE_QUIRK_HDQ1W), | |
1378 | SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff, | |
1379 | SYSC_MODULE_QUIRK_I2C), | |
1380 | SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff, | |
1381 | SYSC_MODULE_QUIRK_I2C), | |
1382 | SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff, | |
1383 | SYSC_MODULE_QUIRK_I2C), | |
1384 | SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, | |
1385 | SYSC_MODULE_QUIRK_I2C), | |
1386 | SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0), | |
1387 | SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, | |
1388 | SYSC_MODULE_QUIRK_SGX), | |
1389 | SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff, | |
1390 | SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), | |
1391 | SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0, | |
1392 | SYSC_MODULE_QUIRK_RTC_UNLOCK), | |
1393 | SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff, | |
1394 | SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), | |
1395 | SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff, | |
1396 | SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), | |
1397 | SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050, | |
1398 | 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), | |
1399 | SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff, | |
1400 | SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), | |
1401 | SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, | |
1402 | SYSC_MODULE_QUIRK_WDT), | |
1403 | /* PRUSS on am3, am4 and am5 */ | |
1404 | SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000, | |
1405 | SYSC_MODULE_QUIRK_PRUSS), | |
1406 | /* Watchdog on am3 and am4 */ | |
1407 | SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, | |
1408 | SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE), | |
1409 | ||
1410 | #ifdef DEBUG | |
1411 | SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0), | |
1412 | SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0), | |
1413 | SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0), | |
1414 | SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0), | |
1415 | SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902, | |
1416 | 0xffff00f0, 0), | |
1417 | SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0), | |
1418 | SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0), | |
1419 | SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), | |
1420 | SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), | |
1421 | SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0), | |
1422 | SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0), | |
1423 | SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), | |
1424 | SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), | |
1425 | SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), | |
1426 | SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), | |
1427 | SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0), | |
1428 | SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), | |
1429 | SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), | |
1430 | SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0), | |
1431 | SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0), | |
1432 | SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0), | |
1433 | SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0), | |
1434 | SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0), | |
1435 | SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0), | |
1436 | SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff, 0), | |
1437 | SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0), | |
1438 | SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0), | |
1439 | SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0), | |
1440 | SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0), | |
1441 | SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0), | |
1442 | SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0), | |
1443 | SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0), | |
1444 | SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0), | |
1445 | SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0), | |
1446 | SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0), | |
1447 | SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0), | |
1448 | SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0), | |
1449 | SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0), | |
1450 | SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), | |
1451 | SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), | |
1452 | SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0), | |
1453 | SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0), | |
1454 | SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0), | |
1455 | SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0), | |
1456 | SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0), | |
1457 | SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0), | |
1458 | SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0), | |
1459 | SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0), | |
1460 | SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0), | |
1461 | SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0), | |
1462 | SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0), | |
1463 | SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0), | |
1464 | SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0), | |
1465 | SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0), | |
1466 | /* Some timers on omap4 and later */ | |
1467 | SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0), | |
1468 | SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0), | |
1469 | SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0), | |
1470 | SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0), | |
1471 | SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0), | |
1472 | SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0), | |
1473 | SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0), | |
1474 | SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0), | |
1475 | SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0), | |
1476 | SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff, 0), | |
1477 | SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0), | |
1478 | SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0), | |
1479 | #endif | |
1480 | }; | |
1481 | ||
1482 | /* | |
1483 | * Early quirks based on module base and register offsets only that are | |
1484 | * needed before the module revision can be read | |
1485 | */ | |
1486 | static void sysc_init_early_quirks(struct sysc *ddata) | |
1487 | { | |
1488 | const struct sysc_revision_quirk *q; | |
1489 | int i; | |
1490 | ||
1491 | for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { | |
1492 | q = &sysc_revision_quirks[i]; | |
1493 | ||
1494 | if (!q->base) | |
1495 | continue; | |
1496 | ||
1497 | if (q->base != ddata->module_pa) | |
1498 | continue; | |
1499 | ||
1500 | if (q->rev_offset != ddata->offsets[SYSC_REVISION]) | |
1501 | continue; | |
1502 | ||
1503 | if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) | |
1504 | continue; | |
1505 | ||
1506 | if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) | |
1507 | continue; | |
1508 | ||
1509 | ddata->name = q->name; | |
1510 | ddata->cfg.quirks |= q->quirks; | |
1511 | } | |
1512 | } | |
1513 | ||
1514 | /* Quirks that also consider the revision register value */ | |
1515 | static void sysc_init_revision_quirks(struct sysc *ddata) | |
1516 | { | |
1517 | const struct sysc_revision_quirk *q; | |
1518 | int i; | |
1519 | ||
1520 | for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { | |
1521 | q = &sysc_revision_quirks[i]; | |
1522 | ||
1523 | if (q->base && q->base != ddata->module_pa) | |
1524 | continue; | |
1525 | ||
1526 | if (q->rev_offset != ddata->offsets[SYSC_REVISION]) | |
1527 | continue; | |
1528 | ||
1529 | if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) | |
1530 | continue; | |
1531 | ||
1532 | if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) | |
1533 | continue; | |
1534 | ||
1535 | if (q->revision == ddata->revision || | |
1536 | (q->revision & q->revision_mask) == | |
1537 | (ddata->revision & q->revision_mask)) { | |
1538 | ddata->name = q->name; | |
1539 | ddata->cfg.quirks |= q->quirks; | |
1540 | } | |
1541 | } | |
1542 | } | |
1543 | ||
1544 | /* | |
1545 | * DSS needs dispc outputs disabled to reset modules. Returns mask of | |
1546 | * enabled DSS interrupts. Eventually we may be able to do this on | |
1547 | * dispc init rather than top-level DSS init. | |
1548 | */ | |
1549 | static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset, | |
1550 | bool disable) | |
1551 | { | |
1552 | bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false; | |
1553 | const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1); | |
1554 | int manager_count; | |
1555 | bool framedonetv_irq = true; | |
1556 | u32 val, irq_mask = 0; | |
1557 | ||
1558 | switch (sysc_soc->soc) { | |
1559 | case SOC_2420 ... SOC_3630: | |
1560 | manager_count = 2; | |
1561 | framedonetv_irq = false; | |
1562 | break; | |
1563 | case SOC_4430 ... SOC_4470: | |
1564 | manager_count = 3; | |
1565 | break; | |
1566 | case SOC_5430: | |
1567 | case SOC_DRA7: | |
1568 | manager_count = 4; | |
1569 | break; | |
1570 | case SOC_AM4: | |
1571 | manager_count = 1; | |
1572 | framedonetv_irq = false; | |
1573 | break; | |
1574 | case SOC_UNKNOWN: | |
1575 | default: | |
1576 | return 0; | |
1577 | }; | |
1578 | ||
1579 | /* Remap the whole module range to be able to reset dispc outputs */ | |
1580 | devm_iounmap(ddata->dev, ddata->module_va); | |
1581 | ddata->module_va = devm_ioremap(ddata->dev, | |
1582 | ddata->module_pa, | |
1583 | ddata->module_size); | |
1584 | if (!ddata->module_va) | |
1585 | return -EIO; | |
1586 | ||
1587 | /* DISP_CONTROL */ | |
1588 | val = sysc_read(ddata, dispc_offset + 0x40); | |
1589 | lcd_en = val & lcd_en_mask; | |
1590 | digit_en = val & digit_en_mask; | |
1591 | if (lcd_en) | |
1592 | irq_mask |= BIT(0); /* FRAMEDONE */ | |
1593 | if (digit_en) { | |
1594 | if (framedonetv_irq) | |
1595 | irq_mask |= BIT(24); /* FRAMEDONETV */ | |
1596 | else | |
1597 | irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */ | |
1598 | } | |
1599 | if (disable & (lcd_en | digit_en)) | |
1600 | sysc_write(ddata, dispc_offset + 0x40, | |
1601 | val & ~(lcd_en_mask | digit_en_mask)); | |
1602 | ||
1603 | if (manager_count <= 2) | |
1604 | return irq_mask; | |
1605 | ||
1606 | /* DISPC_CONTROL2 */ | |
1607 | val = sysc_read(ddata, dispc_offset + 0x238); | |
1608 | lcd2_en = val & lcd_en_mask; | |
1609 | if (lcd2_en) | |
1610 | irq_mask |= BIT(22); /* FRAMEDONE2 */ | |
1611 | if (disable && lcd2_en) | |
1612 | sysc_write(ddata, dispc_offset + 0x238, | |
1613 | val & ~lcd_en_mask); | |
1614 | ||
1615 | if (manager_count <= 3) | |
1616 | return irq_mask; | |
1617 | ||
1618 | /* DISPC_CONTROL3 */ | |
1619 | val = sysc_read(ddata, dispc_offset + 0x848); | |
1620 | lcd3_en = val & lcd_en_mask; | |
1621 | if (lcd3_en) | |
1622 | irq_mask |= BIT(30); /* FRAMEDONE3 */ | |
1623 | if (disable && lcd3_en) | |
1624 | sysc_write(ddata, dispc_offset + 0x848, | |
1625 | val & ~lcd_en_mask); | |
1626 | ||
1627 | return irq_mask; | |
1628 | } | |
1629 | ||
1630 | /* DSS needs child outputs disabled and SDI registers cleared for reset */ | |
1631 | static void sysc_pre_reset_quirk_dss(struct sysc *ddata) | |
1632 | { | |
1633 | const int dispc_offset = 0x1000; | |
1634 | int error; | |
1635 | u32 irq_mask, val; | |
1636 | ||
1637 | /* Get enabled outputs */ | |
1638 | irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false); | |
1639 | if (!irq_mask) | |
1640 | return; | |
1641 | ||
1642 | /* Clear IRQSTATUS */ | |
1643 | sysc_write(ddata, dispc_offset + 0x18, irq_mask); | |
1644 | ||
1645 | /* Disable outputs */ | |
1646 | val = sysc_quirk_dispc(ddata, dispc_offset, true); | |
1647 | ||
1648 | /* Poll IRQSTATUS */ | |
1649 | error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18, | |
1650 | val, val != irq_mask, 100, 50); | |
1651 | if (error) | |
1652 | dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n", | |
1653 | __func__, val, irq_mask); | |
1654 | ||
1655 | if (sysc_soc->soc == SOC_3430) { | |
1656 | /* Clear DSS_SDI_CONTROL */ | |
1657 | sysc_write(ddata, 0x44, 0); | |
1658 | ||
1659 | /* Clear DSS_PLL_CONTROL */ | |
1660 | sysc_write(ddata, 0x48, 0); | |
1661 | } | |
1662 | ||
1663 | /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */ | |
1664 | sysc_write(ddata, 0x40, 0); | |
1665 | } | |
1666 | ||
1667 | /* 1-wire needs module's internal clocks enabled for reset */ | |
1668 | static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata) | |
1669 | { | |
1670 | int offset = 0x0c; /* HDQ_CTRL_STATUS */ | |
1671 | u16 val; | |
1672 | ||
1673 | val = sysc_read(ddata, offset); | |
1674 | val |= BIT(5); | |
1675 | sysc_write(ddata, offset, val); | |
1676 | } | |
1677 | ||
1678 | /* AESS (Audio Engine SubSystem) needs autogating set after enable */ | |
1679 | static void sysc_module_enable_quirk_aess(struct sysc *ddata) | |
1680 | { | |
1681 | int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */ | |
1682 | ||
1683 | sysc_write(ddata, offset, 1); | |
1684 | } | |
1685 | ||
1686 | /* I2C needs to be disabled for reset */ | |
1687 | static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable) | |
1688 | { | |
1689 | int offset; | |
1690 | u16 val; | |
1691 | ||
1692 | /* I2C_CON, omap2/3 is different from omap4 and later */ | |
1693 | if ((ddata->revision & 0xffffff00) == 0x001f0000) | |
1694 | offset = 0x24; | |
1695 | else | |
1696 | offset = 0xa4; | |
1697 | ||
1698 | /* I2C_EN */ | |
1699 | val = sysc_read(ddata, offset); | |
1700 | if (enable) | |
1701 | val |= BIT(15); | |
1702 | else | |
1703 | val &= ~BIT(15); | |
1704 | sysc_write(ddata, offset, val); | |
1705 | } | |
1706 | ||
1707 | static void sysc_pre_reset_quirk_i2c(struct sysc *ddata) | |
1708 | { | |
1709 | sysc_clk_quirk_i2c(ddata, false); | |
1710 | } | |
1711 | ||
1712 | static void sysc_post_reset_quirk_i2c(struct sysc *ddata) | |
1713 | { | |
1714 | sysc_clk_quirk_i2c(ddata, true); | |
1715 | } | |
1716 | ||
1717 | /* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */ | |
1718 | static void sysc_quirk_rtc(struct sysc *ddata, bool lock) | |
1719 | { | |
1720 | u32 val, kick0_val = 0, kick1_val = 0; | |
1721 | unsigned long flags; | |
1722 | int error; | |
1723 | ||
1724 | if (!lock) { | |
1725 | kick0_val = 0x83e70b13; | |
1726 | kick1_val = 0x95a4f1e0; | |
1727 | } | |
1728 | ||
1729 | local_irq_save(flags); | |
1730 | /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */ | |
1731 | error = readl_poll_timeout(ddata->module_va + 0x44, val, | |
1732 | !(val & BIT(0)), 100, 50); | |
1733 | if (error) | |
1734 | dev_warn(ddata->dev, "rtc busy timeout\n"); | |
1735 | /* Now we have ~15 microseconds to read/write various registers */ | |
1736 | sysc_write(ddata, 0x6c, kick0_val); | |
1737 | sysc_write(ddata, 0x70, kick1_val); | |
1738 | local_irq_restore(flags); | |
1739 | } | |
1740 | ||
1741 | static void sysc_module_unlock_quirk_rtc(struct sysc *ddata) | |
1742 | { | |
1743 | sysc_quirk_rtc(ddata, false); | |
1744 | } | |
1745 | ||
1746 | static void sysc_module_lock_quirk_rtc(struct sysc *ddata) | |
1747 | { | |
1748 | sysc_quirk_rtc(ddata, true); | |
1749 | } | |
1750 | ||
1751 | /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */ | |
1752 | static void sysc_module_enable_quirk_sgx(struct sysc *ddata) | |
1753 | { | |
1754 | int offset = 0xff08; /* OCP_DEBUG_CONFIG */ | |
1755 | u32 val = BIT(31); /* THALIA_INT_BYPASS */ | |
1756 | ||
1757 | sysc_write(ddata, offset, val); | |
1758 | } | |
1759 | ||
1760 | /* Watchdog timer needs a disable sequence after reset */ | |
1761 | static void sysc_reset_done_quirk_wdt(struct sysc *ddata) | |
1762 | { | |
1763 | int wps, spr, error; | |
1764 | u32 val; | |
1765 | ||
1766 | wps = 0x34; | |
1767 | spr = 0x48; | |
1768 | ||
1769 | sysc_write(ddata, spr, 0xaaaa); | |
1770 | error = readl_poll_timeout(ddata->module_va + wps, val, | |
1771 | !(val & 0x10), 100, | |
1772 | MAX_MODULE_SOFTRESET_WAIT); | |
1773 | if (error) | |
1774 | dev_warn(ddata->dev, "wdt disable step1 failed\n"); | |
1775 | ||
1776 | sysc_write(ddata, spr, 0x5555); | |
1777 | error = readl_poll_timeout(ddata->module_va + wps, val, | |
1778 | !(val & 0x10), 100, | |
1779 | MAX_MODULE_SOFTRESET_WAIT); | |
1780 | if (error) | |
1781 | dev_warn(ddata->dev, "wdt disable step2 failed\n"); | |
1782 | } | |
1783 | ||
1784 | /* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */ | |
1785 | static void sysc_module_disable_quirk_pruss(struct sysc *ddata) | |
1786 | { | |
1787 | u32 reg; | |
1788 | ||
1789 | reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); | |
1790 | reg |= SYSC_PRUSS_STANDBY_INIT; | |
1791 | sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); | |
1792 | } | |
1793 | ||
1794 | static void sysc_init_module_quirks(struct sysc *ddata) | |
1795 | { | |
1796 | if (ddata->legacy_mode || !ddata->name) | |
1797 | return; | |
1798 | ||
1799 | if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) { | |
1800 | ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w; | |
1801 | ||
1802 | return; | |
1803 | } | |
1804 | ||
1805 | if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) { | |
1806 | ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c; | |
1807 | ddata->post_reset_quirk = sysc_post_reset_quirk_i2c; | |
1808 | ||
1809 | return; | |
1810 | } | |
1811 | ||
1812 | if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS) | |
1813 | ddata->module_enable_quirk = sysc_module_enable_quirk_aess; | |
1814 | ||
1815 | if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET) | |
1816 | ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss; | |
1817 | ||
1818 | if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) { | |
1819 | ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc; | |
1820 | ddata->module_lock_quirk = sysc_module_lock_quirk_rtc; | |
1821 | ||
1822 | return; | |
1823 | } | |
1824 | ||
1825 | if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX) | |
1826 | ddata->module_enable_quirk = sysc_module_enable_quirk_sgx; | |
1827 | ||
1828 | if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) { | |
1829 | ddata->reset_done_quirk = sysc_reset_done_quirk_wdt; | |
1830 | ddata->module_disable_quirk = sysc_reset_done_quirk_wdt; | |
1831 | } | |
1832 | ||
1833 | if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS) | |
1834 | ddata->module_disable_quirk = sysc_module_disable_quirk_pruss; | |
1835 | } | |
1836 | ||
1837 | static int sysc_clockdomain_init(struct sysc *ddata) | |
1838 | { | |
1839 | struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); | |
1840 | struct clk *fck = NULL, *ick = NULL; | |
1841 | int error; | |
1842 | ||
1843 | if (!pdata || !pdata->init_clockdomain) | |
1844 | return 0; | |
1845 | ||
1846 | switch (ddata->nr_clocks) { | |
1847 | case 2: | |
1848 | ick = ddata->clocks[SYSC_ICK]; | |
1849 | /* fallthrough */ | |
1850 | case 1: | |
1851 | fck = ddata->clocks[SYSC_FCK]; | |
1852 | break; | |
1853 | case 0: | |
1854 | return 0; | |
1855 | } | |
1856 | ||
1857 | error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie); | |
1858 | if (!error || error == -ENODEV) | |
1859 | return 0; | |
1860 | ||
1861 | return error; | |
1862 | } | |
1863 | ||
1864 | /* | |
1865 | * Note that pdata->init_module() typically does a reset first. After | |
1866 | * pdata->init_module() is done, PM runtime can be used for the interconnect | |
1867 | * target module. | |
1868 | */ | |
1869 | static int sysc_legacy_init(struct sysc *ddata) | |
1870 | { | |
1871 | struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); | |
1872 | int error; | |
1873 | ||
1874 | if (!pdata || !pdata->init_module) | |
1875 | return 0; | |
1876 | ||
1877 | error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie); | |
1878 | if (error == -EEXIST) | |
1879 | error = 0; | |
1880 | ||
1881 | return error; | |
1882 | } | |
1883 | ||
1884 | /* | |
1885 | * Note that the caller must ensure the interconnect target module is enabled | |
1886 | * before calling reset. Otherwise reset will not complete. | |
1887 | */ | |
1888 | static int sysc_reset(struct sysc *ddata) | |
1889 | { | |
1890 | int sysc_offset, sysc_val, error; | |
1891 | u32 sysc_mask; | |
1892 | ||
1893 | sysc_offset = ddata->offsets[SYSC_SYSCONFIG]; | |
1894 | ||
1895 | if (ddata->legacy_mode || | |
1896 | ddata->cap->regbits->srst_shift < 0 || | |
1897 | ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) | |
1898 | return 0; | |
1899 | ||
1900 | sysc_mask = BIT(ddata->cap->regbits->srst_shift); | |
1901 | ||
1902 | if (ddata->pre_reset_quirk) | |
1903 | ddata->pre_reset_quirk(ddata); | |
1904 | ||
1905 | if (sysc_offset >= 0) { | |
1906 | sysc_val = sysc_read_sysconfig(ddata); | |
1907 | sysc_val |= sysc_mask; | |
1908 | sysc_write(ddata, sysc_offset, sysc_val); | |
1909 | } | |
1910 | ||
1911 | if (ddata->cfg.srst_udelay) | |
1912 | usleep_range(ddata->cfg.srst_udelay, | |
1913 | ddata->cfg.srst_udelay * 2); | |
1914 | ||
1915 | if (ddata->post_reset_quirk) | |
1916 | ddata->post_reset_quirk(ddata); | |
1917 | ||
1918 | error = sysc_wait_softreset(ddata); | |
1919 | if (error) | |
1920 | dev_warn(ddata->dev, "OCP softreset timed out\n"); | |
1921 | ||
1922 | if (ddata->reset_done_quirk) | |
1923 | ddata->reset_done_quirk(ddata); | |
1924 | ||
1925 | return error; | |
1926 | } | |
1927 | ||
1928 | /* | |
1929 | * At this point the module is configured enough to read the revision but | |
1930 | * module may not be completely configured yet to use PM runtime. Enable | |
1931 | * all clocks directly during init to configure the quirks needed for PM | |
1932 | * runtime based on the revision register. | |
1933 | */ | |
1934 | static int sysc_init_module(struct sysc *ddata) | |
1935 | { | |
1936 | int error = 0; | |
1937 | ||
1938 | error = sysc_clockdomain_init(ddata); | |
1939 | if (error) | |
1940 | return error; | |
1941 | ||
1942 | sysc_clkdm_deny_idle(ddata); | |
1943 | ||
1944 | /* | |
1945 | * Always enable clocks. The bootloader may or may not have enabled | |
1946 | * the related clocks. | |
1947 | */ | |
1948 | error = sysc_enable_opt_clocks(ddata); | |
1949 | if (error) | |
1950 | return error; | |
1951 | ||
1952 | error = sysc_enable_main_clocks(ddata); | |
1953 | if (error) | |
1954 | goto err_opt_clocks; | |
1955 | ||
1956 | if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) { | |
1957 | error = reset_control_deassert(ddata->rsts); | |
1958 | if (error) | |
1959 | goto err_main_clocks; | |
1960 | } | |
1961 | ||
1962 | ddata->revision = sysc_read_revision(ddata); | |
1963 | sysc_init_revision_quirks(ddata); | |
1964 | sysc_init_module_quirks(ddata); | |
1965 | ||
1966 | if (ddata->legacy_mode) { | |
1967 | error = sysc_legacy_init(ddata); | |
1968 | if (error) | |
1969 | goto err_reset; | |
1970 | } | |
1971 | ||
1972 | if (!ddata->legacy_mode) { | |
1973 | error = sysc_enable_module(ddata->dev); | |
1974 | if (error) | |
1975 | goto err_reset; | |
1976 | } | |
1977 | ||
1978 | error = sysc_reset(ddata); | |
1979 | if (error) | |
1980 | dev_err(ddata->dev, "Reset failed with %d\n", error); | |
1981 | ||
1982 | if (error && !ddata->legacy_mode) | |
1983 | sysc_disable_module(ddata->dev); | |
1984 | ||
1985 | err_reset: | |
1986 | if (error && !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) | |
1987 | reset_control_assert(ddata->rsts); | |
1988 | ||
1989 | err_main_clocks: | |
1990 | if (error) | |
1991 | sysc_disable_main_clocks(ddata); | |
1992 | err_opt_clocks: | |
1993 | /* No re-enable of clockdomain autoidle to prevent module autoidle */ | |
1994 | if (error) { | |
1995 | sysc_disable_opt_clocks(ddata); | |
1996 | sysc_clkdm_allow_idle(ddata); | |
1997 | } | |
1998 | ||
1999 | return error; | |
2000 | } | |
2001 | ||
2002 | static int sysc_init_sysc_mask(struct sysc *ddata) | |
2003 | { | |
2004 | struct device_node *np = ddata->dev->of_node; | |
2005 | int error; | |
2006 | u32 val; | |
2007 | ||
2008 | error = of_property_read_u32(np, "ti,sysc-mask", &val); | |
2009 | if (error) | |
2010 | return 0; | |
2011 | ||
2012 | ddata->cfg.sysc_val = val & ddata->cap->sysc_mask; | |
2013 | ||
2014 | return 0; | |
2015 | } | |
2016 | ||
2017 | static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes, | |
2018 | const char *name) | |
2019 | { | |
2020 | struct device_node *np = ddata->dev->of_node; | |
2021 | struct property *prop; | |
2022 | const __be32 *p; | |
2023 | u32 val; | |
2024 | ||
2025 | of_property_for_each_u32(np, name, prop, p, val) { | |
2026 | if (val >= SYSC_NR_IDLEMODES) { | |
2027 | dev_err(ddata->dev, "invalid idlemode: %i\n", val); | |
2028 | return -EINVAL; | |
2029 | } | |
2030 | *idlemodes |= (1 << val); | |
2031 | } | |
2032 | ||
2033 | return 0; | |
2034 | } | |
2035 | ||
2036 | static int sysc_init_idlemodes(struct sysc *ddata) | |
2037 | { | |
2038 | int error; | |
2039 | ||
2040 | error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes, | |
2041 | "ti,sysc-midle"); | |
2042 | if (error) | |
2043 | return error; | |
2044 | ||
2045 | error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes, | |
2046 | "ti,sysc-sidle"); | |
2047 | if (error) | |
2048 | return error; | |
2049 | ||
2050 | return 0; | |
2051 | } | |
2052 | ||
2053 | /* | |
2054 | * Only some devices on omap4 and later have SYSCONFIG reset done | |
2055 | * bit. We can detect this if there is no SYSSTATUS at all, or the | |
2056 | * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers | |
2057 | * have multiple bits for the child devices like OHCI and EHCI. | |
2058 | * Depends on SYSC being parsed first. | |
2059 | */ | |
2060 | static int sysc_init_syss_mask(struct sysc *ddata) | |
2061 | { | |
2062 | struct device_node *np = ddata->dev->of_node; | |
2063 | int error; | |
2064 | u32 val; | |
2065 | ||
2066 | error = of_property_read_u32(np, "ti,syss-mask", &val); | |
2067 | if (error) { | |
2068 | if ((ddata->cap->type == TI_SYSC_OMAP4 || | |
2069 | ddata->cap->type == TI_SYSC_OMAP4_TIMER) && | |
2070 | (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) | |
2071 | ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; | |
2072 | ||
2073 | return 0; | |
2074 | } | |
2075 | ||
2076 | if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) | |
2077 | ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; | |
2078 | ||
2079 | ddata->cfg.syss_mask = val; | |
2080 | ||
2081 | return 0; | |
2082 | } | |
2083 | ||
2084 | /* | |
2085 | * Many child device drivers need to have fck and opt clocks available | |
2086 | * to get the clock rate for device internal configuration etc. | |
2087 | */ | |
2088 | static int sysc_child_add_named_clock(struct sysc *ddata, | |
2089 | struct device *child, | |
2090 | const char *name) | |
2091 | { | |
2092 | struct clk *clk; | |
2093 | struct clk_lookup *l; | |
2094 | int error = 0; | |
2095 | ||
2096 | if (!name) | |
2097 | return 0; | |
2098 | ||
2099 | clk = clk_get(child, name); | |
2100 | if (!IS_ERR(clk)) { | |
2101 | error = -EEXIST; | |
2102 | goto put_clk; | |
2103 | } | |
2104 | ||
2105 | clk = clk_get(ddata->dev, name); | |
2106 | if (IS_ERR(clk)) | |
2107 | return -ENODEV; | |
2108 | ||
2109 | l = clkdev_create(clk, name, dev_name(child)); | |
2110 | if (!l) | |
2111 | error = -ENOMEM; | |
2112 | put_clk: | |
2113 | clk_put(clk); | |
2114 | ||
2115 | return error; | |
2116 | } | |
2117 | ||
2118 | static int sysc_child_add_clocks(struct sysc *ddata, | |
2119 | struct device *child) | |
2120 | { | |
2121 | int i, error; | |
2122 | ||
2123 | for (i = 0; i < ddata->nr_clocks; i++) { | |
2124 | error = sysc_child_add_named_clock(ddata, | |
2125 | child, | |
2126 | ddata->clock_roles[i]); | |
2127 | if (error && error != -EEXIST) { | |
2128 | dev_err(ddata->dev, "could not add child clock %s: %i\n", | |
2129 | ddata->clock_roles[i], error); | |
2130 | ||
2131 | return error; | |
2132 | } | |
2133 | } | |
2134 | ||
2135 | return 0; | |
2136 | } | |
2137 | ||
2138 | static struct device_type sysc_device_type = { | |
2139 | }; | |
2140 | ||
2141 | static struct sysc *sysc_child_to_parent(struct device *dev) | |
2142 | { | |
2143 | struct device *parent = dev->parent; | |
2144 | ||
2145 | if (!parent || parent->type != &sysc_device_type) | |
2146 | return NULL; | |
2147 | ||
2148 | return dev_get_drvdata(parent); | |
2149 | } | |
2150 | ||
2151 | static int __maybe_unused sysc_child_runtime_suspend(struct device *dev) | |
2152 | { | |
2153 | struct sysc *ddata; | |
2154 | int error; | |
2155 | ||
2156 | ddata = sysc_child_to_parent(dev); | |
2157 | ||
2158 | error = pm_generic_runtime_suspend(dev); | |
2159 | if (error) | |
2160 | return error; | |
2161 | ||
2162 | if (!ddata->enabled) | |
2163 | return 0; | |
2164 | ||
2165 | return sysc_runtime_suspend(ddata->dev); | |
2166 | } | |
2167 | ||
2168 | static int __maybe_unused sysc_child_runtime_resume(struct device *dev) | |
2169 | { | |
2170 | struct sysc *ddata; | |
2171 | int error; | |
2172 | ||
2173 | ddata = sysc_child_to_parent(dev); | |
2174 | ||
2175 | if (!ddata->enabled) { | |
2176 | error = sysc_runtime_resume(ddata->dev); | |
2177 | if (error < 0) | |
2178 | dev_err(ddata->dev, | |
2179 | "%s error: %i\n", __func__, error); | |
2180 | } | |
2181 | ||
2182 | return pm_generic_runtime_resume(dev); | |
2183 | } | |
2184 | ||
2185 | #ifdef CONFIG_PM_SLEEP | |
2186 | static int sysc_child_suspend_noirq(struct device *dev) | |
2187 | { | |
2188 | struct sysc *ddata; | |
2189 | int error; | |
2190 | ||
2191 | ddata = sysc_child_to_parent(dev); | |
2192 | ||
2193 | dev_dbg(ddata->dev, "%s %s\n", __func__, | |
2194 | ddata->name ? ddata->name : ""); | |
2195 | ||
2196 | error = pm_generic_suspend_noirq(dev); | |
2197 | if (error) { | |
2198 | dev_err(dev, "%s error at %i: %i\n", | |
2199 | __func__, __LINE__, error); | |
2200 | ||
2201 | return error; | |
2202 | } | |
2203 | ||
2204 | if (!pm_runtime_status_suspended(dev)) { | |
2205 | error = pm_generic_runtime_suspend(dev); | |
2206 | if (error) { | |
2207 | dev_dbg(dev, "%s busy at %i: %i\n", | |
2208 | __func__, __LINE__, error); | |
2209 | ||
2210 | return 0; | |
2211 | } | |
2212 | ||
2213 | error = sysc_runtime_suspend(ddata->dev); | |
2214 | if (error) { | |
2215 | dev_err(dev, "%s error at %i: %i\n", | |
2216 | __func__, __LINE__, error); | |
2217 | ||
2218 | return error; | |
2219 | } | |
2220 | ||
2221 | ddata->child_needs_resume = true; | |
2222 | } | |
2223 | ||
2224 | return 0; | |
2225 | } | |
2226 | ||
2227 | static int sysc_child_resume_noirq(struct device *dev) | |
2228 | { | |
2229 | struct sysc *ddata; | |
2230 | int error; | |
2231 | ||
2232 | ddata = sysc_child_to_parent(dev); | |
2233 | ||
2234 | dev_dbg(ddata->dev, "%s %s\n", __func__, | |
2235 | ddata->name ? ddata->name : ""); | |
2236 | ||
2237 | if (ddata->child_needs_resume) { | |
2238 | ddata->child_needs_resume = false; | |
2239 | ||
2240 | error = sysc_runtime_resume(ddata->dev); | |
2241 | if (error) | |
2242 | dev_err(ddata->dev, | |
2243 | "%s runtime resume error: %i\n", | |
2244 | __func__, error); | |
2245 | ||
2246 | error = pm_generic_runtime_resume(dev); | |
2247 | if (error) | |
2248 | dev_err(ddata->dev, | |
2249 | "%s generic runtime resume: %i\n", | |
2250 | __func__, error); | |
2251 | } | |
2252 | ||
2253 | return pm_generic_resume_noirq(dev); | |
2254 | } | |
2255 | #endif | |
2256 | ||
2257 | static struct dev_pm_domain sysc_child_pm_domain = { | |
2258 | .ops = { | |
2259 | SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend, | |
2260 | sysc_child_runtime_resume, | |
2261 | NULL) | |
2262 | USE_PLATFORM_PM_SLEEP_OPS | |
2263 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq, | |
2264 | sysc_child_resume_noirq) | |
2265 | } | |
2266 | }; | |
2267 | ||
2268 | /** | |
2269 | * sysc_legacy_idle_quirk - handle children in omap_device compatible way | |
2270 | * @ddata: device driver data | |
2271 | * @child: child device driver | |
2272 | * | |
2273 | * Allow idle for child devices as done with _od_runtime_suspend(). | |
2274 | * Otherwise many child devices will not idle because of the permanent | |
2275 | * parent usecount set in pm_runtime_irq_safe(). | |
2276 | * | |
2277 | * Note that the long term solution is to just modify the child device | |
2278 | * drivers to not set pm_runtime_irq_safe() and then this can be just | |
2279 | * dropped. | |
2280 | */ | |
2281 | static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child) | |
2282 | { | |
2283 | if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) | |
2284 | dev_pm_domain_set(child, &sysc_child_pm_domain); | |
2285 | } | |
2286 | ||
2287 | static int sysc_notifier_call(struct notifier_block *nb, | |
2288 | unsigned long event, void *device) | |
2289 | { | |
2290 | struct device *dev = device; | |
2291 | struct sysc *ddata; | |
2292 | int error; | |
2293 | ||
2294 | ddata = sysc_child_to_parent(dev); | |
2295 | if (!ddata) | |
2296 | return NOTIFY_DONE; | |
2297 | ||
2298 | switch (event) { | |
2299 | case BUS_NOTIFY_ADD_DEVICE: | |
2300 | error = sysc_child_add_clocks(ddata, dev); | |
2301 | if (error) | |
2302 | return error; | |
2303 | sysc_legacy_idle_quirk(ddata, dev); | |
2304 | break; | |
2305 | default: | |
2306 | break; | |
2307 | } | |
2308 | ||
2309 | return NOTIFY_DONE; | |
2310 | } | |
2311 | ||
2312 | static struct notifier_block sysc_nb = { | |
2313 | .notifier_call = sysc_notifier_call, | |
2314 | }; | |
2315 | ||
2316 | /* Device tree configured quirks */ | |
2317 | struct sysc_dts_quirk { | |
2318 | const char *name; | |
2319 | u32 mask; | |
2320 | }; | |
2321 | ||
2322 | static const struct sysc_dts_quirk sysc_dts_quirks[] = { | |
2323 | { .name = "ti,no-idle-on-init", | |
2324 | .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, }, | |
2325 | { .name = "ti,no-reset-on-init", | |
2326 | .mask = SYSC_QUIRK_NO_RESET_ON_INIT, }, | |
2327 | { .name = "ti,no-idle", | |
2328 | .mask = SYSC_QUIRK_NO_IDLE, }, | |
2329 | }; | |
2330 | ||
2331 | static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, | |
2332 | bool is_child) | |
2333 | { | |
2334 | const struct property *prop; | |
2335 | int i, len; | |
2336 | ||
2337 | for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) { | |
2338 | const char *name = sysc_dts_quirks[i].name; | |
2339 | ||
2340 | prop = of_get_property(np, name, &len); | |
2341 | if (!prop) | |
2342 | continue; | |
2343 | ||
2344 | ddata->cfg.quirks |= sysc_dts_quirks[i].mask; | |
2345 | if (is_child) { | |
2346 | dev_warn(ddata->dev, | |
2347 | "dts flag should be at module level for %s\n", | |
2348 | name); | |
2349 | } | |
2350 | } | |
2351 | } | |
2352 | ||
2353 | static int sysc_init_dts_quirks(struct sysc *ddata) | |
2354 | { | |
2355 | struct device_node *np = ddata->dev->of_node; | |
2356 | int error; | |
2357 | u32 val; | |
2358 | ||
2359 | ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL); | |
2360 | ||
2361 | sysc_parse_dts_quirks(ddata, np, false); | |
2362 | error = of_property_read_u32(np, "ti,sysc-delay-us", &val); | |
2363 | if (!error) { | |
2364 | if (val > 255) { | |
2365 | dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n", | |
2366 | val); | |
2367 | } | |
2368 | ||
2369 | ddata->cfg.srst_udelay = (u8)val; | |
2370 | } | |
2371 | ||
2372 | return 0; | |
2373 | } | |
2374 | ||
2375 | static void sysc_unprepare(struct sysc *ddata) | |
2376 | { | |
2377 | int i; | |
2378 | ||
2379 | if (!ddata->clocks) | |
2380 | return; | |
2381 | ||
2382 | for (i = 0; i < SYSC_MAX_CLOCKS; i++) { | |
2383 | if (!IS_ERR_OR_NULL(ddata->clocks[i])) | |
2384 | clk_unprepare(ddata->clocks[i]); | |
2385 | } | |
2386 | } | |
2387 | ||
2388 | /* | |
2389 | * Common sysc register bits found on omap2, also known as type1 | |
2390 | */ | |
2391 | static const struct sysc_regbits sysc_regbits_omap2 = { | |
2392 | .dmadisable_shift = -ENODEV, | |
2393 | .midle_shift = 12, | |
2394 | .sidle_shift = 3, | |
2395 | .clkact_shift = 8, | |
2396 | .emufree_shift = 5, | |
2397 | .enwkup_shift = 2, | |
2398 | .srst_shift = 1, | |
2399 | .autoidle_shift = 0, | |
2400 | }; | |
2401 | ||
2402 | static const struct sysc_capabilities sysc_omap2 = { | |
2403 | .type = TI_SYSC_OMAP2, | |
2404 | .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | | |
2405 | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | | |
2406 | SYSC_OMAP2_AUTOIDLE, | |
2407 | .regbits = &sysc_regbits_omap2, | |
2408 | }; | |
2409 | ||
2410 | /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */ | |
2411 | static const struct sysc_capabilities sysc_omap2_timer = { | |
2412 | .type = TI_SYSC_OMAP2_TIMER, | |
2413 | .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | | |
2414 | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | | |
2415 | SYSC_OMAP2_AUTOIDLE, | |
2416 | .regbits = &sysc_regbits_omap2, | |
2417 | .mod_quirks = SYSC_QUIRK_USE_CLOCKACT, | |
2418 | }; | |
2419 | ||
2420 | /* | |
2421 | * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2 | |
2422 | * with different sidle position | |
2423 | */ | |
2424 | static const struct sysc_regbits sysc_regbits_omap3_sham = { | |
2425 | .dmadisable_shift = -ENODEV, | |
2426 | .midle_shift = -ENODEV, | |
2427 | .sidle_shift = 4, | |
2428 | .clkact_shift = -ENODEV, | |
2429 | .enwkup_shift = -ENODEV, | |
2430 | .srst_shift = 1, | |
2431 | .autoidle_shift = 0, | |
2432 | .emufree_shift = -ENODEV, | |
2433 | }; | |
2434 | ||
2435 | static const struct sysc_capabilities sysc_omap3_sham = { | |
2436 | .type = TI_SYSC_OMAP3_SHAM, | |
2437 | .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, | |
2438 | .regbits = &sysc_regbits_omap3_sham, | |
2439 | }; | |
2440 | ||
2441 | /* | |
2442 | * AES register bits found on omap3 and later, a variant of | |
2443 | * sysc_regbits_omap2 with different sidle position | |
2444 | */ | |
2445 | static const struct sysc_regbits sysc_regbits_omap3_aes = { | |
2446 | .dmadisable_shift = -ENODEV, | |
2447 | .midle_shift = -ENODEV, | |
2448 | .sidle_shift = 6, | |
2449 | .clkact_shift = -ENODEV, | |
2450 | .enwkup_shift = -ENODEV, | |
2451 | .srst_shift = 1, | |
2452 | .autoidle_shift = 0, | |
2453 | .emufree_shift = -ENODEV, | |
2454 | }; | |
2455 | ||
2456 | static const struct sysc_capabilities sysc_omap3_aes = { | |
2457 | .type = TI_SYSC_OMAP3_AES, | |
2458 | .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, | |
2459 | .regbits = &sysc_regbits_omap3_aes, | |
2460 | }; | |
2461 | ||
2462 | /* | |
2463 | * Common sysc register bits found on omap4, also known as type2 | |
2464 | */ | |
2465 | static const struct sysc_regbits sysc_regbits_omap4 = { | |
2466 | .dmadisable_shift = 16, | |
2467 | .midle_shift = 4, | |
2468 | .sidle_shift = 2, | |
2469 | .clkact_shift = -ENODEV, | |
2470 | .enwkup_shift = -ENODEV, | |
2471 | .emufree_shift = 1, | |
2472 | .srst_shift = 0, | |
2473 | .autoidle_shift = -ENODEV, | |
2474 | }; | |
2475 | ||
2476 | static const struct sysc_capabilities sysc_omap4 = { | |
2477 | .type = TI_SYSC_OMAP4, | |
2478 | .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | | |
2479 | SYSC_OMAP4_SOFTRESET, | |
2480 | .regbits = &sysc_regbits_omap4, | |
2481 | }; | |
2482 | ||
2483 | static const struct sysc_capabilities sysc_omap4_timer = { | |
2484 | .type = TI_SYSC_OMAP4_TIMER, | |
2485 | .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | | |
2486 | SYSC_OMAP4_SOFTRESET, | |
2487 | .regbits = &sysc_regbits_omap4, | |
2488 | }; | |
2489 | ||
2490 | /* | |
2491 | * Common sysc register bits found on omap4, also known as type3 | |
2492 | */ | |
2493 | static const struct sysc_regbits sysc_regbits_omap4_simple = { | |
2494 | .dmadisable_shift = -ENODEV, | |
2495 | .midle_shift = 2, | |
2496 | .sidle_shift = 0, | |
2497 | .clkact_shift = -ENODEV, | |
2498 | .enwkup_shift = -ENODEV, | |
2499 | .srst_shift = -ENODEV, | |
2500 | .emufree_shift = -ENODEV, | |
2501 | .autoidle_shift = -ENODEV, | |
2502 | }; | |
2503 | ||
2504 | static const struct sysc_capabilities sysc_omap4_simple = { | |
2505 | .type = TI_SYSC_OMAP4_SIMPLE, | |
2506 | .regbits = &sysc_regbits_omap4_simple, | |
2507 | }; | |
2508 | ||
2509 | /* | |
2510 | * SmartReflex sysc found on omap34xx | |
2511 | */ | |
2512 | static const struct sysc_regbits sysc_regbits_omap34xx_sr = { | |
2513 | .dmadisable_shift = -ENODEV, | |
2514 | .midle_shift = -ENODEV, | |
2515 | .sidle_shift = -ENODEV, | |
2516 | .clkact_shift = 20, | |
2517 | .enwkup_shift = -ENODEV, | |
2518 | .srst_shift = -ENODEV, | |
2519 | .emufree_shift = -ENODEV, | |
2520 | .autoidle_shift = -ENODEV, | |
2521 | }; | |
2522 | ||
2523 | static const struct sysc_capabilities sysc_34xx_sr = { | |
2524 | .type = TI_SYSC_OMAP34XX_SR, | |
2525 | .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY, | |
2526 | .regbits = &sysc_regbits_omap34xx_sr, | |
2527 | .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED | | |
2528 | SYSC_QUIRK_LEGACY_IDLE, | |
2529 | }; | |
2530 | ||
2531 | /* | |
2532 | * SmartReflex sysc found on omap36xx and later | |
2533 | */ | |
2534 | static const struct sysc_regbits sysc_regbits_omap36xx_sr = { | |
2535 | .dmadisable_shift = -ENODEV, | |
2536 | .midle_shift = -ENODEV, | |
2537 | .sidle_shift = 24, | |
2538 | .clkact_shift = -ENODEV, | |
2539 | .enwkup_shift = 26, | |
2540 | .srst_shift = -ENODEV, | |
2541 | .emufree_shift = -ENODEV, | |
2542 | .autoidle_shift = -ENODEV, | |
2543 | }; | |
2544 | ||
2545 | static const struct sysc_capabilities sysc_36xx_sr = { | |
2546 | .type = TI_SYSC_OMAP36XX_SR, | |
2547 | .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP, | |
2548 | .regbits = &sysc_regbits_omap36xx_sr, | |
2549 | .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE, | |
2550 | }; | |
2551 | ||
2552 | static const struct sysc_capabilities sysc_omap4_sr = { | |
2553 | .type = TI_SYSC_OMAP4_SR, | |
2554 | .regbits = &sysc_regbits_omap36xx_sr, | |
2555 | .mod_quirks = SYSC_QUIRK_LEGACY_IDLE, | |
2556 | }; | |
2557 | ||
2558 | /* | |
2559 | * McASP register bits found on omap4 and later | |
2560 | */ | |
2561 | static const struct sysc_regbits sysc_regbits_omap4_mcasp = { | |
2562 | .dmadisable_shift = -ENODEV, | |
2563 | .midle_shift = -ENODEV, | |
2564 | .sidle_shift = 0, | |
2565 | .clkact_shift = -ENODEV, | |
2566 | .enwkup_shift = -ENODEV, | |
2567 | .srst_shift = -ENODEV, | |
2568 | .emufree_shift = -ENODEV, | |
2569 | .autoidle_shift = -ENODEV, | |
2570 | }; | |
2571 | ||
2572 | static const struct sysc_capabilities sysc_omap4_mcasp = { | |
2573 | .type = TI_SYSC_OMAP4_MCASP, | |
2574 | .regbits = &sysc_regbits_omap4_mcasp, | |
2575 | .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, | |
2576 | }; | |
2577 | ||
2578 | /* | |
2579 | * McASP found on dra7 and later | |
2580 | */ | |
2581 | static const struct sysc_capabilities sysc_dra7_mcasp = { | |
2582 | .type = TI_SYSC_OMAP4_SIMPLE, | |
2583 | .regbits = &sysc_regbits_omap4_simple, | |
2584 | .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, | |
2585 | }; | |
2586 | ||
2587 | /* | |
2588 | * FS USB host found on omap4 and later | |
2589 | */ | |
2590 | static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = { | |
2591 | .dmadisable_shift = -ENODEV, | |
2592 | .midle_shift = -ENODEV, | |
2593 | .sidle_shift = 24, | |
2594 | .clkact_shift = -ENODEV, | |
2595 | .enwkup_shift = 26, | |
2596 | .srst_shift = -ENODEV, | |
2597 | .emufree_shift = -ENODEV, | |
2598 | .autoidle_shift = -ENODEV, | |
2599 | }; | |
2600 | ||
2601 | static const struct sysc_capabilities sysc_omap4_usb_host_fs = { | |
2602 | .type = TI_SYSC_OMAP4_USB_HOST_FS, | |
2603 | .sysc_mask = SYSC_OMAP2_ENAWAKEUP, | |
2604 | .regbits = &sysc_regbits_omap4_usb_host_fs, | |
2605 | }; | |
2606 | ||
2607 | static const struct sysc_regbits sysc_regbits_dra7_mcan = { | |
2608 | .dmadisable_shift = -ENODEV, | |
2609 | .midle_shift = -ENODEV, | |
2610 | .sidle_shift = -ENODEV, | |
2611 | .clkact_shift = -ENODEV, | |
2612 | .enwkup_shift = 4, | |
2613 | .srst_shift = 0, | |
2614 | .emufree_shift = -ENODEV, | |
2615 | .autoidle_shift = -ENODEV, | |
2616 | }; | |
2617 | ||
2618 | static const struct sysc_capabilities sysc_dra7_mcan = { | |
2619 | .type = TI_SYSC_DRA7_MCAN, | |
2620 | .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET, | |
2621 | .regbits = &sysc_regbits_dra7_mcan, | |
2622 | .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED, | |
2623 | }; | |
2624 | ||
2625 | /* | |
2626 | * PRUSS found on some AM33xx, AM437x and AM57xx SoCs | |
2627 | */ | |
2628 | static const struct sysc_capabilities sysc_pruss = { | |
2629 | .type = TI_SYSC_PRUSS, | |
2630 | .sysc_mask = SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT, | |
2631 | .regbits = &sysc_regbits_omap4_simple, | |
2632 | .mod_quirks = SYSC_MODULE_QUIRK_PRUSS, | |
2633 | }; | |
2634 | ||
2635 | static int sysc_init_pdata(struct sysc *ddata) | |
2636 | { | |
2637 | struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); | |
2638 | struct ti_sysc_module_data *mdata; | |
2639 | ||
2640 | if (!pdata) | |
2641 | return 0; | |
2642 | ||
2643 | mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL); | |
2644 | if (!mdata) | |
2645 | return -ENOMEM; | |
2646 | ||
2647 | if (ddata->legacy_mode) { | |
2648 | mdata->name = ddata->legacy_mode; | |
2649 | mdata->module_pa = ddata->module_pa; | |
2650 | mdata->module_size = ddata->module_size; | |
2651 | mdata->offsets = ddata->offsets; | |
2652 | mdata->nr_offsets = SYSC_MAX_REGS; | |
2653 | mdata->cap = ddata->cap; | |
2654 | mdata->cfg = &ddata->cfg; | |
2655 | } | |
2656 | ||
2657 | ddata->mdata = mdata; | |
2658 | ||
2659 | return 0; | |
2660 | } | |
2661 | ||
2662 | static int sysc_init_match(struct sysc *ddata) | |
2663 | { | |
2664 | const struct sysc_capabilities *cap; | |
2665 | ||
2666 | cap = of_device_get_match_data(ddata->dev); | |
2667 | if (!cap) | |
2668 | return -EINVAL; | |
2669 | ||
2670 | ddata->cap = cap; | |
2671 | if (ddata->cap) | |
2672 | ddata->cfg.quirks |= ddata->cap->mod_quirks; | |
2673 | ||
2674 | return 0; | |
2675 | } | |
2676 | ||
2677 | static void ti_sysc_idle(struct work_struct *work) | |
2678 | { | |
2679 | struct sysc *ddata; | |
2680 | ||
2681 | ddata = container_of(work, struct sysc, idle_work.work); | |
2682 | ||
2683 | /* | |
2684 | * One time decrement of clock usage counts if left on from init. | |
2685 | * Note that we disable opt clocks unconditionally in this case | |
2686 | * as they are enabled unconditionally during init without | |
2687 | * considering sysc_opt_clks_needed() at that point. | |
2688 | */ | |
2689 | if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | | |
2690 | SYSC_QUIRK_NO_IDLE_ON_INIT)) { | |
2691 | sysc_disable_main_clocks(ddata); | |
2692 | sysc_disable_opt_clocks(ddata); | |
2693 | sysc_clkdm_allow_idle(ddata); | |
2694 | } | |
2695 | ||
2696 | /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */ | |
2697 | if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE) | |
2698 | return; | |
2699 | ||
2700 | /* | |
2701 | * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT | |
2702 | * and SYSC_QUIRK_NO_RESET_ON_INIT | |
2703 | */ | |
2704 | if (pm_runtime_active(ddata->dev)) | |
2705 | pm_runtime_put_sync(ddata->dev); | |
2706 | } | |
2707 | ||
2708 | /* | |
2709 | * SoC model and features detection. Only needed for SoCs that need | |
2710 | * special handling for quirks, no need to list others. | |
2711 | */ | |
2712 | static const struct soc_device_attribute sysc_soc_match[] = { | |
2713 | SOC_FLAG("OMAP242*", SOC_2420), | |
2714 | SOC_FLAG("OMAP243*", SOC_2430), | |
2715 | SOC_FLAG("OMAP3[45]*", SOC_3430), | |
2716 | SOC_FLAG("OMAP3[67]*", SOC_3630), | |
2717 | SOC_FLAG("OMAP443*", SOC_4430), | |
2718 | SOC_FLAG("OMAP446*", SOC_4460), | |
2719 | SOC_FLAG("OMAP447*", SOC_4470), | |
2720 | SOC_FLAG("OMAP54*", SOC_5430), | |
2721 | SOC_FLAG("AM433", SOC_AM3), | |
2722 | SOC_FLAG("AM43*", SOC_AM4), | |
2723 | SOC_FLAG("DRA7*", SOC_DRA7), | |
2724 | ||
2725 | { /* sentinel */ }, | |
2726 | }; | |
2727 | ||
2728 | /* | |
2729 | * List of SoCs variants with disabled features. By default we assume all | |
2730 | * devices in the device tree are available so no need to list those SoCs. | |
2731 | */ | |
2732 | static const struct soc_device_attribute sysc_soc_feat_match[] = { | |
2733 | /* OMAP3430/3530 and AM3517 variants with some accelerators disabled */ | |
2734 | SOC_FLAG("AM3505", DIS_SGX), | |
2735 | SOC_FLAG("OMAP3525", DIS_SGX), | |
2736 | SOC_FLAG("OMAP3515", DIS_IVA | DIS_SGX), | |
2737 | SOC_FLAG("OMAP3503", DIS_ISP | DIS_IVA | DIS_SGX), | |
2738 | ||
2739 | /* OMAP3630/DM3730 variants with some accelerators disabled */ | |
2740 | SOC_FLAG("AM3703", DIS_IVA | DIS_SGX), | |
2741 | SOC_FLAG("DM3725", DIS_SGX), | |
2742 | SOC_FLAG("OMAP3611", DIS_ISP | DIS_IVA | DIS_SGX), | |
2743 | SOC_FLAG("OMAP3615/AM3715", DIS_IVA), | |
2744 | SOC_FLAG("OMAP3621", DIS_ISP), | |
2745 | ||
2746 | { /* sentinel */ }, | |
2747 | }; | |
2748 | ||
2749 | static int sysc_add_disabled(unsigned long base) | |
2750 | { | |
2751 | struct sysc_address *disabled_module; | |
2752 | ||
2753 | disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL); | |
2754 | if (!disabled_module) | |
2755 | return -ENOMEM; | |
2756 | ||
2757 | disabled_module->base = base; | |
2758 | ||
2759 | mutex_lock(&sysc_soc->list_lock); | |
2760 | list_add(&disabled_module->node, &sysc_soc->disabled_modules); | |
2761 | mutex_unlock(&sysc_soc->list_lock); | |
2762 | ||
2763 | return 0; | |
2764 | } | |
2765 | ||
2766 | /* | |
2767 | * One time init to detect the booted SoC and disable unavailable features. | |
2768 | * Note that we initialize static data shared across all ti-sysc instances | |
2769 | * so ddata is only used for SoC type. This can be called from module_init | |
2770 | * once we no longer need to rely on platform data. | |
2771 | */ | |
2772 | static int sysc_init_soc(struct sysc *ddata) | |
2773 | { | |
2774 | const struct soc_device_attribute *match; | |
2775 | struct ti_sysc_platform_data *pdata; | |
2776 | unsigned long features = 0; | |
2777 | ||
2778 | if (sysc_soc) | |
2779 | return 0; | |
2780 | ||
2781 | sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL); | |
2782 | if (!sysc_soc) | |
2783 | return -ENOMEM; | |
2784 | ||
2785 | mutex_init(&sysc_soc->list_lock); | |
2786 | INIT_LIST_HEAD(&sysc_soc->disabled_modules); | |
2787 | sysc_soc->general_purpose = true; | |
2788 | ||
2789 | pdata = dev_get_platdata(ddata->dev); | |
2790 | if (pdata && pdata->soc_type_gp) | |
2791 | sysc_soc->general_purpose = pdata->soc_type_gp(); | |
2792 | ||
2793 | match = soc_device_match(sysc_soc_match); | |
2794 | if (match && match->data) | |
2795 | sysc_soc->soc = (int)match->data; | |
2796 | ||
2797 | /* Ignore devices that are not available on HS and EMU SoCs */ | |
2798 | if (!sysc_soc->general_purpose) { | |
2799 | switch (sysc_soc->soc) { | |
2800 | case SOC_3430 ... SOC_3630: | |
2801 | sysc_add_disabled(0x48304000); /* timer12 */ | |
2802 | break; | |
2803 | default: | |
2804 | break; | |
2805 | }; | |
2806 | } | |
2807 | ||
2808 | match = soc_device_match(sysc_soc_feat_match); | |
2809 | if (!match) | |
2810 | return 0; | |
2811 | ||
2812 | if (match->data) | |
2813 | features = (unsigned long)match->data; | |
2814 | ||
2815 | /* | |
2816 | * Add disabled devices to the list based on the module base. | |
2817 | * Note that this must be done before we attempt to access the | |
2818 | * device and have module revision checks working. | |
2819 | */ | |
2820 | if (features & DIS_ISP) | |
2821 | sysc_add_disabled(0x480bd400); | |
2822 | if (features & DIS_IVA) | |
2823 | sysc_add_disabled(0x5d000000); | |
2824 | if (features & DIS_SGX) | |
2825 | sysc_add_disabled(0x50000000); | |
2826 | ||
2827 | return 0; | |
2828 | } | |
2829 | ||
2830 | static void sysc_cleanup_soc(void) | |
2831 | { | |
2832 | struct sysc_address *disabled_module; | |
2833 | struct list_head *pos, *tmp; | |
2834 | ||
2835 | if (!sysc_soc) | |
2836 | return; | |
2837 | ||
2838 | mutex_lock(&sysc_soc->list_lock); | |
2839 | list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) { | |
2840 | disabled_module = list_entry(pos, struct sysc_address, node); | |
2841 | list_del(pos); | |
2842 | kfree(disabled_module); | |
2843 | } | |
2844 | mutex_unlock(&sysc_soc->list_lock); | |
2845 | } | |
2846 | ||
2847 | static int sysc_check_disabled_devices(struct sysc *ddata) | |
2848 | { | |
2849 | struct sysc_address *disabled_module; | |
2850 | struct list_head *pos; | |
2851 | int error = 0; | |
2852 | ||
2853 | mutex_lock(&sysc_soc->list_lock); | |
2854 | list_for_each(pos, &sysc_soc->disabled_modules) { | |
2855 | disabled_module = list_entry(pos, struct sysc_address, node); | |
2856 | if (ddata->module_pa == disabled_module->base) { | |
2857 | dev_dbg(ddata->dev, "module disabled for this SoC\n"); | |
2858 | error = -ENODEV; | |
2859 | break; | |
2860 | } | |
2861 | } | |
2862 | mutex_unlock(&sysc_soc->list_lock); | |
2863 | ||
2864 | return error; | |
2865 | } | |
2866 | ||
2867 | static const struct of_device_id sysc_match_table[] = { | |
2868 | { .compatible = "simple-bus", }, | |
2869 | { /* sentinel */ }, | |
2870 | }; | |
2871 | ||
2872 | static int sysc_probe(struct platform_device *pdev) | |
2873 | { | |
2874 | struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev); | |
2875 | struct sysc *ddata; | |
2876 | int error; | |
2877 | ||
2878 | ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); | |
2879 | if (!ddata) | |
2880 | return -ENOMEM; | |
2881 | ||
2882 | ddata->dev = &pdev->dev; | |
2883 | platform_set_drvdata(pdev, ddata); | |
2884 | ||
2885 | error = sysc_init_soc(ddata); | |
2886 | if (error) | |
2887 | return error; | |
2888 | ||
2889 | error = sysc_init_match(ddata); | |
2890 | if (error) | |
2891 | return error; | |
2892 | ||
2893 | error = sysc_init_dts_quirks(ddata); | |
2894 | if (error) | |
2895 | return error; | |
2896 | ||
2897 | error = sysc_map_and_check_registers(ddata); | |
2898 | if (error) | |
2899 | return error; | |
2900 | ||
2901 | error = sysc_init_sysc_mask(ddata); | |
2902 | if (error) | |
2903 | return error; | |
2904 | ||
2905 | error = sysc_init_idlemodes(ddata); | |
2906 | if (error) | |
2907 | return error; | |
2908 | ||
2909 | error = sysc_init_syss_mask(ddata); | |
2910 | if (error) | |
2911 | return error; | |
2912 | ||
2913 | error = sysc_init_pdata(ddata); | |
2914 | if (error) | |
2915 | return error; | |
2916 | ||
2917 | sysc_init_early_quirks(ddata); | |
2918 | ||
2919 | error = sysc_check_disabled_devices(ddata); | |
2920 | if (error) | |
2921 | return error; | |
2922 | ||
2923 | error = sysc_get_clocks(ddata); | |
2924 | if (error) | |
2925 | return error; | |
2926 | ||
2927 | error = sysc_init_resets(ddata); | |
2928 | if (error) | |
2929 | goto unprepare; | |
2930 | ||
2931 | error = sysc_init_module(ddata); | |
2932 | if (error) | |
2933 | goto unprepare; | |
2934 | ||
2935 | pm_runtime_enable(ddata->dev); | |
2936 | error = pm_runtime_get_sync(ddata->dev); | |
2937 | if (error < 0) { | |
2938 | pm_runtime_put_noidle(ddata->dev); | |
2939 | pm_runtime_disable(ddata->dev); | |
2940 | goto unprepare; | |
2941 | } | |
2942 | ||
2943 | /* Balance use counts as PM runtime should have enabled these all */ | |
2944 | if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) | |
2945 | reset_control_assert(ddata->rsts); | |
2946 | ||
2947 | if (!(ddata->cfg.quirks & | |
2948 | (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) { | |
2949 | sysc_disable_main_clocks(ddata); | |
2950 | sysc_disable_opt_clocks(ddata); | |
2951 | sysc_clkdm_allow_idle(ddata); | |
2952 | } | |
2953 | ||
2954 | sysc_show_registers(ddata); | |
2955 | ||
2956 | ddata->dev->type = &sysc_device_type; | |
2957 | error = of_platform_populate(ddata->dev->of_node, sysc_match_table, | |
2958 | pdata ? pdata->auxdata : NULL, | |
2959 | ddata->dev); | |
2960 | if (error) | |
2961 | goto err; | |
2962 | ||
2963 | INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle); | |
2964 | ||
2965 | /* At least earlycon won't survive without deferred idle */ | |
2966 | if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | | |
2967 | SYSC_QUIRK_NO_IDLE_ON_INIT | | |
2968 | SYSC_QUIRK_NO_RESET_ON_INIT)) { | |
2969 | schedule_delayed_work(&ddata->idle_work, 3000); | |
2970 | } else { | |
2971 | pm_runtime_put(&pdev->dev); | |
2972 | } | |
2973 | ||
2974 | return 0; | |
2975 | ||
2976 | err: | |
2977 | pm_runtime_put_sync(&pdev->dev); | |
2978 | pm_runtime_disable(&pdev->dev); | |
2979 | unprepare: | |
2980 | sysc_unprepare(ddata); | |
2981 | ||
2982 | return error; | |
2983 | } | |
2984 | ||
2985 | static int sysc_remove(struct platform_device *pdev) | |
2986 | { | |
2987 | struct sysc *ddata = platform_get_drvdata(pdev); | |
2988 | int error; | |
2989 | ||
2990 | cancel_delayed_work_sync(&ddata->idle_work); | |
2991 | ||
2992 | error = pm_runtime_get_sync(ddata->dev); | |
2993 | if (error < 0) { | |
2994 | pm_runtime_put_noidle(ddata->dev); | |
2995 | pm_runtime_disable(ddata->dev); | |
2996 | goto unprepare; | |
2997 | } | |
2998 | ||
2999 | of_platform_depopulate(&pdev->dev); | |
3000 | ||
3001 | pm_runtime_put_sync(&pdev->dev); | |
3002 | pm_runtime_disable(&pdev->dev); | |
3003 | reset_control_assert(ddata->rsts); | |
3004 | ||
3005 | unprepare: | |
3006 | sysc_unprepare(ddata); | |
3007 | ||
3008 | return 0; | |
3009 | } | |
3010 | ||
3011 | static const struct of_device_id sysc_match[] = { | |
3012 | { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, }, | |
3013 | { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, }, | |
3014 | { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, }, | |
3015 | { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, }, | |
3016 | { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, }, | |
3017 | { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, }, | |
3018 | { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, }, | |
3019 | { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, }, | |
3020 | { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, }, | |
3021 | { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, }, | |
3022 | { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, }, | |
3023 | { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, }, | |
3024 | { .compatible = "ti,sysc-usb-host-fs", | |
3025 | .data = &sysc_omap4_usb_host_fs, }, | |
3026 | { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, }, | |
3027 | { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, }, | |
3028 | { }, | |
3029 | }; | |
3030 | MODULE_DEVICE_TABLE(of, sysc_match); | |
3031 | ||
3032 | static struct platform_driver sysc_driver = { | |
3033 | .probe = sysc_probe, | |
3034 | .remove = sysc_remove, | |
3035 | .driver = { | |
3036 | .name = "ti-sysc", | |
3037 | .of_match_table = sysc_match, | |
3038 | .pm = &sysc_pm_ops, | |
3039 | }, | |
3040 | }; | |
3041 | ||
3042 | static int __init sysc_init(void) | |
3043 | { | |
3044 | bus_register_notifier(&platform_bus_type, &sysc_nb); | |
3045 | ||
3046 | return platform_driver_register(&sysc_driver); | |
3047 | } | |
3048 | module_init(sysc_init); | |
3049 | ||
3050 | static void __exit sysc_exit(void) | |
3051 | { | |
3052 | bus_unregister_notifier(&platform_bus_type, &sysc_nb); | |
3053 | platform_driver_unregister(&sysc_driver); | |
3054 | sysc_cleanup_soc(); | |
3055 | } | |
3056 | module_exit(sysc_exit); | |
3057 | ||
3058 | MODULE_DESCRIPTION("TI sysc interconnect target driver"); | |
3059 | MODULE_LICENSE("GPL v2"); |