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1 | /* | |
2 | * Copyright 2013 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * clock driver for Freescale QorIQ SoCs. | |
9 | */ | |
10 | ||
11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
12 | ||
13 | #include <linux/clk-provider.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/of_address.h> | |
18 | #include <linux/of_platform.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/slab.h> | |
21 | ||
22 | struct cmux_clk { | |
23 | struct clk_hw hw; | |
24 | void __iomem *reg; | |
25 | unsigned int clk_per_pll; | |
26 | u32 flags; | |
27 | }; | |
28 | ||
29 | #define PLL_KILL BIT(31) | |
30 | #define CLKSEL_SHIFT 27 | |
31 | #define CLKSEL_ADJUST BIT(0) | |
32 | #define to_cmux_clk(p) container_of(p, struct cmux_clk, hw) | |
33 | ||
34 | static int cmux_set_parent(struct clk_hw *hw, u8 idx) | |
35 | { | |
36 | struct cmux_clk *clk = to_cmux_clk(hw); | |
37 | u32 clksel; | |
38 | ||
39 | clksel = ((idx / clk->clk_per_pll) << 2) + idx % clk->clk_per_pll; | |
40 | if (clk->flags & CLKSEL_ADJUST) | |
41 | clksel += 8; | |
42 | clksel = (clksel & 0xf) << CLKSEL_SHIFT; | |
43 | iowrite32be(clksel, clk->reg); | |
44 | ||
45 | return 0; | |
46 | } | |
47 | ||
48 | static u8 cmux_get_parent(struct clk_hw *hw) | |
49 | { | |
50 | struct cmux_clk *clk = to_cmux_clk(hw); | |
51 | u32 clksel; | |
52 | ||
53 | clksel = ioread32be(clk->reg); | |
54 | clksel = (clksel >> CLKSEL_SHIFT) & 0xf; | |
55 | if (clk->flags & CLKSEL_ADJUST) | |
56 | clksel -= 8; | |
57 | clksel = (clksel >> 2) * clk->clk_per_pll + clksel % 4; | |
58 | ||
59 | return clksel; | |
60 | } | |
61 | ||
62 | static const struct clk_ops cmux_ops = { | |
63 | .get_parent = cmux_get_parent, | |
64 | .set_parent = cmux_set_parent, | |
65 | }; | |
66 | ||
67 | static void __init core_mux_init(struct device_node *np) | |
68 | { | |
69 | struct clk *clk; | |
70 | struct clk_init_data init; | |
71 | struct cmux_clk *cmux_clk; | |
72 | struct device_node *node; | |
73 | int rc, count, i; | |
74 | u32 offset; | |
75 | const char *clk_name; | |
76 | const char **parent_names; | |
77 | struct of_phandle_args clkspec; | |
78 | ||
79 | rc = of_property_read_u32(np, "reg", &offset); | |
80 | if (rc) { | |
81 | pr_err("%s: could not get reg property\n", np->name); | |
82 | return; | |
83 | } | |
84 | ||
85 | /* get the input clock source count */ | |
86 | count = of_property_count_strings(np, "clock-names"); | |
87 | if (count < 0) { | |
88 | pr_err("%s: get clock count error\n", np->name); | |
89 | return; | |
90 | } | |
91 | parent_names = kcalloc(count, sizeof(char *), GFP_KERNEL); | |
92 | if (!parent_names) | |
93 | return; | |
94 | ||
95 | for (i = 0; i < count; i++) | |
96 | parent_names[i] = of_clk_get_parent_name(np, i); | |
97 | ||
98 | cmux_clk = kzalloc(sizeof(*cmux_clk), GFP_KERNEL); | |
99 | if (!cmux_clk) | |
100 | goto err_name; | |
101 | ||
102 | cmux_clk->reg = of_iomap(np, 0); | |
103 | if (!cmux_clk->reg) { | |
104 | pr_err("%s: could not map register\n", __func__); | |
105 | goto err_clk; | |
106 | } | |
107 | ||
108 | rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", 0, | |
109 | &clkspec); | |
110 | if (rc) { | |
111 | pr_err("%s: parse clock node error\n", __func__); | |
112 | goto err_clk; | |
113 | } | |
114 | ||
115 | cmux_clk->clk_per_pll = of_property_count_strings(clkspec.np, | |
116 | "clock-output-names"); | |
117 | of_node_put(clkspec.np); | |
118 | ||
119 | node = of_find_compatible_node(NULL, NULL, "fsl,p4080-clockgen"); | |
120 | if (node && (offset >= 0x80)) | |
121 | cmux_clk->flags = CLKSEL_ADJUST; | |
122 | ||
123 | rc = of_property_read_string_index(np, "clock-output-names", | |
124 | 0, &clk_name); | |
125 | if (rc) { | |
126 | pr_err("%s: read clock names error\n", np->name); | |
127 | goto err_clk; | |
128 | } | |
129 | ||
130 | init.name = clk_name; | |
131 | init.ops = &cmux_ops; | |
132 | init.parent_names = parent_names; | |
133 | init.num_parents = count; | |
134 | init.flags = 0; | |
135 | cmux_clk->hw.init = &init; | |
136 | ||
137 | clk = clk_register(NULL, &cmux_clk->hw); | |
138 | if (IS_ERR(clk)) { | |
139 | pr_err("%s: could not register clock\n", clk_name); | |
140 | goto err_clk; | |
141 | } | |
142 | ||
143 | rc = of_clk_add_provider(np, of_clk_src_simple_get, clk); | |
144 | if (rc) { | |
145 | pr_err("Could not register clock provider for node:%s\n", | |
146 | np->name); | |
147 | goto err_clk; | |
148 | } | |
149 | goto err_name; | |
150 | ||
151 | err_clk: | |
152 | kfree(cmux_clk); | |
153 | err_name: | |
154 | /* free *_names because they are reallocated when registered */ | |
155 | kfree(parent_names); | |
156 | } | |
157 | ||
158 | static void __init core_pll_init(struct device_node *np) | |
159 | { | |
160 | u32 mult; | |
161 | int i, rc, count; | |
162 | const char *clk_name, *parent_name; | |
163 | struct clk_onecell_data *onecell_data; | |
164 | struct clk **subclks; | |
165 | void __iomem *base; | |
166 | ||
167 | base = of_iomap(np, 0); | |
168 | if (!base) { | |
169 | pr_err("iomap error\n"); | |
170 | return; | |
171 | } | |
172 | ||
173 | /* get the multiple of PLL */ | |
174 | mult = ioread32be(base); | |
175 | ||
176 | /* check if this PLL is disabled */ | |
177 | if (mult & PLL_KILL) { | |
178 | pr_debug("PLL:%s is disabled\n", np->name); | |
179 | goto err_map; | |
180 | } | |
181 | mult = (mult >> 1) & 0x3f; | |
182 | ||
183 | parent_name = of_clk_get_parent_name(np, 0); | |
184 | if (!parent_name) { | |
185 | pr_err("PLL: %s must have a parent\n", np->name); | |
186 | goto err_map; | |
187 | } | |
188 | ||
189 | count = of_property_count_strings(np, "clock-output-names"); | |
190 | if (count < 0 || count > 4) { | |
191 | pr_err("%s: clock is not supported\n", np->name); | |
192 | goto err_map; | |
193 | } | |
194 | ||
195 | subclks = kcalloc(count, sizeof(struct clk *), GFP_KERNEL); | |
196 | if (!subclks) | |
197 | goto err_map; | |
198 | ||
199 | onecell_data = kmalloc(sizeof(*onecell_data), GFP_KERNEL); | |
200 | if (!onecell_data) | |
201 | goto err_clks; | |
202 | ||
203 | for (i = 0; i < count; i++) { | |
204 | rc = of_property_read_string_index(np, "clock-output-names", | |
205 | i, &clk_name); | |
206 | if (rc) { | |
207 | pr_err("%s: could not get clock names\n", np->name); | |
208 | goto err_cell; | |
209 | } | |
210 | ||
211 | /* | |
212 | * when count == 4, there are 4 output clocks: | |
213 | * /1, /2, /3, /4 respectively | |
214 | * when count < 4, there are at least 2 output clocks: | |
215 | * /1, /2, (/4, if count == 3) respectively. | |
216 | */ | |
217 | if (count == 4) | |
218 | subclks[i] = clk_register_fixed_factor(NULL, clk_name, | |
219 | parent_name, 0, mult, 1 + i); | |
220 | else | |
221 | ||
222 | subclks[i] = clk_register_fixed_factor(NULL, clk_name, | |
223 | parent_name, 0, mult, 1 << i); | |
224 | ||
225 | if (IS_ERR(subclks[i])) { | |
226 | pr_err("%s: could not register clock\n", clk_name); | |
227 | goto err_cell; | |
228 | } | |
229 | } | |
230 | ||
231 | onecell_data->clks = subclks; | |
232 | onecell_data->clk_num = count; | |
233 | ||
234 | rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data); | |
235 | if (rc) { | |
236 | pr_err("Could not register clk provider for node:%s\n", | |
237 | np->name); | |
238 | goto err_cell; | |
239 | } | |
240 | ||
241 | iounmap(base); | |
242 | return; | |
243 | err_cell: | |
244 | kfree(onecell_data); | |
245 | err_clks: | |
246 | kfree(subclks); | |
247 | err_map: | |
248 | iounmap(base); | |
249 | } | |
250 | ||
251 | static void __init sysclk_init(struct device_node *node) | |
252 | { | |
253 | struct clk *clk; | |
254 | const char *clk_name = node->name; | |
255 | struct device_node *np = of_get_parent(node); | |
256 | u32 rate; | |
257 | ||
258 | if (!np) { | |
259 | pr_err("could not get parent node\n"); | |
260 | return; | |
261 | } | |
262 | ||
263 | if (of_property_read_u32(np, "clock-frequency", &rate)) { | |
264 | of_node_put(node); | |
265 | return; | |
266 | } | |
267 | ||
268 | of_property_read_string(np, "clock-output-names", &clk_name); | |
269 | ||
270 | clk = clk_register_fixed_rate(NULL, clk_name, NULL, CLK_IS_ROOT, rate); | |
271 | if (!IS_ERR(clk)) | |
272 | of_clk_add_provider(np, of_clk_src_simple_get, clk); | |
273 | } | |
274 | ||
275 | static void __init pltfrm_pll_init(struct device_node *np) | |
276 | { | |
277 | void __iomem *base; | |
278 | uint32_t mult; | |
279 | const char *parent_name, *clk_name; | |
280 | int i, _errno; | |
281 | struct clk_onecell_data *cod; | |
282 | ||
283 | base = of_iomap(np, 0); | |
284 | if (!base) { | |
285 | pr_err("%s(): %s: of_iomap() failed\n", __func__, np->name); | |
286 | return; | |
287 | } | |
288 | ||
289 | /* Get the multiple of PLL */ | |
290 | mult = ioread32be(base); | |
291 | ||
292 | iounmap(base); | |
293 | ||
294 | /* Check if this PLL is disabled */ | |
295 | if (mult & PLL_KILL) { | |
296 | pr_debug("%s(): %s: Disabled\n", __func__, np->name); | |
297 | return; | |
298 | } | |
299 | mult = (mult & GENMASK(6, 1)) >> 1; | |
300 | ||
301 | parent_name = of_clk_get_parent_name(np, 0); | |
302 | if (!parent_name) { | |
303 | pr_err("%s(): %s: of_clk_get_parent_name() failed\n", | |
304 | __func__, np->name); | |
305 | return; | |
306 | } | |
307 | ||
308 | i = of_property_count_strings(np, "clock-output-names"); | |
309 | if (i < 0) { | |
310 | pr_err("%s(): %s: of_property_count_strings(clock-output-names) = %d\n", | |
311 | __func__, np->name, i); | |
312 | return; | |
313 | } | |
314 | ||
315 | cod = kmalloc(sizeof(*cod) + i * sizeof(struct clk *), GFP_KERNEL); | |
316 | if (!cod) | |
317 | return; | |
318 | cod->clks = (struct clk **)(cod + 1); | |
319 | cod->clk_num = i; | |
320 | ||
321 | for (i = 0; i < cod->clk_num; i++) { | |
322 | _errno = of_property_read_string_index(np, "clock-output-names", | |
323 | i, &clk_name); | |
324 | if (_errno < 0) { | |
325 | pr_err("%s(): %s: of_property_read_string_index(clock-output-names) = %d\n", | |
326 | __func__, np->name, _errno); | |
327 | goto return_clk_unregister; | |
328 | } | |
329 | ||
330 | cod->clks[i] = clk_register_fixed_factor(NULL, clk_name, | |
331 | parent_name, 0, mult, 1 + i); | |
332 | if (IS_ERR(cod->clks[i])) { | |
333 | pr_err("%s(): %s: clk_register_fixed_factor(%s) = %ld\n", | |
334 | __func__, np->name, | |
335 | clk_name, PTR_ERR(cod->clks[i])); | |
336 | goto return_clk_unregister; | |
337 | } | |
338 | } | |
339 | ||
340 | _errno = of_clk_add_provider(np, of_clk_src_onecell_get, cod); | |
341 | if (_errno < 0) { | |
342 | pr_err("%s(): %s: of_clk_add_provider() = %d\n", | |
343 | __func__, np->name, _errno); | |
344 | goto return_clk_unregister; | |
345 | } | |
346 | ||
347 | return; | |
348 | ||
349 | return_clk_unregister: | |
350 | while (--i >= 0) | |
351 | clk_unregister(cod->clks[i]); | |
352 | kfree(cod); | |
353 | } | |
354 | ||
355 | CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init); | |
356 | CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init); | |
357 | CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init); | |
358 | CLK_OF_DECLARE(qoriq_core_pll_2, "fsl,qoriq-core-pll-2.0", core_pll_init); | |
359 | CLK_OF_DECLARE(qoriq_core_mux_1, "fsl,qoriq-core-mux-1.0", core_mux_init); | |
360 | CLK_OF_DECLARE(qoriq_core_mux_2, "fsl,qoriq-core-mux-2.0", core_mux_init); | |
361 | CLK_OF_DECLARE(qoriq_pltfrm_pll_1, "fsl,qoriq-platform-pll-1.0", pltfrm_pll_init); | |
362 | CLK_OF_DECLARE(qoriq_pltfrm_pll_2, "fsl,qoriq-platform-pll-2.0", pltfrm_pll_init); |