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1 | /* | |
2 | * linux/arch/arm/plat-mxc/time.c | |
3 | * | |
4 | * Copyright (C) 2000-2001 Deep Blue Solutions | |
5 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) | |
6 | * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com) | |
7 | * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version 2 | |
12 | * of the License, or (at your option) any later version. | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
21 | * MA 02110-1301, USA. | |
22 | */ | |
23 | ||
24 | #include <linux/interrupt.h> | |
25 | #include <linux/irq.h> | |
26 | #include <linux/clockchips.h> | |
27 | #include <linux/clk.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/err.h> | |
30 | #include <linux/sched_clock.h> | |
31 | #include <linux/slab.h> | |
32 | #include <linux/of.h> | |
33 | #include <linux/of_address.h> | |
34 | #include <linux/of_irq.h> | |
35 | #include <soc/imx/timer.h> | |
36 | ||
37 | /* | |
38 | * There are 4 versions of the timer hardware on Freescale MXC hardware. | |
39 | * - MX1/MXL | |
40 | * - MX21, MX27. | |
41 | * - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0) | |
42 | * - MX6DL, MX6SX, MX6Q(rev1.1+) | |
43 | */ | |
44 | ||
45 | /* defines common for all i.MX */ | |
46 | #define MXC_TCTL 0x00 | |
47 | #define MXC_TCTL_TEN (1 << 0) /* Enable module */ | |
48 | #define MXC_TPRER 0x04 | |
49 | ||
50 | /* MX1, MX21, MX27 */ | |
51 | #define MX1_2_TCTL_CLK_PCLK1 (1 << 1) | |
52 | #define MX1_2_TCTL_IRQEN (1 << 4) | |
53 | #define MX1_2_TCTL_FRR (1 << 8) | |
54 | #define MX1_2_TCMP 0x08 | |
55 | #define MX1_2_TCN 0x10 | |
56 | #define MX1_2_TSTAT 0x14 | |
57 | ||
58 | /* MX21, MX27 */ | |
59 | #define MX2_TSTAT_CAPT (1 << 1) | |
60 | #define MX2_TSTAT_COMP (1 << 0) | |
61 | ||
62 | /* MX31, MX35, MX25, MX5, MX6 */ | |
63 | #define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */ | |
64 | #define V2_TCTL_CLK_IPG (1 << 6) | |
65 | #define V2_TCTL_CLK_PER (2 << 6) | |
66 | #define V2_TCTL_CLK_OSC_DIV8 (5 << 6) | |
67 | #define V2_TCTL_FRR (1 << 9) | |
68 | #define V2_TCTL_24MEN (1 << 10) | |
69 | #define V2_TPRER_PRE24M 12 | |
70 | #define V2_IR 0x0c | |
71 | #define V2_TSTAT 0x08 | |
72 | #define V2_TSTAT_OF1 (1 << 0) | |
73 | #define V2_TCN 0x24 | |
74 | #define V2_TCMP 0x10 | |
75 | ||
76 | #define V2_TIMER_RATE_OSC_DIV8 3000000 | |
77 | ||
78 | struct imx_timer { | |
79 | enum imx_gpt_type type; | |
80 | void __iomem *base; | |
81 | int irq; | |
82 | struct clk *clk_per; | |
83 | struct clk *clk_ipg; | |
84 | const struct imx_gpt_data *gpt; | |
85 | struct clock_event_device ced; | |
86 | struct irqaction act; | |
87 | }; | |
88 | ||
89 | struct imx_gpt_data { | |
90 | int reg_tstat; | |
91 | int reg_tcn; | |
92 | int reg_tcmp; | |
93 | void (*gpt_setup_tctl)(struct imx_timer *imxtm); | |
94 | void (*gpt_irq_enable)(struct imx_timer *imxtm); | |
95 | void (*gpt_irq_disable)(struct imx_timer *imxtm); | |
96 | void (*gpt_irq_acknowledge)(struct imx_timer *imxtm); | |
97 | int (*set_next_event)(unsigned long evt, | |
98 | struct clock_event_device *ced); | |
99 | }; | |
100 | ||
101 | static inline struct imx_timer *to_imx_timer(struct clock_event_device *ced) | |
102 | { | |
103 | return container_of(ced, struct imx_timer, ced); | |
104 | } | |
105 | ||
106 | static void imx1_gpt_irq_disable(struct imx_timer *imxtm) | |
107 | { | |
108 | unsigned int tmp; | |
109 | ||
110 | tmp = readl_relaxed(imxtm->base + MXC_TCTL); | |
111 | writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL); | |
112 | } | |
113 | #define imx21_gpt_irq_disable imx1_gpt_irq_disable | |
114 | ||
115 | static void imx31_gpt_irq_disable(struct imx_timer *imxtm) | |
116 | { | |
117 | writel_relaxed(0, imxtm->base + V2_IR); | |
118 | } | |
119 | #define imx6dl_gpt_irq_disable imx31_gpt_irq_disable | |
120 | ||
121 | static void imx1_gpt_irq_enable(struct imx_timer *imxtm) | |
122 | { | |
123 | unsigned int tmp; | |
124 | ||
125 | tmp = readl_relaxed(imxtm->base + MXC_TCTL); | |
126 | writel_relaxed(tmp | MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL); | |
127 | } | |
128 | #define imx21_gpt_irq_enable imx1_gpt_irq_enable | |
129 | ||
130 | static void imx31_gpt_irq_enable(struct imx_timer *imxtm) | |
131 | { | |
132 | writel_relaxed(1<<0, imxtm->base + V2_IR); | |
133 | } | |
134 | #define imx6dl_gpt_irq_enable imx31_gpt_irq_enable | |
135 | ||
136 | static void imx1_gpt_irq_acknowledge(struct imx_timer *imxtm) | |
137 | { | |
138 | writel_relaxed(0, imxtm->base + MX1_2_TSTAT); | |
139 | } | |
140 | ||
141 | static void imx21_gpt_irq_acknowledge(struct imx_timer *imxtm) | |
142 | { | |
143 | writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, | |
144 | imxtm->base + MX1_2_TSTAT); | |
145 | } | |
146 | ||
147 | static void imx31_gpt_irq_acknowledge(struct imx_timer *imxtm) | |
148 | { | |
149 | writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT); | |
150 | } | |
151 | #define imx6dl_gpt_irq_acknowledge imx31_gpt_irq_acknowledge | |
152 | ||
153 | static void __iomem *sched_clock_reg; | |
154 | ||
155 | static u64 notrace mxc_read_sched_clock(void) | |
156 | { | |
157 | return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0; | |
158 | } | |
159 | ||
160 | static struct delay_timer imx_delay_timer; | |
161 | ||
162 | static unsigned long imx_read_current_timer(void) | |
163 | { | |
164 | return readl_relaxed(sched_clock_reg); | |
165 | } | |
166 | ||
167 | static int __init mxc_clocksource_init(struct imx_timer *imxtm) | |
168 | { | |
169 | unsigned int c = clk_get_rate(imxtm->clk_per); | |
170 | void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn; | |
171 | ||
172 | imx_delay_timer.read_current_timer = &imx_read_current_timer; | |
173 | imx_delay_timer.freq = c; | |
174 | register_current_timer_delay(&imx_delay_timer); | |
175 | ||
176 | sched_clock_reg = reg; | |
177 | ||
178 | sched_clock_register(mxc_read_sched_clock, 32, c); | |
179 | return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32, | |
180 | clocksource_mmio_readl_up); | |
181 | } | |
182 | ||
183 | /* clock event */ | |
184 | ||
185 | static int mx1_2_set_next_event(unsigned long evt, | |
186 | struct clock_event_device *ced) | |
187 | { | |
188 | struct imx_timer *imxtm = to_imx_timer(ced); | |
189 | unsigned long tcmp; | |
190 | ||
191 | tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt; | |
192 | ||
193 | writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP); | |
194 | ||
195 | return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ? | |
196 | -ETIME : 0; | |
197 | } | |
198 | ||
199 | static int v2_set_next_event(unsigned long evt, | |
200 | struct clock_event_device *ced) | |
201 | { | |
202 | struct imx_timer *imxtm = to_imx_timer(ced); | |
203 | unsigned long tcmp; | |
204 | ||
205 | tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt; | |
206 | ||
207 | writel_relaxed(tcmp, imxtm->base + V2_TCMP); | |
208 | ||
209 | return evt < 0x7fffffff && | |
210 | (int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ? | |
211 | -ETIME : 0; | |
212 | } | |
213 | ||
214 | static int mxc_shutdown(struct clock_event_device *ced) | |
215 | { | |
216 | struct imx_timer *imxtm = to_imx_timer(ced); | |
217 | unsigned long flags; | |
218 | u32 tcn; | |
219 | ||
220 | /* | |
221 | * The timer interrupt generation is disabled at least | |
222 | * for enough time to call mxc_set_next_event() | |
223 | */ | |
224 | local_irq_save(flags); | |
225 | ||
226 | /* Disable interrupt in GPT module */ | |
227 | imxtm->gpt->gpt_irq_disable(imxtm); | |
228 | ||
229 | tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn); | |
230 | /* Set event time into far-far future */ | |
231 | writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp); | |
232 | ||
233 | /* Clear pending interrupt */ | |
234 | imxtm->gpt->gpt_irq_acknowledge(imxtm); | |
235 | ||
236 | #ifdef DEBUG | |
237 | printk(KERN_INFO "%s: changing mode\n", __func__); | |
238 | #endif /* DEBUG */ | |
239 | ||
240 | local_irq_restore(flags); | |
241 | ||
242 | return 0; | |
243 | } | |
244 | ||
245 | static int mxc_set_oneshot(struct clock_event_device *ced) | |
246 | { | |
247 | struct imx_timer *imxtm = to_imx_timer(ced); | |
248 | unsigned long flags; | |
249 | ||
250 | /* | |
251 | * The timer interrupt generation is disabled at least | |
252 | * for enough time to call mxc_set_next_event() | |
253 | */ | |
254 | local_irq_save(flags); | |
255 | ||
256 | /* Disable interrupt in GPT module */ | |
257 | imxtm->gpt->gpt_irq_disable(imxtm); | |
258 | ||
259 | if (!clockevent_state_oneshot(ced)) { | |
260 | u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn); | |
261 | /* Set event time into far-far future */ | |
262 | writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp); | |
263 | ||
264 | /* Clear pending interrupt */ | |
265 | imxtm->gpt->gpt_irq_acknowledge(imxtm); | |
266 | } | |
267 | ||
268 | #ifdef DEBUG | |
269 | printk(KERN_INFO "%s: changing mode\n", __func__); | |
270 | #endif /* DEBUG */ | |
271 | ||
272 | /* | |
273 | * Do not put overhead of interrupt enable/disable into | |
274 | * mxc_set_next_event(), the core has about 4 minutes | |
275 | * to call mxc_set_next_event() or shutdown clock after | |
276 | * mode switching | |
277 | */ | |
278 | imxtm->gpt->gpt_irq_enable(imxtm); | |
279 | local_irq_restore(flags); | |
280 | ||
281 | return 0; | |
282 | } | |
283 | ||
284 | /* | |
285 | * IRQ handler for the timer | |
286 | */ | |
287 | static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) | |
288 | { | |
289 | struct clock_event_device *ced = dev_id; | |
290 | struct imx_timer *imxtm = to_imx_timer(ced); | |
291 | uint32_t tstat; | |
292 | ||
293 | tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat); | |
294 | ||
295 | imxtm->gpt->gpt_irq_acknowledge(imxtm); | |
296 | ||
297 | ced->event_handler(ced); | |
298 | ||
299 | return IRQ_HANDLED; | |
300 | } | |
301 | ||
302 | static int __init mxc_clockevent_init(struct imx_timer *imxtm) | |
303 | { | |
304 | struct clock_event_device *ced = &imxtm->ced; | |
305 | struct irqaction *act = &imxtm->act; | |
306 | ||
307 | ced->name = "mxc_timer1"; | |
308 | ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ; | |
309 | ced->set_state_shutdown = mxc_shutdown; | |
310 | ced->set_state_oneshot = mxc_set_oneshot; | |
311 | ced->tick_resume = mxc_shutdown; | |
312 | ced->set_next_event = imxtm->gpt->set_next_event; | |
313 | ced->rating = 200; | |
314 | ced->cpumask = cpumask_of(0); | |
315 | ced->irq = imxtm->irq; | |
316 | clockevents_config_and_register(ced, clk_get_rate(imxtm->clk_per), | |
317 | 0xff, 0xfffffffe); | |
318 | ||
319 | act->name = "i.MX Timer Tick"; | |
320 | act->flags = IRQF_TIMER | IRQF_IRQPOLL; | |
321 | act->handler = mxc_timer_interrupt; | |
322 | act->dev_id = ced; | |
323 | ||
324 | return setup_irq(imxtm->irq, act); | |
325 | } | |
326 | ||
327 | static void imx1_gpt_setup_tctl(struct imx_timer *imxtm) | |
328 | { | |
329 | u32 tctl_val; | |
330 | ||
331 | tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; | |
332 | writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); | |
333 | } | |
334 | #define imx21_gpt_setup_tctl imx1_gpt_setup_tctl | |
335 | ||
336 | static void imx31_gpt_setup_tctl(struct imx_timer *imxtm) | |
337 | { | |
338 | u32 tctl_val; | |
339 | ||
340 | tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; | |
341 | if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) | |
342 | tctl_val |= V2_TCTL_CLK_OSC_DIV8; | |
343 | else | |
344 | tctl_val |= V2_TCTL_CLK_PER; | |
345 | ||
346 | writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); | |
347 | } | |
348 | ||
349 | static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm) | |
350 | { | |
351 | u32 tctl_val; | |
352 | ||
353 | tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; | |
354 | if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) { | |
355 | tctl_val |= V2_TCTL_CLK_OSC_DIV8; | |
356 | /* 24 / 8 = 3 MHz */ | |
357 | writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER); | |
358 | tctl_val |= V2_TCTL_24MEN; | |
359 | } else { | |
360 | tctl_val |= V2_TCTL_CLK_PER; | |
361 | } | |
362 | ||
363 | writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); | |
364 | } | |
365 | ||
366 | static const struct imx_gpt_data imx1_gpt_data = { | |
367 | .reg_tstat = MX1_2_TSTAT, | |
368 | .reg_tcn = MX1_2_TCN, | |
369 | .reg_tcmp = MX1_2_TCMP, | |
370 | .gpt_irq_enable = imx1_gpt_irq_enable, | |
371 | .gpt_irq_disable = imx1_gpt_irq_disable, | |
372 | .gpt_irq_acknowledge = imx1_gpt_irq_acknowledge, | |
373 | .gpt_setup_tctl = imx1_gpt_setup_tctl, | |
374 | .set_next_event = mx1_2_set_next_event, | |
375 | }; | |
376 | ||
377 | static const struct imx_gpt_data imx21_gpt_data = { | |
378 | .reg_tstat = MX1_2_TSTAT, | |
379 | .reg_tcn = MX1_2_TCN, | |
380 | .reg_tcmp = MX1_2_TCMP, | |
381 | .gpt_irq_enable = imx21_gpt_irq_enable, | |
382 | .gpt_irq_disable = imx21_gpt_irq_disable, | |
383 | .gpt_irq_acknowledge = imx21_gpt_irq_acknowledge, | |
384 | .gpt_setup_tctl = imx21_gpt_setup_tctl, | |
385 | .set_next_event = mx1_2_set_next_event, | |
386 | }; | |
387 | ||
388 | static const struct imx_gpt_data imx31_gpt_data = { | |
389 | .reg_tstat = V2_TSTAT, | |
390 | .reg_tcn = V2_TCN, | |
391 | .reg_tcmp = V2_TCMP, | |
392 | .gpt_irq_enable = imx31_gpt_irq_enable, | |
393 | .gpt_irq_disable = imx31_gpt_irq_disable, | |
394 | .gpt_irq_acknowledge = imx31_gpt_irq_acknowledge, | |
395 | .gpt_setup_tctl = imx31_gpt_setup_tctl, | |
396 | .set_next_event = v2_set_next_event, | |
397 | }; | |
398 | ||
399 | static const struct imx_gpt_data imx6dl_gpt_data = { | |
400 | .reg_tstat = V2_TSTAT, | |
401 | .reg_tcn = V2_TCN, | |
402 | .reg_tcmp = V2_TCMP, | |
403 | .gpt_irq_enable = imx6dl_gpt_irq_enable, | |
404 | .gpt_irq_disable = imx6dl_gpt_irq_disable, | |
405 | .gpt_irq_acknowledge = imx6dl_gpt_irq_acknowledge, | |
406 | .gpt_setup_tctl = imx6dl_gpt_setup_tctl, | |
407 | .set_next_event = v2_set_next_event, | |
408 | }; | |
409 | ||
410 | static int __init _mxc_timer_init(struct imx_timer *imxtm) | |
411 | { | |
412 | int ret; | |
413 | ||
414 | switch (imxtm->type) { | |
415 | case GPT_TYPE_IMX1: | |
416 | imxtm->gpt = &imx1_gpt_data; | |
417 | break; | |
418 | case GPT_TYPE_IMX21: | |
419 | imxtm->gpt = &imx21_gpt_data; | |
420 | break; | |
421 | case GPT_TYPE_IMX31: | |
422 | imxtm->gpt = &imx31_gpt_data; | |
423 | break; | |
424 | case GPT_TYPE_IMX6DL: | |
425 | imxtm->gpt = &imx6dl_gpt_data; | |
426 | break; | |
427 | default: | |
428 | return -EINVAL; | |
429 | } | |
430 | ||
431 | if (IS_ERR(imxtm->clk_per)) { | |
432 | pr_err("i.MX timer: unable to get clk\n"); | |
433 | return PTR_ERR(imxtm->clk_per); | |
434 | } | |
435 | ||
436 | if (!IS_ERR(imxtm->clk_ipg)) | |
437 | clk_prepare_enable(imxtm->clk_ipg); | |
438 | ||
439 | clk_prepare_enable(imxtm->clk_per); | |
440 | ||
441 | /* | |
442 | * Initialise to a known state (all timers off, and timing reset) | |
443 | */ | |
444 | ||
445 | writel_relaxed(0, imxtm->base + MXC_TCTL); | |
446 | writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */ | |
447 | ||
448 | imxtm->gpt->gpt_setup_tctl(imxtm); | |
449 | ||
450 | /* init and register the timer to the framework */ | |
451 | ret = mxc_clocksource_init(imxtm); | |
452 | if (ret) | |
453 | return ret; | |
454 | ||
455 | return mxc_clockevent_init(imxtm); | |
456 | } | |
457 | ||
458 | void __init mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type) | |
459 | { | |
460 | struct imx_timer *imxtm; | |
461 | ||
462 | imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL); | |
463 | BUG_ON(!imxtm); | |
464 | ||
465 | imxtm->clk_per = clk_get_sys("imx-gpt.0", "per"); | |
466 | imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg"); | |
467 | ||
468 | imxtm->base = ioremap(pbase, SZ_4K); | |
469 | BUG_ON(!imxtm->base); | |
470 | ||
471 | imxtm->type = type; | |
472 | imxtm->irq = irq; | |
473 | ||
474 | _mxc_timer_init(imxtm); | |
475 | } | |
476 | ||
477 | static int __init mxc_timer_init_dt(struct device_node *np, enum imx_gpt_type type) | |
478 | { | |
479 | struct imx_timer *imxtm; | |
480 | static int initialized; | |
481 | int ret; | |
482 | ||
483 | /* Support one instance only */ | |
484 | if (initialized) | |
485 | return 0; | |
486 | ||
487 | imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL); | |
488 | if (!imxtm) | |
489 | return -ENOMEM; | |
490 | ||
491 | imxtm->base = of_iomap(np, 0); | |
492 | if (!imxtm->base) | |
493 | return -ENXIO; | |
494 | ||
495 | imxtm->irq = irq_of_parse_and_map(np, 0); | |
496 | if (imxtm->irq <= 0) | |
497 | return -EINVAL; | |
498 | ||
499 | imxtm->clk_ipg = of_clk_get_by_name(np, "ipg"); | |
500 | ||
501 | /* Try osc_per first, and fall back to per otherwise */ | |
502 | imxtm->clk_per = of_clk_get_by_name(np, "osc_per"); | |
503 | if (IS_ERR(imxtm->clk_per)) | |
504 | imxtm->clk_per = of_clk_get_by_name(np, "per"); | |
505 | ||
506 | imxtm->type = type; | |
507 | ||
508 | ret = _mxc_timer_init(imxtm); | |
509 | if (ret) | |
510 | return ret; | |
511 | ||
512 | initialized = 1; | |
513 | ||
514 | return 0; | |
515 | } | |
516 | ||
517 | static int __init imx1_timer_init_dt(struct device_node *np) | |
518 | { | |
519 | return mxc_timer_init_dt(np, GPT_TYPE_IMX1); | |
520 | } | |
521 | ||
522 | static int __init imx21_timer_init_dt(struct device_node *np) | |
523 | { | |
524 | return mxc_timer_init_dt(np, GPT_TYPE_IMX21); | |
525 | } | |
526 | ||
527 | static int __init imx31_timer_init_dt(struct device_node *np) | |
528 | { | |
529 | enum imx_gpt_type type = GPT_TYPE_IMX31; | |
530 | ||
531 | /* | |
532 | * We were using the same compatible string for i.MX6Q/D and i.MX6DL/S | |
533 | * GPT device, while they actually have different programming model. | |
534 | * This is a workaround to keep the existing i.MX6DL/S DTBs continue | |
535 | * working with the new kernel. | |
536 | */ | |
537 | if (of_machine_is_compatible("fsl,imx6dl")) | |
538 | type = GPT_TYPE_IMX6DL; | |
539 | ||
540 | return mxc_timer_init_dt(np, type); | |
541 | } | |
542 | ||
543 | static int __init imx6dl_timer_init_dt(struct device_node *np) | |
544 | { | |
545 | return mxc_timer_init_dt(np, GPT_TYPE_IMX6DL); | |
546 | } | |
547 | ||
548 | CLOCKSOURCE_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt); | |
549 | CLOCKSOURCE_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt); | |
550 | CLOCKSOURCE_OF_DECLARE(imx27_timer, "fsl,imx27-gpt", imx21_timer_init_dt); | |
551 | CLOCKSOURCE_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt); | |
552 | CLOCKSOURCE_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt); | |
553 | CLOCKSOURCE_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt); | |
554 | CLOCKSOURCE_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt); | |
555 | CLOCKSOURCE_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt); | |
556 | CLOCKSOURCE_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt); | |
557 | CLOCKSOURCE_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt); | |
558 | CLOCKSOURCE_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt); | |
559 | CLOCKSOURCE_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt); |