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1 | /* | |
2 | * Cryptographic API. | |
3 | * | |
4 | * Support for Samsung S5PV210 HW acceleration. | |
5 | * | |
6 | * Copyright (C) 2011 NetUP Inc. All rights reserved. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as published | |
10 | * by the Free Software Foundation. | |
11 | * | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/crypto.h> | |
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/of.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/scatterlist.h> | |
27 | ||
28 | #include <crypto/ctr.h> | |
29 | #include <crypto/aes.h> | |
30 | #include <crypto/algapi.h> | |
31 | #include <crypto/scatterwalk.h> | |
32 | ||
33 | #define _SBF(s, v) ((v) << (s)) | |
34 | ||
35 | /* Feed control registers */ | |
36 | #define SSS_REG_FCINTSTAT 0x0000 | |
37 | #define SSS_FCINTSTAT_BRDMAINT BIT(3) | |
38 | #define SSS_FCINTSTAT_BTDMAINT BIT(2) | |
39 | #define SSS_FCINTSTAT_HRDMAINT BIT(1) | |
40 | #define SSS_FCINTSTAT_PKDMAINT BIT(0) | |
41 | ||
42 | #define SSS_REG_FCINTENSET 0x0004 | |
43 | #define SSS_FCINTENSET_BRDMAINTENSET BIT(3) | |
44 | #define SSS_FCINTENSET_BTDMAINTENSET BIT(2) | |
45 | #define SSS_FCINTENSET_HRDMAINTENSET BIT(1) | |
46 | #define SSS_FCINTENSET_PKDMAINTENSET BIT(0) | |
47 | ||
48 | #define SSS_REG_FCINTENCLR 0x0008 | |
49 | #define SSS_FCINTENCLR_BRDMAINTENCLR BIT(3) | |
50 | #define SSS_FCINTENCLR_BTDMAINTENCLR BIT(2) | |
51 | #define SSS_FCINTENCLR_HRDMAINTENCLR BIT(1) | |
52 | #define SSS_FCINTENCLR_PKDMAINTENCLR BIT(0) | |
53 | ||
54 | #define SSS_REG_FCINTPEND 0x000C | |
55 | #define SSS_FCINTPEND_BRDMAINTP BIT(3) | |
56 | #define SSS_FCINTPEND_BTDMAINTP BIT(2) | |
57 | #define SSS_FCINTPEND_HRDMAINTP BIT(1) | |
58 | #define SSS_FCINTPEND_PKDMAINTP BIT(0) | |
59 | ||
60 | #define SSS_REG_FCFIFOSTAT 0x0010 | |
61 | #define SSS_FCFIFOSTAT_BRFIFOFUL BIT(7) | |
62 | #define SSS_FCFIFOSTAT_BRFIFOEMP BIT(6) | |
63 | #define SSS_FCFIFOSTAT_BTFIFOFUL BIT(5) | |
64 | #define SSS_FCFIFOSTAT_BTFIFOEMP BIT(4) | |
65 | #define SSS_FCFIFOSTAT_HRFIFOFUL BIT(3) | |
66 | #define SSS_FCFIFOSTAT_HRFIFOEMP BIT(2) | |
67 | #define SSS_FCFIFOSTAT_PKFIFOFUL BIT(1) | |
68 | #define SSS_FCFIFOSTAT_PKFIFOEMP BIT(0) | |
69 | ||
70 | #define SSS_REG_FCFIFOCTRL 0x0014 | |
71 | #define SSS_FCFIFOCTRL_DESSEL BIT(2) | |
72 | #define SSS_HASHIN_INDEPENDENT _SBF(0, 0x00) | |
73 | #define SSS_HASHIN_CIPHER_INPUT _SBF(0, 0x01) | |
74 | #define SSS_HASHIN_CIPHER_OUTPUT _SBF(0, 0x02) | |
75 | ||
76 | #define SSS_REG_FCBRDMAS 0x0020 | |
77 | #define SSS_REG_FCBRDMAL 0x0024 | |
78 | #define SSS_REG_FCBRDMAC 0x0028 | |
79 | #define SSS_FCBRDMAC_BYTESWAP BIT(1) | |
80 | #define SSS_FCBRDMAC_FLUSH BIT(0) | |
81 | ||
82 | #define SSS_REG_FCBTDMAS 0x0030 | |
83 | #define SSS_REG_FCBTDMAL 0x0034 | |
84 | #define SSS_REG_FCBTDMAC 0x0038 | |
85 | #define SSS_FCBTDMAC_BYTESWAP BIT(1) | |
86 | #define SSS_FCBTDMAC_FLUSH BIT(0) | |
87 | ||
88 | #define SSS_REG_FCHRDMAS 0x0040 | |
89 | #define SSS_REG_FCHRDMAL 0x0044 | |
90 | #define SSS_REG_FCHRDMAC 0x0048 | |
91 | #define SSS_FCHRDMAC_BYTESWAP BIT(1) | |
92 | #define SSS_FCHRDMAC_FLUSH BIT(0) | |
93 | ||
94 | #define SSS_REG_FCPKDMAS 0x0050 | |
95 | #define SSS_REG_FCPKDMAL 0x0054 | |
96 | #define SSS_REG_FCPKDMAC 0x0058 | |
97 | #define SSS_FCPKDMAC_BYTESWAP BIT(3) | |
98 | #define SSS_FCPKDMAC_DESCEND BIT(2) | |
99 | #define SSS_FCPKDMAC_TRANSMIT BIT(1) | |
100 | #define SSS_FCPKDMAC_FLUSH BIT(0) | |
101 | ||
102 | #define SSS_REG_FCPKDMAO 0x005C | |
103 | ||
104 | /* AES registers */ | |
105 | #define SSS_REG_AES_CONTROL 0x00 | |
106 | #define SSS_AES_BYTESWAP_DI BIT(11) | |
107 | #define SSS_AES_BYTESWAP_DO BIT(10) | |
108 | #define SSS_AES_BYTESWAP_IV BIT(9) | |
109 | #define SSS_AES_BYTESWAP_CNT BIT(8) | |
110 | #define SSS_AES_BYTESWAP_KEY BIT(7) | |
111 | #define SSS_AES_KEY_CHANGE_MODE BIT(6) | |
112 | #define SSS_AES_KEY_SIZE_128 _SBF(4, 0x00) | |
113 | #define SSS_AES_KEY_SIZE_192 _SBF(4, 0x01) | |
114 | #define SSS_AES_KEY_SIZE_256 _SBF(4, 0x02) | |
115 | #define SSS_AES_FIFO_MODE BIT(3) | |
116 | #define SSS_AES_CHAIN_MODE_ECB _SBF(1, 0x00) | |
117 | #define SSS_AES_CHAIN_MODE_CBC _SBF(1, 0x01) | |
118 | #define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02) | |
119 | #define SSS_AES_MODE_DECRYPT BIT(0) | |
120 | ||
121 | #define SSS_REG_AES_STATUS 0x04 | |
122 | #define SSS_AES_BUSY BIT(2) | |
123 | #define SSS_AES_INPUT_READY BIT(1) | |
124 | #define SSS_AES_OUTPUT_READY BIT(0) | |
125 | ||
126 | #define SSS_REG_AES_IN_DATA(s) (0x10 + (s << 2)) | |
127 | #define SSS_REG_AES_OUT_DATA(s) (0x20 + (s << 2)) | |
128 | #define SSS_REG_AES_IV_DATA(s) (0x30 + (s << 2)) | |
129 | #define SSS_REG_AES_CNT_DATA(s) (0x40 + (s << 2)) | |
130 | #define SSS_REG_AES_KEY_DATA(s) (0x80 + (s << 2)) | |
131 | ||
132 | #define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg)) | |
133 | #define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg)) | |
134 | #define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg)) | |
135 | ||
136 | #define SSS_AES_REG(dev, reg) ((dev)->aes_ioaddr + SSS_REG_##reg) | |
137 | #define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \ | |
138 | SSS_AES_REG(dev, reg)) | |
139 | ||
140 | /* HW engine modes */ | |
141 | #define FLAGS_AES_DECRYPT BIT(0) | |
142 | #define FLAGS_AES_MODE_MASK _SBF(1, 0x03) | |
143 | #define FLAGS_AES_CBC _SBF(1, 0x01) | |
144 | #define FLAGS_AES_CTR _SBF(1, 0x02) | |
145 | ||
146 | #define AES_KEY_LEN 16 | |
147 | #define CRYPTO_QUEUE_LEN 1 | |
148 | ||
149 | /** | |
150 | * struct samsung_aes_variant - platform specific SSS driver data | |
151 | * @aes_offset: AES register offset from SSS module's base. | |
152 | * | |
153 | * Specifies platform specific configuration of SSS module. | |
154 | * Note: A structure for driver specific platform data is used for future | |
155 | * expansion of its usage. | |
156 | */ | |
157 | struct samsung_aes_variant { | |
158 | unsigned int aes_offset; | |
159 | }; | |
160 | ||
161 | struct s5p_aes_reqctx { | |
162 | unsigned long mode; | |
163 | }; | |
164 | ||
165 | struct s5p_aes_ctx { | |
166 | struct s5p_aes_dev *dev; | |
167 | ||
168 | uint8_t aes_key[AES_MAX_KEY_SIZE]; | |
169 | uint8_t nonce[CTR_RFC3686_NONCE_SIZE]; | |
170 | int keylen; | |
171 | }; | |
172 | ||
173 | struct s5p_aes_dev { | |
174 | struct device *dev; | |
175 | struct clk *clk; | |
176 | void __iomem *ioaddr; | |
177 | void __iomem *aes_ioaddr; | |
178 | int irq_fc; | |
179 | ||
180 | struct ablkcipher_request *req; | |
181 | struct s5p_aes_ctx *ctx; | |
182 | struct scatterlist *sg_src; | |
183 | struct scatterlist *sg_dst; | |
184 | ||
185 | /* In case of unaligned access: */ | |
186 | struct scatterlist *sg_src_cpy; | |
187 | struct scatterlist *sg_dst_cpy; | |
188 | ||
189 | struct tasklet_struct tasklet; | |
190 | struct crypto_queue queue; | |
191 | bool busy; | |
192 | spinlock_t lock; | |
193 | }; | |
194 | ||
195 | static struct s5p_aes_dev *s5p_dev; | |
196 | ||
197 | static const struct samsung_aes_variant s5p_aes_data = { | |
198 | .aes_offset = 0x4000, | |
199 | }; | |
200 | ||
201 | static const struct samsung_aes_variant exynos_aes_data = { | |
202 | .aes_offset = 0x200, | |
203 | }; | |
204 | ||
205 | static const struct of_device_id s5p_sss_dt_match[] = { | |
206 | { | |
207 | .compatible = "samsung,s5pv210-secss", | |
208 | .data = &s5p_aes_data, | |
209 | }, | |
210 | { | |
211 | .compatible = "samsung,exynos4210-secss", | |
212 | .data = &exynos_aes_data, | |
213 | }, | |
214 | { }, | |
215 | }; | |
216 | MODULE_DEVICE_TABLE(of, s5p_sss_dt_match); | |
217 | ||
218 | static inline struct samsung_aes_variant *find_s5p_sss_version | |
219 | (struct platform_device *pdev) | |
220 | { | |
221 | if (IS_ENABLED(CONFIG_OF) && (pdev->dev.of_node)) { | |
222 | const struct of_device_id *match; | |
223 | ||
224 | match = of_match_node(s5p_sss_dt_match, | |
225 | pdev->dev.of_node); | |
226 | return (struct samsung_aes_variant *)match->data; | |
227 | } | |
228 | return (struct samsung_aes_variant *) | |
229 | platform_get_device_id(pdev)->driver_data; | |
230 | } | |
231 | ||
232 | static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct scatterlist *sg) | |
233 | { | |
234 | SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg)); | |
235 | SSS_WRITE(dev, FCBRDMAL, sg_dma_len(sg)); | |
236 | } | |
237 | ||
238 | static void s5p_set_dma_outdata(struct s5p_aes_dev *dev, struct scatterlist *sg) | |
239 | { | |
240 | SSS_WRITE(dev, FCBTDMAS, sg_dma_address(sg)); | |
241 | SSS_WRITE(dev, FCBTDMAL, sg_dma_len(sg)); | |
242 | } | |
243 | ||
244 | static void s5p_free_sg_cpy(struct s5p_aes_dev *dev, struct scatterlist **sg) | |
245 | { | |
246 | int len; | |
247 | ||
248 | if (!*sg) | |
249 | return; | |
250 | ||
251 | len = ALIGN(dev->req->nbytes, AES_BLOCK_SIZE); | |
252 | free_pages((unsigned long)sg_virt(*sg), get_order(len)); | |
253 | ||
254 | kfree(*sg); | |
255 | *sg = NULL; | |
256 | } | |
257 | ||
258 | static void s5p_sg_copy_buf(void *buf, struct scatterlist *sg, | |
259 | unsigned int nbytes, int out) | |
260 | { | |
261 | struct scatter_walk walk; | |
262 | ||
263 | if (!nbytes) | |
264 | return; | |
265 | ||
266 | scatterwalk_start(&walk, sg); | |
267 | scatterwalk_copychunks(buf, &walk, nbytes, out); | |
268 | scatterwalk_done(&walk, out, 0); | |
269 | } | |
270 | ||
271 | static void s5p_sg_done(struct s5p_aes_dev *dev) | |
272 | { | |
273 | if (dev->sg_dst_cpy) { | |
274 | dev_dbg(dev->dev, | |
275 | "Copying %d bytes of output data back to original place\n", | |
276 | dev->req->nbytes); | |
277 | s5p_sg_copy_buf(sg_virt(dev->sg_dst_cpy), dev->req->dst, | |
278 | dev->req->nbytes, 1); | |
279 | } | |
280 | s5p_free_sg_cpy(dev, &dev->sg_src_cpy); | |
281 | s5p_free_sg_cpy(dev, &dev->sg_dst_cpy); | |
282 | } | |
283 | ||
284 | /* Calls the completion. Cannot be called with dev->lock hold. */ | |
285 | static void s5p_aes_complete(struct s5p_aes_dev *dev, int err) | |
286 | { | |
287 | dev->req->base.complete(&dev->req->base, err); | |
288 | } | |
289 | ||
290 | static void s5p_unset_outdata(struct s5p_aes_dev *dev) | |
291 | { | |
292 | dma_unmap_sg(dev->dev, dev->sg_dst, 1, DMA_FROM_DEVICE); | |
293 | } | |
294 | ||
295 | static void s5p_unset_indata(struct s5p_aes_dev *dev) | |
296 | { | |
297 | dma_unmap_sg(dev->dev, dev->sg_src, 1, DMA_TO_DEVICE); | |
298 | } | |
299 | ||
300 | static int s5p_make_sg_cpy(struct s5p_aes_dev *dev, struct scatterlist *src, | |
301 | struct scatterlist **dst) | |
302 | { | |
303 | void *pages; | |
304 | int len; | |
305 | ||
306 | *dst = kmalloc(sizeof(**dst), GFP_ATOMIC); | |
307 | if (!*dst) | |
308 | return -ENOMEM; | |
309 | ||
310 | len = ALIGN(dev->req->nbytes, AES_BLOCK_SIZE); | |
311 | pages = (void *)__get_free_pages(GFP_ATOMIC, get_order(len)); | |
312 | if (!pages) { | |
313 | kfree(*dst); | |
314 | *dst = NULL; | |
315 | return -ENOMEM; | |
316 | } | |
317 | ||
318 | s5p_sg_copy_buf(pages, src, dev->req->nbytes, 0); | |
319 | ||
320 | sg_init_table(*dst, 1); | |
321 | sg_set_buf(*dst, pages, len); | |
322 | ||
323 | return 0; | |
324 | } | |
325 | ||
326 | static int s5p_set_outdata(struct s5p_aes_dev *dev, struct scatterlist *sg) | |
327 | { | |
328 | int err; | |
329 | ||
330 | if (!sg->length) { | |
331 | err = -EINVAL; | |
332 | goto exit; | |
333 | } | |
334 | ||
335 | err = dma_map_sg(dev->dev, sg, 1, DMA_FROM_DEVICE); | |
336 | if (!err) { | |
337 | err = -ENOMEM; | |
338 | goto exit; | |
339 | } | |
340 | ||
341 | dev->sg_dst = sg; | |
342 | err = 0; | |
343 | ||
344 | exit: | |
345 | return err; | |
346 | } | |
347 | ||
348 | static int s5p_set_indata(struct s5p_aes_dev *dev, struct scatterlist *sg) | |
349 | { | |
350 | int err; | |
351 | ||
352 | if (!sg->length) { | |
353 | err = -EINVAL; | |
354 | goto exit; | |
355 | } | |
356 | ||
357 | err = dma_map_sg(dev->dev, sg, 1, DMA_TO_DEVICE); | |
358 | if (!err) { | |
359 | err = -ENOMEM; | |
360 | goto exit; | |
361 | } | |
362 | ||
363 | dev->sg_src = sg; | |
364 | err = 0; | |
365 | ||
366 | exit: | |
367 | return err; | |
368 | } | |
369 | ||
370 | /* | |
371 | * Returns -ERRNO on error (mapping of new data failed). | |
372 | * On success returns: | |
373 | * - 0 if there is no more data, | |
374 | * - 1 if new transmitting (output) data is ready and its address+length | |
375 | * have to be written to device (by calling s5p_set_dma_outdata()). | |
376 | */ | |
377 | static int s5p_aes_tx(struct s5p_aes_dev *dev) | |
378 | { | |
379 | int ret = 0; | |
380 | ||
381 | s5p_unset_outdata(dev); | |
382 | ||
383 | if (!sg_is_last(dev->sg_dst)) { | |
384 | ret = s5p_set_outdata(dev, sg_next(dev->sg_dst)); | |
385 | if (!ret) | |
386 | ret = 1; | |
387 | } | |
388 | ||
389 | return ret; | |
390 | } | |
391 | ||
392 | /* | |
393 | * Returns -ERRNO on error (mapping of new data failed). | |
394 | * On success returns: | |
395 | * - 0 if there is no more data, | |
396 | * - 1 if new receiving (input) data is ready and its address+length | |
397 | * have to be written to device (by calling s5p_set_dma_indata()). | |
398 | */ | |
399 | static int s5p_aes_rx(struct s5p_aes_dev *dev/*, bool *set_dma*/) | |
400 | { | |
401 | int ret = 0; | |
402 | ||
403 | s5p_unset_indata(dev); | |
404 | ||
405 | if (!sg_is_last(dev->sg_src)) { | |
406 | ret = s5p_set_indata(dev, sg_next(dev->sg_src)); | |
407 | if (!ret) | |
408 | ret = 1; | |
409 | } | |
410 | ||
411 | return ret; | |
412 | } | |
413 | ||
414 | static irqreturn_t s5p_aes_interrupt(int irq, void *dev_id) | |
415 | { | |
416 | struct platform_device *pdev = dev_id; | |
417 | struct s5p_aes_dev *dev = platform_get_drvdata(pdev); | |
418 | int err_dma_tx = 0; | |
419 | int err_dma_rx = 0; | |
420 | bool tx_end = false; | |
421 | unsigned long flags; | |
422 | uint32_t status; | |
423 | int err; | |
424 | ||
425 | spin_lock_irqsave(&dev->lock, flags); | |
426 | ||
427 | /* | |
428 | * Handle rx or tx interrupt. If there is still data (scatterlist did not | |
429 | * reach end), then map next scatterlist entry. | |
430 | * In case of such mapping error, s5p_aes_complete() should be called. | |
431 | * | |
432 | * If there is no more data in tx scatter list, call s5p_aes_complete() | |
433 | * and schedule new tasklet. | |
434 | */ | |
435 | status = SSS_READ(dev, FCINTSTAT); | |
436 | if (status & SSS_FCINTSTAT_BRDMAINT) | |
437 | err_dma_rx = s5p_aes_rx(dev); | |
438 | ||
439 | if (status & SSS_FCINTSTAT_BTDMAINT) { | |
440 | if (sg_is_last(dev->sg_dst)) | |
441 | tx_end = true; | |
442 | err_dma_tx = s5p_aes_tx(dev); | |
443 | } | |
444 | ||
445 | SSS_WRITE(dev, FCINTPEND, status); | |
446 | ||
447 | if (err_dma_rx < 0) { | |
448 | err = err_dma_rx; | |
449 | goto error; | |
450 | } | |
451 | if (err_dma_tx < 0) { | |
452 | err = err_dma_tx; | |
453 | goto error; | |
454 | } | |
455 | ||
456 | if (tx_end) { | |
457 | s5p_sg_done(dev); | |
458 | ||
459 | spin_unlock_irqrestore(&dev->lock, flags); | |
460 | ||
461 | s5p_aes_complete(dev, 0); | |
462 | /* Device is still busy */ | |
463 | tasklet_schedule(&dev->tasklet); | |
464 | } else { | |
465 | /* | |
466 | * Writing length of DMA block (either receiving or | |
467 | * transmitting) will start the operation immediately, so this | |
468 | * should be done at the end (even after clearing pending | |
469 | * interrupts to not miss the interrupt). | |
470 | */ | |
471 | if (err_dma_tx == 1) | |
472 | s5p_set_dma_outdata(dev, dev->sg_dst); | |
473 | if (err_dma_rx == 1) | |
474 | s5p_set_dma_indata(dev, dev->sg_src); | |
475 | ||
476 | spin_unlock_irqrestore(&dev->lock, flags); | |
477 | } | |
478 | ||
479 | return IRQ_HANDLED; | |
480 | ||
481 | error: | |
482 | s5p_sg_done(dev); | |
483 | dev->busy = false; | |
484 | spin_unlock_irqrestore(&dev->lock, flags); | |
485 | s5p_aes_complete(dev, err); | |
486 | ||
487 | return IRQ_HANDLED; | |
488 | } | |
489 | ||
490 | static void s5p_set_aes(struct s5p_aes_dev *dev, | |
491 | uint8_t *key, uint8_t *iv, unsigned int keylen) | |
492 | { | |
493 | void __iomem *keystart; | |
494 | ||
495 | if (iv) | |
496 | memcpy_toio(dev->aes_ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10); | |
497 | ||
498 | if (keylen == AES_KEYSIZE_256) | |
499 | keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(0); | |
500 | else if (keylen == AES_KEYSIZE_192) | |
501 | keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(2); | |
502 | else | |
503 | keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(4); | |
504 | ||
505 | memcpy_toio(keystart, key, keylen); | |
506 | } | |
507 | ||
508 | static bool s5p_is_sg_aligned(struct scatterlist *sg) | |
509 | { | |
510 | while (sg) { | |
511 | if (!IS_ALIGNED(sg->length, AES_BLOCK_SIZE)) | |
512 | return false; | |
513 | sg = sg_next(sg); | |
514 | } | |
515 | ||
516 | return true; | |
517 | } | |
518 | ||
519 | static int s5p_set_indata_start(struct s5p_aes_dev *dev, | |
520 | struct ablkcipher_request *req) | |
521 | { | |
522 | struct scatterlist *sg; | |
523 | int err; | |
524 | ||
525 | dev->sg_src_cpy = NULL; | |
526 | sg = req->src; | |
527 | if (!s5p_is_sg_aligned(sg)) { | |
528 | dev_dbg(dev->dev, | |
529 | "At least one unaligned source scatter list, making a copy\n"); | |
530 | err = s5p_make_sg_cpy(dev, sg, &dev->sg_src_cpy); | |
531 | if (err) | |
532 | return err; | |
533 | ||
534 | sg = dev->sg_src_cpy; | |
535 | } | |
536 | ||
537 | err = s5p_set_indata(dev, sg); | |
538 | if (err) { | |
539 | s5p_free_sg_cpy(dev, &dev->sg_src_cpy); | |
540 | return err; | |
541 | } | |
542 | ||
543 | return 0; | |
544 | } | |
545 | ||
546 | static int s5p_set_outdata_start(struct s5p_aes_dev *dev, | |
547 | struct ablkcipher_request *req) | |
548 | { | |
549 | struct scatterlist *sg; | |
550 | int err; | |
551 | ||
552 | dev->sg_dst_cpy = NULL; | |
553 | sg = req->dst; | |
554 | if (!s5p_is_sg_aligned(sg)) { | |
555 | dev_dbg(dev->dev, | |
556 | "At least one unaligned dest scatter list, making a copy\n"); | |
557 | err = s5p_make_sg_cpy(dev, sg, &dev->sg_dst_cpy); | |
558 | if (err) | |
559 | return err; | |
560 | ||
561 | sg = dev->sg_dst_cpy; | |
562 | } | |
563 | ||
564 | err = s5p_set_outdata(dev, sg); | |
565 | if (err) { | |
566 | s5p_free_sg_cpy(dev, &dev->sg_dst_cpy); | |
567 | return err; | |
568 | } | |
569 | ||
570 | return 0; | |
571 | } | |
572 | ||
573 | static void s5p_aes_crypt_start(struct s5p_aes_dev *dev, unsigned long mode) | |
574 | { | |
575 | struct ablkcipher_request *req = dev->req; | |
576 | uint32_t aes_control; | |
577 | unsigned long flags; | |
578 | int err; | |
579 | ||
580 | aes_control = SSS_AES_KEY_CHANGE_MODE; | |
581 | if (mode & FLAGS_AES_DECRYPT) | |
582 | aes_control |= SSS_AES_MODE_DECRYPT; | |
583 | ||
584 | if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CBC) | |
585 | aes_control |= SSS_AES_CHAIN_MODE_CBC; | |
586 | else if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CTR) | |
587 | aes_control |= SSS_AES_CHAIN_MODE_CTR; | |
588 | ||
589 | if (dev->ctx->keylen == AES_KEYSIZE_192) | |
590 | aes_control |= SSS_AES_KEY_SIZE_192; | |
591 | else if (dev->ctx->keylen == AES_KEYSIZE_256) | |
592 | aes_control |= SSS_AES_KEY_SIZE_256; | |
593 | ||
594 | aes_control |= SSS_AES_FIFO_MODE; | |
595 | ||
596 | /* as a variant it is possible to use byte swapping on DMA side */ | |
597 | aes_control |= SSS_AES_BYTESWAP_DI | |
598 | | SSS_AES_BYTESWAP_DO | |
599 | | SSS_AES_BYTESWAP_IV | |
600 | | SSS_AES_BYTESWAP_KEY | |
601 | | SSS_AES_BYTESWAP_CNT; | |
602 | ||
603 | spin_lock_irqsave(&dev->lock, flags); | |
604 | ||
605 | SSS_WRITE(dev, FCINTENCLR, | |
606 | SSS_FCINTENCLR_BTDMAINTENCLR | SSS_FCINTENCLR_BRDMAINTENCLR); | |
607 | SSS_WRITE(dev, FCFIFOCTRL, 0x00); | |
608 | ||
609 | err = s5p_set_indata_start(dev, req); | |
610 | if (err) | |
611 | goto indata_error; | |
612 | ||
613 | err = s5p_set_outdata_start(dev, req); | |
614 | if (err) | |
615 | goto outdata_error; | |
616 | ||
617 | SSS_AES_WRITE(dev, AES_CONTROL, aes_control); | |
618 | s5p_set_aes(dev, dev->ctx->aes_key, req->info, dev->ctx->keylen); | |
619 | ||
620 | s5p_set_dma_indata(dev, dev->sg_src); | |
621 | s5p_set_dma_outdata(dev, dev->sg_dst); | |
622 | ||
623 | SSS_WRITE(dev, FCINTENSET, | |
624 | SSS_FCINTENSET_BTDMAINTENSET | SSS_FCINTENSET_BRDMAINTENSET); | |
625 | ||
626 | spin_unlock_irqrestore(&dev->lock, flags); | |
627 | ||
628 | return; | |
629 | ||
630 | outdata_error: | |
631 | s5p_unset_indata(dev); | |
632 | ||
633 | indata_error: | |
634 | s5p_sg_done(dev); | |
635 | dev->busy = false; | |
636 | spin_unlock_irqrestore(&dev->lock, flags); | |
637 | s5p_aes_complete(dev, err); | |
638 | } | |
639 | ||
640 | static void s5p_tasklet_cb(unsigned long data) | |
641 | { | |
642 | struct s5p_aes_dev *dev = (struct s5p_aes_dev *)data; | |
643 | struct crypto_async_request *async_req, *backlog; | |
644 | struct s5p_aes_reqctx *reqctx; | |
645 | unsigned long flags; | |
646 | ||
647 | spin_lock_irqsave(&dev->lock, flags); | |
648 | backlog = crypto_get_backlog(&dev->queue); | |
649 | async_req = crypto_dequeue_request(&dev->queue); | |
650 | ||
651 | if (!async_req) { | |
652 | dev->busy = false; | |
653 | spin_unlock_irqrestore(&dev->lock, flags); | |
654 | return; | |
655 | } | |
656 | spin_unlock_irqrestore(&dev->lock, flags); | |
657 | ||
658 | if (backlog) | |
659 | backlog->complete(backlog, -EINPROGRESS); | |
660 | ||
661 | dev->req = ablkcipher_request_cast(async_req); | |
662 | dev->ctx = crypto_tfm_ctx(dev->req->base.tfm); | |
663 | reqctx = ablkcipher_request_ctx(dev->req); | |
664 | ||
665 | s5p_aes_crypt_start(dev, reqctx->mode); | |
666 | } | |
667 | ||
668 | static int s5p_aes_handle_req(struct s5p_aes_dev *dev, | |
669 | struct ablkcipher_request *req) | |
670 | { | |
671 | unsigned long flags; | |
672 | int err; | |
673 | ||
674 | spin_lock_irqsave(&dev->lock, flags); | |
675 | err = ablkcipher_enqueue_request(&dev->queue, req); | |
676 | if (dev->busy) { | |
677 | spin_unlock_irqrestore(&dev->lock, flags); | |
678 | goto exit; | |
679 | } | |
680 | dev->busy = true; | |
681 | ||
682 | spin_unlock_irqrestore(&dev->lock, flags); | |
683 | ||
684 | tasklet_schedule(&dev->tasklet); | |
685 | ||
686 | exit: | |
687 | return err; | |
688 | } | |
689 | ||
690 | static int s5p_aes_crypt(struct ablkcipher_request *req, unsigned long mode) | |
691 | { | |
692 | struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req); | |
693 | struct s5p_aes_reqctx *reqctx = ablkcipher_request_ctx(req); | |
694 | struct s5p_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm); | |
695 | struct s5p_aes_dev *dev = ctx->dev; | |
696 | ||
697 | if (!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE)) { | |
698 | dev_err(dev->dev, "request size is not exact amount of AES blocks\n"); | |
699 | return -EINVAL; | |
700 | } | |
701 | ||
702 | reqctx->mode = mode; | |
703 | ||
704 | return s5p_aes_handle_req(dev, req); | |
705 | } | |
706 | ||
707 | static int s5p_aes_setkey(struct crypto_ablkcipher *cipher, | |
708 | const uint8_t *key, unsigned int keylen) | |
709 | { | |
710 | struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher); | |
711 | struct s5p_aes_ctx *ctx = crypto_tfm_ctx(tfm); | |
712 | ||
713 | if (keylen != AES_KEYSIZE_128 && | |
714 | keylen != AES_KEYSIZE_192 && | |
715 | keylen != AES_KEYSIZE_256) | |
716 | return -EINVAL; | |
717 | ||
718 | memcpy(ctx->aes_key, key, keylen); | |
719 | ctx->keylen = keylen; | |
720 | ||
721 | return 0; | |
722 | } | |
723 | ||
724 | static int s5p_aes_ecb_encrypt(struct ablkcipher_request *req) | |
725 | { | |
726 | return s5p_aes_crypt(req, 0); | |
727 | } | |
728 | ||
729 | static int s5p_aes_ecb_decrypt(struct ablkcipher_request *req) | |
730 | { | |
731 | return s5p_aes_crypt(req, FLAGS_AES_DECRYPT); | |
732 | } | |
733 | ||
734 | static int s5p_aes_cbc_encrypt(struct ablkcipher_request *req) | |
735 | { | |
736 | return s5p_aes_crypt(req, FLAGS_AES_CBC); | |
737 | } | |
738 | ||
739 | static int s5p_aes_cbc_decrypt(struct ablkcipher_request *req) | |
740 | { | |
741 | return s5p_aes_crypt(req, FLAGS_AES_DECRYPT | FLAGS_AES_CBC); | |
742 | } | |
743 | ||
744 | static int s5p_aes_cra_init(struct crypto_tfm *tfm) | |
745 | { | |
746 | struct s5p_aes_ctx *ctx = crypto_tfm_ctx(tfm); | |
747 | ||
748 | ctx->dev = s5p_dev; | |
749 | tfm->crt_ablkcipher.reqsize = sizeof(struct s5p_aes_reqctx); | |
750 | ||
751 | return 0; | |
752 | } | |
753 | ||
754 | static struct crypto_alg algs[] = { | |
755 | { | |
756 | .cra_name = "ecb(aes)", | |
757 | .cra_driver_name = "ecb-aes-s5p", | |
758 | .cra_priority = 100, | |
759 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | | |
760 | CRYPTO_ALG_ASYNC | | |
761 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
762 | .cra_blocksize = AES_BLOCK_SIZE, | |
763 | .cra_ctxsize = sizeof(struct s5p_aes_ctx), | |
764 | .cra_alignmask = 0x0f, | |
765 | .cra_type = &crypto_ablkcipher_type, | |
766 | .cra_module = THIS_MODULE, | |
767 | .cra_init = s5p_aes_cra_init, | |
768 | .cra_u.ablkcipher = { | |
769 | .min_keysize = AES_MIN_KEY_SIZE, | |
770 | .max_keysize = AES_MAX_KEY_SIZE, | |
771 | .setkey = s5p_aes_setkey, | |
772 | .encrypt = s5p_aes_ecb_encrypt, | |
773 | .decrypt = s5p_aes_ecb_decrypt, | |
774 | } | |
775 | }, | |
776 | { | |
777 | .cra_name = "cbc(aes)", | |
778 | .cra_driver_name = "cbc-aes-s5p", | |
779 | .cra_priority = 100, | |
780 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | | |
781 | CRYPTO_ALG_ASYNC | | |
782 | CRYPTO_ALG_KERN_DRIVER_ONLY, | |
783 | .cra_blocksize = AES_BLOCK_SIZE, | |
784 | .cra_ctxsize = sizeof(struct s5p_aes_ctx), | |
785 | .cra_alignmask = 0x0f, | |
786 | .cra_type = &crypto_ablkcipher_type, | |
787 | .cra_module = THIS_MODULE, | |
788 | .cra_init = s5p_aes_cra_init, | |
789 | .cra_u.ablkcipher = { | |
790 | .min_keysize = AES_MIN_KEY_SIZE, | |
791 | .max_keysize = AES_MAX_KEY_SIZE, | |
792 | .ivsize = AES_BLOCK_SIZE, | |
793 | .setkey = s5p_aes_setkey, | |
794 | .encrypt = s5p_aes_cbc_encrypt, | |
795 | .decrypt = s5p_aes_cbc_decrypt, | |
796 | } | |
797 | }, | |
798 | }; | |
799 | ||
800 | static int s5p_aes_probe(struct platform_device *pdev) | |
801 | { | |
802 | struct device *dev = &pdev->dev; | |
803 | int i, j, err = -ENODEV; | |
804 | struct samsung_aes_variant *variant; | |
805 | struct s5p_aes_dev *pdata; | |
806 | struct resource *res; | |
807 | ||
808 | if (s5p_dev) | |
809 | return -EEXIST; | |
810 | ||
811 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); | |
812 | if (!pdata) | |
813 | return -ENOMEM; | |
814 | ||
815 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
816 | pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res); | |
817 | if (IS_ERR(pdata->ioaddr)) | |
818 | return PTR_ERR(pdata->ioaddr); | |
819 | ||
820 | variant = find_s5p_sss_version(pdev); | |
821 | ||
822 | pdata->clk = devm_clk_get(dev, "secss"); | |
823 | if (IS_ERR(pdata->clk)) { | |
824 | dev_err(dev, "failed to find secss clock source\n"); | |
825 | return -ENOENT; | |
826 | } | |
827 | ||
828 | err = clk_prepare_enable(pdata->clk); | |
829 | if (err < 0) { | |
830 | dev_err(dev, "Enabling SSS clk failed, err %d\n", err); | |
831 | return err; | |
832 | } | |
833 | ||
834 | spin_lock_init(&pdata->lock); | |
835 | ||
836 | pdata->aes_ioaddr = pdata->ioaddr + variant->aes_offset; | |
837 | ||
838 | pdata->irq_fc = platform_get_irq(pdev, 0); | |
839 | if (pdata->irq_fc < 0) { | |
840 | err = pdata->irq_fc; | |
841 | dev_warn(dev, "feed control interrupt is not available.\n"); | |
842 | goto err_irq; | |
843 | } | |
844 | err = devm_request_threaded_irq(dev, pdata->irq_fc, NULL, | |
845 | s5p_aes_interrupt, IRQF_ONESHOT, | |
846 | pdev->name, pdev); | |
847 | if (err < 0) { | |
848 | dev_warn(dev, "feed control interrupt is not available.\n"); | |
849 | goto err_irq; | |
850 | } | |
851 | ||
852 | pdata->busy = false; | |
853 | pdata->dev = dev; | |
854 | platform_set_drvdata(pdev, pdata); | |
855 | s5p_dev = pdata; | |
856 | ||
857 | tasklet_init(&pdata->tasklet, s5p_tasklet_cb, (unsigned long)pdata); | |
858 | crypto_init_queue(&pdata->queue, CRYPTO_QUEUE_LEN); | |
859 | ||
860 | for (i = 0; i < ARRAY_SIZE(algs); i++) { | |
861 | err = crypto_register_alg(&algs[i]); | |
862 | if (err) | |
863 | goto err_algs; | |
864 | } | |
865 | ||
866 | dev_info(dev, "s5p-sss driver registered\n"); | |
867 | ||
868 | return 0; | |
869 | ||
870 | err_algs: | |
871 | dev_err(dev, "can't register '%s': %d\n", algs[i].cra_name, err); | |
872 | ||
873 | for (j = 0; j < i; j++) | |
874 | crypto_unregister_alg(&algs[j]); | |
875 | ||
876 | tasklet_kill(&pdata->tasklet); | |
877 | ||
878 | err_irq: | |
879 | clk_disable_unprepare(pdata->clk); | |
880 | ||
881 | s5p_dev = NULL; | |
882 | ||
883 | return err; | |
884 | } | |
885 | ||
886 | static int s5p_aes_remove(struct platform_device *pdev) | |
887 | { | |
888 | struct s5p_aes_dev *pdata = platform_get_drvdata(pdev); | |
889 | int i; | |
890 | ||
891 | if (!pdata) | |
892 | return -ENODEV; | |
893 | ||
894 | for (i = 0; i < ARRAY_SIZE(algs); i++) | |
895 | crypto_unregister_alg(&algs[i]); | |
896 | ||
897 | tasklet_kill(&pdata->tasklet); | |
898 | ||
899 | clk_disable_unprepare(pdata->clk); | |
900 | ||
901 | s5p_dev = NULL; | |
902 | ||
903 | return 0; | |
904 | } | |
905 | ||
906 | static struct platform_driver s5p_aes_crypto = { | |
907 | .probe = s5p_aes_probe, | |
908 | .remove = s5p_aes_remove, | |
909 | .driver = { | |
910 | .name = "s5p-secss", | |
911 | .of_match_table = s5p_sss_dt_match, | |
912 | }, | |
913 | }; | |
914 | ||
915 | module_platform_driver(s5p_aes_crypto); | |
916 | ||
917 | MODULE_DESCRIPTION("S5PV210 AES hw acceleration support."); | |
918 | MODULE_LICENSE("GPL v2"); | |
919 | MODULE_AUTHOR("Vladimir Zapolskiy <vzapolskiy@gmail.com>"); |