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1 | /* | |
2 | * AMD64 class Memory Controller kernel module | |
3 | * | |
4 | * Copyright (c) 2009 SoftwareBitMaker. | |
5 | * Copyright (c) 2009-15 Advanced Micro Devices, Inc. | |
6 | * | |
7 | * This file may be distributed under the terms of the | |
8 | * GNU General Public License. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/ctype.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/pci_ids.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/mmzone.h> | |
18 | #include <linux/edac.h> | |
19 | #include <asm/msr.h> | |
20 | #include "edac_core.h" | |
21 | #include "mce_amd.h" | |
22 | ||
23 | #define amd64_debug(fmt, arg...) \ | |
24 | edac_printk(KERN_DEBUG, "amd64", fmt, ##arg) | |
25 | ||
26 | #define amd64_info(fmt, arg...) \ | |
27 | edac_printk(KERN_INFO, "amd64", fmt, ##arg) | |
28 | ||
29 | #define amd64_notice(fmt, arg...) \ | |
30 | edac_printk(KERN_NOTICE, "amd64", fmt, ##arg) | |
31 | ||
32 | #define amd64_warn(fmt, arg...) \ | |
33 | edac_printk(KERN_WARNING, "amd64", fmt, ##arg) | |
34 | ||
35 | #define amd64_err(fmt, arg...) \ | |
36 | edac_printk(KERN_ERR, "amd64", fmt, ##arg) | |
37 | ||
38 | #define amd64_mc_warn(mci, fmt, arg...) \ | |
39 | edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg) | |
40 | ||
41 | #define amd64_mc_err(mci, fmt, arg...) \ | |
42 | edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg) | |
43 | ||
44 | /* | |
45 | * Throughout the comments in this code, the following terms are used: | |
46 | * | |
47 | * SysAddr, DramAddr, and InputAddr | |
48 | * | |
49 | * These terms come directly from the amd64 documentation | |
50 | * (AMD publication #26094). They are defined as follows: | |
51 | * | |
52 | * SysAddr: | |
53 | * This is a physical address generated by a CPU core or a device | |
54 | * doing DMA. If generated by a CPU core, a SysAddr is the result of | |
55 | * a virtual to physical address translation by the CPU core's address | |
56 | * translation mechanism (MMU). | |
57 | * | |
58 | * DramAddr: | |
59 | * A DramAddr is derived from a SysAddr by subtracting an offset that | |
60 | * depends on which node the SysAddr maps to and whether the SysAddr | |
61 | * is within a range affected by memory hoisting. The DRAM Base | |
62 | * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers | |
63 | * determine which node a SysAddr maps to. | |
64 | * | |
65 | * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr | |
66 | * is within the range of addresses specified by this register, then | |
67 | * a value x from the DHAR is subtracted from the SysAddr to produce a | |
68 | * DramAddr. Here, x represents the base address for the node that | |
69 | * the SysAddr maps to plus an offset due to memory hoisting. See | |
70 | * section 3.4.8 and the comments in amd64_get_dram_hole_info() and | |
71 | * sys_addr_to_dram_addr() below for more information. | |
72 | * | |
73 | * If the SysAddr is not affected by the DHAR then a value y is | |
74 | * subtracted from the SysAddr to produce a DramAddr. Here, y is the | |
75 | * base address for the node that the SysAddr maps to. See section | |
76 | * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more | |
77 | * information. | |
78 | * | |
79 | * InputAddr: | |
80 | * A DramAddr is translated to an InputAddr before being passed to the | |
81 | * memory controller for the node that the DramAddr is associated | |
82 | * with. The memory controller then maps the InputAddr to a csrow. | |
83 | * If node interleaving is not in use, then the InputAddr has the same | |
84 | * value as the DramAddr. Otherwise, the InputAddr is produced by | |
85 | * discarding the bits used for node interleaving from the DramAddr. | |
86 | * See section 3.4.4 for more information. | |
87 | * | |
88 | * The memory controller for a given node uses its DRAM CS Base and | |
89 | * DRAM CS Mask registers to map an InputAddr to a csrow. See | |
90 | * sections 3.5.4 and 3.5.5 for more information. | |
91 | */ | |
92 | ||
93 | #define EDAC_AMD64_VERSION "3.4.0" | |
94 | #define EDAC_MOD_STR "amd64_edac" | |
95 | ||
96 | /* Extended Model from CPUID, for CPU Revision numbers */ | |
97 | #define K8_REV_D 1 | |
98 | #define K8_REV_E 2 | |
99 | #define K8_REV_F 4 | |
100 | ||
101 | /* Hardware limit on ChipSelect rows per MC and processors per system */ | |
102 | #define NUM_CHIPSELECTS 8 | |
103 | #define DRAM_RANGES 8 | |
104 | ||
105 | #define ON true | |
106 | #define OFF false | |
107 | ||
108 | /* | |
109 | * PCI-defined configuration space registers | |
110 | */ | |
111 | #define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601 | |
112 | #define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602 | |
113 | #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b | |
114 | #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c | |
115 | #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571 | |
116 | #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572 | |
117 | #define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531 | |
118 | #define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532 | |
119 | #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581 | |
120 | #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582 | |
121 | ||
122 | /* | |
123 | * Function 1 - Address Map | |
124 | */ | |
125 | #define DRAM_BASE_LO 0x40 | |
126 | #define DRAM_LIMIT_LO 0x44 | |
127 | ||
128 | /* | |
129 | * F15 M30h D18F1x2[1C:00] | |
130 | */ | |
131 | #define DRAM_CONT_BASE 0x200 | |
132 | #define DRAM_CONT_LIMIT 0x204 | |
133 | ||
134 | /* | |
135 | * F15 M30h D18F1x2[4C:40] | |
136 | */ | |
137 | #define DRAM_CONT_HIGH_OFF 0x240 | |
138 | ||
139 | #define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3)) | |
140 | #define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7)) | |
141 | #define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7)) | |
142 | ||
143 | #define DHAR 0xf0 | |
144 | #define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1)) | |
145 | #define dhar_base(pvt) ((pvt)->dhar & 0xff000000) | |
146 | #define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16) | |
147 | ||
148 | /* NOTE: Extra mask bit vs K8 */ | |
149 | #define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16) | |
150 | ||
151 | #define DCT_CFG_SEL 0x10C | |
152 | ||
153 | #define DRAM_LOCAL_NODE_BASE 0x120 | |
154 | #define DRAM_LOCAL_NODE_LIM 0x124 | |
155 | ||
156 | #define DRAM_BASE_HI 0x140 | |
157 | #define DRAM_LIMIT_HI 0x144 | |
158 | ||
159 | ||
160 | /* | |
161 | * Function 2 - DRAM controller | |
162 | */ | |
163 | #define DCSB0 0x40 | |
164 | #define DCSB1 0x140 | |
165 | #define DCSB_CS_ENABLE BIT(0) | |
166 | ||
167 | #define DCSM0 0x60 | |
168 | #define DCSM1 0x160 | |
169 | ||
170 | #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE) | |
171 | ||
172 | #define DRAM_CONTROL 0x78 | |
173 | ||
174 | #define DBAM0 0x80 | |
175 | #define DBAM1 0x180 | |
176 | ||
177 | /* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */ | |
178 | #define DBAM_DIMM(i, reg) ((((reg) >> (4*(i)))) & 0xF) | |
179 | ||
180 | #define DBAM_MAX_VALUE 11 | |
181 | ||
182 | #define DCLR0 0x90 | |
183 | #define DCLR1 0x190 | |
184 | #define REVE_WIDTH_128 BIT(16) | |
185 | #define WIDTH_128 BIT(11) | |
186 | ||
187 | #define DCHR0 0x94 | |
188 | #define DCHR1 0x194 | |
189 | #define DDR3_MODE BIT(8) | |
190 | ||
191 | #define DCT_SEL_LO 0x110 | |
192 | #define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0)) | |
193 | #define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2)) | |
194 | ||
195 | #define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4))) | |
196 | ||
197 | #define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5)) | |
198 | #define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10)) | |
199 | ||
200 | #define SWAP_INTLV_REG 0x10c | |
201 | ||
202 | #define DCT_SEL_HI 0x114 | |
203 | ||
204 | #define F15H_M60H_SCRCTRL 0x1C8 | |
205 | ||
206 | /* | |
207 | * Function 3 - Misc Control | |
208 | */ | |
209 | #define NBCTL 0x40 | |
210 | ||
211 | #define NBCFG 0x44 | |
212 | #define NBCFG_CHIPKILL BIT(23) | |
213 | #define NBCFG_ECC_ENABLE BIT(22) | |
214 | ||
215 | /* F3x48: NBSL */ | |
216 | #define F10_NBSL_EXT_ERR_ECC 0x8 | |
217 | #define NBSL_PP_OBS 0x2 | |
218 | ||
219 | #define SCRCTRL 0x58 | |
220 | ||
221 | #define F10_ONLINE_SPARE 0xB0 | |
222 | #define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1) | |
223 | #define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7) | |
224 | ||
225 | #define F10_NB_ARRAY_ADDR 0xB8 | |
226 | #define F10_NB_ARRAY_DRAM BIT(31) | |
227 | ||
228 | /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */ | |
229 | #define SET_NB_ARRAY_ADDR(section) (((section) & 0x3) << 1) | |
230 | ||
231 | #define F10_NB_ARRAY_DATA 0xBC | |
232 | #define F10_NB_ARR_ECC_WR_REQ BIT(17) | |
233 | #define SET_NB_DRAM_INJECTION_WRITE(inj) \ | |
234 | (BIT(((inj.word) & 0xF) + 20) | \ | |
235 | F10_NB_ARR_ECC_WR_REQ | inj.bit_map) | |
236 | #define SET_NB_DRAM_INJECTION_READ(inj) \ | |
237 | (BIT(((inj.word) & 0xF) + 20) | \ | |
238 | BIT(16) | inj.bit_map) | |
239 | ||
240 | ||
241 | #define NBCAP 0xE8 | |
242 | #define NBCAP_CHIPKILL BIT(4) | |
243 | #define NBCAP_SECDED BIT(3) | |
244 | #define NBCAP_DCT_DUAL BIT(0) | |
245 | ||
246 | #define EXT_NB_MCA_CFG 0x180 | |
247 | ||
248 | /* MSRs */ | |
249 | #define MSR_MCGCTL_NBE BIT(4) | |
250 | ||
251 | enum amd_families { | |
252 | K8_CPUS = 0, | |
253 | F10_CPUS, | |
254 | F15_CPUS, | |
255 | F15_M30H_CPUS, | |
256 | F15_M60H_CPUS, | |
257 | F16_CPUS, | |
258 | F16_M30H_CPUS, | |
259 | NUM_FAMILIES, | |
260 | }; | |
261 | ||
262 | /* Error injection control structure */ | |
263 | struct error_injection { | |
264 | u32 section; | |
265 | u32 word; | |
266 | u32 bit_map; | |
267 | }; | |
268 | ||
269 | /* low and high part of PCI config space regs */ | |
270 | struct reg_pair { | |
271 | u32 lo, hi; | |
272 | }; | |
273 | ||
274 | /* | |
275 | * See F1x[1, 0][7C:40] DRAM Base/Limit Registers | |
276 | */ | |
277 | struct dram_range { | |
278 | struct reg_pair base; | |
279 | struct reg_pair lim; | |
280 | }; | |
281 | ||
282 | /* A DCT chip selects collection */ | |
283 | struct chip_select { | |
284 | u32 csbases[NUM_CHIPSELECTS]; | |
285 | u8 b_cnt; | |
286 | ||
287 | u32 csmasks[NUM_CHIPSELECTS]; | |
288 | u8 m_cnt; | |
289 | }; | |
290 | ||
291 | struct amd64_pvt { | |
292 | struct low_ops *ops; | |
293 | ||
294 | /* pci_device handles which we utilize */ | |
295 | struct pci_dev *F1, *F2, *F3; | |
296 | ||
297 | u16 mc_node_id; /* MC index of this MC node */ | |
298 | u8 fam; /* CPU family */ | |
299 | u8 model; /* ... model */ | |
300 | u8 stepping; /* ... stepping */ | |
301 | ||
302 | int ext_model; /* extended model value of this node */ | |
303 | int channel_count; | |
304 | ||
305 | /* Raw registers */ | |
306 | u32 dclr0; /* DRAM Configuration Low DCT0 reg */ | |
307 | u32 dclr1; /* DRAM Configuration Low DCT1 reg */ | |
308 | u32 dchr0; /* DRAM Configuration High DCT0 reg */ | |
309 | u32 dchr1; /* DRAM Configuration High DCT1 reg */ | |
310 | u32 nbcap; /* North Bridge Capabilities */ | |
311 | u32 nbcfg; /* F10 North Bridge Configuration */ | |
312 | u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */ | |
313 | u32 dhar; /* DRAM Hoist reg */ | |
314 | u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */ | |
315 | u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */ | |
316 | ||
317 | /* one for each DCT */ | |
318 | struct chip_select csels[2]; | |
319 | ||
320 | /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */ | |
321 | struct dram_range ranges[DRAM_RANGES]; | |
322 | ||
323 | u64 top_mem; /* top of memory below 4GB */ | |
324 | u64 top_mem2; /* top of memory above 4GB */ | |
325 | ||
326 | u32 dct_sel_lo; /* DRAM Controller Select Low */ | |
327 | u32 dct_sel_hi; /* DRAM Controller Select High */ | |
328 | u32 online_spare; /* On-Line spare Reg */ | |
329 | ||
330 | /* x4 or x8 syndromes in use */ | |
331 | u8 ecc_sym_sz; | |
332 | ||
333 | /* place to store error injection parameters prior to issue */ | |
334 | struct error_injection injection; | |
335 | ||
336 | /* cache the dram_type */ | |
337 | enum mem_type dram_type; | |
338 | }; | |
339 | ||
340 | enum err_codes { | |
341 | DECODE_OK = 0, | |
342 | ERR_NODE = -1, | |
343 | ERR_CSROW = -2, | |
344 | ERR_CHANNEL = -3, | |
345 | }; | |
346 | ||
347 | struct err_info { | |
348 | int err_code; | |
349 | struct mem_ctl_info *src_mci; | |
350 | int csrow; | |
351 | int channel; | |
352 | u16 syndrome; | |
353 | u32 page; | |
354 | u32 offset; | |
355 | }; | |
356 | ||
357 | static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i) | |
358 | { | |
359 | u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8; | |
360 | ||
361 | if (boot_cpu_data.x86 == 0xf) | |
362 | return addr; | |
363 | ||
364 | return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr; | |
365 | } | |
366 | ||
367 | static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i) | |
368 | { | |
369 | u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff; | |
370 | ||
371 | if (boot_cpu_data.x86 == 0xf) | |
372 | return lim; | |
373 | ||
374 | return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim; | |
375 | } | |
376 | ||
377 | static inline u16 extract_syndrome(u64 status) | |
378 | { | |
379 | return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00); | |
380 | } | |
381 | ||
382 | static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt) | |
383 | { | |
384 | if (pvt->fam == 0x15 && pvt->model >= 0x30) | |
385 | return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) | | |
386 | ((pvt->dct_sel_lo >> 6) & 0x3); | |
387 | ||
388 | return ((pvt)->dct_sel_lo >> 6) & 0x3; | |
389 | } | |
390 | /* | |
391 | * per-node ECC settings descriptor | |
392 | */ | |
393 | struct ecc_settings { | |
394 | u32 old_nbctl; | |
395 | bool nbctl_valid; | |
396 | ||
397 | struct flags { | |
398 | unsigned long nb_mce_enable:1; | |
399 | unsigned long nb_ecc_prev:1; | |
400 | } flags; | |
401 | }; | |
402 | ||
403 | #ifdef CONFIG_EDAC_DEBUG | |
404 | extern const struct attribute_group amd64_edac_dbg_group; | |
405 | #endif | |
406 | ||
407 | #ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION | |
408 | extern const struct attribute_group amd64_edac_inj_group; | |
409 | #endif | |
410 | ||
411 | /* | |
412 | * Each of the PCI Device IDs types have their own set of hardware accessor | |
413 | * functions and per device encoding/decoding logic. | |
414 | */ | |
415 | struct low_ops { | |
416 | int (*early_channel_count) (struct amd64_pvt *pvt); | |
417 | void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr, | |
418 | struct err_info *); | |
419 | int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct, | |
420 | unsigned cs_mode, int cs_mask_nr); | |
421 | }; | |
422 | ||
423 | struct amd64_family_type { | |
424 | const char *ctl_name; | |
425 | u16 f1_id, f3_id; | |
426 | struct low_ops ops; | |
427 | }; | |
428 | ||
429 | int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, | |
430 | u32 *val, const char *func); | |
431 | int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset, | |
432 | u32 val, const char *func); | |
433 | ||
434 | #define amd64_read_pci_cfg(pdev, offset, val) \ | |
435 | __amd64_read_pci_cfg_dword(pdev, offset, val, __func__) | |
436 | ||
437 | #define amd64_write_pci_cfg(pdev, offset, val) \ | |
438 | __amd64_write_pci_cfg_dword(pdev, offset, val, __func__) | |
439 | ||
440 | int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, | |
441 | u64 *hole_offset, u64 *hole_size); | |
442 | ||
443 | #define to_mci(k) container_of(k, struct mem_ctl_info, dev) | |
444 | ||
445 | /* Injection helpers */ | |
446 | static inline void disable_caches(void *dummy) | |
447 | { | |
448 | write_cr0(read_cr0() | X86_CR0_CD); | |
449 | wbinvd(); | |
450 | } | |
451 | ||
452 | static inline void enable_caches(void *dummy) | |
453 | { | |
454 | write_cr0(read_cr0() & ~X86_CR0_CD); | |
455 | } | |
456 | ||
457 | static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i) | |
458 | { | |
459 | if (pvt->fam == 0x15 && pvt->model >= 0x30) { | |
460 | u32 tmp; | |
461 | amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp); | |
462 | return (u8) tmp & 0xF; | |
463 | } | |
464 | return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7; | |
465 | } | |
466 | ||
467 | static inline u8 dhar_valid(struct amd64_pvt *pvt) | |
468 | { | |
469 | if (pvt->fam == 0x15 && pvt->model >= 0x30) { | |
470 | u32 tmp; | |
471 | amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp); | |
472 | return (tmp >> 1) & BIT(0); | |
473 | } | |
474 | return (pvt)->dhar & BIT(0); | |
475 | } | |
476 | ||
477 | static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt) | |
478 | { | |
479 | if (pvt->fam == 0x15 && pvt->model >= 0x30) { | |
480 | u32 tmp; | |
481 | amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp); | |
482 | return (tmp >> 11) & 0x1FFF; | |
483 | } | |
484 | return (pvt)->dct_sel_lo & 0xFFFFF800; | |
485 | } |