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1 | /* | |
2 | * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible | |
3 | * | |
4 | * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk> | |
5 | * Copyright (C) 2016 Freescale Semiconductor Inc. | |
6 | * | |
7 | * This file is licensed under the terms of the GNU General Public License | |
8 | * version 2. This program is licensed "as is" without any warranty of any | |
9 | * kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/spinlock.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/of.h> | |
17 | #include <linux/of_gpio.h> | |
18 | #include <linux/of_address.h> | |
19 | #include <linux/of_irq.h> | |
20 | #include <linux/of_platform.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/irq.h> | |
23 | #include <linux/gpio/driver.h> | |
24 | ||
25 | #define MPC8XXX_GPIO_PINS 32 | |
26 | ||
27 | #define GPIO_DIR 0x00 | |
28 | #define GPIO_ODR 0x04 | |
29 | #define GPIO_DAT 0x08 | |
30 | #define GPIO_IER 0x0c | |
31 | #define GPIO_IMR 0x10 | |
32 | #define GPIO_ICR 0x14 | |
33 | #define GPIO_ICR2 0x18 | |
34 | ||
35 | struct mpc8xxx_gpio_chip { | |
36 | struct gpio_chip gc; | |
37 | void __iomem *regs; | |
38 | raw_spinlock_t lock; | |
39 | ||
40 | int (*direction_output)(struct gpio_chip *chip, | |
41 | unsigned offset, int value); | |
42 | ||
43 | struct irq_domain *irq; | |
44 | unsigned int irqn; | |
45 | }; | |
46 | ||
47 | /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs | |
48 | * defined as output cannot be determined by reading GPDAT register, | |
49 | * so we use shadow data register instead. The status of input pins | |
50 | * is determined by reading GPDAT register. | |
51 | */ | |
52 | static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio) | |
53 | { | |
54 | u32 val; | |
55 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); | |
56 | u32 out_mask, out_shadow; | |
57 | ||
58 | out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); | |
59 | val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask; | |
60 | out_shadow = gc->bgpio_data & out_mask; | |
61 | ||
62 | return !!((val | out_shadow) & gc->pin2mask(gc, gpio)); | |
63 | } | |
64 | ||
65 | static int mpc5121_gpio_dir_out(struct gpio_chip *gc, | |
66 | unsigned int gpio, int val) | |
67 | { | |
68 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); | |
69 | /* GPIO 28..31 are input only on MPC5121 */ | |
70 | if (gpio >= 28) | |
71 | return -EINVAL; | |
72 | ||
73 | return mpc8xxx_gc->direction_output(gc, gpio, val); | |
74 | } | |
75 | ||
76 | static int mpc5125_gpio_dir_out(struct gpio_chip *gc, | |
77 | unsigned int gpio, int val) | |
78 | { | |
79 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); | |
80 | /* GPIO 0..3 are input only on MPC5125 */ | |
81 | if (gpio <= 3) | |
82 | return -EINVAL; | |
83 | ||
84 | return mpc8xxx_gc->direction_output(gc, gpio, val); | |
85 | } | |
86 | ||
87 | static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset) | |
88 | { | |
89 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); | |
90 | ||
91 | if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS) | |
92 | return irq_create_mapping(mpc8xxx_gc->irq, offset); | |
93 | else | |
94 | return -ENXIO; | |
95 | } | |
96 | ||
97 | static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc) | |
98 | { | |
99 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc); | |
100 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
101 | struct gpio_chip *gc = &mpc8xxx_gc->gc; | |
102 | unsigned int mask; | |
103 | ||
104 | mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER) | |
105 | & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR); | |
106 | if (mask) | |
107 | generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, | |
108 | 32 - ffs(mask))); | |
109 | if (chip->irq_eoi) | |
110 | chip->irq_eoi(&desc->irq_data); | |
111 | } | |
112 | ||
113 | static void mpc8xxx_irq_unmask(struct irq_data *d) | |
114 | { | |
115 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); | |
116 | struct gpio_chip *gc = &mpc8xxx_gc->gc; | |
117 | unsigned long flags; | |
118 | ||
119 | raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
120 | ||
121 | gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, | |
122 | gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) | |
123 | | gc->pin2mask(gc, irqd_to_hwirq(d))); | |
124 | ||
125 | raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
126 | } | |
127 | ||
128 | static void mpc8xxx_irq_mask(struct irq_data *d) | |
129 | { | |
130 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); | |
131 | struct gpio_chip *gc = &mpc8xxx_gc->gc; | |
132 | unsigned long flags; | |
133 | ||
134 | raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
135 | ||
136 | gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, | |
137 | gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) | |
138 | & ~(gc->pin2mask(gc, irqd_to_hwirq(d)))); | |
139 | ||
140 | raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
141 | } | |
142 | ||
143 | static void mpc8xxx_irq_ack(struct irq_data *d) | |
144 | { | |
145 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); | |
146 | struct gpio_chip *gc = &mpc8xxx_gc->gc; | |
147 | ||
148 | gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, | |
149 | gc->pin2mask(gc, irqd_to_hwirq(d))); | |
150 | } | |
151 | ||
152 | static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) | |
153 | { | |
154 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); | |
155 | struct gpio_chip *gc = &mpc8xxx_gc->gc; | |
156 | unsigned long flags; | |
157 | ||
158 | switch (flow_type) { | |
159 | case IRQ_TYPE_EDGE_FALLING: | |
160 | raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
161 | gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, | |
162 | gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) | |
163 | | gc->pin2mask(gc, irqd_to_hwirq(d))); | |
164 | raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
165 | break; | |
166 | ||
167 | case IRQ_TYPE_EDGE_BOTH: | |
168 | raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
169 | gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, | |
170 | gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) | |
171 | & ~(gc->pin2mask(gc, irqd_to_hwirq(d)))); | |
172 | raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
173 | break; | |
174 | ||
175 | default: | |
176 | return -EINVAL; | |
177 | } | |
178 | ||
179 | return 0; | |
180 | } | |
181 | ||
182 | static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type) | |
183 | { | |
184 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); | |
185 | struct gpio_chip *gc = &mpc8xxx_gc->gc; | |
186 | unsigned long gpio = irqd_to_hwirq(d); | |
187 | void __iomem *reg; | |
188 | unsigned int shift; | |
189 | unsigned long flags; | |
190 | ||
191 | if (gpio < 16) { | |
192 | reg = mpc8xxx_gc->regs + GPIO_ICR; | |
193 | shift = (15 - gpio) * 2; | |
194 | } else { | |
195 | reg = mpc8xxx_gc->regs + GPIO_ICR2; | |
196 | shift = (15 - (gpio % 16)) * 2; | |
197 | } | |
198 | ||
199 | switch (flow_type) { | |
200 | case IRQ_TYPE_EDGE_FALLING: | |
201 | case IRQ_TYPE_LEVEL_LOW: | |
202 | raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
203 | gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) | |
204 | | (2 << shift)); | |
205 | raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
206 | break; | |
207 | ||
208 | case IRQ_TYPE_EDGE_RISING: | |
209 | case IRQ_TYPE_LEVEL_HIGH: | |
210 | raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
211 | gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) | |
212 | | (1 << shift)); | |
213 | raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
214 | break; | |
215 | ||
216 | case IRQ_TYPE_EDGE_BOTH: | |
217 | raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | |
218 | gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))); | |
219 | raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | |
220 | break; | |
221 | ||
222 | default: | |
223 | return -EINVAL; | |
224 | } | |
225 | ||
226 | return 0; | |
227 | } | |
228 | ||
229 | static struct irq_chip mpc8xxx_irq_chip = { | |
230 | .name = "mpc8xxx-gpio", | |
231 | .irq_unmask = mpc8xxx_irq_unmask, | |
232 | .irq_mask = mpc8xxx_irq_mask, | |
233 | .irq_ack = mpc8xxx_irq_ack, | |
234 | /* this might get overwritten in mpc8xxx_probe() */ | |
235 | .irq_set_type = mpc8xxx_irq_set_type, | |
236 | }; | |
237 | ||
238 | static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq, | |
239 | irq_hw_number_t hwirq) | |
240 | { | |
241 | irq_set_chip_data(irq, h->host_data); | |
242 | irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq); | |
243 | ||
244 | return 0; | |
245 | } | |
246 | ||
247 | static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = { | |
248 | .map = mpc8xxx_gpio_irq_map, | |
249 | .xlate = irq_domain_xlate_twocell, | |
250 | }; | |
251 | ||
252 | struct mpc8xxx_gpio_devtype { | |
253 | int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int); | |
254 | int (*gpio_get)(struct gpio_chip *, unsigned int); | |
255 | int (*irq_set_type)(struct irq_data *, unsigned int); | |
256 | }; | |
257 | ||
258 | static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = { | |
259 | .gpio_dir_out = mpc5121_gpio_dir_out, | |
260 | .irq_set_type = mpc512x_irq_set_type, | |
261 | }; | |
262 | ||
263 | static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = { | |
264 | .gpio_dir_out = mpc5125_gpio_dir_out, | |
265 | .irq_set_type = mpc512x_irq_set_type, | |
266 | }; | |
267 | ||
268 | static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = { | |
269 | .gpio_get = mpc8572_gpio_get, | |
270 | }; | |
271 | ||
272 | static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = { | |
273 | .irq_set_type = mpc8xxx_irq_set_type, | |
274 | }; | |
275 | ||
276 | static const struct of_device_id mpc8xxx_gpio_ids[] = { | |
277 | { .compatible = "fsl,mpc8349-gpio", }, | |
278 | { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, }, | |
279 | { .compatible = "fsl,mpc8610-gpio", }, | |
280 | { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, }, | |
281 | { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, }, | |
282 | { .compatible = "fsl,pq3-gpio", }, | |
283 | { .compatible = "fsl,qoriq-gpio", }, | |
284 | {} | |
285 | }; | |
286 | ||
287 | static int mpc8xxx_probe(struct platform_device *pdev) | |
288 | { | |
289 | struct device_node *np = pdev->dev.of_node; | |
290 | struct mpc8xxx_gpio_chip *mpc8xxx_gc; | |
291 | struct gpio_chip *gc; | |
292 | const struct mpc8xxx_gpio_devtype *devtype = | |
293 | of_device_get_match_data(&pdev->dev); | |
294 | int ret; | |
295 | ||
296 | mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL); | |
297 | if (!mpc8xxx_gc) | |
298 | return -ENOMEM; | |
299 | ||
300 | platform_set_drvdata(pdev, mpc8xxx_gc); | |
301 | ||
302 | raw_spin_lock_init(&mpc8xxx_gc->lock); | |
303 | ||
304 | mpc8xxx_gc->regs = of_iomap(np, 0); | |
305 | if (!mpc8xxx_gc->regs) | |
306 | return -ENOMEM; | |
307 | ||
308 | gc = &mpc8xxx_gc->gc; | |
309 | ||
310 | if (of_property_read_bool(np, "little-endian")) { | |
311 | ret = bgpio_init(gc, &pdev->dev, 4, | |
312 | mpc8xxx_gc->regs + GPIO_DAT, | |
313 | NULL, NULL, | |
314 | mpc8xxx_gc->regs + GPIO_DIR, NULL, | |
315 | BGPIOF_BIG_ENDIAN); | |
316 | if (ret) | |
317 | goto err; | |
318 | dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n"); | |
319 | } else { | |
320 | ret = bgpio_init(gc, &pdev->dev, 4, | |
321 | mpc8xxx_gc->regs + GPIO_DAT, | |
322 | NULL, NULL, | |
323 | mpc8xxx_gc->regs + GPIO_DIR, NULL, | |
324 | BGPIOF_BIG_ENDIAN | |
325 | | BGPIOF_BIG_ENDIAN_BYTE_ORDER); | |
326 | if (ret) | |
327 | goto err; | |
328 | dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n"); | |
329 | } | |
330 | ||
331 | mpc8xxx_gc->direction_output = gc->direction_output; | |
332 | ||
333 | if (!devtype) | |
334 | devtype = &mpc8xxx_gpio_devtype_default; | |
335 | ||
336 | /* | |
337 | * It's assumed that only a single type of gpio controller is available | |
338 | * on the current machine, so overwriting global data is fine. | |
339 | */ | |
340 | mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type; | |
341 | ||
342 | if (devtype->gpio_dir_out) | |
343 | gc->direction_output = devtype->gpio_dir_out; | |
344 | if (devtype->gpio_get) | |
345 | gc->get = devtype->gpio_get; | |
346 | ||
347 | gc->to_irq = mpc8xxx_gpio_to_irq; | |
348 | ||
349 | ret = gpiochip_add_data(gc, mpc8xxx_gc); | |
350 | if (ret) { | |
351 | pr_err("%s: GPIO chip registration failed with status %d\n", | |
352 | np->full_name, ret); | |
353 | goto err; | |
354 | } | |
355 | ||
356 | mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0); | |
357 | if (!mpc8xxx_gc->irqn) | |
358 | return 0; | |
359 | ||
360 | mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS, | |
361 | &mpc8xxx_gpio_irq_ops, mpc8xxx_gc); | |
362 | if (!mpc8xxx_gc->irq) | |
363 | return 0; | |
364 | ||
365 | /* ack and mask all irqs */ | |
366 | gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff); | |
367 | gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0); | |
368 | ||
369 | irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, | |
370 | mpc8xxx_gpio_irq_cascade, mpc8xxx_gc); | |
371 | return 0; | |
372 | err: | |
373 | iounmap(mpc8xxx_gc->regs); | |
374 | return ret; | |
375 | } | |
376 | ||
377 | static int mpc8xxx_remove(struct platform_device *pdev) | |
378 | { | |
379 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev); | |
380 | ||
381 | if (mpc8xxx_gc->irq) { | |
382 | irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL); | |
383 | irq_domain_remove(mpc8xxx_gc->irq); | |
384 | } | |
385 | ||
386 | gpiochip_remove(&mpc8xxx_gc->gc); | |
387 | iounmap(mpc8xxx_gc->regs); | |
388 | ||
389 | return 0; | |
390 | } | |
391 | ||
392 | static struct platform_driver mpc8xxx_plat_driver = { | |
393 | .probe = mpc8xxx_probe, | |
394 | .remove = mpc8xxx_remove, | |
395 | .driver = { | |
396 | .name = "gpio-mpc8xxx", | |
397 | .of_match_table = mpc8xxx_gpio_ids, | |
398 | }, | |
399 | }; | |
400 | ||
401 | static int __init mpc8xxx_init(void) | |
402 | { | |
403 | return platform_driver_register(&mpc8xxx_plat_driver); | |
404 | } | |
405 | ||
406 | arch_initcall(mpc8xxx_init); |