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1 | /* | |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/dma-fence-array.h> | |
29 | #include <linux/interval_tree_generic.h> | |
30 | #include <linux/idr.h> | |
31 | #include <drm/drmP.h> | |
32 | #include <drm/amdgpu_drm.h> | |
33 | #include "amdgpu.h" | |
34 | #include "amdgpu_trace.h" | |
35 | #include "amdgpu_amdkfd.h" | |
36 | #include "amdgpu_gmc.h" | |
37 | ||
38 | /** | |
39 | * DOC: GPUVM | |
40 | * | |
41 | * GPUVM is similar to the legacy gart on older asics, however | |
42 | * rather than there being a single global gart table | |
43 | * for the entire GPU, there are multiple VM page tables active | |
44 | * at any given time. The VM page tables can contain a mix | |
45 | * vram pages and system memory pages and system memory pages | |
46 | * can be mapped as snooped (cached system pages) or unsnooped | |
47 | * (uncached system pages). | |
48 | * Each VM has an ID associated with it and there is a page table | |
49 | * associated with each VMID. When execting a command buffer, | |
50 | * the kernel tells the the ring what VMID to use for that command | |
51 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
52 | * The userspace drivers maintain their own address space and the kernel | |
53 | * sets up their pages tables accordingly when they submit their | |
54 | * command buffers and a VMID is assigned. | |
55 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
56 | * SI supports 16. | |
57 | */ | |
58 | ||
59 | #define START(node) ((node)->start) | |
60 | #define LAST(node) ((node)->last) | |
61 | ||
62 | INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last, | |
63 | START, LAST, static, amdgpu_vm_it) | |
64 | ||
65 | #undef START | |
66 | #undef LAST | |
67 | ||
68 | /** | |
69 | * struct amdgpu_pte_update_params - Local structure | |
70 | * | |
71 | * Encapsulate some VM table update parameters to reduce | |
72 | * the number of function parameters | |
73 | * | |
74 | */ | |
75 | struct amdgpu_pte_update_params { | |
76 | ||
77 | /** | |
78 | * @adev: amdgpu device we do this update for | |
79 | */ | |
80 | struct amdgpu_device *adev; | |
81 | ||
82 | /** | |
83 | * @vm: optional amdgpu_vm we do this update for | |
84 | */ | |
85 | struct amdgpu_vm *vm; | |
86 | ||
87 | /** | |
88 | * @src: address where to copy page table entries from | |
89 | */ | |
90 | uint64_t src; | |
91 | ||
92 | /** | |
93 | * @ib: indirect buffer to fill with commands | |
94 | */ | |
95 | struct amdgpu_ib *ib; | |
96 | ||
97 | /** | |
98 | * @func: Function which actually does the update | |
99 | */ | |
100 | void (*func)(struct amdgpu_pte_update_params *params, | |
101 | struct amdgpu_bo *bo, uint64_t pe, | |
102 | uint64_t addr, unsigned count, uint32_t incr, | |
103 | uint64_t flags); | |
104 | /** | |
105 | * @pages_addr: | |
106 | * | |
107 | * DMA addresses to use for mapping, used during VM update by CPU | |
108 | */ | |
109 | dma_addr_t *pages_addr; | |
110 | ||
111 | /** | |
112 | * @kptr: | |
113 | * | |
114 | * Kernel pointer of PD/PT BO that needs to be updated, | |
115 | * used during VM update by CPU | |
116 | */ | |
117 | void *kptr; | |
118 | }; | |
119 | ||
120 | /** | |
121 | * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback | |
122 | */ | |
123 | struct amdgpu_prt_cb { | |
124 | ||
125 | /** | |
126 | * @adev: amdgpu device | |
127 | */ | |
128 | struct amdgpu_device *adev; | |
129 | ||
130 | /** | |
131 | * @cb: callback | |
132 | */ | |
133 | struct dma_fence_cb cb; | |
134 | }; | |
135 | ||
136 | /** | |
137 | * amdgpu_vm_level_shift - return the addr shift for each level | |
138 | * | |
139 | * @adev: amdgpu_device pointer | |
140 | * @level: VMPT level | |
141 | * | |
142 | * Returns: | |
143 | * The number of bits the pfn needs to be right shifted for a level. | |
144 | */ | |
145 | static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev, | |
146 | unsigned level) | |
147 | { | |
148 | unsigned shift = 0xff; | |
149 | ||
150 | switch (level) { | |
151 | case AMDGPU_VM_PDB2: | |
152 | case AMDGPU_VM_PDB1: | |
153 | case AMDGPU_VM_PDB0: | |
154 | shift = 9 * (AMDGPU_VM_PDB0 - level) + | |
155 | adev->vm_manager.block_size; | |
156 | break; | |
157 | case AMDGPU_VM_PTB: | |
158 | shift = 0; | |
159 | break; | |
160 | default: | |
161 | dev_err(adev->dev, "the level%d isn't supported.\n", level); | |
162 | } | |
163 | ||
164 | return shift; | |
165 | } | |
166 | ||
167 | /** | |
168 | * amdgpu_vm_num_entries - return the number of entries in a PD/PT | |
169 | * | |
170 | * @adev: amdgpu_device pointer | |
171 | * @level: VMPT level | |
172 | * | |
173 | * Returns: | |
174 | * The number of entries in a page directory or page table. | |
175 | */ | |
176 | static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev, | |
177 | unsigned level) | |
178 | { | |
179 | unsigned shift = amdgpu_vm_level_shift(adev, | |
180 | adev->vm_manager.root_level); | |
181 | ||
182 | if (level == adev->vm_manager.root_level) | |
183 | /* For the root directory */ | |
184 | return round_up(adev->vm_manager.max_pfn, 1 << shift) >> shift; | |
185 | else if (level != AMDGPU_VM_PTB) | |
186 | /* Everything in between */ | |
187 | return 512; | |
188 | else | |
189 | /* For the page tables on the leaves */ | |
190 | return AMDGPU_VM_PTE_COUNT(adev); | |
191 | } | |
192 | ||
193 | /** | |
194 | * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT | |
195 | * | |
196 | * @adev: amdgpu_device pointer | |
197 | * @level: VMPT level | |
198 | * | |
199 | * Returns: | |
200 | * The mask to extract the entry number of a PD/PT from an address. | |
201 | */ | |
202 | static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev, | |
203 | unsigned int level) | |
204 | { | |
205 | if (level <= adev->vm_manager.root_level) | |
206 | return 0xffffffff; | |
207 | else if (level != AMDGPU_VM_PTB) | |
208 | return 0x1ff; | |
209 | else | |
210 | return AMDGPU_VM_PTE_COUNT(adev) - 1; | |
211 | } | |
212 | ||
213 | /** | |
214 | * amdgpu_vm_bo_size - returns the size of the BOs in bytes | |
215 | * | |
216 | * @adev: amdgpu_device pointer | |
217 | * @level: VMPT level | |
218 | * | |
219 | * Returns: | |
220 | * The size of the BO for a page directory or page table in bytes. | |
221 | */ | |
222 | static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level) | |
223 | { | |
224 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8); | |
225 | } | |
226 | ||
227 | /** | |
228 | * amdgpu_vm_bo_evicted - vm_bo is evicted | |
229 | * | |
230 | * @vm_bo: vm_bo which is evicted | |
231 | * | |
232 | * State for PDs/PTs and per VM BOs which are not at the location they should | |
233 | * be. | |
234 | */ | |
235 | static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo) | |
236 | { | |
237 | struct amdgpu_vm *vm = vm_bo->vm; | |
238 | struct amdgpu_bo *bo = vm_bo->bo; | |
239 | ||
240 | vm_bo->moved = true; | |
241 | if (bo->tbo.type == ttm_bo_type_kernel) | |
242 | list_move(&vm_bo->vm_status, &vm->evicted); | |
243 | else | |
244 | list_move_tail(&vm_bo->vm_status, &vm->evicted); | |
245 | } | |
246 | ||
247 | /** | |
248 | * amdgpu_vm_bo_relocated - vm_bo is reloacted | |
249 | * | |
250 | * @vm_bo: vm_bo which is relocated | |
251 | * | |
252 | * State for PDs/PTs which needs to update their parent PD. | |
253 | */ | |
254 | static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo) | |
255 | { | |
256 | list_move(&vm_bo->vm_status, &vm_bo->vm->relocated); | |
257 | } | |
258 | ||
259 | /** | |
260 | * amdgpu_vm_bo_moved - vm_bo is moved | |
261 | * | |
262 | * @vm_bo: vm_bo which is moved | |
263 | * | |
264 | * State for per VM BOs which are moved, but that change is not yet reflected | |
265 | * in the page tables. | |
266 | */ | |
267 | static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo) | |
268 | { | |
269 | list_move(&vm_bo->vm_status, &vm_bo->vm->moved); | |
270 | } | |
271 | ||
272 | /** | |
273 | * amdgpu_vm_bo_idle - vm_bo is idle | |
274 | * | |
275 | * @vm_bo: vm_bo which is now idle | |
276 | * | |
277 | * State for PDs/PTs and per VM BOs which have gone through the state machine | |
278 | * and are now idle. | |
279 | */ | |
280 | static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo) | |
281 | { | |
282 | list_move(&vm_bo->vm_status, &vm_bo->vm->idle); | |
283 | vm_bo->moved = false; | |
284 | } | |
285 | ||
286 | /** | |
287 | * amdgpu_vm_bo_invalidated - vm_bo is invalidated | |
288 | * | |
289 | * @vm_bo: vm_bo which is now invalidated | |
290 | * | |
291 | * State for normal BOs which are invalidated and that change not yet reflected | |
292 | * in the PTs. | |
293 | */ | |
294 | static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo) | |
295 | { | |
296 | spin_lock(&vm_bo->vm->invalidated_lock); | |
297 | list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated); | |
298 | spin_unlock(&vm_bo->vm->invalidated_lock); | |
299 | } | |
300 | ||
301 | /** | |
302 | * amdgpu_vm_bo_done - vm_bo is done | |
303 | * | |
304 | * @vm_bo: vm_bo which is now done | |
305 | * | |
306 | * State for normal BOs which are invalidated and that change has been updated | |
307 | * in the PTs. | |
308 | */ | |
309 | static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo) | |
310 | { | |
311 | spin_lock(&vm_bo->vm->invalidated_lock); | |
312 | list_del_init(&vm_bo->vm_status); | |
313 | spin_unlock(&vm_bo->vm->invalidated_lock); | |
314 | } | |
315 | ||
316 | /** | |
317 | * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm | |
318 | * | |
319 | * @base: base structure for tracking BO usage in a VM | |
320 | * @vm: vm to which bo is to be added | |
321 | * @bo: amdgpu buffer object | |
322 | * | |
323 | * Initialize a bo_va_base structure and add it to the appropriate lists | |
324 | * | |
325 | */ | |
326 | static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, | |
327 | struct amdgpu_vm *vm, | |
328 | struct amdgpu_bo *bo) | |
329 | { | |
330 | base->vm = vm; | |
331 | base->bo = bo; | |
332 | base->next = NULL; | |
333 | INIT_LIST_HEAD(&base->vm_status); | |
334 | ||
335 | if (!bo) | |
336 | return; | |
337 | base->next = bo->vm_bo; | |
338 | bo->vm_bo = base; | |
339 | ||
340 | if (bo->tbo.resv != vm->root.base.bo->tbo.resv) | |
341 | return; | |
342 | ||
343 | vm->bulk_moveable = false; | |
344 | if (bo->tbo.type == ttm_bo_type_kernel) | |
345 | amdgpu_vm_bo_relocated(base); | |
346 | else | |
347 | amdgpu_vm_bo_idle(base); | |
348 | ||
349 | if (bo->preferred_domains & | |
350 | amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type)) | |
351 | return; | |
352 | ||
353 | /* | |
354 | * we checked all the prerequisites, but it looks like this per vm bo | |
355 | * is currently evicted. add the bo to the evicted list to make sure it | |
356 | * is validated on next vm use to avoid fault. | |
357 | * */ | |
358 | amdgpu_vm_bo_evicted(base); | |
359 | } | |
360 | ||
361 | /** | |
362 | * amdgpu_vm_pt_parent - get the parent page directory | |
363 | * | |
364 | * @pt: child page table | |
365 | * | |
366 | * Helper to get the parent entry for the child page table. NULL if we are at | |
367 | * the root page directory. | |
368 | */ | |
369 | static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt *pt) | |
370 | { | |
371 | struct amdgpu_bo *parent = pt->base.bo->parent; | |
372 | ||
373 | if (!parent) | |
374 | return NULL; | |
375 | ||
376 | return container_of(parent->vm_bo, struct amdgpu_vm_pt, base); | |
377 | } | |
378 | ||
379 | /** | |
380 | * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt | |
381 | */ | |
382 | struct amdgpu_vm_pt_cursor { | |
383 | uint64_t pfn; | |
384 | struct amdgpu_vm_pt *parent; | |
385 | struct amdgpu_vm_pt *entry; | |
386 | unsigned level; | |
387 | }; | |
388 | ||
389 | /** | |
390 | * amdgpu_vm_pt_start - start PD/PT walk | |
391 | * | |
392 | * @adev: amdgpu_device pointer | |
393 | * @vm: amdgpu_vm structure | |
394 | * @start: start address of the walk | |
395 | * @cursor: state to initialize | |
396 | * | |
397 | * Initialize a amdgpu_vm_pt_cursor to start a walk. | |
398 | */ | |
399 | static void amdgpu_vm_pt_start(struct amdgpu_device *adev, | |
400 | struct amdgpu_vm *vm, uint64_t start, | |
401 | struct amdgpu_vm_pt_cursor *cursor) | |
402 | { | |
403 | cursor->pfn = start; | |
404 | cursor->parent = NULL; | |
405 | cursor->entry = &vm->root; | |
406 | cursor->level = adev->vm_manager.root_level; | |
407 | } | |
408 | ||
409 | /** | |
410 | * amdgpu_vm_pt_descendant - go to child node | |
411 | * | |
412 | * @adev: amdgpu_device pointer | |
413 | * @cursor: current state | |
414 | * | |
415 | * Walk to the child node of the current node. | |
416 | * Returns: | |
417 | * True if the walk was possible, false otherwise. | |
418 | */ | |
419 | static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev, | |
420 | struct amdgpu_vm_pt_cursor *cursor) | |
421 | { | |
422 | unsigned mask, shift, idx; | |
423 | ||
424 | if (!cursor->entry->entries) | |
425 | return false; | |
426 | ||
427 | BUG_ON(!cursor->entry->base.bo); | |
428 | mask = amdgpu_vm_entries_mask(adev, cursor->level); | |
429 | shift = amdgpu_vm_level_shift(adev, cursor->level); | |
430 | ||
431 | ++cursor->level; | |
432 | idx = (cursor->pfn >> shift) & mask; | |
433 | cursor->parent = cursor->entry; | |
434 | cursor->entry = &cursor->entry->entries[idx]; | |
435 | return true; | |
436 | } | |
437 | ||
438 | /** | |
439 | * amdgpu_vm_pt_sibling - go to sibling node | |
440 | * | |
441 | * @adev: amdgpu_device pointer | |
442 | * @cursor: current state | |
443 | * | |
444 | * Walk to the sibling node of the current node. | |
445 | * Returns: | |
446 | * True if the walk was possible, false otherwise. | |
447 | */ | |
448 | static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev, | |
449 | struct amdgpu_vm_pt_cursor *cursor) | |
450 | { | |
451 | unsigned shift, num_entries; | |
452 | ||
453 | /* Root doesn't have a sibling */ | |
454 | if (!cursor->parent) | |
455 | return false; | |
456 | ||
457 | /* Go to our parents and see if we got a sibling */ | |
458 | shift = amdgpu_vm_level_shift(adev, cursor->level - 1); | |
459 | num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1); | |
460 | ||
461 | if (cursor->entry == &cursor->parent->entries[num_entries - 1]) | |
462 | return false; | |
463 | ||
464 | cursor->pfn += 1ULL << shift; | |
465 | cursor->pfn &= ~((1ULL << shift) - 1); | |
466 | ++cursor->entry; | |
467 | return true; | |
468 | } | |
469 | ||
470 | /** | |
471 | * amdgpu_vm_pt_ancestor - go to parent node | |
472 | * | |
473 | * @cursor: current state | |
474 | * | |
475 | * Walk to the parent node of the current node. | |
476 | * Returns: | |
477 | * True if the walk was possible, false otherwise. | |
478 | */ | |
479 | static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor *cursor) | |
480 | { | |
481 | if (!cursor->parent) | |
482 | return false; | |
483 | ||
484 | --cursor->level; | |
485 | cursor->entry = cursor->parent; | |
486 | cursor->parent = amdgpu_vm_pt_parent(cursor->parent); | |
487 | return true; | |
488 | } | |
489 | ||
490 | /** | |
491 | * amdgpu_vm_pt_next - get next PD/PT in hieratchy | |
492 | * | |
493 | * @adev: amdgpu_device pointer | |
494 | * @cursor: current state | |
495 | * | |
496 | * Walk the PD/PT tree to the next node. | |
497 | */ | |
498 | static void amdgpu_vm_pt_next(struct amdgpu_device *adev, | |
499 | struct amdgpu_vm_pt_cursor *cursor) | |
500 | { | |
501 | /* First try a newborn child */ | |
502 | if (amdgpu_vm_pt_descendant(adev, cursor)) | |
503 | return; | |
504 | ||
505 | /* If that didn't worked try to find a sibling */ | |
506 | while (!amdgpu_vm_pt_sibling(adev, cursor)) { | |
507 | /* No sibling, go to our parents and grandparents */ | |
508 | if (!amdgpu_vm_pt_ancestor(cursor)) { | |
509 | cursor->pfn = ~0ll; | |
510 | return; | |
511 | } | |
512 | } | |
513 | } | |
514 | ||
515 | /** | |
516 | * amdgpu_vm_pt_first_leaf - get first leaf PD/PT | |
517 | * | |
518 | * @adev: amdgpu_device pointer | |
519 | * @vm: amdgpu_vm structure | |
520 | * @start: start addr of the walk | |
521 | * @cursor: state to initialize | |
522 | * | |
523 | * Start a walk and go directly to the leaf node. | |
524 | */ | |
525 | static void amdgpu_vm_pt_first_leaf(struct amdgpu_device *adev, | |
526 | struct amdgpu_vm *vm, uint64_t start, | |
527 | struct amdgpu_vm_pt_cursor *cursor) | |
528 | { | |
529 | amdgpu_vm_pt_start(adev, vm, start, cursor); | |
530 | while (amdgpu_vm_pt_descendant(adev, cursor)); | |
531 | } | |
532 | ||
533 | /** | |
534 | * amdgpu_vm_pt_next_leaf - get next leaf PD/PT | |
535 | * | |
536 | * @adev: amdgpu_device pointer | |
537 | * @cursor: current state | |
538 | * | |
539 | * Walk the PD/PT tree to the next leaf node. | |
540 | */ | |
541 | static void amdgpu_vm_pt_next_leaf(struct amdgpu_device *adev, | |
542 | struct amdgpu_vm_pt_cursor *cursor) | |
543 | { | |
544 | amdgpu_vm_pt_next(adev, cursor); | |
545 | if (cursor->pfn != ~0ll) | |
546 | while (amdgpu_vm_pt_descendant(adev, cursor)); | |
547 | } | |
548 | ||
549 | /** | |
550 | * for_each_amdgpu_vm_pt_leaf - walk over all leaf PDs/PTs in the hierarchy | |
551 | */ | |
552 | #define for_each_amdgpu_vm_pt_leaf(adev, vm, start, end, cursor) \ | |
553 | for (amdgpu_vm_pt_first_leaf((adev), (vm), (start), &(cursor)); \ | |
554 | (cursor).pfn <= end; amdgpu_vm_pt_next_leaf((adev), &(cursor))) | |
555 | ||
556 | /** | |
557 | * amdgpu_vm_pt_first_dfs - start a deep first search | |
558 | * | |
559 | * @adev: amdgpu_device structure | |
560 | * @vm: amdgpu_vm structure | |
561 | * @cursor: state to initialize | |
562 | * | |
563 | * Starts a deep first traversal of the PD/PT tree. | |
564 | */ | |
565 | static void amdgpu_vm_pt_first_dfs(struct amdgpu_device *adev, | |
566 | struct amdgpu_vm *vm, | |
567 | struct amdgpu_vm_pt_cursor *cursor) | |
568 | { | |
569 | amdgpu_vm_pt_start(adev, vm, 0, cursor); | |
570 | while (amdgpu_vm_pt_descendant(adev, cursor)); | |
571 | } | |
572 | ||
573 | /** | |
574 | * amdgpu_vm_pt_next_dfs - get the next node for a deep first search | |
575 | * | |
576 | * @adev: amdgpu_device structure | |
577 | * @cursor: current state | |
578 | * | |
579 | * Move the cursor to the next node in a deep first search. | |
580 | */ | |
581 | static void amdgpu_vm_pt_next_dfs(struct amdgpu_device *adev, | |
582 | struct amdgpu_vm_pt_cursor *cursor) | |
583 | { | |
584 | if (!cursor->entry) | |
585 | return; | |
586 | ||
587 | if (!cursor->parent) | |
588 | cursor->entry = NULL; | |
589 | else if (amdgpu_vm_pt_sibling(adev, cursor)) | |
590 | while (amdgpu_vm_pt_descendant(adev, cursor)); | |
591 | else | |
592 | amdgpu_vm_pt_ancestor(cursor); | |
593 | } | |
594 | ||
595 | /** | |
596 | * for_each_amdgpu_vm_pt_dfs_safe - safe deep first search of all PDs/PTs | |
597 | */ | |
598 | #define for_each_amdgpu_vm_pt_dfs_safe(adev, vm, cursor, entry) \ | |
599 | for (amdgpu_vm_pt_first_dfs((adev), (vm), &(cursor)), \ | |
600 | (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor));\ | |
601 | (entry); (entry) = (cursor).entry, \ | |
602 | amdgpu_vm_pt_next_dfs((adev), &(cursor))) | |
603 | ||
604 | /** | |
605 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list | |
606 | * | |
607 | * @vm: vm providing the BOs | |
608 | * @validated: head of validation list | |
609 | * @entry: entry to add | |
610 | * | |
611 | * Add the page directory to the list of BOs to | |
612 | * validate for command submission. | |
613 | */ | |
614 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, | |
615 | struct list_head *validated, | |
616 | struct amdgpu_bo_list_entry *entry) | |
617 | { | |
618 | entry->priority = 0; | |
619 | entry->tv.bo = &vm->root.base.bo->tbo; | |
620 | /* One for the VM updates and one for the CS job */ | |
621 | entry->tv.num_shared = 2; | |
622 | entry->user_pages = NULL; | |
623 | list_add(&entry->tv.head, validated); | |
624 | } | |
625 | ||
626 | /** | |
627 | * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU | |
628 | * | |
629 | * @adev: amdgpu device pointer | |
630 | * @vm: vm providing the BOs | |
631 | * | |
632 | * Move all BOs to the end of LRU and remember their positions to put them | |
633 | * together. | |
634 | */ | |
635 | void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, | |
636 | struct amdgpu_vm *vm) | |
637 | { | |
638 | struct ttm_bo_global *glob = adev->mman.bdev.glob; | |
639 | struct amdgpu_vm_bo_base *bo_base; | |
640 | ||
641 | if (vm->bulk_moveable) { | |
642 | spin_lock(&glob->lru_lock); | |
643 | ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move); | |
644 | spin_unlock(&glob->lru_lock); | |
645 | return; | |
646 | } | |
647 | ||
648 | memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move)); | |
649 | ||
650 | spin_lock(&glob->lru_lock); | |
651 | list_for_each_entry(bo_base, &vm->idle, vm_status) { | |
652 | struct amdgpu_bo *bo = bo_base->bo; | |
653 | ||
654 | if (!bo->parent) | |
655 | continue; | |
656 | ||
657 | ttm_bo_move_to_lru_tail(&bo->tbo, &vm->lru_bulk_move); | |
658 | if (bo->shadow) | |
659 | ttm_bo_move_to_lru_tail(&bo->shadow->tbo, | |
660 | &vm->lru_bulk_move); | |
661 | } | |
662 | spin_unlock(&glob->lru_lock); | |
663 | ||
664 | vm->bulk_moveable = true; | |
665 | } | |
666 | ||
667 | /** | |
668 | * amdgpu_vm_validate_pt_bos - validate the page table BOs | |
669 | * | |
670 | * @adev: amdgpu device pointer | |
671 | * @vm: vm providing the BOs | |
672 | * @validate: callback to do the validation | |
673 | * @param: parameter for the validation callback | |
674 | * | |
675 | * Validate the page table BOs on command submission if neccessary. | |
676 | * | |
677 | * Returns: | |
678 | * Validation result. | |
679 | */ | |
680 | int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, | |
681 | int (*validate)(void *p, struct amdgpu_bo *bo), | |
682 | void *param) | |
683 | { | |
684 | struct amdgpu_vm_bo_base *bo_base, *tmp; | |
685 | int r = 0; | |
686 | ||
687 | vm->bulk_moveable &= list_empty(&vm->evicted); | |
688 | ||
689 | list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) { | |
690 | struct amdgpu_bo *bo = bo_base->bo; | |
691 | ||
692 | r = validate(param, bo); | |
693 | if (r) | |
694 | break; | |
695 | ||
696 | if (bo->tbo.type != ttm_bo_type_kernel) { | |
697 | amdgpu_vm_bo_moved(bo_base); | |
698 | } else { | |
699 | if (vm->use_cpu_for_update) | |
700 | r = amdgpu_bo_kmap(bo, NULL); | |
701 | else | |
702 | r = amdgpu_ttm_alloc_gart(&bo->tbo); | |
703 | if (r) | |
704 | break; | |
705 | if (bo->shadow) { | |
706 | r = amdgpu_ttm_alloc_gart(&bo->shadow->tbo); | |
707 | if (r) | |
708 | break; | |
709 | } | |
710 | amdgpu_vm_bo_relocated(bo_base); | |
711 | } | |
712 | } | |
713 | ||
714 | return r; | |
715 | } | |
716 | ||
717 | /** | |
718 | * amdgpu_vm_ready - check VM is ready for updates | |
719 | * | |
720 | * @vm: VM to check | |
721 | * | |
722 | * Check if all VM PDs/PTs are ready for updates | |
723 | * | |
724 | * Returns: | |
725 | * True if eviction list is empty. | |
726 | */ | |
727 | bool amdgpu_vm_ready(struct amdgpu_vm *vm) | |
728 | { | |
729 | return list_empty(&vm->evicted); | |
730 | } | |
731 | ||
732 | /** | |
733 | * amdgpu_vm_clear_bo - initially clear the PDs/PTs | |
734 | * | |
735 | * @adev: amdgpu_device pointer | |
736 | * @vm: VM to clear BO from | |
737 | * @bo: BO to clear | |
738 | * @level: level this BO is at | |
739 | * @pte_support_ats: indicate ATS support from PTE | |
740 | * | |
741 | * Root PD needs to be reserved when calling this. | |
742 | * | |
743 | * Returns: | |
744 | * 0 on success, errno otherwise. | |
745 | */ | |
746 | static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, | |
747 | struct amdgpu_vm *vm, struct amdgpu_bo *bo, | |
748 | unsigned level, bool pte_support_ats) | |
749 | { | |
750 | struct ttm_operation_ctx ctx = { true, false }; | |
751 | struct dma_fence *fence = NULL; | |
752 | unsigned entries, ats_entries; | |
753 | struct amdgpu_ring *ring; | |
754 | struct amdgpu_job *job; | |
755 | uint64_t addr; | |
756 | int r; | |
757 | ||
758 | entries = amdgpu_bo_size(bo) / 8; | |
759 | ||
760 | if (pte_support_ats) { | |
761 | if (level == adev->vm_manager.root_level) { | |
762 | ats_entries = amdgpu_vm_level_shift(adev, level); | |
763 | ats_entries += AMDGPU_GPU_PAGE_SHIFT; | |
764 | ats_entries = AMDGPU_GMC_HOLE_START >> ats_entries; | |
765 | ats_entries = min(ats_entries, entries); | |
766 | entries -= ats_entries; | |
767 | } else { | |
768 | ats_entries = entries; | |
769 | entries = 0; | |
770 | } | |
771 | } else { | |
772 | ats_entries = 0; | |
773 | } | |
774 | ||
775 | ring = container_of(vm->entity.rq->sched, struct amdgpu_ring, sched); | |
776 | ||
777 | r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); | |
778 | if (r) | |
779 | goto error; | |
780 | ||
781 | r = amdgpu_ttm_alloc_gart(&bo->tbo); | |
782 | if (r) | |
783 | return r; | |
784 | ||
785 | r = amdgpu_job_alloc_with_ib(adev, 64, &job); | |
786 | if (r) | |
787 | goto error; | |
788 | ||
789 | addr = amdgpu_bo_gpu_offset(bo); | |
790 | if (ats_entries) { | |
791 | uint64_t ats_value; | |
792 | ||
793 | ats_value = AMDGPU_PTE_DEFAULT_ATC; | |
794 | if (level != AMDGPU_VM_PTB) | |
795 | ats_value |= AMDGPU_PDE_PTE; | |
796 | ||
797 | amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0, | |
798 | ats_entries, 0, ats_value); | |
799 | addr += ats_entries * 8; | |
800 | } | |
801 | ||
802 | if (entries) | |
803 | amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0, | |
804 | entries, 0, 0); | |
805 | ||
806 | amdgpu_ring_pad_ib(ring, &job->ibs[0]); | |
807 | ||
808 | WARN_ON(job->ibs[0].length_dw > 64); | |
809 | r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv, | |
810 | AMDGPU_FENCE_OWNER_UNDEFINED, false); | |
811 | if (r) | |
812 | goto error_free; | |
813 | ||
814 | r = amdgpu_job_submit(job, &vm->entity, AMDGPU_FENCE_OWNER_UNDEFINED, | |
815 | &fence); | |
816 | if (r) | |
817 | goto error_free; | |
818 | ||
819 | amdgpu_bo_fence(bo, fence, true); | |
820 | dma_fence_put(fence); | |
821 | ||
822 | if (bo->shadow) | |
823 | return amdgpu_vm_clear_bo(adev, vm, bo->shadow, | |
824 | level, pte_support_ats); | |
825 | ||
826 | return 0; | |
827 | ||
828 | error_free: | |
829 | amdgpu_job_free(job); | |
830 | ||
831 | error: | |
832 | return r; | |
833 | } | |
834 | ||
835 | /** | |
836 | * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation | |
837 | * | |
838 | * @adev: amdgpu_device pointer | |
839 | * @vm: requesting vm | |
840 | * @bp: resulting BO allocation parameters | |
841 | */ | |
842 | static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm, | |
843 | int level, struct amdgpu_bo_param *bp) | |
844 | { | |
845 | memset(bp, 0, sizeof(*bp)); | |
846 | ||
847 | bp->size = amdgpu_vm_bo_size(adev, level); | |
848 | bp->byte_align = AMDGPU_GPU_PAGE_SIZE; | |
849 | bp->domain = AMDGPU_GEM_DOMAIN_VRAM; | |
850 | if (bp->size <= PAGE_SIZE && adev->asic_type >= CHIP_VEGA10 && | |
851 | adev->flags & AMD_IS_APU) | |
852 | bp->domain |= AMDGPU_GEM_DOMAIN_GTT; | |
853 | bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain); | |
854 | bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | | |
855 | AMDGPU_GEM_CREATE_CPU_GTT_USWC; | |
856 | if (vm->use_cpu_for_update) | |
857 | bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
858 | else if (!vm->root.base.bo || vm->root.base.bo->shadow) | |
859 | bp->flags |= AMDGPU_GEM_CREATE_SHADOW; | |
860 | bp->type = ttm_bo_type_kernel; | |
861 | if (vm->root.base.bo) | |
862 | bp->resv = vm->root.base.bo->tbo.resv; | |
863 | } | |
864 | ||
865 | /** | |
866 | * amdgpu_vm_alloc_pts - Allocate page tables. | |
867 | * | |
868 | * @adev: amdgpu_device pointer | |
869 | * @vm: VM to allocate page tables for | |
870 | * @saddr: Start address which needs to be allocated | |
871 | * @size: Size from start address we need. | |
872 | * | |
873 | * Make sure the page directories and page tables are allocated | |
874 | * | |
875 | * Returns: | |
876 | * 0 on success, errno otherwise. | |
877 | */ | |
878 | int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, | |
879 | struct amdgpu_vm *vm, | |
880 | uint64_t saddr, uint64_t size) | |
881 | { | |
882 | struct amdgpu_vm_pt_cursor cursor; | |
883 | struct amdgpu_bo *pt; | |
884 | bool ats = false; | |
885 | uint64_t eaddr; | |
886 | int r; | |
887 | ||
888 | /* validate the parameters */ | |
889 | if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK) | |
890 | return -EINVAL; | |
891 | ||
892 | eaddr = saddr + size - 1; | |
893 | ||
894 | if (vm->pte_support_ats) | |
895 | ats = saddr < AMDGPU_GMC_HOLE_START; | |
896 | ||
897 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
898 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
899 | ||
900 | if (eaddr >= adev->vm_manager.max_pfn) { | |
901 | dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n", | |
902 | eaddr, adev->vm_manager.max_pfn); | |
903 | return -EINVAL; | |
904 | } | |
905 | ||
906 | for_each_amdgpu_vm_pt_leaf(adev, vm, saddr, eaddr, cursor) { | |
907 | struct amdgpu_vm_pt *entry = cursor.entry; | |
908 | struct amdgpu_bo_param bp; | |
909 | ||
910 | if (cursor.level < AMDGPU_VM_PTB) { | |
911 | unsigned num_entries; | |
912 | ||
913 | num_entries = amdgpu_vm_num_entries(adev, cursor.level); | |
914 | entry->entries = kvmalloc_array(num_entries, | |
915 | sizeof(*entry->entries), | |
916 | GFP_KERNEL | | |
917 | __GFP_ZERO); | |
918 | if (!entry->entries) | |
919 | return -ENOMEM; | |
920 | } | |
921 | ||
922 | ||
923 | if (entry->base.bo) | |
924 | continue; | |
925 | ||
926 | amdgpu_vm_bo_param(adev, vm, cursor.level, &bp); | |
927 | ||
928 | r = amdgpu_bo_create(adev, &bp, &pt); | |
929 | if (r) | |
930 | return r; | |
931 | ||
932 | r = amdgpu_vm_clear_bo(adev, vm, pt, cursor.level, ats); | |
933 | if (r) | |
934 | goto error_free_pt; | |
935 | ||
936 | if (vm->use_cpu_for_update) { | |
937 | r = amdgpu_bo_kmap(pt, NULL); | |
938 | if (r) | |
939 | goto error_free_pt; | |
940 | } | |
941 | ||
942 | /* Keep a reference to the root directory to avoid | |
943 | * freeing them up in the wrong order. | |
944 | */ | |
945 | pt->parent = amdgpu_bo_ref(cursor.parent->base.bo); | |
946 | ||
947 | amdgpu_vm_bo_base_init(&entry->base, vm, pt); | |
948 | } | |
949 | ||
950 | return 0; | |
951 | ||
952 | error_free_pt: | |
953 | amdgpu_bo_unref(&pt->shadow); | |
954 | amdgpu_bo_unref(&pt); | |
955 | return r; | |
956 | } | |
957 | ||
958 | /** | |
959 | * amdgpu_vm_free_pts - free PD/PT levels | |
960 | * | |
961 | * @adev: amdgpu device structure | |
962 | * @vm: amdgpu vm structure | |
963 | * | |
964 | * Free the page directory or page table level and all sub levels. | |
965 | */ | |
966 | static void amdgpu_vm_free_pts(struct amdgpu_device *adev, | |
967 | struct amdgpu_vm *vm) | |
968 | { | |
969 | struct amdgpu_vm_pt_cursor cursor; | |
970 | struct amdgpu_vm_pt *entry; | |
971 | ||
972 | for_each_amdgpu_vm_pt_dfs_safe(adev, vm, cursor, entry) { | |
973 | ||
974 | if (entry->base.bo) { | |
975 | entry->base.bo->vm_bo = NULL; | |
976 | list_del(&entry->base.vm_status); | |
977 | amdgpu_bo_unref(&entry->base.bo->shadow); | |
978 | amdgpu_bo_unref(&entry->base.bo); | |
979 | } | |
980 | kvfree(entry->entries); | |
981 | } | |
982 | ||
983 | BUG_ON(vm->root.base.bo); | |
984 | } | |
985 | ||
986 | /** | |
987 | * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug | |
988 | * | |
989 | * @adev: amdgpu_device pointer | |
990 | */ | |
991 | void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev) | |
992 | { | |
993 | const struct amdgpu_ip_block *ip_block; | |
994 | bool has_compute_vm_bug; | |
995 | struct amdgpu_ring *ring; | |
996 | int i; | |
997 | ||
998 | has_compute_vm_bug = false; | |
999 | ||
1000 | ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); | |
1001 | if (ip_block) { | |
1002 | /* Compute has a VM bug for GFX version < 7. | |
1003 | Compute has a VM bug for GFX 8 MEC firmware version < 673.*/ | |
1004 | if (ip_block->version->major <= 7) | |
1005 | has_compute_vm_bug = true; | |
1006 | else if (ip_block->version->major == 8) | |
1007 | if (adev->gfx.mec_fw_version < 673) | |
1008 | has_compute_vm_bug = true; | |
1009 | } | |
1010 | ||
1011 | for (i = 0; i < adev->num_rings; i++) { | |
1012 | ring = adev->rings[i]; | |
1013 | if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) | |
1014 | /* only compute rings */ | |
1015 | ring->has_compute_vm_bug = has_compute_vm_bug; | |
1016 | else | |
1017 | ring->has_compute_vm_bug = false; | |
1018 | } | |
1019 | } | |
1020 | ||
1021 | /** | |
1022 | * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job. | |
1023 | * | |
1024 | * @ring: ring on which the job will be submitted | |
1025 | * @job: job to submit | |
1026 | * | |
1027 | * Returns: | |
1028 | * True if sync is needed. | |
1029 | */ | |
1030 | bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, | |
1031 | struct amdgpu_job *job) | |
1032 | { | |
1033 | struct amdgpu_device *adev = ring->adev; | |
1034 | unsigned vmhub = ring->funcs->vmhub; | |
1035 | struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
1036 | struct amdgpu_vmid *id; | |
1037 | bool gds_switch_needed; | |
1038 | bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug; | |
1039 | ||
1040 | if (job->vmid == 0) | |
1041 | return false; | |
1042 | id = &id_mgr->ids[job->vmid]; | |
1043 | gds_switch_needed = ring->funcs->emit_gds_switch && ( | |
1044 | id->gds_base != job->gds_base || | |
1045 | id->gds_size != job->gds_size || | |
1046 | id->gws_base != job->gws_base || | |
1047 | id->gws_size != job->gws_size || | |
1048 | id->oa_base != job->oa_base || | |
1049 | id->oa_size != job->oa_size); | |
1050 | ||
1051 | if (amdgpu_vmid_had_gpu_reset(adev, id)) | |
1052 | return true; | |
1053 | ||
1054 | return vm_flush_needed || gds_switch_needed; | |
1055 | } | |
1056 | ||
1057 | /** | |
1058 | * amdgpu_vm_flush - hardware flush the vm | |
1059 | * | |
1060 | * @ring: ring to use for flush | |
1061 | * @job: related job | |
1062 | * @need_pipe_sync: is pipe sync needed | |
1063 | * | |
1064 | * Emit a VM flush when it is necessary. | |
1065 | * | |
1066 | * Returns: | |
1067 | * 0 on success, errno otherwise. | |
1068 | */ | |
1069 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync) | |
1070 | { | |
1071 | struct amdgpu_device *adev = ring->adev; | |
1072 | unsigned vmhub = ring->funcs->vmhub; | |
1073 | struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
1074 | struct amdgpu_vmid *id = &id_mgr->ids[job->vmid]; | |
1075 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( | |
1076 | id->gds_base != job->gds_base || | |
1077 | id->gds_size != job->gds_size || | |
1078 | id->gws_base != job->gws_base || | |
1079 | id->gws_size != job->gws_size || | |
1080 | id->oa_base != job->oa_base || | |
1081 | id->oa_size != job->oa_size); | |
1082 | bool vm_flush_needed = job->vm_needs_flush; | |
1083 | bool pasid_mapping_needed = id->pasid != job->pasid || | |
1084 | !id->pasid_mapping || | |
1085 | !dma_fence_is_signaled(id->pasid_mapping); | |
1086 | struct dma_fence *fence = NULL; | |
1087 | unsigned patch_offset = 0; | |
1088 | int r; | |
1089 | ||
1090 | if (amdgpu_vmid_had_gpu_reset(adev, id)) { | |
1091 | gds_switch_needed = true; | |
1092 | vm_flush_needed = true; | |
1093 | pasid_mapping_needed = true; | |
1094 | } | |
1095 | ||
1096 | gds_switch_needed &= !!ring->funcs->emit_gds_switch; | |
1097 | vm_flush_needed &= !!ring->funcs->emit_vm_flush && | |
1098 | job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET; | |
1099 | pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping && | |
1100 | ring->funcs->emit_wreg; | |
1101 | ||
1102 | if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync) | |
1103 | return 0; | |
1104 | ||
1105 | if (ring->funcs->init_cond_exec) | |
1106 | patch_offset = amdgpu_ring_init_cond_exec(ring); | |
1107 | ||
1108 | if (need_pipe_sync) | |
1109 | amdgpu_ring_emit_pipeline_sync(ring); | |
1110 | ||
1111 | if (vm_flush_needed) { | |
1112 | trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr); | |
1113 | amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr); | |
1114 | } | |
1115 | ||
1116 | if (pasid_mapping_needed) | |
1117 | amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid); | |
1118 | ||
1119 | if (vm_flush_needed || pasid_mapping_needed) { | |
1120 | r = amdgpu_fence_emit(ring, &fence, 0); | |
1121 | if (r) | |
1122 | return r; | |
1123 | } | |
1124 | ||
1125 | if (vm_flush_needed) { | |
1126 | mutex_lock(&id_mgr->lock); | |
1127 | dma_fence_put(id->last_flush); | |
1128 | id->last_flush = dma_fence_get(fence); | |
1129 | id->current_gpu_reset_count = | |
1130 | atomic_read(&adev->gpu_reset_counter); | |
1131 | mutex_unlock(&id_mgr->lock); | |
1132 | } | |
1133 | ||
1134 | if (pasid_mapping_needed) { | |
1135 | id->pasid = job->pasid; | |
1136 | dma_fence_put(id->pasid_mapping); | |
1137 | id->pasid_mapping = dma_fence_get(fence); | |
1138 | } | |
1139 | dma_fence_put(fence); | |
1140 | ||
1141 | if (ring->funcs->emit_gds_switch && gds_switch_needed) { | |
1142 | id->gds_base = job->gds_base; | |
1143 | id->gds_size = job->gds_size; | |
1144 | id->gws_base = job->gws_base; | |
1145 | id->gws_size = job->gws_size; | |
1146 | id->oa_base = job->oa_base; | |
1147 | id->oa_size = job->oa_size; | |
1148 | amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base, | |
1149 | job->gds_size, job->gws_base, | |
1150 | job->gws_size, job->oa_base, | |
1151 | job->oa_size); | |
1152 | } | |
1153 | ||
1154 | if (ring->funcs->patch_cond_exec) | |
1155 | amdgpu_ring_patch_cond_exec(ring, patch_offset); | |
1156 | ||
1157 | /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */ | |
1158 | if (ring->funcs->emit_switch_buffer) { | |
1159 | amdgpu_ring_emit_switch_buffer(ring); | |
1160 | amdgpu_ring_emit_switch_buffer(ring); | |
1161 | } | |
1162 | return 0; | |
1163 | } | |
1164 | ||
1165 | /** | |
1166 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
1167 | * | |
1168 | * @vm: requested vm | |
1169 | * @bo: requested buffer object | |
1170 | * | |
1171 | * Find @bo inside the requested vm. | |
1172 | * Search inside the @bos vm list for the requested vm | |
1173 | * Returns the found bo_va or NULL if none is found | |
1174 | * | |
1175 | * Object has to be reserved! | |
1176 | * | |
1177 | * Returns: | |
1178 | * Found bo_va or NULL. | |
1179 | */ | |
1180 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
1181 | struct amdgpu_bo *bo) | |
1182 | { | |
1183 | struct amdgpu_vm_bo_base *base; | |
1184 | ||
1185 | for (base = bo->vm_bo; base; base = base->next) { | |
1186 | if (base->vm != vm) | |
1187 | continue; | |
1188 | ||
1189 | return container_of(base, struct amdgpu_bo_va, base); | |
1190 | } | |
1191 | return NULL; | |
1192 | } | |
1193 | ||
1194 | /** | |
1195 | * amdgpu_vm_do_set_ptes - helper to call the right asic function | |
1196 | * | |
1197 | * @params: see amdgpu_pte_update_params definition | |
1198 | * @bo: PD/PT to update | |
1199 | * @pe: addr of the page entry | |
1200 | * @addr: dst addr to write into pe | |
1201 | * @count: number of page entries to update | |
1202 | * @incr: increase next addr by incr bytes | |
1203 | * @flags: hw access flags | |
1204 | * | |
1205 | * Traces the parameters and calls the right asic functions | |
1206 | * to setup the page table using the DMA. | |
1207 | */ | |
1208 | static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params, | |
1209 | struct amdgpu_bo *bo, | |
1210 | uint64_t pe, uint64_t addr, | |
1211 | unsigned count, uint32_t incr, | |
1212 | uint64_t flags) | |
1213 | { | |
1214 | pe += amdgpu_bo_gpu_offset(bo); | |
1215 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); | |
1216 | ||
1217 | if (count < 3) { | |
1218 | amdgpu_vm_write_pte(params->adev, params->ib, pe, | |
1219 | addr | flags, count, incr); | |
1220 | ||
1221 | } else { | |
1222 | amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr, | |
1223 | count, incr, flags); | |
1224 | } | |
1225 | } | |
1226 | ||
1227 | /** | |
1228 | * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART | |
1229 | * | |
1230 | * @params: see amdgpu_pte_update_params definition | |
1231 | * @bo: PD/PT to update | |
1232 | * @pe: addr of the page entry | |
1233 | * @addr: dst addr to write into pe | |
1234 | * @count: number of page entries to update | |
1235 | * @incr: increase next addr by incr bytes | |
1236 | * @flags: hw access flags | |
1237 | * | |
1238 | * Traces the parameters and calls the DMA function to copy the PTEs. | |
1239 | */ | |
1240 | static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params, | |
1241 | struct amdgpu_bo *bo, | |
1242 | uint64_t pe, uint64_t addr, | |
1243 | unsigned count, uint32_t incr, | |
1244 | uint64_t flags) | |
1245 | { | |
1246 | uint64_t src = (params->src + (addr >> 12) * 8); | |
1247 | ||
1248 | pe += amdgpu_bo_gpu_offset(bo); | |
1249 | trace_amdgpu_vm_copy_ptes(pe, src, count); | |
1250 | ||
1251 | amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count); | |
1252 | } | |
1253 | ||
1254 | /** | |
1255 | * amdgpu_vm_map_gart - Resolve gart mapping of addr | |
1256 | * | |
1257 | * @pages_addr: optional DMA address to use for lookup | |
1258 | * @addr: the unmapped addr | |
1259 | * | |
1260 | * Look up the physical address of the page that the pte resolves | |
1261 | * to. | |
1262 | * | |
1263 | * Returns: | |
1264 | * The pointer for the page table entry. | |
1265 | */ | |
1266 | static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) | |
1267 | { | |
1268 | uint64_t result; | |
1269 | ||
1270 | /* page table offset */ | |
1271 | result = pages_addr[addr >> PAGE_SHIFT]; | |
1272 | ||
1273 | /* in case cpu page size != gpu page size*/ | |
1274 | result |= addr & (~PAGE_MASK); | |
1275 | ||
1276 | result &= 0xFFFFFFFFFFFFF000ULL; | |
1277 | ||
1278 | return result; | |
1279 | } | |
1280 | ||
1281 | /** | |
1282 | * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU | |
1283 | * | |
1284 | * @params: see amdgpu_pte_update_params definition | |
1285 | * @bo: PD/PT to update | |
1286 | * @pe: kmap addr of the page entry | |
1287 | * @addr: dst addr to write into pe | |
1288 | * @count: number of page entries to update | |
1289 | * @incr: increase next addr by incr bytes | |
1290 | * @flags: hw access flags | |
1291 | * | |
1292 | * Write count number of PT/PD entries directly. | |
1293 | */ | |
1294 | static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params, | |
1295 | struct amdgpu_bo *bo, | |
1296 | uint64_t pe, uint64_t addr, | |
1297 | unsigned count, uint32_t incr, | |
1298 | uint64_t flags) | |
1299 | { | |
1300 | unsigned int i; | |
1301 | uint64_t value; | |
1302 | ||
1303 | pe += (unsigned long)amdgpu_bo_kptr(bo); | |
1304 | ||
1305 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); | |
1306 | ||
1307 | for (i = 0; i < count; i++) { | |
1308 | value = params->pages_addr ? | |
1309 | amdgpu_vm_map_gart(params->pages_addr, addr) : | |
1310 | addr; | |
1311 | amdgpu_gmc_set_pte_pde(params->adev, (void *)(uintptr_t)pe, | |
1312 | i, value, flags); | |
1313 | addr += incr; | |
1314 | } | |
1315 | } | |
1316 | ||
1317 | ||
1318 | /** | |
1319 | * amdgpu_vm_wait_pd - Wait for PT BOs to be free. | |
1320 | * | |
1321 | * @adev: amdgpu_device pointer | |
1322 | * @vm: related vm | |
1323 | * @owner: fence owner | |
1324 | * | |
1325 | * Returns: | |
1326 | * 0 on success, errno otherwise. | |
1327 | */ | |
1328 | static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm, | |
1329 | void *owner) | |
1330 | { | |
1331 | struct amdgpu_sync sync; | |
1332 | int r; | |
1333 | ||
1334 | amdgpu_sync_create(&sync); | |
1335 | amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner, false); | |
1336 | r = amdgpu_sync_wait(&sync, true); | |
1337 | amdgpu_sync_free(&sync); | |
1338 | ||
1339 | return r; | |
1340 | } | |
1341 | ||
1342 | /** | |
1343 | * amdgpu_vm_update_func - helper to call update function | |
1344 | * | |
1345 | * Calls the update function for both the given BO as well as its shadow. | |
1346 | */ | |
1347 | static void amdgpu_vm_update_func(struct amdgpu_pte_update_params *params, | |
1348 | struct amdgpu_bo *bo, | |
1349 | uint64_t pe, uint64_t addr, | |
1350 | unsigned count, uint32_t incr, | |
1351 | uint64_t flags) | |
1352 | { | |
1353 | if (bo->shadow) | |
1354 | params->func(params, bo->shadow, pe, addr, count, incr, flags); | |
1355 | params->func(params, bo, pe, addr, count, incr, flags); | |
1356 | } | |
1357 | ||
1358 | /* | |
1359 | * amdgpu_vm_update_pde - update a single level in the hierarchy | |
1360 | * | |
1361 | * @param: parameters for the update | |
1362 | * @vm: requested vm | |
1363 | * @parent: parent directory | |
1364 | * @entry: entry to update | |
1365 | * | |
1366 | * Makes sure the requested entry in parent is up to date. | |
1367 | */ | |
1368 | static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params, | |
1369 | struct amdgpu_vm *vm, | |
1370 | struct amdgpu_vm_pt *parent, | |
1371 | struct amdgpu_vm_pt *entry) | |
1372 | { | |
1373 | struct amdgpu_bo *bo = parent->base.bo, *pbo; | |
1374 | uint64_t pde, pt, flags; | |
1375 | unsigned level; | |
1376 | ||
1377 | /* Don't update huge pages here */ | |
1378 | if (entry->huge) | |
1379 | return; | |
1380 | ||
1381 | for (level = 0, pbo = bo->parent; pbo; ++level) | |
1382 | pbo = pbo->parent; | |
1383 | ||
1384 | level += params->adev->vm_manager.root_level; | |
1385 | amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags); | |
1386 | pde = (entry - parent->entries) * 8; | |
1387 | amdgpu_vm_update_func(params, bo, pde, pt, 1, 0, flags); | |
1388 | } | |
1389 | ||
1390 | /* | |
1391 | * amdgpu_vm_invalidate_pds - mark all PDs as invalid | |
1392 | * | |
1393 | * @adev: amdgpu_device pointer | |
1394 | * @vm: related vm | |
1395 | * | |
1396 | * Mark all PD level as invalid after an error. | |
1397 | */ | |
1398 | static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev, | |
1399 | struct amdgpu_vm *vm) | |
1400 | { | |
1401 | struct amdgpu_vm_pt_cursor cursor; | |
1402 | struct amdgpu_vm_pt *entry; | |
1403 | ||
1404 | for_each_amdgpu_vm_pt_dfs_safe(adev, vm, cursor, entry) | |
1405 | if (entry->base.bo && !entry->base.moved) | |
1406 | amdgpu_vm_bo_relocated(&entry->base); | |
1407 | } | |
1408 | ||
1409 | /* | |
1410 | * amdgpu_vm_update_directories - make sure that all directories are valid | |
1411 | * | |
1412 | * @adev: amdgpu_device pointer | |
1413 | * @vm: requested vm | |
1414 | * | |
1415 | * Makes sure all directories are up to date. | |
1416 | * | |
1417 | * Returns: | |
1418 | * 0 for success, error for failure. | |
1419 | */ | |
1420 | int amdgpu_vm_update_directories(struct amdgpu_device *adev, | |
1421 | struct amdgpu_vm *vm) | |
1422 | { | |
1423 | struct amdgpu_pte_update_params params; | |
1424 | struct amdgpu_job *job; | |
1425 | unsigned ndw = 0; | |
1426 | int r = 0; | |
1427 | ||
1428 | if (list_empty(&vm->relocated)) | |
1429 | return 0; | |
1430 | ||
1431 | restart: | |
1432 | memset(¶ms, 0, sizeof(params)); | |
1433 | params.adev = adev; | |
1434 | ||
1435 | if (vm->use_cpu_for_update) { | |
1436 | r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM); | |
1437 | if (unlikely(r)) | |
1438 | return r; | |
1439 | ||
1440 | params.func = amdgpu_vm_cpu_set_ptes; | |
1441 | } else { | |
1442 | ndw = 512 * 8; | |
1443 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); | |
1444 | if (r) | |
1445 | return r; | |
1446 | ||
1447 | params.ib = &job->ibs[0]; | |
1448 | params.func = amdgpu_vm_do_set_ptes; | |
1449 | } | |
1450 | ||
1451 | while (!list_empty(&vm->relocated)) { | |
1452 | struct amdgpu_vm_pt *pt, *entry; | |
1453 | ||
1454 | entry = list_first_entry(&vm->relocated, struct amdgpu_vm_pt, | |
1455 | base.vm_status); | |
1456 | amdgpu_vm_bo_idle(&entry->base); | |
1457 | ||
1458 | pt = amdgpu_vm_pt_parent(entry); | |
1459 | if (!pt) | |
1460 | continue; | |
1461 | ||
1462 | amdgpu_vm_update_pde(¶ms, vm, pt, entry); | |
1463 | ||
1464 | if (!vm->use_cpu_for_update && | |
1465 | (ndw - params.ib->length_dw) < 32) | |
1466 | break; | |
1467 | } | |
1468 | ||
1469 | if (vm->use_cpu_for_update) { | |
1470 | /* Flush HDP */ | |
1471 | mb(); | |
1472 | amdgpu_asic_flush_hdp(adev, NULL); | |
1473 | } else if (params.ib->length_dw == 0) { | |
1474 | amdgpu_job_free(job); | |
1475 | } else { | |
1476 | struct amdgpu_bo *root = vm->root.base.bo; | |
1477 | struct amdgpu_ring *ring; | |
1478 | struct dma_fence *fence; | |
1479 | ||
1480 | ring = container_of(vm->entity.rq->sched, struct amdgpu_ring, | |
1481 | sched); | |
1482 | ||
1483 | amdgpu_ring_pad_ib(ring, params.ib); | |
1484 | amdgpu_sync_resv(adev, &job->sync, root->tbo.resv, | |
1485 | AMDGPU_FENCE_OWNER_VM, false); | |
1486 | WARN_ON(params.ib->length_dw > ndw); | |
1487 | r = amdgpu_job_submit(job, &vm->entity, AMDGPU_FENCE_OWNER_VM, | |
1488 | &fence); | |
1489 | if (r) | |
1490 | goto error; | |
1491 | ||
1492 | amdgpu_bo_fence(root, fence, true); | |
1493 | dma_fence_put(vm->last_update); | |
1494 | vm->last_update = fence; | |
1495 | } | |
1496 | ||
1497 | if (!list_empty(&vm->relocated)) | |
1498 | goto restart; | |
1499 | ||
1500 | return 0; | |
1501 | ||
1502 | error: | |
1503 | amdgpu_vm_invalidate_pds(adev, vm); | |
1504 | amdgpu_job_free(job); | |
1505 | return r; | |
1506 | } | |
1507 | ||
1508 | /** | |
1509 | * amdgpu_vm_update_huge - figure out parameters for PTE updates | |
1510 | * | |
1511 | * Make sure to set the right flags for the PTEs at the desired level. | |
1512 | */ | |
1513 | static void amdgpu_vm_update_huge(struct amdgpu_pte_update_params *params, | |
1514 | struct amdgpu_bo *bo, unsigned level, | |
1515 | uint64_t pe, uint64_t addr, | |
1516 | unsigned count, uint32_t incr, | |
1517 | uint64_t flags) | |
1518 | ||
1519 | { | |
1520 | if (level != AMDGPU_VM_PTB) { | |
1521 | flags |= AMDGPU_PDE_PTE; | |
1522 | amdgpu_gmc_get_vm_pde(params->adev, level, &addr, &flags); | |
1523 | } | |
1524 | ||
1525 | amdgpu_vm_update_func(params, bo, pe, addr, count, incr, flags); | |
1526 | } | |
1527 | ||
1528 | /** | |
1529 | * amdgpu_vm_fragment - get fragment for PTEs | |
1530 | * | |
1531 | * @params: see amdgpu_pte_update_params definition | |
1532 | * @start: first PTE to handle | |
1533 | * @end: last PTE to handle | |
1534 | * @flags: hw mapping flags | |
1535 | * @frag: resulting fragment size | |
1536 | * @frag_end: end of this fragment | |
1537 | * | |
1538 | * Returns the first possible fragment for the start and end address. | |
1539 | */ | |
1540 | static void amdgpu_vm_fragment(struct amdgpu_pte_update_params *params, | |
1541 | uint64_t start, uint64_t end, uint64_t flags, | |
1542 | unsigned int *frag, uint64_t *frag_end) | |
1543 | { | |
1544 | /** | |
1545 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
1546 | * field in the PTE. When this field is set to a non-zero value, page | |
1547 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
1548 | * flags are considered valid for all PTEs within the fragment range | |
1549 | * and corresponding mappings are assumed to be physically contiguous. | |
1550 | * | |
1551 | * The L1 TLB can store a single PTE for the whole fragment, | |
1552 | * significantly increasing the space available for translation | |
1553 | * caching. This leads to large improvements in throughput when the | |
1554 | * TLB is under pressure. | |
1555 | * | |
1556 | * The L2 TLB distributes small and large fragments into two | |
1557 | * asymmetric partitions. The large fragment cache is significantly | |
1558 | * larger. Thus, we try to use large fragments wherever possible. | |
1559 | * Userspace can support this by aligning virtual base address and | |
1560 | * allocation size to the fragment size. | |
1561 | * | |
1562 | * Starting with Vega10 the fragment size only controls the L1. The L2 | |
1563 | * is now directly feed with small/huge/giant pages from the walker. | |
1564 | */ | |
1565 | unsigned max_frag; | |
1566 | ||
1567 | if (params->adev->asic_type < CHIP_VEGA10) | |
1568 | max_frag = params->adev->vm_manager.fragment_size; | |
1569 | else | |
1570 | max_frag = 31; | |
1571 | ||
1572 | /* system pages are non continuously */ | |
1573 | if (params->src) { | |
1574 | *frag = 0; | |
1575 | *frag_end = end; | |
1576 | return; | |
1577 | } | |
1578 | ||
1579 | /* This intentionally wraps around if no bit is set */ | |
1580 | *frag = min((unsigned)ffs(start) - 1, (unsigned)fls64(end - start) - 1); | |
1581 | if (*frag >= max_frag) { | |
1582 | *frag = max_frag; | |
1583 | *frag_end = end & ~((1ULL << max_frag) - 1); | |
1584 | } else { | |
1585 | *frag_end = start + (1 << *frag); | |
1586 | } | |
1587 | } | |
1588 | ||
1589 | /** | |
1590 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
1591 | * | |
1592 | * @params: see amdgpu_pte_update_params definition | |
1593 | * @start: start of GPU address range | |
1594 | * @end: end of GPU address range | |
1595 | * @dst: destination address to map to, the next dst inside the function | |
1596 | * @flags: mapping flags | |
1597 | * | |
1598 | * Update the page tables in the range @start - @end. | |
1599 | * | |
1600 | * Returns: | |
1601 | * 0 for success, -EINVAL for failure. | |
1602 | */ | |
1603 | static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, | |
1604 | uint64_t start, uint64_t end, | |
1605 | uint64_t dst, uint64_t flags) | |
1606 | { | |
1607 | struct amdgpu_device *adev = params->adev; | |
1608 | struct amdgpu_vm_pt_cursor cursor; | |
1609 | uint64_t frag_start = start, frag_end; | |
1610 | unsigned int frag; | |
1611 | ||
1612 | /* figure out the initial fragment */ | |
1613 | amdgpu_vm_fragment(params, frag_start, end, flags, &frag, &frag_end); | |
1614 | ||
1615 | /* walk over the address space and update the PTs */ | |
1616 | amdgpu_vm_pt_start(adev, params->vm, start, &cursor); | |
1617 | while (cursor.pfn < end) { | |
1618 | struct amdgpu_bo *pt = cursor.entry->base.bo; | |
1619 | unsigned shift, parent_shift, mask; | |
1620 | uint64_t incr, entry_end, pe_start; | |
1621 | ||
1622 | if (!pt) | |
1623 | return -ENOENT; | |
1624 | ||
1625 | /* The root level can't be a huge page */ | |
1626 | if (cursor.level == adev->vm_manager.root_level) { | |
1627 | if (!amdgpu_vm_pt_descendant(adev, &cursor)) | |
1628 | return -ENOENT; | |
1629 | continue; | |
1630 | } | |
1631 | ||
1632 | /* If it isn't already handled it can't be a huge page */ | |
1633 | if (cursor.entry->huge) { | |
1634 | /* Add the entry to the relocated list to update it. */ | |
1635 | cursor.entry->huge = false; | |
1636 | amdgpu_vm_bo_relocated(&cursor.entry->base); | |
1637 | } | |
1638 | ||
1639 | shift = amdgpu_vm_level_shift(adev, cursor.level); | |
1640 | parent_shift = amdgpu_vm_level_shift(adev, cursor.level - 1); | |
1641 | if (adev->asic_type < CHIP_VEGA10) { | |
1642 | /* No huge page support before GMC v9 */ | |
1643 | if (cursor.level != AMDGPU_VM_PTB) { | |
1644 | if (!amdgpu_vm_pt_descendant(adev, &cursor)) | |
1645 | return -ENOENT; | |
1646 | continue; | |
1647 | } | |
1648 | } else if (frag < shift) { | |
1649 | /* We can't use this level when the fragment size is | |
1650 | * smaller than the address shift. Go to the next | |
1651 | * child entry and try again. | |
1652 | */ | |
1653 | if (!amdgpu_vm_pt_descendant(adev, &cursor)) | |
1654 | return -ENOENT; | |
1655 | continue; | |
1656 | } else if (frag >= parent_shift) { | |
1657 | /* If the fragment size is even larger than the parent | |
1658 | * shift we should go up one level and check it again. | |
1659 | */ | |
1660 | if (!amdgpu_vm_pt_ancestor(&cursor)) | |
1661 | return -ENOENT; | |
1662 | continue; | |
1663 | } | |
1664 | ||
1665 | /* Looks good so far, calculate parameters for the update */ | |
1666 | incr = AMDGPU_GPU_PAGE_SIZE << shift; | |
1667 | mask = amdgpu_vm_entries_mask(adev, cursor.level); | |
1668 | pe_start = ((cursor.pfn >> shift) & mask) * 8; | |
1669 | entry_end = (mask + 1) << shift; | |
1670 | entry_end += cursor.pfn & ~(entry_end - 1); | |
1671 | entry_end = min(entry_end, end); | |
1672 | ||
1673 | do { | |
1674 | uint64_t upd_end = min(entry_end, frag_end); | |
1675 | unsigned nptes = (upd_end - frag_start) >> shift; | |
1676 | ||
1677 | amdgpu_vm_update_huge(params, pt, cursor.level, | |
1678 | pe_start, dst, nptes, incr, | |
1679 | flags | AMDGPU_PTE_FRAG(frag)); | |
1680 | ||
1681 | pe_start += nptes * 8; | |
1682 | dst += nptes * AMDGPU_GPU_PAGE_SIZE << shift; | |
1683 | ||
1684 | frag_start = upd_end; | |
1685 | if (frag_start >= frag_end) { | |
1686 | /* figure out the next fragment */ | |
1687 | amdgpu_vm_fragment(params, frag_start, end, | |
1688 | flags, &frag, &frag_end); | |
1689 | if (frag < shift) | |
1690 | break; | |
1691 | } | |
1692 | } while (frag_start < entry_end); | |
1693 | ||
1694 | if (amdgpu_vm_pt_descendant(adev, &cursor)) { | |
1695 | /* Mark all child entries as huge */ | |
1696 | while (cursor.pfn < frag_start) { | |
1697 | cursor.entry->huge = true; | |
1698 | amdgpu_vm_pt_next(adev, &cursor); | |
1699 | } | |
1700 | ||
1701 | } else if (frag >= shift) { | |
1702 | /* or just move on to the next on the same level. */ | |
1703 | amdgpu_vm_pt_next(adev, &cursor); | |
1704 | } | |
1705 | } | |
1706 | ||
1707 | return 0; | |
1708 | } | |
1709 | ||
1710 | /** | |
1711 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
1712 | * | |
1713 | * @adev: amdgpu_device pointer | |
1714 | * @exclusive: fence we need to sync to | |
1715 | * @pages_addr: DMA addresses to use for mapping | |
1716 | * @vm: requested vm | |
1717 | * @start: start of mapped range | |
1718 | * @last: last mapped entry | |
1719 | * @flags: flags for the entries | |
1720 | * @addr: addr to set the area to | |
1721 | * @fence: optional resulting fence | |
1722 | * | |
1723 | * Fill in the page table entries between @start and @last. | |
1724 | * | |
1725 | * Returns: | |
1726 | * 0 for success, -EINVAL for failure. | |
1727 | */ | |
1728 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
1729 | struct dma_fence *exclusive, | |
1730 | dma_addr_t *pages_addr, | |
1731 | struct amdgpu_vm *vm, | |
1732 | uint64_t start, uint64_t last, | |
1733 | uint64_t flags, uint64_t addr, | |
1734 | struct dma_fence **fence) | |
1735 | { | |
1736 | struct amdgpu_ring *ring; | |
1737 | void *owner = AMDGPU_FENCE_OWNER_VM; | |
1738 | unsigned nptes, ncmds, ndw; | |
1739 | struct amdgpu_job *job; | |
1740 | struct amdgpu_pte_update_params params; | |
1741 | struct dma_fence *f = NULL; | |
1742 | int r; | |
1743 | ||
1744 | memset(¶ms, 0, sizeof(params)); | |
1745 | params.adev = adev; | |
1746 | params.vm = vm; | |
1747 | ||
1748 | /* sync to everything on unmapping */ | |
1749 | if (!(flags & AMDGPU_PTE_VALID)) | |
1750 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
1751 | ||
1752 | if (vm->use_cpu_for_update) { | |
1753 | /* params.src is used as flag to indicate system Memory */ | |
1754 | if (pages_addr) | |
1755 | params.src = ~0; | |
1756 | ||
1757 | /* Wait for PT BOs to be free. PTs share the same resv. object | |
1758 | * as the root PD BO | |
1759 | */ | |
1760 | r = amdgpu_vm_wait_pd(adev, vm, owner); | |
1761 | if (unlikely(r)) | |
1762 | return r; | |
1763 | ||
1764 | params.func = amdgpu_vm_cpu_set_ptes; | |
1765 | params.pages_addr = pages_addr; | |
1766 | return amdgpu_vm_update_ptes(¶ms, start, last + 1, | |
1767 | addr, flags); | |
1768 | } | |
1769 | ||
1770 | ring = container_of(vm->entity.rq->sched, struct amdgpu_ring, sched); | |
1771 | ||
1772 | nptes = last - start + 1; | |
1773 | ||
1774 | /* | |
1775 | * reserve space for two commands every (1 << BLOCK_SIZE) | |
1776 | * entries or 2k dwords (whatever is smaller) | |
1777 | * | |
1778 | * The second command is for the shadow pagetables. | |
1779 | */ | |
1780 | if (vm->root.base.bo->shadow) | |
1781 | ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1) * 2; | |
1782 | else | |
1783 | ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1); | |
1784 | ||
1785 | /* padding, etc. */ | |
1786 | ndw = 64; | |
1787 | ||
1788 | if (pages_addr) { | |
1789 | /* copy commands needed */ | |
1790 | ndw += ncmds * adev->vm_manager.vm_pte_funcs->copy_pte_num_dw; | |
1791 | ||
1792 | /* and also PTEs */ | |
1793 | ndw += nptes * 2; | |
1794 | ||
1795 | params.func = amdgpu_vm_do_copy_ptes; | |
1796 | ||
1797 | } else { | |
1798 | /* set page commands needed */ | |
1799 | ndw += ncmds * 10; | |
1800 | ||
1801 | /* extra commands for begin/end fragments */ | |
1802 | if (vm->root.base.bo->shadow) | |
1803 | ndw += 2 * 10 * adev->vm_manager.fragment_size * 2; | |
1804 | else | |
1805 | ndw += 2 * 10 * adev->vm_manager.fragment_size; | |
1806 | ||
1807 | params.func = amdgpu_vm_do_set_ptes; | |
1808 | } | |
1809 | ||
1810 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); | |
1811 | if (r) | |
1812 | return r; | |
1813 | ||
1814 | params.ib = &job->ibs[0]; | |
1815 | ||
1816 | if (pages_addr) { | |
1817 | uint64_t *pte; | |
1818 | unsigned i; | |
1819 | ||
1820 | /* Put the PTEs at the end of the IB. */ | |
1821 | i = ndw - nptes * 2; | |
1822 | pte= (uint64_t *)&(job->ibs->ptr[i]); | |
1823 | params.src = job->ibs->gpu_addr + i * 4; | |
1824 | ||
1825 | for (i = 0; i < nptes; ++i) { | |
1826 | pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i * | |
1827 | AMDGPU_GPU_PAGE_SIZE); | |
1828 | pte[i] |= flags; | |
1829 | } | |
1830 | addr = 0; | |
1831 | } | |
1832 | ||
1833 | r = amdgpu_sync_fence(adev, &job->sync, exclusive, false); | |
1834 | if (r) | |
1835 | goto error_free; | |
1836 | ||
1837 | r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv, | |
1838 | owner, false); | |
1839 | if (r) | |
1840 | goto error_free; | |
1841 | ||
1842 | r = amdgpu_vm_update_ptes(¶ms, start, last + 1, addr, flags); | |
1843 | if (r) | |
1844 | goto error_free; | |
1845 | ||
1846 | amdgpu_ring_pad_ib(ring, params.ib); | |
1847 | WARN_ON(params.ib->length_dw > ndw); | |
1848 | r = amdgpu_job_submit(job, &vm->entity, AMDGPU_FENCE_OWNER_VM, &f); | |
1849 | if (r) | |
1850 | goto error_free; | |
1851 | ||
1852 | amdgpu_bo_fence(vm->root.base.bo, f, true); | |
1853 | dma_fence_put(*fence); | |
1854 | *fence = f; | |
1855 | return 0; | |
1856 | ||
1857 | error_free: | |
1858 | amdgpu_job_free(job); | |
1859 | return r; | |
1860 | } | |
1861 | ||
1862 | /** | |
1863 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
1864 | * | |
1865 | * @adev: amdgpu_device pointer | |
1866 | * @exclusive: fence we need to sync to | |
1867 | * @pages_addr: DMA addresses to use for mapping | |
1868 | * @vm: requested vm | |
1869 | * @mapping: mapped range and flags to use for the update | |
1870 | * @flags: HW flags for the mapping | |
1871 | * @nodes: array of drm_mm_nodes with the MC addresses | |
1872 | * @fence: optional resulting fence | |
1873 | * | |
1874 | * Split the mapping into smaller chunks so that each update fits | |
1875 | * into a SDMA IB. | |
1876 | * | |
1877 | * Returns: | |
1878 | * 0 for success, -EINVAL for failure. | |
1879 | */ | |
1880 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
1881 | struct dma_fence *exclusive, | |
1882 | dma_addr_t *pages_addr, | |
1883 | struct amdgpu_vm *vm, | |
1884 | struct amdgpu_bo_va_mapping *mapping, | |
1885 | uint64_t flags, | |
1886 | struct drm_mm_node *nodes, | |
1887 | struct dma_fence **fence) | |
1888 | { | |
1889 | unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size; | |
1890 | uint64_t pfn, start = mapping->start; | |
1891 | int r; | |
1892 | ||
1893 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
1894 | * but in case of something, we filter the flags in first place | |
1895 | */ | |
1896 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
1897 | flags &= ~AMDGPU_PTE_READABLE; | |
1898 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
1899 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
1900 | ||
1901 | flags &= ~AMDGPU_PTE_EXECUTABLE; | |
1902 | flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; | |
1903 | ||
1904 | flags &= ~AMDGPU_PTE_MTYPE_MASK; | |
1905 | flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK); | |
1906 | ||
1907 | if ((mapping->flags & AMDGPU_PTE_PRT) && | |
1908 | (adev->asic_type >= CHIP_VEGA10)) { | |
1909 | flags |= AMDGPU_PTE_PRT; | |
1910 | flags &= ~AMDGPU_PTE_VALID; | |
1911 | } | |
1912 | ||
1913 | trace_amdgpu_vm_bo_update(mapping); | |
1914 | ||
1915 | pfn = mapping->offset >> PAGE_SHIFT; | |
1916 | if (nodes) { | |
1917 | while (pfn >= nodes->size) { | |
1918 | pfn -= nodes->size; | |
1919 | ++nodes; | |
1920 | } | |
1921 | } | |
1922 | ||
1923 | do { | |
1924 | dma_addr_t *dma_addr = NULL; | |
1925 | uint64_t max_entries; | |
1926 | uint64_t addr, last; | |
1927 | ||
1928 | if (nodes) { | |
1929 | addr = nodes->start << PAGE_SHIFT; | |
1930 | max_entries = (nodes->size - pfn) * | |
1931 | AMDGPU_GPU_PAGES_IN_CPU_PAGE; | |
1932 | } else { | |
1933 | addr = 0; | |
1934 | max_entries = S64_MAX; | |
1935 | } | |
1936 | ||
1937 | if (pages_addr) { | |
1938 | uint64_t count; | |
1939 | ||
1940 | max_entries = min(max_entries, 16ull * 1024ull); | |
1941 | for (count = 1; | |
1942 | count < max_entries / AMDGPU_GPU_PAGES_IN_CPU_PAGE; | |
1943 | ++count) { | |
1944 | uint64_t idx = pfn + count; | |
1945 | ||
1946 | if (pages_addr[idx] != | |
1947 | (pages_addr[idx - 1] + PAGE_SIZE)) | |
1948 | break; | |
1949 | } | |
1950 | ||
1951 | if (count < min_linear_pages) { | |
1952 | addr = pfn << PAGE_SHIFT; | |
1953 | dma_addr = pages_addr; | |
1954 | } else { | |
1955 | addr = pages_addr[pfn]; | |
1956 | max_entries = count * AMDGPU_GPU_PAGES_IN_CPU_PAGE; | |
1957 | } | |
1958 | ||
1959 | } else if (flags & AMDGPU_PTE_VALID) { | |
1960 | addr += adev->vm_manager.vram_base_offset; | |
1961 | addr += pfn << PAGE_SHIFT; | |
1962 | } | |
1963 | ||
1964 | last = min((uint64_t)mapping->last, start + max_entries - 1); | |
1965 | r = amdgpu_vm_bo_update_mapping(adev, exclusive, dma_addr, vm, | |
1966 | start, last, flags, addr, | |
1967 | fence); | |
1968 | if (r) | |
1969 | return r; | |
1970 | ||
1971 | pfn += (last - start + 1) / AMDGPU_GPU_PAGES_IN_CPU_PAGE; | |
1972 | if (nodes && nodes->size == pfn) { | |
1973 | pfn = 0; | |
1974 | ++nodes; | |
1975 | } | |
1976 | start = last + 1; | |
1977 | ||
1978 | } while (unlikely(start != mapping->last + 1)); | |
1979 | ||
1980 | return 0; | |
1981 | } | |
1982 | ||
1983 | /** | |
1984 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
1985 | * | |
1986 | * @adev: amdgpu_device pointer | |
1987 | * @bo_va: requested BO and VM object | |
1988 | * @clear: if true clear the entries | |
1989 | * | |
1990 | * Fill in the page table entries for @bo_va. | |
1991 | * | |
1992 | * Returns: | |
1993 | * 0 for success, -EINVAL for failure. | |
1994 | */ | |
1995 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
1996 | struct amdgpu_bo_va *bo_va, | |
1997 | bool clear) | |
1998 | { | |
1999 | struct amdgpu_bo *bo = bo_va->base.bo; | |
2000 | struct amdgpu_vm *vm = bo_va->base.vm; | |
2001 | struct amdgpu_bo_va_mapping *mapping; | |
2002 | dma_addr_t *pages_addr = NULL; | |
2003 | struct ttm_mem_reg *mem; | |
2004 | struct drm_mm_node *nodes; | |
2005 | struct dma_fence *exclusive, **last_update; | |
2006 | uint64_t flags; | |
2007 | int r; | |
2008 | ||
2009 | if (clear || !bo) { | |
2010 | mem = NULL; | |
2011 | nodes = NULL; | |
2012 | exclusive = NULL; | |
2013 | } else { | |
2014 | struct ttm_dma_tt *ttm; | |
2015 | ||
2016 | mem = &bo->tbo.mem; | |
2017 | nodes = mem->mm_node; | |
2018 | if (mem->mem_type == TTM_PL_TT) { | |
2019 | ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm); | |
2020 | pages_addr = ttm->dma_address; | |
2021 | } | |
2022 | exclusive = reservation_object_get_excl(bo->tbo.resv); | |
2023 | } | |
2024 | ||
2025 | if (bo) | |
2026 | flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem); | |
2027 | else | |
2028 | flags = 0x0; | |
2029 | ||
2030 | if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv)) | |
2031 | last_update = &vm->last_update; | |
2032 | else | |
2033 | last_update = &bo_va->last_pt_update; | |
2034 | ||
2035 | if (!clear && bo_va->base.moved) { | |
2036 | bo_va->base.moved = false; | |
2037 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
2038 | ||
2039 | } else if (bo_va->cleared != clear) { | |
2040 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
2041 | } | |
2042 | ||
2043 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
2044 | r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm, | |
2045 | mapping, flags, nodes, | |
2046 | last_update); | |
2047 | if (r) | |
2048 | return r; | |
2049 | } | |
2050 | ||
2051 | if (vm->use_cpu_for_update) { | |
2052 | /* Flush HDP */ | |
2053 | mb(); | |
2054 | amdgpu_asic_flush_hdp(adev, NULL); | |
2055 | } | |
2056 | ||
2057 | /* If the BO is not in its preferred location add it back to | |
2058 | * the evicted list so that it gets validated again on the | |
2059 | * next command submission. | |
2060 | */ | |
2061 | if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) { | |
2062 | uint32_t mem_type = bo->tbo.mem.mem_type; | |
2063 | ||
2064 | if (!(bo->preferred_domains & amdgpu_mem_type_to_domain(mem_type))) | |
2065 | amdgpu_vm_bo_evicted(&bo_va->base); | |
2066 | else | |
2067 | amdgpu_vm_bo_idle(&bo_va->base); | |
2068 | } else { | |
2069 | amdgpu_vm_bo_done(&bo_va->base); | |
2070 | } | |
2071 | ||
2072 | list_splice_init(&bo_va->invalids, &bo_va->valids); | |
2073 | bo_va->cleared = clear; | |
2074 | ||
2075 | if (trace_amdgpu_vm_bo_mapping_enabled()) { | |
2076 | list_for_each_entry(mapping, &bo_va->valids, list) | |
2077 | trace_amdgpu_vm_bo_mapping(mapping); | |
2078 | } | |
2079 | ||
2080 | return 0; | |
2081 | } | |
2082 | ||
2083 | /** | |
2084 | * amdgpu_vm_update_prt_state - update the global PRT state | |
2085 | * | |
2086 | * @adev: amdgpu_device pointer | |
2087 | */ | |
2088 | static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev) | |
2089 | { | |
2090 | unsigned long flags; | |
2091 | bool enable; | |
2092 | ||
2093 | spin_lock_irqsave(&adev->vm_manager.prt_lock, flags); | |
2094 | enable = !!atomic_read(&adev->vm_manager.num_prt_users); | |
2095 | adev->gmc.gmc_funcs->set_prt(adev, enable); | |
2096 | spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags); | |
2097 | } | |
2098 | ||
2099 | /** | |
2100 | * amdgpu_vm_prt_get - add a PRT user | |
2101 | * | |
2102 | * @adev: amdgpu_device pointer | |
2103 | */ | |
2104 | static void amdgpu_vm_prt_get(struct amdgpu_device *adev) | |
2105 | { | |
2106 | if (!adev->gmc.gmc_funcs->set_prt) | |
2107 | return; | |
2108 | ||
2109 | if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1) | |
2110 | amdgpu_vm_update_prt_state(adev); | |
2111 | } | |
2112 | ||
2113 | /** | |
2114 | * amdgpu_vm_prt_put - drop a PRT user | |
2115 | * | |
2116 | * @adev: amdgpu_device pointer | |
2117 | */ | |
2118 | static void amdgpu_vm_prt_put(struct amdgpu_device *adev) | |
2119 | { | |
2120 | if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0) | |
2121 | amdgpu_vm_update_prt_state(adev); | |
2122 | } | |
2123 | ||
2124 | /** | |
2125 | * amdgpu_vm_prt_cb - callback for updating the PRT status | |
2126 | * | |
2127 | * @fence: fence for the callback | |
2128 | * @_cb: the callback function | |
2129 | */ | |
2130 | static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb) | |
2131 | { | |
2132 | struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb); | |
2133 | ||
2134 | amdgpu_vm_prt_put(cb->adev); | |
2135 | kfree(cb); | |
2136 | } | |
2137 | ||
2138 | /** | |
2139 | * amdgpu_vm_add_prt_cb - add callback for updating the PRT status | |
2140 | * | |
2141 | * @adev: amdgpu_device pointer | |
2142 | * @fence: fence for the callback | |
2143 | */ | |
2144 | static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev, | |
2145 | struct dma_fence *fence) | |
2146 | { | |
2147 | struct amdgpu_prt_cb *cb; | |
2148 | ||
2149 | if (!adev->gmc.gmc_funcs->set_prt) | |
2150 | return; | |
2151 | ||
2152 | cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL); | |
2153 | if (!cb) { | |
2154 | /* Last resort when we are OOM */ | |
2155 | if (fence) | |
2156 | dma_fence_wait(fence, false); | |
2157 | ||
2158 | amdgpu_vm_prt_put(adev); | |
2159 | } else { | |
2160 | cb->adev = adev; | |
2161 | if (!fence || dma_fence_add_callback(fence, &cb->cb, | |
2162 | amdgpu_vm_prt_cb)) | |
2163 | amdgpu_vm_prt_cb(fence, &cb->cb); | |
2164 | } | |
2165 | } | |
2166 | ||
2167 | /** | |
2168 | * amdgpu_vm_free_mapping - free a mapping | |
2169 | * | |
2170 | * @adev: amdgpu_device pointer | |
2171 | * @vm: requested vm | |
2172 | * @mapping: mapping to be freed | |
2173 | * @fence: fence of the unmap operation | |
2174 | * | |
2175 | * Free a mapping and make sure we decrease the PRT usage count if applicable. | |
2176 | */ | |
2177 | static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, | |
2178 | struct amdgpu_vm *vm, | |
2179 | struct amdgpu_bo_va_mapping *mapping, | |
2180 | struct dma_fence *fence) | |
2181 | { | |
2182 | if (mapping->flags & AMDGPU_PTE_PRT) | |
2183 | amdgpu_vm_add_prt_cb(adev, fence); | |
2184 | kfree(mapping); | |
2185 | } | |
2186 | ||
2187 | /** | |
2188 | * amdgpu_vm_prt_fini - finish all prt mappings | |
2189 | * | |
2190 | * @adev: amdgpu_device pointer | |
2191 | * @vm: requested vm | |
2192 | * | |
2193 | * Register a cleanup callback to disable PRT support after VM dies. | |
2194 | */ | |
2195 | static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
2196 | { | |
2197 | struct reservation_object *resv = vm->root.base.bo->tbo.resv; | |
2198 | struct dma_fence *excl, **shared; | |
2199 | unsigned i, shared_count; | |
2200 | int r; | |
2201 | ||
2202 | r = reservation_object_get_fences_rcu(resv, &excl, | |
2203 | &shared_count, &shared); | |
2204 | if (r) { | |
2205 | /* Not enough memory to grab the fence list, as last resort | |
2206 | * block for all the fences to complete. | |
2207 | */ | |
2208 | reservation_object_wait_timeout_rcu(resv, true, false, | |
2209 | MAX_SCHEDULE_TIMEOUT); | |
2210 | return; | |
2211 | } | |
2212 | ||
2213 | /* Add a callback for each fence in the reservation object */ | |
2214 | amdgpu_vm_prt_get(adev); | |
2215 | amdgpu_vm_add_prt_cb(adev, excl); | |
2216 | ||
2217 | for (i = 0; i < shared_count; ++i) { | |
2218 | amdgpu_vm_prt_get(adev); | |
2219 | amdgpu_vm_add_prt_cb(adev, shared[i]); | |
2220 | } | |
2221 | ||
2222 | kfree(shared); | |
2223 | } | |
2224 | ||
2225 | /** | |
2226 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
2227 | * | |
2228 | * @adev: amdgpu_device pointer | |
2229 | * @vm: requested vm | |
2230 | * @fence: optional resulting fence (unchanged if no work needed to be done | |
2231 | * or if an error occurred) | |
2232 | * | |
2233 | * Make sure all freed BOs are cleared in the PT. | |
2234 | * PTs have to be reserved and mutex must be locked! | |
2235 | * | |
2236 | * Returns: | |
2237 | * 0 for success. | |
2238 | * | |
2239 | */ | |
2240 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
2241 | struct amdgpu_vm *vm, | |
2242 | struct dma_fence **fence) | |
2243 | { | |
2244 | struct amdgpu_bo_va_mapping *mapping; | |
2245 | uint64_t init_pte_value = 0; | |
2246 | struct dma_fence *f = NULL; | |
2247 | int r; | |
2248 | ||
2249 | while (!list_empty(&vm->freed)) { | |
2250 | mapping = list_first_entry(&vm->freed, | |
2251 | struct amdgpu_bo_va_mapping, list); | |
2252 | list_del(&mapping->list); | |
2253 | ||
2254 | if (vm->pte_support_ats && | |
2255 | mapping->start < AMDGPU_GMC_HOLE_START) | |
2256 | init_pte_value = AMDGPU_PTE_DEFAULT_ATC; | |
2257 | ||
2258 | r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm, | |
2259 | mapping->start, mapping->last, | |
2260 | init_pte_value, 0, &f); | |
2261 | amdgpu_vm_free_mapping(adev, vm, mapping, f); | |
2262 | if (r) { | |
2263 | dma_fence_put(f); | |
2264 | return r; | |
2265 | } | |
2266 | } | |
2267 | ||
2268 | if (fence && f) { | |
2269 | dma_fence_put(*fence); | |
2270 | *fence = f; | |
2271 | } else { | |
2272 | dma_fence_put(f); | |
2273 | } | |
2274 | ||
2275 | return 0; | |
2276 | ||
2277 | } | |
2278 | ||
2279 | /** | |
2280 | * amdgpu_vm_handle_moved - handle moved BOs in the PT | |
2281 | * | |
2282 | * @adev: amdgpu_device pointer | |
2283 | * @vm: requested vm | |
2284 | * | |
2285 | * Make sure all BOs which are moved are updated in the PTs. | |
2286 | * | |
2287 | * Returns: | |
2288 | * 0 for success. | |
2289 | * | |
2290 | * PTs have to be reserved! | |
2291 | */ | |
2292 | int amdgpu_vm_handle_moved(struct amdgpu_device *adev, | |
2293 | struct amdgpu_vm *vm) | |
2294 | { | |
2295 | struct amdgpu_bo_va *bo_va, *tmp; | |
2296 | struct reservation_object *resv; | |
2297 | bool clear; | |
2298 | int r; | |
2299 | ||
2300 | list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) { | |
2301 | /* Per VM BOs never need to bo cleared in the page tables */ | |
2302 | r = amdgpu_vm_bo_update(adev, bo_va, false); | |
2303 | if (r) | |
2304 | return r; | |
2305 | } | |
2306 | ||
2307 | spin_lock(&vm->invalidated_lock); | |
2308 | while (!list_empty(&vm->invalidated)) { | |
2309 | bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va, | |
2310 | base.vm_status); | |
2311 | resv = bo_va->base.bo->tbo.resv; | |
2312 | spin_unlock(&vm->invalidated_lock); | |
2313 | ||
2314 | /* Try to reserve the BO to avoid clearing its ptes */ | |
2315 | if (!amdgpu_vm_debug && reservation_object_trylock(resv)) | |
2316 | clear = false; | |
2317 | /* Somebody else is using the BO right now */ | |
2318 | else | |
2319 | clear = true; | |
2320 | ||
2321 | r = amdgpu_vm_bo_update(adev, bo_va, clear); | |
2322 | if (r) | |
2323 | return r; | |
2324 | ||
2325 | if (!clear) | |
2326 | reservation_object_unlock(resv); | |
2327 | spin_lock(&vm->invalidated_lock); | |
2328 | } | |
2329 | spin_unlock(&vm->invalidated_lock); | |
2330 | ||
2331 | return 0; | |
2332 | } | |
2333 | ||
2334 | /** | |
2335 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
2336 | * | |
2337 | * @adev: amdgpu_device pointer | |
2338 | * @vm: requested vm | |
2339 | * @bo: amdgpu buffer object | |
2340 | * | |
2341 | * Add @bo into the requested vm. | |
2342 | * Add @bo to the list of bos associated with the vm | |
2343 | * | |
2344 | * Returns: | |
2345 | * Newly added bo_va or NULL for failure | |
2346 | * | |
2347 | * Object has to be reserved! | |
2348 | */ | |
2349 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
2350 | struct amdgpu_vm *vm, | |
2351 | struct amdgpu_bo *bo) | |
2352 | { | |
2353 | struct amdgpu_bo_va *bo_va; | |
2354 | ||
2355 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
2356 | if (bo_va == NULL) { | |
2357 | return NULL; | |
2358 | } | |
2359 | amdgpu_vm_bo_base_init(&bo_va->base, vm, bo); | |
2360 | ||
2361 | bo_va->ref_count = 1; | |
2362 | INIT_LIST_HEAD(&bo_va->valids); | |
2363 | INIT_LIST_HEAD(&bo_va->invalids); | |
2364 | ||
2365 | return bo_va; | |
2366 | } | |
2367 | ||
2368 | ||
2369 | /** | |
2370 | * amdgpu_vm_bo_insert_mapping - insert a new mapping | |
2371 | * | |
2372 | * @adev: amdgpu_device pointer | |
2373 | * @bo_va: bo_va to store the address | |
2374 | * @mapping: the mapping to insert | |
2375 | * | |
2376 | * Insert a new mapping into all structures. | |
2377 | */ | |
2378 | static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev, | |
2379 | struct amdgpu_bo_va *bo_va, | |
2380 | struct amdgpu_bo_va_mapping *mapping) | |
2381 | { | |
2382 | struct amdgpu_vm *vm = bo_va->base.vm; | |
2383 | struct amdgpu_bo *bo = bo_va->base.bo; | |
2384 | ||
2385 | mapping->bo_va = bo_va; | |
2386 | list_add(&mapping->list, &bo_va->invalids); | |
2387 | amdgpu_vm_it_insert(mapping, &vm->va); | |
2388 | ||
2389 | if (mapping->flags & AMDGPU_PTE_PRT) | |
2390 | amdgpu_vm_prt_get(adev); | |
2391 | ||
2392 | if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv && | |
2393 | !bo_va->base.moved) { | |
2394 | list_move(&bo_va->base.vm_status, &vm->moved); | |
2395 | } | |
2396 | trace_amdgpu_vm_bo_map(bo_va, mapping); | |
2397 | } | |
2398 | ||
2399 | /** | |
2400 | * amdgpu_vm_bo_map - map bo inside a vm | |
2401 | * | |
2402 | * @adev: amdgpu_device pointer | |
2403 | * @bo_va: bo_va to store the address | |
2404 | * @saddr: where to map the BO | |
2405 | * @offset: requested offset in the BO | |
2406 | * @size: BO size in bytes | |
2407 | * @flags: attributes of pages (read/write/valid/etc.) | |
2408 | * | |
2409 | * Add a mapping of the BO at the specefied addr into the VM. | |
2410 | * | |
2411 | * Returns: | |
2412 | * 0 for success, error for failure. | |
2413 | * | |
2414 | * Object has to be reserved and unreserved outside! | |
2415 | */ | |
2416 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
2417 | struct amdgpu_bo_va *bo_va, | |
2418 | uint64_t saddr, uint64_t offset, | |
2419 | uint64_t size, uint64_t flags) | |
2420 | { | |
2421 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
2422 | struct amdgpu_bo *bo = bo_va->base.bo; | |
2423 | struct amdgpu_vm *vm = bo_va->base.vm; | |
2424 | uint64_t eaddr; | |
2425 | ||
2426 | /* validate the parameters */ | |
2427 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
2428 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) | |
2429 | return -EINVAL; | |
2430 | ||
2431 | /* make sure object fit at this offset */ | |
2432 | eaddr = saddr + size - 1; | |
2433 | if (saddr >= eaddr || | |
2434 | (bo && offset + size > amdgpu_bo_size(bo))) | |
2435 | return -EINVAL; | |
2436 | ||
2437 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2438 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2439 | ||
2440 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); | |
2441 | if (tmp) { | |
2442 | /* bo and tmp overlap, invalid addr */ | |
2443 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
2444 | "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr, | |
2445 | tmp->start, tmp->last + 1); | |
2446 | return -EINVAL; | |
2447 | } | |
2448 | ||
2449 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
2450 | if (!mapping) | |
2451 | return -ENOMEM; | |
2452 | ||
2453 | mapping->start = saddr; | |
2454 | mapping->last = eaddr; | |
2455 | mapping->offset = offset; | |
2456 | mapping->flags = flags; | |
2457 | ||
2458 | amdgpu_vm_bo_insert_map(adev, bo_va, mapping); | |
2459 | ||
2460 | return 0; | |
2461 | } | |
2462 | ||
2463 | /** | |
2464 | * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings | |
2465 | * | |
2466 | * @adev: amdgpu_device pointer | |
2467 | * @bo_va: bo_va to store the address | |
2468 | * @saddr: where to map the BO | |
2469 | * @offset: requested offset in the BO | |
2470 | * @size: BO size in bytes | |
2471 | * @flags: attributes of pages (read/write/valid/etc.) | |
2472 | * | |
2473 | * Add a mapping of the BO at the specefied addr into the VM. Replace existing | |
2474 | * mappings as we do so. | |
2475 | * | |
2476 | * Returns: | |
2477 | * 0 for success, error for failure. | |
2478 | * | |
2479 | * Object has to be reserved and unreserved outside! | |
2480 | */ | |
2481 | int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, | |
2482 | struct amdgpu_bo_va *bo_va, | |
2483 | uint64_t saddr, uint64_t offset, | |
2484 | uint64_t size, uint64_t flags) | |
2485 | { | |
2486 | struct amdgpu_bo_va_mapping *mapping; | |
2487 | struct amdgpu_bo *bo = bo_va->base.bo; | |
2488 | uint64_t eaddr; | |
2489 | int r; | |
2490 | ||
2491 | /* validate the parameters */ | |
2492 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
2493 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) | |
2494 | return -EINVAL; | |
2495 | ||
2496 | /* make sure object fit at this offset */ | |
2497 | eaddr = saddr + size - 1; | |
2498 | if (saddr >= eaddr || | |
2499 | (bo && offset + size > amdgpu_bo_size(bo))) | |
2500 | return -EINVAL; | |
2501 | ||
2502 | /* Allocate all the needed memory */ | |
2503 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
2504 | if (!mapping) | |
2505 | return -ENOMEM; | |
2506 | ||
2507 | r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size); | |
2508 | if (r) { | |
2509 | kfree(mapping); | |
2510 | return r; | |
2511 | } | |
2512 | ||
2513 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2514 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2515 | ||
2516 | mapping->start = saddr; | |
2517 | mapping->last = eaddr; | |
2518 | mapping->offset = offset; | |
2519 | mapping->flags = flags; | |
2520 | ||
2521 | amdgpu_vm_bo_insert_map(adev, bo_va, mapping); | |
2522 | ||
2523 | return 0; | |
2524 | } | |
2525 | ||
2526 | /** | |
2527 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
2528 | * | |
2529 | * @adev: amdgpu_device pointer | |
2530 | * @bo_va: bo_va to remove the address from | |
2531 | * @saddr: where to the BO is mapped | |
2532 | * | |
2533 | * Remove a mapping of the BO at the specefied addr from the VM. | |
2534 | * | |
2535 | * Returns: | |
2536 | * 0 for success, error for failure. | |
2537 | * | |
2538 | * Object has to be reserved and unreserved outside! | |
2539 | */ | |
2540 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
2541 | struct amdgpu_bo_va *bo_va, | |
2542 | uint64_t saddr) | |
2543 | { | |
2544 | struct amdgpu_bo_va_mapping *mapping; | |
2545 | struct amdgpu_vm *vm = bo_va->base.vm; | |
2546 | bool valid = true; | |
2547 | ||
2548 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2549 | ||
2550 | list_for_each_entry(mapping, &bo_va->valids, list) { | |
2551 | if (mapping->start == saddr) | |
2552 | break; | |
2553 | } | |
2554 | ||
2555 | if (&mapping->list == &bo_va->valids) { | |
2556 | valid = false; | |
2557 | ||
2558 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
2559 | if (mapping->start == saddr) | |
2560 | break; | |
2561 | } | |
2562 | ||
2563 | if (&mapping->list == &bo_va->invalids) | |
2564 | return -ENOENT; | |
2565 | } | |
2566 | ||
2567 | list_del(&mapping->list); | |
2568 | amdgpu_vm_it_remove(mapping, &vm->va); | |
2569 | mapping->bo_va = NULL; | |
2570 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); | |
2571 | ||
2572 | if (valid) | |
2573 | list_add(&mapping->list, &vm->freed); | |
2574 | else | |
2575 | amdgpu_vm_free_mapping(adev, vm, mapping, | |
2576 | bo_va->last_pt_update); | |
2577 | ||
2578 | return 0; | |
2579 | } | |
2580 | ||
2581 | /** | |
2582 | * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range | |
2583 | * | |
2584 | * @adev: amdgpu_device pointer | |
2585 | * @vm: VM structure to use | |
2586 | * @saddr: start of the range | |
2587 | * @size: size of the range | |
2588 | * | |
2589 | * Remove all mappings in a range, split them as appropriate. | |
2590 | * | |
2591 | * Returns: | |
2592 | * 0 for success, error for failure. | |
2593 | */ | |
2594 | int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, | |
2595 | struct amdgpu_vm *vm, | |
2596 | uint64_t saddr, uint64_t size) | |
2597 | { | |
2598 | struct amdgpu_bo_va_mapping *before, *after, *tmp, *next; | |
2599 | LIST_HEAD(removed); | |
2600 | uint64_t eaddr; | |
2601 | ||
2602 | eaddr = saddr + size - 1; | |
2603 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2604 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2605 | ||
2606 | /* Allocate all the needed memory */ | |
2607 | before = kzalloc(sizeof(*before), GFP_KERNEL); | |
2608 | if (!before) | |
2609 | return -ENOMEM; | |
2610 | INIT_LIST_HEAD(&before->list); | |
2611 | ||
2612 | after = kzalloc(sizeof(*after), GFP_KERNEL); | |
2613 | if (!after) { | |
2614 | kfree(before); | |
2615 | return -ENOMEM; | |
2616 | } | |
2617 | INIT_LIST_HEAD(&after->list); | |
2618 | ||
2619 | /* Now gather all removed mappings */ | |
2620 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); | |
2621 | while (tmp) { | |
2622 | /* Remember mapping split at the start */ | |
2623 | if (tmp->start < saddr) { | |
2624 | before->start = tmp->start; | |
2625 | before->last = saddr - 1; | |
2626 | before->offset = tmp->offset; | |
2627 | before->flags = tmp->flags; | |
2628 | before->bo_va = tmp->bo_va; | |
2629 | list_add(&before->list, &tmp->bo_va->invalids); | |
2630 | } | |
2631 | ||
2632 | /* Remember mapping split at the end */ | |
2633 | if (tmp->last > eaddr) { | |
2634 | after->start = eaddr + 1; | |
2635 | after->last = tmp->last; | |
2636 | after->offset = tmp->offset; | |
2637 | after->offset += after->start - tmp->start; | |
2638 | after->flags = tmp->flags; | |
2639 | after->bo_va = tmp->bo_va; | |
2640 | list_add(&after->list, &tmp->bo_va->invalids); | |
2641 | } | |
2642 | ||
2643 | list_del(&tmp->list); | |
2644 | list_add(&tmp->list, &removed); | |
2645 | ||
2646 | tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr); | |
2647 | } | |
2648 | ||
2649 | /* And free them up */ | |
2650 | list_for_each_entry_safe(tmp, next, &removed, list) { | |
2651 | amdgpu_vm_it_remove(tmp, &vm->va); | |
2652 | list_del(&tmp->list); | |
2653 | ||
2654 | if (tmp->start < saddr) | |
2655 | tmp->start = saddr; | |
2656 | if (tmp->last > eaddr) | |
2657 | tmp->last = eaddr; | |
2658 | ||
2659 | tmp->bo_va = NULL; | |
2660 | list_add(&tmp->list, &vm->freed); | |
2661 | trace_amdgpu_vm_bo_unmap(NULL, tmp); | |
2662 | } | |
2663 | ||
2664 | /* Insert partial mapping before the range */ | |
2665 | if (!list_empty(&before->list)) { | |
2666 | amdgpu_vm_it_insert(before, &vm->va); | |
2667 | if (before->flags & AMDGPU_PTE_PRT) | |
2668 | amdgpu_vm_prt_get(adev); | |
2669 | } else { | |
2670 | kfree(before); | |
2671 | } | |
2672 | ||
2673 | /* Insert partial mapping after the range */ | |
2674 | if (!list_empty(&after->list)) { | |
2675 | amdgpu_vm_it_insert(after, &vm->va); | |
2676 | if (after->flags & AMDGPU_PTE_PRT) | |
2677 | amdgpu_vm_prt_get(adev); | |
2678 | } else { | |
2679 | kfree(after); | |
2680 | } | |
2681 | ||
2682 | return 0; | |
2683 | } | |
2684 | ||
2685 | /** | |
2686 | * amdgpu_vm_bo_lookup_mapping - find mapping by address | |
2687 | * | |
2688 | * @vm: the requested VM | |
2689 | * @addr: the address | |
2690 | * | |
2691 | * Find a mapping by it's address. | |
2692 | * | |
2693 | * Returns: | |
2694 | * The amdgpu_bo_va_mapping matching for addr or NULL | |
2695 | * | |
2696 | */ | |
2697 | struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, | |
2698 | uint64_t addr) | |
2699 | { | |
2700 | return amdgpu_vm_it_iter_first(&vm->va, addr, addr); | |
2701 | } | |
2702 | ||
2703 | /** | |
2704 | * amdgpu_vm_bo_trace_cs - trace all reserved mappings | |
2705 | * | |
2706 | * @vm: the requested vm | |
2707 | * @ticket: CS ticket | |
2708 | * | |
2709 | * Trace all mappings of BOs reserved during a command submission. | |
2710 | */ | |
2711 | void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket) | |
2712 | { | |
2713 | struct amdgpu_bo_va_mapping *mapping; | |
2714 | ||
2715 | if (!trace_amdgpu_vm_bo_cs_enabled()) | |
2716 | return; | |
2717 | ||
2718 | for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping; | |
2719 | mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) { | |
2720 | if (mapping->bo_va && mapping->bo_va->base.bo) { | |
2721 | struct amdgpu_bo *bo; | |
2722 | ||
2723 | bo = mapping->bo_va->base.bo; | |
2724 | if (READ_ONCE(bo->tbo.resv->lock.ctx) != ticket) | |
2725 | continue; | |
2726 | } | |
2727 | ||
2728 | trace_amdgpu_vm_bo_cs(mapping); | |
2729 | } | |
2730 | } | |
2731 | ||
2732 | /** | |
2733 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
2734 | * | |
2735 | * @adev: amdgpu_device pointer | |
2736 | * @bo_va: requested bo_va | |
2737 | * | |
2738 | * Remove @bo_va->bo from the requested vm. | |
2739 | * | |
2740 | * Object have to be reserved! | |
2741 | */ | |
2742 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
2743 | struct amdgpu_bo_va *bo_va) | |
2744 | { | |
2745 | struct amdgpu_bo_va_mapping *mapping, *next; | |
2746 | struct amdgpu_bo *bo = bo_va->base.bo; | |
2747 | struct amdgpu_vm *vm = bo_va->base.vm; | |
2748 | struct amdgpu_vm_bo_base **base; | |
2749 | ||
2750 | if (bo) { | |
2751 | if (bo->tbo.resv == vm->root.base.bo->tbo.resv) | |
2752 | vm->bulk_moveable = false; | |
2753 | ||
2754 | for (base = &bo_va->base.bo->vm_bo; *base; | |
2755 | base = &(*base)->next) { | |
2756 | if (*base != &bo_va->base) | |
2757 | continue; | |
2758 | ||
2759 | *base = bo_va->base.next; | |
2760 | break; | |
2761 | } | |
2762 | } | |
2763 | ||
2764 | spin_lock(&vm->invalidated_lock); | |
2765 | list_del(&bo_va->base.vm_status); | |
2766 | spin_unlock(&vm->invalidated_lock); | |
2767 | ||
2768 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { | |
2769 | list_del(&mapping->list); | |
2770 | amdgpu_vm_it_remove(mapping, &vm->va); | |
2771 | mapping->bo_va = NULL; | |
2772 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); | |
2773 | list_add(&mapping->list, &vm->freed); | |
2774 | } | |
2775 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
2776 | list_del(&mapping->list); | |
2777 | amdgpu_vm_it_remove(mapping, &vm->va); | |
2778 | amdgpu_vm_free_mapping(adev, vm, mapping, | |
2779 | bo_va->last_pt_update); | |
2780 | } | |
2781 | ||
2782 | dma_fence_put(bo_va->last_pt_update); | |
2783 | kfree(bo_va); | |
2784 | } | |
2785 | ||
2786 | /** | |
2787 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
2788 | * | |
2789 | * @adev: amdgpu_device pointer | |
2790 | * @bo: amdgpu buffer object | |
2791 | * @evicted: is the BO evicted | |
2792 | * | |
2793 | * Mark @bo as invalid. | |
2794 | */ | |
2795 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
2796 | struct amdgpu_bo *bo, bool evicted) | |
2797 | { | |
2798 | struct amdgpu_vm_bo_base *bo_base; | |
2799 | ||
2800 | /* shadow bo doesn't have bo base, its validation needs its parent */ | |
2801 | if (bo->parent && bo->parent->shadow == bo) | |
2802 | bo = bo->parent; | |
2803 | ||
2804 | for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) { | |
2805 | struct amdgpu_vm *vm = bo_base->vm; | |
2806 | ||
2807 | if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) { | |
2808 | amdgpu_vm_bo_evicted(bo_base); | |
2809 | continue; | |
2810 | } | |
2811 | ||
2812 | if (bo_base->moved) | |
2813 | continue; | |
2814 | bo_base->moved = true; | |
2815 | ||
2816 | if (bo->tbo.type == ttm_bo_type_kernel) | |
2817 | amdgpu_vm_bo_relocated(bo_base); | |
2818 | else if (bo->tbo.resv == vm->root.base.bo->tbo.resv) | |
2819 | amdgpu_vm_bo_moved(bo_base); | |
2820 | else | |
2821 | amdgpu_vm_bo_invalidated(bo_base); | |
2822 | } | |
2823 | } | |
2824 | ||
2825 | /** | |
2826 | * amdgpu_vm_get_block_size - calculate VM page table size as power of two | |
2827 | * | |
2828 | * @vm_size: VM size | |
2829 | * | |
2830 | * Returns: | |
2831 | * VM page table as power of two | |
2832 | */ | |
2833 | static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) | |
2834 | { | |
2835 | /* Total bits covered by PD + PTs */ | |
2836 | unsigned bits = ilog2(vm_size) + 18; | |
2837 | ||
2838 | /* Make sure the PD is 4K in size up to 8GB address space. | |
2839 | Above that split equal between PD and PTs */ | |
2840 | if (vm_size <= 8) | |
2841 | return (bits - 9); | |
2842 | else | |
2843 | return ((bits + 3) / 2); | |
2844 | } | |
2845 | ||
2846 | /** | |
2847 | * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size | |
2848 | * | |
2849 | * @adev: amdgpu_device pointer | |
2850 | * @min_vm_size: the minimum vm size in GB if it's set auto | |
2851 | * @fragment_size_default: Default PTE fragment size | |
2852 | * @max_level: max VMPT level | |
2853 | * @max_bits: max address space size in bits | |
2854 | * | |
2855 | */ | |
2856 | void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, | |
2857 | uint32_t fragment_size_default, unsigned max_level, | |
2858 | unsigned max_bits) | |
2859 | { | |
2860 | unsigned int max_size = 1 << (max_bits - 30); | |
2861 | unsigned int vm_size; | |
2862 | uint64_t tmp; | |
2863 | ||
2864 | /* adjust vm size first */ | |
2865 | if (amdgpu_vm_size != -1) { | |
2866 | vm_size = amdgpu_vm_size; | |
2867 | if (vm_size > max_size) { | |
2868 | dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n", | |
2869 | amdgpu_vm_size, max_size); | |
2870 | vm_size = max_size; | |
2871 | } | |
2872 | } else { | |
2873 | struct sysinfo si; | |
2874 | unsigned int phys_ram_gb; | |
2875 | ||
2876 | /* Optimal VM size depends on the amount of physical | |
2877 | * RAM available. Underlying requirements and | |
2878 | * assumptions: | |
2879 | * | |
2880 | * - Need to map system memory and VRAM from all GPUs | |
2881 | * - VRAM from other GPUs not known here | |
2882 | * - Assume VRAM <= system memory | |
2883 | * - On GFX8 and older, VM space can be segmented for | |
2884 | * different MTYPEs | |
2885 | * - Need to allow room for fragmentation, guard pages etc. | |
2886 | * | |
2887 | * This adds up to a rough guess of system memory x3. | |
2888 | * Round up to power of two to maximize the available | |
2889 | * VM size with the given page table size. | |
2890 | */ | |
2891 | si_meminfo(&si); | |
2892 | phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit + | |
2893 | (1 << 30) - 1) >> 30; | |
2894 | vm_size = roundup_pow_of_two( | |
2895 | min(max(phys_ram_gb * 3, min_vm_size), max_size)); | |
2896 | } | |
2897 | ||
2898 | adev->vm_manager.max_pfn = (uint64_t)vm_size << 18; | |
2899 | ||
2900 | tmp = roundup_pow_of_two(adev->vm_manager.max_pfn); | |
2901 | if (amdgpu_vm_block_size != -1) | |
2902 | tmp >>= amdgpu_vm_block_size - 9; | |
2903 | tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1; | |
2904 | adev->vm_manager.num_level = min(max_level, (unsigned)tmp); | |
2905 | switch (adev->vm_manager.num_level) { | |
2906 | case 3: | |
2907 | adev->vm_manager.root_level = AMDGPU_VM_PDB2; | |
2908 | break; | |
2909 | case 2: | |
2910 | adev->vm_manager.root_level = AMDGPU_VM_PDB1; | |
2911 | break; | |
2912 | case 1: | |
2913 | adev->vm_manager.root_level = AMDGPU_VM_PDB0; | |
2914 | break; | |
2915 | default: | |
2916 | dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n"); | |
2917 | } | |
2918 | /* block size depends on vm size and hw setup*/ | |
2919 | if (amdgpu_vm_block_size != -1) | |
2920 | adev->vm_manager.block_size = | |
2921 | min((unsigned)amdgpu_vm_block_size, max_bits | |
2922 | - AMDGPU_GPU_PAGE_SHIFT | |
2923 | - 9 * adev->vm_manager.num_level); | |
2924 | else if (adev->vm_manager.num_level > 1) | |
2925 | adev->vm_manager.block_size = 9; | |
2926 | else | |
2927 | adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp); | |
2928 | ||
2929 | if (amdgpu_vm_fragment_size == -1) | |
2930 | adev->vm_manager.fragment_size = fragment_size_default; | |
2931 | else | |
2932 | adev->vm_manager.fragment_size = amdgpu_vm_fragment_size; | |
2933 | ||
2934 | DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n", | |
2935 | vm_size, adev->vm_manager.num_level + 1, | |
2936 | adev->vm_manager.block_size, | |
2937 | adev->vm_manager.fragment_size); | |
2938 | } | |
2939 | ||
2940 | static struct amdgpu_retryfault_hashtable *init_fault_hash(void) | |
2941 | { | |
2942 | struct amdgpu_retryfault_hashtable *fault_hash; | |
2943 | ||
2944 | fault_hash = kmalloc(sizeof(*fault_hash), GFP_KERNEL); | |
2945 | if (!fault_hash) | |
2946 | return fault_hash; | |
2947 | ||
2948 | INIT_CHASH_TABLE(fault_hash->hash, | |
2949 | AMDGPU_PAGEFAULT_HASH_BITS, 8, 0); | |
2950 | spin_lock_init(&fault_hash->lock); | |
2951 | fault_hash->count = 0; | |
2952 | ||
2953 | return fault_hash; | |
2954 | } | |
2955 | ||
2956 | /** | |
2957 | * amdgpu_vm_init - initialize a vm instance | |
2958 | * | |
2959 | * @adev: amdgpu_device pointer | |
2960 | * @vm: requested vm | |
2961 | * @vm_context: Indicates if it GFX or Compute context | |
2962 | * @pasid: Process address space identifier | |
2963 | * | |
2964 | * Init @vm fields. | |
2965 | * | |
2966 | * Returns: | |
2967 | * 0 for success, error for failure. | |
2968 | */ | |
2969 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, | |
2970 | int vm_context, unsigned int pasid) | |
2971 | { | |
2972 | struct amdgpu_bo_param bp; | |
2973 | struct amdgpu_bo *root; | |
2974 | int r, i; | |
2975 | ||
2976 | vm->va = RB_ROOT_CACHED; | |
2977 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) | |
2978 | vm->reserved_vmid[i] = NULL; | |
2979 | INIT_LIST_HEAD(&vm->evicted); | |
2980 | INIT_LIST_HEAD(&vm->relocated); | |
2981 | INIT_LIST_HEAD(&vm->moved); | |
2982 | INIT_LIST_HEAD(&vm->idle); | |
2983 | INIT_LIST_HEAD(&vm->invalidated); | |
2984 | spin_lock_init(&vm->invalidated_lock); | |
2985 | INIT_LIST_HEAD(&vm->freed); | |
2986 | ||
2987 | /* create scheduler entity for page table updates */ | |
2988 | r = drm_sched_entity_init(&vm->entity, adev->vm_manager.vm_pte_rqs, | |
2989 | adev->vm_manager.vm_pte_num_rqs, NULL); | |
2990 | if (r) | |
2991 | return r; | |
2992 | ||
2993 | vm->pte_support_ats = false; | |
2994 | ||
2995 | if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) { | |
2996 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & | |
2997 | AMDGPU_VM_USE_CPU_FOR_COMPUTE); | |
2998 | ||
2999 | if (adev->asic_type == CHIP_RAVEN) | |
3000 | vm->pte_support_ats = true; | |
3001 | } else { | |
3002 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & | |
3003 | AMDGPU_VM_USE_CPU_FOR_GFX); | |
3004 | } | |
3005 | DRM_DEBUG_DRIVER("VM update mode is %s\n", | |
3006 | vm->use_cpu_for_update ? "CPU" : "SDMA"); | |
3007 | WARN_ONCE((vm->use_cpu_for_update & !amdgpu_gmc_vram_full_visible(&adev->gmc)), | |
3008 | "CPU update of VM recommended only for large BAR system\n"); | |
3009 | vm->last_update = NULL; | |
3010 | ||
3011 | amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, &bp); | |
3012 | if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) | |
3013 | bp.flags &= ~AMDGPU_GEM_CREATE_SHADOW; | |
3014 | r = amdgpu_bo_create(adev, &bp, &root); | |
3015 | if (r) | |
3016 | goto error_free_sched_entity; | |
3017 | ||
3018 | r = amdgpu_bo_reserve(root, true); | |
3019 | if (r) | |
3020 | goto error_free_root; | |
3021 | ||
3022 | r = reservation_object_reserve_shared(root->tbo.resv, 1); | |
3023 | if (r) | |
3024 | goto error_unreserve; | |
3025 | ||
3026 | r = amdgpu_vm_clear_bo(adev, vm, root, | |
3027 | adev->vm_manager.root_level, | |
3028 | vm->pte_support_ats); | |
3029 | if (r) | |
3030 | goto error_unreserve; | |
3031 | ||
3032 | amdgpu_vm_bo_base_init(&vm->root.base, vm, root); | |
3033 | amdgpu_bo_unreserve(vm->root.base.bo); | |
3034 | ||
3035 | if (pasid) { | |
3036 | unsigned long flags; | |
3037 | ||
3038 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
3039 | r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1, | |
3040 | GFP_ATOMIC); | |
3041 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
3042 | if (r < 0) | |
3043 | goto error_free_root; | |
3044 | ||
3045 | vm->pasid = pasid; | |
3046 | } | |
3047 | ||
3048 | vm->fault_hash = init_fault_hash(); | |
3049 | if (!vm->fault_hash) { | |
3050 | r = -ENOMEM; | |
3051 | goto error_free_root; | |
3052 | } | |
3053 | ||
3054 | INIT_KFIFO(vm->faults); | |
3055 | vm->fault_credit = 16; | |
3056 | ||
3057 | return 0; | |
3058 | ||
3059 | error_unreserve: | |
3060 | amdgpu_bo_unreserve(vm->root.base.bo); | |
3061 | ||
3062 | error_free_root: | |
3063 | amdgpu_bo_unref(&vm->root.base.bo->shadow); | |
3064 | amdgpu_bo_unref(&vm->root.base.bo); | |
3065 | vm->root.base.bo = NULL; | |
3066 | ||
3067 | error_free_sched_entity: | |
3068 | drm_sched_entity_destroy(&vm->entity); | |
3069 | ||
3070 | return r; | |
3071 | } | |
3072 | ||
3073 | /** | |
3074 | * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM | |
3075 | * | |
3076 | * @adev: amdgpu_device pointer | |
3077 | * @vm: requested vm | |
3078 | * | |
3079 | * This only works on GFX VMs that don't have any BOs added and no | |
3080 | * page tables allocated yet. | |
3081 | * | |
3082 | * Changes the following VM parameters: | |
3083 | * - use_cpu_for_update | |
3084 | * - pte_supports_ats | |
3085 | * - pasid (old PASID is released, because compute manages its own PASIDs) | |
3086 | * | |
3087 | * Reinitializes the page directory to reflect the changed ATS | |
3088 | * setting. | |
3089 | * | |
3090 | * Returns: | |
3091 | * 0 for success, -errno for errors. | |
3092 | */ | |
3093 | int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid) | |
3094 | { | |
3095 | bool pte_support_ats = (adev->asic_type == CHIP_RAVEN); | |
3096 | int r; | |
3097 | ||
3098 | r = amdgpu_bo_reserve(vm->root.base.bo, true); | |
3099 | if (r) | |
3100 | return r; | |
3101 | ||
3102 | /* Sanity checks */ | |
3103 | if (!RB_EMPTY_ROOT(&vm->va.rb_root) || vm->root.entries) { | |
3104 | r = -EINVAL; | |
3105 | goto unreserve_bo; | |
3106 | } | |
3107 | ||
3108 | if (pasid) { | |
3109 | unsigned long flags; | |
3110 | ||
3111 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
3112 | r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1, | |
3113 | GFP_ATOMIC); | |
3114 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
3115 | ||
3116 | if (r == -ENOSPC) | |
3117 | goto unreserve_bo; | |
3118 | r = 0; | |
3119 | } | |
3120 | ||
3121 | /* Check if PD needs to be reinitialized and do it before | |
3122 | * changing any other state, in case it fails. | |
3123 | */ | |
3124 | if (pte_support_ats != vm->pte_support_ats) { | |
3125 | r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo, | |
3126 | adev->vm_manager.root_level, | |
3127 | pte_support_ats); | |
3128 | if (r) | |
3129 | goto free_idr; | |
3130 | } | |
3131 | ||
3132 | /* Update VM state */ | |
3133 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & | |
3134 | AMDGPU_VM_USE_CPU_FOR_COMPUTE); | |
3135 | vm->pte_support_ats = pte_support_ats; | |
3136 | DRM_DEBUG_DRIVER("VM update mode is %s\n", | |
3137 | vm->use_cpu_for_update ? "CPU" : "SDMA"); | |
3138 | WARN_ONCE((vm->use_cpu_for_update & !amdgpu_gmc_vram_full_visible(&adev->gmc)), | |
3139 | "CPU update of VM recommended only for large BAR system\n"); | |
3140 | ||
3141 | if (vm->pasid) { | |
3142 | unsigned long flags; | |
3143 | ||
3144 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
3145 | idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); | |
3146 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
3147 | ||
3148 | /* Free the original amdgpu allocated pasid | |
3149 | * Will be replaced with kfd allocated pasid | |
3150 | */ | |
3151 | amdgpu_pasid_free(vm->pasid); | |
3152 | vm->pasid = 0; | |
3153 | } | |
3154 | ||
3155 | /* Free the shadow bo for compute VM */ | |
3156 | amdgpu_bo_unref(&vm->root.base.bo->shadow); | |
3157 | ||
3158 | if (pasid) | |
3159 | vm->pasid = pasid; | |
3160 | ||
3161 | goto unreserve_bo; | |
3162 | ||
3163 | free_idr: | |
3164 | if (pasid) { | |
3165 | unsigned long flags; | |
3166 | ||
3167 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
3168 | idr_remove(&adev->vm_manager.pasid_idr, pasid); | |
3169 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
3170 | } | |
3171 | unreserve_bo: | |
3172 | amdgpu_bo_unreserve(vm->root.base.bo); | |
3173 | return r; | |
3174 | } | |
3175 | ||
3176 | /** | |
3177 | * amdgpu_vm_release_compute - release a compute vm | |
3178 | * @adev: amdgpu_device pointer | |
3179 | * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute | |
3180 | * | |
3181 | * This is a correspondant of amdgpu_vm_make_compute. It decouples compute | |
3182 | * pasid from vm. Compute should stop use of vm after this call. | |
3183 | */ | |
3184 | void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
3185 | { | |
3186 | if (vm->pasid) { | |
3187 | unsigned long flags; | |
3188 | ||
3189 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
3190 | idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); | |
3191 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
3192 | } | |
3193 | vm->pasid = 0; | |
3194 | } | |
3195 | ||
3196 | /** | |
3197 | * amdgpu_vm_fini - tear down a vm instance | |
3198 | * | |
3199 | * @adev: amdgpu_device pointer | |
3200 | * @vm: requested vm | |
3201 | * | |
3202 | * Tear down @vm. | |
3203 | * Unbind the VM and remove all bos from the vm bo list | |
3204 | */ | |
3205 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
3206 | { | |
3207 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
3208 | bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt; | |
3209 | struct amdgpu_bo *root; | |
3210 | u64 fault; | |
3211 | int i, r; | |
3212 | ||
3213 | amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm); | |
3214 | ||
3215 | /* Clear pending page faults from IH when the VM is destroyed */ | |
3216 | while (kfifo_get(&vm->faults, &fault)) | |
3217 | amdgpu_vm_clear_fault(vm->fault_hash, fault); | |
3218 | ||
3219 | if (vm->pasid) { | |
3220 | unsigned long flags; | |
3221 | ||
3222 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
3223 | idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); | |
3224 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
3225 | } | |
3226 | ||
3227 | kfree(vm->fault_hash); | |
3228 | vm->fault_hash = NULL; | |
3229 | ||
3230 | drm_sched_entity_destroy(&vm->entity); | |
3231 | ||
3232 | if (!RB_EMPTY_ROOT(&vm->va.rb_root)) { | |
3233 | dev_err(adev->dev, "still active bo inside vm\n"); | |
3234 | } | |
3235 | rbtree_postorder_for_each_entry_safe(mapping, tmp, | |
3236 | &vm->va.rb_root, rb) { | |
3237 | /* Don't remove the mapping here, we don't want to trigger a | |
3238 | * rebalance and the tree is about to be destroyed anyway. | |
3239 | */ | |
3240 | list_del(&mapping->list); | |
3241 | kfree(mapping); | |
3242 | } | |
3243 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
3244 | if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) { | |
3245 | amdgpu_vm_prt_fini(adev, vm); | |
3246 | prt_fini_needed = false; | |
3247 | } | |
3248 | ||
3249 | list_del(&mapping->list); | |
3250 | amdgpu_vm_free_mapping(adev, vm, mapping, NULL); | |
3251 | } | |
3252 | ||
3253 | root = amdgpu_bo_ref(vm->root.base.bo); | |
3254 | r = amdgpu_bo_reserve(root, true); | |
3255 | if (r) { | |
3256 | dev_err(adev->dev, "Leaking page tables because BO reservation failed\n"); | |
3257 | } else { | |
3258 | amdgpu_vm_free_pts(adev, vm); | |
3259 | amdgpu_bo_unreserve(root); | |
3260 | } | |
3261 | amdgpu_bo_unref(&root); | |
3262 | dma_fence_put(vm->last_update); | |
3263 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) | |
3264 | amdgpu_vmid_free_reserved(adev, vm, i); | |
3265 | } | |
3266 | ||
3267 | /** | |
3268 | * amdgpu_vm_pasid_fault_credit - Check fault credit for given PASID | |
3269 | * | |
3270 | * @adev: amdgpu_device pointer | |
3271 | * @pasid: PASID do identify the VM | |
3272 | * | |
3273 | * This function is expected to be called in interrupt context. | |
3274 | * | |
3275 | * Returns: | |
3276 | * True if there was fault credit, false otherwise | |
3277 | */ | |
3278 | bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev, | |
3279 | unsigned int pasid) | |
3280 | { | |
3281 | struct amdgpu_vm *vm; | |
3282 | ||
3283 | spin_lock(&adev->vm_manager.pasid_lock); | |
3284 | vm = idr_find(&adev->vm_manager.pasid_idr, pasid); | |
3285 | if (!vm) { | |
3286 | /* VM not found, can't track fault credit */ | |
3287 | spin_unlock(&adev->vm_manager.pasid_lock); | |
3288 | return true; | |
3289 | } | |
3290 | ||
3291 | /* No lock needed. only accessed by IRQ handler */ | |
3292 | if (!vm->fault_credit) { | |
3293 | /* Too many faults in this VM */ | |
3294 | spin_unlock(&adev->vm_manager.pasid_lock); | |
3295 | return false; | |
3296 | } | |
3297 | ||
3298 | vm->fault_credit--; | |
3299 | spin_unlock(&adev->vm_manager.pasid_lock); | |
3300 | return true; | |
3301 | } | |
3302 | ||
3303 | /** | |
3304 | * amdgpu_vm_manager_init - init the VM manager | |
3305 | * | |
3306 | * @adev: amdgpu_device pointer | |
3307 | * | |
3308 | * Initialize the VM manager structures | |
3309 | */ | |
3310 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
3311 | { | |
3312 | unsigned i; | |
3313 | ||
3314 | amdgpu_vmid_mgr_init(adev); | |
3315 | ||
3316 | adev->vm_manager.fence_context = | |
3317 | dma_fence_context_alloc(AMDGPU_MAX_RINGS); | |
3318 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) | |
3319 | adev->vm_manager.seqno[i] = 0; | |
3320 | ||
3321 | spin_lock_init(&adev->vm_manager.prt_lock); | |
3322 | atomic_set(&adev->vm_manager.num_prt_users, 0); | |
3323 | ||
3324 | /* If not overridden by the user, by default, only in large BAR systems | |
3325 | * Compute VM tables will be updated by CPU | |
3326 | */ | |
3327 | #ifdef CONFIG_X86_64 | |
3328 | if (amdgpu_vm_update_mode == -1) { | |
3329 | if (amdgpu_gmc_vram_full_visible(&adev->gmc)) | |
3330 | adev->vm_manager.vm_update_mode = | |
3331 | AMDGPU_VM_USE_CPU_FOR_COMPUTE; | |
3332 | else | |
3333 | adev->vm_manager.vm_update_mode = 0; | |
3334 | } else | |
3335 | adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode; | |
3336 | #else | |
3337 | adev->vm_manager.vm_update_mode = 0; | |
3338 | #endif | |
3339 | ||
3340 | idr_init(&adev->vm_manager.pasid_idr); | |
3341 | spin_lock_init(&adev->vm_manager.pasid_lock); | |
3342 | } | |
3343 | ||
3344 | /** | |
3345 | * amdgpu_vm_manager_fini - cleanup VM manager | |
3346 | * | |
3347 | * @adev: amdgpu_device pointer | |
3348 | * | |
3349 | * Cleanup the VM manager and free resources. | |
3350 | */ | |
3351 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
3352 | { | |
3353 | WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr)); | |
3354 | idr_destroy(&adev->vm_manager.pasid_idr); | |
3355 | ||
3356 | amdgpu_vmid_mgr_fini(adev); | |
3357 | } | |
3358 | ||
3359 | /** | |
3360 | * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs. | |
3361 | * | |
3362 | * @dev: drm device pointer | |
3363 | * @data: drm_amdgpu_vm | |
3364 | * @filp: drm file pointer | |
3365 | * | |
3366 | * Returns: | |
3367 | * 0 for success, -errno for errors. | |
3368 | */ | |
3369 | int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) | |
3370 | { | |
3371 | union drm_amdgpu_vm *args = data; | |
3372 | struct amdgpu_device *adev = dev->dev_private; | |
3373 | struct amdgpu_fpriv *fpriv = filp->driver_priv; | |
3374 | int r; | |
3375 | ||
3376 | switch (args->in.op) { | |
3377 | case AMDGPU_VM_OP_RESERVE_VMID: | |
3378 | /* current, we only have requirement to reserve vmid from gfxhub */ | |
3379 | r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB); | |
3380 | if (r) | |
3381 | return r; | |
3382 | break; | |
3383 | case AMDGPU_VM_OP_UNRESERVE_VMID: | |
3384 | amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB); | |
3385 | break; | |
3386 | default: | |
3387 | return -EINVAL; | |
3388 | } | |
3389 | ||
3390 | return 0; | |
3391 | } | |
3392 | ||
3393 | /** | |
3394 | * amdgpu_vm_get_task_info - Extracts task info for a PASID. | |
3395 | * | |
3396 | * @adev: drm device pointer | |
3397 | * @pasid: PASID identifier for VM | |
3398 | * @task_info: task_info to fill. | |
3399 | */ | |
3400 | void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid, | |
3401 | struct amdgpu_task_info *task_info) | |
3402 | { | |
3403 | struct amdgpu_vm *vm; | |
3404 | ||
3405 | spin_lock(&adev->vm_manager.pasid_lock); | |
3406 | ||
3407 | vm = idr_find(&adev->vm_manager.pasid_idr, pasid); | |
3408 | if (vm) | |
3409 | *task_info = vm->task_info; | |
3410 | ||
3411 | spin_unlock(&adev->vm_manager.pasid_lock); | |
3412 | } | |
3413 | ||
3414 | /** | |
3415 | * amdgpu_vm_set_task_info - Sets VMs task info. | |
3416 | * | |
3417 | * @vm: vm for which to set the info | |
3418 | */ | |
3419 | void amdgpu_vm_set_task_info(struct amdgpu_vm *vm) | |
3420 | { | |
3421 | if (!vm->task_info.pid) { | |
3422 | vm->task_info.pid = current->pid; | |
3423 | get_task_comm(vm->task_info.task_name, current); | |
3424 | ||
3425 | if (current->group_leader->mm == current->mm) { | |
3426 | vm->task_info.tgid = current->group_leader->pid; | |
3427 | get_task_comm(vm->task_info.process_name, current->group_leader); | |
3428 | } | |
3429 | } | |
3430 | } | |
3431 | ||
3432 | /** | |
3433 | * amdgpu_vm_add_fault - Add a page fault record to fault hash table | |
3434 | * | |
3435 | * @fault_hash: fault hash table | |
3436 | * @key: 64-bit encoding of PASID and address | |
3437 | * | |
3438 | * This should be called when a retry page fault interrupt is | |
3439 | * received. If this is a new page fault, it will be added to a hash | |
3440 | * table. The return value indicates whether this is a new fault, or | |
3441 | * a fault that was already known and is already being handled. | |
3442 | * | |
3443 | * If there are too many pending page faults, this will fail. Retry | |
3444 | * interrupts should be ignored in this case until there is enough | |
3445 | * free space. | |
3446 | * | |
3447 | * Returns 0 if the fault was added, 1 if the fault was already known, | |
3448 | * -ENOSPC if there are too many pending faults. | |
3449 | */ | |
3450 | int amdgpu_vm_add_fault(struct amdgpu_retryfault_hashtable *fault_hash, u64 key) | |
3451 | { | |
3452 | unsigned long flags; | |
3453 | int r = -ENOSPC; | |
3454 | ||
3455 | if (WARN_ON_ONCE(!fault_hash)) | |
3456 | /* Should be allocated in amdgpu_vm_init | |
3457 | */ | |
3458 | return r; | |
3459 | ||
3460 | spin_lock_irqsave(&fault_hash->lock, flags); | |
3461 | ||
3462 | /* Only let the hash table fill up to 50% for best performance */ | |
3463 | if (fault_hash->count >= (1 << (AMDGPU_PAGEFAULT_HASH_BITS-1))) | |
3464 | goto unlock_out; | |
3465 | ||
3466 | r = chash_table_copy_in(&fault_hash->hash, key, NULL); | |
3467 | if (!r) | |
3468 | fault_hash->count++; | |
3469 | ||
3470 | /* chash_table_copy_in should never fail unless we're losing count */ | |
3471 | WARN_ON_ONCE(r < 0); | |
3472 | ||
3473 | unlock_out: | |
3474 | spin_unlock_irqrestore(&fault_hash->lock, flags); | |
3475 | return r; | |
3476 | } | |
3477 | ||
3478 | /** | |
3479 | * amdgpu_vm_clear_fault - Remove a page fault record | |
3480 | * | |
3481 | * @fault_hash: fault hash table | |
3482 | * @key: 64-bit encoding of PASID and address | |
3483 | * | |
3484 | * This should be called when a page fault has been handled. Any | |
3485 | * future interrupt with this key will be processed as a new | |
3486 | * page fault. | |
3487 | */ | |
3488 | void amdgpu_vm_clear_fault(struct amdgpu_retryfault_hashtable *fault_hash, u64 key) | |
3489 | { | |
3490 | unsigned long flags; | |
3491 | int r; | |
3492 | ||
3493 | if (!fault_hash) | |
3494 | return; | |
3495 | ||
3496 | spin_lock_irqsave(&fault_hash->lock, flags); | |
3497 | ||
3498 | r = chash_table_remove(&fault_hash->hash, key, NULL); | |
3499 | if (!WARN_ON_ONCE(r < 0)) { | |
3500 | fault_hash->count--; | |
3501 | WARN_ON_ONCE(fault_hash->count < 0); | |
3502 | } | |
3503 | ||
3504 | spin_unlock_irqrestore(&fault_hash->lock, flags); | |
3505 | } |