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1 | /* | |
2 | * Copyright 2015 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | */ | |
22 | ||
23 | #ifndef __AMD_SHARED_H__ | |
24 | #define __AMD_SHARED_H__ | |
25 | ||
26 | #include <drm/amd_asic_type.h> | |
27 | ||
28 | #define AMD_MAX_USEC_TIMEOUT 200000 /* 200 ms */ | |
29 | ||
30 | /* | |
31 | * Chip flags | |
32 | */ | |
33 | enum amd_chip_flags { | |
34 | AMD_ASIC_MASK = 0x0000ffffUL, | |
35 | AMD_FLAGS_MASK = 0xffff0000UL, | |
36 | AMD_IS_MOBILITY = 0x00010000UL, | |
37 | AMD_IS_APU = 0x00020000UL, | |
38 | AMD_IS_PX = 0x00040000UL, | |
39 | AMD_EXP_HW_SUPPORT = 0x00080000UL, | |
40 | }; | |
41 | ||
42 | enum amd_ip_block_type { | |
43 | AMD_IP_BLOCK_TYPE_COMMON, | |
44 | AMD_IP_BLOCK_TYPE_GMC, | |
45 | AMD_IP_BLOCK_TYPE_IH, | |
46 | AMD_IP_BLOCK_TYPE_SMC, | |
47 | AMD_IP_BLOCK_TYPE_PSP, | |
48 | AMD_IP_BLOCK_TYPE_DCE, | |
49 | AMD_IP_BLOCK_TYPE_GFX, | |
50 | AMD_IP_BLOCK_TYPE_SDMA, | |
51 | AMD_IP_BLOCK_TYPE_UVD, | |
52 | AMD_IP_BLOCK_TYPE_VCE, | |
53 | AMD_IP_BLOCK_TYPE_ACP, | |
54 | AMD_IP_BLOCK_TYPE_VCN | |
55 | }; | |
56 | ||
57 | enum amd_clockgating_state { | |
58 | AMD_CG_STATE_GATE = 0, | |
59 | AMD_CG_STATE_UNGATE, | |
60 | }; | |
61 | ||
62 | enum amd_dpm_forced_level { | |
63 | AMD_DPM_FORCED_LEVEL_AUTO = 0x1, | |
64 | AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, | |
65 | AMD_DPM_FORCED_LEVEL_LOW = 0x4, | |
66 | AMD_DPM_FORCED_LEVEL_HIGH = 0x8, | |
67 | AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, | |
68 | AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, | |
69 | AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, | |
70 | AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, | |
71 | AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, | |
72 | }; | |
73 | ||
74 | enum amd_powergating_state { | |
75 | AMD_PG_STATE_GATE = 0, | |
76 | AMD_PG_STATE_UNGATE, | |
77 | }; | |
78 | ||
79 | struct amd_vce_state { | |
80 | /* vce clocks */ | |
81 | u32 evclk; | |
82 | u32 ecclk; | |
83 | /* gpu clocks */ | |
84 | u32 sclk; | |
85 | u32 mclk; | |
86 | u8 clk_idx; | |
87 | u8 pstate; | |
88 | }; | |
89 | ||
90 | ||
91 | #define AMD_MAX_VCE_LEVELS 6 | |
92 | ||
93 | enum amd_vce_level { | |
94 | AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ | |
95 | AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ | |
96 | AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ | |
97 | AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ | |
98 | AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ | |
99 | AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ | |
100 | }; | |
101 | ||
102 | enum amd_pp_profile_type { | |
103 | AMD_PP_GFX_PROFILE, | |
104 | AMD_PP_COMPUTE_PROFILE, | |
105 | }; | |
106 | ||
107 | struct amd_pp_profile { | |
108 | enum amd_pp_profile_type type; | |
109 | uint32_t min_sclk; | |
110 | uint32_t min_mclk; | |
111 | uint16_t activity_threshold; | |
112 | uint8_t up_hyst; | |
113 | uint8_t down_hyst; | |
114 | }; | |
115 | ||
116 | enum amd_fan_ctrl_mode { | |
117 | AMD_FAN_CTRL_NONE = 0, | |
118 | AMD_FAN_CTRL_MANUAL = 1, | |
119 | AMD_FAN_CTRL_AUTO = 2, | |
120 | }; | |
121 | ||
122 | /* CG flags */ | |
123 | #define AMD_CG_SUPPORT_GFX_MGCG (1 << 0) | |
124 | #define AMD_CG_SUPPORT_GFX_MGLS (1 << 1) | |
125 | #define AMD_CG_SUPPORT_GFX_CGCG (1 << 2) | |
126 | #define AMD_CG_SUPPORT_GFX_CGLS (1 << 3) | |
127 | #define AMD_CG_SUPPORT_GFX_CGTS (1 << 4) | |
128 | #define AMD_CG_SUPPORT_GFX_CGTS_LS (1 << 5) | |
129 | #define AMD_CG_SUPPORT_GFX_CP_LS (1 << 6) | |
130 | #define AMD_CG_SUPPORT_GFX_RLC_LS (1 << 7) | |
131 | #define AMD_CG_SUPPORT_MC_LS (1 << 8) | |
132 | #define AMD_CG_SUPPORT_MC_MGCG (1 << 9) | |
133 | #define AMD_CG_SUPPORT_SDMA_LS (1 << 10) | |
134 | #define AMD_CG_SUPPORT_SDMA_MGCG (1 << 11) | |
135 | #define AMD_CG_SUPPORT_BIF_LS (1 << 12) | |
136 | #define AMD_CG_SUPPORT_UVD_MGCG (1 << 13) | |
137 | #define AMD_CG_SUPPORT_VCE_MGCG (1 << 14) | |
138 | #define AMD_CG_SUPPORT_HDP_LS (1 << 15) | |
139 | #define AMD_CG_SUPPORT_HDP_MGCG (1 << 16) | |
140 | #define AMD_CG_SUPPORT_ROM_MGCG (1 << 17) | |
141 | #define AMD_CG_SUPPORT_DRM_LS (1 << 18) | |
142 | #define AMD_CG_SUPPORT_BIF_MGCG (1 << 19) | |
143 | #define AMD_CG_SUPPORT_GFX_3D_CGCG (1 << 20) | |
144 | #define AMD_CG_SUPPORT_GFX_3D_CGLS (1 << 21) | |
145 | #define AMD_CG_SUPPORT_DRM_MGCG (1 << 22) | |
146 | #define AMD_CG_SUPPORT_DF_MGCG (1 << 23) | |
147 | ||
148 | /* PG flags */ | |
149 | #define AMD_PG_SUPPORT_GFX_PG (1 << 0) | |
150 | #define AMD_PG_SUPPORT_GFX_SMG (1 << 1) | |
151 | #define AMD_PG_SUPPORT_GFX_DMG (1 << 2) | |
152 | #define AMD_PG_SUPPORT_UVD (1 << 3) | |
153 | #define AMD_PG_SUPPORT_VCE (1 << 4) | |
154 | #define AMD_PG_SUPPORT_CP (1 << 5) | |
155 | #define AMD_PG_SUPPORT_GDS (1 << 6) | |
156 | #define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7) | |
157 | #define AMD_PG_SUPPORT_SDMA (1 << 8) | |
158 | #define AMD_PG_SUPPORT_ACP (1 << 9) | |
159 | #define AMD_PG_SUPPORT_SAMU (1 << 10) | |
160 | #define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11) | |
161 | #define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12) | |
162 | #define AMD_PG_SUPPORT_MMHUB (1 << 13) | |
163 | ||
164 | enum amd_pm_state_type { | |
165 | /* not used for dpm */ | |
166 | POWER_STATE_TYPE_DEFAULT, | |
167 | POWER_STATE_TYPE_POWERSAVE, | |
168 | /* user selectable states */ | |
169 | POWER_STATE_TYPE_BATTERY, | |
170 | POWER_STATE_TYPE_BALANCED, | |
171 | POWER_STATE_TYPE_PERFORMANCE, | |
172 | /* internal states */ | |
173 | POWER_STATE_TYPE_INTERNAL_UVD, | |
174 | POWER_STATE_TYPE_INTERNAL_UVD_SD, | |
175 | POWER_STATE_TYPE_INTERNAL_UVD_HD, | |
176 | POWER_STATE_TYPE_INTERNAL_UVD_HD2, | |
177 | POWER_STATE_TYPE_INTERNAL_UVD_MVC, | |
178 | POWER_STATE_TYPE_INTERNAL_BOOT, | |
179 | POWER_STATE_TYPE_INTERNAL_THERMAL, | |
180 | POWER_STATE_TYPE_INTERNAL_ACPI, | |
181 | POWER_STATE_TYPE_INTERNAL_ULV, | |
182 | POWER_STATE_TYPE_INTERNAL_3DPERF, | |
183 | }; | |
184 | ||
185 | struct amd_ip_funcs { | |
186 | /* Name of IP block */ | |
187 | char *name; | |
188 | /* sets up early driver state (pre sw_init), does not configure hw - Optional */ | |
189 | int (*early_init)(void *handle); | |
190 | /* sets up late driver/hw state (post hw_init) - Optional */ | |
191 | int (*late_init)(void *handle); | |
192 | /* sets up driver state, does not configure hw */ | |
193 | int (*sw_init)(void *handle); | |
194 | /* tears down driver state, does not configure hw */ | |
195 | int (*sw_fini)(void *handle); | |
196 | /* sets up the hw state */ | |
197 | int (*hw_init)(void *handle); | |
198 | /* tears down the hw state */ | |
199 | int (*hw_fini)(void *handle); | |
200 | void (*late_fini)(void *handle); | |
201 | /* handles IP specific hw/sw changes for suspend */ | |
202 | int (*suspend)(void *handle); | |
203 | /* handles IP specific hw/sw changes for resume */ | |
204 | int (*resume)(void *handle); | |
205 | /* returns current IP block idle status */ | |
206 | bool (*is_idle)(void *handle); | |
207 | /* poll for idle */ | |
208 | int (*wait_for_idle)(void *handle); | |
209 | /* check soft reset the IP block */ | |
210 | bool (*check_soft_reset)(void *handle); | |
211 | /* pre soft reset the IP block */ | |
212 | int (*pre_soft_reset)(void *handle); | |
213 | /* soft reset the IP block */ | |
214 | int (*soft_reset)(void *handle); | |
215 | /* post soft reset the IP block */ | |
216 | int (*post_soft_reset)(void *handle); | |
217 | /* enable/disable cg for the IP block */ | |
218 | int (*set_clockgating_state)(void *handle, | |
219 | enum amd_clockgating_state state); | |
220 | /* enable/disable pg for the IP block */ | |
221 | int (*set_powergating_state)(void *handle, | |
222 | enum amd_powergating_state state); | |
223 | /* get current clockgating status */ | |
224 | void (*get_clockgating_state)(void *handle, u32 *flags); | |
225 | }; | |
226 | ||
227 | #endif /* __AMD_SHARED_H__ */ |