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drm/i915: Introduce i915_gem_active for request tracking
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / i915_debugfs.c
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1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
30#include <linux/circ_buf.h>
31#include <linux/ctype.h>
32#include <linux/debugfs.h>
33#include <linux/slab.h>
34#include <linux/export.h>
35#include <linux/list_sort.h>
36#include <asm/msr-index.h>
37#include <drm/drmP.h>
38#include "intel_drv.h"
39#include "intel_ringbuffer.h"
40#include <drm/i915_drm.h>
41#include "i915_drv.h"
42
43enum {
44 ACTIVE_LIST,
45 INACTIVE_LIST,
46 PINNED_LIST,
47};
48
49/* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
51static int
52drm_add_fake_info_node(struct drm_minor *minor,
53 struct dentry *ent,
54 const void *key)
55{
56 struct drm_info_node *node;
57
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
59 if (node == NULL) {
60 debugfs_remove(ent);
61 return -ENOMEM;
62 }
63
64 node->minor = minor;
65 node->dent = ent;
66 node->info_ent = (void *) key;
67
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
71
72 return 0;
73}
74
75static int i915_capabilities(struct seq_file *m, void *data)
76{
77 struct drm_info_node *node = m->private;
78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
80
81 seq_printf(m, "gen: %d\n", info->gen);
82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
83#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84#define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
86#undef PRINT_FLAG
87#undef SEP_SEMICOLON
88
89 return 0;
90}
91
92static char get_active_flag(struct drm_i915_gem_object *obj)
93{
94 return obj->active ? '*' : ' ';
95}
96
97static char get_pin_flag(struct drm_i915_gem_object *obj)
98{
99 return obj->pin_display ? 'p' : ' ';
100}
101
102static char get_tiling_flag(struct drm_i915_gem_object *obj)
103{
104 switch (obj->tiling_mode) {
105 default:
106 case I915_TILING_NONE: return ' ';
107 case I915_TILING_X: return 'X';
108 case I915_TILING_Y: return 'Y';
109 }
110}
111
112static char get_global_flag(struct drm_i915_gem_object *obj)
113{
114 return i915_gem_obj_to_ggtt(obj) ? 'g' : ' ';
115}
116
117static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
118{
119 return obj->mapping ? 'M' : ' ';
120}
121
122static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
123{
124 u64 size = 0;
125 struct i915_vma *vma;
126
127 list_for_each_entry(vma, &obj->vma_list, obj_link) {
128 if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
129 size += vma->node.size;
130 }
131
132 return size;
133}
134
135static void
136describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
137{
138 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
139 struct intel_engine_cs *engine;
140 struct i915_vma *vma;
141 int pin_count = 0;
142 enum intel_engine_id id;
143
144 lockdep_assert_held(&obj->base.dev->struct_mutex);
145
146 seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
147 &obj->base,
148 get_active_flag(obj),
149 get_pin_flag(obj),
150 get_tiling_flag(obj),
151 get_global_flag(obj),
152 get_pin_mapped_flag(obj),
153 obj->base.size / 1024,
154 obj->base.read_domains,
155 obj->base.write_domain);
156 for_each_engine_id(engine, dev_priv, id)
157 seq_printf(m, "%x ",
158 i915_gem_request_get_seqno(obj->last_read[id].request));
159 seq_printf(m, "] %x %x%s%s%s",
160 i915_gem_request_get_seqno(obj->last_write.request),
161 i915_gem_request_get_seqno(obj->last_fence.request),
162 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
163 obj->dirty ? " dirty" : "",
164 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
165 if (obj->base.name)
166 seq_printf(m, " (name: %d)", obj->base.name);
167 list_for_each_entry(vma, &obj->vma_list, obj_link) {
168 if (vma->pin_count > 0)
169 pin_count++;
170 }
171 seq_printf(m, " (pinned x %d)", pin_count);
172 if (obj->pin_display)
173 seq_printf(m, " (display)");
174 if (obj->fence_reg != I915_FENCE_REG_NONE)
175 seq_printf(m, " (fence: %d)", obj->fence_reg);
176 list_for_each_entry(vma, &obj->vma_list, obj_link) {
177 if (!drm_mm_node_allocated(&vma->node))
178 continue;
179
180 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
181 vma->is_ggtt ? "g" : "pp",
182 vma->node.start, vma->node.size);
183 if (vma->is_ggtt)
184 seq_printf(m, ", type: %u", vma->ggtt_view.type);
185 seq_puts(m, ")");
186 }
187 if (obj->stolen)
188 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
189 if (obj->pin_display || obj->fault_mappable) {
190 char s[3], *t = s;
191 if (obj->pin_display)
192 *t++ = 'p';
193 if (obj->fault_mappable)
194 *t++ = 'f';
195 *t = '\0';
196 seq_printf(m, " (%s mappable)", s);
197 }
198 if (obj->last_write.request)
199 seq_printf(m, " (%s)", obj->last_write.request->engine->name);
200 if (obj->frontbuffer_bits)
201 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
202}
203
204static int i915_gem_object_list_info(struct seq_file *m, void *data)
205{
206 struct drm_info_node *node = m->private;
207 uintptr_t list = (uintptr_t) node->info_ent->data;
208 struct list_head *head;
209 struct drm_device *dev = node->minor->dev;
210 struct drm_i915_private *dev_priv = to_i915(dev);
211 struct i915_ggtt *ggtt = &dev_priv->ggtt;
212 struct i915_vma *vma;
213 u64 total_obj_size, total_gtt_size;
214 int count, ret;
215
216 ret = mutex_lock_interruptible(&dev->struct_mutex);
217 if (ret)
218 return ret;
219
220 /* FIXME: the user of this interface might want more than just GGTT */
221 switch (list) {
222 case ACTIVE_LIST:
223 seq_puts(m, "Active:\n");
224 head = &ggtt->base.active_list;
225 break;
226 case INACTIVE_LIST:
227 seq_puts(m, "Inactive:\n");
228 head = &ggtt->base.inactive_list;
229 break;
230 default:
231 mutex_unlock(&dev->struct_mutex);
232 return -EINVAL;
233 }
234
235 total_obj_size = total_gtt_size = count = 0;
236 list_for_each_entry(vma, head, vm_link) {
237 seq_printf(m, " ");
238 describe_obj(m, vma->obj);
239 seq_printf(m, "\n");
240 total_obj_size += vma->obj->base.size;
241 total_gtt_size += vma->node.size;
242 count++;
243 }
244 mutex_unlock(&dev->struct_mutex);
245
246 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
247 count, total_obj_size, total_gtt_size);
248 return 0;
249}
250
251static int obj_rank_by_stolen(void *priv,
252 struct list_head *A, struct list_head *B)
253{
254 struct drm_i915_gem_object *a =
255 container_of(A, struct drm_i915_gem_object, obj_exec_link);
256 struct drm_i915_gem_object *b =
257 container_of(B, struct drm_i915_gem_object, obj_exec_link);
258
259 if (a->stolen->start < b->stolen->start)
260 return -1;
261 if (a->stolen->start > b->stolen->start)
262 return 1;
263 return 0;
264}
265
266static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
267{
268 struct drm_info_node *node = m->private;
269 struct drm_device *dev = node->minor->dev;
270 struct drm_i915_private *dev_priv = to_i915(dev);
271 struct drm_i915_gem_object *obj;
272 u64 total_obj_size, total_gtt_size;
273 LIST_HEAD(stolen);
274 int count, ret;
275
276 ret = mutex_lock_interruptible(&dev->struct_mutex);
277 if (ret)
278 return ret;
279
280 total_obj_size = total_gtt_size = count = 0;
281 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
282 if (obj->stolen == NULL)
283 continue;
284
285 list_add(&obj->obj_exec_link, &stolen);
286
287 total_obj_size += obj->base.size;
288 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
289 count++;
290 }
291 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
292 if (obj->stolen == NULL)
293 continue;
294
295 list_add(&obj->obj_exec_link, &stolen);
296
297 total_obj_size += obj->base.size;
298 count++;
299 }
300 list_sort(NULL, &stolen, obj_rank_by_stolen);
301 seq_puts(m, "Stolen:\n");
302 while (!list_empty(&stolen)) {
303 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
304 seq_puts(m, " ");
305 describe_obj(m, obj);
306 seq_putc(m, '\n');
307 list_del_init(&obj->obj_exec_link);
308 }
309 mutex_unlock(&dev->struct_mutex);
310
311 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
312 count, total_obj_size, total_gtt_size);
313 return 0;
314}
315
316#define count_objects(list, member) do { \
317 list_for_each_entry(obj, list, member) { \
318 size += i915_gem_obj_total_ggtt_size(obj); \
319 ++count; \
320 if (obj->map_and_fenceable) { \
321 mappable_size += i915_gem_obj_ggtt_size(obj); \
322 ++mappable_count; \
323 } \
324 } \
325} while (0)
326
327struct file_stats {
328 struct drm_i915_file_private *file_priv;
329 unsigned long count;
330 u64 total, unbound;
331 u64 global, shared;
332 u64 active, inactive;
333};
334
335static int per_file_stats(int id, void *ptr, void *data)
336{
337 struct drm_i915_gem_object *obj = ptr;
338 struct file_stats *stats = data;
339 struct i915_vma *vma;
340
341 stats->count++;
342 stats->total += obj->base.size;
343 if (!obj->bind_count)
344 stats->unbound += obj->base.size;
345 if (obj->base.name || obj->base.dma_buf)
346 stats->shared += obj->base.size;
347
348 list_for_each_entry(vma, &obj->vma_list, obj_link) {
349 if (!drm_mm_node_allocated(&vma->node))
350 continue;
351
352 if (vma->is_ggtt) {
353 stats->global += vma->node.size;
354 } else {
355 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
356
357 if (ppgtt->base.file != stats->file_priv)
358 continue;
359 }
360
361 if (obj->active) /* XXX per-vma statistic */
362 stats->active += vma->node.size;
363 else
364 stats->inactive += vma->node.size;
365 }
366
367 return 0;
368}
369
370#define print_file_stats(m, name, stats) do { \
371 if (stats.count) \
372 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
373 name, \
374 stats.count, \
375 stats.total, \
376 stats.active, \
377 stats.inactive, \
378 stats.global, \
379 stats.shared, \
380 stats.unbound); \
381} while (0)
382
383static void print_batch_pool_stats(struct seq_file *m,
384 struct drm_i915_private *dev_priv)
385{
386 struct drm_i915_gem_object *obj;
387 struct file_stats stats;
388 struct intel_engine_cs *engine;
389 int j;
390
391 memset(&stats, 0, sizeof(stats));
392
393 for_each_engine(engine, dev_priv) {
394 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
395 list_for_each_entry(obj,
396 &engine->batch_pool.cache_list[j],
397 batch_pool_link)
398 per_file_stats(0, obj, &stats);
399 }
400 }
401
402 print_file_stats(m, "[k]batch pool", stats);
403}
404
405static int per_file_ctx_stats(int id, void *ptr, void *data)
406{
407 struct i915_gem_context *ctx = ptr;
408 int n;
409
410 for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
411 if (ctx->engine[n].state)
412 per_file_stats(0, ctx->engine[n].state, data);
413 if (ctx->engine[n].ring)
414 per_file_stats(0, ctx->engine[n].ring->obj, data);
415 }
416
417 return 0;
418}
419
420static void print_context_stats(struct seq_file *m,
421 struct drm_i915_private *dev_priv)
422{
423 struct file_stats stats;
424 struct drm_file *file;
425
426 memset(&stats, 0, sizeof(stats));
427
428 mutex_lock(&dev_priv->drm.struct_mutex);
429 if (dev_priv->kernel_context)
430 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
431
432 list_for_each_entry(file, &dev_priv->drm.filelist, lhead) {
433 struct drm_i915_file_private *fpriv = file->driver_priv;
434 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
435 }
436 mutex_unlock(&dev_priv->drm.struct_mutex);
437
438 print_file_stats(m, "[k]contexts", stats);
439}
440
441#define count_vmas(list, member) do { \
442 list_for_each_entry(vma, list, member) { \
443 size += i915_gem_obj_total_ggtt_size(vma->obj); \
444 ++count; \
445 if (vma->obj->map_and_fenceable) { \
446 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
447 ++mappable_count; \
448 } \
449 } \
450} while (0)
451
452static int i915_gem_object_info(struct seq_file *m, void* data)
453{
454 struct drm_info_node *node = m->private;
455 struct drm_device *dev = node->minor->dev;
456 struct drm_i915_private *dev_priv = to_i915(dev);
457 struct i915_ggtt *ggtt = &dev_priv->ggtt;
458 u32 count, mappable_count, purgeable_count;
459 u64 size, mappable_size, purgeable_size;
460 unsigned long pin_mapped_count = 0, pin_mapped_purgeable_count = 0;
461 u64 pin_mapped_size = 0, pin_mapped_purgeable_size = 0;
462 struct drm_i915_gem_object *obj;
463 struct drm_file *file;
464 struct i915_vma *vma;
465 int ret;
466
467 ret = mutex_lock_interruptible(&dev->struct_mutex);
468 if (ret)
469 return ret;
470
471 seq_printf(m, "%u objects, %zu bytes\n",
472 dev_priv->mm.object_count,
473 dev_priv->mm.object_memory);
474
475 size = count = mappable_size = mappable_count = 0;
476 count_objects(&dev_priv->mm.bound_list, global_list);
477 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
478 count, mappable_count, size, mappable_size);
479
480 size = count = mappable_size = mappable_count = 0;
481 count_vmas(&ggtt->base.active_list, vm_link);
482 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
483 count, mappable_count, size, mappable_size);
484
485 size = count = mappable_size = mappable_count = 0;
486 count_vmas(&ggtt->base.inactive_list, vm_link);
487 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
488 count, mappable_count, size, mappable_size);
489
490 size = count = purgeable_size = purgeable_count = 0;
491 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
492 size += obj->base.size, ++count;
493 if (obj->madv == I915_MADV_DONTNEED)
494 purgeable_size += obj->base.size, ++purgeable_count;
495 if (obj->mapping) {
496 pin_mapped_count++;
497 pin_mapped_size += obj->base.size;
498 if (obj->pages_pin_count == 0) {
499 pin_mapped_purgeable_count++;
500 pin_mapped_purgeable_size += obj->base.size;
501 }
502 }
503 }
504 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
505
506 size = count = mappable_size = mappable_count = 0;
507 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
508 if (obj->fault_mappable) {
509 size += i915_gem_obj_ggtt_size(obj);
510 ++count;
511 }
512 if (obj->pin_display) {
513 mappable_size += i915_gem_obj_ggtt_size(obj);
514 ++mappable_count;
515 }
516 if (obj->madv == I915_MADV_DONTNEED) {
517 purgeable_size += obj->base.size;
518 ++purgeable_count;
519 }
520 if (obj->mapping) {
521 pin_mapped_count++;
522 pin_mapped_size += obj->base.size;
523 if (obj->pages_pin_count == 0) {
524 pin_mapped_purgeable_count++;
525 pin_mapped_purgeable_size += obj->base.size;
526 }
527 }
528 }
529 seq_printf(m, "%u purgeable objects, %llu bytes\n",
530 purgeable_count, purgeable_size);
531 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
532 mappable_count, mappable_size);
533 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
534 count, size);
535 seq_printf(m,
536 "%lu [%lu] pin mapped objects, %llu [%llu] bytes [purgeable]\n",
537 pin_mapped_count, pin_mapped_purgeable_count,
538 pin_mapped_size, pin_mapped_purgeable_size);
539
540 seq_printf(m, "%llu [%llu] gtt total\n",
541 ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
542
543 seq_putc(m, '\n');
544 print_batch_pool_stats(m, dev_priv);
545 mutex_unlock(&dev->struct_mutex);
546
547 mutex_lock(&dev->filelist_mutex);
548 print_context_stats(m, dev_priv);
549 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
550 struct file_stats stats;
551 struct task_struct *task;
552
553 memset(&stats, 0, sizeof(stats));
554 stats.file_priv = file->driver_priv;
555 spin_lock(&file->table_lock);
556 idr_for_each(&file->object_idr, per_file_stats, &stats);
557 spin_unlock(&file->table_lock);
558 /*
559 * Although we have a valid reference on file->pid, that does
560 * not guarantee that the task_struct who called get_pid() is
561 * still alive (e.g. get_pid(current) => fork() => exit()).
562 * Therefore, we need to protect this ->comm access using RCU.
563 */
564 rcu_read_lock();
565 task = pid_task(file->pid, PIDTYPE_PID);
566 print_file_stats(m, task ? task->comm : "<unknown>", stats);
567 rcu_read_unlock();
568 }
569 mutex_unlock(&dev->filelist_mutex);
570
571 return 0;
572}
573
574static int i915_gem_gtt_info(struct seq_file *m, void *data)
575{
576 struct drm_info_node *node = m->private;
577 struct drm_device *dev = node->minor->dev;
578 uintptr_t list = (uintptr_t) node->info_ent->data;
579 struct drm_i915_private *dev_priv = to_i915(dev);
580 struct drm_i915_gem_object *obj;
581 u64 total_obj_size, total_gtt_size;
582 int count, ret;
583
584 ret = mutex_lock_interruptible(&dev->struct_mutex);
585 if (ret)
586 return ret;
587
588 total_obj_size = total_gtt_size = count = 0;
589 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
590 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
591 continue;
592
593 seq_puts(m, " ");
594 describe_obj(m, obj);
595 seq_putc(m, '\n');
596 total_obj_size += obj->base.size;
597 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
598 count++;
599 }
600
601 mutex_unlock(&dev->struct_mutex);
602
603 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
604 count, total_obj_size, total_gtt_size);
605
606 return 0;
607}
608
609static int i915_gem_pageflip_info(struct seq_file *m, void *data)
610{
611 struct drm_info_node *node = m->private;
612 struct drm_device *dev = node->minor->dev;
613 struct drm_i915_private *dev_priv = to_i915(dev);
614 struct intel_crtc *crtc;
615 int ret;
616
617 ret = mutex_lock_interruptible(&dev->struct_mutex);
618 if (ret)
619 return ret;
620
621 for_each_intel_crtc(dev, crtc) {
622 const char pipe = pipe_name(crtc->pipe);
623 const char plane = plane_name(crtc->plane);
624 struct intel_flip_work *work;
625
626 spin_lock_irq(&dev->event_lock);
627 work = crtc->flip_work;
628 if (work == NULL) {
629 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
630 pipe, plane);
631 } else {
632 u32 pending;
633 u32 addr;
634
635 pending = atomic_read(&work->pending);
636 if (pending) {
637 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
638 pipe, plane);
639 } else {
640 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
641 pipe, plane);
642 }
643 if (work->flip_queued_req) {
644 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
645
646 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
647 engine->name,
648 i915_gem_request_get_seqno(work->flip_queued_req),
649 dev_priv->next_seqno,
650 intel_engine_get_seqno(engine),
651 i915_gem_request_completed(work->flip_queued_req));
652 } else
653 seq_printf(m, "Flip not associated with any ring\n");
654 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
655 work->flip_queued_vblank,
656 work->flip_ready_vblank,
657 intel_crtc_get_vblank_counter(crtc));
658 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
659
660 if (INTEL_INFO(dev)->gen >= 4)
661 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
662 else
663 addr = I915_READ(DSPADDR(crtc->plane));
664 seq_printf(m, "Current scanout address 0x%08x\n", addr);
665
666 if (work->pending_flip_obj) {
667 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
668 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
669 }
670 }
671 spin_unlock_irq(&dev->event_lock);
672 }
673
674 mutex_unlock(&dev->struct_mutex);
675
676 return 0;
677}
678
679static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
680{
681 struct drm_info_node *node = m->private;
682 struct drm_device *dev = node->minor->dev;
683 struct drm_i915_private *dev_priv = to_i915(dev);
684 struct drm_i915_gem_object *obj;
685 struct intel_engine_cs *engine;
686 int total = 0;
687 int ret, j;
688
689 ret = mutex_lock_interruptible(&dev->struct_mutex);
690 if (ret)
691 return ret;
692
693 for_each_engine(engine, dev_priv) {
694 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
695 int count;
696
697 count = 0;
698 list_for_each_entry(obj,
699 &engine->batch_pool.cache_list[j],
700 batch_pool_link)
701 count++;
702 seq_printf(m, "%s cache[%d]: %d objects\n",
703 engine->name, j, count);
704
705 list_for_each_entry(obj,
706 &engine->batch_pool.cache_list[j],
707 batch_pool_link) {
708 seq_puts(m, " ");
709 describe_obj(m, obj);
710 seq_putc(m, '\n');
711 }
712
713 total += count;
714 }
715 }
716
717 seq_printf(m, "total: %d\n", total);
718
719 mutex_unlock(&dev->struct_mutex);
720
721 return 0;
722}
723
724static int i915_gem_request_info(struct seq_file *m, void *data)
725{
726 struct drm_info_node *node = m->private;
727 struct drm_device *dev = node->minor->dev;
728 struct drm_i915_private *dev_priv = to_i915(dev);
729 struct intel_engine_cs *engine;
730 struct drm_i915_gem_request *req;
731 int ret, any;
732
733 ret = mutex_lock_interruptible(&dev->struct_mutex);
734 if (ret)
735 return ret;
736
737 any = 0;
738 for_each_engine(engine, dev_priv) {
739 int count;
740
741 count = 0;
742 list_for_each_entry(req, &engine->request_list, list)
743 count++;
744 if (count == 0)
745 continue;
746
747 seq_printf(m, "%s requests: %d\n", engine->name, count);
748 list_for_each_entry(req, &engine->request_list, list) {
749 struct task_struct *task;
750
751 rcu_read_lock();
752 task = NULL;
753 if (req->pid)
754 task = pid_task(req->pid, PIDTYPE_PID);
755 seq_printf(m, " %x @ %d: %s [%d]\n",
756 req->fence.seqno,
757 (int) (jiffies - req->emitted_jiffies),
758 task ? task->comm : "<unknown>",
759 task ? task->pid : -1);
760 rcu_read_unlock();
761 }
762
763 any++;
764 }
765 mutex_unlock(&dev->struct_mutex);
766
767 if (any == 0)
768 seq_puts(m, "No requests\n");
769
770 return 0;
771}
772
773static void i915_ring_seqno_info(struct seq_file *m,
774 struct intel_engine_cs *engine)
775{
776 struct intel_breadcrumbs *b = &engine->breadcrumbs;
777 struct rb_node *rb;
778
779 seq_printf(m, "Current sequence (%s): %x\n",
780 engine->name, intel_engine_get_seqno(engine));
781 seq_printf(m, "Current user interrupts (%s): %lx\n",
782 engine->name, READ_ONCE(engine->breadcrumbs.irq_wakeups));
783
784 spin_lock(&b->lock);
785 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
786 struct intel_wait *w = container_of(rb, typeof(*w), node);
787
788 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
789 engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
790 }
791 spin_unlock(&b->lock);
792}
793
794static int i915_gem_seqno_info(struct seq_file *m, void *data)
795{
796 struct drm_info_node *node = m->private;
797 struct drm_device *dev = node->minor->dev;
798 struct drm_i915_private *dev_priv = to_i915(dev);
799 struct intel_engine_cs *engine;
800 int ret;
801
802 ret = mutex_lock_interruptible(&dev->struct_mutex);
803 if (ret)
804 return ret;
805 intel_runtime_pm_get(dev_priv);
806
807 for_each_engine(engine, dev_priv)
808 i915_ring_seqno_info(m, engine);
809
810 intel_runtime_pm_put(dev_priv);
811 mutex_unlock(&dev->struct_mutex);
812
813 return 0;
814}
815
816
817static int i915_interrupt_info(struct seq_file *m, void *data)
818{
819 struct drm_info_node *node = m->private;
820 struct drm_device *dev = node->minor->dev;
821 struct drm_i915_private *dev_priv = to_i915(dev);
822 struct intel_engine_cs *engine;
823 int ret, i, pipe;
824
825 ret = mutex_lock_interruptible(&dev->struct_mutex);
826 if (ret)
827 return ret;
828 intel_runtime_pm_get(dev_priv);
829
830 if (IS_CHERRYVIEW(dev)) {
831 seq_printf(m, "Master Interrupt Control:\t%08x\n",
832 I915_READ(GEN8_MASTER_IRQ));
833
834 seq_printf(m, "Display IER:\t%08x\n",
835 I915_READ(VLV_IER));
836 seq_printf(m, "Display IIR:\t%08x\n",
837 I915_READ(VLV_IIR));
838 seq_printf(m, "Display IIR_RW:\t%08x\n",
839 I915_READ(VLV_IIR_RW));
840 seq_printf(m, "Display IMR:\t%08x\n",
841 I915_READ(VLV_IMR));
842 for_each_pipe(dev_priv, pipe)
843 seq_printf(m, "Pipe %c stat:\t%08x\n",
844 pipe_name(pipe),
845 I915_READ(PIPESTAT(pipe)));
846
847 seq_printf(m, "Port hotplug:\t%08x\n",
848 I915_READ(PORT_HOTPLUG_EN));
849 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
850 I915_READ(VLV_DPFLIPSTAT));
851 seq_printf(m, "DPINVGTT:\t%08x\n",
852 I915_READ(DPINVGTT));
853
854 for (i = 0; i < 4; i++) {
855 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
856 i, I915_READ(GEN8_GT_IMR(i)));
857 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
858 i, I915_READ(GEN8_GT_IIR(i)));
859 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
860 i, I915_READ(GEN8_GT_IER(i)));
861 }
862
863 seq_printf(m, "PCU interrupt mask:\t%08x\n",
864 I915_READ(GEN8_PCU_IMR));
865 seq_printf(m, "PCU interrupt identity:\t%08x\n",
866 I915_READ(GEN8_PCU_IIR));
867 seq_printf(m, "PCU interrupt enable:\t%08x\n",
868 I915_READ(GEN8_PCU_IER));
869 } else if (INTEL_INFO(dev)->gen >= 8) {
870 seq_printf(m, "Master Interrupt Control:\t%08x\n",
871 I915_READ(GEN8_MASTER_IRQ));
872
873 for (i = 0; i < 4; i++) {
874 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
875 i, I915_READ(GEN8_GT_IMR(i)));
876 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
877 i, I915_READ(GEN8_GT_IIR(i)));
878 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
879 i, I915_READ(GEN8_GT_IER(i)));
880 }
881
882 for_each_pipe(dev_priv, pipe) {
883 enum intel_display_power_domain power_domain;
884
885 power_domain = POWER_DOMAIN_PIPE(pipe);
886 if (!intel_display_power_get_if_enabled(dev_priv,
887 power_domain)) {
888 seq_printf(m, "Pipe %c power disabled\n",
889 pipe_name(pipe));
890 continue;
891 }
892 seq_printf(m, "Pipe %c IMR:\t%08x\n",
893 pipe_name(pipe),
894 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
895 seq_printf(m, "Pipe %c IIR:\t%08x\n",
896 pipe_name(pipe),
897 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
898 seq_printf(m, "Pipe %c IER:\t%08x\n",
899 pipe_name(pipe),
900 I915_READ(GEN8_DE_PIPE_IER(pipe)));
901
902 intel_display_power_put(dev_priv, power_domain);
903 }
904
905 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
906 I915_READ(GEN8_DE_PORT_IMR));
907 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
908 I915_READ(GEN8_DE_PORT_IIR));
909 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
910 I915_READ(GEN8_DE_PORT_IER));
911
912 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
913 I915_READ(GEN8_DE_MISC_IMR));
914 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
915 I915_READ(GEN8_DE_MISC_IIR));
916 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
917 I915_READ(GEN8_DE_MISC_IER));
918
919 seq_printf(m, "PCU interrupt mask:\t%08x\n",
920 I915_READ(GEN8_PCU_IMR));
921 seq_printf(m, "PCU interrupt identity:\t%08x\n",
922 I915_READ(GEN8_PCU_IIR));
923 seq_printf(m, "PCU interrupt enable:\t%08x\n",
924 I915_READ(GEN8_PCU_IER));
925 } else if (IS_VALLEYVIEW(dev)) {
926 seq_printf(m, "Display IER:\t%08x\n",
927 I915_READ(VLV_IER));
928 seq_printf(m, "Display IIR:\t%08x\n",
929 I915_READ(VLV_IIR));
930 seq_printf(m, "Display IIR_RW:\t%08x\n",
931 I915_READ(VLV_IIR_RW));
932 seq_printf(m, "Display IMR:\t%08x\n",
933 I915_READ(VLV_IMR));
934 for_each_pipe(dev_priv, pipe)
935 seq_printf(m, "Pipe %c stat:\t%08x\n",
936 pipe_name(pipe),
937 I915_READ(PIPESTAT(pipe)));
938
939 seq_printf(m, "Master IER:\t%08x\n",
940 I915_READ(VLV_MASTER_IER));
941
942 seq_printf(m, "Render IER:\t%08x\n",
943 I915_READ(GTIER));
944 seq_printf(m, "Render IIR:\t%08x\n",
945 I915_READ(GTIIR));
946 seq_printf(m, "Render IMR:\t%08x\n",
947 I915_READ(GTIMR));
948
949 seq_printf(m, "PM IER:\t\t%08x\n",
950 I915_READ(GEN6_PMIER));
951 seq_printf(m, "PM IIR:\t\t%08x\n",
952 I915_READ(GEN6_PMIIR));
953 seq_printf(m, "PM IMR:\t\t%08x\n",
954 I915_READ(GEN6_PMIMR));
955
956 seq_printf(m, "Port hotplug:\t%08x\n",
957 I915_READ(PORT_HOTPLUG_EN));
958 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
959 I915_READ(VLV_DPFLIPSTAT));
960 seq_printf(m, "DPINVGTT:\t%08x\n",
961 I915_READ(DPINVGTT));
962
963 } else if (!HAS_PCH_SPLIT(dev)) {
964 seq_printf(m, "Interrupt enable: %08x\n",
965 I915_READ(IER));
966 seq_printf(m, "Interrupt identity: %08x\n",
967 I915_READ(IIR));
968 seq_printf(m, "Interrupt mask: %08x\n",
969 I915_READ(IMR));
970 for_each_pipe(dev_priv, pipe)
971 seq_printf(m, "Pipe %c stat: %08x\n",
972 pipe_name(pipe),
973 I915_READ(PIPESTAT(pipe)));
974 } else {
975 seq_printf(m, "North Display Interrupt enable: %08x\n",
976 I915_READ(DEIER));
977 seq_printf(m, "North Display Interrupt identity: %08x\n",
978 I915_READ(DEIIR));
979 seq_printf(m, "North Display Interrupt mask: %08x\n",
980 I915_READ(DEIMR));
981 seq_printf(m, "South Display Interrupt enable: %08x\n",
982 I915_READ(SDEIER));
983 seq_printf(m, "South Display Interrupt identity: %08x\n",
984 I915_READ(SDEIIR));
985 seq_printf(m, "South Display Interrupt mask: %08x\n",
986 I915_READ(SDEIMR));
987 seq_printf(m, "Graphics Interrupt enable: %08x\n",
988 I915_READ(GTIER));
989 seq_printf(m, "Graphics Interrupt identity: %08x\n",
990 I915_READ(GTIIR));
991 seq_printf(m, "Graphics Interrupt mask: %08x\n",
992 I915_READ(GTIMR));
993 }
994 for_each_engine(engine, dev_priv) {
995 if (INTEL_INFO(dev)->gen >= 6) {
996 seq_printf(m,
997 "Graphics Interrupt mask (%s): %08x\n",
998 engine->name, I915_READ_IMR(engine));
999 }
1000 i915_ring_seqno_info(m, engine);
1001 }
1002 intel_runtime_pm_put(dev_priv);
1003 mutex_unlock(&dev->struct_mutex);
1004
1005 return 0;
1006}
1007
1008static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
1009{
1010 struct drm_info_node *node = m->private;
1011 struct drm_device *dev = node->minor->dev;
1012 struct drm_i915_private *dev_priv = to_i915(dev);
1013 int i, ret;
1014
1015 ret = mutex_lock_interruptible(&dev->struct_mutex);
1016 if (ret)
1017 return ret;
1018
1019 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
1020 for (i = 0; i < dev_priv->num_fence_regs; i++) {
1021 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
1022
1023 seq_printf(m, "Fence %d, pin count = %d, object = ",
1024 i, dev_priv->fence_regs[i].pin_count);
1025 if (obj == NULL)
1026 seq_puts(m, "unused");
1027 else
1028 describe_obj(m, obj);
1029 seq_putc(m, '\n');
1030 }
1031
1032 mutex_unlock(&dev->struct_mutex);
1033 return 0;
1034}
1035
1036static int i915_hws_info(struct seq_file *m, void *data)
1037{
1038 struct drm_info_node *node = m->private;
1039 struct drm_device *dev = node->minor->dev;
1040 struct drm_i915_private *dev_priv = to_i915(dev);
1041 struct intel_engine_cs *engine;
1042 const u32 *hws;
1043 int i;
1044
1045 engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
1046 hws = engine->status_page.page_addr;
1047 if (hws == NULL)
1048 return 0;
1049
1050 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
1051 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1052 i * 4,
1053 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
1054 }
1055 return 0;
1056}
1057
1058static ssize_t
1059i915_error_state_write(struct file *filp,
1060 const char __user *ubuf,
1061 size_t cnt,
1062 loff_t *ppos)
1063{
1064 struct i915_error_state_file_priv *error_priv = filp->private_data;
1065 struct drm_device *dev = error_priv->dev;
1066 int ret;
1067
1068 DRM_DEBUG_DRIVER("Resetting error state\n");
1069
1070 ret = mutex_lock_interruptible(&dev->struct_mutex);
1071 if (ret)
1072 return ret;
1073
1074 i915_destroy_error_state(dev);
1075 mutex_unlock(&dev->struct_mutex);
1076
1077 return cnt;
1078}
1079
1080static int i915_error_state_open(struct inode *inode, struct file *file)
1081{
1082 struct drm_device *dev = inode->i_private;
1083 struct i915_error_state_file_priv *error_priv;
1084
1085 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1086 if (!error_priv)
1087 return -ENOMEM;
1088
1089 error_priv->dev = dev;
1090
1091 i915_error_state_get(dev, error_priv);
1092
1093 file->private_data = error_priv;
1094
1095 return 0;
1096}
1097
1098static int i915_error_state_release(struct inode *inode, struct file *file)
1099{
1100 struct i915_error_state_file_priv *error_priv = file->private_data;
1101
1102 i915_error_state_put(error_priv);
1103 kfree(error_priv);
1104
1105 return 0;
1106}
1107
1108static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1109 size_t count, loff_t *pos)
1110{
1111 struct i915_error_state_file_priv *error_priv = file->private_data;
1112 struct drm_i915_error_state_buf error_str;
1113 loff_t tmp_pos = 0;
1114 ssize_t ret_count = 0;
1115 int ret;
1116
1117 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1118 if (ret)
1119 return ret;
1120
1121 ret = i915_error_state_to_str(&error_str, error_priv);
1122 if (ret)
1123 goto out;
1124
1125 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1126 error_str.buf,
1127 error_str.bytes);
1128
1129 if (ret_count < 0)
1130 ret = ret_count;
1131 else
1132 *pos = error_str.start + ret_count;
1133out:
1134 i915_error_state_buf_release(&error_str);
1135 return ret ?: ret_count;
1136}
1137
1138static const struct file_operations i915_error_state_fops = {
1139 .owner = THIS_MODULE,
1140 .open = i915_error_state_open,
1141 .read = i915_error_state_read,
1142 .write = i915_error_state_write,
1143 .llseek = default_llseek,
1144 .release = i915_error_state_release,
1145};
1146
1147static int
1148i915_next_seqno_get(void *data, u64 *val)
1149{
1150 struct drm_device *dev = data;
1151 struct drm_i915_private *dev_priv = to_i915(dev);
1152 int ret;
1153
1154 ret = mutex_lock_interruptible(&dev->struct_mutex);
1155 if (ret)
1156 return ret;
1157
1158 *val = dev_priv->next_seqno;
1159 mutex_unlock(&dev->struct_mutex);
1160
1161 return 0;
1162}
1163
1164static int
1165i915_next_seqno_set(void *data, u64 val)
1166{
1167 struct drm_device *dev = data;
1168 int ret;
1169
1170 ret = mutex_lock_interruptible(&dev->struct_mutex);
1171 if (ret)
1172 return ret;
1173
1174 ret = i915_gem_set_seqno(dev, val);
1175 mutex_unlock(&dev->struct_mutex);
1176
1177 return ret;
1178}
1179
1180DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1181 i915_next_seqno_get, i915_next_seqno_set,
1182 "0x%llx\n");
1183
1184static int i915_frequency_info(struct seq_file *m, void *unused)
1185{
1186 struct drm_info_node *node = m->private;
1187 struct drm_device *dev = node->minor->dev;
1188 struct drm_i915_private *dev_priv = to_i915(dev);
1189 int ret = 0;
1190
1191 intel_runtime_pm_get(dev_priv);
1192
1193 if (IS_GEN5(dev)) {
1194 u16 rgvswctl = I915_READ16(MEMSWCTL);
1195 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1196
1197 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1198 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1199 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1200 MEMSTAT_VID_SHIFT);
1201 seq_printf(m, "Current P-state: %d\n",
1202 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1203 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1204 u32 freq_sts;
1205
1206 mutex_lock(&dev_priv->rps.hw_lock);
1207 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1208 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1209 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1210
1211 seq_printf(m, "actual GPU freq: %d MHz\n",
1212 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1213
1214 seq_printf(m, "current GPU freq: %d MHz\n",
1215 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1216
1217 seq_printf(m, "max GPU freq: %d MHz\n",
1218 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1219
1220 seq_printf(m, "min GPU freq: %d MHz\n",
1221 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1222
1223 seq_printf(m, "idle GPU freq: %d MHz\n",
1224 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1225
1226 seq_printf(m,
1227 "efficient (RPe) frequency: %d MHz\n",
1228 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1229 mutex_unlock(&dev_priv->rps.hw_lock);
1230 } else if (INTEL_INFO(dev)->gen >= 6) {
1231 u32 rp_state_limits;
1232 u32 gt_perf_status;
1233 u32 rp_state_cap;
1234 u32 rpmodectl, rpinclimit, rpdeclimit;
1235 u32 rpstat, cagf, reqf;
1236 u32 rpupei, rpcurup, rpprevup;
1237 u32 rpdownei, rpcurdown, rpprevdown;
1238 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1239 int max_freq;
1240
1241 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1242 if (IS_BROXTON(dev)) {
1243 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1244 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1245 } else {
1246 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1247 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1248 }
1249
1250 /* RPSTAT1 is in the GT power well */
1251 ret = mutex_lock_interruptible(&dev->struct_mutex);
1252 if (ret)
1253 goto out;
1254
1255 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1256
1257 reqf = I915_READ(GEN6_RPNSWREQ);
1258 if (IS_GEN9(dev))
1259 reqf >>= 23;
1260 else {
1261 reqf &= ~GEN6_TURBO_DISABLE;
1262 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1263 reqf >>= 24;
1264 else
1265 reqf >>= 25;
1266 }
1267 reqf = intel_gpu_freq(dev_priv, reqf);
1268
1269 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1270 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1271 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1272
1273 rpstat = I915_READ(GEN6_RPSTAT1);
1274 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1275 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1276 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1277 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1278 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1279 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1280 if (IS_GEN9(dev))
1281 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1282 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1283 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1284 else
1285 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1286 cagf = intel_gpu_freq(dev_priv, cagf);
1287
1288 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1289 mutex_unlock(&dev->struct_mutex);
1290
1291 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1292 pm_ier = I915_READ(GEN6_PMIER);
1293 pm_imr = I915_READ(GEN6_PMIMR);
1294 pm_isr = I915_READ(GEN6_PMISR);
1295 pm_iir = I915_READ(GEN6_PMIIR);
1296 pm_mask = I915_READ(GEN6_PMINTRMSK);
1297 } else {
1298 pm_ier = I915_READ(GEN8_GT_IER(2));
1299 pm_imr = I915_READ(GEN8_GT_IMR(2));
1300 pm_isr = I915_READ(GEN8_GT_ISR(2));
1301 pm_iir = I915_READ(GEN8_GT_IIR(2));
1302 pm_mask = I915_READ(GEN6_PMINTRMSK);
1303 }
1304 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1305 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1306 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1307 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1308 seq_printf(m, "Render p-state ratio: %d\n",
1309 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1310 seq_printf(m, "Render p-state VID: %d\n",
1311 gt_perf_status & 0xff);
1312 seq_printf(m, "Render p-state limit: %d\n",
1313 rp_state_limits & 0xff);
1314 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1315 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1316 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1317 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1318 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1319 seq_printf(m, "CAGF: %dMHz\n", cagf);
1320 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1321 rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1322 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1323 rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1324 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1325 rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1326 seq_printf(m, "Up threshold: %d%%\n",
1327 dev_priv->rps.up_threshold);
1328
1329 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1330 rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1331 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1332 rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1333 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1334 rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1335 seq_printf(m, "Down threshold: %d%%\n",
1336 dev_priv->rps.down_threshold);
1337
1338 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1339 rp_state_cap >> 16) & 0xff;
1340 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1341 GEN9_FREQ_SCALER : 1);
1342 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1343 intel_gpu_freq(dev_priv, max_freq));
1344
1345 max_freq = (rp_state_cap & 0xff00) >> 8;
1346 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1347 GEN9_FREQ_SCALER : 1);
1348 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1349 intel_gpu_freq(dev_priv, max_freq));
1350
1351 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1352 rp_state_cap >> 0) & 0xff;
1353 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1354 GEN9_FREQ_SCALER : 1);
1355 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1356 intel_gpu_freq(dev_priv, max_freq));
1357 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1358 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1359
1360 seq_printf(m, "Current freq: %d MHz\n",
1361 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1362 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1363 seq_printf(m, "Idle freq: %d MHz\n",
1364 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1365 seq_printf(m, "Min freq: %d MHz\n",
1366 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1367 seq_printf(m, "Boost freq: %d MHz\n",
1368 intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1369 seq_printf(m, "Max freq: %d MHz\n",
1370 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1371 seq_printf(m,
1372 "efficient (RPe) frequency: %d MHz\n",
1373 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1374 } else {
1375 seq_puts(m, "no P-state info available\n");
1376 }
1377
1378 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1379 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1380 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1381
1382out:
1383 intel_runtime_pm_put(dev_priv);
1384 return ret;
1385}
1386
1387static int i915_hangcheck_info(struct seq_file *m, void *unused)
1388{
1389 struct drm_info_node *node = m->private;
1390 struct drm_device *dev = node->minor->dev;
1391 struct drm_i915_private *dev_priv = to_i915(dev);
1392 struct intel_engine_cs *engine;
1393 u64 acthd[I915_NUM_ENGINES];
1394 u32 seqno[I915_NUM_ENGINES];
1395 u32 instdone[I915_NUM_INSTDONE_REG];
1396 enum intel_engine_id id;
1397 int j;
1398
1399 if (!i915.enable_hangcheck) {
1400 seq_printf(m, "Hangcheck disabled\n");
1401 return 0;
1402 }
1403
1404 intel_runtime_pm_get(dev_priv);
1405
1406 for_each_engine_id(engine, dev_priv, id) {
1407 acthd[id] = intel_engine_get_active_head(engine);
1408 seqno[id] = intel_engine_get_seqno(engine);
1409 }
1410
1411 i915_get_extra_instdone(dev_priv, instdone);
1412
1413 intel_runtime_pm_put(dev_priv);
1414
1415 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1416 seq_printf(m, "Hangcheck active, fires in %dms\n",
1417 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1418 jiffies));
1419 } else
1420 seq_printf(m, "Hangcheck inactive\n");
1421
1422 for_each_engine_id(engine, dev_priv, id) {
1423 seq_printf(m, "%s:\n", engine->name);
1424 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1425 engine->hangcheck.seqno,
1426 seqno[id],
1427 engine->last_submitted_seqno);
1428 seq_printf(m, "\twaiters? %d\n",
1429 intel_engine_has_waiter(engine));
1430 seq_printf(m, "\tuser interrupts = %lx [current %lx]\n",
1431 engine->hangcheck.user_interrupts,
1432 READ_ONCE(engine->breadcrumbs.irq_wakeups));
1433 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1434 (long long)engine->hangcheck.acthd,
1435 (long long)acthd[id]);
1436 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1437 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1438
1439 if (engine->id == RCS) {
1440 seq_puts(m, "\tinstdone read =");
1441
1442 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1443 seq_printf(m, " 0x%08x", instdone[j]);
1444
1445 seq_puts(m, "\n\tinstdone accu =");
1446
1447 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1448 seq_printf(m, " 0x%08x",
1449 engine->hangcheck.instdone[j]);
1450
1451 seq_puts(m, "\n");
1452 }
1453 }
1454
1455 return 0;
1456}
1457
1458static int ironlake_drpc_info(struct seq_file *m)
1459{
1460 struct drm_info_node *node = m->private;
1461 struct drm_device *dev = node->minor->dev;
1462 struct drm_i915_private *dev_priv = to_i915(dev);
1463 u32 rgvmodectl, rstdbyctl;
1464 u16 crstandvid;
1465 int ret;
1466
1467 ret = mutex_lock_interruptible(&dev->struct_mutex);
1468 if (ret)
1469 return ret;
1470 intel_runtime_pm_get(dev_priv);
1471
1472 rgvmodectl = I915_READ(MEMMODECTL);
1473 rstdbyctl = I915_READ(RSTDBYCTL);
1474 crstandvid = I915_READ16(CRSTANDVID);
1475
1476 intel_runtime_pm_put(dev_priv);
1477 mutex_unlock(&dev->struct_mutex);
1478
1479 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1480 seq_printf(m, "Boost freq: %d\n",
1481 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1482 MEMMODE_BOOST_FREQ_SHIFT);
1483 seq_printf(m, "HW control enabled: %s\n",
1484 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1485 seq_printf(m, "SW control enabled: %s\n",
1486 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1487 seq_printf(m, "Gated voltage change: %s\n",
1488 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1489 seq_printf(m, "Starting frequency: P%d\n",
1490 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1491 seq_printf(m, "Max P-state: P%d\n",
1492 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1493 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1494 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1495 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1496 seq_printf(m, "Render standby enabled: %s\n",
1497 yesno(!(rstdbyctl & RCX_SW_EXIT)));
1498 seq_puts(m, "Current RS state: ");
1499 switch (rstdbyctl & RSX_STATUS_MASK) {
1500 case RSX_STATUS_ON:
1501 seq_puts(m, "on\n");
1502 break;
1503 case RSX_STATUS_RC1:
1504 seq_puts(m, "RC1\n");
1505 break;
1506 case RSX_STATUS_RC1E:
1507 seq_puts(m, "RC1E\n");
1508 break;
1509 case RSX_STATUS_RS1:
1510 seq_puts(m, "RS1\n");
1511 break;
1512 case RSX_STATUS_RS2:
1513 seq_puts(m, "RS2 (RC6)\n");
1514 break;
1515 case RSX_STATUS_RS3:
1516 seq_puts(m, "RC3 (RC6+)\n");
1517 break;
1518 default:
1519 seq_puts(m, "unknown\n");
1520 break;
1521 }
1522
1523 return 0;
1524}
1525
1526static int i915_forcewake_domains(struct seq_file *m, void *data)
1527{
1528 struct drm_info_node *node = m->private;
1529 struct drm_device *dev = node->minor->dev;
1530 struct drm_i915_private *dev_priv = to_i915(dev);
1531 struct intel_uncore_forcewake_domain *fw_domain;
1532
1533 spin_lock_irq(&dev_priv->uncore.lock);
1534 for_each_fw_domain(fw_domain, dev_priv) {
1535 seq_printf(m, "%s.wake_count = %u\n",
1536 intel_uncore_forcewake_domain_to_str(fw_domain->id),
1537 fw_domain->wake_count);
1538 }
1539 spin_unlock_irq(&dev_priv->uncore.lock);
1540
1541 return 0;
1542}
1543
1544static int vlv_drpc_info(struct seq_file *m)
1545{
1546 struct drm_info_node *node = m->private;
1547 struct drm_device *dev = node->minor->dev;
1548 struct drm_i915_private *dev_priv = to_i915(dev);
1549 u32 rpmodectl1, rcctl1, pw_status;
1550
1551 intel_runtime_pm_get(dev_priv);
1552
1553 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1554 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1555 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1556
1557 intel_runtime_pm_put(dev_priv);
1558
1559 seq_printf(m, "Video Turbo Mode: %s\n",
1560 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1561 seq_printf(m, "Turbo enabled: %s\n",
1562 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1563 seq_printf(m, "HW control enabled: %s\n",
1564 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1565 seq_printf(m, "SW control enabled: %s\n",
1566 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1567 GEN6_RP_MEDIA_SW_MODE));
1568 seq_printf(m, "RC6 Enabled: %s\n",
1569 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1570 GEN6_RC_CTL_EI_MODE(1))));
1571 seq_printf(m, "Render Power Well: %s\n",
1572 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1573 seq_printf(m, "Media Power Well: %s\n",
1574 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1575
1576 seq_printf(m, "Render RC6 residency since boot: %u\n",
1577 I915_READ(VLV_GT_RENDER_RC6));
1578 seq_printf(m, "Media RC6 residency since boot: %u\n",
1579 I915_READ(VLV_GT_MEDIA_RC6));
1580
1581 return i915_forcewake_domains(m, NULL);
1582}
1583
1584static int gen6_drpc_info(struct seq_file *m)
1585{
1586 struct drm_info_node *node = m->private;
1587 struct drm_device *dev = node->minor->dev;
1588 struct drm_i915_private *dev_priv = to_i915(dev);
1589 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1590 u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1591 unsigned forcewake_count;
1592 int count = 0, ret;
1593
1594 ret = mutex_lock_interruptible(&dev->struct_mutex);
1595 if (ret)
1596 return ret;
1597 intel_runtime_pm_get(dev_priv);
1598
1599 spin_lock_irq(&dev_priv->uncore.lock);
1600 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1601 spin_unlock_irq(&dev_priv->uncore.lock);
1602
1603 if (forcewake_count) {
1604 seq_puts(m, "RC information inaccurate because somebody "
1605 "holds a forcewake reference \n");
1606 } else {
1607 /* NB: we cannot use forcewake, else we read the wrong values */
1608 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1609 udelay(10);
1610 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1611 }
1612
1613 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1614 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1615
1616 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1617 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1618 if (INTEL_INFO(dev)->gen >= 9) {
1619 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1620 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1621 }
1622 mutex_unlock(&dev->struct_mutex);
1623 mutex_lock(&dev_priv->rps.hw_lock);
1624 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1625 mutex_unlock(&dev_priv->rps.hw_lock);
1626
1627 intel_runtime_pm_put(dev_priv);
1628
1629 seq_printf(m, "Video Turbo Mode: %s\n",
1630 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1631 seq_printf(m, "HW control enabled: %s\n",
1632 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1633 seq_printf(m, "SW control enabled: %s\n",
1634 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1635 GEN6_RP_MEDIA_SW_MODE));
1636 seq_printf(m, "RC1e Enabled: %s\n",
1637 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1638 seq_printf(m, "RC6 Enabled: %s\n",
1639 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1640 if (INTEL_INFO(dev)->gen >= 9) {
1641 seq_printf(m, "Render Well Gating Enabled: %s\n",
1642 yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1643 seq_printf(m, "Media Well Gating Enabled: %s\n",
1644 yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1645 }
1646 seq_printf(m, "Deep RC6 Enabled: %s\n",
1647 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1648 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1649 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1650 seq_puts(m, "Current RC state: ");
1651 switch (gt_core_status & GEN6_RCn_MASK) {
1652 case GEN6_RC0:
1653 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1654 seq_puts(m, "Core Power Down\n");
1655 else
1656 seq_puts(m, "on\n");
1657 break;
1658 case GEN6_RC3:
1659 seq_puts(m, "RC3\n");
1660 break;
1661 case GEN6_RC6:
1662 seq_puts(m, "RC6\n");
1663 break;
1664 case GEN6_RC7:
1665 seq_puts(m, "RC7\n");
1666 break;
1667 default:
1668 seq_puts(m, "Unknown\n");
1669 break;
1670 }
1671
1672 seq_printf(m, "Core Power Down: %s\n",
1673 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1674 if (INTEL_INFO(dev)->gen >= 9) {
1675 seq_printf(m, "Render Power Well: %s\n",
1676 (gen9_powergate_status &
1677 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1678 seq_printf(m, "Media Power Well: %s\n",
1679 (gen9_powergate_status &
1680 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1681 }
1682
1683 /* Not exactly sure what this is */
1684 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1685 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1686 seq_printf(m, "RC6 residency since boot: %u\n",
1687 I915_READ(GEN6_GT_GFX_RC6));
1688 seq_printf(m, "RC6+ residency since boot: %u\n",
1689 I915_READ(GEN6_GT_GFX_RC6p));
1690 seq_printf(m, "RC6++ residency since boot: %u\n",
1691 I915_READ(GEN6_GT_GFX_RC6pp));
1692
1693 seq_printf(m, "RC6 voltage: %dmV\n",
1694 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1695 seq_printf(m, "RC6+ voltage: %dmV\n",
1696 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1697 seq_printf(m, "RC6++ voltage: %dmV\n",
1698 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1699 return i915_forcewake_domains(m, NULL);
1700}
1701
1702static int i915_drpc_info(struct seq_file *m, void *unused)
1703{
1704 struct drm_info_node *node = m->private;
1705 struct drm_device *dev = node->minor->dev;
1706
1707 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1708 return vlv_drpc_info(m);
1709 else if (INTEL_INFO(dev)->gen >= 6)
1710 return gen6_drpc_info(m);
1711 else
1712 return ironlake_drpc_info(m);
1713}
1714
1715static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1716{
1717 struct drm_info_node *node = m->private;
1718 struct drm_device *dev = node->minor->dev;
1719 struct drm_i915_private *dev_priv = to_i915(dev);
1720
1721 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1722 dev_priv->fb_tracking.busy_bits);
1723
1724 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1725 dev_priv->fb_tracking.flip_bits);
1726
1727 return 0;
1728}
1729
1730static int i915_fbc_status(struct seq_file *m, void *unused)
1731{
1732 struct drm_info_node *node = m->private;
1733 struct drm_device *dev = node->minor->dev;
1734 struct drm_i915_private *dev_priv = to_i915(dev);
1735
1736 if (!HAS_FBC(dev)) {
1737 seq_puts(m, "FBC unsupported on this chipset\n");
1738 return 0;
1739 }
1740
1741 intel_runtime_pm_get(dev_priv);
1742 mutex_lock(&dev_priv->fbc.lock);
1743
1744 if (intel_fbc_is_active(dev_priv))
1745 seq_puts(m, "FBC enabled\n");
1746 else
1747 seq_printf(m, "FBC disabled: %s\n",
1748 dev_priv->fbc.no_fbc_reason);
1749
1750 if (INTEL_INFO(dev_priv)->gen >= 7)
1751 seq_printf(m, "Compressing: %s\n",
1752 yesno(I915_READ(FBC_STATUS2) &
1753 FBC_COMPRESSION_MASK));
1754
1755 mutex_unlock(&dev_priv->fbc.lock);
1756 intel_runtime_pm_put(dev_priv);
1757
1758 return 0;
1759}
1760
1761static int i915_fbc_fc_get(void *data, u64 *val)
1762{
1763 struct drm_device *dev = data;
1764 struct drm_i915_private *dev_priv = to_i915(dev);
1765
1766 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1767 return -ENODEV;
1768
1769 *val = dev_priv->fbc.false_color;
1770
1771 return 0;
1772}
1773
1774static int i915_fbc_fc_set(void *data, u64 val)
1775{
1776 struct drm_device *dev = data;
1777 struct drm_i915_private *dev_priv = to_i915(dev);
1778 u32 reg;
1779
1780 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1781 return -ENODEV;
1782
1783 mutex_lock(&dev_priv->fbc.lock);
1784
1785 reg = I915_READ(ILK_DPFC_CONTROL);
1786 dev_priv->fbc.false_color = val;
1787
1788 I915_WRITE(ILK_DPFC_CONTROL, val ?
1789 (reg | FBC_CTL_FALSE_COLOR) :
1790 (reg & ~FBC_CTL_FALSE_COLOR));
1791
1792 mutex_unlock(&dev_priv->fbc.lock);
1793 return 0;
1794}
1795
1796DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1797 i915_fbc_fc_get, i915_fbc_fc_set,
1798 "%llu\n");
1799
1800static int i915_ips_status(struct seq_file *m, void *unused)
1801{
1802 struct drm_info_node *node = m->private;
1803 struct drm_device *dev = node->minor->dev;
1804 struct drm_i915_private *dev_priv = to_i915(dev);
1805
1806 if (!HAS_IPS(dev)) {
1807 seq_puts(m, "not supported\n");
1808 return 0;
1809 }
1810
1811 intel_runtime_pm_get(dev_priv);
1812
1813 seq_printf(m, "Enabled by kernel parameter: %s\n",
1814 yesno(i915.enable_ips));
1815
1816 if (INTEL_INFO(dev)->gen >= 8) {
1817 seq_puts(m, "Currently: unknown\n");
1818 } else {
1819 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1820 seq_puts(m, "Currently: enabled\n");
1821 else
1822 seq_puts(m, "Currently: disabled\n");
1823 }
1824
1825 intel_runtime_pm_put(dev_priv);
1826
1827 return 0;
1828}
1829
1830static int i915_sr_status(struct seq_file *m, void *unused)
1831{
1832 struct drm_info_node *node = m->private;
1833 struct drm_device *dev = node->minor->dev;
1834 struct drm_i915_private *dev_priv = to_i915(dev);
1835 bool sr_enabled = false;
1836
1837 intel_runtime_pm_get(dev_priv);
1838
1839 if (HAS_PCH_SPLIT(dev))
1840 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1841 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1842 IS_I945G(dev) || IS_I945GM(dev))
1843 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1844 else if (IS_I915GM(dev))
1845 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1846 else if (IS_PINEVIEW(dev))
1847 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1848 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1849 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1850
1851 intel_runtime_pm_put(dev_priv);
1852
1853 seq_printf(m, "self-refresh: %s\n",
1854 sr_enabled ? "enabled" : "disabled");
1855
1856 return 0;
1857}
1858
1859static int i915_emon_status(struct seq_file *m, void *unused)
1860{
1861 struct drm_info_node *node = m->private;
1862 struct drm_device *dev = node->minor->dev;
1863 struct drm_i915_private *dev_priv = to_i915(dev);
1864 unsigned long temp, chipset, gfx;
1865 int ret;
1866
1867 if (!IS_GEN5(dev))
1868 return -ENODEV;
1869
1870 ret = mutex_lock_interruptible(&dev->struct_mutex);
1871 if (ret)
1872 return ret;
1873
1874 temp = i915_mch_val(dev_priv);
1875 chipset = i915_chipset_val(dev_priv);
1876 gfx = i915_gfx_val(dev_priv);
1877 mutex_unlock(&dev->struct_mutex);
1878
1879 seq_printf(m, "GMCH temp: %ld\n", temp);
1880 seq_printf(m, "Chipset power: %ld\n", chipset);
1881 seq_printf(m, "GFX power: %ld\n", gfx);
1882 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1883
1884 return 0;
1885}
1886
1887static int i915_ring_freq_table(struct seq_file *m, void *unused)
1888{
1889 struct drm_info_node *node = m->private;
1890 struct drm_device *dev = node->minor->dev;
1891 struct drm_i915_private *dev_priv = to_i915(dev);
1892 int ret = 0;
1893 int gpu_freq, ia_freq;
1894 unsigned int max_gpu_freq, min_gpu_freq;
1895
1896 if (!HAS_CORE_RING_FREQ(dev)) {
1897 seq_puts(m, "unsupported on this chipset\n");
1898 return 0;
1899 }
1900
1901 intel_runtime_pm_get(dev_priv);
1902
1903 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1904 if (ret)
1905 goto out;
1906
1907 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1908 /* Convert GT frequency to 50 HZ units */
1909 min_gpu_freq =
1910 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1911 max_gpu_freq =
1912 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1913 } else {
1914 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1915 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1916 }
1917
1918 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1919
1920 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1921 ia_freq = gpu_freq;
1922 sandybridge_pcode_read(dev_priv,
1923 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1924 &ia_freq);
1925 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1926 intel_gpu_freq(dev_priv, (gpu_freq *
1927 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1928 GEN9_FREQ_SCALER : 1))),
1929 ((ia_freq >> 0) & 0xff) * 100,
1930 ((ia_freq >> 8) & 0xff) * 100);
1931 }
1932
1933 mutex_unlock(&dev_priv->rps.hw_lock);
1934
1935out:
1936 intel_runtime_pm_put(dev_priv);
1937 return ret;
1938}
1939
1940static int i915_opregion(struct seq_file *m, void *unused)
1941{
1942 struct drm_info_node *node = m->private;
1943 struct drm_device *dev = node->minor->dev;
1944 struct drm_i915_private *dev_priv = to_i915(dev);
1945 struct intel_opregion *opregion = &dev_priv->opregion;
1946 int ret;
1947
1948 ret = mutex_lock_interruptible(&dev->struct_mutex);
1949 if (ret)
1950 goto out;
1951
1952 if (opregion->header)
1953 seq_write(m, opregion->header, OPREGION_SIZE);
1954
1955 mutex_unlock(&dev->struct_mutex);
1956
1957out:
1958 return 0;
1959}
1960
1961static int i915_vbt(struct seq_file *m, void *unused)
1962{
1963 struct drm_info_node *node = m->private;
1964 struct drm_device *dev = node->minor->dev;
1965 struct drm_i915_private *dev_priv = to_i915(dev);
1966 struct intel_opregion *opregion = &dev_priv->opregion;
1967
1968 if (opregion->vbt)
1969 seq_write(m, opregion->vbt, opregion->vbt_size);
1970
1971 return 0;
1972}
1973
1974static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1975{
1976 struct drm_info_node *node = m->private;
1977 struct drm_device *dev = node->minor->dev;
1978 struct intel_framebuffer *fbdev_fb = NULL;
1979 struct drm_framebuffer *drm_fb;
1980 int ret;
1981
1982 ret = mutex_lock_interruptible(&dev->struct_mutex);
1983 if (ret)
1984 return ret;
1985
1986#ifdef CONFIG_DRM_FBDEV_EMULATION
1987 if (to_i915(dev)->fbdev) {
1988 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1989
1990 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1991 fbdev_fb->base.width,
1992 fbdev_fb->base.height,
1993 fbdev_fb->base.depth,
1994 fbdev_fb->base.bits_per_pixel,
1995 fbdev_fb->base.modifier[0],
1996 drm_framebuffer_read_refcount(&fbdev_fb->base));
1997 describe_obj(m, fbdev_fb->obj);
1998 seq_putc(m, '\n');
1999 }
2000#endif
2001
2002 mutex_lock(&dev->mode_config.fb_lock);
2003 drm_for_each_fb(drm_fb, dev) {
2004 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
2005 if (fb == fbdev_fb)
2006 continue;
2007
2008 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
2009 fb->base.width,
2010 fb->base.height,
2011 fb->base.depth,
2012 fb->base.bits_per_pixel,
2013 fb->base.modifier[0],
2014 drm_framebuffer_read_refcount(&fb->base));
2015 describe_obj(m, fb->obj);
2016 seq_putc(m, '\n');
2017 }
2018 mutex_unlock(&dev->mode_config.fb_lock);
2019 mutex_unlock(&dev->struct_mutex);
2020
2021 return 0;
2022}
2023
2024static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
2025{
2026 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
2027 ring->space, ring->head, ring->tail,
2028 ring->last_retired_head);
2029}
2030
2031static int i915_context_status(struct seq_file *m, void *unused)
2032{
2033 struct drm_info_node *node = m->private;
2034 struct drm_device *dev = node->minor->dev;
2035 struct drm_i915_private *dev_priv = to_i915(dev);
2036 struct intel_engine_cs *engine;
2037 struct i915_gem_context *ctx;
2038 int ret;
2039
2040 ret = mutex_lock_interruptible(&dev->struct_mutex);
2041 if (ret)
2042 return ret;
2043
2044 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2045 seq_printf(m, "HW context %u ", ctx->hw_id);
2046 if (IS_ERR(ctx->file_priv)) {
2047 seq_puts(m, "(deleted) ");
2048 } else if (ctx->file_priv) {
2049 struct pid *pid = ctx->file_priv->file->pid;
2050 struct task_struct *task;
2051
2052 task = get_pid_task(pid, PIDTYPE_PID);
2053 if (task) {
2054 seq_printf(m, "(%s [%d]) ",
2055 task->comm, task->pid);
2056 put_task_struct(task);
2057 }
2058 } else {
2059 seq_puts(m, "(kernel) ");
2060 }
2061
2062 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
2063 seq_putc(m, '\n');
2064
2065 for_each_engine(engine, dev_priv) {
2066 struct intel_context *ce = &ctx->engine[engine->id];
2067
2068 seq_printf(m, "%s: ", engine->name);
2069 seq_putc(m, ce->initialised ? 'I' : 'i');
2070 if (ce->state)
2071 describe_obj(m, ce->state);
2072 if (ce->ring)
2073 describe_ctx_ring(m, ce->ring);
2074 seq_putc(m, '\n');
2075 }
2076
2077 seq_putc(m, '\n');
2078 }
2079
2080 mutex_unlock(&dev->struct_mutex);
2081
2082 return 0;
2083}
2084
2085static void i915_dump_lrc_obj(struct seq_file *m,
2086 struct i915_gem_context *ctx,
2087 struct intel_engine_cs *engine)
2088{
2089 struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
2090 struct page *page;
2091 uint32_t *reg_state;
2092 int j;
2093 unsigned long ggtt_offset = 0;
2094
2095 seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2096
2097 if (ctx_obj == NULL) {
2098 seq_puts(m, "\tNot allocated\n");
2099 return;
2100 }
2101
2102 if (!i915_gem_obj_ggtt_bound(ctx_obj))
2103 seq_puts(m, "\tNot bound in GGTT\n");
2104 else
2105 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2106
2107 if (i915_gem_object_get_pages(ctx_obj)) {
2108 seq_puts(m, "\tFailed to get pages for context object\n");
2109 return;
2110 }
2111
2112 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2113 if (!WARN_ON(page == NULL)) {
2114 reg_state = kmap_atomic(page);
2115
2116 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2117 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2118 ggtt_offset + 4096 + (j * 4),
2119 reg_state[j], reg_state[j + 1],
2120 reg_state[j + 2], reg_state[j + 3]);
2121 }
2122 kunmap_atomic(reg_state);
2123 }
2124
2125 seq_putc(m, '\n');
2126}
2127
2128static int i915_dump_lrc(struct seq_file *m, void *unused)
2129{
2130 struct drm_info_node *node = (struct drm_info_node *) m->private;
2131 struct drm_device *dev = node->minor->dev;
2132 struct drm_i915_private *dev_priv = to_i915(dev);
2133 struct intel_engine_cs *engine;
2134 struct i915_gem_context *ctx;
2135 int ret;
2136
2137 if (!i915.enable_execlists) {
2138 seq_printf(m, "Logical Ring Contexts are disabled\n");
2139 return 0;
2140 }
2141
2142 ret = mutex_lock_interruptible(&dev->struct_mutex);
2143 if (ret)
2144 return ret;
2145
2146 list_for_each_entry(ctx, &dev_priv->context_list, link)
2147 for_each_engine(engine, dev_priv)
2148 i915_dump_lrc_obj(m, ctx, engine);
2149
2150 mutex_unlock(&dev->struct_mutex);
2151
2152 return 0;
2153}
2154
2155static int i915_execlists(struct seq_file *m, void *data)
2156{
2157 struct drm_info_node *node = (struct drm_info_node *)m->private;
2158 struct drm_device *dev = node->minor->dev;
2159 struct drm_i915_private *dev_priv = to_i915(dev);
2160 struct intel_engine_cs *engine;
2161 u32 status_pointer;
2162 u8 read_pointer;
2163 u8 write_pointer;
2164 u32 status;
2165 u32 ctx_id;
2166 struct list_head *cursor;
2167 int i, ret;
2168
2169 if (!i915.enable_execlists) {
2170 seq_puts(m, "Logical Ring Contexts are disabled\n");
2171 return 0;
2172 }
2173
2174 ret = mutex_lock_interruptible(&dev->struct_mutex);
2175 if (ret)
2176 return ret;
2177
2178 intel_runtime_pm_get(dev_priv);
2179
2180 for_each_engine(engine, dev_priv) {
2181 struct drm_i915_gem_request *head_req = NULL;
2182 int count = 0;
2183
2184 seq_printf(m, "%s\n", engine->name);
2185
2186 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2187 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
2188 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2189 status, ctx_id);
2190
2191 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
2192 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2193
2194 read_pointer = engine->next_context_status_buffer;
2195 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
2196 if (read_pointer > write_pointer)
2197 write_pointer += GEN8_CSB_ENTRIES;
2198 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2199 read_pointer, write_pointer);
2200
2201 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
2202 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2203 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
2204
2205 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2206 i, status, ctx_id);
2207 }
2208
2209 spin_lock_bh(&engine->execlist_lock);
2210 list_for_each(cursor, &engine->execlist_queue)
2211 count++;
2212 head_req = list_first_entry_or_null(&engine->execlist_queue,
2213 struct drm_i915_gem_request,
2214 execlist_link);
2215 spin_unlock_bh(&engine->execlist_lock);
2216
2217 seq_printf(m, "\t%d requests in queue\n", count);
2218 if (head_req) {
2219 seq_printf(m, "\tHead request context: %u\n",
2220 head_req->ctx->hw_id);
2221 seq_printf(m, "\tHead request tail: %u\n",
2222 head_req->tail);
2223 }
2224
2225 seq_putc(m, '\n');
2226 }
2227
2228 intel_runtime_pm_put(dev_priv);
2229 mutex_unlock(&dev->struct_mutex);
2230
2231 return 0;
2232}
2233
2234static const char *swizzle_string(unsigned swizzle)
2235{
2236 switch (swizzle) {
2237 case I915_BIT_6_SWIZZLE_NONE:
2238 return "none";
2239 case I915_BIT_6_SWIZZLE_9:
2240 return "bit9";
2241 case I915_BIT_6_SWIZZLE_9_10:
2242 return "bit9/bit10";
2243 case I915_BIT_6_SWIZZLE_9_11:
2244 return "bit9/bit11";
2245 case I915_BIT_6_SWIZZLE_9_10_11:
2246 return "bit9/bit10/bit11";
2247 case I915_BIT_6_SWIZZLE_9_17:
2248 return "bit9/bit17";
2249 case I915_BIT_6_SWIZZLE_9_10_17:
2250 return "bit9/bit10/bit17";
2251 case I915_BIT_6_SWIZZLE_UNKNOWN:
2252 return "unknown";
2253 }
2254
2255 return "bug";
2256}
2257
2258static int i915_swizzle_info(struct seq_file *m, void *data)
2259{
2260 struct drm_info_node *node = m->private;
2261 struct drm_device *dev = node->minor->dev;
2262 struct drm_i915_private *dev_priv = to_i915(dev);
2263 int ret;
2264
2265 ret = mutex_lock_interruptible(&dev->struct_mutex);
2266 if (ret)
2267 return ret;
2268 intel_runtime_pm_get(dev_priv);
2269
2270 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2271 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2272 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2273 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2274
2275 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2276 seq_printf(m, "DDC = 0x%08x\n",
2277 I915_READ(DCC));
2278 seq_printf(m, "DDC2 = 0x%08x\n",
2279 I915_READ(DCC2));
2280 seq_printf(m, "C0DRB3 = 0x%04x\n",
2281 I915_READ16(C0DRB3));
2282 seq_printf(m, "C1DRB3 = 0x%04x\n",
2283 I915_READ16(C1DRB3));
2284 } else if (INTEL_INFO(dev)->gen >= 6) {
2285 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2286 I915_READ(MAD_DIMM_C0));
2287 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2288 I915_READ(MAD_DIMM_C1));
2289 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2290 I915_READ(MAD_DIMM_C2));
2291 seq_printf(m, "TILECTL = 0x%08x\n",
2292 I915_READ(TILECTL));
2293 if (INTEL_INFO(dev)->gen >= 8)
2294 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2295 I915_READ(GAMTARBMODE));
2296 else
2297 seq_printf(m, "ARB_MODE = 0x%08x\n",
2298 I915_READ(ARB_MODE));
2299 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2300 I915_READ(DISP_ARB_CTL));
2301 }
2302
2303 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2304 seq_puts(m, "L-shaped memory detected\n");
2305
2306 intel_runtime_pm_put(dev_priv);
2307 mutex_unlock(&dev->struct_mutex);
2308
2309 return 0;
2310}
2311
2312static int per_file_ctx(int id, void *ptr, void *data)
2313{
2314 struct i915_gem_context *ctx = ptr;
2315 struct seq_file *m = data;
2316 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2317
2318 if (!ppgtt) {
2319 seq_printf(m, " no ppgtt for context %d\n",
2320 ctx->user_handle);
2321 return 0;
2322 }
2323
2324 if (i915_gem_context_is_default(ctx))
2325 seq_puts(m, " default context:\n");
2326 else
2327 seq_printf(m, " context %d:\n", ctx->user_handle);
2328 ppgtt->debug_dump(ppgtt, m);
2329
2330 return 0;
2331}
2332
2333static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2334{
2335 struct drm_i915_private *dev_priv = to_i915(dev);
2336 struct intel_engine_cs *engine;
2337 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2338 int i;
2339
2340 if (!ppgtt)
2341 return;
2342
2343 for_each_engine(engine, dev_priv) {
2344 seq_printf(m, "%s\n", engine->name);
2345 for (i = 0; i < 4; i++) {
2346 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2347 pdp <<= 32;
2348 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2349 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2350 }
2351 }
2352}
2353
2354static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2355{
2356 struct drm_i915_private *dev_priv = to_i915(dev);
2357 struct intel_engine_cs *engine;
2358
2359 if (IS_GEN6(dev_priv))
2360 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2361
2362 for_each_engine(engine, dev_priv) {
2363 seq_printf(m, "%s\n", engine->name);
2364 if (IS_GEN7(dev_priv))
2365 seq_printf(m, "GFX_MODE: 0x%08x\n",
2366 I915_READ(RING_MODE_GEN7(engine)));
2367 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2368 I915_READ(RING_PP_DIR_BASE(engine)));
2369 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2370 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2371 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2372 I915_READ(RING_PP_DIR_DCLV(engine)));
2373 }
2374 if (dev_priv->mm.aliasing_ppgtt) {
2375 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2376
2377 seq_puts(m, "aliasing PPGTT:\n");
2378 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2379
2380 ppgtt->debug_dump(ppgtt, m);
2381 }
2382
2383 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2384}
2385
2386static int i915_ppgtt_info(struct seq_file *m, void *data)
2387{
2388 struct drm_info_node *node = m->private;
2389 struct drm_device *dev = node->minor->dev;
2390 struct drm_i915_private *dev_priv = to_i915(dev);
2391 struct drm_file *file;
2392
2393 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2394 if (ret)
2395 return ret;
2396 intel_runtime_pm_get(dev_priv);
2397
2398 if (INTEL_INFO(dev)->gen >= 8)
2399 gen8_ppgtt_info(m, dev);
2400 else if (INTEL_INFO(dev)->gen >= 6)
2401 gen6_ppgtt_info(m, dev);
2402
2403 mutex_lock(&dev->filelist_mutex);
2404 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2405 struct drm_i915_file_private *file_priv = file->driver_priv;
2406 struct task_struct *task;
2407
2408 task = get_pid_task(file->pid, PIDTYPE_PID);
2409 if (!task) {
2410 ret = -ESRCH;
2411 goto out_unlock;
2412 }
2413 seq_printf(m, "\nproc: %s\n", task->comm);
2414 put_task_struct(task);
2415 idr_for_each(&file_priv->context_idr, per_file_ctx,
2416 (void *)(unsigned long)m);
2417 }
2418out_unlock:
2419 mutex_unlock(&dev->filelist_mutex);
2420
2421 intel_runtime_pm_put(dev_priv);
2422 mutex_unlock(&dev->struct_mutex);
2423
2424 return ret;
2425}
2426
2427static int count_irq_waiters(struct drm_i915_private *i915)
2428{
2429 struct intel_engine_cs *engine;
2430 int count = 0;
2431
2432 for_each_engine(engine, i915)
2433 count += intel_engine_has_waiter(engine);
2434
2435 return count;
2436}
2437
2438static int i915_rps_boost_info(struct seq_file *m, void *data)
2439{
2440 struct drm_info_node *node = m->private;
2441 struct drm_device *dev = node->minor->dev;
2442 struct drm_i915_private *dev_priv = to_i915(dev);
2443 struct drm_file *file;
2444
2445 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2446 seq_printf(m, "GPU busy? %s [%x]\n",
2447 yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
2448 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2449 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2450 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2451 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2452 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2453 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2454 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2455
2456 mutex_lock(&dev->filelist_mutex);
2457 spin_lock(&dev_priv->rps.client_lock);
2458 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2459 struct drm_i915_file_private *file_priv = file->driver_priv;
2460 struct task_struct *task;
2461
2462 rcu_read_lock();
2463 task = pid_task(file->pid, PIDTYPE_PID);
2464 seq_printf(m, "%s [%d]: %d boosts%s\n",
2465 task ? task->comm : "<unknown>",
2466 task ? task->pid : -1,
2467 file_priv->rps.boosts,
2468 list_empty(&file_priv->rps.link) ? "" : ", active");
2469 rcu_read_unlock();
2470 }
2471 seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2472 spin_unlock(&dev_priv->rps.client_lock);
2473 mutex_unlock(&dev->filelist_mutex);
2474
2475 return 0;
2476}
2477
2478static int i915_llc(struct seq_file *m, void *data)
2479{
2480 struct drm_info_node *node = m->private;
2481 struct drm_device *dev = node->minor->dev;
2482 struct drm_i915_private *dev_priv = to_i915(dev);
2483 const bool edram = INTEL_GEN(dev_priv) > 8;
2484
2485 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2486 seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2487 intel_uncore_edram_size(dev_priv)/1024/1024);
2488
2489 return 0;
2490}
2491
2492static int i915_guc_load_status_info(struct seq_file *m, void *data)
2493{
2494 struct drm_info_node *node = m->private;
2495 struct drm_i915_private *dev_priv = to_i915(node->minor->dev);
2496 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2497 u32 tmp, i;
2498
2499 if (!HAS_GUC_UCODE(dev_priv))
2500 return 0;
2501
2502 seq_printf(m, "GuC firmware status:\n");
2503 seq_printf(m, "\tpath: %s\n",
2504 guc_fw->guc_fw_path);
2505 seq_printf(m, "\tfetch: %s\n",
2506 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2507 seq_printf(m, "\tload: %s\n",
2508 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2509 seq_printf(m, "\tversion wanted: %d.%d\n",
2510 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2511 seq_printf(m, "\tversion found: %d.%d\n",
2512 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2513 seq_printf(m, "\theader: offset is %d; size = %d\n",
2514 guc_fw->header_offset, guc_fw->header_size);
2515 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2516 guc_fw->ucode_offset, guc_fw->ucode_size);
2517 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2518 guc_fw->rsa_offset, guc_fw->rsa_size);
2519
2520 tmp = I915_READ(GUC_STATUS);
2521
2522 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2523 seq_printf(m, "\tBootrom status = 0x%x\n",
2524 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2525 seq_printf(m, "\tuKernel status = 0x%x\n",
2526 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2527 seq_printf(m, "\tMIA Core status = 0x%x\n",
2528 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2529 seq_puts(m, "\nScratch registers:\n");
2530 for (i = 0; i < 16; i++)
2531 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2532
2533 return 0;
2534}
2535
2536static void i915_guc_client_info(struct seq_file *m,
2537 struct drm_i915_private *dev_priv,
2538 struct i915_guc_client *client)
2539{
2540 struct intel_engine_cs *engine;
2541 uint64_t tot = 0;
2542
2543 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2544 client->priority, client->ctx_index, client->proc_desc_offset);
2545 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2546 client->doorbell_id, client->doorbell_offset, client->cookie);
2547 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2548 client->wq_size, client->wq_offset, client->wq_tail);
2549
2550 seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2551 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2552 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2553 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2554
2555 for_each_engine(engine, dev_priv) {
2556 seq_printf(m, "\tSubmissions: %llu %s\n",
2557 client->submissions[engine->id],
2558 engine->name);
2559 tot += client->submissions[engine->id];
2560 }
2561 seq_printf(m, "\tTotal: %llu\n", tot);
2562}
2563
2564static int i915_guc_info(struct seq_file *m, void *data)
2565{
2566 struct drm_info_node *node = m->private;
2567 struct drm_device *dev = node->minor->dev;
2568 struct drm_i915_private *dev_priv = to_i915(dev);
2569 struct intel_guc guc;
2570 struct i915_guc_client client = {};
2571 struct intel_engine_cs *engine;
2572 u64 total = 0;
2573
2574 if (!HAS_GUC_SCHED(dev_priv))
2575 return 0;
2576
2577 if (mutex_lock_interruptible(&dev->struct_mutex))
2578 return 0;
2579
2580 /* Take a local copy of the GuC data, so we can dump it at leisure */
2581 guc = dev_priv->guc;
2582 if (guc.execbuf_client)
2583 client = *guc.execbuf_client;
2584
2585 mutex_unlock(&dev->struct_mutex);
2586
2587 seq_printf(m, "Doorbell map:\n");
2588 seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2589 seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2590
2591 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2592 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2593 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2594 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2595 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2596
2597 seq_printf(m, "\nGuC submissions:\n");
2598 for_each_engine(engine, dev_priv) {
2599 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2600 engine->name, guc.submissions[engine->id],
2601 guc.last_seqno[engine->id]);
2602 total += guc.submissions[engine->id];
2603 }
2604 seq_printf(m, "\t%s: %llu\n", "Total", total);
2605
2606 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2607 i915_guc_client_info(m, dev_priv, &client);
2608
2609 /* Add more as required ... */
2610
2611 return 0;
2612}
2613
2614static int i915_guc_log_dump(struct seq_file *m, void *data)
2615{
2616 struct drm_info_node *node = m->private;
2617 struct drm_device *dev = node->minor->dev;
2618 struct drm_i915_private *dev_priv = to_i915(dev);
2619 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2620 u32 *log;
2621 int i = 0, pg;
2622
2623 if (!log_obj)
2624 return 0;
2625
2626 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2627 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2628
2629 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2630 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2631 *(log + i), *(log + i + 1),
2632 *(log + i + 2), *(log + i + 3));
2633
2634 kunmap_atomic(log);
2635 }
2636
2637 seq_putc(m, '\n');
2638
2639 return 0;
2640}
2641
2642static int i915_edp_psr_status(struct seq_file *m, void *data)
2643{
2644 struct drm_info_node *node = m->private;
2645 struct drm_device *dev = node->minor->dev;
2646 struct drm_i915_private *dev_priv = to_i915(dev);
2647 u32 psrperf = 0;
2648 u32 stat[3];
2649 enum pipe pipe;
2650 bool enabled = false;
2651
2652 if (!HAS_PSR(dev)) {
2653 seq_puts(m, "PSR not supported\n");
2654 return 0;
2655 }
2656
2657 intel_runtime_pm_get(dev_priv);
2658
2659 mutex_lock(&dev_priv->psr.lock);
2660 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2661 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2662 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2663 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2664 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2665 dev_priv->psr.busy_frontbuffer_bits);
2666 seq_printf(m, "Re-enable work scheduled: %s\n",
2667 yesno(work_busy(&dev_priv->psr.work.work)));
2668
2669 if (HAS_DDI(dev))
2670 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2671 else {
2672 for_each_pipe(dev_priv, pipe) {
2673 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2674 VLV_EDP_PSR_CURR_STATE_MASK;
2675 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2676 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2677 enabled = true;
2678 }
2679 }
2680
2681 seq_printf(m, "Main link in standby mode: %s\n",
2682 yesno(dev_priv->psr.link_standby));
2683
2684 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2685
2686 if (!HAS_DDI(dev))
2687 for_each_pipe(dev_priv, pipe) {
2688 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2689 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2690 seq_printf(m, " pipe %c", pipe_name(pipe));
2691 }
2692 seq_puts(m, "\n");
2693
2694 /*
2695 * VLV/CHV PSR has no kind of performance counter
2696 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2697 */
2698 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2699 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2700 EDP_PSR_PERF_CNT_MASK;
2701
2702 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2703 }
2704 mutex_unlock(&dev_priv->psr.lock);
2705
2706 intel_runtime_pm_put(dev_priv);
2707 return 0;
2708}
2709
2710static int i915_sink_crc(struct seq_file *m, void *data)
2711{
2712 struct drm_info_node *node = m->private;
2713 struct drm_device *dev = node->minor->dev;
2714 struct intel_connector *connector;
2715 struct intel_dp *intel_dp = NULL;
2716 int ret;
2717 u8 crc[6];
2718
2719 drm_modeset_lock_all(dev);
2720 for_each_intel_connector(dev, connector) {
2721 struct drm_crtc *crtc;
2722
2723 if (!connector->base.state->best_encoder)
2724 continue;
2725
2726 crtc = connector->base.state->crtc;
2727 if (!crtc->state->active)
2728 continue;
2729
2730 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2731 continue;
2732
2733 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2734
2735 ret = intel_dp_sink_crc(intel_dp, crc);
2736 if (ret)
2737 goto out;
2738
2739 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2740 crc[0], crc[1], crc[2],
2741 crc[3], crc[4], crc[5]);
2742 goto out;
2743 }
2744 ret = -ENODEV;
2745out:
2746 drm_modeset_unlock_all(dev);
2747 return ret;
2748}
2749
2750static int i915_energy_uJ(struct seq_file *m, void *data)
2751{
2752 struct drm_info_node *node = m->private;
2753 struct drm_device *dev = node->minor->dev;
2754 struct drm_i915_private *dev_priv = to_i915(dev);
2755 u64 power;
2756 u32 units;
2757
2758 if (INTEL_INFO(dev)->gen < 6)
2759 return -ENODEV;
2760
2761 intel_runtime_pm_get(dev_priv);
2762
2763 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2764 power = (power & 0x1f00) >> 8;
2765 units = 1000000 / (1 << power); /* convert to uJ */
2766 power = I915_READ(MCH_SECP_NRG_STTS);
2767 power *= units;
2768
2769 intel_runtime_pm_put(dev_priv);
2770
2771 seq_printf(m, "%llu", (long long unsigned)power);
2772
2773 return 0;
2774}
2775
2776static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2777{
2778 struct drm_info_node *node = m->private;
2779 struct drm_device *dev = node->minor->dev;
2780 struct drm_i915_private *dev_priv = to_i915(dev);
2781
2782 if (!HAS_RUNTIME_PM(dev_priv))
2783 seq_puts(m, "Runtime power management not supported\n");
2784
2785 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2786 seq_printf(m, "IRQs disabled: %s\n",
2787 yesno(!intel_irqs_enabled(dev_priv)));
2788#ifdef CONFIG_PM
2789 seq_printf(m, "Usage count: %d\n",
2790 atomic_read(&dev->dev->power.usage_count));
2791#else
2792 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2793#endif
2794 seq_printf(m, "PCI device power state: %s [%d]\n",
2795 pci_power_name(dev_priv->drm.pdev->current_state),
2796 dev_priv->drm.pdev->current_state);
2797
2798 return 0;
2799}
2800
2801static int i915_power_domain_info(struct seq_file *m, void *unused)
2802{
2803 struct drm_info_node *node = m->private;
2804 struct drm_device *dev = node->minor->dev;
2805 struct drm_i915_private *dev_priv = to_i915(dev);
2806 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2807 int i;
2808
2809 mutex_lock(&power_domains->lock);
2810
2811 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2812 for (i = 0; i < power_domains->power_well_count; i++) {
2813 struct i915_power_well *power_well;
2814 enum intel_display_power_domain power_domain;
2815
2816 power_well = &power_domains->power_wells[i];
2817 seq_printf(m, "%-25s %d\n", power_well->name,
2818 power_well->count);
2819
2820 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2821 power_domain++) {
2822 if (!(BIT(power_domain) & power_well->domains))
2823 continue;
2824
2825 seq_printf(m, " %-23s %d\n",
2826 intel_display_power_domain_str(power_domain),
2827 power_domains->domain_use_count[power_domain]);
2828 }
2829 }
2830
2831 mutex_unlock(&power_domains->lock);
2832
2833 return 0;
2834}
2835
2836static int i915_dmc_info(struct seq_file *m, void *unused)
2837{
2838 struct drm_info_node *node = m->private;
2839 struct drm_device *dev = node->minor->dev;
2840 struct drm_i915_private *dev_priv = to_i915(dev);
2841 struct intel_csr *csr;
2842
2843 if (!HAS_CSR(dev)) {
2844 seq_puts(m, "not supported\n");
2845 return 0;
2846 }
2847
2848 csr = &dev_priv->csr;
2849
2850 intel_runtime_pm_get(dev_priv);
2851
2852 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2853 seq_printf(m, "path: %s\n", csr->fw_path);
2854
2855 if (!csr->dmc_payload)
2856 goto out;
2857
2858 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2859 CSR_VERSION_MINOR(csr->version));
2860
2861 if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2862 seq_printf(m, "DC3 -> DC5 count: %d\n",
2863 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2864 seq_printf(m, "DC5 -> DC6 count: %d\n",
2865 I915_READ(SKL_CSR_DC5_DC6_COUNT));
2866 } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2867 seq_printf(m, "DC3 -> DC5 count: %d\n",
2868 I915_READ(BXT_CSR_DC3_DC5_COUNT));
2869 }
2870
2871out:
2872 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2873 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2874 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2875
2876 intel_runtime_pm_put(dev_priv);
2877
2878 return 0;
2879}
2880
2881static void intel_seq_print_mode(struct seq_file *m, int tabs,
2882 struct drm_display_mode *mode)
2883{
2884 int i;
2885
2886 for (i = 0; i < tabs; i++)
2887 seq_putc(m, '\t');
2888
2889 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2890 mode->base.id, mode->name,
2891 mode->vrefresh, mode->clock,
2892 mode->hdisplay, mode->hsync_start,
2893 mode->hsync_end, mode->htotal,
2894 mode->vdisplay, mode->vsync_start,
2895 mode->vsync_end, mode->vtotal,
2896 mode->type, mode->flags);
2897}
2898
2899static void intel_encoder_info(struct seq_file *m,
2900 struct intel_crtc *intel_crtc,
2901 struct intel_encoder *intel_encoder)
2902{
2903 struct drm_info_node *node = m->private;
2904 struct drm_device *dev = node->minor->dev;
2905 struct drm_crtc *crtc = &intel_crtc->base;
2906 struct intel_connector *intel_connector;
2907 struct drm_encoder *encoder;
2908
2909 encoder = &intel_encoder->base;
2910 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2911 encoder->base.id, encoder->name);
2912 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2913 struct drm_connector *connector = &intel_connector->base;
2914 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2915 connector->base.id,
2916 connector->name,
2917 drm_get_connector_status_name(connector->status));
2918 if (connector->status == connector_status_connected) {
2919 struct drm_display_mode *mode = &crtc->mode;
2920 seq_printf(m, ", mode:\n");
2921 intel_seq_print_mode(m, 2, mode);
2922 } else {
2923 seq_putc(m, '\n');
2924 }
2925 }
2926}
2927
2928static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2929{
2930 struct drm_info_node *node = m->private;
2931 struct drm_device *dev = node->minor->dev;
2932 struct drm_crtc *crtc = &intel_crtc->base;
2933 struct intel_encoder *intel_encoder;
2934 struct drm_plane_state *plane_state = crtc->primary->state;
2935 struct drm_framebuffer *fb = plane_state->fb;
2936
2937 if (fb)
2938 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2939 fb->base.id, plane_state->src_x >> 16,
2940 plane_state->src_y >> 16, fb->width, fb->height);
2941 else
2942 seq_puts(m, "\tprimary plane disabled\n");
2943 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2944 intel_encoder_info(m, intel_crtc, intel_encoder);
2945}
2946
2947static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2948{
2949 struct drm_display_mode *mode = panel->fixed_mode;
2950
2951 seq_printf(m, "\tfixed mode:\n");
2952 intel_seq_print_mode(m, 2, mode);
2953}
2954
2955static void intel_dp_info(struct seq_file *m,
2956 struct intel_connector *intel_connector)
2957{
2958 struct intel_encoder *intel_encoder = intel_connector->encoder;
2959 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2960
2961 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2962 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2963 if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2964 intel_panel_info(m, &intel_connector->panel);
2965}
2966
2967static void intel_hdmi_info(struct seq_file *m,
2968 struct intel_connector *intel_connector)
2969{
2970 struct intel_encoder *intel_encoder = intel_connector->encoder;
2971 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2972
2973 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2974}
2975
2976static void intel_lvds_info(struct seq_file *m,
2977 struct intel_connector *intel_connector)
2978{
2979 intel_panel_info(m, &intel_connector->panel);
2980}
2981
2982static void intel_connector_info(struct seq_file *m,
2983 struct drm_connector *connector)
2984{
2985 struct intel_connector *intel_connector = to_intel_connector(connector);
2986 struct intel_encoder *intel_encoder = intel_connector->encoder;
2987 struct drm_display_mode *mode;
2988
2989 seq_printf(m, "connector %d: type %s, status: %s\n",
2990 connector->base.id, connector->name,
2991 drm_get_connector_status_name(connector->status));
2992 if (connector->status == connector_status_connected) {
2993 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2994 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2995 connector->display_info.width_mm,
2996 connector->display_info.height_mm);
2997 seq_printf(m, "\tsubpixel order: %s\n",
2998 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2999 seq_printf(m, "\tCEA rev: %d\n",
3000 connector->display_info.cea_rev);
3001 }
3002
3003 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3004 return;
3005
3006 switch (connector->connector_type) {
3007 case DRM_MODE_CONNECTOR_DisplayPort:
3008 case DRM_MODE_CONNECTOR_eDP:
3009 intel_dp_info(m, intel_connector);
3010 break;
3011 case DRM_MODE_CONNECTOR_LVDS:
3012 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
3013 intel_lvds_info(m, intel_connector);
3014 break;
3015 case DRM_MODE_CONNECTOR_HDMIA:
3016 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
3017 intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
3018 intel_hdmi_info(m, intel_connector);
3019 break;
3020 default:
3021 break;
3022 }
3023
3024 seq_printf(m, "\tmodes:\n");
3025 list_for_each_entry(mode, &connector->modes, head)
3026 intel_seq_print_mode(m, 2, mode);
3027}
3028
3029static bool cursor_active(struct drm_device *dev, int pipe)
3030{
3031 struct drm_i915_private *dev_priv = to_i915(dev);
3032 u32 state;
3033
3034 if (IS_845G(dev) || IS_I865G(dev))
3035 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
3036 else
3037 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
3038
3039 return state;
3040}
3041
3042static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
3043{
3044 struct drm_i915_private *dev_priv = to_i915(dev);
3045 u32 pos;
3046
3047 pos = I915_READ(CURPOS(pipe));
3048
3049 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
3050 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
3051 *x = -*x;
3052
3053 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
3054 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
3055 *y = -*y;
3056
3057 return cursor_active(dev, pipe);
3058}
3059
3060static const char *plane_type(enum drm_plane_type type)
3061{
3062 switch (type) {
3063 case DRM_PLANE_TYPE_OVERLAY:
3064 return "OVL";
3065 case DRM_PLANE_TYPE_PRIMARY:
3066 return "PRI";
3067 case DRM_PLANE_TYPE_CURSOR:
3068 return "CUR";
3069 /*
3070 * Deliberately omitting default: to generate compiler warnings
3071 * when a new drm_plane_type gets added.
3072 */
3073 }
3074
3075 return "unknown";
3076}
3077
3078static const char *plane_rotation(unsigned int rotation)
3079{
3080 static char buf[48];
3081 /*
3082 * According to doc only one DRM_ROTATE_ is allowed but this
3083 * will print them all to visualize if the values are misused
3084 */
3085 snprintf(buf, sizeof(buf),
3086 "%s%s%s%s%s%s(0x%08x)",
3087 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
3088 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
3089 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3090 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3091 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3092 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3093 rotation);
3094
3095 return buf;
3096}
3097
3098static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3099{
3100 struct drm_info_node *node = m->private;
3101 struct drm_device *dev = node->minor->dev;
3102 struct intel_plane *intel_plane;
3103
3104 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3105 struct drm_plane_state *state;
3106 struct drm_plane *plane = &intel_plane->base;
3107
3108 if (!plane->state) {
3109 seq_puts(m, "plane->state is NULL!\n");
3110 continue;
3111 }
3112
3113 state = plane->state;
3114
3115 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3116 plane->base.id,
3117 plane_type(intel_plane->base.type),
3118 state->crtc_x, state->crtc_y,
3119 state->crtc_w, state->crtc_h,
3120 (state->src_x >> 16),
3121 ((state->src_x & 0xffff) * 15625) >> 10,
3122 (state->src_y >> 16),
3123 ((state->src_y & 0xffff) * 15625) >> 10,
3124 (state->src_w >> 16),
3125 ((state->src_w & 0xffff) * 15625) >> 10,
3126 (state->src_h >> 16),
3127 ((state->src_h & 0xffff) * 15625) >> 10,
3128 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3129 plane_rotation(state->rotation));
3130 }
3131}
3132
3133static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3134{
3135 struct intel_crtc_state *pipe_config;
3136 int num_scalers = intel_crtc->num_scalers;
3137 int i;
3138
3139 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3140
3141 /* Not all platformas have a scaler */
3142 if (num_scalers) {
3143 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3144 num_scalers,
3145 pipe_config->scaler_state.scaler_users,
3146 pipe_config->scaler_state.scaler_id);
3147
3148 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3149 struct intel_scaler *sc =
3150 &pipe_config->scaler_state.scalers[i];
3151
3152 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3153 i, yesno(sc->in_use), sc->mode);
3154 }
3155 seq_puts(m, "\n");
3156 } else {
3157 seq_puts(m, "\tNo scalers available on this platform\n");
3158 }
3159}
3160
3161static int i915_display_info(struct seq_file *m, void *unused)
3162{
3163 struct drm_info_node *node = m->private;
3164 struct drm_device *dev = node->minor->dev;
3165 struct drm_i915_private *dev_priv = to_i915(dev);
3166 struct intel_crtc *crtc;
3167 struct drm_connector *connector;
3168
3169 intel_runtime_pm_get(dev_priv);
3170 drm_modeset_lock_all(dev);
3171 seq_printf(m, "CRTC info\n");
3172 seq_printf(m, "---------\n");
3173 for_each_intel_crtc(dev, crtc) {
3174 bool active;
3175 struct intel_crtc_state *pipe_config;
3176 int x, y;
3177
3178 pipe_config = to_intel_crtc_state(crtc->base.state);
3179
3180 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3181 crtc->base.base.id, pipe_name(crtc->pipe),
3182 yesno(pipe_config->base.active),
3183 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3184 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3185
3186 if (pipe_config->base.active) {
3187 intel_crtc_info(m, crtc);
3188
3189 active = cursor_position(dev, crtc->pipe, &x, &y);
3190 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3191 yesno(crtc->cursor_base),
3192 x, y, crtc->base.cursor->state->crtc_w,
3193 crtc->base.cursor->state->crtc_h,
3194 crtc->cursor_addr, yesno(active));
3195 intel_scaler_info(m, crtc);
3196 intel_plane_info(m, crtc);
3197 }
3198
3199 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3200 yesno(!crtc->cpu_fifo_underrun_disabled),
3201 yesno(!crtc->pch_fifo_underrun_disabled));
3202 }
3203
3204 seq_printf(m, "\n");
3205 seq_printf(m, "Connector info\n");
3206 seq_printf(m, "--------------\n");
3207 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3208 intel_connector_info(m, connector);
3209 }
3210 drm_modeset_unlock_all(dev);
3211 intel_runtime_pm_put(dev_priv);
3212
3213 return 0;
3214}
3215
3216static int i915_semaphore_status(struct seq_file *m, void *unused)
3217{
3218 struct drm_info_node *node = (struct drm_info_node *) m->private;
3219 struct drm_device *dev = node->minor->dev;
3220 struct drm_i915_private *dev_priv = to_i915(dev);
3221 struct intel_engine_cs *engine;
3222 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3223 enum intel_engine_id id;
3224 int j, ret;
3225
3226 if (!i915.semaphores) {
3227 seq_puts(m, "Semaphores are disabled\n");
3228 return 0;
3229 }
3230
3231 ret = mutex_lock_interruptible(&dev->struct_mutex);
3232 if (ret)
3233 return ret;
3234 intel_runtime_pm_get(dev_priv);
3235
3236 if (IS_BROADWELL(dev)) {
3237 struct page *page;
3238 uint64_t *seqno;
3239
3240 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3241
3242 seqno = (uint64_t *)kmap_atomic(page);
3243 for_each_engine_id(engine, dev_priv, id) {
3244 uint64_t offset;
3245
3246 seq_printf(m, "%s\n", engine->name);
3247
3248 seq_puts(m, " Last signal:");
3249 for (j = 0; j < num_rings; j++) {
3250 offset = id * I915_NUM_ENGINES + j;
3251 seq_printf(m, "0x%08llx (0x%02llx) ",
3252 seqno[offset], offset * 8);
3253 }
3254 seq_putc(m, '\n');
3255
3256 seq_puts(m, " Last wait: ");
3257 for (j = 0; j < num_rings; j++) {
3258 offset = id + (j * I915_NUM_ENGINES);
3259 seq_printf(m, "0x%08llx (0x%02llx) ",
3260 seqno[offset], offset * 8);
3261 }
3262 seq_putc(m, '\n');
3263
3264 }
3265 kunmap_atomic(seqno);
3266 } else {
3267 seq_puts(m, " Last signal:");
3268 for_each_engine(engine, dev_priv)
3269 for (j = 0; j < num_rings; j++)
3270 seq_printf(m, "0x%08x\n",
3271 I915_READ(engine->semaphore.mbox.signal[j]));
3272 seq_putc(m, '\n');
3273 }
3274
3275 seq_puts(m, "\nSync seqno:\n");
3276 for_each_engine(engine, dev_priv) {
3277 for (j = 0; j < num_rings; j++)
3278 seq_printf(m, " 0x%08x ",
3279 engine->semaphore.sync_seqno[j]);
3280 seq_putc(m, '\n');
3281 }
3282 seq_putc(m, '\n');
3283
3284 intel_runtime_pm_put(dev_priv);
3285 mutex_unlock(&dev->struct_mutex);
3286 return 0;
3287}
3288
3289static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3290{
3291 struct drm_info_node *node = (struct drm_info_node *) m->private;
3292 struct drm_device *dev = node->minor->dev;
3293 struct drm_i915_private *dev_priv = to_i915(dev);
3294 int i;
3295
3296 drm_modeset_lock_all(dev);
3297 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3298 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3299
3300 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3301 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3302 pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3303 seq_printf(m, " tracked hardware state:\n");
3304 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3305 seq_printf(m, " dpll_md: 0x%08x\n",
3306 pll->config.hw_state.dpll_md);
3307 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3308 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3309 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
3310 }
3311 drm_modeset_unlock_all(dev);
3312
3313 return 0;
3314}
3315
3316static int i915_wa_registers(struct seq_file *m, void *unused)
3317{
3318 int i;
3319 int ret;
3320 struct intel_engine_cs *engine;
3321 struct drm_info_node *node = (struct drm_info_node *) m->private;
3322 struct drm_device *dev = node->minor->dev;
3323 struct drm_i915_private *dev_priv = to_i915(dev);
3324 struct i915_workarounds *workarounds = &dev_priv->workarounds;
3325 enum intel_engine_id id;
3326
3327 ret = mutex_lock_interruptible(&dev->struct_mutex);
3328 if (ret)
3329 return ret;
3330
3331 intel_runtime_pm_get(dev_priv);
3332
3333 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3334 for_each_engine_id(engine, dev_priv, id)
3335 seq_printf(m, "HW whitelist count for %s: %d\n",
3336 engine->name, workarounds->hw_whitelist_count[id]);
3337 for (i = 0; i < workarounds->count; ++i) {
3338 i915_reg_t addr;
3339 u32 mask, value, read;
3340 bool ok;
3341
3342 addr = workarounds->reg[i].addr;
3343 mask = workarounds->reg[i].mask;
3344 value = workarounds->reg[i].value;
3345 read = I915_READ(addr);
3346 ok = (value & mask) == (read & mask);
3347 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3348 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3349 }
3350
3351 intel_runtime_pm_put(dev_priv);
3352 mutex_unlock(&dev->struct_mutex);
3353
3354 return 0;
3355}
3356
3357static int i915_ddb_info(struct seq_file *m, void *unused)
3358{
3359 struct drm_info_node *node = m->private;
3360 struct drm_device *dev = node->minor->dev;
3361 struct drm_i915_private *dev_priv = to_i915(dev);
3362 struct skl_ddb_allocation *ddb;
3363 struct skl_ddb_entry *entry;
3364 enum pipe pipe;
3365 int plane;
3366
3367 if (INTEL_INFO(dev)->gen < 9)
3368 return 0;
3369
3370 drm_modeset_lock_all(dev);
3371
3372 ddb = &dev_priv->wm.skl_hw.ddb;
3373
3374 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3375
3376 for_each_pipe(dev_priv, pipe) {
3377 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3378
3379 for_each_plane(dev_priv, pipe, plane) {
3380 entry = &ddb->plane[pipe][plane];
3381 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3382 entry->start, entry->end,
3383 skl_ddb_entry_size(entry));
3384 }
3385
3386 entry = &ddb->plane[pipe][PLANE_CURSOR];
3387 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3388 entry->end, skl_ddb_entry_size(entry));
3389 }
3390
3391 drm_modeset_unlock_all(dev);
3392
3393 return 0;
3394}
3395
3396static void drrs_status_per_crtc(struct seq_file *m,
3397 struct drm_device *dev, struct intel_crtc *intel_crtc)
3398{
3399 struct drm_i915_private *dev_priv = to_i915(dev);
3400 struct i915_drrs *drrs = &dev_priv->drrs;
3401 int vrefresh = 0;
3402 struct drm_connector *connector;
3403
3404 drm_for_each_connector(connector, dev) {
3405 if (connector->state->crtc != &intel_crtc->base)
3406 continue;
3407
3408 seq_printf(m, "%s:\n", connector->name);
3409 }
3410
3411 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3412 seq_puts(m, "\tVBT: DRRS_type: Static");
3413 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3414 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3415 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3416 seq_puts(m, "\tVBT: DRRS_type: None");
3417 else
3418 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3419
3420 seq_puts(m, "\n\n");
3421
3422 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3423 struct intel_panel *panel;
3424
3425 mutex_lock(&drrs->mutex);
3426 /* DRRS Supported */
3427 seq_puts(m, "\tDRRS Supported: Yes\n");
3428
3429 /* disable_drrs() will make drrs->dp NULL */
3430 if (!drrs->dp) {
3431 seq_puts(m, "Idleness DRRS: Disabled");
3432 mutex_unlock(&drrs->mutex);
3433 return;
3434 }
3435
3436 panel = &drrs->dp->attached_connector->panel;
3437 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3438 drrs->busy_frontbuffer_bits);
3439
3440 seq_puts(m, "\n\t\t");
3441 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3442 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3443 vrefresh = panel->fixed_mode->vrefresh;
3444 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3445 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3446 vrefresh = panel->downclock_mode->vrefresh;
3447 } else {
3448 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3449 drrs->refresh_rate_type);
3450 mutex_unlock(&drrs->mutex);
3451 return;
3452 }
3453 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3454
3455 seq_puts(m, "\n\t\t");
3456 mutex_unlock(&drrs->mutex);
3457 } else {
3458 /* DRRS not supported. Print the VBT parameter*/
3459 seq_puts(m, "\tDRRS Supported : No");
3460 }
3461 seq_puts(m, "\n");
3462}
3463
3464static int i915_drrs_status(struct seq_file *m, void *unused)
3465{
3466 struct drm_info_node *node = m->private;
3467 struct drm_device *dev = node->minor->dev;
3468 struct intel_crtc *intel_crtc;
3469 int active_crtc_cnt = 0;
3470
3471 drm_modeset_lock_all(dev);
3472 for_each_intel_crtc(dev, intel_crtc) {
3473 if (intel_crtc->base.state->active) {
3474 active_crtc_cnt++;
3475 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3476
3477 drrs_status_per_crtc(m, dev, intel_crtc);
3478 }
3479 }
3480 drm_modeset_unlock_all(dev);
3481
3482 if (!active_crtc_cnt)
3483 seq_puts(m, "No active crtc found\n");
3484
3485 return 0;
3486}
3487
3488struct pipe_crc_info {
3489 const char *name;
3490 struct drm_device *dev;
3491 enum pipe pipe;
3492};
3493
3494static int i915_dp_mst_info(struct seq_file *m, void *unused)
3495{
3496 struct drm_info_node *node = (struct drm_info_node *) m->private;
3497 struct drm_device *dev = node->minor->dev;
3498 struct intel_encoder *intel_encoder;
3499 struct intel_digital_port *intel_dig_port;
3500 struct drm_connector *connector;
3501
3502 drm_modeset_lock_all(dev);
3503 drm_for_each_connector(connector, dev) {
3504 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3505 continue;
3506
3507 intel_encoder = intel_attached_encoder(connector);
3508 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3509 continue;
3510
3511 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3512 if (!intel_dig_port->dp.can_mst)
3513 continue;
3514
3515 seq_printf(m, "MST Source Port %c\n",
3516 port_name(intel_dig_port->port));
3517 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3518 }
3519 drm_modeset_unlock_all(dev);
3520 return 0;
3521}
3522
3523static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3524{
3525 struct pipe_crc_info *info = inode->i_private;
3526 struct drm_i915_private *dev_priv = to_i915(info->dev);
3527 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3528
3529 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3530 return -ENODEV;
3531
3532 spin_lock_irq(&pipe_crc->lock);
3533
3534 if (pipe_crc->opened) {
3535 spin_unlock_irq(&pipe_crc->lock);
3536 return -EBUSY; /* already open */
3537 }
3538
3539 pipe_crc->opened = true;
3540 filep->private_data = inode->i_private;
3541
3542 spin_unlock_irq(&pipe_crc->lock);
3543
3544 return 0;
3545}
3546
3547static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3548{
3549 struct pipe_crc_info *info = inode->i_private;
3550 struct drm_i915_private *dev_priv = to_i915(info->dev);
3551 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3552
3553 spin_lock_irq(&pipe_crc->lock);
3554 pipe_crc->opened = false;
3555 spin_unlock_irq(&pipe_crc->lock);
3556
3557 return 0;
3558}
3559
3560/* (6 fields, 8 chars each, space separated (5) + '\n') */
3561#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3562/* account for \'0' */
3563#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3564
3565static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3566{
3567 assert_spin_locked(&pipe_crc->lock);
3568 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3569 INTEL_PIPE_CRC_ENTRIES_NR);
3570}
3571
3572static ssize_t
3573i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3574 loff_t *pos)
3575{
3576 struct pipe_crc_info *info = filep->private_data;
3577 struct drm_device *dev = info->dev;
3578 struct drm_i915_private *dev_priv = to_i915(dev);
3579 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3580 char buf[PIPE_CRC_BUFFER_LEN];
3581 int n_entries;
3582 ssize_t bytes_read;
3583
3584 /*
3585 * Don't allow user space to provide buffers not big enough to hold
3586 * a line of data.
3587 */
3588 if (count < PIPE_CRC_LINE_LEN)
3589 return -EINVAL;
3590
3591 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3592 return 0;
3593
3594 /* nothing to read */
3595 spin_lock_irq(&pipe_crc->lock);
3596 while (pipe_crc_data_count(pipe_crc) == 0) {
3597 int ret;
3598
3599 if (filep->f_flags & O_NONBLOCK) {
3600 spin_unlock_irq(&pipe_crc->lock);
3601 return -EAGAIN;
3602 }
3603
3604 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3605 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3606 if (ret) {
3607 spin_unlock_irq(&pipe_crc->lock);
3608 return ret;
3609 }
3610 }
3611
3612 /* We now have one or more entries to read */
3613 n_entries = count / PIPE_CRC_LINE_LEN;
3614
3615 bytes_read = 0;
3616 while (n_entries > 0) {
3617 struct intel_pipe_crc_entry *entry =
3618 &pipe_crc->entries[pipe_crc->tail];
3619 int ret;
3620
3621 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3622 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3623 break;
3624
3625 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3626 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3627
3628 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3629 "%8u %8x %8x %8x %8x %8x\n",
3630 entry->frame, entry->crc[0],
3631 entry->crc[1], entry->crc[2],
3632 entry->crc[3], entry->crc[4]);
3633
3634 spin_unlock_irq(&pipe_crc->lock);
3635
3636 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3637 if (ret == PIPE_CRC_LINE_LEN)
3638 return -EFAULT;
3639
3640 user_buf += PIPE_CRC_LINE_LEN;
3641 n_entries--;
3642
3643 spin_lock_irq(&pipe_crc->lock);
3644 }
3645
3646 spin_unlock_irq(&pipe_crc->lock);
3647
3648 return bytes_read;
3649}
3650
3651static const struct file_operations i915_pipe_crc_fops = {
3652 .owner = THIS_MODULE,
3653 .open = i915_pipe_crc_open,
3654 .read = i915_pipe_crc_read,
3655 .release = i915_pipe_crc_release,
3656};
3657
3658static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3659 {
3660 .name = "i915_pipe_A_crc",
3661 .pipe = PIPE_A,
3662 },
3663 {
3664 .name = "i915_pipe_B_crc",
3665 .pipe = PIPE_B,
3666 },
3667 {
3668 .name = "i915_pipe_C_crc",
3669 .pipe = PIPE_C,
3670 },
3671};
3672
3673static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3674 enum pipe pipe)
3675{
3676 struct drm_device *dev = minor->dev;
3677 struct dentry *ent;
3678 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3679
3680 info->dev = dev;
3681 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3682 &i915_pipe_crc_fops);
3683 if (!ent)
3684 return -ENOMEM;
3685
3686 return drm_add_fake_info_node(minor, ent, info);
3687}
3688
3689static const char * const pipe_crc_sources[] = {
3690 "none",
3691 "plane1",
3692 "plane2",
3693 "pf",
3694 "pipe",
3695 "TV",
3696 "DP-B",
3697 "DP-C",
3698 "DP-D",
3699 "auto",
3700};
3701
3702static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3703{
3704 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3705 return pipe_crc_sources[source];
3706}
3707
3708static int display_crc_ctl_show(struct seq_file *m, void *data)
3709{
3710 struct drm_device *dev = m->private;
3711 struct drm_i915_private *dev_priv = to_i915(dev);
3712 int i;
3713
3714 for (i = 0; i < I915_MAX_PIPES; i++)
3715 seq_printf(m, "%c %s\n", pipe_name(i),
3716 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3717
3718 return 0;
3719}
3720
3721static int display_crc_ctl_open(struct inode *inode, struct file *file)
3722{
3723 struct drm_device *dev = inode->i_private;
3724
3725 return single_open(file, display_crc_ctl_show, dev);
3726}
3727
3728static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3729 uint32_t *val)
3730{
3731 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3732 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3733
3734 switch (*source) {
3735 case INTEL_PIPE_CRC_SOURCE_PIPE:
3736 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3737 break;
3738 case INTEL_PIPE_CRC_SOURCE_NONE:
3739 *val = 0;
3740 break;
3741 default:
3742 return -EINVAL;
3743 }
3744
3745 return 0;
3746}
3747
3748static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3749 enum intel_pipe_crc_source *source)
3750{
3751 struct intel_encoder *encoder;
3752 struct intel_crtc *crtc;
3753 struct intel_digital_port *dig_port;
3754 int ret = 0;
3755
3756 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3757
3758 drm_modeset_lock_all(dev);
3759 for_each_intel_encoder(dev, encoder) {
3760 if (!encoder->base.crtc)
3761 continue;
3762
3763 crtc = to_intel_crtc(encoder->base.crtc);
3764
3765 if (crtc->pipe != pipe)
3766 continue;
3767
3768 switch (encoder->type) {
3769 case INTEL_OUTPUT_TVOUT:
3770 *source = INTEL_PIPE_CRC_SOURCE_TV;
3771 break;
3772 case INTEL_OUTPUT_DP:
3773 case INTEL_OUTPUT_EDP:
3774 dig_port = enc_to_dig_port(&encoder->base);
3775 switch (dig_port->port) {
3776 case PORT_B:
3777 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3778 break;
3779 case PORT_C:
3780 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3781 break;
3782 case PORT_D:
3783 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3784 break;
3785 default:
3786 WARN(1, "nonexisting DP port %c\n",
3787 port_name(dig_port->port));
3788 break;
3789 }
3790 break;
3791 default:
3792 break;
3793 }
3794 }
3795 drm_modeset_unlock_all(dev);
3796
3797 return ret;
3798}
3799
3800static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3801 enum pipe pipe,
3802 enum intel_pipe_crc_source *source,
3803 uint32_t *val)
3804{
3805 struct drm_i915_private *dev_priv = to_i915(dev);
3806 bool need_stable_symbols = false;
3807
3808 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3809 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3810 if (ret)
3811 return ret;
3812 }
3813
3814 switch (*source) {
3815 case INTEL_PIPE_CRC_SOURCE_PIPE:
3816 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3817 break;
3818 case INTEL_PIPE_CRC_SOURCE_DP_B:
3819 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3820 need_stable_symbols = true;
3821 break;
3822 case INTEL_PIPE_CRC_SOURCE_DP_C:
3823 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3824 need_stable_symbols = true;
3825 break;
3826 case INTEL_PIPE_CRC_SOURCE_DP_D:
3827 if (!IS_CHERRYVIEW(dev))
3828 return -EINVAL;
3829 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3830 need_stable_symbols = true;
3831 break;
3832 case INTEL_PIPE_CRC_SOURCE_NONE:
3833 *val = 0;
3834 break;
3835 default:
3836 return -EINVAL;
3837 }
3838
3839 /*
3840 * When the pipe CRC tap point is after the transcoders we need
3841 * to tweak symbol-level features to produce a deterministic series of
3842 * symbols for a given frame. We need to reset those features only once
3843 * a frame (instead of every nth symbol):
3844 * - DC-balance: used to ensure a better clock recovery from the data
3845 * link (SDVO)
3846 * - DisplayPort scrambling: used for EMI reduction
3847 */
3848 if (need_stable_symbols) {
3849 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3850
3851 tmp |= DC_BALANCE_RESET_VLV;
3852 switch (pipe) {
3853 case PIPE_A:
3854 tmp |= PIPE_A_SCRAMBLE_RESET;
3855 break;
3856 case PIPE_B:
3857 tmp |= PIPE_B_SCRAMBLE_RESET;
3858 break;
3859 case PIPE_C:
3860 tmp |= PIPE_C_SCRAMBLE_RESET;
3861 break;
3862 default:
3863 return -EINVAL;
3864 }
3865 I915_WRITE(PORT_DFT2_G4X, tmp);
3866 }
3867
3868 return 0;
3869}
3870
3871static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3872 enum pipe pipe,
3873 enum intel_pipe_crc_source *source,
3874 uint32_t *val)
3875{
3876 struct drm_i915_private *dev_priv = to_i915(dev);
3877 bool need_stable_symbols = false;
3878
3879 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3880 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3881 if (ret)
3882 return ret;
3883 }
3884
3885 switch (*source) {
3886 case INTEL_PIPE_CRC_SOURCE_PIPE:
3887 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3888 break;
3889 case INTEL_PIPE_CRC_SOURCE_TV:
3890 if (!SUPPORTS_TV(dev))
3891 return -EINVAL;
3892 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3893 break;
3894 case INTEL_PIPE_CRC_SOURCE_DP_B:
3895 if (!IS_G4X(dev))
3896 return -EINVAL;
3897 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3898 need_stable_symbols = true;
3899 break;
3900 case INTEL_PIPE_CRC_SOURCE_DP_C:
3901 if (!IS_G4X(dev))
3902 return -EINVAL;
3903 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3904 need_stable_symbols = true;
3905 break;
3906 case INTEL_PIPE_CRC_SOURCE_DP_D:
3907 if (!IS_G4X(dev))
3908 return -EINVAL;
3909 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3910 need_stable_symbols = true;
3911 break;
3912 case INTEL_PIPE_CRC_SOURCE_NONE:
3913 *val = 0;
3914 break;
3915 default:
3916 return -EINVAL;
3917 }
3918
3919 /*
3920 * When the pipe CRC tap point is after the transcoders we need
3921 * to tweak symbol-level features to produce a deterministic series of
3922 * symbols for a given frame. We need to reset those features only once
3923 * a frame (instead of every nth symbol):
3924 * - DC-balance: used to ensure a better clock recovery from the data
3925 * link (SDVO)
3926 * - DisplayPort scrambling: used for EMI reduction
3927 */
3928 if (need_stable_symbols) {
3929 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3930
3931 WARN_ON(!IS_G4X(dev));
3932
3933 I915_WRITE(PORT_DFT_I9XX,
3934 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3935
3936 if (pipe == PIPE_A)
3937 tmp |= PIPE_A_SCRAMBLE_RESET;
3938 else
3939 tmp |= PIPE_B_SCRAMBLE_RESET;
3940
3941 I915_WRITE(PORT_DFT2_G4X, tmp);
3942 }
3943
3944 return 0;
3945}
3946
3947static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3948 enum pipe pipe)
3949{
3950 struct drm_i915_private *dev_priv = to_i915(dev);
3951 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3952
3953 switch (pipe) {
3954 case PIPE_A:
3955 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3956 break;
3957 case PIPE_B:
3958 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3959 break;
3960 case PIPE_C:
3961 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3962 break;
3963 default:
3964 return;
3965 }
3966 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3967 tmp &= ~DC_BALANCE_RESET_VLV;
3968 I915_WRITE(PORT_DFT2_G4X, tmp);
3969
3970}
3971
3972static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3973 enum pipe pipe)
3974{
3975 struct drm_i915_private *dev_priv = to_i915(dev);
3976 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3977
3978 if (pipe == PIPE_A)
3979 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3980 else
3981 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3982 I915_WRITE(PORT_DFT2_G4X, tmp);
3983
3984 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3985 I915_WRITE(PORT_DFT_I9XX,
3986 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3987 }
3988}
3989
3990static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3991 uint32_t *val)
3992{
3993 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3994 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3995
3996 switch (*source) {
3997 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3998 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3999 break;
4000 case INTEL_PIPE_CRC_SOURCE_PLANE2:
4001 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
4002 break;
4003 case INTEL_PIPE_CRC_SOURCE_PIPE:
4004 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
4005 break;
4006 case INTEL_PIPE_CRC_SOURCE_NONE:
4007 *val = 0;
4008 break;
4009 default:
4010 return -EINVAL;
4011 }
4012
4013 return 0;
4014}
4015
4016static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
4017{
4018 struct drm_i915_private *dev_priv = to_i915(dev);
4019 struct intel_crtc *crtc =
4020 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
4021 struct intel_crtc_state *pipe_config;
4022 struct drm_atomic_state *state;
4023 int ret = 0;
4024
4025 drm_modeset_lock_all(dev);
4026 state = drm_atomic_state_alloc(dev);
4027 if (!state) {
4028 ret = -ENOMEM;
4029 goto out;
4030 }
4031
4032 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
4033 pipe_config = intel_atomic_get_crtc_state(state, crtc);
4034 if (IS_ERR(pipe_config)) {
4035 ret = PTR_ERR(pipe_config);
4036 goto out;
4037 }
4038
4039 pipe_config->pch_pfit.force_thru = enable;
4040 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
4041 pipe_config->pch_pfit.enabled != enable)
4042 pipe_config->base.connectors_changed = true;
4043
4044 ret = drm_atomic_commit(state);
4045out:
4046 drm_modeset_unlock_all(dev);
4047 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
4048 if (ret)
4049 drm_atomic_state_free(state);
4050}
4051
4052static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
4053 enum pipe pipe,
4054 enum intel_pipe_crc_source *source,
4055 uint32_t *val)
4056{
4057 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4058 *source = INTEL_PIPE_CRC_SOURCE_PF;
4059
4060 switch (*source) {
4061 case INTEL_PIPE_CRC_SOURCE_PLANE1:
4062 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4063 break;
4064 case INTEL_PIPE_CRC_SOURCE_PLANE2:
4065 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4066 break;
4067 case INTEL_PIPE_CRC_SOURCE_PF:
4068 if (IS_HASWELL(dev) && pipe == PIPE_A)
4069 hsw_trans_edp_pipe_A_crc_wa(dev, true);
4070
4071 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4072 break;
4073 case INTEL_PIPE_CRC_SOURCE_NONE:
4074 *val = 0;
4075 break;
4076 default:
4077 return -EINVAL;
4078 }
4079
4080 return 0;
4081}
4082
4083static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4084 enum intel_pipe_crc_source source)
4085{
4086 struct drm_i915_private *dev_priv = to_i915(dev);
4087 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4088 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4089 pipe));
4090 enum intel_display_power_domain power_domain;
4091 u32 val = 0; /* shut up gcc */
4092 int ret;
4093
4094 if (pipe_crc->source == source)
4095 return 0;
4096
4097 /* forbid changing the source without going back to 'none' */
4098 if (pipe_crc->source && source)
4099 return -EINVAL;
4100
4101 power_domain = POWER_DOMAIN_PIPE(pipe);
4102 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4103 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4104 return -EIO;
4105 }
4106
4107 if (IS_GEN2(dev))
4108 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4109 else if (INTEL_INFO(dev)->gen < 5)
4110 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4111 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4112 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4113 else if (IS_GEN5(dev) || IS_GEN6(dev))
4114 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4115 else
4116 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4117
4118 if (ret != 0)
4119 goto out;
4120
4121 /* none -> real source transition */
4122 if (source) {
4123 struct intel_pipe_crc_entry *entries;
4124
4125 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4126 pipe_name(pipe), pipe_crc_source_name(source));
4127
4128 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4129 sizeof(pipe_crc->entries[0]),
4130 GFP_KERNEL);
4131 if (!entries) {
4132 ret = -ENOMEM;
4133 goto out;
4134 }
4135
4136 /*
4137 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4138 * enabled and disabled dynamically based on package C states,
4139 * user space can't make reliable use of the CRCs, so let's just
4140 * completely disable it.
4141 */
4142 hsw_disable_ips(crtc);
4143
4144 spin_lock_irq(&pipe_crc->lock);
4145 kfree(pipe_crc->entries);
4146 pipe_crc->entries = entries;
4147 pipe_crc->head = 0;
4148 pipe_crc->tail = 0;
4149 spin_unlock_irq(&pipe_crc->lock);
4150 }
4151
4152 pipe_crc->source = source;
4153
4154 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4155 POSTING_READ(PIPE_CRC_CTL(pipe));
4156
4157 /* real source -> none transition */
4158 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4159 struct intel_pipe_crc_entry *entries;
4160 struct intel_crtc *crtc =
4161 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4162
4163 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4164 pipe_name(pipe));
4165
4166 drm_modeset_lock(&crtc->base.mutex, NULL);
4167 if (crtc->base.state->active)
4168 intel_wait_for_vblank(dev, pipe);
4169 drm_modeset_unlock(&crtc->base.mutex);
4170
4171 spin_lock_irq(&pipe_crc->lock);
4172 entries = pipe_crc->entries;
4173 pipe_crc->entries = NULL;
4174 pipe_crc->head = 0;
4175 pipe_crc->tail = 0;
4176 spin_unlock_irq(&pipe_crc->lock);
4177
4178 kfree(entries);
4179
4180 if (IS_G4X(dev))
4181 g4x_undo_pipe_scramble_reset(dev, pipe);
4182 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4183 vlv_undo_pipe_scramble_reset(dev, pipe);
4184 else if (IS_HASWELL(dev) && pipe == PIPE_A)
4185 hsw_trans_edp_pipe_A_crc_wa(dev, false);
4186
4187 hsw_enable_ips(crtc);
4188 }
4189
4190 ret = 0;
4191
4192out:
4193 intel_display_power_put(dev_priv, power_domain);
4194
4195 return ret;
4196}
4197
4198/*
4199 * Parse pipe CRC command strings:
4200 * command: wsp* object wsp+ name wsp+ source wsp*
4201 * object: 'pipe'
4202 * name: (A | B | C)
4203 * source: (none | plane1 | plane2 | pf)
4204 * wsp: (#0x20 | #0x9 | #0xA)+
4205 *
4206 * eg.:
4207 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4208 * "pipe A none" -> Stop CRC
4209 */
4210static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4211{
4212 int n_words = 0;
4213
4214 while (*buf) {
4215 char *end;
4216
4217 /* skip leading white space */
4218 buf = skip_spaces(buf);
4219 if (!*buf)
4220 break; /* end of buffer */
4221
4222 /* find end of word */
4223 for (end = buf; *end && !isspace(*end); end++)
4224 ;
4225
4226 if (n_words == max_words) {
4227 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4228 max_words);
4229 return -EINVAL; /* ran out of words[] before bytes */
4230 }
4231
4232 if (*end)
4233 *end++ = '\0';
4234 words[n_words++] = buf;
4235 buf = end;
4236 }
4237
4238 return n_words;
4239}
4240
4241enum intel_pipe_crc_object {
4242 PIPE_CRC_OBJECT_PIPE,
4243};
4244
4245static const char * const pipe_crc_objects[] = {
4246 "pipe",
4247};
4248
4249static int
4250display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4251{
4252 int i;
4253
4254 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4255 if (!strcmp(buf, pipe_crc_objects[i])) {
4256 *o = i;
4257 return 0;
4258 }
4259
4260 return -EINVAL;
4261}
4262
4263static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4264{
4265 const char name = buf[0];
4266
4267 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4268 return -EINVAL;
4269
4270 *pipe = name - 'A';
4271
4272 return 0;
4273}
4274
4275static int
4276display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4277{
4278 int i;
4279
4280 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4281 if (!strcmp(buf, pipe_crc_sources[i])) {
4282 *s = i;
4283 return 0;
4284 }
4285
4286 return -EINVAL;
4287}
4288
4289static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4290{
4291#define N_WORDS 3
4292 int n_words;
4293 char *words[N_WORDS];
4294 enum pipe pipe;
4295 enum intel_pipe_crc_object object;
4296 enum intel_pipe_crc_source source;
4297
4298 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4299 if (n_words != N_WORDS) {
4300 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4301 N_WORDS);
4302 return -EINVAL;
4303 }
4304
4305 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4306 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4307 return -EINVAL;
4308 }
4309
4310 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4311 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4312 return -EINVAL;
4313 }
4314
4315 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4316 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4317 return -EINVAL;
4318 }
4319
4320 return pipe_crc_set_source(dev, pipe, source);
4321}
4322
4323static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4324 size_t len, loff_t *offp)
4325{
4326 struct seq_file *m = file->private_data;
4327 struct drm_device *dev = m->private;
4328 char *tmpbuf;
4329 int ret;
4330
4331 if (len == 0)
4332 return 0;
4333
4334 if (len > PAGE_SIZE - 1) {
4335 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4336 PAGE_SIZE);
4337 return -E2BIG;
4338 }
4339
4340 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4341 if (!tmpbuf)
4342 return -ENOMEM;
4343
4344 if (copy_from_user(tmpbuf, ubuf, len)) {
4345 ret = -EFAULT;
4346 goto out;
4347 }
4348 tmpbuf[len] = '\0';
4349
4350 ret = display_crc_ctl_parse(dev, tmpbuf, len);
4351
4352out:
4353 kfree(tmpbuf);
4354 if (ret < 0)
4355 return ret;
4356
4357 *offp += len;
4358 return len;
4359}
4360
4361static const struct file_operations i915_display_crc_ctl_fops = {
4362 .owner = THIS_MODULE,
4363 .open = display_crc_ctl_open,
4364 .read = seq_read,
4365 .llseek = seq_lseek,
4366 .release = single_release,
4367 .write = display_crc_ctl_write
4368};
4369
4370static ssize_t i915_displayport_test_active_write(struct file *file,
4371 const char __user *ubuf,
4372 size_t len, loff_t *offp)
4373{
4374 char *input_buffer;
4375 int status = 0;
4376 struct drm_device *dev;
4377 struct drm_connector *connector;
4378 struct list_head *connector_list;
4379 struct intel_dp *intel_dp;
4380 int val = 0;
4381
4382 dev = ((struct seq_file *)file->private_data)->private;
4383
4384 connector_list = &dev->mode_config.connector_list;
4385
4386 if (len == 0)
4387 return 0;
4388
4389 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4390 if (!input_buffer)
4391 return -ENOMEM;
4392
4393 if (copy_from_user(input_buffer, ubuf, len)) {
4394 status = -EFAULT;
4395 goto out;
4396 }
4397
4398 input_buffer[len] = '\0';
4399 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4400
4401 list_for_each_entry(connector, connector_list, head) {
4402
4403 if (connector->connector_type !=
4404 DRM_MODE_CONNECTOR_DisplayPort)
4405 continue;
4406
4407 if (connector->status == connector_status_connected &&
4408 connector->encoder != NULL) {
4409 intel_dp = enc_to_intel_dp(connector->encoder);
4410 status = kstrtoint(input_buffer, 10, &val);
4411 if (status < 0)
4412 goto out;
4413 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4414 /* To prevent erroneous activation of the compliance
4415 * testing code, only accept an actual value of 1 here
4416 */
4417 if (val == 1)
4418 intel_dp->compliance_test_active = 1;
4419 else
4420 intel_dp->compliance_test_active = 0;
4421 }
4422 }
4423out:
4424 kfree(input_buffer);
4425 if (status < 0)
4426 return status;
4427
4428 *offp += len;
4429 return len;
4430}
4431
4432static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4433{
4434 struct drm_device *dev = m->private;
4435 struct drm_connector *connector;
4436 struct list_head *connector_list = &dev->mode_config.connector_list;
4437 struct intel_dp *intel_dp;
4438
4439 list_for_each_entry(connector, connector_list, head) {
4440
4441 if (connector->connector_type !=
4442 DRM_MODE_CONNECTOR_DisplayPort)
4443 continue;
4444
4445 if (connector->status == connector_status_connected &&
4446 connector->encoder != NULL) {
4447 intel_dp = enc_to_intel_dp(connector->encoder);
4448 if (intel_dp->compliance_test_active)
4449 seq_puts(m, "1");
4450 else
4451 seq_puts(m, "0");
4452 } else
4453 seq_puts(m, "0");
4454 }
4455
4456 return 0;
4457}
4458
4459static int i915_displayport_test_active_open(struct inode *inode,
4460 struct file *file)
4461{
4462 struct drm_device *dev = inode->i_private;
4463
4464 return single_open(file, i915_displayport_test_active_show, dev);
4465}
4466
4467static const struct file_operations i915_displayport_test_active_fops = {
4468 .owner = THIS_MODULE,
4469 .open = i915_displayport_test_active_open,
4470 .read = seq_read,
4471 .llseek = seq_lseek,
4472 .release = single_release,
4473 .write = i915_displayport_test_active_write
4474};
4475
4476static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4477{
4478 struct drm_device *dev = m->private;
4479 struct drm_connector *connector;
4480 struct list_head *connector_list = &dev->mode_config.connector_list;
4481 struct intel_dp *intel_dp;
4482
4483 list_for_each_entry(connector, connector_list, head) {
4484
4485 if (connector->connector_type !=
4486 DRM_MODE_CONNECTOR_DisplayPort)
4487 continue;
4488
4489 if (connector->status == connector_status_connected &&
4490 connector->encoder != NULL) {
4491 intel_dp = enc_to_intel_dp(connector->encoder);
4492 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4493 } else
4494 seq_puts(m, "0");
4495 }
4496
4497 return 0;
4498}
4499static int i915_displayport_test_data_open(struct inode *inode,
4500 struct file *file)
4501{
4502 struct drm_device *dev = inode->i_private;
4503
4504 return single_open(file, i915_displayport_test_data_show, dev);
4505}
4506
4507static const struct file_operations i915_displayport_test_data_fops = {
4508 .owner = THIS_MODULE,
4509 .open = i915_displayport_test_data_open,
4510 .read = seq_read,
4511 .llseek = seq_lseek,
4512 .release = single_release
4513};
4514
4515static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4516{
4517 struct drm_device *dev = m->private;
4518 struct drm_connector *connector;
4519 struct list_head *connector_list = &dev->mode_config.connector_list;
4520 struct intel_dp *intel_dp;
4521
4522 list_for_each_entry(connector, connector_list, head) {
4523
4524 if (connector->connector_type !=
4525 DRM_MODE_CONNECTOR_DisplayPort)
4526 continue;
4527
4528 if (connector->status == connector_status_connected &&
4529 connector->encoder != NULL) {
4530 intel_dp = enc_to_intel_dp(connector->encoder);
4531 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4532 } else
4533 seq_puts(m, "0");
4534 }
4535
4536 return 0;
4537}
4538
4539static int i915_displayport_test_type_open(struct inode *inode,
4540 struct file *file)
4541{
4542 struct drm_device *dev = inode->i_private;
4543
4544 return single_open(file, i915_displayport_test_type_show, dev);
4545}
4546
4547static const struct file_operations i915_displayport_test_type_fops = {
4548 .owner = THIS_MODULE,
4549 .open = i915_displayport_test_type_open,
4550 .read = seq_read,
4551 .llseek = seq_lseek,
4552 .release = single_release
4553};
4554
4555static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4556{
4557 struct drm_device *dev = m->private;
4558 int level;
4559 int num_levels;
4560
4561 if (IS_CHERRYVIEW(dev))
4562 num_levels = 3;
4563 else if (IS_VALLEYVIEW(dev))
4564 num_levels = 1;
4565 else
4566 num_levels = ilk_wm_max_level(dev) + 1;
4567
4568 drm_modeset_lock_all(dev);
4569
4570 for (level = 0; level < num_levels; level++) {
4571 unsigned int latency = wm[level];
4572
4573 /*
4574 * - WM1+ latency values in 0.5us units
4575 * - latencies are in us on gen9/vlv/chv
4576 */
4577 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4578 IS_CHERRYVIEW(dev))
4579 latency *= 10;
4580 else if (level > 0)
4581 latency *= 5;
4582
4583 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4584 level, wm[level], latency / 10, latency % 10);
4585 }
4586
4587 drm_modeset_unlock_all(dev);
4588}
4589
4590static int pri_wm_latency_show(struct seq_file *m, void *data)
4591{
4592 struct drm_device *dev = m->private;
4593 struct drm_i915_private *dev_priv = to_i915(dev);
4594 const uint16_t *latencies;
4595
4596 if (INTEL_INFO(dev)->gen >= 9)
4597 latencies = dev_priv->wm.skl_latency;
4598 else
4599 latencies = to_i915(dev)->wm.pri_latency;
4600
4601 wm_latency_show(m, latencies);
4602
4603 return 0;
4604}
4605
4606static int spr_wm_latency_show(struct seq_file *m, void *data)
4607{
4608 struct drm_device *dev = m->private;
4609 struct drm_i915_private *dev_priv = to_i915(dev);
4610 const uint16_t *latencies;
4611
4612 if (INTEL_INFO(dev)->gen >= 9)
4613 latencies = dev_priv->wm.skl_latency;
4614 else
4615 latencies = to_i915(dev)->wm.spr_latency;
4616
4617 wm_latency_show(m, latencies);
4618
4619 return 0;
4620}
4621
4622static int cur_wm_latency_show(struct seq_file *m, void *data)
4623{
4624 struct drm_device *dev = m->private;
4625 struct drm_i915_private *dev_priv = to_i915(dev);
4626 const uint16_t *latencies;
4627
4628 if (INTEL_INFO(dev)->gen >= 9)
4629 latencies = dev_priv->wm.skl_latency;
4630 else
4631 latencies = to_i915(dev)->wm.cur_latency;
4632
4633 wm_latency_show(m, latencies);
4634
4635 return 0;
4636}
4637
4638static int pri_wm_latency_open(struct inode *inode, struct file *file)
4639{
4640 struct drm_device *dev = inode->i_private;
4641
4642 if (INTEL_INFO(dev)->gen < 5)
4643 return -ENODEV;
4644
4645 return single_open(file, pri_wm_latency_show, dev);
4646}
4647
4648static int spr_wm_latency_open(struct inode *inode, struct file *file)
4649{
4650 struct drm_device *dev = inode->i_private;
4651
4652 if (HAS_GMCH_DISPLAY(dev))
4653 return -ENODEV;
4654
4655 return single_open(file, spr_wm_latency_show, dev);
4656}
4657
4658static int cur_wm_latency_open(struct inode *inode, struct file *file)
4659{
4660 struct drm_device *dev = inode->i_private;
4661
4662 if (HAS_GMCH_DISPLAY(dev))
4663 return -ENODEV;
4664
4665 return single_open(file, cur_wm_latency_show, dev);
4666}
4667
4668static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4669 size_t len, loff_t *offp, uint16_t wm[8])
4670{
4671 struct seq_file *m = file->private_data;
4672 struct drm_device *dev = m->private;
4673 uint16_t new[8] = { 0 };
4674 int num_levels;
4675 int level;
4676 int ret;
4677 char tmp[32];
4678
4679 if (IS_CHERRYVIEW(dev))
4680 num_levels = 3;
4681 else if (IS_VALLEYVIEW(dev))
4682 num_levels = 1;
4683 else
4684 num_levels = ilk_wm_max_level(dev) + 1;
4685
4686 if (len >= sizeof(tmp))
4687 return -EINVAL;
4688
4689 if (copy_from_user(tmp, ubuf, len))
4690 return -EFAULT;
4691
4692 tmp[len] = '\0';
4693
4694 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4695 &new[0], &new[1], &new[2], &new[3],
4696 &new[4], &new[5], &new[6], &new[7]);
4697 if (ret != num_levels)
4698 return -EINVAL;
4699
4700 drm_modeset_lock_all(dev);
4701
4702 for (level = 0; level < num_levels; level++)
4703 wm[level] = new[level];
4704
4705 drm_modeset_unlock_all(dev);
4706
4707 return len;
4708}
4709
4710
4711static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4712 size_t len, loff_t *offp)
4713{
4714 struct seq_file *m = file->private_data;
4715 struct drm_device *dev = m->private;
4716 struct drm_i915_private *dev_priv = to_i915(dev);
4717 uint16_t *latencies;
4718
4719 if (INTEL_INFO(dev)->gen >= 9)
4720 latencies = dev_priv->wm.skl_latency;
4721 else
4722 latencies = to_i915(dev)->wm.pri_latency;
4723
4724 return wm_latency_write(file, ubuf, len, offp, latencies);
4725}
4726
4727static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4728 size_t len, loff_t *offp)
4729{
4730 struct seq_file *m = file->private_data;
4731 struct drm_device *dev = m->private;
4732 struct drm_i915_private *dev_priv = to_i915(dev);
4733 uint16_t *latencies;
4734
4735 if (INTEL_INFO(dev)->gen >= 9)
4736 latencies = dev_priv->wm.skl_latency;
4737 else
4738 latencies = to_i915(dev)->wm.spr_latency;
4739
4740 return wm_latency_write(file, ubuf, len, offp, latencies);
4741}
4742
4743static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4744 size_t len, loff_t *offp)
4745{
4746 struct seq_file *m = file->private_data;
4747 struct drm_device *dev = m->private;
4748 struct drm_i915_private *dev_priv = to_i915(dev);
4749 uint16_t *latencies;
4750
4751 if (INTEL_INFO(dev)->gen >= 9)
4752 latencies = dev_priv->wm.skl_latency;
4753 else
4754 latencies = to_i915(dev)->wm.cur_latency;
4755
4756 return wm_latency_write(file, ubuf, len, offp, latencies);
4757}
4758
4759static const struct file_operations i915_pri_wm_latency_fops = {
4760 .owner = THIS_MODULE,
4761 .open = pri_wm_latency_open,
4762 .read = seq_read,
4763 .llseek = seq_lseek,
4764 .release = single_release,
4765 .write = pri_wm_latency_write
4766};
4767
4768static const struct file_operations i915_spr_wm_latency_fops = {
4769 .owner = THIS_MODULE,
4770 .open = spr_wm_latency_open,
4771 .read = seq_read,
4772 .llseek = seq_lseek,
4773 .release = single_release,
4774 .write = spr_wm_latency_write
4775};
4776
4777static const struct file_operations i915_cur_wm_latency_fops = {
4778 .owner = THIS_MODULE,
4779 .open = cur_wm_latency_open,
4780 .read = seq_read,
4781 .llseek = seq_lseek,
4782 .release = single_release,
4783 .write = cur_wm_latency_write
4784};
4785
4786static int
4787i915_wedged_get(void *data, u64 *val)
4788{
4789 struct drm_device *dev = data;
4790 struct drm_i915_private *dev_priv = to_i915(dev);
4791
4792 *val = i915_terminally_wedged(&dev_priv->gpu_error);
4793
4794 return 0;
4795}
4796
4797static int
4798i915_wedged_set(void *data, u64 val)
4799{
4800 struct drm_device *dev = data;
4801 struct drm_i915_private *dev_priv = to_i915(dev);
4802
4803 /*
4804 * There is no safeguard against this debugfs entry colliding
4805 * with the hangcheck calling same i915_handle_error() in
4806 * parallel, causing an explosion. For now we assume that the
4807 * test harness is responsible enough not to inject gpu hangs
4808 * while it is writing to 'i915_wedged'
4809 */
4810
4811 if (i915_reset_in_progress(&dev_priv->gpu_error))
4812 return -EAGAIN;
4813
4814 intel_runtime_pm_get(dev_priv);
4815
4816 i915_handle_error(dev_priv, val,
4817 "Manually setting wedged to %llu", val);
4818
4819 intel_runtime_pm_put(dev_priv);
4820
4821 return 0;
4822}
4823
4824DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4825 i915_wedged_get, i915_wedged_set,
4826 "%llu\n");
4827
4828static int
4829i915_ring_missed_irq_get(void *data, u64 *val)
4830{
4831 struct drm_device *dev = data;
4832 struct drm_i915_private *dev_priv = to_i915(dev);
4833
4834 *val = dev_priv->gpu_error.missed_irq_rings;
4835 return 0;
4836}
4837
4838static int
4839i915_ring_missed_irq_set(void *data, u64 val)
4840{
4841 struct drm_device *dev = data;
4842 struct drm_i915_private *dev_priv = to_i915(dev);
4843 int ret;
4844
4845 /* Lock against concurrent debugfs callers */
4846 ret = mutex_lock_interruptible(&dev->struct_mutex);
4847 if (ret)
4848 return ret;
4849 dev_priv->gpu_error.missed_irq_rings = val;
4850 mutex_unlock(&dev->struct_mutex);
4851
4852 return 0;
4853}
4854
4855DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4856 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4857 "0x%08llx\n");
4858
4859static int
4860i915_ring_test_irq_get(void *data, u64 *val)
4861{
4862 struct drm_device *dev = data;
4863 struct drm_i915_private *dev_priv = to_i915(dev);
4864
4865 *val = dev_priv->gpu_error.test_irq_rings;
4866
4867 return 0;
4868}
4869
4870static int
4871i915_ring_test_irq_set(void *data, u64 val)
4872{
4873 struct drm_device *dev = data;
4874 struct drm_i915_private *dev_priv = to_i915(dev);
4875
4876 val &= INTEL_INFO(dev_priv)->ring_mask;
4877 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4878 dev_priv->gpu_error.test_irq_rings = val;
4879
4880 return 0;
4881}
4882
4883DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4884 i915_ring_test_irq_get, i915_ring_test_irq_set,
4885 "0x%08llx\n");
4886
4887#define DROP_UNBOUND 0x1
4888#define DROP_BOUND 0x2
4889#define DROP_RETIRE 0x4
4890#define DROP_ACTIVE 0x8
4891#define DROP_ALL (DROP_UNBOUND | \
4892 DROP_BOUND | \
4893 DROP_RETIRE | \
4894 DROP_ACTIVE)
4895static int
4896i915_drop_caches_get(void *data, u64 *val)
4897{
4898 *val = DROP_ALL;
4899
4900 return 0;
4901}
4902
4903static int
4904i915_drop_caches_set(void *data, u64 val)
4905{
4906 struct drm_device *dev = data;
4907 struct drm_i915_private *dev_priv = to_i915(dev);
4908 int ret;
4909
4910 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4911
4912 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4913 * on ioctls on -EAGAIN. */
4914 ret = mutex_lock_interruptible(&dev->struct_mutex);
4915 if (ret)
4916 return ret;
4917
4918 if (val & DROP_ACTIVE) {
4919 ret = i915_gem_wait_for_idle(dev_priv);
4920 if (ret)
4921 goto unlock;
4922 }
4923
4924 if (val & (DROP_RETIRE | DROP_ACTIVE))
4925 i915_gem_retire_requests(dev_priv);
4926
4927 if (val & DROP_BOUND)
4928 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4929
4930 if (val & DROP_UNBOUND)
4931 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4932
4933unlock:
4934 mutex_unlock(&dev->struct_mutex);
4935
4936 return ret;
4937}
4938
4939DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4940 i915_drop_caches_get, i915_drop_caches_set,
4941 "0x%08llx\n");
4942
4943static int
4944i915_max_freq_get(void *data, u64 *val)
4945{
4946 struct drm_device *dev = data;
4947 struct drm_i915_private *dev_priv = to_i915(dev);
4948
4949 if (INTEL_INFO(dev)->gen < 6)
4950 return -ENODEV;
4951
4952 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4953 return 0;
4954}
4955
4956static int
4957i915_max_freq_set(void *data, u64 val)
4958{
4959 struct drm_device *dev = data;
4960 struct drm_i915_private *dev_priv = to_i915(dev);
4961 u32 hw_max, hw_min;
4962 int ret;
4963
4964 if (INTEL_INFO(dev)->gen < 6)
4965 return -ENODEV;
4966
4967 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4968
4969 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4970 if (ret)
4971 return ret;
4972
4973 /*
4974 * Turbo will still be enabled, but won't go above the set value.
4975 */
4976 val = intel_freq_opcode(dev_priv, val);
4977
4978 hw_max = dev_priv->rps.max_freq;
4979 hw_min = dev_priv->rps.min_freq;
4980
4981 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4982 mutex_unlock(&dev_priv->rps.hw_lock);
4983 return -EINVAL;
4984 }
4985
4986 dev_priv->rps.max_freq_softlimit = val;
4987
4988 intel_set_rps(dev_priv, val);
4989
4990 mutex_unlock(&dev_priv->rps.hw_lock);
4991
4992 return 0;
4993}
4994
4995DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4996 i915_max_freq_get, i915_max_freq_set,
4997 "%llu\n");
4998
4999static int
5000i915_min_freq_get(void *data, u64 *val)
5001{
5002 struct drm_device *dev = data;
5003 struct drm_i915_private *dev_priv = to_i915(dev);
5004
5005 if (INTEL_GEN(dev_priv) < 6)
5006 return -ENODEV;
5007
5008 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
5009 return 0;
5010}
5011
5012static int
5013i915_min_freq_set(void *data, u64 val)
5014{
5015 struct drm_device *dev = data;
5016 struct drm_i915_private *dev_priv = to_i915(dev);
5017 u32 hw_max, hw_min;
5018 int ret;
5019
5020 if (INTEL_GEN(dev_priv) < 6)
5021 return -ENODEV;
5022
5023 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5024
5025 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5026 if (ret)
5027 return ret;
5028
5029 /*
5030 * Turbo will still be enabled, but won't go below the set value.
5031 */
5032 val = intel_freq_opcode(dev_priv, val);
5033
5034 hw_max = dev_priv->rps.max_freq;
5035 hw_min = dev_priv->rps.min_freq;
5036
5037 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5038 mutex_unlock(&dev_priv->rps.hw_lock);
5039 return -EINVAL;
5040 }
5041
5042 dev_priv->rps.min_freq_softlimit = val;
5043
5044 intel_set_rps(dev_priv, val);
5045
5046 mutex_unlock(&dev_priv->rps.hw_lock);
5047
5048 return 0;
5049}
5050
5051DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5052 i915_min_freq_get, i915_min_freq_set,
5053 "%llu\n");
5054
5055static int
5056i915_cache_sharing_get(void *data, u64 *val)
5057{
5058 struct drm_device *dev = data;
5059 struct drm_i915_private *dev_priv = to_i915(dev);
5060 u32 snpcr;
5061 int ret;
5062
5063 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5064 return -ENODEV;
5065
5066 ret = mutex_lock_interruptible(&dev->struct_mutex);
5067 if (ret)
5068 return ret;
5069 intel_runtime_pm_get(dev_priv);
5070
5071 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5072
5073 intel_runtime_pm_put(dev_priv);
5074 mutex_unlock(&dev_priv->drm.struct_mutex);
5075
5076 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5077
5078 return 0;
5079}
5080
5081static int
5082i915_cache_sharing_set(void *data, u64 val)
5083{
5084 struct drm_device *dev = data;
5085 struct drm_i915_private *dev_priv = to_i915(dev);
5086 u32 snpcr;
5087
5088 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5089 return -ENODEV;
5090
5091 if (val > 3)
5092 return -EINVAL;
5093
5094 intel_runtime_pm_get(dev_priv);
5095 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5096
5097 /* Update the cache sharing policy here as well */
5098 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5099 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5100 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5101 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5102
5103 intel_runtime_pm_put(dev_priv);
5104 return 0;
5105}
5106
5107DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5108 i915_cache_sharing_get, i915_cache_sharing_set,
5109 "%llu\n");
5110
5111struct sseu_dev_status {
5112 unsigned int slice_total;
5113 unsigned int subslice_total;
5114 unsigned int subslice_per_slice;
5115 unsigned int eu_total;
5116 unsigned int eu_per_subslice;
5117};
5118
5119static void cherryview_sseu_device_status(struct drm_device *dev,
5120 struct sseu_dev_status *stat)
5121{
5122 struct drm_i915_private *dev_priv = to_i915(dev);
5123 int ss_max = 2;
5124 int ss;
5125 u32 sig1[ss_max], sig2[ss_max];
5126
5127 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5128 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5129 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5130 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5131
5132 for (ss = 0; ss < ss_max; ss++) {
5133 unsigned int eu_cnt;
5134
5135 if (sig1[ss] & CHV_SS_PG_ENABLE)
5136 /* skip disabled subslice */
5137 continue;
5138
5139 stat->slice_total = 1;
5140 stat->subslice_per_slice++;
5141 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5142 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5143 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5144 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5145 stat->eu_total += eu_cnt;
5146 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5147 }
5148 stat->subslice_total = stat->subslice_per_slice;
5149}
5150
5151static void gen9_sseu_device_status(struct drm_device *dev,
5152 struct sseu_dev_status *stat)
5153{
5154 struct drm_i915_private *dev_priv = to_i915(dev);
5155 int s_max = 3, ss_max = 4;
5156 int s, ss;
5157 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5158
5159 /* BXT has a single slice and at most 3 subslices. */
5160 if (IS_BROXTON(dev)) {
5161 s_max = 1;
5162 ss_max = 3;
5163 }
5164
5165 for (s = 0; s < s_max; s++) {
5166 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5167 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5168 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5169 }
5170
5171 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5172 GEN9_PGCTL_SSA_EU19_ACK |
5173 GEN9_PGCTL_SSA_EU210_ACK |
5174 GEN9_PGCTL_SSA_EU311_ACK;
5175 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5176 GEN9_PGCTL_SSB_EU19_ACK |
5177 GEN9_PGCTL_SSB_EU210_ACK |
5178 GEN9_PGCTL_SSB_EU311_ACK;
5179
5180 for (s = 0; s < s_max; s++) {
5181 unsigned int ss_cnt = 0;
5182
5183 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5184 /* skip disabled slice */
5185 continue;
5186
5187 stat->slice_total++;
5188
5189 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5190 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5191
5192 for (ss = 0; ss < ss_max; ss++) {
5193 unsigned int eu_cnt;
5194
5195 if (IS_BROXTON(dev) &&
5196 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5197 /* skip disabled subslice */
5198 continue;
5199
5200 if (IS_BROXTON(dev))
5201 ss_cnt++;
5202
5203 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5204 eu_mask[ss%2]);
5205 stat->eu_total += eu_cnt;
5206 stat->eu_per_subslice = max(stat->eu_per_subslice,
5207 eu_cnt);
5208 }
5209
5210 stat->subslice_total += ss_cnt;
5211 stat->subslice_per_slice = max(stat->subslice_per_slice,
5212 ss_cnt);
5213 }
5214}
5215
5216static void broadwell_sseu_device_status(struct drm_device *dev,
5217 struct sseu_dev_status *stat)
5218{
5219 struct drm_i915_private *dev_priv = to_i915(dev);
5220 int s;
5221 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5222
5223 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5224
5225 if (stat->slice_total) {
5226 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5227 stat->subslice_total = stat->slice_total *
5228 stat->subslice_per_slice;
5229 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5230 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5231
5232 /* subtract fused off EU(s) from enabled slice(s) */
5233 for (s = 0; s < stat->slice_total; s++) {
5234 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5235
5236 stat->eu_total -= hweight8(subslice_7eu);
5237 }
5238 }
5239}
5240
5241static int i915_sseu_status(struct seq_file *m, void *unused)
5242{
5243 struct drm_info_node *node = (struct drm_info_node *) m->private;
5244 struct drm_i915_private *dev_priv = to_i915(node->minor->dev);
5245 struct drm_device *dev = &dev_priv->drm;
5246 struct sseu_dev_status stat;
5247
5248 if (INTEL_INFO(dev)->gen < 8)
5249 return -ENODEV;
5250
5251 seq_puts(m, "SSEU Device Info\n");
5252 seq_printf(m, " Available Slice Total: %u\n",
5253 INTEL_INFO(dev)->slice_total);
5254 seq_printf(m, " Available Subslice Total: %u\n",
5255 INTEL_INFO(dev)->subslice_total);
5256 seq_printf(m, " Available Subslice Per Slice: %u\n",
5257 INTEL_INFO(dev)->subslice_per_slice);
5258 seq_printf(m, " Available EU Total: %u\n",
5259 INTEL_INFO(dev)->eu_total);
5260 seq_printf(m, " Available EU Per Subslice: %u\n",
5261 INTEL_INFO(dev)->eu_per_subslice);
5262 seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev)));
5263 if (HAS_POOLED_EU(dev))
5264 seq_printf(m, " Min EU in pool: %u\n",
5265 INTEL_INFO(dev)->min_eu_in_pool);
5266 seq_printf(m, " Has Slice Power Gating: %s\n",
5267 yesno(INTEL_INFO(dev)->has_slice_pg));
5268 seq_printf(m, " Has Subslice Power Gating: %s\n",
5269 yesno(INTEL_INFO(dev)->has_subslice_pg));
5270 seq_printf(m, " Has EU Power Gating: %s\n",
5271 yesno(INTEL_INFO(dev)->has_eu_pg));
5272
5273 seq_puts(m, "SSEU Device Status\n");
5274 memset(&stat, 0, sizeof(stat));
5275
5276 intel_runtime_pm_get(dev_priv);
5277
5278 if (IS_CHERRYVIEW(dev)) {
5279 cherryview_sseu_device_status(dev, &stat);
5280 } else if (IS_BROADWELL(dev)) {
5281 broadwell_sseu_device_status(dev, &stat);
5282 } else if (INTEL_INFO(dev)->gen >= 9) {
5283 gen9_sseu_device_status(dev, &stat);
5284 }
5285
5286 intel_runtime_pm_put(dev_priv);
5287
5288 seq_printf(m, " Enabled Slice Total: %u\n",
5289 stat.slice_total);
5290 seq_printf(m, " Enabled Subslice Total: %u\n",
5291 stat.subslice_total);
5292 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5293 stat.subslice_per_slice);
5294 seq_printf(m, " Enabled EU Total: %u\n",
5295 stat.eu_total);
5296 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5297 stat.eu_per_subslice);
5298
5299 return 0;
5300}
5301
5302static int i915_forcewake_open(struct inode *inode, struct file *file)
5303{
5304 struct drm_device *dev = inode->i_private;
5305 struct drm_i915_private *dev_priv = to_i915(dev);
5306
5307 if (INTEL_INFO(dev)->gen < 6)
5308 return 0;
5309
5310 intel_runtime_pm_get(dev_priv);
5311 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5312
5313 return 0;
5314}
5315
5316static int i915_forcewake_release(struct inode *inode, struct file *file)
5317{
5318 struct drm_device *dev = inode->i_private;
5319 struct drm_i915_private *dev_priv = to_i915(dev);
5320
5321 if (INTEL_INFO(dev)->gen < 6)
5322 return 0;
5323
5324 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5325 intel_runtime_pm_put(dev_priv);
5326
5327 return 0;
5328}
5329
5330static const struct file_operations i915_forcewake_fops = {
5331 .owner = THIS_MODULE,
5332 .open = i915_forcewake_open,
5333 .release = i915_forcewake_release,
5334};
5335
5336static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5337{
5338 struct drm_device *dev = minor->dev;
5339 struct dentry *ent;
5340
5341 ent = debugfs_create_file("i915_forcewake_user",
5342 S_IRUSR,
5343 root, dev,
5344 &i915_forcewake_fops);
5345 if (!ent)
5346 return -ENOMEM;
5347
5348 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5349}
5350
5351static int i915_debugfs_create(struct dentry *root,
5352 struct drm_minor *minor,
5353 const char *name,
5354 const struct file_operations *fops)
5355{
5356 struct drm_device *dev = minor->dev;
5357 struct dentry *ent;
5358
5359 ent = debugfs_create_file(name,
5360 S_IRUGO | S_IWUSR,
5361 root, dev,
5362 fops);
5363 if (!ent)
5364 return -ENOMEM;
5365
5366 return drm_add_fake_info_node(minor, ent, fops);
5367}
5368
5369static const struct drm_info_list i915_debugfs_list[] = {
5370 {"i915_capabilities", i915_capabilities, 0},
5371 {"i915_gem_objects", i915_gem_object_info, 0},
5372 {"i915_gem_gtt", i915_gem_gtt_info, 0},
5373 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5374 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5375 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5376 {"i915_gem_stolen", i915_gem_stolen_list_info },
5377 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5378 {"i915_gem_request", i915_gem_request_info, 0},
5379 {"i915_gem_seqno", i915_gem_seqno_info, 0},
5380 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5381 {"i915_gem_interrupt", i915_interrupt_info, 0},
5382 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5383 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5384 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5385 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5386 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5387 {"i915_guc_info", i915_guc_info, 0},
5388 {"i915_guc_load_status", i915_guc_load_status_info, 0},
5389 {"i915_guc_log_dump", i915_guc_log_dump, 0},
5390 {"i915_frequency_info", i915_frequency_info, 0},
5391 {"i915_hangcheck_info", i915_hangcheck_info, 0},
5392 {"i915_drpc_info", i915_drpc_info, 0},
5393 {"i915_emon_status", i915_emon_status, 0},
5394 {"i915_ring_freq_table", i915_ring_freq_table, 0},
5395 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5396 {"i915_fbc_status", i915_fbc_status, 0},
5397 {"i915_ips_status", i915_ips_status, 0},
5398 {"i915_sr_status", i915_sr_status, 0},
5399 {"i915_opregion", i915_opregion, 0},
5400 {"i915_vbt", i915_vbt, 0},
5401 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5402 {"i915_context_status", i915_context_status, 0},
5403 {"i915_dump_lrc", i915_dump_lrc, 0},
5404 {"i915_execlists", i915_execlists, 0},
5405 {"i915_forcewake_domains", i915_forcewake_domains, 0},
5406 {"i915_swizzle_info", i915_swizzle_info, 0},
5407 {"i915_ppgtt_info", i915_ppgtt_info, 0},
5408 {"i915_llc", i915_llc, 0},
5409 {"i915_edp_psr_status", i915_edp_psr_status, 0},
5410 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5411 {"i915_energy_uJ", i915_energy_uJ, 0},
5412 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5413 {"i915_power_domain_info", i915_power_domain_info, 0},
5414 {"i915_dmc_info", i915_dmc_info, 0},
5415 {"i915_display_info", i915_display_info, 0},
5416 {"i915_semaphore_status", i915_semaphore_status, 0},
5417 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5418 {"i915_dp_mst_info", i915_dp_mst_info, 0},
5419 {"i915_wa_registers", i915_wa_registers, 0},
5420 {"i915_ddb_info", i915_ddb_info, 0},
5421 {"i915_sseu_status", i915_sseu_status, 0},
5422 {"i915_drrs_status", i915_drrs_status, 0},
5423 {"i915_rps_boost_info", i915_rps_boost_info, 0},
5424};
5425#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5426
5427static const struct i915_debugfs_files {
5428 const char *name;
5429 const struct file_operations *fops;
5430} i915_debugfs_files[] = {
5431 {"i915_wedged", &i915_wedged_fops},
5432 {"i915_max_freq", &i915_max_freq_fops},
5433 {"i915_min_freq", &i915_min_freq_fops},
5434 {"i915_cache_sharing", &i915_cache_sharing_fops},
5435 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5436 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5437 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5438 {"i915_error_state", &i915_error_state_fops},
5439 {"i915_next_seqno", &i915_next_seqno_fops},
5440 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5441 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5442 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5443 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5444 {"i915_fbc_false_color", &i915_fbc_fc_fops},
5445 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5446 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5447 {"i915_dp_test_active", &i915_displayport_test_active_fops}
5448};
5449
5450void intel_display_crc_init(struct drm_device *dev)
5451{
5452 struct drm_i915_private *dev_priv = to_i915(dev);
5453 enum pipe pipe;
5454
5455 for_each_pipe(dev_priv, pipe) {
5456 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5457
5458 pipe_crc->opened = false;
5459 spin_lock_init(&pipe_crc->lock);
5460 init_waitqueue_head(&pipe_crc->wq);
5461 }
5462}
5463
5464int i915_debugfs_register(struct drm_i915_private *dev_priv)
5465{
5466 struct drm_minor *minor = dev_priv->drm.primary;
5467 int ret, i;
5468
5469 ret = i915_forcewake_create(minor->debugfs_root, minor);
5470 if (ret)
5471 return ret;
5472
5473 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5474 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5475 if (ret)
5476 return ret;
5477 }
5478
5479 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5480 ret = i915_debugfs_create(minor->debugfs_root, minor,
5481 i915_debugfs_files[i].name,
5482 i915_debugfs_files[i].fops);
5483 if (ret)
5484 return ret;
5485 }
5486
5487 return drm_debugfs_create_files(i915_debugfs_list,
5488 I915_DEBUGFS_ENTRIES,
5489 minor->debugfs_root, minor);
5490}
5491
5492void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
5493{
5494 struct drm_minor *minor = dev_priv->drm.primary;
5495 int i;
5496
5497 drm_debugfs_remove_files(i915_debugfs_list,
5498 I915_DEBUGFS_ENTRIES, minor);
5499
5500 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5501 1, minor);
5502
5503 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5504 struct drm_info_list *info_list =
5505 (struct drm_info_list *)&i915_pipe_crc_data[i];
5506
5507 drm_debugfs_remove_files(info_list, 1, minor);
5508 }
5509
5510 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5511 struct drm_info_list *info_list =
5512 (struct drm_info_list *) i915_debugfs_files[i].fops;
5513
5514 drm_debugfs_remove_files(info_list, 1, minor);
5515 }
5516}
5517
5518struct dpcd_block {
5519 /* DPCD dump start address. */
5520 unsigned int offset;
5521 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5522 unsigned int end;
5523 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5524 size_t size;
5525 /* Only valid for eDP. */
5526 bool edp;
5527};
5528
5529static const struct dpcd_block i915_dpcd_debug[] = {
5530 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5531 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5532 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5533 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5534 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5535 { .offset = DP_SET_POWER },
5536 { .offset = DP_EDP_DPCD_REV },
5537 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5538 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5539 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5540};
5541
5542static int i915_dpcd_show(struct seq_file *m, void *data)
5543{
5544 struct drm_connector *connector = m->private;
5545 struct intel_dp *intel_dp =
5546 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5547 uint8_t buf[16];
5548 ssize_t err;
5549 int i;
5550
5551 if (connector->status != connector_status_connected)
5552 return -ENODEV;
5553
5554 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5555 const struct dpcd_block *b = &i915_dpcd_debug[i];
5556 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5557
5558 if (b->edp &&
5559 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5560 continue;
5561
5562 /* low tech for now */
5563 if (WARN_ON(size > sizeof(buf)))
5564 continue;
5565
5566 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5567 if (err <= 0) {
5568 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5569 size, b->offset, err);
5570 continue;
5571 }
5572
5573 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5574 }
5575
5576 return 0;
5577}
5578
5579static int i915_dpcd_open(struct inode *inode, struct file *file)
5580{
5581 return single_open(file, i915_dpcd_show, inode->i_private);
5582}
5583
5584static const struct file_operations i915_dpcd_fops = {
5585 .owner = THIS_MODULE,
5586 .open = i915_dpcd_open,
5587 .read = seq_read,
5588 .llseek = seq_lseek,
5589 .release = single_release,
5590};
5591
5592/**
5593 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5594 * @connector: pointer to a registered drm_connector
5595 *
5596 * Cleanup will be done by drm_connector_unregister() through a call to
5597 * drm_debugfs_connector_remove().
5598 *
5599 * Returns 0 on success, negative error codes on error.
5600 */
5601int i915_debugfs_connector_add(struct drm_connector *connector)
5602{
5603 struct dentry *root = connector->debugfs_entry;
5604
5605 /* The connector must have been registered beforehands. */
5606 if (!root)
5607 return -ENODEV;
5608
5609 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5610 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5611 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5612 &i915_dpcd_fops);
5613
5614 return 0;
5615}
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