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drm/i915: rename VLV IOSF sideband functions logically
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_debugfs.c
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1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
30#include <linux/debugfs.h>
31#include <linux/slab.h>
32#include <linux/export.h>
33#include <generated/utsrelease.h>
34#include <drm/drmP.h>
35#include "intel_drv.h"
36#include "intel_ringbuffer.h"
37#include <drm/i915_drm.h>
38#include "i915_drv.h"
39
40#define DRM_I915_RING_DEBUG 1
41
42
43#if defined(CONFIG_DEBUG_FS)
44
45enum {
46 ACTIVE_LIST,
47 INACTIVE_LIST,
48 PINNED_LIST,
49};
50
51static const char *yesno(int v)
52{
53 return v ? "yes" : "no";
54}
55
56static int i915_capabilities(struct seq_file *m, void *data)
57{
58 struct drm_info_node *node = (struct drm_info_node *) m->private;
59 struct drm_device *dev = node->minor->dev;
60 const struct intel_device_info *info = INTEL_INFO(dev);
61
62 seq_printf(m, "gen: %d\n", info->gen);
63 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
64#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
65#define SEP_SEMICOLON ;
66 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
67#undef PRINT_FLAG
68#undef SEP_SEMICOLON
69
70 return 0;
71}
72
73static const char *get_pin_flag(struct drm_i915_gem_object *obj)
74{
75 if (obj->user_pin_count > 0)
76 return "P";
77 else if (obj->pin_count > 0)
78 return "p";
79 else
80 return " ";
81}
82
83static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
84{
85 switch (obj->tiling_mode) {
86 default:
87 case I915_TILING_NONE: return " ";
88 case I915_TILING_X: return "X";
89 case I915_TILING_Y: return "Y";
90 }
91}
92
93static const char *cache_level_str(int type)
94{
95 switch (type) {
96 case I915_CACHE_NONE: return " uncached";
97 case I915_CACHE_LLC: return " snooped (LLC)";
98 case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
99 default: return "";
100 }
101}
102
103static void
104describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
105{
106 seq_printf(m, "%pK: %s%s %8zdKiB %02x %02x %d %d %d%s%s%s",
107 &obj->base,
108 get_pin_flag(obj),
109 get_tiling_flag(obj),
110 obj->base.size / 1024,
111 obj->base.read_domains,
112 obj->base.write_domain,
113 obj->last_read_seqno,
114 obj->last_write_seqno,
115 obj->last_fenced_seqno,
116 cache_level_str(obj->cache_level),
117 obj->dirty ? " dirty" : "",
118 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
119 if (obj->base.name)
120 seq_printf(m, " (name: %d)", obj->base.name);
121 if (obj->pin_count)
122 seq_printf(m, " (pinned x %d)", obj->pin_count);
123 if (obj->fence_reg != I915_FENCE_REG_NONE)
124 seq_printf(m, " (fence: %d)", obj->fence_reg);
125 if (obj->gtt_space != NULL)
126 seq_printf(m, " (gtt offset: %08x, size: %08x)",
127 obj->gtt_offset, (unsigned int)obj->gtt_space->size);
128 if (obj->stolen)
129 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
130 if (obj->pin_mappable || obj->fault_mappable) {
131 char s[3], *t = s;
132 if (obj->pin_mappable)
133 *t++ = 'p';
134 if (obj->fault_mappable)
135 *t++ = 'f';
136 *t = '\0';
137 seq_printf(m, " (%s mappable)", s);
138 }
139 if (obj->ring != NULL)
140 seq_printf(m, " (%s)", obj->ring->name);
141}
142
143static int i915_gem_object_list_info(struct seq_file *m, void *data)
144{
145 struct drm_info_node *node = (struct drm_info_node *) m->private;
146 uintptr_t list = (uintptr_t) node->info_ent->data;
147 struct list_head *head;
148 struct drm_device *dev = node->minor->dev;
149 drm_i915_private_t *dev_priv = dev->dev_private;
150 struct drm_i915_gem_object *obj;
151 size_t total_obj_size, total_gtt_size;
152 int count, ret;
153
154 ret = mutex_lock_interruptible(&dev->struct_mutex);
155 if (ret)
156 return ret;
157
158 switch (list) {
159 case ACTIVE_LIST:
160 seq_printf(m, "Active:\n");
161 head = &dev_priv->mm.active_list;
162 break;
163 case INACTIVE_LIST:
164 seq_printf(m, "Inactive:\n");
165 head = &dev_priv->mm.inactive_list;
166 break;
167 default:
168 mutex_unlock(&dev->struct_mutex);
169 return -EINVAL;
170 }
171
172 total_obj_size = total_gtt_size = count = 0;
173 list_for_each_entry(obj, head, mm_list) {
174 seq_printf(m, " ");
175 describe_obj(m, obj);
176 seq_printf(m, "\n");
177 total_obj_size += obj->base.size;
178 total_gtt_size += obj->gtt_space->size;
179 count++;
180 }
181 mutex_unlock(&dev->struct_mutex);
182
183 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
184 count, total_obj_size, total_gtt_size);
185 return 0;
186}
187
188#define count_objects(list, member) do { \
189 list_for_each_entry(obj, list, member) { \
190 size += obj->gtt_space->size; \
191 ++count; \
192 if (obj->map_and_fenceable) { \
193 mappable_size += obj->gtt_space->size; \
194 ++mappable_count; \
195 } \
196 } \
197} while (0)
198
199static int i915_gem_object_info(struct seq_file *m, void* data)
200{
201 struct drm_info_node *node = (struct drm_info_node *) m->private;
202 struct drm_device *dev = node->minor->dev;
203 struct drm_i915_private *dev_priv = dev->dev_private;
204 u32 count, mappable_count, purgeable_count;
205 size_t size, mappable_size, purgeable_size;
206 struct drm_i915_gem_object *obj;
207 int ret;
208
209 ret = mutex_lock_interruptible(&dev->struct_mutex);
210 if (ret)
211 return ret;
212
213 seq_printf(m, "%u objects, %zu bytes\n",
214 dev_priv->mm.object_count,
215 dev_priv->mm.object_memory);
216
217 size = count = mappable_size = mappable_count = 0;
218 count_objects(&dev_priv->mm.bound_list, gtt_list);
219 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
220 count, mappable_count, size, mappable_size);
221
222 size = count = mappable_size = mappable_count = 0;
223 count_objects(&dev_priv->mm.active_list, mm_list);
224 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
225 count, mappable_count, size, mappable_size);
226
227 size = count = mappable_size = mappable_count = 0;
228 count_objects(&dev_priv->mm.inactive_list, mm_list);
229 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
230 count, mappable_count, size, mappable_size);
231
232 size = count = purgeable_size = purgeable_count = 0;
233 list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) {
234 size += obj->base.size, ++count;
235 if (obj->madv == I915_MADV_DONTNEED)
236 purgeable_size += obj->base.size, ++purgeable_count;
237 }
238 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
239
240 size = count = mappable_size = mappable_count = 0;
241 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
242 if (obj->fault_mappable) {
243 size += obj->gtt_space->size;
244 ++count;
245 }
246 if (obj->pin_mappable) {
247 mappable_size += obj->gtt_space->size;
248 ++mappable_count;
249 }
250 if (obj->madv == I915_MADV_DONTNEED) {
251 purgeable_size += obj->base.size;
252 ++purgeable_count;
253 }
254 }
255 seq_printf(m, "%u purgeable objects, %zu bytes\n",
256 purgeable_count, purgeable_size);
257 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
258 mappable_count, mappable_size);
259 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
260 count, size);
261
262 seq_printf(m, "%zu [%lu] gtt total\n",
263 dev_priv->gtt.total,
264 dev_priv->gtt.mappable_end - dev_priv->gtt.start);
265
266 mutex_unlock(&dev->struct_mutex);
267
268 return 0;
269}
270
271static int i915_gem_gtt_info(struct seq_file *m, void* data)
272{
273 struct drm_info_node *node = (struct drm_info_node *) m->private;
274 struct drm_device *dev = node->minor->dev;
275 uintptr_t list = (uintptr_t) node->info_ent->data;
276 struct drm_i915_private *dev_priv = dev->dev_private;
277 struct drm_i915_gem_object *obj;
278 size_t total_obj_size, total_gtt_size;
279 int count, ret;
280
281 ret = mutex_lock_interruptible(&dev->struct_mutex);
282 if (ret)
283 return ret;
284
285 total_obj_size = total_gtt_size = count = 0;
286 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
287 if (list == PINNED_LIST && obj->pin_count == 0)
288 continue;
289
290 seq_printf(m, " ");
291 describe_obj(m, obj);
292 seq_printf(m, "\n");
293 total_obj_size += obj->base.size;
294 total_gtt_size += obj->gtt_space->size;
295 count++;
296 }
297
298 mutex_unlock(&dev->struct_mutex);
299
300 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
301 count, total_obj_size, total_gtt_size);
302
303 return 0;
304}
305
306static int i915_gem_pageflip_info(struct seq_file *m, void *data)
307{
308 struct drm_info_node *node = (struct drm_info_node *) m->private;
309 struct drm_device *dev = node->minor->dev;
310 unsigned long flags;
311 struct intel_crtc *crtc;
312
313 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
314 const char pipe = pipe_name(crtc->pipe);
315 const char plane = plane_name(crtc->plane);
316 struct intel_unpin_work *work;
317
318 spin_lock_irqsave(&dev->event_lock, flags);
319 work = crtc->unpin_work;
320 if (work == NULL) {
321 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
322 pipe, plane);
323 } else {
324 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
325 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
326 pipe, plane);
327 } else {
328 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
329 pipe, plane);
330 }
331 if (work->enable_stall_check)
332 seq_printf(m, "Stall check enabled, ");
333 else
334 seq_printf(m, "Stall check waiting for page flip ioctl, ");
335 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
336
337 if (work->old_fb_obj) {
338 struct drm_i915_gem_object *obj = work->old_fb_obj;
339 if (obj)
340 seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
341 }
342 if (work->pending_flip_obj) {
343 struct drm_i915_gem_object *obj = work->pending_flip_obj;
344 if (obj)
345 seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
346 }
347 }
348 spin_unlock_irqrestore(&dev->event_lock, flags);
349 }
350
351 return 0;
352}
353
354static int i915_gem_request_info(struct seq_file *m, void *data)
355{
356 struct drm_info_node *node = (struct drm_info_node *) m->private;
357 struct drm_device *dev = node->minor->dev;
358 drm_i915_private_t *dev_priv = dev->dev_private;
359 struct intel_ring_buffer *ring;
360 struct drm_i915_gem_request *gem_request;
361 int ret, count, i;
362
363 ret = mutex_lock_interruptible(&dev->struct_mutex);
364 if (ret)
365 return ret;
366
367 count = 0;
368 for_each_ring(ring, dev_priv, i) {
369 if (list_empty(&ring->request_list))
370 continue;
371
372 seq_printf(m, "%s requests:\n", ring->name);
373 list_for_each_entry(gem_request,
374 &ring->request_list,
375 list) {
376 seq_printf(m, " %d @ %d\n",
377 gem_request->seqno,
378 (int) (jiffies - gem_request->emitted_jiffies));
379 }
380 count++;
381 }
382 mutex_unlock(&dev->struct_mutex);
383
384 if (count == 0)
385 seq_printf(m, "No requests\n");
386
387 return 0;
388}
389
390static void i915_ring_seqno_info(struct seq_file *m,
391 struct intel_ring_buffer *ring)
392{
393 if (ring->get_seqno) {
394 seq_printf(m, "Current sequence (%s): %u\n",
395 ring->name, ring->get_seqno(ring, false));
396 }
397}
398
399static int i915_gem_seqno_info(struct seq_file *m, void *data)
400{
401 struct drm_info_node *node = (struct drm_info_node *) m->private;
402 struct drm_device *dev = node->minor->dev;
403 drm_i915_private_t *dev_priv = dev->dev_private;
404 struct intel_ring_buffer *ring;
405 int ret, i;
406
407 ret = mutex_lock_interruptible(&dev->struct_mutex);
408 if (ret)
409 return ret;
410
411 for_each_ring(ring, dev_priv, i)
412 i915_ring_seqno_info(m, ring);
413
414 mutex_unlock(&dev->struct_mutex);
415
416 return 0;
417}
418
419
420static int i915_interrupt_info(struct seq_file *m, void *data)
421{
422 struct drm_info_node *node = (struct drm_info_node *) m->private;
423 struct drm_device *dev = node->minor->dev;
424 drm_i915_private_t *dev_priv = dev->dev_private;
425 struct intel_ring_buffer *ring;
426 int ret, i, pipe;
427
428 ret = mutex_lock_interruptible(&dev->struct_mutex);
429 if (ret)
430 return ret;
431
432 if (IS_VALLEYVIEW(dev)) {
433 seq_printf(m, "Display IER:\t%08x\n",
434 I915_READ(VLV_IER));
435 seq_printf(m, "Display IIR:\t%08x\n",
436 I915_READ(VLV_IIR));
437 seq_printf(m, "Display IIR_RW:\t%08x\n",
438 I915_READ(VLV_IIR_RW));
439 seq_printf(m, "Display IMR:\t%08x\n",
440 I915_READ(VLV_IMR));
441 for_each_pipe(pipe)
442 seq_printf(m, "Pipe %c stat:\t%08x\n",
443 pipe_name(pipe),
444 I915_READ(PIPESTAT(pipe)));
445
446 seq_printf(m, "Master IER:\t%08x\n",
447 I915_READ(VLV_MASTER_IER));
448
449 seq_printf(m, "Render IER:\t%08x\n",
450 I915_READ(GTIER));
451 seq_printf(m, "Render IIR:\t%08x\n",
452 I915_READ(GTIIR));
453 seq_printf(m, "Render IMR:\t%08x\n",
454 I915_READ(GTIMR));
455
456 seq_printf(m, "PM IER:\t\t%08x\n",
457 I915_READ(GEN6_PMIER));
458 seq_printf(m, "PM IIR:\t\t%08x\n",
459 I915_READ(GEN6_PMIIR));
460 seq_printf(m, "PM IMR:\t\t%08x\n",
461 I915_READ(GEN6_PMIMR));
462
463 seq_printf(m, "Port hotplug:\t%08x\n",
464 I915_READ(PORT_HOTPLUG_EN));
465 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
466 I915_READ(VLV_DPFLIPSTAT));
467 seq_printf(m, "DPINVGTT:\t%08x\n",
468 I915_READ(DPINVGTT));
469
470 } else if (!HAS_PCH_SPLIT(dev)) {
471 seq_printf(m, "Interrupt enable: %08x\n",
472 I915_READ(IER));
473 seq_printf(m, "Interrupt identity: %08x\n",
474 I915_READ(IIR));
475 seq_printf(m, "Interrupt mask: %08x\n",
476 I915_READ(IMR));
477 for_each_pipe(pipe)
478 seq_printf(m, "Pipe %c stat: %08x\n",
479 pipe_name(pipe),
480 I915_READ(PIPESTAT(pipe)));
481 } else {
482 seq_printf(m, "North Display Interrupt enable: %08x\n",
483 I915_READ(DEIER));
484 seq_printf(m, "North Display Interrupt identity: %08x\n",
485 I915_READ(DEIIR));
486 seq_printf(m, "North Display Interrupt mask: %08x\n",
487 I915_READ(DEIMR));
488 seq_printf(m, "South Display Interrupt enable: %08x\n",
489 I915_READ(SDEIER));
490 seq_printf(m, "South Display Interrupt identity: %08x\n",
491 I915_READ(SDEIIR));
492 seq_printf(m, "South Display Interrupt mask: %08x\n",
493 I915_READ(SDEIMR));
494 seq_printf(m, "Graphics Interrupt enable: %08x\n",
495 I915_READ(GTIER));
496 seq_printf(m, "Graphics Interrupt identity: %08x\n",
497 I915_READ(GTIIR));
498 seq_printf(m, "Graphics Interrupt mask: %08x\n",
499 I915_READ(GTIMR));
500 }
501 seq_printf(m, "Interrupts received: %d\n",
502 atomic_read(&dev_priv->irq_received));
503 for_each_ring(ring, dev_priv, i) {
504 if (IS_GEN6(dev) || IS_GEN7(dev)) {
505 seq_printf(m,
506 "Graphics Interrupt mask (%s): %08x\n",
507 ring->name, I915_READ_IMR(ring));
508 }
509 i915_ring_seqno_info(m, ring);
510 }
511 mutex_unlock(&dev->struct_mutex);
512
513 return 0;
514}
515
516static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
517{
518 struct drm_info_node *node = (struct drm_info_node *) m->private;
519 struct drm_device *dev = node->minor->dev;
520 drm_i915_private_t *dev_priv = dev->dev_private;
521 int i, ret;
522
523 ret = mutex_lock_interruptible(&dev->struct_mutex);
524 if (ret)
525 return ret;
526
527 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
528 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
529 for (i = 0; i < dev_priv->num_fence_regs; i++) {
530 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
531
532 seq_printf(m, "Fence %d, pin count = %d, object = ",
533 i, dev_priv->fence_regs[i].pin_count);
534 if (obj == NULL)
535 seq_printf(m, "unused");
536 else
537 describe_obj(m, obj);
538 seq_printf(m, "\n");
539 }
540
541 mutex_unlock(&dev->struct_mutex);
542 return 0;
543}
544
545static int i915_hws_info(struct seq_file *m, void *data)
546{
547 struct drm_info_node *node = (struct drm_info_node *) m->private;
548 struct drm_device *dev = node->minor->dev;
549 drm_i915_private_t *dev_priv = dev->dev_private;
550 struct intel_ring_buffer *ring;
551 const u32 *hws;
552 int i;
553
554 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
555 hws = ring->status_page.page_addr;
556 if (hws == NULL)
557 return 0;
558
559 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
560 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
561 i * 4,
562 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
563 }
564 return 0;
565}
566
567static const char *ring_str(int ring)
568{
569 switch (ring) {
570 case RCS: return "render";
571 case VCS: return "bsd";
572 case BCS: return "blt";
573 default: return "";
574 }
575}
576
577static const char *pin_flag(int pinned)
578{
579 if (pinned > 0)
580 return " P";
581 else if (pinned < 0)
582 return " p";
583 else
584 return "";
585}
586
587static const char *tiling_flag(int tiling)
588{
589 switch (tiling) {
590 default:
591 case I915_TILING_NONE: return "";
592 case I915_TILING_X: return " X";
593 case I915_TILING_Y: return " Y";
594 }
595}
596
597static const char *dirty_flag(int dirty)
598{
599 return dirty ? " dirty" : "";
600}
601
602static const char *purgeable_flag(int purgeable)
603{
604 return purgeable ? " purgeable" : "";
605}
606
607static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
608 const char *f, va_list args)
609{
610 unsigned len;
611
612 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
613 e->err = -ENOSPC;
614 return;
615 }
616
617 if (e->bytes == e->size - 1 || e->err)
618 return;
619
620 /* Seek the first printf which is hits start position */
621 if (e->pos < e->start) {
622 len = vsnprintf(NULL, 0, f, args);
623 if (e->pos + len <= e->start) {
624 e->pos += len;
625 return;
626 }
627
628 /* First vsnprintf needs to fit in full for memmove*/
629 if (len >= e->size) {
630 e->err = -EIO;
631 return;
632 }
633 }
634
635 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
636 if (len >= e->size - e->bytes)
637 len = e->size - e->bytes - 1;
638
639 /* If this is first printf in this window, adjust it so that
640 * start position matches start of the buffer
641 */
642 if (e->pos < e->start) {
643 const size_t off = e->start - e->pos;
644
645 /* Should not happen but be paranoid */
646 if (off > len || e->bytes) {
647 e->err = -EIO;
648 return;
649 }
650
651 memmove(e->buf, e->buf + off, len - off);
652 e->bytes = len - off;
653 e->pos = e->start;
654 return;
655 }
656
657 e->bytes += len;
658 e->pos += len;
659}
660
661void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
662{
663 va_list args;
664
665 va_start(args, f);
666 i915_error_vprintf(e, f, args);
667 va_end(args);
668}
669
670#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
671
672static void print_error_buffers(struct drm_i915_error_state_buf *m,
673 const char *name,
674 struct drm_i915_error_buffer *err,
675 int count)
676{
677 err_printf(m, "%s [%d]:\n", name, count);
678
679 while (count--) {
680 err_printf(m, " %08x %8u %02x %02x %x %x%s%s%s%s%s%s%s",
681 err->gtt_offset,
682 err->size,
683 err->read_domains,
684 err->write_domain,
685 err->rseqno, err->wseqno,
686 pin_flag(err->pinned),
687 tiling_flag(err->tiling),
688 dirty_flag(err->dirty),
689 purgeable_flag(err->purgeable),
690 err->ring != -1 ? " " : "",
691 ring_str(err->ring),
692 cache_level_str(err->cache_level));
693
694 if (err->name)
695 err_printf(m, " (name: %d)", err->name);
696 if (err->fence_reg != I915_FENCE_REG_NONE)
697 err_printf(m, " (fence: %d)", err->fence_reg);
698
699 err_printf(m, "\n");
700 err++;
701 }
702}
703
704static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
705 struct drm_device *dev,
706 struct drm_i915_error_state *error,
707 unsigned ring)
708{
709 BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */
710 err_printf(m, "%s command stream:\n", ring_str(ring));
711 err_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
712 err_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
713 err_printf(m, " CTL: 0x%08x\n", error->ctl[ring]);
714 err_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
715 err_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
716 err_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
717 err_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
718 if (ring == RCS && INTEL_INFO(dev)->gen >= 4)
719 err_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
720
721 if (INTEL_INFO(dev)->gen >= 4)
722 err_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
723 err_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
724 err_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
725 if (INTEL_INFO(dev)->gen >= 6) {
726 err_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]);
727 err_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
728 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
729 error->semaphore_mboxes[ring][0],
730 error->semaphore_seqno[ring][0]);
731 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
732 error->semaphore_mboxes[ring][1],
733 error->semaphore_seqno[ring][1]);
734 }
735 err_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
736 err_printf(m, " waiting: %s\n", yesno(error->waiting[ring]));
737 err_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
738 err_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
739}
740
741struct i915_error_state_file_priv {
742 struct drm_device *dev;
743 struct drm_i915_error_state *error;
744};
745
746
747static int i915_error_state(struct i915_error_state_file_priv *error_priv,
748 struct drm_i915_error_state_buf *m)
749
750{
751 struct drm_device *dev = error_priv->dev;
752 drm_i915_private_t *dev_priv = dev->dev_private;
753 struct drm_i915_error_state *error = error_priv->error;
754 struct intel_ring_buffer *ring;
755 int i, j, page, offset, elt;
756
757 if (!error) {
758 err_printf(m, "no error state collected\n");
759 return 0;
760 }
761
762 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
763 error->time.tv_usec);
764 err_printf(m, "Kernel: " UTS_RELEASE "\n");
765 err_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
766 err_printf(m, "EIR: 0x%08x\n", error->eir);
767 err_printf(m, "IER: 0x%08x\n", error->ier);
768 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
769 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
770 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
771 err_printf(m, "CCID: 0x%08x\n", error->ccid);
772
773 for (i = 0; i < dev_priv->num_fence_regs; i++)
774 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
775
776 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
777 err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
778 error->extra_instdone[i]);
779
780 if (INTEL_INFO(dev)->gen >= 6) {
781 err_printf(m, "ERROR: 0x%08x\n", error->error);
782 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
783 }
784
785 if (INTEL_INFO(dev)->gen == 7)
786 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
787
788 for_each_ring(ring, dev_priv, i)
789 i915_ring_error_state(m, dev, error, i);
790
791 if (error->active_bo)
792 print_error_buffers(m, "Active",
793 error->active_bo,
794 error->active_bo_count);
795
796 if (error->pinned_bo)
797 print_error_buffers(m, "Pinned",
798 error->pinned_bo,
799 error->pinned_bo_count);
800
801 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
802 struct drm_i915_error_object *obj;
803
804 if ((obj = error->ring[i].batchbuffer)) {
805 err_printf(m, "%s --- gtt_offset = 0x%08x\n",
806 dev_priv->ring[i].name,
807 obj->gtt_offset);
808 offset = 0;
809 for (page = 0; page < obj->page_count; page++) {
810 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
811 err_printf(m, "%08x : %08x\n", offset,
812 obj->pages[page][elt]);
813 offset += 4;
814 }
815 }
816 }
817
818 if (error->ring[i].num_requests) {
819 err_printf(m, "%s --- %d requests\n",
820 dev_priv->ring[i].name,
821 error->ring[i].num_requests);
822 for (j = 0; j < error->ring[i].num_requests; j++) {
823 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
824 error->ring[i].requests[j].seqno,
825 error->ring[i].requests[j].jiffies,
826 error->ring[i].requests[j].tail);
827 }
828 }
829
830 if ((obj = error->ring[i].ringbuffer)) {
831 err_printf(m, "%s --- ringbuffer = 0x%08x\n",
832 dev_priv->ring[i].name,
833 obj->gtt_offset);
834 offset = 0;
835 for (page = 0; page < obj->page_count; page++) {
836 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
837 err_printf(m, "%08x : %08x\n",
838 offset,
839 obj->pages[page][elt]);
840 offset += 4;
841 }
842 }
843 }
844
845 obj = error->ring[i].ctx;
846 if (obj) {
847 err_printf(m, "%s --- HW Context = 0x%08x\n",
848 dev_priv->ring[i].name,
849 obj->gtt_offset);
850 offset = 0;
851 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
852 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
853 offset,
854 obj->pages[0][elt],
855 obj->pages[0][elt+1],
856 obj->pages[0][elt+2],
857 obj->pages[0][elt+3]);
858 offset += 16;
859 }
860 }
861 }
862
863 if (error->overlay)
864 intel_overlay_print_error_state(m, error->overlay);
865
866 if (error->display)
867 intel_display_print_error_state(m, dev, error->display);
868
869 return 0;
870}
871
872static ssize_t
873i915_error_state_write(struct file *filp,
874 const char __user *ubuf,
875 size_t cnt,
876 loff_t *ppos)
877{
878 struct i915_error_state_file_priv *error_priv = filp->private_data;
879 struct drm_device *dev = error_priv->dev;
880 int ret;
881
882 DRM_DEBUG_DRIVER("Resetting error state\n");
883
884 ret = mutex_lock_interruptible(&dev->struct_mutex);
885 if (ret)
886 return ret;
887
888 i915_destroy_error_state(dev);
889 mutex_unlock(&dev->struct_mutex);
890
891 return cnt;
892}
893
894static int i915_error_state_open(struct inode *inode, struct file *file)
895{
896 struct drm_device *dev = inode->i_private;
897 drm_i915_private_t *dev_priv = dev->dev_private;
898 struct i915_error_state_file_priv *error_priv;
899 unsigned long flags;
900
901 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
902 if (!error_priv)
903 return -ENOMEM;
904
905 error_priv->dev = dev;
906
907 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
908 error_priv->error = dev_priv->gpu_error.first_error;
909 if (error_priv->error)
910 kref_get(&error_priv->error->ref);
911 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
912
913 file->private_data = error_priv;
914
915 return 0;
916}
917
918static int i915_error_state_release(struct inode *inode, struct file *file)
919{
920 struct i915_error_state_file_priv *error_priv = file->private_data;
921
922 if (error_priv->error)
923 kref_put(&error_priv->error->ref, i915_error_state_free);
924 kfree(error_priv);
925
926 return 0;
927}
928
929static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
930 size_t count, loff_t *pos)
931{
932 struct i915_error_state_file_priv *error_priv = file->private_data;
933 struct drm_i915_error_state_buf error_str;
934 loff_t tmp_pos = 0;
935 ssize_t ret_count = 0;
936 int ret = 0;
937
938 memset(&error_str, 0, sizeof(error_str));
939
940 /* We need to have enough room to store any i915_error_state printf
941 * so that we can move it to start position.
942 */
943 error_str.size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
944 error_str.buf = kmalloc(error_str.size,
945 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
946
947 if (error_str.buf == NULL) {
948 error_str.size = PAGE_SIZE;
949 error_str.buf = kmalloc(error_str.size, GFP_TEMPORARY);
950 }
951
952 if (error_str.buf == NULL) {
953 error_str.size = 128;
954 error_str.buf = kmalloc(error_str.size, GFP_TEMPORARY);
955 }
956
957 if (error_str.buf == NULL)
958 return -ENOMEM;
959
960 error_str.start = *pos;
961
962 ret = i915_error_state(error_priv, &error_str);
963 if (ret)
964 goto out;
965
966 if (error_str.bytes == 0 && error_str.err) {
967 ret = error_str.err;
968 goto out;
969 }
970
971 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
972 error_str.buf,
973 error_str.bytes);
974
975 if (ret_count < 0)
976 ret = ret_count;
977 else
978 *pos = error_str.start + ret_count;
979out:
980 kfree(error_str.buf);
981 return ret ?: ret_count;
982}
983
984static const struct file_operations i915_error_state_fops = {
985 .owner = THIS_MODULE,
986 .open = i915_error_state_open,
987 .read = i915_error_state_read,
988 .write = i915_error_state_write,
989 .llseek = default_llseek,
990 .release = i915_error_state_release,
991};
992
993static int
994i915_next_seqno_get(void *data, u64 *val)
995{
996 struct drm_device *dev = data;
997 drm_i915_private_t *dev_priv = dev->dev_private;
998 int ret;
999
1000 ret = mutex_lock_interruptible(&dev->struct_mutex);
1001 if (ret)
1002 return ret;
1003
1004 *val = dev_priv->next_seqno;
1005 mutex_unlock(&dev->struct_mutex);
1006
1007 return 0;
1008}
1009
1010static int
1011i915_next_seqno_set(void *data, u64 val)
1012{
1013 struct drm_device *dev = data;
1014 int ret;
1015
1016 ret = mutex_lock_interruptible(&dev->struct_mutex);
1017 if (ret)
1018 return ret;
1019
1020 ret = i915_gem_set_seqno(dev, val);
1021 mutex_unlock(&dev->struct_mutex);
1022
1023 return ret;
1024}
1025
1026DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1027 i915_next_seqno_get, i915_next_seqno_set,
1028 "0x%llx\n");
1029
1030static int i915_rstdby_delays(struct seq_file *m, void *unused)
1031{
1032 struct drm_info_node *node = (struct drm_info_node *) m->private;
1033 struct drm_device *dev = node->minor->dev;
1034 drm_i915_private_t *dev_priv = dev->dev_private;
1035 u16 crstanddelay;
1036 int ret;
1037
1038 ret = mutex_lock_interruptible(&dev->struct_mutex);
1039 if (ret)
1040 return ret;
1041
1042 crstanddelay = I915_READ16(CRSTANDVID);
1043
1044 mutex_unlock(&dev->struct_mutex);
1045
1046 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
1047
1048 return 0;
1049}
1050
1051static int i915_cur_delayinfo(struct seq_file *m, void *unused)
1052{
1053 struct drm_info_node *node = (struct drm_info_node *) m->private;
1054 struct drm_device *dev = node->minor->dev;
1055 drm_i915_private_t *dev_priv = dev->dev_private;
1056 int ret;
1057
1058 if (IS_GEN5(dev)) {
1059 u16 rgvswctl = I915_READ16(MEMSWCTL);
1060 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1061
1062 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1063 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1064 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1065 MEMSTAT_VID_SHIFT);
1066 seq_printf(m, "Current P-state: %d\n",
1067 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1068 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
1069 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1070 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1071 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1072 u32 rpstat, cagf;
1073 u32 rpupei, rpcurup, rpprevup;
1074 u32 rpdownei, rpcurdown, rpprevdown;
1075 int max_freq;
1076
1077 /* RPSTAT1 is in the GT power well */
1078 ret = mutex_lock_interruptible(&dev->struct_mutex);
1079 if (ret)
1080 return ret;
1081
1082 gen6_gt_force_wake_get(dev_priv);
1083
1084 rpstat = I915_READ(GEN6_RPSTAT1);
1085 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1086 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1087 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1088 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1089 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1090 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1091 if (IS_HASWELL(dev))
1092 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1093 else
1094 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1095 cagf *= GT_FREQUENCY_MULTIPLIER;
1096
1097 gen6_gt_force_wake_put(dev_priv);
1098 mutex_unlock(&dev->struct_mutex);
1099
1100 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1101 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1102 seq_printf(m, "Render p-state ratio: %d\n",
1103 (gt_perf_status & 0xff00) >> 8);
1104 seq_printf(m, "Render p-state VID: %d\n",
1105 gt_perf_status & 0xff);
1106 seq_printf(m, "Render p-state limit: %d\n",
1107 rp_state_limits & 0xff);
1108 seq_printf(m, "CAGF: %dMHz\n", cagf);
1109 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1110 GEN6_CURICONT_MASK);
1111 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1112 GEN6_CURBSYTAVG_MASK);
1113 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1114 GEN6_CURBSYTAVG_MASK);
1115 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1116 GEN6_CURIAVG_MASK);
1117 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1118 GEN6_CURBSYTAVG_MASK);
1119 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1120 GEN6_CURBSYTAVG_MASK);
1121
1122 max_freq = (rp_state_cap & 0xff0000) >> 16;
1123 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1124 max_freq * GT_FREQUENCY_MULTIPLIER);
1125
1126 max_freq = (rp_state_cap & 0xff00) >> 8;
1127 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1128 max_freq * GT_FREQUENCY_MULTIPLIER);
1129
1130 max_freq = rp_state_cap & 0xff;
1131 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1132 max_freq * GT_FREQUENCY_MULTIPLIER);
1133
1134 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1135 dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
1136 } else if (IS_VALLEYVIEW(dev)) {
1137 u32 freq_sts, val;
1138
1139 mutex_lock(&dev_priv->rps.hw_lock);
1140 vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS,
1141 &freq_sts);
1142 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1143 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1144
1145 vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1, &val);
1146 seq_printf(m, "max GPU freq: %d MHz\n",
1147 vlv_gpu_freq(dev_priv->mem_freq, val));
1148
1149 vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val);
1150 seq_printf(m, "min GPU freq: %d MHz\n",
1151 vlv_gpu_freq(dev_priv->mem_freq, val));
1152
1153 seq_printf(m, "current GPU freq: %d MHz\n",
1154 vlv_gpu_freq(dev_priv->mem_freq,
1155 (freq_sts >> 8) & 0xff));
1156 mutex_unlock(&dev_priv->rps.hw_lock);
1157 } else {
1158 seq_printf(m, "no P-state info available\n");
1159 }
1160
1161 return 0;
1162}
1163
1164static int i915_delayfreq_table(struct seq_file *m, void *unused)
1165{
1166 struct drm_info_node *node = (struct drm_info_node *) m->private;
1167 struct drm_device *dev = node->minor->dev;
1168 drm_i915_private_t *dev_priv = dev->dev_private;
1169 u32 delayfreq;
1170 int ret, i;
1171
1172 ret = mutex_lock_interruptible(&dev->struct_mutex);
1173 if (ret)
1174 return ret;
1175
1176 for (i = 0; i < 16; i++) {
1177 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
1178 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1179 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
1180 }
1181
1182 mutex_unlock(&dev->struct_mutex);
1183
1184 return 0;
1185}
1186
1187static inline int MAP_TO_MV(int map)
1188{
1189 return 1250 - (map * 25);
1190}
1191
1192static int i915_inttoext_table(struct seq_file *m, void *unused)
1193{
1194 struct drm_info_node *node = (struct drm_info_node *) m->private;
1195 struct drm_device *dev = node->minor->dev;
1196 drm_i915_private_t *dev_priv = dev->dev_private;
1197 u32 inttoext;
1198 int ret, i;
1199
1200 ret = mutex_lock_interruptible(&dev->struct_mutex);
1201 if (ret)
1202 return ret;
1203
1204 for (i = 1; i <= 32; i++) {
1205 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1206 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1207 }
1208
1209 mutex_unlock(&dev->struct_mutex);
1210
1211 return 0;
1212}
1213
1214static int ironlake_drpc_info(struct seq_file *m)
1215{
1216 struct drm_info_node *node = (struct drm_info_node *) m->private;
1217 struct drm_device *dev = node->minor->dev;
1218 drm_i915_private_t *dev_priv = dev->dev_private;
1219 u32 rgvmodectl, rstdbyctl;
1220 u16 crstandvid;
1221 int ret;
1222
1223 ret = mutex_lock_interruptible(&dev->struct_mutex);
1224 if (ret)
1225 return ret;
1226
1227 rgvmodectl = I915_READ(MEMMODECTL);
1228 rstdbyctl = I915_READ(RSTDBYCTL);
1229 crstandvid = I915_READ16(CRSTANDVID);
1230
1231 mutex_unlock(&dev->struct_mutex);
1232
1233 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1234 "yes" : "no");
1235 seq_printf(m, "Boost freq: %d\n",
1236 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1237 MEMMODE_BOOST_FREQ_SHIFT);
1238 seq_printf(m, "HW control enabled: %s\n",
1239 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1240 seq_printf(m, "SW control enabled: %s\n",
1241 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1242 seq_printf(m, "Gated voltage change: %s\n",
1243 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1244 seq_printf(m, "Starting frequency: P%d\n",
1245 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1246 seq_printf(m, "Max P-state: P%d\n",
1247 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1248 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1249 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1250 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1251 seq_printf(m, "Render standby enabled: %s\n",
1252 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1253 seq_printf(m, "Current RS state: ");
1254 switch (rstdbyctl & RSX_STATUS_MASK) {
1255 case RSX_STATUS_ON:
1256 seq_printf(m, "on\n");
1257 break;
1258 case RSX_STATUS_RC1:
1259 seq_printf(m, "RC1\n");
1260 break;
1261 case RSX_STATUS_RC1E:
1262 seq_printf(m, "RC1E\n");
1263 break;
1264 case RSX_STATUS_RS1:
1265 seq_printf(m, "RS1\n");
1266 break;
1267 case RSX_STATUS_RS2:
1268 seq_printf(m, "RS2 (RC6)\n");
1269 break;
1270 case RSX_STATUS_RS3:
1271 seq_printf(m, "RC3 (RC6+)\n");
1272 break;
1273 default:
1274 seq_printf(m, "unknown\n");
1275 break;
1276 }
1277
1278 return 0;
1279}
1280
1281static int gen6_drpc_info(struct seq_file *m)
1282{
1283
1284 struct drm_info_node *node = (struct drm_info_node *) m->private;
1285 struct drm_device *dev = node->minor->dev;
1286 struct drm_i915_private *dev_priv = dev->dev_private;
1287 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1288 unsigned forcewake_count;
1289 int count=0, ret;
1290
1291
1292 ret = mutex_lock_interruptible(&dev->struct_mutex);
1293 if (ret)
1294 return ret;
1295
1296 spin_lock_irq(&dev_priv->gt_lock);
1297 forcewake_count = dev_priv->forcewake_count;
1298 spin_unlock_irq(&dev_priv->gt_lock);
1299
1300 if (forcewake_count) {
1301 seq_printf(m, "RC information inaccurate because somebody "
1302 "holds a forcewake reference \n");
1303 } else {
1304 /* NB: we cannot use forcewake, else we read the wrong values */
1305 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1306 udelay(10);
1307 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1308 }
1309
1310 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1311 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4);
1312
1313 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1314 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1315 mutex_unlock(&dev->struct_mutex);
1316 mutex_lock(&dev_priv->rps.hw_lock);
1317 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1318 mutex_unlock(&dev_priv->rps.hw_lock);
1319
1320 seq_printf(m, "Video Turbo Mode: %s\n",
1321 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1322 seq_printf(m, "HW control enabled: %s\n",
1323 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1324 seq_printf(m, "SW control enabled: %s\n",
1325 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1326 GEN6_RP_MEDIA_SW_MODE));
1327 seq_printf(m, "RC1e Enabled: %s\n",
1328 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1329 seq_printf(m, "RC6 Enabled: %s\n",
1330 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1331 seq_printf(m, "Deep RC6 Enabled: %s\n",
1332 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1333 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1334 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1335 seq_printf(m, "Current RC state: ");
1336 switch (gt_core_status & GEN6_RCn_MASK) {
1337 case GEN6_RC0:
1338 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1339 seq_printf(m, "Core Power Down\n");
1340 else
1341 seq_printf(m, "on\n");
1342 break;
1343 case GEN6_RC3:
1344 seq_printf(m, "RC3\n");
1345 break;
1346 case GEN6_RC6:
1347 seq_printf(m, "RC6\n");
1348 break;
1349 case GEN6_RC7:
1350 seq_printf(m, "RC7\n");
1351 break;
1352 default:
1353 seq_printf(m, "Unknown\n");
1354 break;
1355 }
1356
1357 seq_printf(m, "Core Power Down: %s\n",
1358 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1359
1360 /* Not exactly sure what this is */
1361 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1362 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1363 seq_printf(m, "RC6 residency since boot: %u\n",
1364 I915_READ(GEN6_GT_GFX_RC6));
1365 seq_printf(m, "RC6+ residency since boot: %u\n",
1366 I915_READ(GEN6_GT_GFX_RC6p));
1367 seq_printf(m, "RC6++ residency since boot: %u\n",
1368 I915_READ(GEN6_GT_GFX_RC6pp));
1369
1370 seq_printf(m, "RC6 voltage: %dmV\n",
1371 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1372 seq_printf(m, "RC6+ voltage: %dmV\n",
1373 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1374 seq_printf(m, "RC6++ voltage: %dmV\n",
1375 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1376 return 0;
1377}
1378
1379static int i915_drpc_info(struct seq_file *m, void *unused)
1380{
1381 struct drm_info_node *node = (struct drm_info_node *) m->private;
1382 struct drm_device *dev = node->minor->dev;
1383
1384 if (IS_GEN6(dev) || IS_GEN7(dev))
1385 return gen6_drpc_info(m);
1386 else
1387 return ironlake_drpc_info(m);
1388}
1389
1390static int i915_fbc_status(struct seq_file *m, void *unused)
1391{
1392 struct drm_info_node *node = (struct drm_info_node *) m->private;
1393 struct drm_device *dev = node->minor->dev;
1394 drm_i915_private_t *dev_priv = dev->dev_private;
1395
1396 if (!I915_HAS_FBC(dev)) {
1397 seq_printf(m, "FBC unsupported on this chipset\n");
1398 return 0;
1399 }
1400
1401 if (intel_fbc_enabled(dev)) {
1402 seq_printf(m, "FBC enabled\n");
1403 } else {
1404 seq_printf(m, "FBC disabled: ");
1405 switch (dev_priv->no_fbc_reason) {
1406 case FBC_NO_OUTPUT:
1407 seq_printf(m, "no outputs");
1408 break;
1409 case FBC_STOLEN_TOO_SMALL:
1410 seq_printf(m, "not enough stolen memory");
1411 break;
1412 case FBC_UNSUPPORTED_MODE:
1413 seq_printf(m, "mode not supported");
1414 break;
1415 case FBC_MODE_TOO_LARGE:
1416 seq_printf(m, "mode too large");
1417 break;
1418 case FBC_BAD_PLANE:
1419 seq_printf(m, "FBC unsupported on plane");
1420 break;
1421 case FBC_NOT_TILED:
1422 seq_printf(m, "scanout buffer not tiled");
1423 break;
1424 case FBC_MULTIPLE_PIPES:
1425 seq_printf(m, "multiple pipes are enabled");
1426 break;
1427 case FBC_MODULE_PARAM:
1428 seq_printf(m, "disabled per module param (default off)");
1429 break;
1430 default:
1431 seq_printf(m, "unknown reason");
1432 }
1433 seq_printf(m, "\n");
1434 }
1435 return 0;
1436}
1437
1438static int i915_sr_status(struct seq_file *m, void *unused)
1439{
1440 struct drm_info_node *node = (struct drm_info_node *) m->private;
1441 struct drm_device *dev = node->minor->dev;
1442 drm_i915_private_t *dev_priv = dev->dev_private;
1443 bool sr_enabled = false;
1444
1445 if (HAS_PCH_SPLIT(dev))
1446 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1447 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1448 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1449 else if (IS_I915GM(dev))
1450 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1451 else if (IS_PINEVIEW(dev))
1452 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1453
1454 seq_printf(m, "self-refresh: %s\n",
1455 sr_enabled ? "enabled" : "disabled");
1456
1457 return 0;
1458}
1459
1460static int i915_emon_status(struct seq_file *m, void *unused)
1461{
1462 struct drm_info_node *node = (struct drm_info_node *) m->private;
1463 struct drm_device *dev = node->minor->dev;
1464 drm_i915_private_t *dev_priv = dev->dev_private;
1465 unsigned long temp, chipset, gfx;
1466 int ret;
1467
1468 if (!IS_GEN5(dev))
1469 return -ENODEV;
1470
1471 ret = mutex_lock_interruptible(&dev->struct_mutex);
1472 if (ret)
1473 return ret;
1474
1475 temp = i915_mch_val(dev_priv);
1476 chipset = i915_chipset_val(dev_priv);
1477 gfx = i915_gfx_val(dev_priv);
1478 mutex_unlock(&dev->struct_mutex);
1479
1480 seq_printf(m, "GMCH temp: %ld\n", temp);
1481 seq_printf(m, "Chipset power: %ld\n", chipset);
1482 seq_printf(m, "GFX power: %ld\n", gfx);
1483 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1484
1485 return 0;
1486}
1487
1488static int i915_ring_freq_table(struct seq_file *m, void *unused)
1489{
1490 struct drm_info_node *node = (struct drm_info_node *) m->private;
1491 struct drm_device *dev = node->minor->dev;
1492 drm_i915_private_t *dev_priv = dev->dev_private;
1493 int ret;
1494 int gpu_freq, ia_freq;
1495
1496 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1497 seq_printf(m, "unsupported on this chipset\n");
1498 return 0;
1499 }
1500
1501 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1502 if (ret)
1503 return ret;
1504
1505 seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1506
1507 for (gpu_freq = dev_priv->rps.min_delay;
1508 gpu_freq <= dev_priv->rps.max_delay;
1509 gpu_freq++) {
1510 ia_freq = gpu_freq;
1511 sandybridge_pcode_read(dev_priv,
1512 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1513 &ia_freq);
1514 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1515 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1516 ((ia_freq >> 0) & 0xff) * 100,
1517 ((ia_freq >> 8) & 0xff) * 100);
1518 }
1519
1520 mutex_unlock(&dev_priv->rps.hw_lock);
1521
1522 return 0;
1523}
1524
1525static int i915_gfxec(struct seq_file *m, void *unused)
1526{
1527 struct drm_info_node *node = (struct drm_info_node *) m->private;
1528 struct drm_device *dev = node->minor->dev;
1529 drm_i915_private_t *dev_priv = dev->dev_private;
1530 int ret;
1531
1532 ret = mutex_lock_interruptible(&dev->struct_mutex);
1533 if (ret)
1534 return ret;
1535
1536 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1537
1538 mutex_unlock(&dev->struct_mutex);
1539
1540 return 0;
1541}
1542
1543static int i915_opregion(struct seq_file *m, void *unused)
1544{
1545 struct drm_info_node *node = (struct drm_info_node *) m->private;
1546 struct drm_device *dev = node->minor->dev;
1547 drm_i915_private_t *dev_priv = dev->dev_private;
1548 struct intel_opregion *opregion = &dev_priv->opregion;
1549 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1550 int ret;
1551
1552 if (data == NULL)
1553 return -ENOMEM;
1554
1555 ret = mutex_lock_interruptible(&dev->struct_mutex);
1556 if (ret)
1557 goto out;
1558
1559 if (opregion->header) {
1560 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1561 seq_write(m, data, OPREGION_SIZE);
1562 }
1563
1564 mutex_unlock(&dev->struct_mutex);
1565
1566out:
1567 kfree(data);
1568 return 0;
1569}
1570
1571static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1572{
1573 struct drm_info_node *node = (struct drm_info_node *) m->private;
1574 struct drm_device *dev = node->minor->dev;
1575 drm_i915_private_t *dev_priv = dev->dev_private;
1576 struct intel_fbdev *ifbdev;
1577 struct intel_framebuffer *fb;
1578 int ret;
1579
1580 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1581 if (ret)
1582 return ret;
1583
1584 ifbdev = dev_priv->fbdev;
1585 fb = to_intel_framebuffer(ifbdev->helper.fb);
1586
1587 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1588 fb->base.width,
1589 fb->base.height,
1590 fb->base.depth,
1591 fb->base.bits_per_pixel,
1592 atomic_read(&fb->base.refcount.refcount));
1593 describe_obj(m, fb->obj);
1594 seq_printf(m, "\n");
1595 mutex_unlock(&dev->mode_config.mutex);
1596
1597 mutex_lock(&dev->mode_config.fb_lock);
1598 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1599 if (&fb->base == ifbdev->helper.fb)
1600 continue;
1601
1602 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1603 fb->base.width,
1604 fb->base.height,
1605 fb->base.depth,
1606 fb->base.bits_per_pixel,
1607 atomic_read(&fb->base.refcount.refcount));
1608 describe_obj(m, fb->obj);
1609 seq_printf(m, "\n");
1610 }
1611 mutex_unlock(&dev->mode_config.fb_lock);
1612
1613 return 0;
1614}
1615
1616static int i915_context_status(struct seq_file *m, void *unused)
1617{
1618 struct drm_info_node *node = (struct drm_info_node *) m->private;
1619 struct drm_device *dev = node->minor->dev;
1620 drm_i915_private_t *dev_priv = dev->dev_private;
1621 struct intel_ring_buffer *ring;
1622 int ret, i;
1623
1624 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1625 if (ret)
1626 return ret;
1627
1628 if (dev_priv->ips.pwrctx) {
1629 seq_printf(m, "power context ");
1630 describe_obj(m, dev_priv->ips.pwrctx);
1631 seq_printf(m, "\n");
1632 }
1633
1634 if (dev_priv->ips.renderctx) {
1635 seq_printf(m, "render context ");
1636 describe_obj(m, dev_priv->ips.renderctx);
1637 seq_printf(m, "\n");
1638 }
1639
1640 for_each_ring(ring, dev_priv, i) {
1641 if (ring->default_context) {
1642 seq_printf(m, "HW default context %s ring ", ring->name);
1643 describe_obj(m, ring->default_context->obj);
1644 seq_printf(m, "\n");
1645 }
1646 }
1647
1648 mutex_unlock(&dev->mode_config.mutex);
1649
1650 return 0;
1651}
1652
1653static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1654{
1655 struct drm_info_node *node = (struct drm_info_node *) m->private;
1656 struct drm_device *dev = node->minor->dev;
1657 struct drm_i915_private *dev_priv = dev->dev_private;
1658 unsigned forcewake_count;
1659
1660 spin_lock_irq(&dev_priv->gt_lock);
1661 forcewake_count = dev_priv->forcewake_count;
1662 spin_unlock_irq(&dev_priv->gt_lock);
1663
1664 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1665
1666 return 0;
1667}
1668
1669static const char *swizzle_string(unsigned swizzle)
1670{
1671 switch(swizzle) {
1672 case I915_BIT_6_SWIZZLE_NONE:
1673 return "none";
1674 case I915_BIT_6_SWIZZLE_9:
1675 return "bit9";
1676 case I915_BIT_6_SWIZZLE_9_10:
1677 return "bit9/bit10";
1678 case I915_BIT_6_SWIZZLE_9_11:
1679 return "bit9/bit11";
1680 case I915_BIT_6_SWIZZLE_9_10_11:
1681 return "bit9/bit10/bit11";
1682 case I915_BIT_6_SWIZZLE_9_17:
1683 return "bit9/bit17";
1684 case I915_BIT_6_SWIZZLE_9_10_17:
1685 return "bit9/bit10/bit17";
1686 case I915_BIT_6_SWIZZLE_UNKNOWN:
1687 return "unknown";
1688 }
1689
1690 return "bug";
1691}
1692
1693static int i915_swizzle_info(struct seq_file *m, void *data)
1694{
1695 struct drm_info_node *node = (struct drm_info_node *) m->private;
1696 struct drm_device *dev = node->minor->dev;
1697 struct drm_i915_private *dev_priv = dev->dev_private;
1698 int ret;
1699
1700 ret = mutex_lock_interruptible(&dev->struct_mutex);
1701 if (ret)
1702 return ret;
1703
1704 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1705 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1706 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1707 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1708
1709 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1710 seq_printf(m, "DDC = 0x%08x\n",
1711 I915_READ(DCC));
1712 seq_printf(m, "C0DRB3 = 0x%04x\n",
1713 I915_READ16(C0DRB3));
1714 seq_printf(m, "C1DRB3 = 0x%04x\n",
1715 I915_READ16(C1DRB3));
1716 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1717 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1718 I915_READ(MAD_DIMM_C0));
1719 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1720 I915_READ(MAD_DIMM_C1));
1721 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1722 I915_READ(MAD_DIMM_C2));
1723 seq_printf(m, "TILECTL = 0x%08x\n",
1724 I915_READ(TILECTL));
1725 seq_printf(m, "ARB_MODE = 0x%08x\n",
1726 I915_READ(ARB_MODE));
1727 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1728 I915_READ(DISP_ARB_CTL));
1729 }
1730 mutex_unlock(&dev->struct_mutex);
1731
1732 return 0;
1733}
1734
1735static int i915_ppgtt_info(struct seq_file *m, void *data)
1736{
1737 struct drm_info_node *node = (struct drm_info_node *) m->private;
1738 struct drm_device *dev = node->minor->dev;
1739 struct drm_i915_private *dev_priv = dev->dev_private;
1740 struct intel_ring_buffer *ring;
1741 int i, ret;
1742
1743
1744 ret = mutex_lock_interruptible(&dev->struct_mutex);
1745 if (ret)
1746 return ret;
1747 if (INTEL_INFO(dev)->gen == 6)
1748 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1749
1750 for_each_ring(ring, dev_priv, i) {
1751 seq_printf(m, "%s\n", ring->name);
1752 if (INTEL_INFO(dev)->gen == 7)
1753 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1754 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1755 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1756 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1757 }
1758 if (dev_priv->mm.aliasing_ppgtt) {
1759 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1760
1761 seq_printf(m, "aliasing PPGTT:\n");
1762 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1763 }
1764 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1765 mutex_unlock(&dev->struct_mutex);
1766
1767 return 0;
1768}
1769
1770static int i915_dpio_info(struct seq_file *m, void *data)
1771{
1772 struct drm_info_node *node = (struct drm_info_node *) m->private;
1773 struct drm_device *dev = node->minor->dev;
1774 struct drm_i915_private *dev_priv = dev->dev_private;
1775 int ret;
1776
1777
1778 if (!IS_VALLEYVIEW(dev)) {
1779 seq_printf(m, "unsupported\n");
1780 return 0;
1781 }
1782
1783 ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
1784 if (ret)
1785 return ret;
1786
1787 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1788
1789 seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
1790 vlv_dpio_read(dev_priv, _DPIO_DIV_A));
1791 seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
1792 vlv_dpio_read(dev_priv, _DPIO_DIV_B));
1793
1794 seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
1795 vlv_dpio_read(dev_priv, _DPIO_REFSFR_A));
1796 seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
1797 vlv_dpio_read(dev_priv, _DPIO_REFSFR_B));
1798
1799 seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
1800 vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
1801 seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
1802 vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
1803
1804 seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n",
1805 vlv_dpio_read(dev_priv, _DPIO_LFP_COEFF_A));
1806 seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n",
1807 vlv_dpio_read(dev_priv, _DPIO_LFP_COEFF_B));
1808
1809 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1810 vlv_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
1811
1812 mutex_unlock(&dev_priv->dpio_lock);
1813
1814 return 0;
1815}
1816
1817static int
1818i915_wedged_get(void *data, u64 *val)
1819{
1820 struct drm_device *dev = data;
1821 drm_i915_private_t *dev_priv = dev->dev_private;
1822
1823 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
1824
1825 return 0;
1826}
1827
1828static int
1829i915_wedged_set(void *data, u64 val)
1830{
1831 struct drm_device *dev = data;
1832
1833 DRM_INFO("Manually setting wedged to %llu\n", val);
1834 i915_handle_error(dev, val);
1835
1836 return 0;
1837}
1838
1839DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
1840 i915_wedged_get, i915_wedged_set,
1841 "%llu\n");
1842
1843static int
1844i915_ring_stop_get(void *data, u64 *val)
1845{
1846 struct drm_device *dev = data;
1847 drm_i915_private_t *dev_priv = dev->dev_private;
1848
1849 *val = dev_priv->gpu_error.stop_rings;
1850
1851 return 0;
1852}
1853
1854static int
1855i915_ring_stop_set(void *data, u64 val)
1856{
1857 struct drm_device *dev = data;
1858 struct drm_i915_private *dev_priv = dev->dev_private;
1859 int ret;
1860
1861 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
1862
1863 ret = mutex_lock_interruptible(&dev->struct_mutex);
1864 if (ret)
1865 return ret;
1866
1867 dev_priv->gpu_error.stop_rings = val;
1868 mutex_unlock(&dev->struct_mutex);
1869
1870 return 0;
1871}
1872
1873DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
1874 i915_ring_stop_get, i915_ring_stop_set,
1875 "0x%08llx\n");
1876
1877#define DROP_UNBOUND 0x1
1878#define DROP_BOUND 0x2
1879#define DROP_RETIRE 0x4
1880#define DROP_ACTIVE 0x8
1881#define DROP_ALL (DROP_UNBOUND | \
1882 DROP_BOUND | \
1883 DROP_RETIRE | \
1884 DROP_ACTIVE)
1885static int
1886i915_drop_caches_get(void *data, u64 *val)
1887{
1888 *val = DROP_ALL;
1889
1890 return 0;
1891}
1892
1893static int
1894i915_drop_caches_set(void *data, u64 val)
1895{
1896 struct drm_device *dev = data;
1897 struct drm_i915_private *dev_priv = dev->dev_private;
1898 struct drm_i915_gem_object *obj, *next;
1899 int ret;
1900
1901 DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val);
1902
1903 /* No need to check and wait for gpu resets, only libdrm auto-restarts
1904 * on ioctls on -EAGAIN. */
1905 ret = mutex_lock_interruptible(&dev->struct_mutex);
1906 if (ret)
1907 return ret;
1908
1909 if (val & DROP_ACTIVE) {
1910 ret = i915_gpu_idle(dev);
1911 if (ret)
1912 goto unlock;
1913 }
1914
1915 if (val & (DROP_RETIRE | DROP_ACTIVE))
1916 i915_gem_retire_requests(dev);
1917
1918 if (val & DROP_BOUND) {
1919 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list, mm_list)
1920 if (obj->pin_count == 0) {
1921 ret = i915_gem_object_unbind(obj);
1922 if (ret)
1923 goto unlock;
1924 }
1925 }
1926
1927 if (val & DROP_UNBOUND) {
1928 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)
1929 if (obj->pages_pin_count == 0) {
1930 ret = i915_gem_object_put_pages(obj);
1931 if (ret)
1932 goto unlock;
1933 }
1934 }
1935
1936unlock:
1937 mutex_unlock(&dev->struct_mutex);
1938
1939 return ret;
1940}
1941
1942DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
1943 i915_drop_caches_get, i915_drop_caches_set,
1944 "0x%08llx\n");
1945
1946static int
1947i915_max_freq_get(void *data, u64 *val)
1948{
1949 struct drm_device *dev = data;
1950 drm_i915_private_t *dev_priv = dev->dev_private;
1951 int ret;
1952
1953 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1954 return -ENODEV;
1955
1956 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1957 if (ret)
1958 return ret;
1959
1960 if (IS_VALLEYVIEW(dev))
1961 *val = vlv_gpu_freq(dev_priv->mem_freq,
1962 dev_priv->rps.max_delay);
1963 else
1964 *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
1965 mutex_unlock(&dev_priv->rps.hw_lock);
1966
1967 return 0;
1968}
1969
1970static int
1971i915_max_freq_set(void *data, u64 val)
1972{
1973 struct drm_device *dev = data;
1974 struct drm_i915_private *dev_priv = dev->dev_private;
1975 int ret;
1976
1977 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1978 return -ENODEV;
1979
1980 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
1981
1982 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1983 if (ret)
1984 return ret;
1985
1986 /*
1987 * Turbo will still be enabled, but won't go above the set value.
1988 */
1989 if (IS_VALLEYVIEW(dev)) {
1990 val = vlv_freq_opcode(dev_priv->mem_freq, val);
1991 dev_priv->rps.max_delay = val;
1992 gen6_set_rps(dev, val);
1993 } else {
1994 do_div(val, GT_FREQUENCY_MULTIPLIER);
1995 dev_priv->rps.max_delay = val;
1996 gen6_set_rps(dev, val);
1997 }
1998
1999 mutex_unlock(&dev_priv->rps.hw_lock);
2000
2001 return 0;
2002}
2003
2004DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
2005 i915_max_freq_get, i915_max_freq_set,
2006 "%llu\n");
2007
2008static int
2009i915_min_freq_get(void *data, u64 *val)
2010{
2011 struct drm_device *dev = data;
2012 drm_i915_private_t *dev_priv = dev->dev_private;
2013 int ret;
2014
2015 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2016 return -ENODEV;
2017
2018 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2019 if (ret)
2020 return ret;
2021
2022 if (IS_VALLEYVIEW(dev))
2023 *val = vlv_gpu_freq(dev_priv->mem_freq,
2024 dev_priv->rps.min_delay);
2025 else
2026 *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
2027 mutex_unlock(&dev_priv->rps.hw_lock);
2028
2029 return 0;
2030}
2031
2032static int
2033i915_min_freq_set(void *data, u64 val)
2034{
2035 struct drm_device *dev = data;
2036 struct drm_i915_private *dev_priv = dev->dev_private;
2037 int ret;
2038
2039 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2040 return -ENODEV;
2041
2042 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
2043
2044 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2045 if (ret)
2046 return ret;
2047
2048 /*
2049 * Turbo will still be enabled, but won't go below the set value.
2050 */
2051 if (IS_VALLEYVIEW(dev)) {
2052 val = vlv_freq_opcode(dev_priv->mem_freq, val);
2053 dev_priv->rps.min_delay = val;
2054 valleyview_set_rps(dev, val);
2055 } else {
2056 do_div(val, GT_FREQUENCY_MULTIPLIER);
2057 dev_priv->rps.min_delay = val;
2058 gen6_set_rps(dev, val);
2059 }
2060 mutex_unlock(&dev_priv->rps.hw_lock);
2061
2062 return 0;
2063}
2064
2065DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
2066 i915_min_freq_get, i915_min_freq_set,
2067 "%llu\n");
2068
2069static int
2070i915_cache_sharing_get(void *data, u64 *val)
2071{
2072 struct drm_device *dev = data;
2073 drm_i915_private_t *dev_priv = dev->dev_private;
2074 u32 snpcr;
2075 int ret;
2076
2077 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2078 return -ENODEV;
2079
2080 ret = mutex_lock_interruptible(&dev->struct_mutex);
2081 if (ret)
2082 return ret;
2083
2084 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2085 mutex_unlock(&dev_priv->dev->struct_mutex);
2086
2087 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
2088
2089 return 0;
2090}
2091
2092static int
2093i915_cache_sharing_set(void *data, u64 val)
2094{
2095 struct drm_device *dev = data;
2096 struct drm_i915_private *dev_priv = dev->dev_private;
2097 u32 snpcr;
2098
2099 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2100 return -ENODEV;
2101
2102 if (val > 3)
2103 return -EINVAL;
2104
2105 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
2106
2107 /* Update the cache sharing policy here as well */
2108 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2109 snpcr &= ~GEN6_MBC_SNPCR_MASK;
2110 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
2111 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
2112
2113 return 0;
2114}
2115
2116DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
2117 i915_cache_sharing_get, i915_cache_sharing_set,
2118 "%llu\n");
2119
2120/* As the drm_debugfs_init() routines are called before dev->dev_private is
2121 * allocated we need to hook into the minor for release. */
2122static int
2123drm_add_fake_info_node(struct drm_minor *minor,
2124 struct dentry *ent,
2125 const void *key)
2126{
2127 struct drm_info_node *node;
2128
2129 node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
2130 if (node == NULL) {
2131 debugfs_remove(ent);
2132 return -ENOMEM;
2133 }
2134
2135 node->minor = minor;
2136 node->dent = ent;
2137 node->info_ent = (void *) key;
2138
2139 mutex_lock(&minor->debugfs_lock);
2140 list_add(&node->list, &minor->debugfs_list);
2141 mutex_unlock(&minor->debugfs_lock);
2142
2143 return 0;
2144}
2145
2146static int i915_forcewake_open(struct inode *inode, struct file *file)
2147{
2148 struct drm_device *dev = inode->i_private;
2149 struct drm_i915_private *dev_priv = dev->dev_private;
2150
2151 if (INTEL_INFO(dev)->gen < 6)
2152 return 0;
2153
2154 gen6_gt_force_wake_get(dev_priv);
2155
2156 return 0;
2157}
2158
2159static int i915_forcewake_release(struct inode *inode, struct file *file)
2160{
2161 struct drm_device *dev = inode->i_private;
2162 struct drm_i915_private *dev_priv = dev->dev_private;
2163
2164 if (INTEL_INFO(dev)->gen < 6)
2165 return 0;
2166
2167 gen6_gt_force_wake_put(dev_priv);
2168
2169 return 0;
2170}
2171
2172static const struct file_operations i915_forcewake_fops = {
2173 .owner = THIS_MODULE,
2174 .open = i915_forcewake_open,
2175 .release = i915_forcewake_release,
2176};
2177
2178static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
2179{
2180 struct drm_device *dev = minor->dev;
2181 struct dentry *ent;
2182
2183 ent = debugfs_create_file("i915_forcewake_user",
2184 S_IRUSR,
2185 root, dev,
2186 &i915_forcewake_fops);
2187 if (IS_ERR(ent))
2188 return PTR_ERR(ent);
2189
2190 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
2191}
2192
2193static int i915_debugfs_create(struct dentry *root,
2194 struct drm_minor *minor,
2195 const char *name,
2196 const struct file_operations *fops)
2197{
2198 struct drm_device *dev = minor->dev;
2199 struct dentry *ent;
2200
2201 ent = debugfs_create_file(name,
2202 S_IRUGO | S_IWUSR,
2203 root, dev,
2204 fops);
2205 if (IS_ERR(ent))
2206 return PTR_ERR(ent);
2207
2208 return drm_add_fake_info_node(minor, ent, fops);
2209}
2210
2211static struct drm_info_list i915_debugfs_list[] = {
2212 {"i915_capabilities", i915_capabilities, 0},
2213 {"i915_gem_objects", i915_gem_object_info, 0},
2214 {"i915_gem_gtt", i915_gem_gtt_info, 0},
2215 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
2216 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
2217 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
2218 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2219 {"i915_gem_request", i915_gem_request_info, 0},
2220 {"i915_gem_seqno", i915_gem_seqno_info, 0},
2221 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2222 {"i915_gem_interrupt", i915_interrupt_info, 0},
2223 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
2224 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
2225 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
2226 {"i915_rstdby_delays", i915_rstdby_delays, 0},
2227 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
2228 {"i915_delayfreq_table", i915_delayfreq_table, 0},
2229 {"i915_inttoext_table", i915_inttoext_table, 0},
2230 {"i915_drpc_info", i915_drpc_info, 0},
2231 {"i915_emon_status", i915_emon_status, 0},
2232 {"i915_ring_freq_table", i915_ring_freq_table, 0},
2233 {"i915_gfxec", i915_gfxec, 0},
2234 {"i915_fbc_status", i915_fbc_status, 0},
2235 {"i915_sr_status", i915_sr_status, 0},
2236 {"i915_opregion", i915_opregion, 0},
2237 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
2238 {"i915_context_status", i915_context_status, 0},
2239 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
2240 {"i915_swizzle_info", i915_swizzle_info, 0},
2241 {"i915_ppgtt_info", i915_ppgtt_info, 0},
2242 {"i915_dpio", i915_dpio_info, 0},
2243};
2244#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2245
2246int i915_debugfs_init(struct drm_minor *minor)
2247{
2248 int ret;
2249
2250 ret = i915_debugfs_create(minor->debugfs_root, minor,
2251 "i915_wedged",
2252 &i915_wedged_fops);
2253 if (ret)
2254 return ret;
2255
2256 ret = i915_forcewake_create(minor->debugfs_root, minor);
2257 if (ret)
2258 return ret;
2259
2260 ret = i915_debugfs_create(minor->debugfs_root, minor,
2261 "i915_max_freq",
2262 &i915_max_freq_fops);
2263 if (ret)
2264 return ret;
2265
2266 ret = i915_debugfs_create(minor->debugfs_root, minor,
2267 "i915_min_freq",
2268 &i915_min_freq_fops);
2269 if (ret)
2270 return ret;
2271
2272 ret = i915_debugfs_create(minor->debugfs_root, minor,
2273 "i915_cache_sharing",
2274 &i915_cache_sharing_fops);
2275 if (ret)
2276 return ret;
2277
2278 ret = i915_debugfs_create(minor->debugfs_root, minor,
2279 "i915_ring_stop",
2280 &i915_ring_stop_fops);
2281 if (ret)
2282 return ret;
2283
2284 ret = i915_debugfs_create(minor->debugfs_root, minor,
2285 "i915_gem_drop_caches",
2286 &i915_drop_caches_fops);
2287 if (ret)
2288 return ret;
2289
2290 ret = i915_debugfs_create(minor->debugfs_root, minor,
2291 "i915_error_state",
2292 &i915_error_state_fops);
2293 if (ret)
2294 return ret;
2295
2296 ret = i915_debugfs_create(minor->debugfs_root, minor,
2297 "i915_next_seqno",
2298 &i915_next_seqno_fops);
2299 if (ret)
2300 return ret;
2301
2302 return drm_debugfs_create_files(i915_debugfs_list,
2303 I915_DEBUGFS_ENTRIES,
2304 minor->debugfs_root, minor);
2305}
2306
2307void i915_debugfs_cleanup(struct drm_minor *minor)
2308{
2309 drm_debugfs_remove_files(i915_debugfs_list,
2310 I915_DEBUGFS_ENTRIES, minor);
2311 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
2312 1, minor);
2313 drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
2314 1, minor);
2315 drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops,
2316 1, minor);
2317 drm_debugfs_remove_files((struct drm_info_list *) &i915_min_freq_fops,
2318 1, minor);
2319 drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops,
2320 1, minor);
2321 drm_debugfs_remove_files((struct drm_info_list *) &i915_drop_caches_fops,
2322 1, minor);
2323 drm_debugfs_remove_files((struct drm_info_list *) &i915_ring_stop_fops,
2324 1, minor);
2325 drm_debugfs_remove_files((struct drm_info_list *) &i915_error_state_fops,
2326 1, minor);
2327 drm_debugfs_remove_files((struct drm_info_list *) &i915_next_seqno_fops,
2328 1, minor);
2329}
2330
2331#endif /* CONFIG_DEBUG_FS */
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