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1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
30#include <linux/circ_buf.h>
31#include <linux/ctype.h>
32#include <linux/debugfs.h>
33#include <linux/slab.h>
34#include <linux/export.h>
35#include <linux/list_sort.h>
36#include <asm/msr-index.h>
37#include <drm/drmP.h>
38#include "intel_drv.h"
39#include "intel_ringbuffer.h"
40#include <drm/i915_drm.h>
41#include "i915_drv.h"
42
43static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
44{
45 return to_i915(node->minor->dev);
46}
47
48/* As the drm_debugfs_init() routines are called before dev->dev_private is
49 * allocated we need to hook into the minor for release. */
50static int
51drm_add_fake_info_node(struct drm_minor *minor,
52 struct dentry *ent,
53 const void *key)
54{
55 struct drm_info_node *node;
56
57 node = kmalloc(sizeof(*node), GFP_KERNEL);
58 if (node == NULL) {
59 debugfs_remove(ent);
60 return -ENOMEM;
61 }
62
63 node->minor = minor;
64 node->dent = ent;
65 node->info_ent = (void *)key;
66
67 mutex_lock(&minor->debugfs_lock);
68 list_add(&node->list, &minor->debugfs_list);
69 mutex_unlock(&minor->debugfs_lock);
70
71 return 0;
72}
73
74static int i915_capabilities(struct seq_file *m, void *data)
75{
76 struct drm_i915_private *dev_priv = node_to_i915(m->private);
77 const struct intel_device_info *info = INTEL_INFO(dev_priv);
78
79 seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
80 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
81#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
82 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
83#undef PRINT_FLAG
84
85 return 0;
86}
87
88static char get_active_flag(struct drm_i915_gem_object *obj)
89{
90 return i915_gem_object_is_active(obj) ? '*' : ' ';
91}
92
93static char get_pin_flag(struct drm_i915_gem_object *obj)
94{
95 return obj->pin_display ? 'p' : ' ';
96}
97
98static char get_tiling_flag(struct drm_i915_gem_object *obj)
99{
100 switch (i915_gem_object_get_tiling(obj)) {
101 default:
102 case I915_TILING_NONE: return ' ';
103 case I915_TILING_X: return 'X';
104 case I915_TILING_Y: return 'Y';
105 }
106}
107
108static char get_global_flag(struct drm_i915_gem_object *obj)
109{
110 return !list_empty(&obj->userfault_link) ? 'g' : ' ';
111}
112
113static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
114{
115 return obj->mm.mapping ? 'M' : ' ';
116}
117
118static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
119{
120 u64 size = 0;
121 struct i915_vma *vma;
122
123 list_for_each_entry(vma, &obj->vma_list, obj_link) {
124 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
125 size += vma->node.size;
126 }
127
128 return size;
129}
130
131static void
132describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
133{
134 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
135 struct intel_engine_cs *engine;
136 struct i915_vma *vma;
137 unsigned int frontbuffer_bits;
138 int pin_count = 0;
139
140 lockdep_assert_held(&obj->base.dev->struct_mutex);
141
142 seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s",
143 &obj->base,
144 get_active_flag(obj),
145 get_pin_flag(obj),
146 get_tiling_flag(obj),
147 get_global_flag(obj),
148 get_pin_mapped_flag(obj),
149 obj->base.size / 1024,
150 obj->base.read_domains,
151 obj->base.write_domain,
152 i915_cache_level_str(dev_priv, obj->cache_level),
153 obj->mm.dirty ? " dirty" : "",
154 obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
155 if (obj->base.name)
156 seq_printf(m, " (name: %d)", obj->base.name);
157 list_for_each_entry(vma, &obj->vma_list, obj_link) {
158 if (i915_vma_is_pinned(vma))
159 pin_count++;
160 }
161 seq_printf(m, " (pinned x %d)", pin_count);
162 if (obj->pin_display)
163 seq_printf(m, " (display)");
164 list_for_each_entry(vma, &obj->vma_list, obj_link) {
165 if (!drm_mm_node_allocated(&vma->node))
166 continue;
167
168 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
169 i915_vma_is_ggtt(vma) ? "g" : "pp",
170 vma->node.start, vma->node.size);
171 if (i915_vma_is_ggtt(vma))
172 seq_printf(m, ", type: %u", vma->ggtt_view.type);
173 if (vma->fence)
174 seq_printf(m, " , fence: %d%s",
175 vma->fence->id,
176 i915_gem_active_isset(&vma->last_fence) ? "*" : "");
177 seq_puts(m, ")");
178 }
179 if (obj->stolen)
180 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
181
182 engine = i915_gem_object_last_write_engine(obj);
183 if (engine)
184 seq_printf(m, " (%s)", engine->name);
185
186 frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
187 if (frontbuffer_bits)
188 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
189}
190
191static int obj_rank_by_stolen(void *priv,
192 struct list_head *A, struct list_head *B)
193{
194 struct drm_i915_gem_object *a =
195 container_of(A, struct drm_i915_gem_object, obj_exec_link);
196 struct drm_i915_gem_object *b =
197 container_of(B, struct drm_i915_gem_object, obj_exec_link);
198
199 if (a->stolen->start < b->stolen->start)
200 return -1;
201 if (a->stolen->start > b->stolen->start)
202 return 1;
203 return 0;
204}
205
206static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
207{
208 struct drm_i915_private *dev_priv = node_to_i915(m->private);
209 struct drm_device *dev = &dev_priv->drm;
210 struct drm_i915_gem_object *obj;
211 u64 total_obj_size, total_gtt_size;
212 LIST_HEAD(stolen);
213 int count, ret;
214
215 ret = mutex_lock_interruptible(&dev->struct_mutex);
216 if (ret)
217 return ret;
218
219 total_obj_size = total_gtt_size = count = 0;
220 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
221 if (obj->stolen == NULL)
222 continue;
223
224 list_add(&obj->obj_exec_link, &stolen);
225
226 total_obj_size += obj->base.size;
227 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
228 count++;
229 }
230 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
231 if (obj->stolen == NULL)
232 continue;
233
234 list_add(&obj->obj_exec_link, &stolen);
235
236 total_obj_size += obj->base.size;
237 count++;
238 }
239 list_sort(NULL, &stolen, obj_rank_by_stolen);
240 seq_puts(m, "Stolen:\n");
241 while (!list_empty(&stolen)) {
242 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
243 seq_puts(m, " ");
244 describe_obj(m, obj);
245 seq_putc(m, '\n');
246 list_del_init(&obj->obj_exec_link);
247 }
248 mutex_unlock(&dev->struct_mutex);
249
250 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
251 count, total_obj_size, total_gtt_size);
252 return 0;
253}
254
255struct file_stats {
256 struct drm_i915_file_private *file_priv;
257 unsigned long count;
258 u64 total, unbound;
259 u64 global, shared;
260 u64 active, inactive;
261};
262
263static int per_file_stats(int id, void *ptr, void *data)
264{
265 struct drm_i915_gem_object *obj = ptr;
266 struct file_stats *stats = data;
267 struct i915_vma *vma;
268
269 stats->count++;
270 stats->total += obj->base.size;
271 if (!obj->bind_count)
272 stats->unbound += obj->base.size;
273 if (obj->base.name || obj->base.dma_buf)
274 stats->shared += obj->base.size;
275
276 list_for_each_entry(vma, &obj->vma_list, obj_link) {
277 if (!drm_mm_node_allocated(&vma->node))
278 continue;
279
280 if (i915_vma_is_ggtt(vma)) {
281 stats->global += vma->node.size;
282 } else {
283 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
284
285 if (ppgtt->base.file != stats->file_priv)
286 continue;
287 }
288
289 if (i915_vma_is_active(vma))
290 stats->active += vma->node.size;
291 else
292 stats->inactive += vma->node.size;
293 }
294
295 return 0;
296}
297
298#define print_file_stats(m, name, stats) do { \
299 if (stats.count) \
300 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
301 name, \
302 stats.count, \
303 stats.total, \
304 stats.active, \
305 stats.inactive, \
306 stats.global, \
307 stats.shared, \
308 stats.unbound); \
309} while (0)
310
311static void print_batch_pool_stats(struct seq_file *m,
312 struct drm_i915_private *dev_priv)
313{
314 struct drm_i915_gem_object *obj;
315 struct file_stats stats;
316 struct intel_engine_cs *engine;
317 enum intel_engine_id id;
318 int j;
319
320 memset(&stats, 0, sizeof(stats));
321
322 for_each_engine(engine, dev_priv, id) {
323 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
324 list_for_each_entry(obj,
325 &engine->batch_pool.cache_list[j],
326 batch_pool_link)
327 per_file_stats(0, obj, &stats);
328 }
329 }
330
331 print_file_stats(m, "[k]batch pool", stats);
332}
333
334static int per_file_ctx_stats(int id, void *ptr, void *data)
335{
336 struct i915_gem_context *ctx = ptr;
337 int n;
338
339 for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
340 if (ctx->engine[n].state)
341 per_file_stats(0, ctx->engine[n].state->obj, data);
342 if (ctx->engine[n].ring)
343 per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
344 }
345
346 return 0;
347}
348
349static void print_context_stats(struct seq_file *m,
350 struct drm_i915_private *dev_priv)
351{
352 struct drm_device *dev = &dev_priv->drm;
353 struct file_stats stats;
354 struct drm_file *file;
355
356 memset(&stats, 0, sizeof(stats));
357
358 mutex_lock(&dev->struct_mutex);
359 if (dev_priv->kernel_context)
360 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
361
362 list_for_each_entry(file, &dev->filelist, lhead) {
363 struct drm_i915_file_private *fpriv = file->driver_priv;
364 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
365 }
366 mutex_unlock(&dev->struct_mutex);
367
368 print_file_stats(m, "[k]contexts", stats);
369}
370
371static int i915_gem_object_info(struct seq_file *m, void *data)
372{
373 struct drm_i915_private *dev_priv = node_to_i915(m->private);
374 struct drm_device *dev = &dev_priv->drm;
375 struct i915_ggtt *ggtt = &dev_priv->ggtt;
376 u32 count, mapped_count, purgeable_count, dpy_count;
377 u64 size, mapped_size, purgeable_size, dpy_size;
378 struct drm_i915_gem_object *obj;
379 struct drm_file *file;
380 int ret;
381
382 ret = mutex_lock_interruptible(&dev->struct_mutex);
383 if (ret)
384 return ret;
385
386 seq_printf(m, "%u objects, %llu bytes\n",
387 dev_priv->mm.object_count,
388 dev_priv->mm.object_memory);
389
390 size = count = 0;
391 mapped_size = mapped_count = 0;
392 purgeable_size = purgeable_count = 0;
393 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
394 size += obj->base.size;
395 ++count;
396
397 if (obj->mm.madv == I915_MADV_DONTNEED) {
398 purgeable_size += obj->base.size;
399 ++purgeable_count;
400 }
401
402 if (obj->mm.mapping) {
403 mapped_count++;
404 mapped_size += obj->base.size;
405 }
406 }
407 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
408
409 size = count = dpy_size = dpy_count = 0;
410 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
411 size += obj->base.size;
412 ++count;
413
414 if (obj->pin_display) {
415 dpy_size += obj->base.size;
416 ++dpy_count;
417 }
418
419 if (obj->mm.madv == I915_MADV_DONTNEED) {
420 purgeable_size += obj->base.size;
421 ++purgeable_count;
422 }
423
424 if (obj->mm.mapping) {
425 mapped_count++;
426 mapped_size += obj->base.size;
427 }
428 }
429 seq_printf(m, "%u bound objects, %llu bytes\n",
430 count, size);
431 seq_printf(m, "%u purgeable objects, %llu bytes\n",
432 purgeable_count, purgeable_size);
433 seq_printf(m, "%u mapped objects, %llu bytes\n",
434 mapped_count, mapped_size);
435 seq_printf(m, "%u display objects (pinned), %llu bytes\n",
436 dpy_count, dpy_size);
437
438 seq_printf(m, "%llu [%llu] gtt total\n",
439 ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
440
441 seq_putc(m, '\n');
442 print_batch_pool_stats(m, dev_priv);
443 mutex_unlock(&dev->struct_mutex);
444
445 mutex_lock(&dev->filelist_mutex);
446 print_context_stats(m, dev_priv);
447 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
448 struct file_stats stats;
449 struct drm_i915_file_private *file_priv = file->driver_priv;
450 struct drm_i915_gem_request *request;
451 struct task_struct *task;
452
453 memset(&stats, 0, sizeof(stats));
454 stats.file_priv = file->driver_priv;
455 spin_lock(&file->table_lock);
456 idr_for_each(&file->object_idr, per_file_stats, &stats);
457 spin_unlock(&file->table_lock);
458 /*
459 * Although we have a valid reference on file->pid, that does
460 * not guarantee that the task_struct who called get_pid() is
461 * still alive (e.g. get_pid(current) => fork() => exit()).
462 * Therefore, we need to protect this ->comm access using RCU.
463 */
464 mutex_lock(&dev->struct_mutex);
465 request = list_first_entry_or_null(&file_priv->mm.request_list,
466 struct drm_i915_gem_request,
467 client_list);
468 rcu_read_lock();
469 task = pid_task(request && request->ctx->pid ?
470 request->ctx->pid : file->pid,
471 PIDTYPE_PID);
472 print_file_stats(m, task ? task->comm : "<unknown>", stats);
473 rcu_read_unlock();
474 mutex_unlock(&dev->struct_mutex);
475 }
476 mutex_unlock(&dev->filelist_mutex);
477
478 return 0;
479}
480
481static int i915_gem_gtt_info(struct seq_file *m, void *data)
482{
483 struct drm_info_node *node = m->private;
484 struct drm_i915_private *dev_priv = node_to_i915(node);
485 struct drm_device *dev = &dev_priv->drm;
486 bool show_pin_display_only = !!node->info_ent->data;
487 struct drm_i915_gem_object *obj;
488 u64 total_obj_size, total_gtt_size;
489 int count, ret;
490
491 ret = mutex_lock_interruptible(&dev->struct_mutex);
492 if (ret)
493 return ret;
494
495 total_obj_size = total_gtt_size = count = 0;
496 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
497 if (show_pin_display_only && !obj->pin_display)
498 continue;
499
500 seq_puts(m, " ");
501 describe_obj(m, obj);
502 seq_putc(m, '\n');
503 total_obj_size += obj->base.size;
504 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
505 count++;
506 }
507
508 mutex_unlock(&dev->struct_mutex);
509
510 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
511 count, total_obj_size, total_gtt_size);
512
513 return 0;
514}
515
516static int i915_gem_pageflip_info(struct seq_file *m, void *data)
517{
518 struct drm_i915_private *dev_priv = node_to_i915(m->private);
519 struct drm_device *dev = &dev_priv->drm;
520 struct intel_crtc *crtc;
521 int ret;
522
523 ret = mutex_lock_interruptible(&dev->struct_mutex);
524 if (ret)
525 return ret;
526
527 for_each_intel_crtc(dev, crtc) {
528 const char pipe = pipe_name(crtc->pipe);
529 const char plane = plane_name(crtc->plane);
530 struct intel_flip_work *work;
531
532 spin_lock_irq(&dev->event_lock);
533 work = crtc->flip_work;
534 if (work == NULL) {
535 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
536 pipe, plane);
537 } else {
538 u32 pending;
539 u32 addr;
540
541 pending = atomic_read(&work->pending);
542 if (pending) {
543 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
544 pipe, plane);
545 } else {
546 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
547 pipe, plane);
548 }
549 if (work->flip_queued_req) {
550 struct intel_engine_cs *engine = work->flip_queued_req->engine;
551
552 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
553 engine->name,
554 work->flip_queued_req->global_seqno,
555 atomic_read(&dev_priv->gt.global_timeline.next_seqno),
556 intel_engine_get_seqno(engine),
557 i915_gem_request_completed(work->flip_queued_req));
558 } else
559 seq_printf(m, "Flip not associated with any ring\n");
560 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
561 work->flip_queued_vblank,
562 work->flip_ready_vblank,
563 intel_crtc_get_vblank_counter(crtc));
564 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
565
566 if (INTEL_GEN(dev_priv) >= 4)
567 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
568 else
569 addr = I915_READ(DSPADDR(crtc->plane));
570 seq_printf(m, "Current scanout address 0x%08x\n", addr);
571
572 if (work->pending_flip_obj) {
573 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
574 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
575 }
576 }
577 spin_unlock_irq(&dev->event_lock);
578 }
579
580 mutex_unlock(&dev->struct_mutex);
581
582 return 0;
583}
584
585static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
586{
587 struct drm_i915_private *dev_priv = node_to_i915(m->private);
588 struct drm_device *dev = &dev_priv->drm;
589 struct drm_i915_gem_object *obj;
590 struct intel_engine_cs *engine;
591 enum intel_engine_id id;
592 int total = 0;
593 int ret, j;
594
595 ret = mutex_lock_interruptible(&dev->struct_mutex);
596 if (ret)
597 return ret;
598
599 for_each_engine(engine, dev_priv, id) {
600 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
601 int count;
602
603 count = 0;
604 list_for_each_entry(obj,
605 &engine->batch_pool.cache_list[j],
606 batch_pool_link)
607 count++;
608 seq_printf(m, "%s cache[%d]: %d objects\n",
609 engine->name, j, count);
610
611 list_for_each_entry(obj,
612 &engine->batch_pool.cache_list[j],
613 batch_pool_link) {
614 seq_puts(m, " ");
615 describe_obj(m, obj);
616 seq_putc(m, '\n');
617 }
618
619 total += count;
620 }
621 }
622
623 seq_printf(m, "total: %d\n", total);
624
625 mutex_unlock(&dev->struct_mutex);
626
627 return 0;
628}
629
630static void print_request(struct seq_file *m,
631 struct drm_i915_gem_request *rq,
632 const char *prefix)
633{
634 seq_printf(m, "%s%x [%x:%x] prio=%d @ %dms: %s\n", prefix,
635 rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno,
636 rq->priotree.priority,
637 jiffies_to_msecs(jiffies - rq->emitted_jiffies),
638 rq->timeline->common->name);
639}
640
641static int i915_gem_request_info(struct seq_file *m, void *data)
642{
643 struct drm_i915_private *dev_priv = node_to_i915(m->private);
644 struct drm_device *dev = &dev_priv->drm;
645 struct drm_i915_gem_request *req;
646 struct intel_engine_cs *engine;
647 enum intel_engine_id id;
648 int ret, any;
649
650 ret = mutex_lock_interruptible(&dev->struct_mutex);
651 if (ret)
652 return ret;
653
654 any = 0;
655 for_each_engine(engine, dev_priv, id) {
656 int count;
657
658 count = 0;
659 list_for_each_entry(req, &engine->timeline->requests, link)
660 count++;
661 if (count == 0)
662 continue;
663
664 seq_printf(m, "%s requests: %d\n", engine->name, count);
665 list_for_each_entry(req, &engine->timeline->requests, link)
666 print_request(m, req, " ");
667
668 any++;
669 }
670 mutex_unlock(&dev->struct_mutex);
671
672 if (any == 0)
673 seq_puts(m, "No requests\n");
674
675 return 0;
676}
677
678static void i915_ring_seqno_info(struct seq_file *m,
679 struct intel_engine_cs *engine)
680{
681 struct intel_breadcrumbs *b = &engine->breadcrumbs;
682 struct rb_node *rb;
683
684 seq_printf(m, "Current sequence (%s): %x\n",
685 engine->name, intel_engine_get_seqno(engine));
686
687 spin_lock_irq(&b->lock);
688 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
689 struct intel_wait *w = container_of(rb, typeof(*w), node);
690
691 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
692 engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
693 }
694 spin_unlock_irq(&b->lock);
695}
696
697static int i915_gem_seqno_info(struct seq_file *m, void *data)
698{
699 struct drm_i915_private *dev_priv = node_to_i915(m->private);
700 struct intel_engine_cs *engine;
701 enum intel_engine_id id;
702
703 for_each_engine(engine, dev_priv, id)
704 i915_ring_seqno_info(m, engine);
705
706 return 0;
707}
708
709
710static int i915_interrupt_info(struct seq_file *m, void *data)
711{
712 struct drm_i915_private *dev_priv = node_to_i915(m->private);
713 struct intel_engine_cs *engine;
714 enum intel_engine_id id;
715 int i, pipe;
716
717 intel_runtime_pm_get(dev_priv);
718
719 if (IS_CHERRYVIEW(dev_priv)) {
720 seq_printf(m, "Master Interrupt Control:\t%08x\n",
721 I915_READ(GEN8_MASTER_IRQ));
722
723 seq_printf(m, "Display IER:\t%08x\n",
724 I915_READ(VLV_IER));
725 seq_printf(m, "Display IIR:\t%08x\n",
726 I915_READ(VLV_IIR));
727 seq_printf(m, "Display IIR_RW:\t%08x\n",
728 I915_READ(VLV_IIR_RW));
729 seq_printf(m, "Display IMR:\t%08x\n",
730 I915_READ(VLV_IMR));
731 for_each_pipe(dev_priv, pipe) {
732 enum intel_display_power_domain power_domain;
733
734 power_domain = POWER_DOMAIN_PIPE(pipe);
735 if (!intel_display_power_get_if_enabled(dev_priv,
736 power_domain)) {
737 seq_printf(m, "Pipe %c power disabled\n",
738 pipe_name(pipe));
739 continue;
740 }
741
742 seq_printf(m, "Pipe %c stat:\t%08x\n",
743 pipe_name(pipe),
744 I915_READ(PIPESTAT(pipe)));
745
746 intel_display_power_put(dev_priv, power_domain);
747 }
748
749 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
750 seq_printf(m, "Port hotplug:\t%08x\n",
751 I915_READ(PORT_HOTPLUG_EN));
752 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
753 I915_READ(VLV_DPFLIPSTAT));
754 seq_printf(m, "DPINVGTT:\t%08x\n",
755 I915_READ(DPINVGTT));
756 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
757
758 for (i = 0; i < 4; i++) {
759 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
760 i, I915_READ(GEN8_GT_IMR(i)));
761 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
762 i, I915_READ(GEN8_GT_IIR(i)));
763 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
764 i, I915_READ(GEN8_GT_IER(i)));
765 }
766
767 seq_printf(m, "PCU interrupt mask:\t%08x\n",
768 I915_READ(GEN8_PCU_IMR));
769 seq_printf(m, "PCU interrupt identity:\t%08x\n",
770 I915_READ(GEN8_PCU_IIR));
771 seq_printf(m, "PCU interrupt enable:\t%08x\n",
772 I915_READ(GEN8_PCU_IER));
773 } else if (INTEL_GEN(dev_priv) >= 8) {
774 seq_printf(m, "Master Interrupt Control:\t%08x\n",
775 I915_READ(GEN8_MASTER_IRQ));
776
777 for (i = 0; i < 4; i++) {
778 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
779 i, I915_READ(GEN8_GT_IMR(i)));
780 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
781 i, I915_READ(GEN8_GT_IIR(i)));
782 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
783 i, I915_READ(GEN8_GT_IER(i)));
784 }
785
786 for_each_pipe(dev_priv, pipe) {
787 enum intel_display_power_domain power_domain;
788
789 power_domain = POWER_DOMAIN_PIPE(pipe);
790 if (!intel_display_power_get_if_enabled(dev_priv,
791 power_domain)) {
792 seq_printf(m, "Pipe %c power disabled\n",
793 pipe_name(pipe));
794 continue;
795 }
796 seq_printf(m, "Pipe %c IMR:\t%08x\n",
797 pipe_name(pipe),
798 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
799 seq_printf(m, "Pipe %c IIR:\t%08x\n",
800 pipe_name(pipe),
801 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
802 seq_printf(m, "Pipe %c IER:\t%08x\n",
803 pipe_name(pipe),
804 I915_READ(GEN8_DE_PIPE_IER(pipe)));
805
806 intel_display_power_put(dev_priv, power_domain);
807 }
808
809 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
810 I915_READ(GEN8_DE_PORT_IMR));
811 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
812 I915_READ(GEN8_DE_PORT_IIR));
813 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
814 I915_READ(GEN8_DE_PORT_IER));
815
816 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
817 I915_READ(GEN8_DE_MISC_IMR));
818 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
819 I915_READ(GEN8_DE_MISC_IIR));
820 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
821 I915_READ(GEN8_DE_MISC_IER));
822
823 seq_printf(m, "PCU interrupt mask:\t%08x\n",
824 I915_READ(GEN8_PCU_IMR));
825 seq_printf(m, "PCU interrupt identity:\t%08x\n",
826 I915_READ(GEN8_PCU_IIR));
827 seq_printf(m, "PCU interrupt enable:\t%08x\n",
828 I915_READ(GEN8_PCU_IER));
829 } else if (IS_VALLEYVIEW(dev_priv)) {
830 seq_printf(m, "Display IER:\t%08x\n",
831 I915_READ(VLV_IER));
832 seq_printf(m, "Display IIR:\t%08x\n",
833 I915_READ(VLV_IIR));
834 seq_printf(m, "Display IIR_RW:\t%08x\n",
835 I915_READ(VLV_IIR_RW));
836 seq_printf(m, "Display IMR:\t%08x\n",
837 I915_READ(VLV_IMR));
838 for_each_pipe(dev_priv, pipe)
839 seq_printf(m, "Pipe %c stat:\t%08x\n",
840 pipe_name(pipe),
841 I915_READ(PIPESTAT(pipe)));
842
843 seq_printf(m, "Master IER:\t%08x\n",
844 I915_READ(VLV_MASTER_IER));
845
846 seq_printf(m, "Render IER:\t%08x\n",
847 I915_READ(GTIER));
848 seq_printf(m, "Render IIR:\t%08x\n",
849 I915_READ(GTIIR));
850 seq_printf(m, "Render IMR:\t%08x\n",
851 I915_READ(GTIMR));
852
853 seq_printf(m, "PM IER:\t\t%08x\n",
854 I915_READ(GEN6_PMIER));
855 seq_printf(m, "PM IIR:\t\t%08x\n",
856 I915_READ(GEN6_PMIIR));
857 seq_printf(m, "PM IMR:\t\t%08x\n",
858 I915_READ(GEN6_PMIMR));
859
860 seq_printf(m, "Port hotplug:\t%08x\n",
861 I915_READ(PORT_HOTPLUG_EN));
862 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
863 I915_READ(VLV_DPFLIPSTAT));
864 seq_printf(m, "DPINVGTT:\t%08x\n",
865 I915_READ(DPINVGTT));
866
867 } else if (!HAS_PCH_SPLIT(dev_priv)) {
868 seq_printf(m, "Interrupt enable: %08x\n",
869 I915_READ(IER));
870 seq_printf(m, "Interrupt identity: %08x\n",
871 I915_READ(IIR));
872 seq_printf(m, "Interrupt mask: %08x\n",
873 I915_READ(IMR));
874 for_each_pipe(dev_priv, pipe)
875 seq_printf(m, "Pipe %c stat: %08x\n",
876 pipe_name(pipe),
877 I915_READ(PIPESTAT(pipe)));
878 } else {
879 seq_printf(m, "North Display Interrupt enable: %08x\n",
880 I915_READ(DEIER));
881 seq_printf(m, "North Display Interrupt identity: %08x\n",
882 I915_READ(DEIIR));
883 seq_printf(m, "North Display Interrupt mask: %08x\n",
884 I915_READ(DEIMR));
885 seq_printf(m, "South Display Interrupt enable: %08x\n",
886 I915_READ(SDEIER));
887 seq_printf(m, "South Display Interrupt identity: %08x\n",
888 I915_READ(SDEIIR));
889 seq_printf(m, "South Display Interrupt mask: %08x\n",
890 I915_READ(SDEIMR));
891 seq_printf(m, "Graphics Interrupt enable: %08x\n",
892 I915_READ(GTIER));
893 seq_printf(m, "Graphics Interrupt identity: %08x\n",
894 I915_READ(GTIIR));
895 seq_printf(m, "Graphics Interrupt mask: %08x\n",
896 I915_READ(GTIMR));
897 }
898 for_each_engine(engine, dev_priv, id) {
899 if (INTEL_GEN(dev_priv) >= 6) {
900 seq_printf(m,
901 "Graphics Interrupt mask (%s): %08x\n",
902 engine->name, I915_READ_IMR(engine));
903 }
904 i915_ring_seqno_info(m, engine);
905 }
906 intel_runtime_pm_put(dev_priv);
907
908 return 0;
909}
910
911static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
912{
913 struct drm_i915_private *dev_priv = node_to_i915(m->private);
914 struct drm_device *dev = &dev_priv->drm;
915 int i, ret;
916
917 ret = mutex_lock_interruptible(&dev->struct_mutex);
918 if (ret)
919 return ret;
920
921 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
922 for (i = 0; i < dev_priv->num_fence_regs; i++) {
923 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
924
925 seq_printf(m, "Fence %d, pin count = %d, object = ",
926 i, dev_priv->fence_regs[i].pin_count);
927 if (!vma)
928 seq_puts(m, "unused");
929 else
930 describe_obj(m, vma->obj);
931 seq_putc(m, '\n');
932 }
933
934 mutex_unlock(&dev->struct_mutex);
935 return 0;
936}
937
938#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
939
940static ssize_t
941i915_error_state_write(struct file *filp,
942 const char __user *ubuf,
943 size_t cnt,
944 loff_t *ppos)
945{
946 struct i915_error_state_file_priv *error_priv = filp->private_data;
947
948 DRM_DEBUG_DRIVER("Resetting error state\n");
949 i915_destroy_error_state(error_priv->dev);
950
951 return cnt;
952}
953
954static int i915_error_state_open(struct inode *inode, struct file *file)
955{
956 struct drm_i915_private *dev_priv = inode->i_private;
957 struct i915_error_state_file_priv *error_priv;
958
959 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
960 if (!error_priv)
961 return -ENOMEM;
962
963 error_priv->dev = &dev_priv->drm;
964
965 i915_error_state_get(&dev_priv->drm, error_priv);
966
967 file->private_data = error_priv;
968
969 return 0;
970}
971
972static int i915_error_state_release(struct inode *inode, struct file *file)
973{
974 struct i915_error_state_file_priv *error_priv = file->private_data;
975
976 i915_error_state_put(error_priv);
977 kfree(error_priv);
978
979 return 0;
980}
981
982static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
983 size_t count, loff_t *pos)
984{
985 struct i915_error_state_file_priv *error_priv = file->private_data;
986 struct drm_i915_error_state_buf error_str;
987 loff_t tmp_pos = 0;
988 ssize_t ret_count = 0;
989 int ret;
990
991 ret = i915_error_state_buf_init(&error_str,
992 to_i915(error_priv->dev), count, *pos);
993 if (ret)
994 return ret;
995
996 ret = i915_error_state_to_str(&error_str, error_priv);
997 if (ret)
998 goto out;
999
1000 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1001 error_str.buf,
1002 error_str.bytes);
1003
1004 if (ret_count < 0)
1005 ret = ret_count;
1006 else
1007 *pos = error_str.start + ret_count;
1008out:
1009 i915_error_state_buf_release(&error_str);
1010 return ret ?: ret_count;
1011}
1012
1013static const struct file_operations i915_error_state_fops = {
1014 .owner = THIS_MODULE,
1015 .open = i915_error_state_open,
1016 .read = i915_error_state_read,
1017 .write = i915_error_state_write,
1018 .llseek = default_llseek,
1019 .release = i915_error_state_release,
1020};
1021
1022#endif
1023
1024static int
1025i915_next_seqno_get(void *data, u64 *val)
1026{
1027 struct drm_i915_private *dev_priv = data;
1028
1029 *val = 1 + atomic_read(&dev_priv->gt.global_timeline.next_seqno);
1030 return 0;
1031}
1032
1033static int
1034i915_next_seqno_set(void *data, u64 val)
1035{
1036 struct drm_i915_private *dev_priv = data;
1037 struct drm_device *dev = &dev_priv->drm;
1038 int ret;
1039
1040 ret = mutex_lock_interruptible(&dev->struct_mutex);
1041 if (ret)
1042 return ret;
1043
1044 ret = i915_gem_set_global_seqno(dev, val);
1045 mutex_unlock(&dev->struct_mutex);
1046
1047 return ret;
1048}
1049
1050DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1051 i915_next_seqno_get, i915_next_seqno_set,
1052 "0x%llx\n");
1053
1054static int i915_frequency_info(struct seq_file *m, void *unused)
1055{
1056 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1057 struct drm_device *dev = &dev_priv->drm;
1058 int ret = 0;
1059
1060 intel_runtime_pm_get(dev_priv);
1061
1062 if (IS_GEN5(dev_priv)) {
1063 u16 rgvswctl = I915_READ16(MEMSWCTL);
1064 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1065
1066 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1067 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1068 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1069 MEMSTAT_VID_SHIFT);
1070 seq_printf(m, "Current P-state: %d\n",
1071 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1072 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1073 u32 freq_sts;
1074
1075 mutex_lock(&dev_priv->rps.hw_lock);
1076 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1077 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1078 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1079
1080 seq_printf(m, "actual GPU freq: %d MHz\n",
1081 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1082
1083 seq_printf(m, "current GPU freq: %d MHz\n",
1084 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1085
1086 seq_printf(m, "max GPU freq: %d MHz\n",
1087 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1088
1089 seq_printf(m, "min GPU freq: %d MHz\n",
1090 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1091
1092 seq_printf(m, "idle GPU freq: %d MHz\n",
1093 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1094
1095 seq_printf(m,
1096 "efficient (RPe) frequency: %d MHz\n",
1097 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1098 mutex_unlock(&dev_priv->rps.hw_lock);
1099 } else if (INTEL_GEN(dev_priv) >= 6) {
1100 u32 rp_state_limits;
1101 u32 gt_perf_status;
1102 u32 rp_state_cap;
1103 u32 rpmodectl, rpinclimit, rpdeclimit;
1104 u32 rpstat, cagf, reqf;
1105 u32 rpupei, rpcurup, rpprevup;
1106 u32 rpdownei, rpcurdown, rpprevdown;
1107 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1108 int max_freq;
1109
1110 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1111 if (IS_BROXTON(dev_priv)) {
1112 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1113 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1114 } else {
1115 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1116 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1117 }
1118
1119 /* RPSTAT1 is in the GT power well */
1120 ret = mutex_lock_interruptible(&dev->struct_mutex);
1121 if (ret)
1122 goto out;
1123
1124 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1125
1126 reqf = I915_READ(GEN6_RPNSWREQ);
1127 if (IS_GEN9(dev_priv))
1128 reqf >>= 23;
1129 else {
1130 reqf &= ~GEN6_TURBO_DISABLE;
1131 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1132 reqf >>= 24;
1133 else
1134 reqf >>= 25;
1135 }
1136 reqf = intel_gpu_freq(dev_priv, reqf);
1137
1138 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1139 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1140 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1141
1142 rpstat = I915_READ(GEN6_RPSTAT1);
1143 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1144 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1145 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1146 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1147 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1148 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1149 if (IS_GEN9(dev_priv))
1150 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1151 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1152 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1153 else
1154 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1155 cagf = intel_gpu_freq(dev_priv, cagf);
1156
1157 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1158 mutex_unlock(&dev->struct_mutex);
1159
1160 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1161 pm_ier = I915_READ(GEN6_PMIER);
1162 pm_imr = I915_READ(GEN6_PMIMR);
1163 pm_isr = I915_READ(GEN6_PMISR);
1164 pm_iir = I915_READ(GEN6_PMIIR);
1165 pm_mask = I915_READ(GEN6_PMINTRMSK);
1166 } else {
1167 pm_ier = I915_READ(GEN8_GT_IER(2));
1168 pm_imr = I915_READ(GEN8_GT_IMR(2));
1169 pm_isr = I915_READ(GEN8_GT_ISR(2));
1170 pm_iir = I915_READ(GEN8_GT_IIR(2));
1171 pm_mask = I915_READ(GEN6_PMINTRMSK);
1172 }
1173 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1174 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1175 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1176 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1177 seq_printf(m, "Render p-state ratio: %d\n",
1178 (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8);
1179 seq_printf(m, "Render p-state VID: %d\n",
1180 gt_perf_status & 0xff);
1181 seq_printf(m, "Render p-state limit: %d\n",
1182 rp_state_limits & 0xff);
1183 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1184 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1185 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1186 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1187 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1188 seq_printf(m, "CAGF: %dMHz\n", cagf);
1189 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1190 rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1191 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1192 rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1193 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1194 rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1195 seq_printf(m, "Up threshold: %d%%\n",
1196 dev_priv->rps.up_threshold);
1197
1198 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1199 rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1200 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1201 rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1202 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1203 rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1204 seq_printf(m, "Down threshold: %d%%\n",
1205 dev_priv->rps.down_threshold);
1206
1207 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
1208 rp_state_cap >> 16) & 0xff;
1209 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1210 GEN9_FREQ_SCALER : 1);
1211 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1212 intel_gpu_freq(dev_priv, max_freq));
1213
1214 max_freq = (rp_state_cap & 0xff00) >> 8;
1215 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1216 GEN9_FREQ_SCALER : 1);
1217 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1218 intel_gpu_freq(dev_priv, max_freq));
1219
1220 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
1221 rp_state_cap >> 0) & 0xff;
1222 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1223 GEN9_FREQ_SCALER : 1);
1224 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1225 intel_gpu_freq(dev_priv, max_freq));
1226 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1227 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1228
1229 seq_printf(m, "Current freq: %d MHz\n",
1230 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1231 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1232 seq_printf(m, "Idle freq: %d MHz\n",
1233 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1234 seq_printf(m, "Min freq: %d MHz\n",
1235 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1236 seq_printf(m, "Boost freq: %d MHz\n",
1237 intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1238 seq_printf(m, "Max freq: %d MHz\n",
1239 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1240 seq_printf(m,
1241 "efficient (RPe) frequency: %d MHz\n",
1242 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1243 } else {
1244 seq_puts(m, "no P-state info available\n");
1245 }
1246
1247 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1248 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1249 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1250
1251out:
1252 intel_runtime_pm_put(dev_priv);
1253 return ret;
1254}
1255
1256static void i915_instdone_info(struct drm_i915_private *dev_priv,
1257 struct seq_file *m,
1258 struct intel_instdone *instdone)
1259{
1260 int slice;
1261 int subslice;
1262
1263 seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1264 instdone->instdone);
1265
1266 if (INTEL_GEN(dev_priv) <= 3)
1267 return;
1268
1269 seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1270 instdone->slice_common);
1271
1272 if (INTEL_GEN(dev_priv) <= 6)
1273 return;
1274
1275 for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1276 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1277 slice, subslice, instdone->sampler[slice][subslice]);
1278
1279 for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1280 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1281 slice, subslice, instdone->row[slice][subslice]);
1282}
1283
1284static int i915_hangcheck_info(struct seq_file *m, void *unused)
1285{
1286 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1287 struct intel_engine_cs *engine;
1288 u64 acthd[I915_NUM_ENGINES];
1289 u32 seqno[I915_NUM_ENGINES];
1290 struct intel_instdone instdone;
1291 enum intel_engine_id id;
1292
1293 if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1294 seq_printf(m, "Wedged\n");
1295 if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags))
1296 seq_printf(m, "Reset in progress\n");
1297 if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1298 seq_printf(m, "Waiter holding struct mutex\n");
1299 if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1300 seq_printf(m, "struct_mutex blocked for reset\n");
1301
1302 if (!i915.enable_hangcheck) {
1303 seq_printf(m, "Hangcheck disabled\n");
1304 return 0;
1305 }
1306
1307 intel_runtime_pm_get(dev_priv);
1308
1309 for_each_engine(engine, dev_priv, id) {
1310 acthd[id] = intel_engine_get_active_head(engine);
1311 seqno[id] = intel_engine_get_seqno(engine);
1312 }
1313
1314 intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
1315
1316 intel_runtime_pm_put(dev_priv);
1317
1318 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1319 seq_printf(m, "Hangcheck active, fires in %dms\n",
1320 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1321 jiffies));
1322 } else
1323 seq_printf(m, "Hangcheck inactive\n");
1324
1325 for_each_engine(engine, dev_priv, id) {
1326 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1327 struct rb_node *rb;
1328
1329 seq_printf(m, "%s:\n", engine->name);
1330 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1331 engine->hangcheck.seqno, seqno[id],
1332 intel_engine_last_submit(engine));
1333 seq_printf(m, "\twaiters? %s, fake irq active? %s\n",
1334 yesno(intel_engine_has_waiter(engine)),
1335 yesno(test_bit(engine->id,
1336 &dev_priv->gpu_error.missed_irq_rings)));
1337 spin_lock_irq(&b->lock);
1338 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1339 struct intel_wait *w = container_of(rb, typeof(*w), node);
1340
1341 seq_printf(m, "\t%s [%d] waiting for %x\n",
1342 w->tsk->comm, w->tsk->pid, w->seqno);
1343 }
1344 spin_unlock_irq(&b->lock);
1345
1346 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1347 (long long)engine->hangcheck.acthd,
1348 (long long)acthd[id]);
1349 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1350 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1351
1352 if (engine->id == RCS) {
1353 seq_puts(m, "\tinstdone read =\n");
1354
1355 i915_instdone_info(dev_priv, m, &instdone);
1356
1357 seq_puts(m, "\tinstdone accu =\n");
1358
1359 i915_instdone_info(dev_priv, m,
1360 &engine->hangcheck.instdone);
1361 }
1362 }
1363
1364 return 0;
1365}
1366
1367static int ironlake_drpc_info(struct seq_file *m)
1368{
1369 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1370 u32 rgvmodectl, rstdbyctl;
1371 u16 crstandvid;
1372
1373 intel_runtime_pm_get(dev_priv);
1374
1375 rgvmodectl = I915_READ(MEMMODECTL);
1376 rstdbyctl = I915_READ(RSTDBYCTL);
1377 crstandvid = I915_READ16(CRSTANDVID);
1378
1379 intel_runtime_pm_put(dev_priv);
1380
1381 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1382 seq_printf(m, "Boost freq: %d\n",
1383 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1384 MEMMODE_BOOST_FREQ_SHIFT);
1385 seq_printf(m, "HW control enabled: %s\n",
1386 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1387 seq_printf(m, "SW control enabled: %s\n",
1388 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1389 seq_printf(m, "Gated voltage change: %s\n",
1390 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1391 seq_printf(m, "Starting frequency: P%d\n",
1392 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1393 seq_printf(m, "Max P-state: P%d\n",
1394 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1395 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1396 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1397 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1398 seq_printf(m, "Render standby enabled: %s\n",
1399 yesno(!(rstdbyctl & RCX_SW_EXIT)));
1400 seq_puts(m, "Current RS state: ");
1401 switch (rstdbyctl & RSX_STATUS_MASK) {
1402 case RSX_STATUS_ON:
1403 seq_puts(m, "on\n");
1404 break;
1405 case RSX_STATUS_RC1:
1406 seq_puts(m, "RC1\n");
1407 break;
1408 case RSX_STATUS_RC1E:
1409 seq_puts(m, "RC1E\n");
1410 break;
1411 case RSX_STATUS_RS1:
1412 seq_puts(m, "RS1\n");
1413 break;
1414 case RSX_STATUS_RS2:
1415 seq_puts(m, "RS2 (RC6)\n");
1416 break;
1417 case RSX_STATUS_RS3:
1418 seq_puts(m, "RC3 (RC6+)\n");
1419 break;
1420 default:
1421 seq_puts(m, "unknown\n");
1422 break;
1423 }
1424
1425 return 0;
1426}
1427
1428static int i915_forcewake_domains(struct seq_file *m, void *data)
1429{
1430 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1431 struct intel_uncore_forcewake_domain *fw_domain;
1432
1433 spin_lock_irq(&dev_priv->uncore.lock);
1434 for_each_fw_domain(fw_domain, dev_priv) {
1435 seq_printf(m, "%s.wake_count = %u\n",
1436 intel_uncore_forcewake_domain_to_str(fw_domain->id),
1437 fw_domain->wake_count);
1438 }
1439 spin_unlock_irq(&dev_priv->uncore.lock);
1440
1441 return 0;
1442}
1443
1444static int vlv_drpc_info(struct seq_file *m)
1445{
1446 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1447 u32 rpmodectl1, rcctl1, pw_status;
1448
1449 intel_runtime_pm_get(dev_priv);
1450
1451 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1452 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1453 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1454
1455 intel_runtime_pm_put(dev_priv);
1456
1457 seq_printf(m, "Video Turbo Mode: %s\n",
1458 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1459 seq_printf(m, "Turbo enabled: %s\n",
1460 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1461 seq_printf(m, "HW control enabled: %s\n",
1462 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1463 seq_printf(m, "SW control enabled: %s\n",
1464 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1465 GEN6_RP_MEDIA_SW_MODE));
1466 seq_printf(m, "RC6 Enabled: %s\n",
1467 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1468 GEN6_RC_CTL_EI_MODE(1))));
1469 seq_printf(m, "Render Power Well: %s\n",
1470 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1471 seq_printf(m, "Media Power Well: %s\n",
1472 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1473
1474 seq_printf(m, "Render RC6 residency since boot: %u\n",
1475 I915_READ(VLV_GT_RENDER_RC6));
1476 seq_printf(m, "Media RC6 residency since boot: %u\n",
1477 I915_READ(VLV_GT_MEDIA_RC6));
1478
1479 return i915_forcewake_domains(m, NULL);
1480}
1481
1482static int gen6_drpc_info(struct seq_file *m)
1483{
1484 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1485 struct drm_device *dev = &dev_priv->drm;
1486 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1487 u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1488 unsigned forcewake_count;
1489 int count = 0, ret;
1490
1491 ret = mutex_lock_interruptible(&dev->struct_mutex);
1492 if (ret)
1493 return ret;
1494 intel_runtime_pm_get(dev_priv);
1495
1496 spin_lock_irq(&dev_priv->uncore.lock);
1497 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1498 spin_unlock_irq(&dev_priv->uncore.lock);
1499
1500 if (forcewake_count) {
1501 seq_puts(m, "RC information inaccurate because somebody "
1502 "holds a forcewake reference \n");
1503 } else {
1504 /* NB: we cannot use forcewake, else we read the wrong values */
1505 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1506 udelay(10);
1507 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1508 }
1509
1510 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1511 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1512
1513 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1514 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1515 if (INTEL_GEN(dev_priv) >= 9) {
1516 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1517 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1518 }
1519 mutex_unlock(&dev->struct_mutex);
1520 mutex_lock(&dev_priv->rps.hw_lock);
1521 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1522 mutex_unlock(&dev_priv->rps.hw_lock);
1523
1524 intel_runtime_pm_put(dev_priv);
1525
1526 seq_printf(m, "Video Turbo Mode: %s\n",
1527 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1528 seq_printf(m, "HW control enabled: %s\n",
1529 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1530 seq_printf(m, "SW control enabled: %s\n",
1531 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1532 GEN6_RP_MEDIA_SW_MODE));
1533 seq_printf(m, "RC1e Enabled: %s\n",
1534 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1535 seq_printf(m, "RC6 Enabled: %s\n",
1536 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1537 if (INTEL_GEN(dev_priv) >= 9) {
1538 seq_printf(m, "Render Well Gating Enabled: %s\n",
1539 yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1540 seq_printf(m, "Media Well Gating Enabled: %s\n",
1541 yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1542 }
1543 seq_printf(m, "Deep RC6 Enabled: %s\n",
1544 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1545 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1546 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1547 seq_puts(m, "Current RC state: ");
1548 switch (gt_core_status & GEN6_RCn_MASK) {
1549 case GEN6_RC0:
1550 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1551 seq_puts(m, "Core Power Down\n");
1552 else
1553 seq_puts(m, "on\n");
1554 break;
1555 case GEN6_RC3:
1556 seq_puts(m, "RC3\n");
1557 break;
1558 case GEN6_RC6:
1559 seq_puts(m, "RC6\n");
1560 break;
1561 case GEN6_RC7:
1562 seq_puts(m, "RC7\n");
1563 break;
1564 default:
1565 seq_puts(m, "Unknown\n");
1566 break;
1567 }
1568
1569 seq_printf(m, "Core Power Down: %s\n",
1570 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1571 if (INTEL_GEN(dev_priv) >= 9) {
1572 seq_printf(m, "Render Power Well: %s\n",
1573 (gen9_powergate_status &
1574 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1575 seq_printf(m, "Media Power Well: %s\n",
1576 (gen9_powergate_status &
1577 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1578 }
1579
1580 /* Not exactly sure what this is */
1581 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1582 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1583 seq_printf(m, "RC6 residency since boot: %u\n",
1584 I915_READ(GEN6_GT_GFX_RC6));
1585 seq_printf(m, "RC6+ residency since boot: %u\n",
1586 I915_READ(GEN6_GT_GFX_RC6p));
1587 seq_printf(m, "RC6++ residency since boot: %u\n",
1588 I915_READ(GEN6_GT_GFX_RC6pp));
1589
1590 seq_printf(m, "RC6 voltage: %dmV\n",
1591 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1592 seq_printf(m, "RC6+ voltage: %dmV\n",
1593 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1594 seq_printf(m, "RC6++ voltage: %dmV\n",
1595 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1596 return i915_forcewake_domains(m, NULL);
1597}
1598
1599static int i915_drpc_info(struct seq_file *m, void *unused)
1600{
1601 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1602
1603 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1604 return vlv_drpc_info(m);
1605 else if (INTEL_GEN(dev_priv) >= 6)
1606 return gen6_drpc_info(m);
1607 else
1608 return ironlake_drpc_info(m);
1609}
1610
1611static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1612{
1613 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1614
1615 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1616 dev_priv->fb_tracking.busy_bits);
1617
1618 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1619 dev_priv->fb_tracking.flip_bits);
1620
1621 return 0;
1622}
1623
1624static int i915_fbc_status(struct seq_file *m, void *unused)
1625{
1626 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1627
1628 if (!HAS_FBC(dev_priv)) {
1629 seq_puts(m, "FBC unsupported on this chipset\n");
1630 return 0;
1631 }
1632
1633 intel_runtime_pm_get(dev_priv);
1634 mutex_lock(&dev_priv->fbc.lock);
1635
1636 if (intel_fbc_is_active(dev_priv))
1637 seq_puts(m, "FBC enabled\n");
1638 else
1639 seq_printf(m, "FBC disabled: %s\n",
1640 dev_priv->fbc.no_fbc_reason);
1641
1642 if (intel_fbc_is_active(dev_priv) && INTEL_GEN(dev_priv) >= 7) {
1643 uint32_t mask = INTEL_GEN(dev_priv) >= 8 ?
1644 BDW_FBC_COMPRESSION_MASK :
1645 IVB_FBC_COMPRESSION_MASK;
1646 seq_printf(m, "Compressing: %s\n",
1647 yesno(I915_READ(FBC_STATUS2) & mask));
1648 }
1649
1650 mutex_unlock(&dev_priv->fbc.lock);
1651 intel_runtime_pm_put(dev_priv);
1652
1653 return 0;
1654}
1655
1656static int i915_fbc_fc_get(void *data, u64 *val)
1657{
1658 struct drm_i915_private *dev_priv = data;
1659
1660 if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1661 return -ENODEV;
1662
1663 *val = dev_priv->fbc.false_color;
1664
1665 return 0;
1666}
1667
1668static int i915_fbc_fc_set(void *data, u64 val)
1669{
1670 struct drm_i915_private *dev_priv = data;
1671 u32 reg;
1672
1673 if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1674 return -ENODEV;
1675
1676 mutex_lock(&dev_priv->fbc.lock);
1677
1678 reg = I915_READ(ILK_DPFC_CONTROL);
1679 dev_priv->fbc.false_color = val;
1680
1681 I915_WRITE(ILK_DPFC_CONTROL, val ?
1682 (reg | FBC_CTL_FALSE_COLOR) :
1683 (reg & ~FBC_CTL_FALSE_COLOR));
1684
1685 mutex_unlock(&dev_priv->fbc.lock);
1686 return 0;
1687}
1688
1689DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1690 i915_fbc_fc_get, i915_fbc_fc_set,
1691 "%llu\n");
1692
1693static int i915_ips_status(struct seq_file *m, void *unused)
1694{
1695 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1696
1697 if (!HAS_IPS(dev_priv)) {
1698 seq_puts(m, "not supported\n");
1699 return 0;
1700 }
1701
1702 intel_runtime_pm_get(dev_priv);
1703
1704 seq_printf(m, "Enabled by kernel parameter: %s\n",
1705 yesno(i915.enable_ips));
1706
1707 if (INTEL_GEN(dev_priv) >= 8) {
1708 seq_puts(m, "Currently: unknown\n");
1709 } else {
1710 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1711 seq_puts(m, "Currently: enabled\n");
1712 else
1713 seq_puts(m, "Currently: disabled\n");
1714 }
1715
1716 intel_runtime_pm_put(dev_priv);
1717
1718 return 0;
1719}
1720
1721static int i915_sr_status(struct seq_file *m, void *unused)
1722{
1723 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1724 bool sr_enabled = false;
1725
1726 intel_runtime_pm_get(dev_priv);
1727 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1728
1729 if (HAS_PCH_SPLIT(dev_priv))
1730 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1731 else if (IS_CRESTLINE(dev_priv) || IS_G4X(dev_priv) ||
1732 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1733 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1734 else if (IS_I915GM(dev_priv))
1735 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1736 else if (IS_PINEVIEW(dev_priv))
1737 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1738 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1739 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1740
1741 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1742 intel_runtime_pm_put(dev_priv);
1743
1744 seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled));
1745
1746 return 0;
1747}
1748
1749static int i915_emon_status(struct seq_file *m, void *unused)
1750{
1751 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1752 struct drm_device *dev = &dev_priv->drm;
1753 unsigned long temp, chipset, gfx;
1754 int ret;
1755
1756 if (!IS_GEN5(dev_priv))
1757 return -ENODEV;
1758
1759 ret = mutex_lock_interruptible(&dev->struct_mutex);
1760 if (ret)
1761 return ret;
1762
1763 temp = i915_mch_val(dev_priv);
1764 chipset = i915_chipset_val(dev_priv);
1765 gfx = i915_gfx_val(dev_priv);
1766 mutex_unlock(&dev->struct_mutex);
1767
1768 seq_printf(m, "GMCH temp: %ld\n", temp);
1769 seq_printf(m, "Chipset power: %ld\n", chipset);
1770 seq_printf(m, "GFX power: %ld\n", gfx);
1771 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1772
1773 return 0;
1774}
1775
1776static int i915_ring_freq_table(struct seq_file *m, void *unused)
1777{
1778 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1779 int ret = 0;
1780 int gpu_freq, ia_freq;
1781 unsigned int max_gpu_freq, min_gpu_freq;
1782
1783 if (!HAS_LLC(dev_priv)) {
1784 seq_puts(m, "unsupported on this chipset\n");
1785 return 0;
1786 }
1787
1788 intel_runtime_pm_get(dev_priv);
1789
1790 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1791 if (ret)
1792 goto out;
1793
1794 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1795 /* Convert GT frequency to 50 HZ units */
1796 min_gpu_freq =
1797 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1798 max_gpu_freq =
1799 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1800 } else {
1801 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1802 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1803 }
1804
1805 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1806
1807 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1808 ia_freq = gpu_freq;
1809 sandybridge_pcode_read(dev_priv,
1810 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1811 &ia_freq);
1812 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1813 intel_gpu_freq(dev_priv, (gpu_freq *
1814 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1815 GEN9_FREQ_SCALER : 1))),
1816 ((ia_freq >> 0) & 0xff) * 100,
1817 ((ia_freq >> 8) & 0xff) * 100);
1818 }
1819
1820 mutex_unlock(&dev_priv->rps.hw_lock);
1821
1822out:
1823 intel_runtime_pm_put(dev_priv);
1824 return ret;
1825}
1826
1827static int i915_opregion(struct seq_file *m, void *unused)
1828{
1829 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1830 struct drm_device *dev = &dev_priv->drm;
1831 struct intel_opregion *opregion = &dev_priv->opregion;
1832 int ret;
1833
1834 ret = mutex_lock_interruptible(&dev->struct_mutex);
1835 if (ret)
1836 goto out;
1837
1838 if (opregion->header)
1839 seq_write(m, opregion->header, OPREGION_SIZE);
1840
1841 mutex_unlock(&dev->struct_mutex);
1842
1843out:
1844 return 0;
1845}
1846
1847static int i915_vbt(struct seq_file *m, void *unused)
1848{
1849 struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1850
1851 if (opregion->vbt)
1852 seq_write(m, opregion->vbt, opregion->vbt_size);
1853
1854 return 0;
1855}
1856
1857static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1858{
1859 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1860 struct drm_device *dev = &dev_priv->drm;
1861 struct intel_framebuffer *fbdev_fb = NULL;
1862 struct drm_framebuffer *drm_fb;
1863 int ret;
1864
1865 ret = mutex_lock_interruptible(&dev->struct_mutex);
1866 if (ret)
1867 return ret;
1868
1869#ifdef CONFIG_DRM_FBDEV_EMULATION
1870 if (dev_priv->fbdev) {
1871 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1872
1873 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1874 fbdev_fb->base.width,
1875 fbdev_fb->base.height,
1876 fbdev_fb->base.format->depth,
1877 fbdev_fb->base.bits_per_pixel,
1878 fbdev_fb->base.modifier,
1879 drm_framebuffer_read_refcount(&fbdev_fb->base));
1880 describe_obj(m, fbdev_fb->obj);
1881 seq_putc(m, '\n');
1882 }
1883#endif
1884
1885 mutex_lock(&dev->mode_config.fb_lock);
1886 drm_for_each_fb(drm_fb, dev) {
1887 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1888 if (fb == fbdev_fb)
1889 continue;
1890
1891 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1892 fb->base.width,
1893 fb->base.height,
1894 fb->base.format->depth,
1895 fb->base.bits_per_pixel,
1896 fb->base.modifier,
1897 drm_framebuffer_read_refcount(&fb->base));
1898 describe_obj(m, fb->obj);
1899 seq_putc(m, '\n');
1900 }
1901 mutex_unlock(&dev->mode_config.fb_lock);
1902 mutex_unlock(&dev->struct_mutex);
1903
1904 return 0;
1905}
1906
1907static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1908{
1909 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1910 ring->space, ring->head, ring->tail,
1911 ring->last_retired_head);
1912}
1913
1914static int i915_context_status(struct seq_file *m, void *unused)
1915{
1916 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1917 struct drm_device *dev = &dev_priv->drm;
1918 struct intel_engine_cs *engine;
1919 struct i915_gem_context *ctx;
1920 enum intel_engine_id id;
1921 int ret;
1922
1923 ret = mutex_lock_interruptible(&dev->struct_mutex);
1924 if (ret)
1925 return ret;
1926
1927 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1928 seq_printf(m, "HW context %u ", ctx->hw_id);
1929 if (ctx->pid) {
1930 struct task_struct *task;
1931
1932 task = get_pid_task(ctx->pid, PIDTYPE_PID);
1933 if (task) {
1934 seq_printf(m, "(%s [%d]) ",
1935 task->comm, task->pid);
1936 put_task_struct(task);
1937 }
1938 } else if (IS_ERR(ctx->file_priv)) {
1939 seq_puts(m, "(deleted) ");
1940 } else {
1941 seq_puts(m, "(kernel) ");
1942 }
1943
1944 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1945 seq_putc(m, '\n');
1946
1947 for_each_engine(engine, dev_priv, id) {
1948 struct intel_context *ce = &ctx->engine[engine->id];
1949
1950 seq_printf(m, "%s: ", engine->name);
1951 seq_putc(m, ce->initialised ? 'I' : 'i');
1952 if (ce->state)
1953 describe_obj(m, ce->state->obj);
1954 if (ce->ring)
1955 describe_ctx_ring(m, ce->ring);
1956 seq_putc(m, '\n');
1957 }
1958
1959 seq_putc(m, '\n');
1960 }
1961
1962 mutex_unlock(&dev->struct_mutex);
1963
1964 return 0;
1965}
1966
1967static void i915_dump_lrc_obj(struct seq_file *m,
1968 struct i915_gem_context *ctx,
1969 struct intel_engine_cs *engine)
1970{
1971 struct i915_vma *vma = ctx->engine[engine->id].state;
1972 struct page *page;
1973 int j;
1974
1975 seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
1976
1977 if (!vma) {
1978 seq_puts(m, "\tFake context\n");
1979 return;
1980 }
1981
1982 if (vma->flags & I915_VMA_GLOBAL_BIND)
1983 seq_printf(m, "\tBound in GGTT at 0x%08x\n",
1984 i915_ggtt_offset(vma));
1985
1986 if (i915_gem_object_pin_pages(vma->obj)) {
1987 seq_puts(m, "\tFailed to get pages for context object\n\n");
1988 return;
1989 }
1990
1991 page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
1992 if (page) {
1993 u32 *reg_state = kmap_atomic(page);
1994
1995 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1996 seq_printf(m,
1997 "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1998 j * 4,
1999 reg_state[j], reg_state[j + 1],
2000 reg_state[j + 2], reg_state[j + 3]);
2001 }
2002 kunmap_atomic(reg_state);
2003 }
2004
2005 i915_gem_object_unpin_pages(vma->obj);
2006 seq_putc(m, '\n');
2007}
2008
2009static int i915_dump_lrc(struct seq_file *m, void *unused)
2010{
2011 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2012 struct drm_device *dev = &dev_priv->drm;
2013 struct intel_engine_cs *engine;
2014 struct i915_gem_context *ctx;
2015 enum intel_engine_id id;
2016 int ret;
2017
2018 if (!i915.enable_execlists) {
2019 seq_printf(m, "Logical Ring Contexts are disabled\n");
2020 return 0;
2021 }
2022
2023 ret = mutex_lock_interruptible(&dev->struct_mutex);
2024 if (ret)
2025 return ret;
2026
2027 list_for_each_entry(ctx, &dev_priv->context_list, link)
2028 for_each_engine(engine, dev_priv, id)
2029 i915_dump_lrc_obj(m, ctx, engine);
2030
2031 mutex_unlock(&dev->struct_mutex);
2032
2033 return 0;
2034}
2035
2036static const char *swizzle_string(unsigned swizzle)
2037{
2038 switch (swizzle) {
2039 case I915_BIT_6_SWIZZLE_NONE:
2040 return "none";
2041 case I915_BIT_6_SWIZZLE_9:
2042 return "bit9";
2043 case I915_BIT_6_SWIZZLE_9_10:
2044 return "bit9/bit10";
2045 case I915_BIT_6_SWIZZLE_9_11:
2046 return "bit9/bit11";
2047 case I915_BIT_6_SWIZZLE_9_10_11:
2048 return "bit9/bit10/bit11";
2049 case I915_BIT_6_SWIZZLE_9_17:
2050 return "bit9/bit17";
2051 case I915_BIT_6_SWIZZLE_9_10_17:
2052 return "bit9/bit10/bit17";
2053 case I915_BIT_6_SWIZZLE_UNKNOWN:
2054 return "unknown";
2055 }
2056
2057 return "bug";
2058}
2059
2060static int i915_swizzle_info(struct seq_file *m, void *data)
2061{
2062 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2063
2064 intel_runtime_pm_get(dev_priv);
2065
2066 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2067 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2068 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2069 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2070
2071 if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2072 seq_printf(m, "DDC = 0x%08x\n",
2073 I915_READ(DCC));
2074 seq_printf(m, "DDC2 = 0x%08x\n",
2075 I915_READ(DCC2));
2076 seq_printf(m, "C0DRB3 = 0x%04x\n",
2077 I915_READ16(C0DRB3));
2078 seq_printf(m, "C1DRB3 = 0x%04x\n",
2079 I915_READ16(C1DRB3));
2080 } else if (INTEL_GEN(dev_priv) >= 6) {
2081 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2082 I915_READ(MAD_DIMM_C0));
2083 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2084 I915_READ(MAD_DIMM_C1));
2085 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2086 I915_READ(MAD_DIMM_C2));
2087 seq_printf(m, "TILECTL = 0x%08x\n",
2088 I915_READ(TILECTL));
2089 if (INTEL_GEN(dev_priv) >= 8)
2090 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2091 I915_READ(GAMTARBMODE));
2092 else
2093 seq_printf(m, "ARB_MODE = 0x%08x\n",
2094 I915_READ(ARB_MODE));
2095 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2096 I915_READ(DISP_ARB_CTL));
2097 }
2098
2099 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2100 seq_puts(m, "L-shaped memory detected\n");
2101
2102 intel_runtime_pm_put(dev_priv);
2103
2104 return 0;
2105}
2106
2107static int per_file_ctx(int id, void *ptr, void *data)
2108{
2109 struct i915_gem_context *ctx = ptr;
2110 struct seq_file *m = data;
2111 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2112
2113 if (!ppgtt) {
2114 seq_printf(m, " no ppgtt for context %d\n",
2115 ctx->user_handle);
2116 return 0;
2117 }
2118
2119 if (i915_gem_context_is_default(ctx))
2120 seq_puts(m, " default context:\n");
2121 else
2122 seq_printf(m, " context %d:\n", ctx->user_handle);
2123 ppgtt->debug_dump(ppgtt, m);
2124
2125 return 0;
2126}
2127
2128static void gen8_ppgtt_info(struct seq_file *m,
2129 struct drm_i915_private *dev_priv)
2130{
2131 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2132 struct intel_engine_cs *engine;
2133 enum intel_engine_id id;
2134 int i;
2135
2136 if (!ppgtt)
2137 return;
2138
2139 for_each_engine(engine, dev_priv, id) {
2140 seq_printf(m, "%s\n", engine->name);
2141 for (i = 0; i < 4; i++) {
2142 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2143 pdp <<= 32;
2144 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2145 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2146 }
2147 }
2148}
2149
2150static void gen6_ppgtt_info(struct seq_file *m,
2151 struct drm_i915_private *dev_priv)
2152{
2153 struct intel_engine_cs *engine;
2154 enum intel_engine_id id;
2155
2156 if (IS_GEN6(dev_priv))
2157 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2158
2159 for_each_engine(engine, dev_priv, id) {
2160 seq_printf(m, "%s\n", engine->name);
2161 if (IS_GEN7(dev_priv))
2162 seq_printf(m, "GFX_MODE: 0x%08x\n",
2163 I915_READ(RING_MODE_GEN7(engine)));
2164 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2165 I915_READ(RING_PP_DIR_BASE(engine)));
2166 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2167 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2168 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2169 I915_READ(RING_PP_DIR_DCLV(engine)));
2170 }
2171 if (dev_priv->mm.aliasing_ppgtt) {
2172 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2173
2174 seq_puts(m, "aliasing PPGTT:\n");
2175 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2176
2177 ppgtt->debug_dump(ppgtt, m);
2178 }
2179
2180 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2181}
2182
2183static int i915_ppgtt_info(struct seq_file *m, void *data)
2184{
2185 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2186 struct drm_device *dev = &dev_priv->drm;
2187 struct drm_file *file;
2188 int ret;
2189
2190 mutex_lock(&dev->filelist_mutex);
2191 ret = mutex_lock_interruptible(&dev->struct_mutex);
2192 if (ret)
2193 goto out_unlock;
2194
2195 intel_runtime_pm_get(dev_priv);
2196
2197 if (INTEL_GEN(dev_priv) >= 8)
2198 gen8_ppgtt_info(m, dev_priv);
2199 else if (INTEL_GEN(dev_priv) >= 6)
2200 gen6_ppgtt_info(m, dev_priv);
2201
2202 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2203 struct drm_i915_file_private *file_priv = file->driver_priv;
2204 struct task_struct *task;
2205
2206 task = get_pid_task(file->pid, PIDTYPE_PID);
2207 if (!task) {
2208 ret = -ESRCH;
2209 goto out_rpm;
2210 }
2211 seq_printf(m, "\nproc: %s\n", task->comm);
2212 put_task_struct(task);
2213 idr_for_each(&file_priv->context_idr, per_file_ctx,
2214 (void *)(unsigned long)m);
2215 }
2216
2217out_rpm:
2218 intel_runtime_pm_put(dev_priv);
2219 mutex_unlock(&dev->struct_mutex);
2220out_unlock:
2221 mutex_unlock(&dev->filelist_mutex);
2222 return ret;
2223}
2224
2225static int count_irq_waiters(struct drm_i915_private *i915)
2226{
2227 struct intel_engine_cs *engine;
2228 enum intel_engine_id id;
2229 int count = 0;
2230
2231 for_each_engine(engine, i915, id)
2232 count += intel_engine_has_waiter(engine);
2233
2234 return count;
2235}
2236
2237static const char *rps_power_to_str(unsigned int power)
2238{
2239 static const char * const strings[] = {
2240 [LOW_POWER] = "low power",
2241 [BETWEEN] = "mixed",
2242 [HIGH_POWER] = "high power",
2243 };
2244
2245 if (power >= ARRAY_SIZE(strings) || !strings[power])
2246 return "unknown";
2247
2248 return strings[power];
2249}
2250
2251static int i915_rps_boost_info(struct seq_file *m, void *data)
2252{
2253 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2254 struct drm_device *dev = &dev_priv->drm;
2255 struct drm_file *file;
2256
2257 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2258 seq_printf(m, "GPU busy? %s [%d requests]\n",
2259 yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
2260 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2261 seq_printf(m, "Frequency requested %d\n",
2262 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
2263 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2264 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2265 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2266 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2267 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2268 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n",
2269 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
2270 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2271 intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
2272
2273 mutex_lock(&dev->filelist_mutex);
2274 spin_lock(&dev_priv->rps.client_lock);
2275 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2276 struct drm_i915_file_private *file_priv = file->driver_priv;
2277 struct task_struct *task;
2278
2279 rcu_read_lock();
2280 task = pid_task(file->pid, PIDTYPE_PID);
2281 seq_printf(m, "%s [%d]: %d boosts%s\n",
2282 task ? task->comm : "<unknown>",
2283 task ? task->pid : -1,
2284 file_priv->rps.boosts,
2285 list_empty(&file_priv->rps.link) ? "" : ", active");
2286 rcu_read_unlock();
2287 }
2288 seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2289 spin_unlock(&dev_priv->rps.client_lock);
2290 mutex_unlock(&dev->filelist_mutex);
2291
2292 if (INTEL_GEN(dev_priv) >= 6 &&
2293 dev_priv->rps.enabled &&
2294 dev_priv->gt.active_requests) {
2295 u32 rpup, rpupei;
2296 u32 rpdown, rpdownei;
2297
2298 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2299 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2300 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2301 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2302 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2303 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2304
2305 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2306 rps_power_to_str(dev_priv->rps.power));
2307 seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n",
2308 100 * rpup / rpupei,
2309 dev_priv->rps.up_threshold);
2310 seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n",
2311 100 * rpdown / rpdownei,
2312 dev_priv->rps.down_threshold);
2313 } else {
2314 seq_puts(m, "\nRPS Autotuning inactive\n");
2315 }
2316
2317 return 0;
2318}
2319
2320static int i915_llc(struct seq_file *m, void *data)
2321{
2322 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2323 const bool edram = INTEL_GEN(dev_priv) > 8;
2324
2325 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2326 seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2327 intel_uncore_edram_size(dev_priv)/1024/1024);
2328
2329 return 0;
2330}
2331
2332static int i915_guc_load_status_info(struct seq_file *m, void *data)
2333{
2334 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2335 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2336 u32 tmp, i;
2337
2338 if (!HAS_GUC_UCODE(dev_priv))
2339 return 0;
2340
2341 seq_printf(m, "GuC firmware status:\n");
2342 seq_printf(m, "\tpath: %s\n",
2343 guc_fw->guc_fw_path);
2344 seq_printf(m, "\tfetch: %s\n",
2345 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2346 seq_printf(m, "\tload: %s\n",
2347 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2348 seq_printf(m, "\tversion wanted: %d.%d\n",
2349 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2350 seq_printf(m, "\tversion found: %d.%d\n",
2351 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2352 seq_printf(m, "\theader: offset is %d; size = %d\n",
2353 guc_fw->header_offset, guc_fw->header_size);
2354 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2355 guc_fw->ucode_offset, guc_fw->ucode_size);
2356 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2357 guc_fw->rsa_offset, guc_fw->rsa_size);
2358
2359 tmp = I915_READ(GUC_STATUS);
2360
2361 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2362 seq_printf(m, "\tBootrom status = 0x%x\n",
2363 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2364 seq_printf(m, "\tuKernel status = 0x%x\n",
2365 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2366 seq_printf(m, "\tMIA Core status = 0x%x\n",
2367 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2368 seq_puts(m, "\nScratch registers:\n");
2369 for (i = 0; i < 16; i++)
2370 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2371
2372 return 0;
2373}
2374
2375static void i915_guc_log_info(struct seq_file *m,
2376 struct drm_i915_private *dev_priv)
2377{
2378 struct intel_guc *guc = &dev_priv->guc;
2379
2380 seq_puts(m, "\nGuC logging stats:\n");
2381
2382 seq_printf(m, "\tISR: flush count %10u, overflow count %10u\n",
2383 guc->log.flush_count[GUC_ISR_LOG_BUFFER],
2384 guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]);
2385
2386 seq_printf(m, "\tDPC: flush count %10u, overflow count %10u\n",
2387 guc->log.flush_count[GUC_DPC_LOG_BUFFER],
2388 guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]);
2389
2390 seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n",
2391 guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER],
2392 guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]);
2393
2394 seq_printf(m, "\tTotal flush interrupt count: %u\n",
2395 guc->log.flush_interrupt_count);
2396
2397 seq_printf(m, "\tCapture miss count: %u\n",
2398 guc->log.capture_miss_count);
2399}
2400
2401static void i915_guc_client_info(struct seq_file *m,
2402 struct drm_i915_private *dev_priv,
2403 struct i915_guc_client *client)
2404{
2405 struct intel_engine_cs *engine;
2406 enum intel_engine_id id;
2407 uint64_t tot = 0;
2408
2409 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2410 client->priority, client->ctx_index, client->proc_desc_offset);
2411 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2412 client->doorbell_id, client->doorbell_offset, client->cookie);
2413 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2414 client->wq_size, client->wq_offset, client->wq_tail);
2415
2416 seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2417 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2418 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2419
2420 for_each_engine(engine, dev_priv, id) {
2421 u64 submissions = client->submissions[id];
2422 tot += submissions;
2423 seq_printf(m, "\tSubmissions: %llu %s\n",
2424 submissions, engine->name);
2425 }
2426 seq_printf(m, "\tTotal: %llu\n", tot);
2427}
2428
2429static int i915_guc_info(struct seq_file *m, void *data)
2430{
2431 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2432 struct drm_device *dev = &dev_priv->drm;
2433 struct intel_guc guc;
2434 struct i915_guc_client client = {};
2435 struct intel_engine_cs *engine;
2436 enum intel_engine_id id;
2437 u64 total = 0;
2438
2439 if (!HAS_GUC_SCHED(dev_priv))
2440 return 0;
2441
2442 if (mutex_lock_interruptible(&dev->struct_mutex))
2443 return 0;
2444
2445 /* Take a local copy of the GuC data, so we can dump it at leisure */
2446 guc = dev_priv->guc;
2447 if (guc.execbuf_client)
2448 client = *guc.execbuf_client;
2449
2450 mutex_unlock(&dev->struct_mutex);
2451
2452 seq_printf(m, "Doorbell map:\n");
2453 seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2454 seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2455
2456 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2457 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2458 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2459 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2460 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2461
2462 seq_printf(m, "\nGuC submissions:\n");
2463 for_each_engine(engine, dev_priv, id) {
2464 u64 submissions = guc.submissions[id];
2465 total += submissions;
2466 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2467 engine->name, submissions, guc.last_seqno[id]);
2468 }
2469 seq_printf(m, "\t%s: %llu\n", "Total", total);
2470
2471 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2472 i915_guc_client_info(m, dev_priv, &client);
2473
2474 i915_guc_log_info(m, dev_priv);
2475
2476 /* Add more as required ... */
2477
2478 return 0;
2479}
2480
2481static int i915_guc_log_dump(struct seq_file *m, void *data)
2482{
2483 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2484 struct drm_i915_gem_object *obj;
2485 int i = 0, pg;
2486
2487 if (!dev_priv->guc.log.vma)
2488 return 0;
2489
2490 obj = dev_priv->guc.log.vma->obj;
2491 for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) {
2492 u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg));
2493
2494 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2495 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2496 *(log + i), *(log + i + 1),
2497 *(log + i + 2), *(log + i + 3));
2498
2499 kunmap_atomic(log);
2500 }
2501
2502 seq_putc(m, '\n');
2503
2504 return 0;
2505}
2506
2507static int i915_guc_log_control_get(void *data, u64 *val)
2508{
2509 struct drm_device *dev = data;
2510 struct drm_i915_private *dev_priv = to_i915(dev);
2511
2512 if (!dev_priv->guc.log.vma)
2513 return -EINVAL;
2514
2515 *val = i915.guc_log_level;
2516
2517 return 0;
2518}
2519
2520static int i915_guc_log_control_set(void *data, u64 val)
2521{
2522 struct drm_device *dev = data;
2523 struct drm_i915_private *dev_priv = to_i915(dev);
2524 int ret;
2525
2526 if (!dev_priv->guc.log.vma)
2527 return -EINVAL;
2528
2529 ret = mutex_lock_interruptible(&dev->struct_mutex);
2530 if (ret)
2531 return ret;
2532
2533 intel_runtime_pm_get(dev_priv);
2534 ret = i915_guc_log_control(dev_priv, val);
2535 intel_runtime_pm_put(dev_priv);
2536
2537 mutex_unlock(&dev->struct_mutex);
2538 return ret;
2539}
2540
2541DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,
2542 i915_guc_log_control_get, i915_guc_log_control_set,
2543 "%lld\n");
2544
2545static int i915_edp_psr_status(struct seq_file *m, void *data)
2546{
2547 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2548 u32 psrperf = 0;
2549 u32 stat[3];
2550 enum pipe pipe;
2551 bool enabled = false;
2552
2553 if (!HAS_PSR(dev_priv)) {
2554 seq_puts(m, "PSR not supported\n");
2555 return 0;
2556 }
2557
2558 intel_runtime_pm_get(dev_priv);
2559
2560 mutex_lock(&dev_priv->psr.lock);
2561 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2562 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2563 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2564 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2565 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2566 dev_priv->psr.busy_frontbuffer_bits);
2567 seq_printf(m, "Re-enable work scheduled: %s\n",
2568 yesno(work_busy(&dev_priv->psr.work.work)));
2569
2570 if (HAS_DDI(dev_priv))
2571 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2572 else {
2573 for_each_pipe(dev_priv, pipe) {
2574 enum transcoder cpu_transcoder =
2575 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
2576 enum intel_display_power_domain power_domain;
2577
2578 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
2579 if (!intel_display_power_get_if_enabled(dev_priv,
2580 power_domain))
2581 continue;
2582
2583 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2584 VLV_EDP_PSR_CURR_STATE_MASK;
2585 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2586 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2587 enabled = true;
2588
2589 intel_display_power_put(dev_priv, power_domain);
2590 }
2591 }
2592
2593 seq_printf(m, "Main link in standby mode: %s\n",
2594 yesno(dev_priv->psr.link_standby));
2595
2596 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2597
2598 if (!HAS_DDI(dev_priv))
2599 for_each_pipe(dev_priv, pipe) {
2600 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2601 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2602 seq_printf(m, " pipe %c", pipe_name(pipe));
2603 }
2604 seq_puts(m, "\n");
2605
2606 /*
2607 * VLV/CHV PSR has no kind of performance counter
2608 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2609 */
2610 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2611 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2612 EDP_PSR_PERF_CNT_MASK;
2613
2614 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2615 }
2616 mutex_unlock(&dev_priv->psr.lock);
2617
2618 intel_runtime_pm_put(dev_priv);
2619 return 0;
2620}
2621
2622static int i915_sink_crc(struct seq_file *m, void *data)
2623{
2624 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2625 struct drm_device *dev = &dev_priv->drm;
2626 struct intel_connector *connector;
2627 struct intel_dp *intel_dp = NULL;
2628 int ret;
2629 u8 crc[6];
2630
2631 drm_modeset_lock_all(dev);
2632 for_each_intel_connector(dev, connector) {
2633 struct drm_crtc *crtc;
2634
2635 if (!connector->base.state->best_encoder)
2636 continue;
2637
2638 crtc = connector->base.state->crtc;
2639 if (!crtc->state->active)
2640 continue;
2641
2642 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2643 continue;
2644
2645 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2646
2647 ret = intel_dp_sink_crc(intel_dp, crc);
2648 if (ret)
2649 goto out;
2650
2651 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2652 crc[0], crc[1], crc[2],
2653 crc[3], crc[4], crc[5]);
2654 goto out;
2655 }
2656 ret = -ENODEV;
2657out:
2658 drm_modeset_unlock_all(dev);
2659 return ret;
2660}
2661
2662static int i915_energy_uJ(struct seq_file *m, void *data)
2663{
2664 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2665 u64 power;
2666 u32 units;
2667
2668 if (INTEL_GEN(dev_priv) < 6)
2669 return -ENODEV;
2670
2671 intel_runtime_pm_get(dev_priv);
2672
2673 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2674 power = (power & 0x1f00) >> 8;
2675 units = 1000000 / (1 << power); /* convert to uJ */
2676 power = I915_READ(MCH_SECP_NRG_STTS);
2677 power *= units;
2678
2679 intel_runtime_pm_put(dev_priv);
2680
2681 seq_printf(m, "%llu", (long long unsigned)power);
2682
2683 return 0;
2684}
2685
2686static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2687{
2688 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2689 struct pci_dev *pdev = dev_priv->drm.pdev;
2690
2691 if (!HAS_RUNTIME_PM(dev_priv))
2692 seq_puts(m, "Runtime power management not supported\n");
2693
2694 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2695 seq_printf(m, "IRQs disabled: %s\n",
2696 yesno(!intel_irqs_enabled(dev_priv)));
2697#ifdef CONFIG_PM
2698 seq_printf(m, "Usage count: %d\n",
2699 atomic_read(&dev_priv->drm.dev->power.usage_count));
2700#else
2701 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2702#endif
2703 seq_printf(m, "PCI device power state: %s [%d]\n",
2704 pci_power_name(pdev->current_state),
2705 pdev->current_state);
2706
2707 return 0;
2708}
2709
2710static int i915_power_domain_info(struct seq_file *m, void *unused)
2711{
2712 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2713 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2714 int i;
2715
2716 mutex_lock(&power_domains->lock);
2717
2718 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2719 for (i = 0; i < power_domains->power_well_count; i++) {
2720 struct i915_power_well *power_well;
2721 enum intel_display_power_domain power_domain;
2722
2723 power_well = &power_domains->power_wells[i];
2724 seq_printf(m, "%-25s %d\n", power_well->name,
2725 power_well->count);
2726
2727 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2728 power_domain++) {
2729 if (!(BIT(power_domain) & power_well->domains))
2730 continue;
2731
2732 seq_printf(m, " %-23s %d\n",
2733 intel_display_power_domain_str(power_domain),
2734 power_domains->domain_use_count[power_domain]);
2735 }
2736 }
2737
2738 mutex_unlock(&power_domains->lock);
2739
2740 return 0;
2741}
2742
2743static int i915_dmc_info(struct seq_file *m, void *unused)
2744{
2745 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2746 struct intel_csr *csr;
2747
2748 if (!HAS_CSR(dev_priv)) {
2749 seq_puts(m, "not supported\n");
2750 return 0;
2751 }
2752
2753 csr = &dev_priv->csr;
2754
2755 intel_runtime_pm_get(dev_priv);
2756
2757 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2758 seq_printf(m, "path: %s\n", csr->fw_path);
2759
2760 if (!csr->dmc_payload)
2761 goto out;
2762
2763 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2764 CSR_VERSION_MINOR(csr->version));
2765
2766 if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {
2767 seq_printf(m, "DC3 -> DC5 count: %d\n",
2768 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2769 seq_printf(m, "DC5 -> DC6 count: %d\n",
2770 I915_READ(SKL_CSR_DC5_DC6_COUNT));
2771 } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2772 seq_printf(m, "DC3 -> DC5 count: %d\n",
2773 I915_READ(BXT_CSR_DC3_DC5_COUNT));
2774 }
2775
2776out:
2777 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2778 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2779 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2780
2781 intel_runtime_pm_put(dev_priv);
2782
2783 return 0;
2784}
2785
2786static void intel_seq_print_mode(struct seq_file *m, int tabs,
2787 struct drm_display_mode *mode)
2788{
2789 int i;
2790
2791 for (i = 0; i < tabs; i++)
2792 seq_putc(m, '\t');
2793
2794 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2795 mode->base.id, mode->name,
2796 mode->vrefresh, mode->clock,
2797 mode->hdisplay, mode->hsync_start,
2798 mode->hsync_end, mode->htotal,
2799 mode->vdisplay, mode->vsync_start,
2800 mode->vsync_end, mode->vtotal,
2801 mode->type, mode->flags);
2802}
2803
2804static void intel_encoder_info(struct seq_file *m,
2805 struct intel_crtc *intel_crtc,
2806 struct intel_encoder *intel_encoder)
2807{
2808 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2809 struct drm_device *dev = &dev_priv->drm;
2810 struct drm_crtc *crtc = &intel_crtc->base;
2811 struct intel_connector *intel_connector;
2812 struct drm_encoder *encoder;
2813
2814 encoder = &intel_encoder->base;
2815 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2816 encoder->base.id, encoder->name);
2817 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2818 struct drm_connector *connector = &intel_connector->base;
2819 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2820 connector->base.id,
2821 connector->name,
2822 drm_get_connector_status_name(connector->status));
2823 if (connector->status == connector_status_connected) {
2824 struct drm_display_mode *mode = &crtc->mode;
2825 seq_printf(m, ", mode:\n");
2826 intel_seq_print_mode(m, 2, mode);
2827 } else {
2828 seq_putc(m, '\n');
2829 }
2830 }
2831}
2832
2833static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2834{
2835 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2836 struct drm_device *dev = &dev_priv->drm;
2837 struct drm_crtc *crtc = &intel_crtc->base;
2838 struct intel_encoder *intel_encoder;
2839 struct drm_plane_state *plane_state = crtc->primary->state;
2840 struct drm_framebuffer *fb = plane_state->fb;
2841
2842 if (fb)
2843 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2844 fb->base.id, plane_state->src_x >> 16,
2845 plane_state->src_y >> 16, fb->width, fb->height);
2846 else
2847 seq_puts(m, "\tprimary plane disabled\n");
2848 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2849 intel_encoder_info(m, intel_crtc, intel_encoder);
2850}
2851
2852static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2853{
2854 struct drm_display_mode *mode = panel->fixed_mode;
2855
2856 seq_printf(m, "\tfixed mode:\n");
2857 intel_seq_print_mode(m, 2, mode);
2858}
2859
2860static void intel_dp_info(struct seq_file *m,
2861 struct intel_connector *intel_connector)
2862{
2863 struct intel_encoder *intel_encoder = intel_connector->encoder;
2864 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2865
2866 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2867 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2868 if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2869 intel_panel_info(m, &intel_connector->panel);
2870
2871 drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
2872 &intel_dp->aux);
2873}
2874
2875static void intel_hdmi_info(struct seq_file *m,
2876 struct intel_connector *intel_connector)
2877{
2878 struct intel_encoder *intel_encoder = intel_connector->encoder;
2879 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2880
2881 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2882}
2883
2884static void intel_lvds_info(struct seq_file *m,
2885 struct intel_connector *intel_connector)
2886{
2887 intel_panel_info(m, &intel_connector->panel);
2888}
2889
2890static void intel_connector_info(struct seq_file *m,
2891 struct drm_connector *connector)
2892{
2893 struct intel_connector *intel_connector = to_intel_connector(connector);
2894 struct intel_encoder *intel_encoder = intel_connector->encoder;
2895 struct drm_display_mode *mode;
2896
2897 seq_printf(m, "connector %d: type %s, status: %s\n",
2898 connector->base.id, connector->name,
2899 drm_get_connector_status_name(connector->status));
2900 if (connector->status == connector_status_connected) {
2901 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2902 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2903 connector->display_info.width_mm,
2904 connector->display_info.height_mm);
2905 seq_printf(m, "\tsubpixel order: %s\n",
2906 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2907 seq_printf(m, "\tCEA rev: %d\n",
2908 connector->display_info.cea_rev);
2909 }
2910
2911 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
2912 return;
2913
2914 switch (connector->connector_type) {
2915 case DRM_MODE_CONNECTOR_DisplayPort:
2916 case DRM_MODE_CONNECTOR_eDP:
2917 intel_dp_info(m, intel_connector);
2918 break;
2919 case DRM_MODE_CONNECTOR_LVDS:
2920 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2921 intel_lvds_info(m, intel_connector);
2922 break;
2923 case DRM_MODE_CONNECTOR_HDMIA:
2924 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
2925 intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
2926 intel_hdmi_info(m, intel_connector);
2927 break;
2928 default:
2929 break;
2930 }
2931
2932 seq_printf(m, "\tmodes:\n");
2933 list_for_each_entry(mode, &connector->modes, head)
2934 intel_seq_print_mode(m, 2, mode);
2935}
2936
2937static bool cursor_active(struct drm_i915_private *dev_priv, int pipe)
2938{
2939 u32 state;
2940
2941 if (IS_845G(dev_priv) || IS_I865G(dev_priv))
2942 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2943 else
2944 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2945
2946 return state;
2947}
2948
2949static bool cursor_position(struct drm_i915_private *dev_priv,
2950 int pipe, int *x, int *y)
2951{
2952 u32 pos;
2953
2954 pos = I915_READ(CURPOS(pipe));
2955
2956 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2957 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2958 *x = -*x;
2959
2960 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2961 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2962 *y = -*y;
2963
2964 return cursor_active(dev_priv, pipe);
2965}
2966
2967static const char *plane_type(enum drm_plane_type type)
2968{
2969 switch (type) {
2970 case DRM_PLANE_TYPE_OVERLAY:
2971 return "OVL";
2972 case DRM_PLANE_TYPE_PRIMARY:
2973 return "PRI";
2974 case DRM_PLANE_TYPE_CURSOR:
2975 return "CUR";
2976 /*
2977 * Deliberately omitting default: to generate compiler warnings
2978 * when a new drm_plane_type gets added.
2979 */
2980 }
2981
2982 return "unknown";
2983}
2984
2985static const char *plane_rotation(unsigned int rotation)
2986{
2987 static char buf[48];
2988 /*
2989 * According to doc only one DRM_ROTATE_ is allowed but this
2990 * will print them all to visualize if the values are misused
2991 */
2992 snprintf(buf, sizeof(buf),
2993 "%s%s%s%s%s%s(0x%08x)",
2994 (rotation & DRM_ROTATE_0) ? "0 " : "",
2995 (rotation & DRM_ROTATE_90) ? "90 " : "",
2996 (rotation & DRM_ROTATE_180) ? "180 " : "",
2997 (rotation & DRM_ROTATE_270) ? "270 " : "",
2998 (rotation & DRM_REFLECT_X) ? "FLIPX " : "",
2999 (rotation & DRM_REFLECT_Y) ? "FLIPY " : "",
3000 rotation);
3001
3002 return buf;
3003}
3004
3005static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3006{
3007 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3008 struct drm_device *dev = &dev_priv->drm;
3009 struct intel_plane *intel_plane;
3010
3011 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3012 struct drm_plane_state *state;
3013 struct drm_plane *plane = &intel_plane->base;
3014 struct drm_format_name_buf format_name;
3015
3016 if (!plane->state) {
3017 seq_puts(m, "plane->state is NULL!\n");
3018 continue;
3019 }
3020
3021 state = plane->state;
3022
3023 if (state->fb) {
3024 drm_get_format_name(state->fb->pixel_format, &format_name);
3025 } else {
3026 sprintf(format_name.str, "N/A");
3027 }
3028
3029 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3030 plane->base.id,
3031 plane_type(intel_plane->base.type),
3032 state->crtc_x, state->crtc_y,
3033 state->crtc_w, state->crtc_h,
3034 (state->src_x >> 16),
3035 ((state->src_x & 0xffff) * 15625) >> 10,
3036 (state->src_y >> 16),
3037 ((state->src_y & 0xffff) * 15625) >> 10,
3038 (state->src_w >> 16),
3039 ((state->src_w & 0xffff) * 15625) >> 10,
3040 (state->src_h >> 16),
3041 ((state->src_h & 0xffff) * 15625) >> 10,
3042 format_name.str,
3043 plane_rotation(state->rotation));
3044 }
3045}
3046
3047static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3048{
3049 struct intel_crtc_state *pipe_config;
3050 int num_scalers = intel_crtc->num_scalers;
3051 int i;
3052
3053 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3054
3055 /* Not all platformas have a scaler */
3056 if (num_scalers) {
3057 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3058 num_scalers,
3059 pipe_config->scaler_state.scaler_users,
3060 pipe_config->scaler_state.scaler_id);
3061
3062 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3063 struct intel_scaler *sc =
3064 &pipe_config->scaler_state.scalers[i];
3065
3066 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3067 i, yesno(sc->in_use), sc->mode);
3068 }
3069 seq_puts(m, "\n");
3070 } else {
3071 seq_puts(m, "\tNo scalers available on this platform\n");
3072 }
3073}
3074
3075static int i915_display_info(struct seq_file *m, void *unused)
3076{
3077 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3078 struct drm_device *dev = &dev_priv->drm;
3079 struct intel_crtc *crtc;
3080 struct drm_connector *connector;
3081
3082 intel_runtime_pm_get(dev_priv);
3083 drm_modeset_lock_all(dev);
3084 seq_printf(m, "CRTC info\n");
3085 seq_printf(m, "---------\n");
3086 for_each_intel_crtc(dev, crtc) {
3087 bool active;
3088 struct intel_crtc_state *pipe_config;
3089 int x, y;
3090
3091 pipe_config = to_intel_crtc_state(crtc->base.state);
3092
3093 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3094 crtc->base.base.id, pipe_name(crtc->pipe),
3095 yesno(pipe_config->base.active),
3096 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3097 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3098
3099 if (pipe_config->base.active) {
3100 intel_crtc_info(m, crtc);
3101
3102 active = cursor_position(dev_priv, crtc->pipe, &x, &y);
3103 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3104 yesno(crtc->cursor_base),
3105 x, y, crtc->base.cursor->state->crtc_w,
3106 crtc->base.cursor->state->crtc_h,
3107 crtc->cursor_addr, yesno(active));
3108 intel_scaler_info(m, crtc);
3109 intel_plane_info(m, crtc);
3110 }
3111
3112 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3113 yesno(!crtc->cpu_fifo_underrun_disabled),
3114 yesno(!crtc->pch_fifo_underrun_disabled));
3115 }
3116
3117 seq_printf(m, "\n");
3118 seq_printf(m, "Connector info\n");
3119 seq_printf(m, "--------------\n");
3120 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3121 intel_connector_info(m, connector);
3122 }
3123 drm_modeset_unlock_all(dev);
3124 intel_runtime_pm_put(dev_priv);
3125
3126 return 0;
3127}
3128
3129static int i915_engine_info(struct seq_file *m, void *unused)
3130{
3131 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3132 struct intel_engine_cs *engine;
3133 enum intel_engine_id id;
3134
3135 intel_runtime_pm_get(dev_priv);
3136
3137 for_each_engine(engine, dev_priv, id) {
3138 struct intel_breadcrumbs *b = &engine->breadcrumbs;
3139 struct drm_i915_gem_request *rq;
3140 struct rb_node *rb;
3141 u64 addr;
3142
3143 seq_printf(m, "%s\n", engine->name);
3144 seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [score %d]\n",
3145 intel_engine_get_seqno(engine),
3146 intel_engine_last_submit(engine),
3147 engine->hangcheck.seqno,
3148 engine->hangcheck.score);
3149
3150 rcu_read_lock();
3151
3152 seq_printf(m, "\tRequests:\n");
3153
3154 rq = list_first_entry(&engine->timeline->requests,
3155 struct drm_i915_gem_request, link);
3156 if (&rq->link != &engine->timeline->requests)
3157 print_request(m, rq, "\t\tfirst ");
3158
3159 rq = list_last_entry(&engine->timeline->requests,
3160 struct drm_i915_gem_request, link);
3161 if (&rq->link != &engine->timeline->requests)
3162 print_request(m, rq, "\t\tlast ");
3163
3164 rq = i915_gem_find_active_request(engine);
3165 if (rq) {
3166 print_request(m, rq, "\t\tactive ");
3167 seq_printf(m,
3168 "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n",
3169 rq->head, rq->postfix, rq->tail,
3170 rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
3171 rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
3172 }
3173
3174 seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n",
3175 I915_READ(RING_START(engine->mmio_base)),
3176 rq ? i915_ggtt_offset(rq->ring->vma) : 0);
3177 seq_printf(m, "\tRING_HEAD: 0x%08x [0x%08x]\n",
3178 I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR,
3179 rq ? rq->ring->head : 0);
3180 seq_printf(m, "\tRING_TAIL: 0x%08x [0x%08x]\n",
3181 I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR,
3182 rq ? rq->ring->tail : 0);
3183 seq_printf(m, "\tRING_CTL: 0x%08x [%s]\n",
3184 I915_READ(RING_CTL(engine->mmio_base)),
3185 I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : "");
3186
3187 rcu_read_unlock();
3188
3189 addr = intel_engine_get_active_head(engine);
3190 seq_printf(m, "\tACTHD: 0x%08x_%08x\n",
3191 upper_32_bits(addr), lower_32_bits(addr));
3192 addr = intel_engine_get_last_batch_head(engine);
3193 seq_printf(m, "\tBBADDR: 0x%08x_%08x\n",
3194 upper_32_bits(addr), lower_32_bits(addr));
3195
3196 if (i915.enable_execlists) {
3197 u32 ptr, read, write;
3198 struct rb_node *rb;
3199
3200 seq_printf(m, "\tExeclist status: 0x%08x %08x\n",
3201 I915_READ(RING_EXECLIST_STATUS_LO(engine)),
3202 I915_READ(RING_EXECLIST_STATUS_HI(engine)));
3203
3204 ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
3205 read = GEN8_CSB_READ_PTR(ptr);
3206 write = GEN8_CSB_WRITE_PTR(ptr);
3207 seq_printf(m, "\tExeclist CSB read %d, write %d\n",
3208 read, write);
3209 if (read >= GEN8_CSB_ENTRIES)
3210 read = 0;
3211 if (write >= GEN8_CSB_ENTRIES)
3212 write = 0;
3213 if (read > write)
3214 write += GEN8_CSB_ENTRIES;
3215 while (read < write) {
3216 unsigned int idx = ++read % GEN8_CSB_ENTRIES;
3217
3218 seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
3219 idx,
3220 I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
3221 I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
3222 }
3223
3224 rcu_read_lock();
3225 rq = READ_ONCE(engine->execlist_port[0].request);
3226 if (rq)
3227 print_request(m, rq, "\t\tELSP[0] ");
3228 else
3229 seq_printf(m, "\t\tELSP[0] idle\n");
3230 rq = READ_ONCE(engine->execlist_port[1].request);
3231 if (rq)
3232 print_request(m, rq, "\t\tELSP[1] ");
3233 else
3234 seq_printf(m, "\t\tELSP[1] idle\n");
3235 rcu_read_unlock();
3236
3237 spin_lock_irq(&engine->timeline->lock);
3238 for (rb = engine->execlist_first; rb; rb = rb_next(rb)) {
3239 rq = rb_entry(rb, typeof(*rq), priotree.node);
3240 print_request(m, rq, "\t\tQ ");
3241 }
3242 spin_unlock_irq(&engine->timeline->lock);
3243 } else if (INTEL_GEN(dev_priv) > 6) {
3244 seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
3245 I915_READ(RING_PP_DIR_BASE(engine)));
3246 seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
3247 I915_READ(RING_PP_DIR_BASE_READ(engine)));
3248 seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
3249 I915_READ(RING_PP_DIR_DCLV(engine)));
3250 }
3251
3252 spin_lock_irq(&b->lock);
3253 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
3254 struct intel_wait *w = container_of(rb, typeof(*w), node);
3255
3256 seq_printf(m, "\t%s [%d] waiting for %x\n",
3257 w->tsk->comm, w->tsk->pid, w->seqno);
3258 }
3259 spin_unlock_irq(&b->lock);
3260
3261 seq_puts(m, "\n");
3262 }
3263
3264 intel_runtime_pm_put(dev_priv);
3265
3266 return 0;
3267}
3268
3269static int i915_semaphore_status(struct seq_file *m, void *unused)
3270{
3271 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3272 struct drm_device *dev = &dev_priv->drm;
3273 struct intel_engine_cs *engine;
3274 int num_rings = INTEL_INFO(dev_priv)->num_rings;
3275 enum intel_engine_id id;
3276 int j, ret;
3277
3278 if (!i915.semaphores) {
3279 seq_puts(m, "Semaphores are disabled\n");
3280 return 0;
3281 }
3282
3283 ret = mutex_lock_interruptible(&dev->struct_mutex);
3284 if (ret)
3285 return ret;
3286 intel_runtime_pm_get(dev_priv);
3287
3288 if (IS_BROADWELL(dev_priv)) {
3289 struct page *page;
3290 uint64_t *seqno;
3291
3292 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
3293
3294 seqno = (uint64_t *)kmap_atomic(page);
3295 for_each_engine(engine, dev_priv, id) {
3296 uint64_t offset;
3297
3298 seq_printf(m, "%s\n", engine->name);
3299
3300 seq_puts(m, " Last signal:");
3301 for (j = 0; j < num_rings; j++) {
3302 offset = id * I915_NUM_ENGINES + j;
3303 seq_printf(m, "0x%08llx (0x%02llx) ",
3304 seqno[offset], offset * 8);
3305 }
3306 seq_putc(m, '\n');
3307
3308 seq_puts(m, " Last wait: ");
3309 for (j = 0; j < num_rings; j++) {
3310 offset = id + (j * I915_NUM_ENGINES);
3311 seq_printf(m, "0x%08llx (0x%02llx) ",
3312 seqno[offset], offset * 8);
3313 }
3314 seq_putc(m, '\n');
3315
3316 }
3317 kunmap_atomic(seqno);
3318 } else {
3319 seq_puts(m, " Last signal:");
3320 for_each_engine(engine, dev_priv, id)
3321 for (j = 0; j < num_rings; j++)
3322 seq_printf(m, "0x%08x\n",
3323 I915_READ(engine->semaphore.mbox.signal[j]));
3324 seq_putc(m, '\n');
3325 }
3326
3327 intel_runtime_pm_put(dev_priv);
3328 mutex_unlock(&dev->struct_mutex);
3329 return 0;
3330}
3331
3332static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3333{
3334 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3335 struct drm_device *dev = &dev_priv->drm;
3336 int i;
3337
3338 drm_modeset_lock_all(dev);
3339 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3340 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3341
3342 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3343 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3344 pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3345 seq_printf(m, " tracked hardware state:\n");
3346 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3347 seq_printf(m, " dpll_md: 0x%08x\n",
3348 pll->config.hw_state.dpll_md);
3349 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3350 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3351 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
3352 }
3353 drm_modeset_unlock_all(dev);
3354
3355 return 0;
3356}
3357
3358static int i915_wa_registers(struct seq_file *m, void *unused)
3359{
3360 int i;
3361 int ret;
3362 struct intel_engine_cs *engine;
3363 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3364 struct drm_device *dev = &dev_priv->drm;
3365 struct i915_workarounds *workarounds = &dev_priv->workarounds;
3366 enum intel_engine_id id;
3367
3368 ret = mutex_lock_interruptible(&dev->struct_mutex);
3369 if (ret)
3370 return ret;
3371
3372 intel_runtime_pm_get(dev_priv);
3373
3374 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3375 for_each_engine(engine, dev_priv, id)
3376 seq_printf(m, "HW whitelist count for %s: %d\n",
3377 engine->name, workarounds->hw_whitelist_count[id]);
3378 for (i = 0; i < workarounds->count; ++i) {
3379 i915_reg_t addr;
3380 u32 mask, value, read;
3381 bool ok;
3382
3383 addr = workarounds->reg[i].addr;
3384 mask = workarounds->reg[i].mask;
3385 value = workarounds->reg[i].value;
3386 read = I915_READ(addr);
3387 ok = (value & mask) == (read & mask);
3388 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3389 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3390 }
3391
3392 intel_runtime_pm_put(dev_priv);
3393 mutex_unlock(&dev->struct_mutex);
3394
3395 return 0;
3396}
3397
3398static int i915_ddb_info(struct seq_file *m, void *unused)
3399{
3400 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3401 struct drm_device *dev = &dev_priv->drm;
3402 struct skl_ddb_allocation *ddb;
3403 struct skl_ddb_entry *entry;
3404 enum pipe pipe;
3405 int plane;
3406
3407 if (INTEL_GEN(dev_priv) < 9)
3408 return 0;
3409
3410 drm_modeset_lock_all(dev);
3411
3412 ddb = &dev_priv->wm.skl_hw.ddb;
3413
3414 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3415
3416 for_each_pipe(dev_priv, pipe) {
3417 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3418
3419 for_each_universal_plane(dev_priv, pipe, plane) {
3420 entry = &ddb->plane[pipe][plane];
3421 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3422 entry->start, entry->end,
3423 skl_ddb_entry_size(entry));
3424 }
3425
3426 entry = &ddb->plane[pipe][PLANE_CURSOR];
3427 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3428 entry->end, skl_ddb_entry_size(entry));
3429 }
3430
3431 drm_modeset_unlock_all(dev);
3432
3433 return 0;
3434}
3435
3436static void drrs_status_per_crtc(struct seq_file *m,
3437 struct drm_device *dev,
3438 struct intel_crtc *intel_crtc)
3439{
3440 struct drm_i915_private *dev_priv = to_i915(dev);
3441 struct i915_drrs *drrs = &dev_priv->drrs;
3442 int vrefresh = 0;
3443 struct drm_connector *connector;
3444
3445 drm_for_each_connector(connector, dev) {
3446 if (connector->state->crtc != &intel_crtc->base)
3447 continue;
3448
3449 seq_printf(m, "%s:\n", connector->name);
3450 }
3451
3452 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3453 seq_puts(m, "\tVBT: DRRS_type: Static");
3454 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3455 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3456 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3457 seq_puts(m, "\tVBT: DRRS_type: None");
3458 else
3459 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3460
3461 seq_puts(m, "\n\n");
3462
3463 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3464 struct intel_panel *panel;
3465
3466 mutex_lock(&drrs->mutex);
3467 /* DRRS Supported */
3468 seq_puts(m, "\tDRRS Supported: Yes\n");
3469
3470 /* disable_drrs() will make drrs->dp NULL */
3471 if (!drrs->dp) {
3472 seq_puts(m, "Idleness DRRS: Disabled");
3473 mutex_unlock(&drrs->mutex);
3474 return;
3475 }
3476
3477 panel = &drrs->dp->attached_connector->panel;
3478 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3479 drrs->busy_frontbuffer_bits);
3480
3481 seq_puts(m, "\n\t\t");
3482 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3483 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3484 vrefresh = panel->fixed_mode->vrefresh;
3485 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3486 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3487 vrefresh = panel->downclock_mode->vrefresh;
3488 } else {
3489 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3490 drrs->refresh_rate_type);
3491 mutex_unlock(&drrs->mutex);
3492 return;
3493 }
3494 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3495
3496 seq_puts(m, "\n\t\t");
3497 mutex_unlock(&drrs->mutex);
3498 } else {
3499 /* DRRS not supported. Print the VBT parameter*/
3500 seq_puts(m, "\tDRRS Supported : No");
3501 }
3502 seq_puts(m, "\n");
3503}
3504
3505static int i915_drrs_status(struct seq_file *m, void *unused)
3506{
3507 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3508 struct drm_device *dev = &dev_priv->drm;
3509 struct intel_crtc *intel_crtc;
3510 int active_crtc_cnt = 0;
3511
3512 drm_modeset_lock_all(dev);
3513 for_each_intel_crtc(dev, intel_crtc) {
3514 if (intel_crtc->base.state->active) {
3515 active_crtc_cnt++;
3516 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3517
3518 drrs_status_per_crtc(m, dev, intel_crtc);
3519 }
3520 }
3521 drm_modeset_unlock_all(dev);
3522
3523 if (!active_crtc_cnt)
3524 seq_puts(m, "No active crtc found\n");
3525
3526 return 0;
3527}
3528
3529struct pipe_crc_info {
3530 const char *name;
3531 struct drm_i915_private *dev_priv;
3532 enum pipe pipe;
3533};
3534
3535static int i915_dp_mst_info(struct seq_file *m, void *unused)
3536{
3537 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3538 struct drm_device *dev = &dev_priv->drm;
3539 struct intel_encoder *intel_encoder;
3540 struct intel_digital_port *intel_dig_port;
3541 struct drm_connector *connector;
3542
3543 drm_modeset_lock_all(dev);
3544 drm_for_each_connector(connector, dev) {
3545 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3546 continue;
3547
3548 intel_encoder = intel_attached_encoder(connector);
3549 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3550 continue;
3551
3552 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3553 if (!intel_dig_port->dp.can_mst)
3554 continue;
3555
3556 seq_printf(m, "MST Source Port %c\n",
3557 port_name(intel_dig_port->port));
3558 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3559 }
3560 drm_modeset_unlock_all(dev);
3561 return 0;
3562}
3563
3564static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3565{
3566 struct pipe_crc_info *info = inode->i_private;
3567 struct drm_i915_private *dev_priv = info->dev_priv;
3568 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3569
3570 if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes)
3571 return -ENODEV;
3572
3573 spin_lock_irq(&pipe_crc->lock);
3574
3575 if (pipe_crc->opened) {
3576 spin_unlock_irq(&pipe_crc->lock);
3577 return -EBUSY; /* already open */
3578 }
3579
3580 pipe_crc->opened = true;
3581 filep->private_data = inode->i_private;
3582
3583 spin_unlock_irq(&pipe_crc->lock);
3584
3585 return 0;
3586}
3587
3588static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3589{
3590 struct pipe_crc_info *info = inode->i_private;
3591 struct drm_i915_private *dev_priv = info->dev_priv;
3592 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3593
3594 spin_lock_irq(&pipe_crc->lock);
3595 pipe_crc->opened = false;
3596 spin_unlock_irq(&pipe_crc->lock);
3597
3598 return 0;
3599}
3600
3601/* (6 fields, 8 chars each, space separated (5) + '\n') */
3602#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3603/* account for \'0' */
3604#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3605
3606static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3607{
3608 assert_spin_locked(&pipe_crc->lock);
3609 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3610 INTEL_PIPE_CRC_ENTRIES_NR);
3611}
3612
3613static ssize_t
3614i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3615 loff_t *pos)
3616{
3617 struct pipe_crc_info *info = filep->private_data;
3618 struct drm_i915_private *dev_priv = info->dev_priv;
3619 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3620 char buf[PIPE_CRC_BUFFER_LEN];
3621 int n_entries;
3622 ssize_t bytes_read;
3623
3624 /*
3625 * Don't allow user space to provide buffers not big enough to hold
3626 * a line of data.
3627 */
3628 if (count < PIPE_CRC_LINE_LEN)
3629 return -EINVAL;
3630
3631 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3632 return 0;
3633
3634 /* nothing to read */
3635 spin_lock_irq(&pipe_crc->lock);
3636 while (pipe_crc_data_count(pipe_crc) == 0) {
3637 int ret;
3638
3639 if (filep->f_flags & O_NONBLOCK) {
3640 spin_unlock_irq(&pipe_crc->lock);
3641 return -EAGAIN;
3642 }
3643
3644 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3645 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3646 if (ret) {
3647 spin_unlock_irq(&pipe_crc->lock);
3648 return ret;
3649 }
3650 }
3651
3652 /* We now have one or more entries to read */
3653 n_entries = count / PIPE_CRC_LINE_LEN;
3654
3655 bytes_read = 0;
3656 while (n_entries > 0) {
3657 struct intel_pipe_crc_entry *entry =
3658 &pipe_crc->entries[pipe_crc->tail];
3659
3660 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3661 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3662 break;
3663
3664 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3665 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3666
3667 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3668 "%8u %8x %8x %8x %8x %8x\n",
3669 entry->frame, entry->crc[0],
3670 entry->crc[1], entry->crc[2],
3671 entry->crc[3], entry->crc[4]);
3672
3673 spin_unlock_irq(&pipe_crc->lock);
3674
3675 if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN))
3676 return -EFAULT;
3677
3678 user_buf += PIPE_CRC_LINE_LEN;
3679 n_entries--;
3680
3681 spin_lock_irq(&pipe_crc->lock);
3682 }
3683
3684 spin_unlock_irq(&pipe_crc->lock);
3685
3686 return bytes_read;
3687}
3688
3689static const struct file_operations i915_pipe_crc_fops = {
3690 .owner = THIS_MODULE,
3691 .open = i915_pipe_crc_open,
3692 .read = i915_pipe_crc_read,
3693 .release = i915_pipe_crc_release,
3694};
3695
3696static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3697 {
3698 .name = "i915_pipe_A_crc",
3699 .pipe = PIPE_A,
3700 },
3701 {
3702 .name = "i915_pipe_B_crc",
3703 .pipe = PIPE_B,
3704 },
3705 {
3706 .name = "i915_pipe_C_crc",
3707 .pipe = PIPE_C,
3708 },
3709};
3710
3711static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3712 enum pipe pipe)
3713{
3714 struct drm_i915_private *dev_priv = to_i915(minor->dev);
3715 struct dentry *ent;
3716 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3717
3718 info->dev_priv = dev_priv;
3719 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3720 &i915_pipe_crc_fops);
3721 if (!ent)
3722 return -ENOMEM;
3723
3724 return drm_add_fake_info_node(minor, ent, info);
3725}
3726
3727static const char * const pipe_crc_sources[] = {
3728 "none",
3729 "plane1",
3730 "plane2",
3731 "pf",
3732 "pipe",
3733 "TV",
3734 "DP-B",
3735 "DP-C",
3736 "DP-D",
3737 "auto",
3738};
3739
3740static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3741{
3742 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3743 return pipe_crc_sources[source];
3744}
3745
3746static int display_crc_ctl_show(struct seq_file *m, void *data)
3747{
3748 struct drm_i915_private *dev_priv = m->private;
3749 int i;
3750
3751 for (i = 0; i < I915_MAX_PIPES; i++)
3752 seq_printf(m, "%c %s\n", pipe_name(i),
3753 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3754
3755 return 0;
3756}
3757
3758static int display_crc_ctl_open(struct inode *inode, struct file *file)
3759{
3760 return single_open(file, display_crc_ctl_show, inode->i_private);
3761}
3762
3763static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3764 uint32_t *val)
3765{
3766 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3767 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3768
3769 switch (*source) {
3770 case INTEL_PIPE_CRC_SOURCE_PIPE:
3771 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3772 break;
3773 case INTEL_PIPE_CRC_SOURCE_NONE:
3774 *val = 0;
3775 break;
3776 default:
3777 return -EINVAL;
3778 }
3779
3780 return 0;
3781}
3782
3783static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
3784 enum pipe pipe,
3785 enum intel_pipe_crc_source *source)
3786{
3787 struct drm_device *dev = &dev_priv->drm;
3788 struct intel_encoder *encoder;
3789 struct intel_crtc *crtc;
3790 struct intel_digital_port *dig_port;
3791 int ret = 0;
3792
3793 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3794
3795 drm_modeset_lock_all(dev);
3796 for_each_intel_encoder(dev, encoder) {
3797 if (!encoder->base.crtc)
3798 continue;
3799
3800 crtc = to_intel_crtc(encoder->base.crtc);
3801
3802 if (crtc->pipe != pipe)
3803 continue;
3804
3805 switch (encoder->type) {
3806 case INTEL_OUTPUT_TVOUT:
3807 *source = INTEL_PIPE_CRC_SOURCE_TV;
3808 break;
3809 case INTEL_OUTPUT_DP:
3810 case INTEL_OUTPUT_EDP:
3811 dig_port = enc_to_dig_port(&encoder->base);
3812 switch (dig_port->port) {
3813 case PORT_B:
3814 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3815 break;
3816 case PORT_C:
3817 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3818 break;
3819 case PORT_D:
3820 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3821 break;
3822 default:
3823 WARN(1, "nonexisting DP port %c\n",
3824 port_name(dig_port->port));
3825 break;
3826 }
3827 break;
3828 default:
3829 break;
3830 }
3831 }
3832 drm_modeset_unlock_all(dev);
3833
3834 return ret;
3835}
3836
3837static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3838 enum pipe pipe,
3839 enum intel_pipe_crc_source *source,
3840 uint32_t *val)
3841{
3842 bool need_stable_symbols = false;
3843
3844 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3845 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3846 if (ret)
3847 return ret;
3848 }
3849
3850 switch (*source) {
3851 case INTEL_PIPE_CRC_SOURCE_PIPE:
3852 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3853 break;
3854 case INTEL_PIPE_CRC_SOURCE_DP_B:
3855 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3856 need_stable_symbols = true;
3857 break;
3858 case INTEL_PIPE_CRC_SOURCE_DP_C:
3859 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3860 need_stable_symbols = true;
3861 break;
3862 case INTEL_PIPE_CRC_SOURCE_DP_D:
3863 if (!IS_CHERRYVIEW(dev_priv))
3864 return -EINVAL;
3865 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3866 need_stable_symbols = true;
3867 break;
3868 case INTEL_PIPE_CRC_SOURCE_NONE:
3869 *val = 0;
3870 break;
3871 default:
3872 return -EINVAL;
3873 }
3874
3875 /*
3876 * When the pipe CRC tap point is after the transcoders we need
3877 * to tweak symbol-level features to produce a deterministic series of
3878 * symbols for a given frame. We need to reset those features only once
3879 * a frame (instead of every nth symbol):
3880 * - DC-balance: used to ensure a better clock recovery from the data
3881 * link (SDVO)
3882 * - DisplayPort scrambling: used for EMI reduction
3883 */
3884 if (need_stable_symbols) {
3885 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3886
3887 tmp |= DC_BALANCE_RESET_VLV;
3888 switch (pipe) {
3889 case PIPE_A:
3890 tmp |= PIPE_A_SCRAMBLE_RESET;
3891 break;
3892 case PIPE_B:
3893 tmp |= PIPE_B_SCRAMBLE_RESET;
3894 break;
3895 case PIPE_C:
3896 tmp |= PIPE_C_SCRAMBLE_RESET;
3897 break;
3898 default:
3899 return -EINVAL;
3900 }
3901 I915_WRITE(PORT_DFT2_G4X, tmp);
3902 }
3903
3904 return 0;
3905}
3906
3907static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3908 enum pipe pipe,
3909 enum intel_pipe_crc_source *source,
3910 uint32_t *val)
3911{
3912 bool need_stable_symbols = false;
3913
3914 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3915 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3916 if (ret)
3917 return ret;
3918 }
3919
3920 switch (*source) {
3921 case INTEL_PIPE_CRC_SOURCE_PIPE:
3922 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3923 break;
3924 case INTEL_PIPE_CRC_SOURCE_TV:
3925 if (!SUPPORTS_TV(dev_priv))
3926 return -EINVAL;
3927 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3928 break;
3929 case INTEL_PIPE_CRC_SOURCE_DP_B:
3930 if (!IS_G4X(dev_priv))
3931 return -EINVAL;
3932 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3933 need_stable_symbols = true;
3934 break;
3935 case INTEL_PIPE_CRC_SOURCE_DP_C:
3936 if (!IS_G4X(dev_priv))
3937 return -EINVAL;
3938 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3939 need_stable_symbols = true;
3940 break;
3941 case INTEL_PIPE_CRC_SOURCE_DP_D:
3942 if (!IS_G4X(dev_priv))
3943 return -EINVAL;
3944 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3945 need_stable_symbols = true;
3946 break;
3947 case INTEL_PIPE_CRC_SOURCE_NONE:
3948 *val = 0;
3949 break;
3950 default:
3951 return -EINVAL;
3952 }
3953
3954 /*
3955 * When the pipe CRC tap point is after the transcoders we need
3956 * to tweak symbol-level features to produce a deterministic series of
3957 * symbols for a given frame. We need to reset those features only once
3958 * a frame (instead of every nth symbol):
3959 * - DC-balance: used to ensure a better clock recovery from the data
3960 * link (SDVO)
3961 * - DisplayPort scrambling: used for EMI reduction
3962 */
3963 if (need_stable_symbols) {
3964 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3965
3966 WARN_ON(!IS_G4X(dev_priv));
3967
3968 I915_WRITE(PORT_DFT_I9XX,
3969 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3970
3971 if (pipe == PIPE_A)
3972 tmp |= PIPE_A_SCRAMBLE_RESET;
3973 else
3974 tmp |= PIPE_B_SCRAMBLE_RESET;
3975
3976 I915_WRITE(PORT_DFT2_G4X, tmp);
3977 }
3978
3979 return 0;
3980}
3981
3982static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
3983 enum pipe pipe)
3984{
3985 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3986
3987 switch (pipe) {
3988 case PIPE_A:
3989 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3990 break;
3991 case PIPE_B:
3992 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3993 break;
3994 case PIPE_C:
3995 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3996 break;
3997 default:
3998 return;
3999 }
4000 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
4001 tmp &= ~DC_BALANCE_RESET_VLV;
4002 I915_WRITE(PORT_DFT2_G4X, tmp);
4003
4004}
4005
4006static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
4007 enum pipe pipe)
4008{
4009 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
4010
4011 if (pipe == PIPE_A)
4012 tmp &= ~PIPE_A_SCRAMBLE_RESET;
4013 else
4014 tmp &= ~PIPE_B_SCRAMBLE_RESET;
4015 I915_WRITE(PORT_DFT2_G4X, tmp);
4016
4017 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
4018 I915_WRITE(PORT_DFT_I9XX,
4019 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
4020 }
4021}
4022
4023static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
4024 uint32_t *val)
4025{
4026 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4027 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
4028
4029 switch (*source) {
4030 case INTEL_PIPE_CRC_SOURCE_PLANE1:
4031 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
4032 break;
4033 case INTEL_PIPE_CRC_SOURCE_PLANE2:
4034 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
4035 break;
4036 case INTEL_PIPE_CRC_SOURCE_PIPE:
4037 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
4038 break;
4039 case INTEL_PIPE_CRC_SOURCE_NONE:
4040 *val = 0;
4041 break;
4042 default:
4043 return -EINVAL;
4044 }
4045
4046 return 0;
4047}
4048
4049static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
4050 bool enable)
4051{
4052 struct drm_device *dev = &dev_priv->drm;
4053 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
4054 struct intel_crtc_state *pipe_config;
4055 struct drm_atomic_state *state;
4056 int ret = 0;
4057
4058 drm_modeset_lock_all(dev);
4059 state = drm_atomic_state_alloc(dev);
4060 if (!state) {
4061 ret = -ENOMEM;
4062 goto out;
4063 }
4064
4065 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
4066 pipe_config = intel_atomic_get_crtc_state(state, crtc);
4067 if (IS_ERR(pipe_config)) {
4068 ret = PTR_ERR(pipe_config);
4069 goto out;
4070 }
4071
4072 pipe_config->pch_pfit.force_thru = enable;
4073 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
4074 pipe_config->pch_pfit.enabled != enable)
4075 pipe_config->base.connectors_changed = true;
4076
4077 ret = drm_atomic_commit(state);
4078out:
4079 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
4080 drm_modeset_unlock_all(dev);
4081 drm_atomic_state_put(state);
4082}
4083
4084static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
4085 enum pipe pipe,
4086 enum intel_pipe_crc_source *source,
4087 uint32_t *val)
4088{
4089 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4090 *source = INTEL_PIPE_CRC_SOURCE_PF;
4091
4092 switch (*source) {
4093 case INTEL_PIPE_CRC_SOURCE_PLANE1:
4094 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4095 break;
4096 case INTEL_PIPE_CRC_SOURCE_PLANE2:
4097 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4098 break;
4099 case INTEL_PIPE_CRC_SOURCE_PF:
4100 if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
4101 hsw_trans_edp_pipe_A_crc_wa(dev_priv, true);
4102
4103 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4104 break;
4105 case INTEL_PIPE_CRC_SOURCE_NONE:
4106 *val = 0;
4107 break;
4108 default:
4109 return -EINVAL;
4110 }
4111
4112 return 0;
4113}
4114
4115static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
4116 enum pipe pipe,
4117 enum intel_pipe_crc_source source)
4118{
4119 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4120 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
4121 enum intel_display_power_domain power_domain;
4122 u32 val = 0; /* shut up gcc */
4123 int ret;
4124
4125 if (pipe_crc->source == source)
4126 return 0;
4127
4128 /* forbid changing the source without going back to 'none' */
4129 if (pipe_crc->source && source)
4130 return -EINVAL;
4131
4132 power_domain = POWER_DOMAIN_PIPE(pipe);
4133 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4134 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4135 return -EIO;
4136 }
4137
4138 if (IS_GEN2(dev_priv))
4139 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4140 else if (INTEL_GEN(dev_priv) < 5)
4141 ret = i9xx_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4142 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4143 ret = vlv_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4144 else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
4145 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4146 else
4147 ret = ivb_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4148
4149 if (ret != 0)
4150 goto out;
4151
4152 /* none -> real source transition */
4153 if (source) {
4154 struct intel_pipe_crc_entry *entries;
4155
4156 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4157 pipe_name(pipe), pipe_crc_source_name(source));
4158
4159 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4160 sizeof(pipe_crc->entries[0]),
4161 GFP_KERNEL);
4162 if (!entries) {
4163 ret = -ENOMEM;
4164 goto out;
4165 }
4166
4167 /*
4168 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4169 * enabled and disabled dynamically based on package C states,
4170 * user space can't make reliable use of the CRCs, so let's just
4171 * completely disable it.
4172 */
4173 hsw_disable_ips(crtc);
4174
4175 spin_lock_irq(&pipe_crc->lock);
4176 kfree(pipe_crc->entries);
4177 pipe_crc->entries = entries;
4178 pipe_crc->head = 0;
4179 pipe_crc->tail = 0;
4180 spin_unlock_irq(&pipe_crc->lock);
4181 }
4182
4183 pipe_crc->source = source;
4184
4185 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4186 POSTING_READ(PIPE_CRC_CTL(pipe));
4187
4188 /* real source -> none transition */
4189 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4190 struct intel_pipe_crc_entry *entries;
4191 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
4192 pipe);
4193
4194 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4195 pipe_name(pipe));
4196
4197 drm_modeset_lock(&crtc->base.mutex, NULL);
4198 if (crtc->base.state->active)
4199 intel_wait_for_vblank(dev_priv, pipe);
4200 drm_modeset_unlock(&crtc->base.mutex);
4201
4202 spin_lock_irq(&pipe_crc->lock);
4203 entries = pipe_crc->entries;
4204 pipe_crc->entries = NULL;
4205 pipe_crc->head = 0;
4206 pipe_crc->tail = 0;
4207 spin_unlock_irq(&pipe_crc->lock);
4208
4209 kfree(entries);
4210
4211 if (IS_G4X(dev_priv))
4212 g4x_undo_pipe_scramble_reset(dev_priv, pipe);
4213 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4214 vlv_undo_pipe_scramble_reset(dev_priv, pipe);
4215 else if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
4216 hsw_trans_edp_pipe_A_crc_wa(dev_priv, false);
4217
4218 hsw_enable_ips(crtc);
4219 }
4220
4221 ret = 0;
4222
4223out:
4224 intel_display_power_put(dev_priv, power_domain);
4225
4226 return ret;
4227}
4228
4229/*
4230 * Parse pipe CRC command strings:
4231 * command: wsp* object wsp+ name wsp+ source wsp*
4232 * object: 'pipe'
4233 * name: (A | B | C)
4234 * source: (none | plane1 | plane2 | pf)
4235 * wsp: (#0x20 | #0x9 | #0xA)+
4236 *
4237 * eg.:
4238 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4239 * "pipe A none" -> Stop CRC
4240 */
4241static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4242{
4243 int n_words = 0;
4244
4245 while (*buf) {
4246 char *end;
4247
4248 /* skip leading white space */
4249 buf = skip_spaces(buf);
4250 if (!*buf)
4251 break; /* end of buffer */
4252
4253 /* find end of word */
4254 for (end = buf; *end && !isspace(*end); end++)
4255 ;
4256
4257 if (n_words == max_words) {
4258 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4259 max_words);
4260 return -EINVAL; /* ran out of words[] before bytes */
4261 }
4262
4263 if (*end)
4264 *end++ = '\0';
4265 words[n_words++] = buf;
4266 buf = end;
4267 }
4268
4269 return n_words;
4270}
4271
4272enum intel_pipe_crc_object {
4273 PIPE_CRC_OBJECT_PIPE,
4274};
4275
4276static const char * const pipe_crc_objects[] = {
4277 "pipe",
4278};
4279
4280static int
4281display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4282{
4283 int i;
4284
4285 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4286 if (!strcmp(buf, pipe_crc_objects[i])) {
4287 *o = i;
4288 return 0;
4289 }
4290
4291 return -EINVAL;
4292}
4293
4294static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4295{
4296 const char name = buf[0];
4297
4298 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4299 return -EINVAL;
4300
4301 *pipe = name - 'A';
4302
4303 return 0;
4304}
4305
4306static int
4307display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4308{
4309 int i;
4310
4311 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4312 if (!strcmp(buf, pipe_crc_sources[i])) {
4313 *s = i;
4314 return 0;
4315 }
4316
4317 return -EINVAL;
4318}
4319
4320static int display_crc_ctl_parse(struct drm_i915_private *dev_priv,
4321 char *buf, size_t len)
4322{
4323#define N_WORDS 3
4324 int n_words;
4325 char *words[N_WORDS];
4326 enum pipe pipe;
4327 enum intel_pipe_crc_object object;
4328 enum intel_pipe_crc_source source;
4329
4330 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4331 if (n_words != N_WORDS) {
4332 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4333 N_WORDS);
4334 return -EINVAL;
4335 }
4336
4337 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4338 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4339 return -EINVAL;
4340 }
4341
4342 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4343 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4344 return -EINVAL;
4345 }
4346
4347 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4348 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4349 return -EINVAL;
4350 }
4351
4352 return pipe_crc_set_source(dev_priv, pipe, source);
4353}
4354
4355static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4356 size_t len, loff_t *offp)
4357{
4358 struct seq_file *m = file->private_data;
4359 struct drm_i915_private *dev_priv = m->private;
4360 char *tmpbuf;
4361 int ret;
4362
4363 if (len == 0)
4364 return 0;
4365
4366 if (len > PAGE_SIZE - 1) {
4367 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4368 PAGE_SIZE);
4369 return -E2BIG;
4370 }
4371
4372 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4373 if (!tmpbuf)
4374 return -ENOMEM;
4375
4376 if (copy_from_user(tmpbuf, ubuf, len)) {
4377 ret = -EFAULT;
4378 goto out;
4379 }
4380 tmpbuf[len] = '\0';
4381
4382 ret = display_crc_ctl_parse(dev_priv, tmpbuf, len);
4383
4384out:
4385 kfree(tmpbuf);
4386 if (ret < 0)
4387 return ret;
4388
4389 *offp += len;
4390 return len;
4391}
4392
4393static const struct file_operations i915_display_crc_ctl_fops = {
4394 .owner = THIS_MODULE,
4395 .open = display_crc_ctl_open,
4396 .read = seq_read,
4397 .llseek = seq_lseek,
4398 .release = single_release,
4399 .write = display_crc_ctl_write
4400};
4401
4402static ssize_t i915_displayport_test_active_write(struct file *file,
4403 const char __user *ubuf,
4404 size_t len, loff_t *offp)
4405{
4406 char *input_buffer;
4407 int status = 0;
4408 struct drm_device *dev;
4409 struct drm_connector *connector;
4410 struct list_head *connector_list;
4411 struct intel_dp *intel_dp;
4412 int val = 0;
4413
4414 dev = ((struct seq_file *)file->private_data)->private;
4415
4416 connector_list = &dev->mode_config.connector_list;
4417
4418 if (len == 0)
4419 return 0;
4420
4421 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4422 if (!input_buffer)
4423 return -ENOMEM;
4424
4425 if (copy_from_user(input_buffer, ubuf, len)) {
4426 status = -EFAULT;
4427 goto out;
4428 }
4429
4430 input_buffer[len] = '\0';
4431 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4432
4433 list_for_each_entry(connector, connector_list, head) {
4434 if (connector->connector_type !=
4435 DRM_MODE_CONNECTOR_DisplayPort)
4436 continue;
4437
4438 if (connector->status == connector_status_connected &&
4439 connector->encoder != NULL) {
4440 intel_dp = enc_to_intel_dp(connector->encoder);
4441 status = kstrtoint(input_buffer, 10, &val);
4442 if (status < 0)
4443 goto out;
4444 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4445 /* To prevent erroneous activation of the compliance
4446 * testing code, only accept an actual value of 1 here
4447 */
4448 if (val == 1)
4449 intel_dp->compliance_test_active = 1;
4450 else
4451 intel_dp->compliance_test_active = 0;
4452 }
4453 }
4454out:
4455 kfree(input_buffer);
4456 if (status < 0)
4457 return status;
4458
4459 *offp += len;
4460 return len;
4461}
4462
4463static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4464{
4465 struct drm_device *dev = m->private;
4466 struct drm_connector *connector;
4467 struct list_head *connector_list = &dev->mode_config.connector_list;
4468 struct intel_dp *intel_dp;
4469
4470 list_for_each_entry(connector, connector_list, head) {
4471 if (connector->connector_type !=
4472 DRM_MODE_CONNECTOR_DisplayPort)
4473 continue;
4474
4475 if (connector->status == connector_status_connected &&
4476 connector->encoder != NULL) {
4477 intel_dp = enc_to_intel_dp(connector->encoder);
4478 if (intel_dp->compliance_test_active)
4479 seq_puts(m, "1");
4480 else
4481 seq_puts(m, "0");
4482 } else
4483 seq_puts(m, "0");
4484 }
4485
4486 return 0;
4487}
4488
4489static int i915_displayport_test_active_open(struct inode *inode,
4490 struct file *file)
4491{
4492 struct drm_i915_private *dev_priv = inode->i_private;
4493
4494 return single_open(file, i915_displayport_test_active_show,
4495 &dev_priv->drm);
4496}
4497
4498static const struct file_operations i915_displayport_test_active_fops = {
4499 .owner = THIS_MODULE,
4500 .open = i915_displayport_test_active_open,
4501 .read = seq_read,
4502 .llseek = seq_lseek,
4503 .release = single_release,
4504 .write = i915_displayport_test_active_write
4505};
4506
4507static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4508{
4509 struct drm_device *dev = m->private;
4510 struct drm_connector *connector;
4511 struct list_head *connector_list = &dev->mode_config.connector_list;
4512 struct intel_dp *intel_dp;
4513
4514 list_for_each_entry(connector, connector_list, head) {
4515 if (connector->connector_type !=
4516 DRM_MODE_CONNECTOR_DisplayPort)
4517 continue;
4518
4519 if (connector->status == connector_status_connected &&
4520 connector->encoder != NULL) {
4521 intel_dp = enc_to_intel_dp(connector->encoder);
4522 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4523 } else
4524 seq_puts(m, "0");
4525 }
4526
4527 return 0;
4528}
4529static int i915_displayport_test_data_open(struct inode *inode,
4530 struct file *file)
4531{
4532 struct drm_i915_private *dev_priv = inode->i_private;
4533
4534 return single_open(file, i915_displayport_test_data_show,
4535 &dev_priv->drm);
4536}
4537
4538static const struct file_operations i915_displayport_test_data_fops = {
4539 .owner = THIS_MODULE,
4540 .open = i915_displayport_test_data_open,
4541 .read = seq_read,
4542 .llseek = seq_lseek,
4543 .release = single_release
4544};
4545
4546static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4547{
4548 struct drm_device *dev = m->private;
4549 struct drm_connector *connector;
4550 struct list_head *connector_list = &dev->mode_config.connector_list;
4551 struct intel_dp *intel_dp;
4552
4553 list_for_each_entry(connector, connector_list, head) {
4554 if (connector->connector_type !=
4555 DRM_MODE_CONNECTOR_DisplayPort)
4556 continue;
4557
4558 if (connector->status == connector_status_connected &&
4559 connector->encoder != NULL) {
4560 intel_dp = enc_to_intel_dp(connector->encoder);
4561 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4562 } else
4563 seq_puts(m, "0");
4564 }
4565
4566 return 0;
4567}
4568
4569static int i915_displayport_test_type_open(struct inode *inode,
4570 struct file *file)
4571{
4572 struct drm_i915_private *dev_priv = inode->i_private;
4573
4574 return single_open(file, i915_displayport_test_type_show,
4575 &dev_priv->drm);
4576}
4577
4578static const struct file_operations i915_displayport_test_type_fops = {
4579 .owner = THIS_MODULE,
4580 .open = i915_displayport_test_type_open,
4581 .read = seq_read,
4582 .llseek = seq_lseek,
4583 .release = single_release
4584};
4585
4586static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4587{
4588 struct drm_i915_private *dev_priv = m->private;
4589 struct drm_device *dev = &dev_priv->drm;
4590 int level;
4591 int num_levels;
4592
4593 if (IS_CHERRYVIEW(dev_priv))
4594 num_levels = 3;
4595 else if (IS_VALLEYVIEW(dev_priv))
4596 num_levels = 1;
4597 else
4598 num_levels = ilk_wm_max_level(dev_priv) + 1;
4599
4600 drm_modeset_lock_all(dev);
4601
4602 for (level = 0; level < num_levels; level++) {
4603 unsigned int latency = wm[level];
4604
4605 /*
4606 * - WM1+ latency values in 0.5us units
4607 * - latencies are in us on gen9/vlv/chv
4608 */
4609 if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) ||
4610 IS_CHERRYVIEW(dev_priv))
4611 latency *= 10;
4612 else if (level > 0)
4613 latency *= 5;
4614
4615 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4616 level, wm[level], latency / 10, latency % 10);
4617 }
4618
4619 drm_modeset_unlock_all(dev);
4620}
4621
4622static int pri_wm_latency_show(struct seq_file *m, void *data)
4623{
4624 struct drm_i915_private *dev_priv = m->private;
4625 const uint16_t *latencies;
4626
4627 if (INTEL_GEN(dev_priv) >= 9)
4628 latencies = dev_priv->wm.skl_latency;
4629 else
4630 latencies = dev_priv->wm.pri_latency;
4631
4632 wm_latency_show(m, latencies);
4633
4634 return 0;
4635}
4636
4637static int spr_wm_latency_show(struct seq_file *m, void *data)
4638{
4639 struct drm_i915_private *dev_priv = m->private;
4640 const uint16_t *latencies;
4641
4642 if (INTEL_GEN(dev_priv) >= 9)
4643 latencies = dev_priv->wm.skl_latency;
4644 else
4645 latencies = dev_priv->wm.spr_latency;
4646
4647 wm_latency_show(m, latencies);
4648
4649 return 0;
4650}
4651
4652static int cur_wm_latency_show(struct seq_file *m, void *data)
4653{
4654 struct drm_i915_private *dev_priv = m->private;
4655 const uint16_t *latencies;
4656
4657 if (INTEL_GEN(dev_priv) >= 9)
4658 latencies = dev_priv->wm.skl_latency;
4659 else
4660 latencies = dev_priv->wm.cur_latency;
4661
4662 wm_latency_show(m, latencies);
4663
4664 return 0;
4665}
4666
4667static int pri_wm_latency_open(struct inode *inode, struct file *file)
4668{
4669 struct drm_i915_private *dev_priv = inode->i_private;
4670
4671 if (INTEL_GEN(dev_priv) < 5)
4672 return -ENODEV;
4673
4674 return single_open(file, pri_wm_latency_show, dev_priv);
4675}
4676
4677static int spr_wm_latency_open(struct inode *inode, struct file *file)
4678{
4679 struct drm_i915_private *dev_priv = inode->i_private;
4680
4681 if (HAS_GMCH_DISPLAY(dev_priv))
4682 return -ENODEV;
4683
4684 return single_open(file, spr_wm_latency_show, dev_priv);
4685}
4686
4687static int cur_wm_latency_open(struct inode *inode, struct file *file)
4688{
4689 struct drm_i915_private *dev_priv = inode->i_private;
4690
4691 if (HAS_GMCH_DISPLAY(dev_priv))
4692 return -ENODEV;
4693
4694 return single_open(file, cur_wm_latency_show, dev_priv);
4695}
4696
4697static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4698 size_t len, loff_t *offp, uint16_t wm[8])
4699{
4700 struct seq_file *m = file->private_data;
4701 struct drm_i915_private *dev_priv = m->private;
4702 struct drm_device *dev = &dev_priv->drm;
4703 uint16_t new[8] = { 0 };
4704 int num_levels;
4705 int level;
4706 int ret;
4707 char tmp[32];
4708
4709 if (IS_CHERRYVIEW(dev_priv))
4710 num_levels = 3;
4711 else if (IS_VALLEYVIEW(dev_priv))
4712 num_levels = 1;
4713 else
4714 num_levels = ilk_wm_max_level(dev_priv) + 1;
4715
4716 if (len >= sizeof(tmp))
4717 return -EINVAL;
4718
4719 if (copy_from_user(tmp, ubuf, len))
4720 return -EFAULT;
4721
4722 tmp[len] = '\0';
4723
4724 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4725 &new[0], &new[1], &new[2], &new[3],
4726 &new[4], &new[5], &new[6], &new[7]);
4727 if (ret != num_levels)
4728 return -EINVAL;
4729
4730 drm_modeset_lock_all(dev);
4731
4732 for (level = 0; level < num_levels; level++)
4733 wm[level] = new[level];
4734
4735 drm_modeset_unlock_all(dev);
4736
4737 return len;
4738}
4739
4740
4741static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4742 size_t len, loff_t *offp)
4743{
4744 struct seq_file *m = file->private_data;
4745 struct drm_i915_private *dev_priv = m->private;
4746 uint16_t *latencies;
4747
4748 if (INTEL_GEN(dev_priv) >= 9)
4749 latencies = dev_priv->wm.skl_latency;
4750 else
4751 latencies = dev_priv->wm.pri_latency;
4752
4753 return wm_latency_write(file, ubuf, len, offp, latencies);
4754}
4755
4756static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4757 size_t len, loff_t *offp)
4758{
4759 struct seq_file *m = file->private_data;
4760 struct drm_i915_private *dev_priv = m->private;
4761 uint16_t *latencies;
4762
4763 if (INTEL_GEN(dev_priv) >= 9)
4764 latencies = dev_priv->wm.skl_latency;
4765 else
4766 latencies = dev_priv->wm.spr_latency;
4767
4768 return wm_latency_write(file, ubuf, len, offp, latencies);
4769}
4770
4771static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4772 size_t len, loff_t *offp)
4773{
4774 struct seq_file *m = file->private_data;
4775 struct drm_i915_private *dev_priv = m->private;
4776 uint16_t *latencies;
4777
4778 if (INTEL_GEN(dev_priv) >= 9)
4779 latencies = dev_priv->wm.skl_latency;
4780 else
4781 latencies = dev_priv->wm.cur_latency;
4782
4783 return wm_latency_write(file, ubuf, len, offp, latencies);
4784}
4785
4786static const struct file_operations i915_pri_wm_latency_fops = {
4787 .owner = THIS_MODULE,
4788 .open = pri_wm_latency_open,
4789 .read = seq_read,
4790 .llseek = seq_lseek,
4791 .release = single_release,
4792 .write = pri_wm_latency_write
4793};
4794
4795static const struct file_operations i915_spr_wm_latency_fops = {
4796 .owner = THIS_MODULE,
4797 .open = spr_wm_latency_open,
4798 .read = seq_read,
4799 .llseek = seq_lseek,
4800 .release = single_release,
4801 .write = spr_wm_latency_write
4802};
4803
4804static const struct file_operations i915_cur_wm_latency_fops = {
4805 .owner = THIS_MODULE,
4806 .open = cur_wm_latency_open,
4807 .read = seq_read,
4808 .llseek = seq_lseek,
4809 .release = single_release,
4810 .write = cur_wm_latency_write
4811};
4812
4813static int
4814i915_wedged_get(void *data, u64 *val)
4815{
4816 struct drm_i915_private *dev_priv = data;
4817
4818 *val = i915_terminally_wedged(&dev_priv->gpu_error);
4819
4820 return 0;
4821}
4822
4823static int
4824i915_wedged_set(void *data, u64 val)
4825{
4826 struct drm_i915_private *dev_priv = data;
4827
4828 /*
4829 * There is no safeguard against this debugfs entry colliding
4830 * with the hangcheck calling same i915_handle_error() in
4831 * parallel, causing an explosion. For now we assume that the
4832 * test harness is responsible enough not to inject gpu hangs
4833 * while it is writing to 'i915_wedged'
4834 */
4835
4836 if (i915_reset_in_progress(&dev_priv->gpu_error))
4837 return -EAGAIN;
4838
4839 i915_handle_error(dev_priv, val,
4840 "Manually setting wedged to %llu", val);
4841
4842 return 0;
4843}
4844
4845DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4846 i915_wedged_get, i915_wedged_set,
4847 "%llu\n");
4848
4849static int
4850i915_ring_missed_irq_get(void *data, u64 *val)
4851{
4852 struct drm_i915_private *dev_priv = data;
4853
4854 *val = dev_priv->gpu_error.missed_irq_rings;
4855 return 0;
4856}
4857
4858static int
4859i915_ring_missed_irq_set(void *data, u64 val)
4860{
4861 struct drm_i915_private *dev_priv = data;
4862 struct drm_device *dev = &dev_priv->drm;
4863 int ret;
4864
4865 /* Lock against concurrent debugfs callers */
4866 ret = mutex_lock_interruptible(&dev->struct_mutex);
4867 if (ret)
4868 return ret;
4869 dev_priv->gpu_error.missed_irq_rings = val;
4870 mutex_unlock(&dev->struct_mutex);
4871
4872 return 0;
4873}
4874
4875DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4876 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4877 "0x%08llx\n");
4878
4879static int
4880i915_ring_test_irq_get(void *data, u64 *val)
4881{
4882 struct drm_i915_private *dev_priv = data;
4883
4884 *val = dev_priv->gpu_error.test_irq_rings;
4885
4886 return 0;
4887}
4888
4889static int
4890i915_ring_test_irq_set(void *data, u64 val)
4891{
4892 struct drm_i915_private *dev_priv = data;
4893
4894 val &= INTEL_INFO(dev_priv)->ring_mask;
4895 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4896 dev_priv->gpu_error.test_irq_rings = val;
4897
4898 return 0;
4899}
4900
4901DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4902 i915_ring_test_irq_get, i915_ring_test_irq_set,
4903 "0x%08llx\n");
4904
4905#define DROP_UNBOUND 0x1
4906#define DROP_BOUND 0x2
4907#define DROP_RETIRE 0x4
4908#define DROP_ACTIVE 0x8
4909#define DROP_FREED 0x10
4910#define DROP_ALL (DROP_UNBOUND | \
4911 DROP_BOUND | \
4912 DROP_RETIRE | \
4913 DROP_ACTIVE | \
4914 DROP_FREED)
4915static int
4916i915_drop_caches_get(void *data, u64 *val)
4917{
4918 *val = DROP_ALL;
4919
4920 return 0;
4921}
4922
4923static int
4924i915_drop_caches_set(void *data, u64 val)
4925{
4926 struct drm_i915_private *dev_priv = data;
4927 struct drm_device *dev = &dev_priv->drm;
4928 int ret;
4929
4930 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4931
4932 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4933 * on ioctls on -EAGAIN. */
4934 ret = mutex_lock_interruptible(&dev->struct_mutex);
4935 if (ret)
4936 return ret;
4937
4938 if (val & DROP_ACTIVE) {
4939 ret = i915_gem_wait_for_idle(dev_priv,
4940 I915_WAIT_INTERRUPTIBLE |
4941 I915_WAIT_LOCKED);
4942 if (ret)
4943 goto unlock;
4944 }
4945
4946 if (val & (DROP_RETIRE | DROP_ACTIVE))
4947 i915_gem_retire_requests(dev_priv);
4948
4949 if (val & DROP_BOUND)
4950 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4951
4952 if (val & DROP_UNBOUND)
4953 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4954
4955unlock:
4956 mutex_unlock(&dev->struct_mutex);
4957
4958 if (val & DROP_FREED) {
4959 synchronize_rcu();
4960 flush_work(&dev_priv->mm.free_work);
4961 }
4962
4963 return ret;
4964}
4965
4966DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4967 i915_drop_caches_get, i915_drop_caches_set,
4968 "0x%08llx\n");
4969
4970static int
4971i915_max_freq_get(void *data, u64 *val)
4972{
4973 struct drm_i915_private *dev_priv = data;
4974
4975 if (INTEL_GEN(dev_priv) < 6)
4976 return -ENODEV;
4977
4978 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4979 return 0;
4980}
4981
4982static int
4983i915_max_freq_set(void *data, u64 val)
4984{
4985 struct drm_i915_private *dev_priv = data;
4986 u32 hw_max, hw_min;
4987 int ret;
4988
4989 if (INTEL_GEN(dev_priv) < 6)
4990 return -ENODEV;
4991
4992 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4993
4994 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4995 if (ret)
4996 return ret;
4997
4998 /*
4999 * Turbo will still be enabled, but won't go above the set value.
5000 */
5001 val = intel_freq_opcode(dev_priv, val);
5002
5003 hw_max = dev_priv->rps.max_freq;
5004 hw_min = dev_priv->rps.min_freq;
5005
5006 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
5007 mutex_unlock(&dev_priv->rps.hw_lock);
5008 return -EINVAL;
5009 }
5010
5011 dev_priv->rps.max_freq_softlimit = val;
5012
5013 intel_set_rps(dev_priv, val);
5014
5015 mutex_unlock(&dev_priv->rps.hw_lock);
5016
5017 return 0;
5018}
5019
5020DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
5021 i915_max_freq_get, i915_max_freq_set,
5022 "%llu\n");
5023
5024static int
5025i915_min_freq_get(void *data, u64 *val)
5026{
5027 struct drm_i915_private *dev_priv = data;
5028
5029 if (INTEL_GEN(dev_priv) < 6)
5030 return -ENODEV;
5031
5032 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
5033 return 0;
5034}
5035
5036static int
5037i915_min_freq_set(void *data, u64 val)
5038{
5039 struct drm_i915_private *dev_priv = data;
5040 u32 hw_max, hw_min;
5041 int ret;
5042
5043 if (INTEL_GEN(dev_priv) < 6)
5044 return -ENODEV;
5045
5046 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5047
5048 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5049 if (ret)
5050 return ret;
5051
5052 /*
5053 * Turbo will still be enabled, but won't go below the set value.
5054 */
5055 val = intel_freq_opcode(dev_priv, val);
5056
5057 hw_max = dev_priv->rps.max_freq;
5058 hw_min = dev_priv->rps.min_freq;
5059
5060 if (val < hw_min ||
5061 val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5062 mutex_unlock(&dev_priv->rps.hw_lock);
5063 return -EINVAL;
5064 }
5065
5066 dev_priv->rps.min_freq_softlimit = val;
5067
5068 intel_set_rps(dev_priv, val);
5069
5070 mutex_unlock(&dev_priv->rps.hw_lock);
5071
5072 return 0;
5073}
5074
5075DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5076 i915_min_freq_get, i915_min_freq_set,
5077 "%llu\n");
5078
5079static int
5080i915_cache_sharing_get(void *data, u64 *val)
5081{
5082 struct drm_i915_private *dev_priv = data;
5083 u32 snpcr;
5084
5085 if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
5086 return -ENODEV;
5087
5088 intel_runtime_pm_get(dev_priv);
5089
5090 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5091
5092 intel_runtime_pm_put(dev_priv);
5093
5094 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5095
5096 return 0;
5097}
5098
5099static int
5100i915_cache_sharing_set(void *data, u64 val)
5101{
5102 struct drm_i915_private *dev_priv = data;
5103 u32 snpcr;
5104
5105 if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
5106 return -ENODEV;
5107
5108 if (val > 3)
5109 return -EINVAL;
5110
5111 intel_runtime_pm_get(dev_priv);
5112 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5113
5114 /* Update the cache sharing policy here as well */
5115 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5116 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5117 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5118 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5119
5120 intel_runtime_pm_put(dev_priv);
5121 return 0;
5122}
5123
5124DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5125 i915_cache_sharing_get, i915_cache_sharing_set,
5126 "%llu\n");
5127
5128static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
5129 struct sseu_dev_info *sseu)
5130{
5131 int ss_max = 2;
5132 int ss;
5133 u32 sig1[ss_max], sig2[ss_max];
5134
5135 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5136 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5137 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5138 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5139
5140 for (ss = 0; ss < ss_max; ss++) {
5141 unsigned int eu_cnt;
5142
5143 if (sig1[ss] & CHV_SS_PG_ENABLE)
5144 /* skip disabled subslice */
5145 continue;
5146
5147 sseu->slice_mask = BIT(0);
5148 sseu->subslice_mask |= BIT(ss);
5149 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5150 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5151 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5152 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5153 sseu->eu_total += eu_cnt;
5154 sseu->eu_per_subslice = max_t(unsigned int,
5155 sseu->eu_per_subslice, eu_cnt);
5156 }
5157}
5158
5159static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
5160 struct sseu_dev_info *sseu)
5161{
5162 int s_max = 3, ss_max = 4;
5163 int s, ss;
5164 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5165
5166 /* BXT has a single slice and at most 3 subslices. */
5167 if (IS_BROXTON(dev_priv)) {
5168 s_max = 1;
5169 ss_max = 3;
5170 }
5171
5172 for (s = 0; s < s_max; s++) {
5173 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5174 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5175 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5176 }
5177
5178 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5179 GEN9_PGCTL_SSA_EU19_ACK |
5180 GEN9_PGCTL_SSA_EU210_ACK |
5181 GEN9_PGCTL_SSA_EU311_ACK;
5182 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5183 GEN9_PGCTL_SSB_EU19_ACK |
5184 GEN9_PGCTL_SSB_EU210_ACK |
5185 GEN9_PGCTL_SSB_EU311_ACK;
5186
5187 for (s = 0; s < s_max; s++) {
5188 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5189 /* skip disabled slice */
5190 continue;
5191
5192 sseu->slice_mask |= BIT(s);
5193
5194 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
5195 sseu->subslice_mask =
5196 INTEL_INFO(dev_priv)->sseu.subslice_mask;
5197
5198 for (ss = 0; ss < ss_max; ss++) {
5199 unsigned int eu_cnt;
5200
5201 if (IS_BROXTON(dev_priv)) {
5202 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5203 /* skip disabled subslice */
5204 continue;
5205
5206 sseu->subslice_mask |= BIT(ss);
5207 }
5208
5209 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5210 eu_mask[ss%2]);
5211 sseu->eu_total += eu_cnt;
5212 sseu->eu_per_subslice = max_t(unsigned int,
5213 sseu->eu_per_subslice,
5214 eu_cnt);
5215 }
5216 }
5217}
5218
5219static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
5220 struct sseu_dev_info *sseu)
5221{
5222 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5223 int s;
5224
5225 sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
5226
5227 if (sseu->slice_mask) {
5228 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
5229 sseu->eu_per_subslice =
5230 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
5231 sseu->eu_total = sseu->eu_per_subslice *
5232 sseu_subslice_total(sseu);
5233
5234 /* subtract fused off EU(s) from enabled slice(s) */
5235 for (s = 0; s < fls(sseu->slice_mask); s++) {
5236 u8 subslice_7eu =
5237 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
5238
5239 sseu->eu_total -= hweight8(subslice_7eu);
5240 }
5241 }
5242}
5243
5244static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
5245 const struct sseu_dev_info *sseu)
5246{
5247 struct drm_i915_private *dev_priv = node_to_i915(m->private);
5248 const char *type = is_available_info ? "Available" : "Enabled";
5249
5250 seq_printf(m, " %s Slice Mask: %04x\n", type,
5251 sseu->slice_mask);
5252 seq_printf(m, " %s Slice Total: %u\n", type,
5253 hweight8(sseu->slice_mask));
5254 seq_printf(m, " %s Subslice Total: %u\n", type,
5255 sseu_subslice_total(sseu));
5256 seq_printf(m, " %s Subslice Mask: %04x\n", type,
5257 sseu->subslice_mask);
5258 seq_printf(m, " %s Subslice Per Slice: %u\n", type,
5259 hweight8(sseu->subslice_mask));
5260 seq_printf(m, " %s EU Total: %u\n", type,
5261 sseu->eu_total);
5262 seq_printf(m, " %s EU Per Subslice: %u\n", type,
5263 sseu->eu_per_subslice);
5264
5265 if (!is_available_info)
5266 return;
5267
5268 seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
5269 if (HAS_POOLED_EU(dev_priv))
5270 seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool);
5271
5272 seq_printf(m, " Has Slice Power Gating: %s\n",
5273 yesno(sseu->has_slice_pg));
5274 seq_printf(m, " Has Subslice Power Gating: %s\n",
5275 yesno(sseu->has_subslice_pg));
5276 seq_printf(m, " Has EU Power Gating: %s\n",
5277 yesno(sseu->has_eu_pg));
5278}
5279
5280static int i915_sseu_status(struct seq_file *m, void *unused)
5281{
5282 struct drm_i915_private *dev_priv = node_to_i915(m->private);
5283 struct sseu_dev_info sseu;
5284
5285 if (INTEL_GEN(dev_priv) < 8)
5286 return -ENODEV;
5287
5288 seq_puts(m, "SSEU Device Info\n");
5289 i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
5290
5291 seq_puts(m, "SSEU Device Status\n");
5292 memset(&sseu, 0, sizeof(sseu));
5293
5294 intel_runtime_pm_get(dev_priv);
5295
5296 if (IS_CHERRYVIEW(dev_priv)) {
5297 cherryview_sseu_device_status(dev_priv, &sseu);
5298 } else if (IS_BROADWELL(dev_priv)) {
5299 broadwell_sseu_device_status(dev_priv, &sseu);
5300 } else if (INTEL_GEN(dev_priv) >= 9) {
5301 gen9_sseu_device_status(dev_priv, &sseu);
5302 }
5303
5304 intel_runtime_pm_put(dev_priv);
5305
5306 i915_print_sseu_info(m, false, &sseu);
5307
5308 return 0;
5309}
5310
5311static int i915_forcewake_open(struct inode *inode, struct file *file)
5312{
5313 struct drm_i915_private *dev_priv = inode->i_private;
5314
5315 if (INTEL_GEN(dev_priv) < 6)
5316 return 0;
5317
5318 intel_runtime_pm_get(dev_priv);
5319 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5320
5321 return 0;
5322}
5323
5324static int i915_forcewake_release(struct inode *inode, struct file *file)
5325{
5326 struct drm_i915_private *dev_priv = inode->i_private;
5327
5328 if (INTEL_GEN(dev_priv) < 6)
5329 return 0;
5330
5331 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5332 intel_runtime_pm_put(dev_priv);
5333
5334 return 0;
5335}
5336
5337static const struct file_operations i915_forcewake_fops = {
5338 .owner = THIS_MODULE,
5339 .open = i915_forcewake_open,
5340 .release = i915_forcewake_release,
5341};
5342
5343static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5344{
5345 struct dentry *ent;
5346
5347 ent = debugfs_create_file("i915_forcewake_user",
5348 S_IRUSR,
5349 root, to_i915(minor->dev),
5350 &i915_forcewake_fops);
5351 if (!ent)
5352 return -ENOMEM;
5353
5354 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5355}
5356
5357static int i915_debugfs_create(struct dentry *root,
5358 struct drm_minor *minor,
5359 const char *name,
5360 const struct file_operations *fops)
5361{
5362 struct dentry *ent;
5363
5364 ent = debugfs_create_file(name,
5365 S_IRUGO | S_IWUSR,
5366 root, to_i915(minor->dev),
5367 fops);
5368 if (!ent)
5369 return -ENOMEM;
5370
5371 return drm_add_fake_info_node(minor, ent, fops);
5372}
5373
5374static const struct drm_info_list i915_debugfs_list[] = {
5375 {"i915_capabilities", i915_capabilities, 0},
5376 {"i915_gem_objects", i915_gem_object_info, 0},
5377 {"i915_gem_gtt", i915_gem_gtt_info, 0},
5378 {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1},
5379 {"i915_gem_stolen", i915_gem_stolen_list_info },
5380 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5381 {"i915_gem_request", i915_gem_request_info, 0},
5382 {"i915_gem_seqno", i915_gem_seqno_info, 0},
5383 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5384 {"i915_gem_interrupt", i915_interrupt_info, 0},
5385 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5386 {"i915_guc_info", i915_guc_info, 0},
5387 {"i915_guc_load_status", i915_guc_load_status_info, 0},
5388 {"i915_guc_log_dump", i915_guc_log_dump, 0},
5389 {"i915_frequency_info", i915_frequency_info, 0},
5390 {"i915_hangcheck_info", i915_hangcheck_info, 0},
5391 {"i915_drpc_info", i915_drpc_info, 0},
5392 {"i915_emon_status", i915_emon_status, 0},
5393 {"i915_ring_freq_table", i915_ring_freq_table, 0},
5394 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5395 {"i915_fbc_status", i915_fbc_status, 0},
5396 {"i915_ips_status", i915_ips_status, 0},
5397 {"i915_sr_status", i915_sr_status, 0},
5398 {"i915_opregion", i915_opregion, 0},
5399 {"i915_vbt", i915_vbt, 0},
5400 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5401 {"i915_context_status", i915_context_status, 0},
5402 {"i915_dump_lrc", i915_dump_lrc, 0},
5403 {"i915_forcewake_domains", i915_forcewake_domains, 0},
5404 {"i915_swizzle_info", i915_swizzle_info, 0},
5405 {"i915_ppgtt_info", i915_ppgtt_info, 0},
5406 {"i915_llc", i915_llc, 0},
5407 {"i915_edp_psr_status", i915_edp_psr_status, 0},
5408 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5409 {"i915_energy_uJ", i915_energy_uJ, 0},
5410 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5411 {"i915_power_domain_info", i915_power_domain_info, 0},
5412 {"i915_dmc_info", i915_dmc_info, 0},
5413 {"i915_display_info", i915_display_info, 0},
5414 {"i915_engine_info", i915_engine_info, 0},
5415 {"i915_semaphore_status", i915_semaphore_status, 0},
5416 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5417 {"i915_dp_mst_info", i915_dp_mst_info, 0},
5418 {"i915_wa_registers", i915_wa_registers, 0},
5419 {"i915_ddb_info", i915_ddb_info, 0},
5420 {"i915_sseu_status", i915_sseu_status, 0},
5421 {"i915_drrs_status", i915_drrs_status, 0},
5422 {"i915_rps_boost_info", i915_rps_boost_info, 0},
5423};
5424#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5425
5426static const struct i915_debugfs_files {
5427 const char *name;
5428 const struct file_operations *fops;
5429} i915_debugfs_files[] = {
5430 {"i915_wedged", &i915_wedged_fops},
5431 {"i915_max_freq", &i915_max_freq_fops},
5432 {"i915_min_freq", &i915_min_freq_fops},
5433 {"i915_cache_sharing", &i915_cache_sharing_fops},
5434 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5435 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5436 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5437#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
5438 {"i915_error_state", &i915_error_state_fops},
5439#endif
5440 {"i915_next_seqno", &i915_next_seqno_fops},
5441 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5442 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5443 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5444 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5445 {"i915_fbc_false_color", &i915_fbc_fc_fops},
5446 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5447 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5448 {"i915_dp_test_active", &i915_displayport_test_active_fops},
5449 {"i915_guc_log_control", &i915_guc_log_control_fops}
5450};
5451
5452void intel_display_crc_init(struct drm_i915_private *dev_priv)
5453{
5454 enum pipe pipe;
5455
5456 for_each_pipe(dev_priv, pipe) {
5457 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5458
5459 pipe_crc->opened = false;
5460 spin_lock_init(&pipe_crc->lock);
5461 init_waitqueue_head(&pipe_crc->wq);
5462 }
5463}
5464
5465int i915_debugfs_register(struct drm_i915_private *dev_priv)
5466{
5467 struct drm_minor *minor = dev_priv->drm.primary;
5468 int ret, i;
5469
5470 ret = i915_forcewake_create(minor->debugfs_root, minor);
5471 if (ret)
5472 return ret;
5473
5474 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5475 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5476 if (ret)
5477 return ret;
5478 }
5479
5480 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5481 ret = i915_debugfs_create(minor->debugfs_root, minor,
5482 i915_debugfs_files[i].name,
5483 i915_debugfs_files[i].fops);
5484 if (ret)
5485 return ret;
5486 }
5487
5488 return drm_debugfs_create_files(i915_debugfs_list,
5489 I915_DEBUGFS_ENTRIES,
5490 minor->debugfs_root, minor);
5491}
5492
5493void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
5494{
5495 struct drm_minor *minor = dev_priv->drm.primary;
5496 int i;
5497
5498 drm_debugfs_remove_files(i915_debugfs_list,
5499 I915_DEBUGFS_ENTRIES, minor);
5500
5501 drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops,
5502 1, minor);
5503
5504 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5505 struct drm_info_list *info_list =
5506 (struct drm_info_list *)&i915_pipe_crc_data[i];
5507
5508 drm_debugfs_remove_files(info_list, 1, minor);
5509 }
5510
5511 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5512 struct drm_info_list *info_list =
5513 (struct drm_info_list *)i915_debugfs_files[i].fops;
5514
5515 drm_debugfs_remove_files(info_list, 1, minor);
5516 }
5517}
5518
5519struct dpcd_block {
5520 /* DPCD dump start address. */
5521 unsigned int offset;
5522 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5523 unsigned int end;
5524 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5525 size_t size;
5526 /* Only valid for eDP. */
5527 bool edp;
5528};
5529
5530static const struct dpcd_block i915_dpcd_debug[] = {
5531 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5532 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5533 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5534 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5535 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5536 { .offset = DP_SET_POWER },
5537 { .offset = DP_EDP_DPCD_REV },
5538 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5539 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5540 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5541};
5542
5543static int i915_dpcd_show(struct seq_file *m, void *data)
5544{
5545 struct drm_connector *connector = m->private;
5546 struct intel_dp *intel_dp =
5547 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5548 uint8_t buf[16];
5549 ssize_t err;
5550 int i;
5551
5552 if (connector->status != connector_status_connected)
5553 return -ENODEV;
5554
5555 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5556 const struct dpcd_block *b = &i915_dpcd_debug[i];
5557 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5558
5559 if (b->edp &&
5560 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5561 continue;
5562
5563 /* low tech for now */
5564 if (WARN_ON(size > sizeof(buf)))
5565 continue;
5566
5567 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5568 if (err <= 0) {
5569 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5570 size, b->offset, err);
5571 continue;
5572 }
5573
5574 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5575 }
5576
5577 return 0;
5578}
5579
5580static int i915_dpcd_open(struct inode *inode, struct file *file)
5581{
5582 return single_open(file, i915_dpcd_show, inode->i_private);
5583}
5584
5585static const struct file_operations i915_dpcd_fops = {
5586 .owner = THIS_MODULE,
5587 .open = i915_dpcd_open,
5588 .read = seq_read,
5589 .llseek = seq_lseek,
5590 .release = single_release,
5591};
5592
5593static int i915_panel_show(struct seq_file *m, void *data)
5594{
5595 struct drm_connector *connector = m->private;
5596 struct intel_dp *intel_dp =
5597 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5598
5599 if (connector->status != connector_status_connected)
5600 return -ENODEV;
5601
5602 seq_printf(m, "Panel power up delay: %d\n",
5603 intel_dp->panel_power_up_delay);
5604 seq_printf(m, "Panel power down delay: %d\n",
5605 intel_dp->panel_power_down_delay);
5606 seq_printf(m, "Backlight on delay: %d\n",
5607 intel_dp->backlight_on_delay);
5608 seq_printf(m, "Backlight off delay: %d\n",
5609 intel_dp->backlight_off_delay);
5610
5611 return 0;
5612}
5613
5614static int i915_panel_open(struct inode *inode, struct file *file)
5615{
5616 return single_open(file, i915_panel_show, inode->i_private);
5617}
5618
5619static const struct file_operations i915_panel_fops = {
5620 .owner = THIS_MODULE,
5621 .open = i915_panel_open,
5622 .read = seq_read,
5623 .llseek = seq_lseek,
5624 .release = single_release,
5625};
5626
5627/**
5628 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5629 * @connector: pointer to a registered drm_connector
5630 *
5631 * Cleanup will be done by drm_connector_unregister() through a call to
5632 * drm_debugfs_connector_remove().
5633 *
5634 * Returns 0 on success, negative error codes on error.
5635 */
5636int i915_debugfs_connector_add(struct drm_connector *connector)
5637{
5638 struct dentry *root = connector->debugfs_entry;
5639
5640 /* The connector must have been registered beforehands. */
5641 if (!root)
5642 return -ENODEV;
5643
5644 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5645 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5646 debugfs_create_file("i915_dpcd", S_IRUGO, root,
5647 connector, &i915_dpcd_fops);
5648
5649 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5650 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
5651 connector, &i915_panel_fops);
5652
5653 return 0;
5654}
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