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1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- | |
2 | */ | |
3 | /* | |
4 | * | |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. | |
6 | * All Rights Reserved. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
28 | */ | |
29 | ||
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
33 | #include <uapi/drm/i915_drm.h> | |
34 | #include <uapi/drm/drm_fourcc.h> | |
35 | ||
36 | #include <linux/io-mapping.h> | |
37 | #include <linux/i2c.h> | |
38 | #include <linux/i2c-algo-bit.h> | |
39 | #include <linux/backlight.h> | |
40 | #include <linux/hashtable.h> | |
41 | #include <linux/intel-iommu.h> | |
42 | #include <linux/kref.h> | |
43 | #include <linux/pm_qos.h> | |
44 | #include <linux/shmem_fs.h> | |
45 | ||
46 | #include <drm/drmP.h> | |
47 | #include <drm/intel-gtt.h> | |
48 | #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ | |
49 | #include <drm/drm_gem.h> | |
50 | #include <drm/drm_auth.h> | |
51 | ||
52 | #include "i915_params.h" | |
53 | #include "i915_reg.h" | |
54 | ||
55 | #include "intel_bios.h" | |
56 | #include "intel_dpll_mgr.h" | |
57 | #include "intel_guc.h" | |
58 | #include "intel_lrc.h" | |
59 | #include "intel_ringbuffer.h" | |
60 | ||
61 | #include "i915_gem.h" | |
62 | #include "i915_gem_gtt.h" | |
63 | #include "i915_gem_render_state.h" | |
64 | #include "i915_gem_request.h" | |
65 | ||
66 | #include "intel_gvt.h" | |
67 | ||
68 | /* General customization: | |
69 | */ | |
70 | ||
71 | #define DRIVER_NAME "i915" | |
72 | #define DRIVER_DESC "Intel Graphics" | |
73 | #define DRIVER_DATE "20160725" | |
74 | ||
75 | #undef WARN_ON | |
76 | /* Many gcc seem to no see through this and fall over :( */ | |
77 | #if 0 | |
78 | #define WARN_ON(x) ({ \ | |
79 | bool __i915_warn_cond = (x); \ | |
80 | if (__builtin_constant_p(__i915_warn_cond)) \ | |
81 | BUILD_BUG_ON(__i915_warn_cond); \ | |
82 | WARN(__i915_warn_cond, "WARN_ON(" #x ")"); }) | |
83 | #else | |
84 | #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")") | |
85 | #endif | |
86 | ||
87 | #undef WARN_ON_ONCE | |
88 | #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")") | |
89 | ||
90 | #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \ | |
91 | (long) (x), __func__); | |
92 | ||
93 | /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and | |
94 | * WARN_ON()) for hw state sanity checks to check for unexpected conditions | |
95 | * which may not necessarily be a user visible problem. This will either | |
96 | * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to | |
97 | * enable distros and users to tailor their preferred amount of i915 abrt | |
98 | * spam. | |
99 | */ | |
100 | #define I915_STATE_WARN(condition, format...) ({ \ | |
101 | int __ret_warn_on = !!(condition); \ | |
102 | if (unlikely(__ret_warn_on)) \ | |
103 | if (!WARN(i915.verbose_state_checks, format)) \ | |
104 | DRM_ERROR(format); \ | |
105 | unlikely(__ret_warn_on); \ | |
106 | }) | |
107 | ||
108 | #define I915_STATE_WARN_ON(x) \ | |
109 | I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") | |
110 | ||
111 | bool __i915_inject_load_failure(const char *func, int line); | |
112 | #define i915_inject_load_failure() \ | |
113 | __i915_inject_load_failure(__func__, __LINE__) | |
114 | ||
115 | static inline const char *yesno(bool v) | |
116 | { | |
117 | return v ? "yes" : "no"; | |
118 | } | |
119 | ||
120 | static inline const char *onoff(bool v) | |
121 | { | |
122 | return v ? "on" : "off"; | |
123 | } | |
124 | ||
125 | enum pipe { | |
126 | INVALID_PIPE = -1, | |
127 | PIPE_A = 0, | |
128 | PIPE_B, | |
129 | PIPE_C, | |
130 | _PIPE_EDP, | |
131 | I915_MAX_PIPES = _PIPE_EDP | |
132 | }; | |
133 | #define pipe_name(p) ((p) + 'A') | |
134 | ||
135 | enum transcoder { | |
136 | TRANSCODER_A = 0, | |
137 | TRANSCODER_B, | |
138 | TRANSCODER_C, | |
139 | TRANSCODER_EDP, | |
140 | TRANSCODER_DSI_A, | |
141 | TRANSCODER_DSI_C, | |
142 | I915_MAX_TRANSCODERS | |
143 | }; | |
144 | ||
145 | static inline const char *transcoder_name(enum transcoder transcoder) | |
146 | { | |
147 | switch (transcoder) { | |
148 | case TRANSCODER_A: | |
149 | return "A"; | |
150 | case TRANSCODER_B: | |
151 | return "B"; | |
152 | case TRANSCODER_C: | |
153 | return "C"; | |
154 | case TRANSCODER_EDP: | |
155 | return "EDP"; | |
156 | case TRANSCODER_DSI_A: | |
157 | return "DSI A"; | |
158 | case TRANSCODER_DSI_C: | |
159 | return "DSI C"; | |
160 | default: | |
161 | return "<invalid>"; | |
162 | } | |
163 | } | |
164 | ||
165 | static inline bool transcoder_is_dsi(enum transcoder transcoder) | |
166 | { | |
167 | return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; | |
168 | } | |
169 | ||
170 | /* | |
171 | * I915_MAX_PLANES in the enum below is the maximum (across all platforms) | |
172 | * number of planes per CRTC. Not all platforms really have this many planes, | |
173 | * which means some arrays of size I915_MAX_PLANES may have unused entries | |
174 | * between the topmost sprite plane and the cursor plane. | |
175 | */ | |
176 | enum plane { | |
177 | PLANE_A = 0, | |
178 | PLANE_B, | |
179 | PLANE_C, | |
180 | PLANE_CURSOR, | |
181 | I915_MAX_PLANES, | |
182 | }; | |
183 | #define plane_name(p) ((p) + 'A') | |
184 | ||
185 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') | |
186 | ||
187 | enum port { | |
188 | PORT_A = 0, | |
189 | PORT_B, | |
190 | PORT_C, | |
191 | PORT_D, | |
192 | PORT_E, | |
193 | I915_MAX_PORTS | |
194 | }; | |
195 | #define port_name(p) ((p) + 'A') | |
196 | ||
197 | #define I915_NUM_PHYS_VLV 2 | |
198 | ||
199 | enum dpio_channel { | |
200 | DPIO_CH0, | |
201 | DPIO_CH1 | |
202 | }; | |
203 | ||
204 | enum dpio_phy { | |
205 | DPIO_PHY0, | |
206 | DPIO_PHY1 | |
207 | }; | |
208 | ||
209 | enum intel_display_power_domain { | |
210 | POWER_DOMAIN_PIPE_A, | |
211 | POWER_DOMAIN_PIPE_B, | |
212 | POWER_DOMAIN_PIPE_C, | |
213 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
214 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
215 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
216 | POWER_DOMAIN_TRANSCODER_A, | |
217 | POWER_DOMAIN_TRANSCODER_B, | |
218 | POWER_DOMAIN_TRANSCODER_C, | |
219 | POWER_DOMAIN_TRANSCODER_EDP, | |
220 | POWER_DOMAIN_TRANSCODER_DSI_A, | |
221 | POWER_DOMAIN_TRANSCODER_DSI_C, | |
222 | POWER_DOMAIN_PORT_DDI_A_LANES, | |
223 | POWER_DOMAIN_PORT_DDI_B_LANES, | |
224 | POWER_DOMAIN_PORT_DDI_C_LANES, | |
225 | POWER_DOMAIN_PORT_DDI_D_LANES, | |
226 | POWER_DOMAIN_PORT_DDI_E_LANES, | |
227 | POWER_DOMAIN_PORT_DSI, | |
228 | POWER_DOMAIN_PORT_CRT, | |
229 | POWER_DOMAIN_PORT_OTHER, | |
230 | POWER_DOMAIN_VGA, | |
231 | POWER_DOMAIN_AUDIO, | |
232 | POWER_DOMAIN_PLLS, | |
233 | POWER_DOMAIN_AUX_A, | |
234 | POWER_DOMAIN_AUX_B, | |
235 | POWER_DOMAIN_AUX_C, | |
236 | POWER_DOMAIN_AUX_D, | |
237 | POWER_DOMAIN_GMBUS, | |
238 | POWER_DOMAIN_MODESET, | |
239 | POWER_DOMAIN_INIT, | |
240 | ||
241 | POWER_DOMAIN_NUM, | |
242 | }; | |
243 | ||
244 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) | |
245 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
246 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
247 | #define POWER_DOMAIN_TRANSCODER(tran) \ | |
248 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ | |
249 | (tran) + POWER_DOMAIN_TRANSCODER_A) | |
250 | ||
251 | enum hpd_pin { | |
252 | HPD_NONE = 0, | |
253 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ | |
254 | HPD_CRT, | |
255 | HPD_SDVO_B, | |
256 | HPD_SDVO_C, | |
257 | HPD_PORT_A, | |
258 | HPD_PORT_B, | |
259 | HPD_PORT_C, | |
260 | HPD_PORT_D, | |
261 | HPD_PORT_E, | |
262 | HPD_NUM_PINS | |
263 | }; | |
264 | ||
265 | #define for_each_hpd_pin(__pin) \ | |
266 | for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) | |
267 | ||
268 | struct i915_hotplug { | |
269 | struct work_struct hotplug_work; | |
270 | ||
271 | struct { | |
272 | unsigned long last_jiffies; | |
273 | int count; | |
274 | enum { | |
275 | HPD_ENABLED = 0, | |
276 | HPD_DISABLED = 1, | |
277 | HPD_MARK_DISABLED = 2 | |
278 | } state; | |
279 | } stats[HPD_NUM_PINS]; | |
280 | u32 event_bits; | |
281 | struct delayed_work reenable_work; | |
282 | ||
283 | struct intel_digital_port *irq_port[I915_MAX_PORTS]; | |
284 | u32 long_port_mask; | |
285 | u32 short_port_mask; | |
286 | struct work_struct dig_port_work; | |
287 | ||
288 | struct work_struct poll_init_work; | |
289 | bool poll_enabled; | |
290 | ||
291 | /* | |
292 | * if we get a HPD irq from DP and a HPD irq from non-DP | |
293 | * the non-DP HPD could block the workqueue on a mode config | |
294 | * mutex getting, that userspace may have taken. However | |
295 | * userspace is waiting on the DP workqueue to run which is | |
296 | * blocked behind the non-DP one. | |
297 | */ | |
298 | struct workqueue_struct *dp_wq; | |
299 | }; | |
300 | ||
301 | #define I915_GEM_GPU_DOMAINS \ | |
302 | (I915_GEM_DOMAIN_RENDER | \ | |
303 | I915_GEM_DOMAIN_SAMPLER | \ | |
304 | I915_GEM_DOMAIN_COMMAND | \ | |
305 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
306 | I915_GEM_DOMAIN_VERTEX) | |
307 | ||
308 | #define for_each_pipe(__dev_priv, __p) \ | |
309 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) | |
310 | #define for_each_pipe_masked(__dev_priv, __p, __mask) \ | |
311 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \ | |
312 | for_each_if ((__mask) & (1 << (__p))) | |
313 | #define for_each_plane(__dev_priv, __pipe, __p) \ | |
314 | for ((__p) = 0; \ | |
315 | (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ | |
316 | (__p)++) | |
317 | #define for_each_sprite(__dev_priv, __p, __s) \ | |
318 | for ((__s) = 0; \ | |
319 | (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \ | |
320 | (__s)++) | |
321 | ||
322 | #define for_each_port_masked(__port, __ports_mask) \ | |
323 | for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ | |
324 | for_each_if ((__ports_mask) & (1 << (__port))) | |
325 | ||
326 | #define for_each_crtc(dev, crtc) \ | |
327 | list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) | |
328 | ||
329 | #define for_each_intel_plane(dev, intel_plane) \ | |
330 | list_for_each_entry(intel_plane, \ | |
331 | &(dev)->mode_config.plane_list, \ | |
332 | base.head) | |
333 | ||
334 | #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ | |
335 | list_for_each_entry(intel_plane, \ | |
336 | &(dev)->mode_config.plane_list, \ | |
337 | base.head) \ | |
338 | for_each_if ((plane_mask) & \ | |
339 | (1 << drm_plane_index(&intel_plane->base))) | |
340 | ||
341 | #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ | |
342 | list_for_each_entry(intel_plane, \ | |
343 | &(dev)->mode_config.plane_list, \ | |
344 | base.head) \ | |
345 | for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe) | |
346 | ||
347 | #define for_each_intel_crtc(dev, intel_crtc) \ | |
348 | list_for_each_entry(intel_crtc, \ | |
349 | &(dev)->mode_config.crtc_list, \ | |
350 | base.head) | |
351 | ||
352 | #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \ | |
353 | list_for_each_entry(intel_crtc, \ | |
354 | &(dev)->mode_config.crtc_list, \ | |
355 | base.head) \ | |
356 | for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base))) | |
357 | ||
358 | #define for_each_intel_encoder(dev, intel_encoder) \ | |
359 | list_for_each_entry(intel_encoder, \ | |
360 | &(dev)->mode_config.encoder_list, \ | |
361 | base.head) | |
362 | ||
363 | #define for_each_intel_connector(dev, intel_connector) \ | |
364 | list_for_each_entry(intel_connector, \ | |
365 | &(dev)->mode_config.connector_list, \ | |
366 | base.head) | |
367 | ||
368 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ | |
369 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
370 | for_each_if ((intel_encoder)->base.crtc == (__crtc)) | |
371 | ||
372 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ | |
373 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ | |
374 | for_each_if ((intel_connector)->base.encoder == (__encoder)) | |
375 | ||
376 | #define for_each_power_domain(domain, mask) \ | |
377 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
378 | for_each_if ((1 << (domain)) & (mask)) | |
379 | ||
380 | struct drm_i915_private; | |
381 | struct i915_mm_struct; | |
382 | struct i915_mmu_object; | |
383 | ||
384 | struct drm_i915_file_private { | |
385 | struct drm_i915_private *dev_priv; | |
386 | struct drm_file *file; | |
387 | ||
388 | struct { | |
389 | spinlock_t lock; | |
390 | struct list_head request_list; | |
391 | /* 20ms is a fairly arbitrary limit (greater than the average frame time) | |
392 | * chosen to prevent the CPU getting more than a frame ahead of the GPU | |
393 | * (when using lax throttling for the frontbuffer). We also use it to | |
394 | * offer free GPU waitboosts for severely congested workloads. | |
395 | */ | |
396 | #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20) | |
397 | } mm; | |
398 | struct idr context_idr; | |
399 | ||
400 | struct intel_rps_client { | |
401 | struct list_head link; | |
402 | unsigned boosts; | |
403 | } rps; | |
404 | ||
405 | unsigned int bsd_engine; | |
406 | }; | |
407 | ||
408 | /* Used by dp and fdi links */ | |
409 | struct intel_link_m_n { | |
410 | uint32_t tu; | |
411 | uint32_t gmch_m; | |
412 | uint32_t gmch_n; | |
413 | uint32_t link_m; | |
414 | uint32_t link_n; | |
415 | }; | |
416 | ||
417 | void intel_link_compute_m_n(int bpp, int nlanes, | |
418 | int pixel_clock, int link_clock, | |
419 | struct intel_link_m_n *m_n); | |
420 | ||
421 | /* Interface history: | |
422 | * | |
423 | * 1.1: Original. | |
424 | * 1.2: Add Power Management | |
425 | * 1.3: Add vblank support | |
426 | * 1.4: Fix cmdbuffer path, add heap destroy | |
427 | * 1.5: Add vblank pipe configuration | |
428 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank | |
429 | * - Support vertical blank on secondary display pipe | |
430 | */ | |
431 | #define DRIVER_MAJOR 1 | |
432 | #define DRIVER_MINOR 6 | |
433 | #define DRIVER_PATCHLEVEL 0 | |
434 | ||
435 | #define WATCH_LISTS 0 | |
436 | ||
437 | struct opregion_header; | |
438 | struct opregion_acpi; | |
439 | struct opregion_swsci; | |
440 | struct opregion_asle; | |
441 | ||
442 | struct intel_opregion { | |
443 | struct opregion_header *header; | |
444 | struct opregion_acpi *acpi; | |
445 | struct opregion_swsci *swsci; | |
446 | u32 swsci_gbda_sub_functions; | |
447 | u32 swsci_sbcb_sub_functions; | |
448 | struct opregion_asle *asle; | |
449 | void *rvda; | |
450 | const void *vbt; | |
451 | u32 vbt_size; | |
452 | u32 *lid_state; | |
453 | struct work_struct asle_work; | |
454 | }; | |
455 | #define OPREGION_SIZE (8*1024) | |
456 | ||
457 | struct intel_overlay; | |
458 | struct intel_overlay_error_state; | |
459 | ||
460 | #define I915_FENCE_REG_NONE -1 | |
461 | #define I915_MAX_NUM_FENCES 32 | |
462 | /* 32 fences + sign bit for FENCE_REG_NONE */ | |
463 | #define I915_MAX_NUM_FENCE_BITS 6 | |
464 | ||
465 | struct drm_i915_fence_reg { | |
466 | struct list_head lru_list; | |
467 | struct drm_i915_gem_object *obj; | |
468 | int pin_count; | |
469 | }; | |
470 | ||
471 | struct sdvo_device_mapping { | |
472 | u8 initialized; | |
473 | u8 dvo_port; | |
474 | u8 slave_addr; | |
475 | u8 dvo_wiring; | |
476 | u8 i2c_pin; | |
477 | u8 ddc_pin; | |
478 | }; | |
479 | ||
480 | struct intel_display_error_state; | |
481 | ||
482 | struct drm_i915_error_state { | |
483 | struct kref ref; | |
484 | struct timeval time; | |
485 | ||
486 | char error_msg[128]; | |
487 | bool simulated; | |
488 | int iommu; | |
489 | u32 reset_count; | |
490 | u32 suspend_count; | |
491 | ||
492 | /* Generic register state */ | |
493 | u32 eir; | |
494 | u32 pgtbl_er; | |
495 | u32 ier; | |
496 | u32 gtier[4]; | |
497 | u32 ccid; | |
498 | u32 derrmr; | |
499 | u32 forcewake; | |
500 | u32 error; /* gen6+ */ | |
501 | u32 err_int; /* gen7 */ | |
502 | u32 fault_data0; /* gen8, gen9 */ | |
503 | u32 fault_data1; /* gen8, gen9 */ | |
504 | u32 done_reg; | |
505 | u32 gac_eco; | |
506 | u32 gam_ecochk; | |
507 | u32 gab_ctl; | |
508 | u32 gfx_mode; | |
509 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; | |
510 | u64 fence[I915_MAX_NUM_FENCES]; | |
511 | struct intel_overlay_error_state *overlay; | |
512 | struct intel_display_error_state *display; | |
513 | struct drm_i915_error_object *semaphore_obj; | |
514 | ||
515 | struct drm_i915_error_engine { | |
516 | int engine_id; | |
517 | /* Software tracked state */ | |
518 | bool waiting; | |
519 | int num_waiters; | |
520 | int hangcheck_score; | |
521 | enum intel_engine_hangcheck_action hangcheck_action; | |
522 | int num_requests; | |
523 | ||
524 | /* our own tracking of ring head and tail */ | |
525 | u32 cpu_ring_head; | |
526 | u32 cpu_ring_tail; | |
527 | ||
528 | u32 last_seqno; | |
529 | u32 semaphore_seqno[I915_NUM_ENGINES - 1]; | |
530 | ||
531 | /* Register state */ | |
532 | u32 start; | |
533 | u32 tail; | |
534 | u32 head; | |
535 | u32 ctl; | |
536 | u32 hws; | |
537 | u32 ipeir; | |
538 | u32 ipehr; | |
539 | u32 instdone; | |
540 | u32 bbstate; | |
541 | u32 instpm; | |
542 | u32 instps; | |
543 | u32 seqno; | |
544 | u64 bbaddr; | |
545 | u64 acthd; | |
546 | u32 fault_reg; | |
547 | u64 faddr; | |
548 | u32 rc_psmi; /* sleep state */ | |
549 | u32 semaphore_mboxes[I915_NUM_ENGINES - 1]; | |
550 | ||
551 | struct drm_i915_error_object { | |
552 | int page_count; | |
553 | u64 gtt_offset; | |
554 | u32 *pages[0]; | |
555 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; | |
556 | ||
557 | struct drm_i915_error_object *wa_ctx; | |
558 | ||
559 | struct drm_i915_error_request { | |
560 | long jiffies; | |
561 | u32 seqno; | |
562 | u32 tail; | |
563 | } *requests; | |
564 | ||
565 | struct drm_i915_error_waiter { | |
566 | char comm[TASK_COMM_LEN]; | |
567 | pid_t pid; | |
568 | u32 seqno; | |
569 | } *waiters; | |
570 | ||
571 | struct { | |
572 | u32 gfx_mode; | |
573 | union { | |
574 | u64 pdp[4]; | |
575 | u32 pp_dir_base; | |
576 | }; | |
577 | } vm_info; | |
578 | ||
579 | pid_t pid; | |
580 | char comm[TASK_COMM_LEN]; | |
581 | } engine[I915_NUM_ENGINES]; | |
582 | ||
583 | struct drm_i915_error_buffer { | |
584 | u32 size; | |
585 | u32 name; | |
586 | u32 rseqno[I915_NUM_ENGINES], wseqno; | |
587 | u64 gtt_offset; | |
588 | u32 read_domains; | |
589 | u32 write_domain; | |
590 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; | |
591 | s32 pinned:2; | |
592 | u32 tiling:2; | |
593 | u32 dirty:1; | |
594 | u32 purgeable:1; | |
595 | u32 userptr:1; | |
596 | s32 engine:4; | |
597 | u32 cache_level:3; | |
598 | } **active_bo, **pinned_bo; | |
599 | ||
600 | u32 *active_bo_count, *pinned_bo_count; | |
601 | u32 vm_count; | |
602 | }; | |
603 | ||
604 | struct intel_connector; | |
605 | struct intel_encoder; | |
606 | struct intel_crtc_state; | |
607 | struct intel_initial_plane_config; | |
608 | struct intel_crtc; | |
609 | struct intel_limit; | |
610 | struct dpll; | |
611 | ||
612 | struct drm_i915_display_funcs { | |
613 | int (*get_display_clock_speed)(struct drm_device *dev); | |
614 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
615 | int (*compute_pipe_wm)(struct intel_crtc_state *cstate); | |
616 | int (*compute_intermediate_wm)(struct drm_device *dev, | |
617 | struct intel_crtc *intel_crtc, | |
618 | struct intel_crtc_state *newstate); | |
619 | void (*initial_watermarks)(struct intel_crtc_state *cstate); | |
620 | void (*optimize_watermarks)(struct intel_crtc_state *cstate); | |
621 | int (*compute_global_watermarks)(struct drm_atomic_state *state); | |
622 | void (*update_wm)(struct drm_crtc *crtc); | |
623 | int (*modeset_calc_cdclk)(struct drm_atomic_state *state); | |
624 | void (*modeset_commit_cdclk)(struct drm_atomic_state *state); | |
625 | /* Returns the active state of the crtc, and if the crtc is active, | |
626 | * fills out the pipe-config with the hw state. */ | |
627 | bool (*get_pipe_config)(struct intel_crtc *, | |
628 | struct intel_crtc_state *); | |
629 | void (*get_initial_plane_config)(struct intel_crtc *, | |
630 | struct intel_initial_plane_config *); | |
631 | int (*crtc_compute_clock)(struct intel_crtc *crtc, | |
632 | struct intel_crtc_state *crtc_state); | |
633 | void (*crtc_enable)(struct drm_crtc *crtc); | |
634 | void (*crtc_disable)(struct drm_crtc *crtc); | |
635 | void (*audio_codec_enable)(struct drm_connector *connector, | |
636 | struct intel_encoder *encoder, | |
637 | const struct drm_display_mode *adjusted_mode); | |
638 | void (*audio_codec_disable)(struct intel_encoder *encoder); | |
639 | void (*fdi_link_train)(struct drm_crtc *crtc); | |
640 | void (*init_clock_gating)(struct drm_device *dev); | |
641 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, | |
642 | struct drm_framebuffer *fb, | |
643 | struct drm_i915_gem_object *obj, | |
644 | struct drm_i915_gem_request *req, | |
645 | uint32_t flags); | |
646 | void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); | |
647 | /* clock updates for mode set */ | |
648 | /* cursor updates */ | |
649 | /* render clock increase/decrease */ | |
650 | /* display clock increase/decrease */ | |
651 | /* pll clock increase/decrease */ | |
652 | ||
653 | void (*load_csc_matrix)(struct drm_crtc_state *crtc_state); | |
654 | void (*load_luts)(struct drm_crtc_state *crtc_state); | |
655 | }; | |
656 | ||
657 | enum forcewake_domain_id { | |
658 | FW_DOMAIN_ID_RENDER = 0, | |
659 | FW_DOMAIN_ID_BLITTER, | |
660 | FW_DOMAIN_ID_MEDIA, | |
661 | ||
662 | FW_DOMAIN_ID_COUNT | |
663 | }; | |
664 | ||
665 | enum forcewake_domains { | |
666 | FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER), | |
667 | FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER), | |
668 | FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA), | |
669 | FORCEWAKE_ALL = (FORCEWAKE_RENDER | | |
670 | FORCEWAKE_BLITTER | | |
671 | FORCEWAKE_MEDIA) | |
672 | }; | |
673 | ||
674 | #define FW_REG_READ (1) | |
675 | #define FW_REG_WRITE (2) | |
676 | ||
677 | enum forcewake_domains | |
678 | intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv, | |
679 | i915_reg_t reg, unsigned int op); | |
680 | ||
681 | struct intel_uncore_funcs { | |
682 | void (*force_wake_get)(struct drm_i915_private *dev_priv, | |
683 | enum forcewake_domains domains); | |
684 | void (*force_wake_put)(struct drm_i915_private *dev_priv, | |
685 | enum forcewake_domains domains); | |
686 | ||
687 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
688 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
689 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
690 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace); | |
691 | ||
692 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r, | |
693 | uint8_t val, bool trace); | |
694 | void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r, | |
695 | uint16_t val, bool trace); | |
696 | void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r, | |
697 | uint32_t val, bool trace); | |
698 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r, | |
699 | uint64_t val, bool trace); | |
700 | }; | |
701 | ||
702 | struct intel_uncore { | |
703 | spinlock_t lock; /** lock is also taken in irq contexts. */ | |
704 | ||
705 | struct intel_uncore_funcs funcs; | |
706 | ||
707 | unsigned fifo_count; | |
708 | enum forcewake_domains fw_domains; | |
709 | ||
710 | struct intel_uncore_forcewake_domain { | |
711 | struct drm_i915_private *i915; | |
712 | enum forcewake_domain_id id; | |
713 | enum forcewake_domains mask; | |
714 | unsigned wake_count; | |
715 | struct hrtimer timer; | |
716 | i915_reg_t reg_set; | |
717 | u32 val_set; | |
718 | u32 val_clear; | |
719 | i915_reg_t reg_ack; | |
720 | i915_reg_t reg_post; | |
721 | u32 val_reset; | |
722 | } fw_domain[FW_DOMAIN_ID_COUNT]; | |
723 | ||
724 | int unclaimed_mmio_check; | |
725 | }; | |
726 | ||
727 | /* Iterate over initialised fw domains */ | |
728 | #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \ | |
729 | for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \ | |
730 | (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \ | |
731 | (domain__)++) \ | |
732 | for_each_if ((mask__) & (domain__)->mask) | |
733 | ||
734 | #define for_each_fw_domain(domain__, dev_priv__) \ | |
735 | for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__) | |
736 | ||
737 | #define CSR_VERSION(major, minor) ((major) << 16 | (minor)) | |
738 | #define CSR_VERSION_MAJOR(version) ((version) >> 16) | |
739 | #define CSR_VERSION_MINOR(version) ((version) & 0xffff) | |
740 | ||
741 | struct intel_csr { | |
742 | struct work_struct work; | |
743 | const char *fw_path; | |
744 | uint32_t *dmc_payload; | |
745 | uint32_t dmc_fw_size; | |
746 | uint32_t version; | |
747 | uint32_t mmio_count; | |
748 | i915_reg_t mmioaddr[8]; | |
749 | uint32_t mmiodata[8]; | |
750 | uint32_t dc_state; | |
751 | uint32_t allowed_dc_mask; | |
752 | }; | |
753 | ||
754 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ | |
755 | func(is_mobile) sep \ | |
756 | func(is_i85x) sep \ | |
757 | func(is_i915g) sep \ | |
758 | func(is_i945gm) sep \ | |
759 | func(is_g33) sep \ | |
760 | func(need_gfx_hws) sep \ | |
761 | func(is_g4x) sep \ | |
762 | func(is_pineview) sep \ | |
763 | func(is_broadwater) sep \ | |
764 | func(is_crestline) sep \ | |
765 | func(is_ivybridge) sep \ | |
766 | func(is_valleyview) sep \ | |
767 | func(is_cherryview) sep \ | |
768 | func(is_haswell) sep \ | |
769 | func(is_broadwell) sep \ | |
770 | func(is_skylake) sep \ | |
771 | func(is_broxton) sep \ | |
772 | func(is_kabylake) sep \ | |
773 | func(is_preliminary) sep \ | |
774 | func(has_fbc) sep \ | |
775 | func(has_pipe_cxsr) sep \ | |
776 | func(has_hotplug) sep \ | |
777 | func(cursor_needs_physical) sep \ | |
778 | func(has_overlay) sep \ | |
779 | func(overlay_needs_physical) sep \ | |
780 | func(supports_tv) sep \ | |
781 | func(has_llc) sep \ | |
782 | func(has_snoop) sep \ | |
783 | func(has_ddi) sep \ | |
784 | func(has_fpga_dbg) sep \ | |
785 | func(has_pooled_eu) | |
786 | ||
787 | #define DEFINE_FLAG(name) u8 name:1 | |
788 | #define SEP_SEMICOLON ; | |
789 | ||
790 | struct intel_device_info { | |
791 | u32 display_mmio_offset; | |
792 | u16 device_id; | |
793 | u8 num_pipes; | |
794 | u8 num_sprites[I915_MAX_PIPES]; | |
795 | u8 gen; | |
796 | u16 gen_mask; | |
797 | u8 ring_mask; /* Rings supported by the HW */ | |
798 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); | |
799 | /* Register offsets for the various display pipes and transcoders */ | |
800 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
801 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
802 | int palette_offsets[I915_MAX_PIPES]; | |
803 | int cursor_offsets[I915_MAX_PIPES]; | |
804 | ||
805 | /* Slice/subslice/EU info */ | |
806 | u8 slice_total; | |
807 | u8 subslice_total; | |
808 | u8 subslice_per_slice; | |
809 | u8 eu_total; | |
810 | u8 eu_per_subslice; | |
811 | u8 min_eu_in_pool; | |
812 | /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ | |
813 | u8 subslice_7eu[3]; | |
814 | u8 has_slice_pg:1; | |
815 | u8 has_subslice_pg:1; | |
816 | u8 has_eu_pg:1; | |
817 | ||
818 | struct color_luts { | |
819 | u16 degamma_lut_size; | |
820 | u16 gamma_lut_size; | |
821 | } color; | |
822 | }; | |
823 | ||
824 | #undef DEFINE_FLAG | |
825 | #undef SEP_SEMICOLON | |
826 | ||
827 | enum i915_cache_level { | |
828 | I915_CACHE_NONE = 0, | |
829 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ | |
830 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
831 | caches, eg sampler/render caches, and the | |
832 | large Last-Level-Cache. LLC is coherent with | |
833 | the CPU, but L3 is only visible to the GPU. */ | |
834 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ | |
835 | }; | |
836 | ||
837 | struct i915_ctx_hang_stats { | |
838 | /* This context had batch pending when hang was declared */ | |
839 | unsigned batch_pending; | |
840 | ||
841 | /* This context had batch active when hang was declared */ | |
842 | unsigned batch_active; | |
843 | ||
844 | /* Time when this context was last blamed for a GPU reset */ | |
845 | unsigned long guilty_ts; | |
846 | ||
847 | /* If the contexts causes a second GPU hang within this time, | |
848 | * it is permanently banned from submitting any more work. | |
849 | */ | |
850 | unsigned long ban_period_seconds; | |
851 | ||
852 | /* This context is banned to submit more work */ | |
853 | bool banned; | |
854 | }; | |
855 | ||
856 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
857 | #define DEFAULT_CONTEXT_HANDLE 0 | |
858 | ||
859 | /** | |
860 | * struct i915_gem_context - as the name implies, represents a context. | |
861 | * @ref: reference count. | |
862 | * @user_handle: userspace tracking identity for this context. | |
863 | * @remap_slice: l3 row remapping information. | |
864 | * @flags: context specific flags: | |
865 | * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0. | |
866 | * @file_priv: filp associated with this context (NULL for global default | |
867 | * context). | |
868 | * @hang_stats: information about the role of this context in possible GPU | |
869 | * hangs. | |
870 | * @ppgtt: virtual memory space used by this context. | |
871 | * @legacy_hw_ctx: render context backing object and whether it is correctly | |
872 | * initialized (legacy ring submission mechanism only). | |
873 | * @link: link in the global list of contexts. | |
874 | * | |
875 | * Contexts are memory images used by the hardware to store copies of their | |
876 | * internal state. | |
877 | */ | |
878 | struct i915_gem_context { | |
879 | struct kref ref; | |
880 | struct drm_i915_private *i915; | |
881 | struct drm_i915_file_private *file_priv; | |
882 | struct i915_hw_ppgtt *ppgtt; | |
883 | ||
884 | struct i915_ctx_hang_stats hang_stats; | |
885 | ||
886 | /* Unique identifier for this context, used by the hw for tracking */ | |
887 | unsigned long flags; | |
888 | #define CONTEXT_NO_ZEROMAP BIT(0) | |
889 | #define CONTEXT_NO_ERROR_CAPTURE BIT(1) | |
890 | unsigned hw_id; | |
891 | u32 user_handle; | |
892 | ||
893 | u32 ggtt_alignment; | |
894 | ||
895 | struct intel_context { | |
896 | struct drm_i915_gem_object *state; | |
897 | struct intel_ring *ring; | |
898 | struct i915_vma *lrc_vma; | |
899 | uint32_t *lrc_reg_state; | |
900 | u64 lrc_desc; | |
901 | int pin_count; | |
902 | bool initialised; | |
903 | } engine[I915_NUM_ENGINES]; | |
904 | u32 ring_size; | |
905 | u32 desc_template; | |
906 | struct atomic_notifier_head status_notifier; | |
907 | bool execlists_force_single_submission; | |
908 | ||
909 | struct list_head link; | |
910 | ||
911 | u8 remap_slice; | |
912 | }; | |
913 | ||
914 | enum fb_op_origin { | |
915 | ORIGIN_GTT, | |
916 | ORIGIN_CPU, | |
917 | ORIGIN_CS, | |
918 | ORIGIN_FLIP, | |
919 | ORIGIN_DIRTYFB, | |
920 | }; | |
921 | ||
922 | struct intel_fbc { | |
923 | /* This is always the inner lock when overlapping with struct_mutex and | |
924 | * it's the outer lock when overlapping with stolen_lock. */ | |
925 | struct mutex lock; | |
926 | unsigned threshold; | |
927 | unsigned int possible_framebuffer_bits; | |
928 | unsigned int busy_bits; | |
929 | unsigned int visible_pipes_mask; | |
930 | struct intel_crtc *crtc; | |
931 | ||
932 | struct drm_mm_node compressed_fb; | |
933 | struct drm_mm_node *compressed_llb; | |
934 | ||
935 | bool false_color; | |
936 | ||
937 | bool enabled; | |
938 | bool active; | |
939 | ||
940 | struct intel_fbc_state_cache { | |
941 | struct { | |
942 | unsigned int mode_flags; | |
943 | uint32_t hsw_bdw_pixel_rate; | |
944 | } crtc; | |
945 | ||
946 | struct { | |
947 | unsigned int rotation; | |
948 | int src_w; | |
949 | int src_h; | |
950 | bool visible; | |
951 | } plane; | |
952 | ||
953 | struct { | |
954 | u64 ilk_ggtt_offset; | |
955 | uint32_t pixel_format; | |
956 | unsigned int stride; | |
957 | int fence_reg; | |
958 | unsigned int tiling_mode; | |
959 | } fb; | |
960 | } state_cache; | |
961 | ||
962 | struct intel_fbc_reg_params { | |
963 | struct { | |
964 | enum pipe pipe; | |
965 | enum plane plane; | |
966 | unsigned int fence_y_offset; | |
967 | } crtc; | |
968 | ||
969 | struct { | |
970 | u64 ggtt_offset; | |
971 | uint32_t pixel_format; | |
972 | unsigned int stride; | |
973 | int fence_reg; | |
974 | } fb; | |
975 | ||
976 | int cfb_size; | |
977 | } params; | |
978 | ||
979 | struct intel_fbc_work { | |
980 | bool scheduled; | |
981 | u32 scheduled_vblank; | |
982 | struct work_struct work; | |
983 | } work; | |
984 | ||
985 | const char *no_fbc_reason; | |
986 | }; | |
987 | ||
988 | /** | |
989 | * HIGH_RR is the highest eDP panel refresh rate read from EDID | |
990 | * LOW_RR is the lowest eDP panel refresh rate found from EDID | |
991 | * parsing for same resolution. | |
992 | */ | |
993 | enum drrs_refresh_rate_type { | |
994 | DRRS_HIGH_RR, | |
995 | DRRS_LOW_RR, | |
996 | DRRS_MAX_RR, /* RR count */ | |
997 | }; | |
998 | ||
999 | enum drrs_support_type { | |
1000 | DRRS_NOT_SUPPORTED = 0, | |
1001 | STATIC_DRRS_SUPPORT = 1, | |
1002 | SEAMLESS_DRRS_SUPPORT = 2 | |
1003 | }; | |
1004 | ||
1005 | struct intel_dp; | |
1006 | struct i915_drrs { | |
1007 | struct mutex mutex; | |
1008 | struct delayed_work work; | |
1009 | struct intel_dp *dp; | |
1010 | unsigned busy_frontbuffer_bits; | |
1011 | enum drrs_refresh_rate_type refresh_rate_type; | |
1012 | enum drrs_support_type type; | |
1013 | }; | |
1014 | ||
1015 | struct i915_psr { | |
1016 | struct mutex lock; | |
1017 | bool sink_support; | |
1018 | bool source_ok; | |
1019 | struct intel_dp *enabled; | |
1020 | bool active; | |
1021 | struct delayed_work work; | |
1022 | unsigned busy_frontbuffer_bits; | |
1023 | bool psr2_support; | |
1024 | bool aux_frame_sync; | |
1025 | bool link_standby; | |
1026 | }; | |
1027 | ||
1028 | enum intel_pch { | |
1029 | PCH_NONE = 0, /* No PCH present */ | |
1030 | PCH_IBX, /* Ibexpeak PCH */ | |
1031 | PCH_CPT, /* Cougarpoint PCH */ | |
1032 | PCH_LPT, /* Lynxpoint PCH */ | |
1033 | PCH_SPT, /* Sunrisepoint PCH */ | |
1034 | PCH_KBP, /* Kabypoint PCH */ | |
1035 | PCH_NOP, | |
1036 | }; | |
1037 | ||
1038 | enum intel_sbi_destination { | |
1039 | SBI_ICLK, | |
1040 | SBI_MPHY, | |
1041 | }; | |
1042 | ||
1043 | #define QUIRK_PIPEA_FORCE (1<<0) | |
1044 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) | |
1045 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) | |
1046 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) | |
1047 | #define QUIRK_PIPEB_FORCE (1<<4) | |
1048 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) | |
1049 | ||
1050 | struct intel_fbdev; | |
1051 | struct intel_fbc_work; | |
1052 | ||
1053 | struct intel_gmbus { | |
1054 | struct i2c_adapter adapter; | |
1055 | #define GMBUS_FORCE_BIT_RETRY (1U << 31) | |
1056 | u32 force_bit; | |
1057 | u32 reg0; | |
1058 | i915_reg_t gpio_reg; | |
1059 | struct i2c_algo_bit_data bit_algo; | |
1060 | struct drm_i915_private *dev_priv; | |
1061 | }; | |
1062 | ||
1063 | struct i915_suspend_saved_registers { | |
1064 | u32 saveDSPARB; | |
1065 | u32 saveLVDS; | |
1066 | u32 savePP_ON_DELAYS; | |
1067 | u32 savePP_OFF_DELAYS; | |
1068 | u32 savePP_ON; | |
1069 | u32 savePP_OFF; | |
1070 | u32 savePP_CONTROL; | |
1071 | u32 savePP_DIVISOR; | |
1072 | u32 saveFBC_CONTROL; | |
1073 | u32 saveCACHE_MODE_0; | |
1074 | u32 saveMI_ARB_STATE; | |
1075 | u32 saveSWF0[16]; | |
1076 | u32 saveSWF1[16]; | |
1077 | u32 saveSWF3[3]; | |
1078 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; | |
1079 | u32 savePCH_PORT_HOTPLUG; | |
1080 | u16 saveGCDGMBUS; | |
1081 | }; | |
1082 | ||
1083 | struct vlv_s0ix_state { | |
1084 | /* GAM */ | |
1085 | u32 wr_watermark; | |
1086 | u32 gfx_prio_ctrl; | |
1087 | u32 arb_mode; | |
1088 | u32 gfx_pend_tlb0; | |
1089 | u32 gfx_pend_tlb1; | |
1090 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; | |
1091 | u32 media_max_req_count; | |
1092 | u32 gfx_max_req_count; | |
1093 | u32 render_hwsp; | |
1094 | u32 ecochk; | |
1095 | u32 bsd_hwsp; | |
1096 | u32 blt_hwsp; | |
1097 | u32 tlb_rd_addr; | |
1098 | ||
1099 | /* MBC */ | |
1100 | u32 g3dctl; | |
1101 | u32 gsckgctl; | |
1102 | u32 mbctl; | |
1103 | ||
1104 | /* GCP */ | |
1105 | u32 ucgctl1; | |
1106 | u32 ucgctl3; | |
1107 | u32 rcgctl1; | |
1108 | u32 rcgctl2; | |
1109 | u32 rstctl; | |
1110 | u32 misccpctl; | |
1111 | ||
1112 | /* GPM */ | |
1113 | u32 gfxpause; | |
1114 | u32 rpdeuhwtc; | |
1115 | u32 rpdeuc; | |
1116 | u32 ecobus; | |
1117 | u32 pwrdwnupctl; | |
1118 | u32 rp_down_timeout; | |
1119 | u32 rp_deucsw; | |
1120 | u32 rcubmabdtmr; | |
1121 | u32 rcedata; | |
1122 | u32 spare2gh; | |
1123 | ||
1124 | /* Display 1 CZ domain */ | |
1125 | u32 gt_imr; | |
1126 | u32 gt_ier; | |
1127 | u32 pm_imr; | |
1128 | u32 pm_ier; | |
1129 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; | |
1130 | ||
1131 | /* GT SA CZ domain */ | |
1132 | u32 tilectl; | |
1133 | u32 gt_fifoctl; | |
1134 | u32 gtlc_wake_ctrl; | |
1135 | u32 gtlc_survive; | |
1136 | u32 pmwgicz; | |
1137 | ||
1138 | /* Display 2 CZ domain */ | |
1139 | u32 gu_ctl0; | |
1140 | u32 gu_ctl1; | |
1141 | u32 pcbr; | |
1142 | u32 clock_gate_dis2; | |
1143 | }; | |
1144 | ||
1145 | struct intel_rps_ei { | |
1146 | u32 cz_clock; | |
1147 | u32 render_c0; | |
1148 | u32 media_c0; | |
1149 | }; | |
1150 | ||
1151 | struct intel_gen6_power_mgmt { | |
1152 | /* | |
1153 | * work, interrupts_enabled and pm_iir are protected by | |
1154 | * dev_priv->irq_lock | |
1155 | */ | |
1156 | struct work_struct work; | |
1157 | bool interrupts_enabled; | |
1158 | u32 pm_iir; | |
1159 | ||
1160 | u32 pm_intr_keep; | |
1161 | ||
1162 | /* Frequencies are stored in potentially platform dependent multiples. | |
1163 | * In other words, *_freq needs to be multiplied by X to be interesting. | |
1164 | * Soft limits are those which are used for the dynamic reclocking done | |
1165 | * by the driver (raise frequencies under heavy loads, and lower for | |
1166 | * lighter loads). Hard limits are those imposed by the hardware. | |
1167 | * | |
1168 | * A distinction is made for overclocking, which is never enabled by | |
1169 | * default, and is considered to be above the hard limit if it's | |
1170 | * possible at all. | |
1171 | */ | |
1172 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ | |
1173 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ | |
1174 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ | |
1175 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ | |
1176 | u8 min_freq; /* AKA RPn. Minimum frequency */ | |
1177 | u8 boost_freq; /* Frequency to request when wait boosting */ | |
1178 | u8 idle_freq; /* Frequency to request when we are idle */ | |
1179 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ | |
1180 | u8 rp1_freq; /* "less than" RP0 power/freqency */ | |
1181 | u8 rp0_freq; /* Non-overclocked max frequency. */ | |
1182 | u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */ | |
1183 | ||
1184 | u8 up_threshold; /* Current %busy required to uplock */ | |
1185 | u8 down_threshold; /* Current %busy required to downclock */ | |
1186 | ||
1187 | int last_adj; | |
1188 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; | |
1189 | ||
1190 | spinlock_t client_lock; | |
1191 | struct list_head clients; | |
1192 | bool client_boost; | |
1193 | ||
1194 | bool enabled; | |
1195 | struct delayed_work autoenable_work; | |
1196 | unsigned boosts; | |
1197 | ||
1198 | /* manual wa residency calculations */ | |
1199 | struct intel_rps_ei up_ei, down_ei; | |
1200 | ||
1201 | /* | |
1202 | * Protects RPS/RC6 register access and PCU communication. | |
1203 | * Must be taken after struct_mutex if nested. Note that | |
1204 | * this lock may be held for long periods of time when | |
1205 | * talking to hw - so only take it when talking to hw! | |
1206 | */ | |
1207 | struct mutex hw_lock; | |
1208 | }; | |
1209 | ||
1210 | /* defined intel_pm.c */ | |
1211 | extern spinlock_t mchdev_lock; | |
1212 | ||
1213 | struct intel_ilk_power_mgmt { | |
1214 | u8 cur_delay; | |
1215 | u8 min_delay; | |
1216 | u8 max_delay; | |
1217 | u8 fmax; | |
1218 | u8 fstart; | |
1219 | ||
1220 | u64 last_count1; | |
1221 | unsigned long last_time1; | |
1222 | unsigned long chipset_power; | |
1223 | u64 last_count2; | |
1224 | u64 last_time2; | |
1225 | unsigned long gfx_power; | |
1226 | u8 corr; | |
1227 | ||
1228 | int c_m; | |
1229 | int r_t; | |
1230 | }; | |
1231 | ||
1232 | struct drm_i915_private; | |
1233 | struct i915_power_well; | |
1234 | ||
1235 | struct i915_power_well_ops { | |
1236 | /* | |
1237 | * Synchronize the well's hw state to match the current sw state, for | |
1238 | * example enable/disable it based on the current refcount. Called | |
1239 | * during driver init and resume time, possibly after first calling | |
1240 | * the enable/disable handlers. | |
1241 | */ | |
1242 | void (*sync_hw)(struct drm_i915_private *dev_priv, | |
1243 | struct i915_power_well *power_well); | |
1244 | /* | |
1245 | * Enable the well and resources that depend on it (for example | |
1246 | * interrupts located on the well). Called after the 0->1 refcount | |
1247 | * transition. | |
1248 | */ | |
1249 | void (*enable)(struct drm_i915_private *dev_priv, | |
1250 | struct i915_power_well *power_well); | |
1251 | /* | |
1252 | * Disable the well and resources that depend on it. Called after | |
1253 | * the 1->0 refcount transition. | |
1254 | */ | |
1255 | void (*disable)(struct drm_i915_private *dev_priv, | |
1256 | struct i915_power_well *power_well); | |
1257 | /* Returns the hw enabled state. */ | |
1258 | bool (*is_enabled)(struct drm_i915_private *dev_priv, | |
1259 | struct i915_power_well *power_well); | |
1260 | }; | |
1261 | ||
1262 | /* Power well structure for haswell */ | |
1263 | struct i915_power_well { | |
1264 | const char *name; | |
1265 | bool always_on; | |
1266 | /* power well enable/disable usage count */ | |
1267 | int count; | |
1268 | /* cached hw enabled state */ | |
1269 | bool hw_enabled; | |
1270 | unsigned long domains; | |
1271 | unsigned long data; | |
1272 | const struct i915_power_well_ops *ops; | |
1273 | }; | |
1274 | ||
1275 | struct i915_power_domains { | |
1276 | /* | |
1277 | * Power wells needed for initialization at driver init and suspend | |
1278 | * time are on. They are kept on until after the first modeset. | |
1279 | */ | |
1280 | bool init_power_on; | |
1281 | bool initializing; | |
1282 | int power_well_count; | |
1283 | ||
1284 | struct mutex lock; | |
1285 | int domain_use_count[POWER_DOMAIN_NUM]; | |
1286 | struct i915_power_well *power_wells; | |
1287 | }; | |
1288 | ||
1289 | #define MAX_L3_SLICES 2 | |
1290 | struct intel_l3_parity { | |
1291 | u32 *remap_info[MAX_L3_SLICES]; | |
1292 | struct work_struct error_work; | |
1293 | int which_slice; | |
1294 | }; | |
1295 | ||
1296 | struct i915_gem_mm { | |
1297 | /** Memory allocator for GTT stolen memory */ | |
1298 | struct drm_mm stolen; | |
1299 | /** Protects the usage of the GTT stolen memory allocator. This is | |
1300 | * always the inner lock when overlapping with struct_mutex. */ | |
1301 | struct mutex stolen_lock; | |
1302 | ||
1303 | /** List of all objects in gtt_space. Used to restore gtt | |
1304 | * mappings on resume */ | |
1305 | struct list_head bound_list; | |
1306 | /** | |
1307 | * List of objects which are not bound to the GTT (thus | |
1308 | * are idle and not used by the GPU) but still have | |
1309 | * (presumably uncached) pages still attached. | |
1310 | */ | |
1311 | struct list_head unbound_list; | |
1312 | ||
1313 | /** Usable portion of the GTT for GEM */ | |
1314 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
1315 | ||
1316 | /** PPGTT used for aliasing the PPGTT with the GTT */ | |
1317 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
1318 | ||
1319 | struct notifier_block oom_notifier; | |
1320 | struct notifier_block vmap_notifier; | |
1321 | struct shrinker shrinker; | |
1322 | bool shrinker_no_lock_stealing; | |
1323 | ||
1324 | /** LRU list of objects with fence regs on them. */ | |
1325 | struct list_head fence_list; | |
1326 | ||
1327 | /** | |
1328 | * Are we in a non-interruptible section of code like | |
1329 | * modesetting? | |
1330 | */ | |
1331 | bool interruptible; | |
1332 | ||
1333 | /* the indicator for dispatch video commands on two BSD rings */ | |
1334 | unsigned int bsd_engine_dispatch_index; | |
1335 | ||
1336 | /** Bit 6 swizzling required for X tiling */ | |
1337 | uint32_t bit_6_swizzle_x; | |
1338 | /** Bit 6 swizzling required for Y tiling */ | |
1339 | uint32_t bit_6_swizzle_y; | |
1340 | ||
1341 | /* accounting, useful for userland debugging */ | |
1342 | spinlock_t object_stat_lock; | |
1343 | size_t object_memory; | |
1344 | u32 object_count; | |
1345 | }; | |
1346 | ||
1347 | struct drm_i915_error_state_buf { | |
1348 | struct drm_i915_private *i915; | |
1349 | unsigned bytes; | |
1350 | unsigned size; | |
1351 | int err; | |
1352 | u8 *buf; | |
1353 | loff_t start; | |
1354 | loff_t pos; | |
1355 | }; | |
1356 | ||
1357 | struct i915_error_state_file_priv { | |
1358 | struct drm_device *dev; | |
1359 | struct drm_i915_error_state *error; | |
1360 | }; | |
1361 | ||
1362 | struct i915_gpu_error { | |
1363 | /* For hangcheck timer */ | |
1364 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
1365 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
1366 | /* Hang gpu twice in this window and your context gets banned */ | |
1367 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) | |
1368 | ||
1369 | struct delayed_work hangcheck_work; | |
1370 | ||
1371 | /* For reset and error_state handling. */ | |
1372 | spinlock_t lock; | |
1373 | /* Protected by the above dev->gpu_error.lock. */ | |
1374 | struct drm_i915_error_state *first_error; | |
1375 | ||
1376 | unsigned long missed_irq_rings; | |
1377 | ||
1378 | /** | |
1379 | * State variable controlling the reset flow and count | |
1380 | * | |
1381 | * This is a counter which gets incremented when reset is triggered, | |
1382 | * and again when reset has been handled. So odd values (lowest bit set) | |
1383 | * means that reset is in progress and even values that | |
1384 | * (reset_counter >> 1):th reset was successfully completed. | |
1385 | * | |
1386 | * If reset is not completed succesfully, the I915_WEDGE bit is | |
1387 | * set meaning that hardware is terminally sour and there is no | |
1388 | * recovery. All waiters on the reset_queue will be woken when | |
1389 | * that happens. | |
1390 | * | |
1391 | * This counter is used by the wait_seqno code to notice that reset | |
1392 | * event happened and it needs to restart the entire ioctl (since most | |
1393 | * likely the seqno it waited for won't ever signal anytime soon). | |
1394 | * | |
1395 | * This is important for lock-free wait paths, where no contended lock | |
1396 | * naturally enforces the correct ordering between the bail-out of the | |
1397 | * waiter and the gpu reset work code. | |
1398 | */ | |
1399 | atomic_t reset_counter; | |
1400 | ||
1401 | #define I915_RESET_IN_PROGRESS_FLAG 1 | |
1402 | #define I915_WEDGED (1 << 31) | |
1403 | ||
1404 | /** | |
1405 | * Waitqueue to signal when a hang is detected. Used to for waiters | |
1406 | * to release the struct_mutex for the reset to procede. | |
1407 | */ | |
1408 | wait_queue_head_t wait_queue; | |
1409 | ||
1410 | /** | |
1411 | * Waitqueue to signal when the reset has completed. Used by clients | |
1412 | * that wait for dev_priv->mm.wedged to settle. | |
1413 | */ | |
1414 | wait_queue_head_t reset_queue; | |
1415 | ||
1416 | /* For missed irq/seqno simulation. */ | |
1417 | unsigned long test_irq_rings; | |
1418 | }; | |
1419 | ||
1420 | enum modeset_restore { | |
1421 | MODESET_ON_LID_OPEN, | |
1422 | MODESET_DONE, | |
1423 | MODESET_SUSPENDED, | |
1424 | }; | |
1425 | ||
1426 | #define DP_AUX_A 0x40 | |
1427 | #define DP_AUX_B 0x10 | |
1428 | #define DP_AUX_C 0x20 | |
1429 | #define DP_AUX_D 0x30 | |
1430 | ||
1431 | #define DDC_PIN_B 0x05 | |
1432 | #define DDC_PIN_C 0x04 | |
1433 | #define DDC_PIN_D 0x06 | |
1434 | ||
1435 | struct ddi_vbt_port_info { | |
1436 | /* | |
1437 | * This is an index in the HDMI/DVI DDI buffer translation table. | |
1438 | * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't | |
1439 | * populate this field. | |
1440 | */ | |
1441 | #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff | |
1442 | uint8_t hdmi_level_shift; | |
1443 | ||
1444 | uint8_t supports_dvi:1; | |
1445 | uint8_t supports_hdmi:1; | |
1446 | uint8_t supports_dp:1; | |
1447 | ||
1448 | uint8_t alternate_aux_channel; | |
1449 | uint8_t alternate_ddc_pin; | |
1450 | ||
1451 | uint8_t dp_boost_level; | |
1452 | uint8_t hdmi_boost_level; | |
1453 | }; | |
1454 | ||
1455 | enum psr_lines_to_wait { | |
1456 | PSR_0_LINES_TO_WAIT = 0, | |
1457 | PSR_1_LINE_TO_WAIT, | |
1458 | PSR_4_LINES_TO_WAIT, | |
1459 | PSR_8_LINES_TO_WAIT | |
1460 | }; | |
1461 | ||
1462 | struct intel_vbt_data { | |
1463 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1464 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1465 | ||
1466 | /* Feature bits */ | |
1467 | unsigned int int_tv_support:1; | |
1468 | unsigned int lvds_dither:1; | |
1469 | unsigned int lvds_vbt:1; | |
1470 | unsigned int int_crt_support:1; | |
1471 | unsigned int lvds_use_ssc:1; | |
1472 | unsigned int display_clock_mode:1; | |
1473 | unsigned int fdi_rx_polarity_inverted:1; | |
1474 | unsigned int panel_type:4; | |
1475 | int lvds_ssc_freq; | |
1476 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1477 | ||
1478 | enum drrs_support_type drrs_type; | |
1479 | ||
1480 | struct { | |
1481 | int rate; | |
1482 | int lanes; | |
1483 | int preemphasis; | |
1484 | int vswing; | |
1485 | bool low_vswing; | |
1486 | bool initialized; | |
1487 | bool support; | |
1488 | int bpp; | |
1489 | struct edp_power_seq pps; | |
1490 | } edp; | |
1491 | ||
1492 | struct { | |
1493 | bool full_link; | |
1494 | bool require_aux_wakeup; | |
1495 | int idle_frames; | |
1496 | enum psr_lines_to_wait lines_to_wait; | |
1497 | int tp1_wakeup_time; | |
1498 | int tp2_tp3_wakeup_time; | |
1499 | } psr; | |
1500 | ||
1501 | struct { | |
1502 | u16 pwm_freq_hz; | |
1503 | bool present; | |
1504 | bool active_low_pwm; | |
1505 | u8 min_brightness; /* min_brightness/255 of max */ | |
1506 | enum intel_backlight_type type; | |
1507 | } backlight; | |
1508 | ||
1509 | /* MIPI DSI */ | |
1510 | struct { | |
1511 | u16 panel_id; | |
1512 | struct mipi_config *config; | |
1513 | struct mipi_pps_data *pps; | |
1514 | u8 seq_version; | |
1515 | u32 size; | |
1516 | u8 *data; | |
1517 | const u8 *sequence[MIPI_SEQ_MAX]; | |
1518 | } dsi; | |
1519 | ||
1520 | int crt_ddc_pin; | |
1521 | ||
1522 | int child_dev_num; | |
1523 | union child_device_config *child_dev; | |
1524 | ||
1525 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
1526 | struct sdvo_device_mapping sdvo_mappings[2]; | |
1527 | }; | |
1528 | ||
1529 | enum intel_ddb_partitioning { | |
1530 | INTEL_DDB_PART_1_2, | |
1531 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1532 | }; | |
1533 | ||
1534 | struct intel_wm_level { | |
1535 | bool enable; | |
1536 | uint32_t pri_val; | |
1537 | uint32_t spr_val; | |
1538 | uint32_t cur_val; | |
1539 | uint32_t fbc_val; | |
1540 | }; | |
1541 | ||
1542 | struct ilk_wm_values { | |
1543 | uint32_t wm_pipe[3]; | |
1544 | uint32_t wm_lp[3]; | |
1545 | uint32_t wm_lp_spr[3]; | |
1546 | uint32_t wm_linetime[3]; | |
1547 | bool enable_fbc_wm; | |
1548 | enum intel_ddb_partitioning partitioning; | |
1549 | }; | |
1550 | ||
1551 | struct vlv_pipe_wm { | |
1552 | uint16_t primary; | |
1553 | uint16_t sprite[2]; | |
1554 | uint8_t cursor; | |
1555 | }; | |
1556 | ||
1557 | struct vlv_sr_wm { | |
1558 | uint16_t plane; | |
1559 | uint8_t cursor; | |
1560 | }; | |
1561 | ||
1562 | struct vlv_wm_values { | |
1563 | struct vlv_pipe_wm pipe[3]; | |
1564 | struct vlv_sr_wm sr; | |
1565 | struct { | |
1566 | uint8_t cursor; | |
1567 | uint8_t sprite[2]; | |
1568 | uint8_t primary; | |
1569 | } ddl[3]; | |
1570 | uint8_t level; | |
1571 | bool cxsr; | |
1572 | }; | |
1573 | ||
1574 | struct skl_ddb_entry { | |
1575 | uint16_t start, end; /* in number of blocks, 'end' is exclusive */ | |
1576 | }; | |
1577 | ||
1578 | static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) | |
1579 | { | |
1580 | return entry->end - entry->start; | |
1581 | } | |
1582 | ||
1583 | static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, | |
1584 | const struct skl_ddb_entry *e2) | |
1585 | { | |
1586 | if (e1->start == e2->start && e1->end == e2->end) | |
1587 | return true; | |
1588 | ||
1589 | return false; | |
1590 | } | |
1591 | ||
1592 | struct skl_ddb_allocation { | |
1593 | struct skl_ddb_entry pipe[I915_MAX_PIPES]; | |
1594 | struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */ | |
1595 | struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; | |
1596 | }; | |
1597 | ||
1598 | struct skl_wm_values { | |
1599 | unsigned dirty_pipes; | |
1600 | struct skl_ddb_allocation ddb; | |
1601 | uint32_t wm_linetime[I915_MAX_PIPES]; | |
1602 | uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; | |
1603 | uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES]; | |
1604 | }; | |
1605 | ||
1606 | struct skl_wm_level { | |
1607 | bool plane_en[I915_MAX_PLANES]; | |
1608 | uint16_t plane_res_b[I915_MAX_PLANES]; | |
1609 | uint8_t plane_res_l[I915_MAX_PLANES]; | |
1610 | }; | |
1611 | ||
1612 | /* | |
1613 | * This struct helps tracking the state needed for runtime PM, which puts the | |
1614 | * device in PCI D3 state. Notice that when this happens, nothing on the | |
1615 | * graphics device works, even register access, so we don't get interrupts nor | |
1616 | * anything else. | |
1617 | * | |
1618 | * Every piece of our code that needs to actually touch the hardware needs to | |
1619 | * either call intel_runtime_pm_get or call intel_display_power_get with the | |
1620 | * appropriate power domain. | |
1621 | * | |
1622 | * Our driver uses the autosuspend delay feature, which means we'll only really | |
1623 | * suspend if we stay with zero refcount for a certain amount of time. The | |
1624 | * default value is currently very conservative (see intel_runtime_pm_enable), but | |
1625 | * it can be changed with the standard runtime PM files from sysfs. | |
1626 | * | |
1627 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1628 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1629 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1630 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
1631 | * case it happens. | |
1632 | * | |
1633 | * For more, read the Documentation/power/runtime_pm.txt. | |
1634 | */ | |
1635 | struct i915_runtime_pm { | |
1636 | atomic_t wakeref_count; | |
1637 | atomic_t atomic_seq; | |
1638 | bool suspended; | |
1639 | bool irqs_enabled; | |
1640 | }; | |
1641 | ||
1642 | enum intel_pipe_crc_source { | |
1643 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1644 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1645 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1646 | INTEL_PIPE_CRC_SOURCE_PF, | |
1647 | INTEL_PIPE_CRC_SOURCE_PIPE, | |
1648 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ | |
1649 | INTEL_PIPE_CRC_SOURCE_TV, | |
1650 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1651 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1652 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
1653 | INTEL_PIPE_CRC_SOURCE_AUTO, | |
1654 | INTEL_PIPE_CRC_SOURCE_MAX, | |
1655 | }; | |
1656 | ||
1657 | struct intel_pipe_crc_entry { | |
1658 | uint32_t frame; | |
1659 | uint32_t crc[5]; | |
1660 | }; | |
1661 | ||
1662 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 | |
1663 | struct intel_pipe_crc { | |
1664 | spinlock_t lock; | |
1665 | bool opened; /* exclusive access to the result file */ | |
1666 | struct intel_pipe_crc_entry *entries; | |
1667 | enum intel_pipe_crc_source source; | |
1668 | int head, tail; | |
1669 | wait_queue_head_t wq; | |
1670 | }; | |
1671 | ||
1672 | struct i915_frontbuffer_tracking { | |
1673 | struct mutex lock; | |
1674 | ||
1675 | /* | |
1676 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or | |
1677 | * scheduled flips. | |
1678 | */ | |
1679 | unsigned busy_bits; | |
1680 | unsigned flip_bits; | |
1681 | }; | |
1682 | ||
1683 | struct i915_wa_reg { | |
1684 | i915_reg_t addr; | |
1685 | u32 value; | |
1686 | /* bitmask representing WA bits */ | |
1687 | u32 mask; | |
1688 | }; | |
1689 | ||
1690 | /* | |
1691 | * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only | |
1692 | * allowing it for RCS as we don't foresee any requirement of having | |
1693 | * a whitelist for other engines. When it is really required for | |
1694 | * other engines then the limit need to be increased. | |
1695 | */ | |
1696 | #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS) | |
1697 | ||
1698 | struct i915_workarounds { | |
1699 | struct i915_wa_reg reg[I915_MAX_WA_REGS]; | |
1700 | u32 count; | |
1701 | u32 hw_whitelist_count[I915_NUM_ENGINES]; | |
1702 | }; | |
1703 | ||
1704 | struct i915_virtual_gpu { | |
1705 | bool active; | |
1706 | }; | |
1707 | ||
1708 | /* used in computing the new watermarks state */ | |
1709 | struct intel_wm_config { | |
1710 | unsigned int num_pipes_active; | |
1711 | bool sprites_enabled; | |
1712 | bool sprites_scaled; | |
1713 | }; | |
1714 | ||
1715 | struct drm_i915_private { | |
1716 | struct drm_device drm; | |
1717 | ||
1718 | struct kmem_cache *objects; | |
1719 | struct kmem_cache *vmas; | |
1720 | struct kmem_cache *requests; | |
1721 | ||
1722 | const struct intel_device_info info; | |
1723 | ||
1724 | int relative_constants_mode; | |
1725 | ||
1726 | void __iomem *regs; | |
1727 | ||
1728 | struct intel_uncore uncore; | |
1729 | ||
1730 | struct i915_virtual_gpu vgpu; | |
1731 | ||
1732 | struct intel_gvt gvt; | |
1733 | ||
1734 | struct intel_guc guc; | |
1735 | ||
1736 | struct intel_csr csr; | |
1737 | ||
1738 | struct intel_gmbus gmbus[GMBUS_NUM_PINS]; | |
1739 | ||
1740 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus | |
1741 | * controller on different i2c buses. */ | |
1742 | struct mutex gmbus_mutex; | |
1743 | ||
1744 | /** | |
1745 | * Base address of the gmbus and gpio block. | |
1746 | */ | |
1747 | uint32_t gpio_mmio_base; | |
1748 | ||
1749 | /* MMIO base address for MIPI regs */ | |
1750 | uint32_t mipi_mmio_base; | |
1751 | ||
1752 | uint32_t psr_mmio_base; | |
1753 | ||
1754 | wait_queue_head_t gmbus_wait_queue; | |
1755 | ||
1756 | struct pci_dev *bridge_dev; | |
1757 | struct i915_gem_context *kernel_context; | |
1758 | struct intel_engine_cs engine[I915_NUM_ENGINES]; | |
1759 | struct drm_i915_gem_object *semaphore_obj; | |
1760 | u32 next_seqno; | |
1761 | ||
1762 | struct drm_dma_handle *status_page_dmah; | |
1763 | struct resource mch_res; | |
1764 | ||
1765 | /* protects the irq masks */ | |
1766 | spinlock_t irq_lock; | |
1767 | ||
1768 | /* protects the mmio flip data */ | |
1769 | spinlock_t mmio_flip_lock; | |
1770 | ||
1771 | bool display_irqs_enabled; | |
1772 | ||
1773 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ | |
1774 | struct pm_qos_request pm_qos; | |
1775 | ||
1776 | /* Sideband mailbox protection */ | |
1777 | struct mutex sb_lock; | |
1778 | ||
1779 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
1780 | union { | |
1781 | u32 irq_mask; | |
1782 | u32 de_irq_mask[I915_MAX_PIPES]; | |
1783 | }; | |
1784 | u32 gt_irq_mask; | |
1785 | u32 pm_irq_mask; | |
1786 | u32 pm_rps_events; | |
1787 | u32 pipestat_irq_mask[I915_MAX_PIPES]; | |
1788 | ||
1789 | struct i915_hotplug hotplug; | |
1790 | struct intel_fbc fbc; | |
1791 | struct i915_drrs drrs; | |
1792 | struct intel_opregion opregion; | |
1793 | struct intel_vbt_data vbt; | |
1794 | ||
1795 | bool preserve_bios_swizzle; | |
1796 | ||
1797 | /* overlay */ | |
1798 | struct intel_overlay *overlay; | |
1799 | ||
1800 | /* backlight registers and fields in struct intel_panel */ | |
1801 | struct mutex backlight_lock; | |
1802 | ||
1803 | /* LVDS info */ | |
1804 | bool no_aux_handshake; | |
1805 | ||
1806 | /* protects panel power sequencer state */ | |
1807 | struct mutex pps_mutex; | |
1808 | ||
1809 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ | |
1810 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
1811 | ||
1812 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
1813 | unsigned int skl_preferred_vco_freq; | |
1814 | unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq; | |
1815 | unsigned int max_dotclk_freq; | |
1816 | unsigned int rawclk_freq; | |
1817 | unsigned int hpll_freq; | |
1818 | unsigned int czclk_freq; | |
1819 | ||
1820 | struct { | |
1821 | unsigned int vco, ref; | |
1822 | } cdclk_pll; | |
1823 | ||
1824 | /** | |
1825 | * wq - Driver workqueue for GEM. | |
1826 | * | |
1827 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
1828 | * locks, for otherwise the flushing done in the pageflip code will | |
1829 | * result in deadlocks. | |
1830 | */ | |
1831 | struct workqueue_struct *wq; | |
1832 | ||
1833 | /* Display functions */ | |
1834 | struct drm_i915_display_funcs display; | |
1835 | ||
1836 | /* PCH chipset type */ | |
1837 | enum intel_pch pch_type; | |
1838 | unsigned short pch_id; | |
1839 | ||
1840 | unsigned long quirks; | |
1841 | ||
1842 | enum modeset_restore modeset_restore; | |
1843 | struct mutex modeset_restore_lock; | |
1844 | struct drm_atomic_state *modeset_restore_state; | |
1845 | ||
1846 | struct list_head vm_list; /* Global list of all address spaces */ | |
1847 | struct i915_ggtt ggtt; /* VM representing the global address space */ | |
1848 | ||
1849 | struct i915_gem_mm mm; | |
1850 | DECLARE_HASHTABLE(mm_structs, 7); | |
1851 | struct mutex mm_lock; | |
1852 | ||
1853 | /* The hw wants to have a stable context identifier for the lifetime | |
1854 | * of the context (for OA, PASID, faults, etc). This is limited | |
1855 | * in execlists to 21 bits. | |
1856 | */ | |
1857 | struct ida context_hw_ida; | |
1858 | #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */ | |
1859 | ||
1860 | /* Kernel Modesetting */ | |
1861 | ||
1862 | struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; | |
1863 | struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; | |
1864 | wait_queue_head_t pending_flip_queue; | |
1865 | ||
1866 | #ifdef CONFIG_DEBUG_FS | |
1867 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
1868 | #endif | |
1869 | ||
1870 | /* dpll and cdclk state is protected by connection_mutex */ | |
1871 | int num_shared_dpll; | |
1872 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
1873 | const struct intel_dpll_mgr *dpll_mgr; | |
1874 | ||
1875 | /* | |
1876 | * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll. | |
1877 | * Must be global rather than per dpll, because on some platforms | |
1878 | * plls share registers. | |
1879 | */ | |
1880 | struct mutex dpll_lock; | |
1881 | ||
1882 | unsigned int active_crtcs; | |
1883 | unsigned int min_pixclk[I915_MAX_PIPES]; | |
1884 | ||
1885 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; | |
1886 | ||
1887 | struct i915_workarounds workarounds; | |
1888 | ||
1889 | struct i915_frontbuffer_tracking fb_tracking; | |
1890 | ||
1891 | u16 orig_clock; | |
1892 | ||
1893 | bool mchbar_need_disable; | |
1894 | ||
1895 | struct intel_l3_parity l3_parity; | |
1896 | ||
1897 | /* Cannot be determined by PCIID. You must always read a register. */ | |
1898 | u32 edram_cap; | |
1899 | ||
1900 | /* gen6+ rps state */ | |
1901 | struct intel_gen6_power_mgmt rps; | |
1902 | ||
1903 | /* ilk-only ips/rps state. Everything in here is protected by the global | |
1904 | * mchdev_lock in intel_pm.c */ | |
1905 | struct intel_ilk_power_mgmt ips; | |
1906 | ||
1907 | struct i915_power_domains power_domains; | |
1908 | ||
1909 | struct i915_psr psr; | |
1910 | ||
1911 | struct i915_gpu_error gpu_error; | |
1912 | ||
1913 | struct drm_i915_gem_object *vlv_pctx; | |
1914 | ||
1915 | #ifdef CONFIG_DRM_FBDEV_EMULATION | |
1916 | /* list of fbdev register on this device */ | |
1917 | struct intel_fbdev *fbdev; | |
1918 | struct work_struct fbdev_suspend_work; | |
1919 | #endif | |
1920 | ||
1921 | struct drm_property *broadcast_rgb_property; | |
1922 | struct drm_property *force_audio_property; | |
1923 | ||
1924 | /* hda/i915 audio component */ | |
1925 | struct i915_audio_component *audio_component; | |
1926 | bool audio_component_registered; | |
1927 | /** | |
1928 | * av_mutex - mutex for audio/video sync | |
1929 | * | |
1930 | */ | |
1931 | struct mutex av_mutex; | |
1932 | ||
1933 | uint32_t hw_context_size; | |
1934 | struct list_head context_list; | |
1935 | ||
1936 | u32 fdi_rx_config; | |
1937 | ||
1938 | /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ | |
1939 | u32 chv_phy_control; | |
1940 | /* | |
1941 | * Shadows for CHV DPLL_MD regs to keep the state | |
1942 | * checker somewhat working in the presence hardware | |
1943 | * crappiness (can't read out DPLL_MD for pipes B & C). | |
1944 | */ | |
1945 | u32 chv_dpll_md[I915_MAX_PIPES]; | |
1946 | u32 bxt_phy_grc; | |
1947 | ||
1948 | u32 suspend_count; | |
1949 | bool suspended_to_idle; | |
1950 | struct i915_suspend_saved_registers regfile; | |
1951 | struct vlv_s0ix_state vlv_s0ix_state; | |
1952 | ||
1953 | struct { | |
1954 | /* | |
1955 | * Raw watermark latency values: | |
1956 | * in 0.1us units for WM0, | |
1957 | * in 0.5us units for WM1+. | |
1958 | */ | |
1959 | /* primary */ | |
1960 | uint16_t pri_latency[5]; | |
1961 | /* sprite */ | |
1962 | uint16_t spr_latency[5]; | |
1963 | /* cursor */ | |
1964 | uint16_t cur_latency[5]; | |
1965 | /* | |
1966 | * Raw watermark memory latency values | |
1967 | * for SKL for all 8 levels | |
1968 | * in 1us units. | |
1969 | */ | |
1970 | uint16_t skl_latency[8]; | |
1971 | ||
1972 | /* | |
1973 | * The skl_wm_values structure is a bit too big for stack | |
1974 | * allocation, so we keep the staging struct where we store | |
1975 | * intermediate results here instead. | |
1976 | */ | |
1977 | struct skl_wm_values skl_results; | |
1978 | ||
1979 | /* current hardware state */ | |
1980 | union { | |
1981 | struct ilk_wm_values hw; | |
1982 | struct skl_wm_values skl_hw; | |
1983 | struct vlv_wm_values vlv; | |
1984 | }; | |
1985 | ||
1986 | uint8_t max_level; | |
1987 | ||
1988 | /* | |
1989 | * Should be held around atomic WM register writing; also | |
1990 | * protects * intel_crtc->wm.active and | |
1991 | * cstate->wm.need_postvbl_update. | |
1992 | */ | |
1993 | struct mutex wm_mutex; | |
1994 | ||
1995 | /* | |
1996 | * Set during HW readout of watermarks/DDB. Some platforms | |
1997 | * need to know when we're still using BIOS-provided values | |
1998 | * (which we don't fully trust). | |
1999 | */ | |
2000 | bool distrust_bios_wm; | |
2001 | } wm; | |
2002 | ||
2003 | struct i915_runtime_pm pm; | |
2004 | ||
2005 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ | |
2006 | struct { | |
2007 | void (*cleanup_engine)(struct intel_engine_cs *engine); | |
2008 | void (*stop_engine)(struct intel_engine_cs *engine); | |
2009 | ||
2010 | /** | |
2011 | * Is the GPU currently considered idle, or busy executing | |
2012 | * userspace requests? Whilst idle, we allow runtime power | |
2013 | * management to power down the hardware and display clocks. | |
2014 | * In order to reduce the effect on performance, there | |
2015 | * is a slight delay before we do so. | |
2016 | */ | |
2017 | unsigned int active_engines; | |
2018 | bool awake; | |
2019 | ||
2020 | /** | |
2021 | * We leave the user IRQ off as much as possible, | |
2022 | * but this means that requests will finish and never | |
2023 | * be retired once the system goes idle. Set a timer to | |
2024 | * fire periodically while the ring is running. When it | |
2025 | * fires, go retire requests. | |
2026 | */ | |
2027 | struct delayed_work retire_work; | |
2028 | ||
2029 | /** | |
2030 | * When we detect an idle GPU, we want to turn on | |
2031 | * powersaving features. So once we see that there | |
2032 | * are no more requests outstanding and no more | |
2033 | * arrive within a small period of time, we fire | |
2034 | * off the idle_work. | |
2035 | */ | |
2036 | struct delayed_work idle_work; | |
2037 | } gt; | |
2038 | ||
2039 | /* perform PHY state sanity checks? */ | |
2040 | bool chv_phy_assert[2]; | |
2041 | ||
2042 | struct intel_encoder *dig_port_map[I915_MAX_PORTS]; | |
2043 | ||
2044 | /* | |
2045 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch | |
2046 | * will be rejected. Instead look for a better place. | |
2047 | */ | |
2048 | }; | |
2049 | ||
2050 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) | |
2051 | { | |
2052 | return container_of(dev, struct drm_i915_private, drm); | |
2053 | } | |
2054 | ||
2055 | static inline struct drm_i915_private *dev_to_i915(struct device *dev) | |
2056 | { | |
2057 | return to_i915(dev_get_drvdata(dev)); | |
2058 | } | |
2059 | ||
2060 | static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc) | |
2061 | { | |
2062 | return container_of(guc, struct drm_i915_private, guc); | |
2063 | } | |
2064 | ||
2065 | /* Simple iterator over all initialised engines */ | |
2066 | #define for_each_engine(engine__, dev_priv__) \ | |
2067 | for ((engine__) = &(dev_priv__)->engine[0]; \ | |
2068 | (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \ | |
2069 | (engine__)++) \ | |
2070 | for_each_if (intel_engine_initialized(engine__)) | |
2071 | ||
2072 | /* Iterator with engine_id */ | |
2073 | #define for_each_engine_id(engine__, dev_priv__, id__) \ | |
2074 | for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \ | |
2075 | (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \ | |
2076 | (engine__)++) \ | |
2077 | for_each_if (((id__) = (engine__)->id, \ | |
2078 | intel_engine_initialized(engine__))) | |
2079 | ||
2080 | /* Iterator over subset of engines selected by mask */ | |
2081 | #define for_each_engine_masked(engine__, dev_priv__, mask__) \ | |
2082 | for ((engine__) = &(dev_priv__)->engine[0]; \ | |
2083 | (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \ | |
2084 | (engine__)++) \ | |
2085 | for_each_if (((mask__) & intel_engine_flag(engine__)) && \ | |
2086 | intel_engine_initialized(engine__)) | |
2087 | ||
2088 | enum hdmi_force_audio { | |
2089 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
2090 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
2091 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
2092 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
2093 | }; | |
2094 | ||
2095 | #define I915_GTT_OFFSET_NONE ((u32)-1) | |
2096 | ||
2097 | struct drm_i915_gem_object_ops { | |
2098 | unsigned int flags; | |
2099 | #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1 | |
2100 | ||
2101 | /* Interface between the GEM object and its backing storage. | |
2102 | * get_pages() is called once prior to the use of the associated set | |
2103 | * of pages before to binding them into the GTT, and put_pages() is | |
2104 | * called after we no longer need them. As we expect there to be | |
2105 | * associated cost with migrating pages between the backing storage | |
2106 | * and making them available for the GPU (e.g. clflush), we may hold | |
2107 | * onto the pages after they are no longer referenced by the GPU | |
2108 | * in case they may be used again shortly (for example migrating the | |
2109 | * pages to a different memory domain within the GTT). put_pages() | |
2110 | * will therefore most likely be called when the object itself is | |
2111 | * being released or under memory pressure (where we attempt to | |
2112 | * reap pages for the shrinker). | |
2113 | */ | |
2114 | int (*get_pages)(struct drm_i915_gem_object *); | |
2115 | void (*put_pages)(struct drm_i915_gem_object *); | |
2116 | ||
2117 | int (*dmabuf_export)(struct drm_i915_gem_object *); | |
2118 | void (*release)(struct drm_i915_gem_object *); | |
2119 | }; | |
2120 | ||
2121 | /* | |
2122 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is | |
2123 | * considered to be the frontbuffer for the given plane interface-wise. This | |
2124 | * doesn't mean that the hw necessarily already scans it out, but that any | |
2125 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. | |
2126 | * | |
2127 | * We have one bit per pipe and per scanout plane type. | |
2128 | */ | |
2129 | #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5 | |
2130 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 | |
2131 | #define INTEL_FRONTBUFFER_BITS \ | |
2132 | (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES) | |
2133 | #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ | |
2134 | (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
2135 | #define INTEL_FRONTBUFFER_CURSOR(pipe) \ | |
2136 | (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
2137 | #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \ | |
2138 | (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
2139 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ | |
2140 | (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
2141 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ | |
2142 | (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
2143 | ||
2144 | struct drm_i915_gem_object { | |
2145 | struct drm_gem_object base; | |
2146 | ||
2147 | const struct drm_i915_gem_object_ops *ops; | |
2148 | ||
2149 | /** List of VMAs backed by this object */ | |
2150 | struct list_head vma_list; | |
2151 | ||
2152 | /** Stolen memory for this object, instead of being backed by shmem. */ | |
2153 | struct drm_mm_node *stolen; | |
2154 | struct list_head global_list; | |
2155 | ||
2156 | struct list_head engine_list[I915_NUM_ENGINES]; | |
2157 | /** Used in execbuf to temporarily hold a ref */ | |
2158 | struct list_head obj_exec_link; | |
2159 | ||
2160 | struct list_head batch_pool_link; | |
2161 | ||
2162 | /** | |
2163 | * This is set if the object is on the active lists (has pending | |
2164 | * rendering and so a non-zero seqno), and is not set if it i s on | |
2165 | * inactive (ready to be unbound) list. | |
2166 | */ | |
2167 | unsigned int active:I915_NUM_ENGINES; | |
2168 | ||
2169 | /** | |
2170 | * This is set if the object has been written to since last bound | |
2171 | * to the GTT | |
2172 | */ | |
2173 | unsigned int dirty:1; | |
2174 | ||
2175 | /** | |
2176 | * Fence register bits (if any) for this object. Will be set | |
2177 | * as needed when mapped into the GTT. | |
2178 | * Protected by dev->struct_mutex. | |
2179 | */ | |
2180 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; | |
2181 | ||
2182 | /** | |
2183 | * Advice: are the backing pages purgeable? | |
2184 | */ | |
2185 | unsigned int madv:2; | |
2186 | ||
2187 | /** | |
2188 | * Current tiling mode for the object. | |
2189 | */ | |
2190 | unsigned int tiling_mode:2; | |
2191 | /** | |
2192 | * Whether the tiling parameters for the currently associated fence | |
2193 | * register have changed. Note that for the purposes of tracking | |
2194 | * tiling changes we also treat the unfenced register, the register | |
2195 | * slot that the object occupies whilst it executes a fenced | |
2196 | * command (such as BLT on gen2/3), as a "fence". | |
2197 | */ | |
2198 | unsigned int fence_dirty:1; | |
2199 | ||
2200 | /** | |
2201 | * Is the object at the current location in the gtt mappable and | |
2202 | * fenceable? Used to avoid costly recalculations. | |
2203 | */ | |
2204 | unsigned int map_and_fenceable:1; | |
2205 | ||
2206 | /** | |
2207 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
2208 | * mappable by accident). Track pin and fault separate for a more | |
2209 | * accurate mappable working set. | |
2210 | */ | |
2211 | unsigned int fault_mappable:1; | |
2212 | ||
2213 | /* | |
2214 | * Is the object to be mapped as read-only to the GPU | |
2215 | * Only honoured if hardware has relevant pte bit | |
2216 | */ | |
2217 | unsigned long gt_ro:1; | |
2218 | unsigned int cache_level:3; | |
2219 | unsigned int cache_dirty:1; | |
2220 | ||
2221 | unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS; | |
2222 | ||
2223 | unsigned int has_wc_mmap; | |
2224 | /** Count of VMA actually bound by this object */ | |
2225 | unsigned int bind_count; | |
2226 | unsigned int pin_display; | |
2227 | ||
2228 | struct sg_table *pages; | |
2229 | int pages_pin_count; | |
2230 | struct get_page { | |
2231 | struct scatterlist *sg; | |
2232 | int last; | |
2233 | } get_page; | |
2234 | void *mapping; | |
2235 | ||
2236 | /** Breadcrumb of last rendering to the buffer. | |
2237 | * There can only be one writer, but we allow for multiple readers. | |
2238 | * If there is a writer that necessarily implies that all other | |
2239 | * read requests are complete - but we may only be lazily clearing | |
2240 | * the read requests. A read request is naturally the most recent | |
2241 | * request on a ring, so we may have two different write and read | |
2242 | * requests on one ring where the write request is older than the | |
2243 | * read request. This allows for the CPU to read from an active | |
2244 | * buffer by only waiting for the write to complete. | |
2245 | * */ | |
2246 | struct drm_i915_gem_request *last_read_req[I915_NUM_ENGINES]; | |
2247 | struct drm_i915_gem_request *last_write_req; | |
2248 | /** Breadcrumb of last fenced GPU access to the buffer. */ | |
2249 | struct drm_i915_gem_request *last_fenced_req; | |
2250 | ||
2251 | /** Current tiling stride for the object, if it's tiled. */ | |
2252 | uint32_t stride; | |
2253 | ||
2254 | /** References from framebuffers, locks out tiling changes. */ | |
2255 | unsigned long framebuffer_references; | |
2256 | ||
2257 | /** Record of address bit 17 of each page at last unbind. */ | |
2258 | unsigned long *bit_17; | |
2259 | ||
2260 | union { | |
2261 | /** for phy allocated objects */ | |
2262 | struct drm_dma_handle *phys_handle; | |
2263 | ||
2264 | struct i915_gem_userptr { | |
2265 | uintptr_t ptr; | |
2266 | unsigned read_only :1; | |
2267 | unsigned workers :4; | |
2268 | #define I915_GEM_USERPTR_MAX_WORKERS 15 | |
2269 | ||
2270 | struct i915_mm_struct *mm; | |
2271 | struct i915_mmu_object *mmu_object; | |
2272 | struct work_struct *work; | |
2273 | } userptr; | |
2274 | }; | |
2275 | }; | |
2276 | ||
2277 | static inline struct drm_i915_gem_object * | |
2278 | to_intel_bo(struct drm_gem_object *gem) | |
2279 | { | |
2280 | /* Assert that to_intel_bo(NULL) == NULL */ | |
2281 | BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base)); | |
2282 | ||
2283 | return container_of(gem, struct drm_i915_gem_object, base); | |
2284 | } | |
2285 | ||
2286 | static inline struct drm_i915_gem_object * | |
2287 | i915_gem_object_lookup(struct drm_file *file, u32 handle) | |
2288 | { | |
2289 | return to_intel_bo(drm_gem_object_lookup(file, handle)); | |
2290 | } | |
2291 | ||
2292 | __deprecated | |
2293 | extern struct drm_gem_object * | |
2294 | drm_gem_object_lookup(struct drm_file *file, u32 handle); | |
2295 | ||
2296 | __attribute__((nonnull)) | |
2297 | static inline struct drm_i915_gem_object * | |
2298 | i915_gem_object_get(struct drm_i915_gem_object *obj) | |
2299 | { | |
2300 | drm_gem_object_reference(&obj->base); | |
2301 | return obj; | |
2302 | } | |
2303 | ||
2304 | __deprecated | |
2305 | extern void drm_gem_object_reference(struct drm_gem_object *); | |
2306 | ||
2307 | __attribute__((nonnull)) | |
2308 | static inline void | |
2309 | i915_gem_object_put(struct drm_i915_gem_object *obj) | |
2310 | { | |
2311 | drm_gem_object_unreference(&obj->base); | |
2312 | } | |
2313 | ||
2314 | __deprecated | |
2315 | extern void drm_gem_object_unreference(struct drm_gem_object *); | |
2316 | ||
2317 | __attribute__((nonnull)) | |
2318 | static inline void | |
2319 | i915_gem_object_put_unlocked(struct drm_i915_gem_object *obj) | |
2320 | { | |
2321 | drm_gem_object_unreference_unlocked(&obj->base); | |
2322 | } | |
2323 | ||
2324 | __deprecated | |
2325 | extern void drm_gem_object_unreference_unlocked(struct drm_gem_object *); | |
2326 | ||
2327 | static inline bool | |
2328 | i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj) | |
2329 | { | |
2330 | return obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE; | |
2331 | } | |
2332 | ||
2333 | /* | |
2334 | * Optimised SGL iterator for GEM objects | |
2335 | */ | |
2336 | static __always_inline struct sgt_iter { | |
2337 | struct scatterlist *sgp; | |
2338 | union { | |
2339 | unsigned long pfn; | |
2340 | dma_addr_t dma; | |
2341 | }; | |
2342 | unsigned int curr; | |
2343 | unsigned int max; | |
2344 | } __sgt_iter(struct scatterlist *sgl, bool dma) { | |
2345 | struct sgt_iter s = { .sgp = sgl }; | |
2346 | ||
2347 | if (s.sgp) { | |
2348 | s.max = s.curr = s.sgp->offset; | |
2349 | s.max += s.sgp->length; | |
2350 | if (dma) | |
2351 | s.dma = sg_dma_address(s.sgp); | |
2352 | else | |
2353 | s.pfn = page_to_pfn(sg_page(s.sgp)); | |
2354 | } | |
2355 | ||
2356 | return s; | |
2357 | } | |
2358 | ||
2359 | /** | |
2360 | * __sg_next - return the next scatterlist entry in a list | |
2361 | * @sg: The current sg entry | |
2362 | * | |
2363 | * Description: | |
2364 | * If the entry is the last, return NULL; otherwise, step to the next | |
2365 | * element in the array (@sg@+1). If that's a chain pointer, follow it; | |
2366 | * otherwise just return the pointer to the current element. | |
2367 | **/ | |
2368 | static inline struct scatterlist *__sg_next(struct scatterlist *sg) | |
2369 | { | |
2370 | #ifdef CONFIG_DEBUG_SG | |
2371 | BUG_ON(sg->sg_magic != SG_MAGIC); | |
2372 | #endif | |
2373 | return sg_is_last(sg) ? NULL : | |
2374 | likely(!sg_is_chain(++sg)) ? sg : | |
2375 | sg_chain_ptr(sg); | |
2376 | } | |
2377 | ||
2378 | /** | |
2379 | * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table | |
2380 | * @__dmap: DMA address (output) | |
2381 | * @__iter: 'struct sgt_iter' (iterator state, internal) | |
2382 | * @__sgt: sg_table to iterate over (input) | |
2383 | */ | |
2384 | #define for_each_sgt_dma(__dmap, __iter, __sgt) \ | |
2385 | for ((__iter) = __sgt_iter((__sgt)->sgl, true); \ | |
2386 | ((__dmap) = (__iter).dma + (__iter).curr); \ | |
2387 | (((__iter).curr += PAGE_SIZE) < (__iter).max) || \ | |
2388 | ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0)) | |
2389 | ||
2390 | /** | |
2391 | * for_each_sgt_page - iterate over the pages of the given sg_table | |
2392 | * @__pp: page pointer (output) | |
2393 | * @__iter: 'struct sgt_iter' (iterator state, internal) | |
2394 | * @__sgt: sg_table to iterate over (input) | |
2395 | */ | |
2396 | #define for_each_sgt_page(__pp, __iter, __sgt) \ | |
2397 | for ((__iter) = __sgt_iter((__sgt)->sgl, false); \ | |
2398 | ((__pp) = (__iter).pfn == 0 ? NULL : \ | |
2399 | pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \ | |
2400 | (((__iter).curr += PAGE_SIZE) < (__iter).max) || \ | |
2401 | ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0)) | |
2402 | ||
2403 | /* | |
2404 | * A command that requires special handling by the command parser. | |
2405 | */ | |
2406 | struct drm_i915_cmd_descriptor { | |
2407 | /* | |
2408 | * Flags describing how the command parser processes the command. | |
2409 | * | |
2410 | * CMD_DESC_FIXED: The command has a fixed length if this is set, | |
2411 | * a length mask if not set | |
2412 | * CMD_DESC_SKIP: The command is allowed but does not follow the | |
2413 | * standard length encoding for the opcode range in | |
2414 | * which it falls | |
2415 | * CMD_DESC_REJECT: The command is never allowed | |
2416 | * CMD_DESC_REGISTER: The command should be checked against the | |
2417 | * register whitelist for the appropriate ring | |
2418 | * CMD_DESC_MASTER: The command is allowed if the submitting process | |
2419 | * is the DRM master | |
2420 | */ | |
2421 | u32 flags; | |
2422 | #define CMD_DESC_FIXED (1<<0) | |
2423 | #define CMD_DESC_SKIP (1<<1) | |
2424 | #define CMD_DESC_REJECT (1<<2) | |
2425 | #define CMD_DESC_REGISTER (1<<3) | |
2426 | #define CMD_DESC_BITMASK (1<<4) | |
2427 | #define CMD_DESC_MASTER (1<<5) | |
2428 | ||
2429 | /* | |
2430 | * The command's unique identification bits and the bitmask to get them. | |
2431 | * This isn't strictly the opcode field as defined in the spec and may | |
2432 | * also include type, subtype, and/or subop fields. | |
2433 | */ | |
2434 | struct { | |
2435 | u32 value; | |
2436 | u32 mask; | |
2437 | } cmd; | |
2438 | ||
2439 | /* | |
2440 | * The command's length. The command is either fixed length (i.e. does | |
2441 | * not include a length field) or has a length field mask. The flag | |
2442 | * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has | |
2443 | * a length mask. All command entries in a command table must include | |
2444 | * length information. | |
2445 | */ | |
2446 | union { | |
2447 | u32 fixed; | |
2448 | u32 mask; | |
2449 | } length; | |
2450 | ||
2451 | /* | |
2452 | * Describes where to find a register address in the command to check | |
2453 | * against the ring's register whitelist. Only valid if flags has the | |
2454 | * CMD_DESC_REGISTER bit set. | |
2455 | * | |
2456 | * A non-zero step value implies that the command may access multiple | |
2457 | * registers in sequence (e.g. LRI), in that case step gives the | |
2458 | * distance in dwords between individual offset fields. | |
2459 | */ | |
2460 | struct { | |
2461 | u32 offset; | |
2462 | u32 mask; | |
2463 | u32 step; | |
2464 | } reg; | |
2465 | ||
2466 | #define MAX_CMD_DESC_BITMASKS 3 | |
2467 | /* | |
2468 | * Describes command checks where a particular dword is masked and | |
2469 | * compared against an expected value. If the command does not match | |
2470 | * the expected value, the parser rejects it. Only valid if flags has | |
2471 | * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero | |
2472 | * are valid. | |
2473 | * | |
2474 | * If the check specifies a non-zero condition_mask then the parser | |
2475 | * only performs the check when the bits specified by condition_mask | |
2476 | * are non-zero. | |
2477 | */ | |
2478 | struct { | |
2479 | u32 offset; | |
2480 | u32 mask; | |
2481 | u32 expected; | |
2482 | u32 condition_offset; | |
2483 | u32 condition_mask; | |
2484 | } bits[MAX_CMD_DESC_BITMASKS]; | |
2485 | }; | |
2486 | ||
2487 | /* | |
2488 | * A table of commands requiring special handling by the command parser. | |
2489 | * | |
2490 | * Each engine has an array of tables. Each table consists of an array of | |
2491 | * command descriptors, which must be sorted with command opcodes in | |
2492 | * ascending order. | |
2493 | */ | |
2494 | struct drm_i915_cmd_table { | |
2495 | const struct drm_i915_cmd_descriptor *table; | |
2496 | int count; | |
2497 | }; | |
2498 | ||
2499 | /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ | |
2500 | #define __I915__(p) ({ \ | |
2501 | struct drm_i915_private *__p; \ | |
2502 | if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ | |
2503 | __p = (struct drm_i915_private *)p; \ | |
2504 | else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ | |
2505 | __p = to_i915((struct drm_device *)p); \ | |
2506 | else \ | |
2507 | BUILD_BUG(); \ | |
2508 | __p; \ | |
2509 | }) | |
2510 | #define INTEL_INFO(p) (&__I915__(p)->info) | |
2511 | #define INTEL_GEN(p) (INTEL_INFO(p)->gen) | |
2512 | #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) | |
2513 | ||
2514 | #define REVID_FOREVER 0xff | |
2515 | #define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision) | |
2516 | ||
2517 | #define GEN_FOREVER (0) | |
2518 | /* | |
2519 | * Returns true if Gen is in inclusive range [Start, End]. | |
2520 | * | |
2521 | * Use GEN_FOREVER for unbound start and or end. | |
2522 | */ | |
2523 | #define IS_GEN(p, s, e) ({ \ | |
2524 | unsigned int __s = (s), __e = (e); \ | |
2525 | BUILD_BUG_ON(!__builtin_constant_p(s)); \ | |
2526 | BUILD_BUG_ON(!__builtin_constant_p(e)); \ | |
2527 | if ((__s) != GEN_FOREVER) \ | |
2528 | __s = (s) - 1; \ | |
2529 | if ((__e) == GEN_FOREVER) \ | |
2530 | __e = BITS_PER_LONG - 1; \ | |
2531 | else \ | |
2532 | __e = (e) - 1; \ | |
2533 | !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \ | |
2534 | }) | |
2535 | ||
2536 | /* | |
2537 | * Return true if revision is in range [since,until] inclusive. | |
2538 | * | |
2539 | * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. | |
2540 | */ | |
2541 | #define IS_REVID(p, since, until) \ | |
2542 | (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) | |
2543 | ||
2544 | #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) | |
2545 | #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) | |
2546 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) | |
2547 | #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) | |
2548 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) | |
2549 | #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) | |
2550 | #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) | |
2551 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) | |
2552 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
2553 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
2554 | #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) | |
2555 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) | |
2556 | #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) | |
2557 | #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) | |
2558 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) | |
2559 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
2560 | #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) | |
2561 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) | |
2562 | #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ | |
2563 | INTEL_DEVID(dev) == 0x0152 || \ | |
2564 | INTEL_DEVID(dev) == 0x015a) | |
2565 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) | |
2566 | #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview) | |
2567 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) | |
2568 | #define IS_BROADWELL(dev) (INTEL_INFO(dev)->is_broadwell) | |
2569 | #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) | |
2570 | #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton) | |
2571 | #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake) | |
2572 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) | |
2573 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ | |
2574 | (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) | |
2575 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ | |
2576 | ((INTEL_DEVID(dev) & 0xf) == 0x6 || \ | |
2577 | (INTEL_DEVID(dev) & 0xf) == 0xb || \ | |
2578 | (INTEL_DEVID(dev) & 0xf) == 0xe)) | |
2579 | /* ULX machines are also considered ULT. */ | |
2580 | #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \ | |
2581 | (INTEL_DEVID(dev) & 0xf) == 0xe) | |
2582 | #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ | |
2583 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
2584 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ | |
2585 | (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) | |
2586 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ | |
2587 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
2588 | /* ULX machines are also considered ULT. */ | |
2589 | #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ | |
2590 | INTEL_DEVID(dev) == 0x0A1E) | |
2591 | #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \ | |
2592 | INTEL_DEVID(dev) == 0x1913 || \ | |
2593 | INTEL_DEVID(dev) == 0x1916 || \ | |
2594 | INTEL_DEVID(dev) == 0x1921 || \ | |
2595 | INTEL_DEVID(dev) == 0x1926) | |
2596 | #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \ | |
2597 | INTEL_DEVID(dev) == 0x1915 || \ | |
2598 | INTEL_DEVID(dev) == 0x191E) | |
2599 | #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \ | |
2600 | INTEL_DEVID(dev) == 0x5913 || \ | |
2601 | INTEL_DEVID(dev) == 0x5916 || \ | |
2602 | INTEL_DEVID(dev) == 0x5921 || \ | |
2603 | INTEL_DEVID(dev) == 0x5926) | |
2604 | #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \ | |
2605 | INTEL_DEVID(dev) == 0x5915 || \ | |
2606 | INTEL_DEVID(dev) == 0x591E) | |
2607 | #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \ | |
2608 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
2609 | #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \ | |
2610 | (INTEL_DEVID(dev) & 0x00F0) == 0x0030) | |
2611 | ||
2612 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) | |
2613 | ||
2614 | #define SKL_REVID_A0 0x0 | |
2615 | #define SKL_REVID_B0 0x1 | |
2616 | #define SKL_REVID_C0 0x2 | |
2617 | #define SKL_REVID_D0 0x3 | |
2618 | #define SKL_REVID_E0 0x4 | |
2619 | #define SKL_REVID_F0 0x5 | |
2620 | #define SKL_REVID_G0 0x6 | |
2621 | #define SKL_REVID_H0 0x7 | |
2622 | ||
2623 | #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) | |
2624 | ||
2625 | #define BXT_REVID_A0 0x0 | |
2626 | #define BXT_REVID_A1 0x1 | |
2627 | #define BXT_REVID_B0 0x3 | |
2628 | #define BXT_REVID_C0 0x9 | |
2629 | ||
2630 | #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until)) | |
2631 | ||
2632 | #define KBL_REVID_A0 0x0 | |
2633 | #define KBL_REVID_B0 0x1 | |
2634 | #define KBL_REVID_C0 0x2 | |
2635 | #define KBL_REVID_D0 0x3 | |
2636 | #define KBL_REVID_E0 0x4 | |
2637 | ||
2638 | #define IS_KBL_REVID(p, since, until) \ | |
2639 | (IS_KABYLAKE(p) && IS_REVID(p, since, until)) | |
2640 | ||
2641 | /* | |
2642 | * The genX designation typically refers to the render engine, so render | |
2643 | * capability related checks should use IS_GEN, while display and other checks | |
2644 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
2645 | * chips, etc.). | |
2646 | */ | |
2647 | #define IS_GEN2(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(1))) | |
2648 | #define IS_GEN3(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(2))) | |
2649 | #define IS_GEN4(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(3))) | |
2650 | #define IS_GEN5(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(4))) | |
2651 | #define IS_GEN6(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(5))) | |
2652 | #define IS_GEN7(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(6))) | |
2653 | #define IS_GEN8(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(7))) | |
2654 | #define IS_GEN9(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(8))) | |
2655 | ||
2656 | #define ENGINE_MASK(id) BIT(id) | |
2657 | #define RENDER_RING ENGINE_MASK(RCS) | |
2658 | #define BSD_RING ENGINE_MASK(VCS) | |
2659 | #define BLT_RING ENGINE_MASK(BCS) | |
2660 | #define VEBOX_RING ENGINE_MASK(VECS) | |
2661 | #define BSD2_RING ENGINE_MASK(VCS2) | |
2662 | #define ALL_ENGINES (~0) | |
2663 | ||
2664 | #define HAS_ENGINE(dev_priv, id) \ | |
2665 | (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id))) | |
2666 | ||
2667 | #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS) | |
2668 | #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2) | |
2669 | #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS) | |
2670 | #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS) | |
2671 | ||
2672 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) | |
2673 | #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop) | |
2674 | #define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED)) | |
2675 | #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ | |
2676 | HAS_EDRAM(dev)) | |
2677 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) | |
2678 | ||
2679 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) | |
2680 | #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8) | |
2681 | #define USES_PPGTT(dev) (i915.enable_ppgtt) | |
2682 | #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2) | |
2683 | #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3) | |
2684 | ||
2685 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) | |
2686 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) | |
2687 | ||
2688 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ | |
2689 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) | |
2690 | ||
2691 | /* WaRsDisableCoarsePowerGating:skl,bxt */ | |
2692 | #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ | |
2693 | (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \ | |
2694 | IS_SKL_GT3(dev_priv) || \ | |
2695 | IS_SKL_GT4(dev_priv)) | |
2696 | ||
2697 | /* | |
2698 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts | |
2699 | * even when in MSI mode. This results in spurious interrupt warnings if the | |
2700 | * legacy irq no. is shared with another device. The kernel then disables that | |
2701 | * interrupt source and so prevents the other device from working properly. | |
2702 | */ | |
2703 | #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
2704 | #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
2705 | ||
2706 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte | |
2707 | * rows, which changed the alignment requirements and fence programming. | |
2708 | */ | |
2709 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
2710 | IS_I915GM(dev))) | |
2711 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) | |
2712 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
2713 | ||
2714 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
2715 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
2716 | #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) | |
2717 | ||
2718 | #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) | |
2719 | ||
2720 | #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ | |
2721 | INTEL_INFO(dev)->gen >= 9) | |
2722 | ||
2723 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) | |
2724 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) | |
2725 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ | |
2726 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \ | |
2727 | IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) | |
2728 | #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ | |
2729 | IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \ | |
2730 | IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \ | |
2731 | IS_KABYLAKE(dev) || IS_BROXTON(dev)) | |
2732 | #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) | |
2733 | #define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) | |
2734 | ||
2735 | #define HAS_CSR(dev) (IS_GEN9(dev)) | |
2736 | ||
2737 | /* | |
2738 | * For now, anything with a GuC requires uCode loading, and then supports | |
2739 | * command submission once loaded. But these are logically independent | |
2740 | * properties, so we have separate macros to test them. | |
2741 | */ | |
2742 | #define HAS_GUC(dev) (IS_GEN9(dev)) | |
2743 | #define HAS_GUC_UCODE(dev) (HAS_GUC(dev)) | |
2744 | #define HAS_GUC_SCHED(dev) (HAS_GUC(dev)) | |
2745 | ||
2746 | #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \ | |
2747 | INTEL_INFO(dev)->gen >= 8) | |
2748 | ||
2749 | #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \ | |
2750 | !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \ | |
2751 | !IS_BROXTON(dev)) | |
2752 | ||
2753 | #define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu) | |
2754 | ||
2755 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 | |
2756 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
2757 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
2758 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
2759 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
2760 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
2761 | #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 | |
2762 | #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 | |
2763 | #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200 | |
2764 | #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 | |
2765 | #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 | |
2766 | #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ | |
2767 | ||
2768 | #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) | |
2769 | #define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP) | |
2770 | #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT) | |
2771 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) | |
2772 | #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) | |
2773 | #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) | |
2774 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) | |
2775 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
2776 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) | |
2777 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) | |
2778 | ||
2779 | #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \ | |
2780 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) | |
2781 | ||
2782 | /* DPF == dynamic parity feature */ | |
2783 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
2784 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) | |
2785 | ||
2786 | #define GT_FREQUENCY_MULTIPLIER 50 | |
2787 | #define GEN9_FREQ_SCALER 3 | |
2788 | ||
2789 | #include "i915_trace.h" | |
2790 | ||
2791 | static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) | |
2792 | { | |
2793 | #ifdef CONFIG_INTEL_IOMMU | |
2794 | if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped) | |
2795 | return true; | |
2796 | #endif | |
2797 | return false; | |
2798 | } | |
2799 | ||
2800 | extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state); | |
2801 | extern int i915_resume_switcheroo(struct drm_device *dev); | |
2802 | ||
2803 | int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, | |
2804 | int enable_ppgtt); | |
2805 | ||
2806 | bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value); | |
2807 | ||
2808 | /* i915_drv.c */ | |
2809 | void __printf(3, 4) | |
2810 | __i915_printk(struct drm_i915_private *dev_priv, const char *level, | |
2811 | const char *fmt, ...); | |
2812 | ||
2813 | #define i915_report_error(dev_priv, fmt, ...) \ | |
2814 | __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__) | |
2815 | ||
2816 | #ifdef CONFIG_COMPAT | |
2817 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, | |
2818 | unsigned long arg); | |
2819 | #endif | |
2820 | extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask); | |
2821 | extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv); | |
2822 | extern int i915_reset(struct drm_i915_private *dev_priv); | |
2823 | extern int intel_guc_reset(struct drm_i915_private *dev_priv); | |
2824 | extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine); | |
2825 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); | |
2826 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
2827 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
2828 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
2829 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); | |
2830 | ||
2831 | /* intel_hotplug.c */ | |
2832 | void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, | |
2833 | u32 pin_mask, u32 long_mask); | |
2834 | void intel_hpd_init(struct drm_i915_private *dev_priv); | |
2835 | void intel_hpd_init_work(struct drm_i915_private *dev_priv); | |
2836 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); | |
2837 | bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port); | |
2838 | bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin); | |
2839 | void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin); | |
2840 | ||
2841 | /* i915_irq.c */ | |
2842 | static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv) | |
2843 | { | |
2844 | unsigned long delay; | |
2845 | ||
2846 | if (unlikely(!i915.enable_hangcheck)) | |
2847 | return; | |
2848 | ||
2849 | /* Don't continually defer the hangcheck so that it is always run at | |
2850 | * least once after work has been scheduled on any ring. Otherwise, | |
2851 | * we will ignore a hung ring if a second ring is kept busy. | |
2852 | */ | |
2853 | ||
2854 | delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES); | |
2855 | queue_delayed_work(system_long_wq, | |
2856 | &dev_priv->gpu_error.hangcheck_work, delay); | |
2857 | } | |
2858 | ||
2859 | __printf(3, 4) | |
2860 | void i915_handle_error(struct drm_i915_private *dev_priv, | |
2861 | u32 engine_mask, | |
2862 | const char *fmt, ...); | |
2863 | ||
2864 | extern void intel_irq_init(struct drm_i915_private *dev_priv); | |
2865 | int intel_irq_install(struct drm_i915_private *dev_priv); | |
2866 | void intel_irq_uninstall(struct drm_i915_private *dev_priv); | |
2867 | ||
2868 | extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv); | |
2869 | extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, | |
2870 | bool restore_forcewake); | |
2871 | extern void intel_uncore_init(struct drm_i915_private *dev_priv); | |
2872 | extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv); | |
2873 | extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv); | |
2874 | extern void intel_uncore_fini(struct drm_i915_private *dev_priv); | |
2875 | extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv, | |
2876 | bool restore); | |
2877 | const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id); | |
2878 | void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, | |
2879 | enum forcewake_domains domains); | |
2880 | void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, | |
2881 | enum forcewake_domains domains); | |
2882 | /* Like above but the caller must manage the uncore.lock itself. | |
2883 | * Must be used with I915_READ_FW and friends. | |
2884 | */ | |
2885 | void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, | |
2886 | enum forcewake_domains domains); | |
2887 | void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, | |
2888 | enum forcewake_domains domains); | |
2889 | u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv); | |
2890 | ||
2891 | void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); | |
2892 | ||
2893 | int intel_wait_for_register(struct drm_i915_private *dev_priv, | |
2894 | i915_reg_t reg, | |
2895 | const u32 mask, | |
2896 | const u32 value, | |
2897 | const unsigned long timeout_ms); | |
2898 | int intel_wait_for_register_fw(struct drm_i915_private *dev_priv, | |
2899 | i915_reg_t reg, | |
2900 | const u32 mask, | |
2901 | const u32 value, | |
2902 | const unsigned long timeout_ms); | |
2903 | ||
2904 | static inline bool intel_gvt_active(struct drm_i915_private *dev_priv) | |
2905 | { | |
2906 | return dev_priv->gvt.initialized; | |
2907 | } | |
2908 | ||
2909 | static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv) | |
2910 | { | |
2911 | return dev_priv->vgpu.active; | |
2912 | } | |
2913 | ||
2914 | void | |
2915 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
2916 | u32 status_mask); | |
2917 | ||
2918 | void | |
2919 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
2920 | u32 status_mask); | |
2921 | ||
2922 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); | |
2923 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); | |
2924 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, | |
2925 | uint32_t mask, | |
2926 | uint32_t bits); | |
2927 | void ilk_update_display_irq(struct drm_i915_private *dev_priv, | |
2928 | uint32_t interrupt_mask, | |
2929 | uint32_t enabled_irq_mask); | |
2930 | static inline void | |
2931 | ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
2932 | { | |
2933 | ilk_update_display_irq(dev_priv, bits, bits); | |
2934 | } | |
2935 | static inline void | |
2936 | ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
2937 | { | |
2938 | ilk_update_display_irq(dev_priv, bits, 0); | |
2939 | } | |
2940 | void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, | |
2941 | enum pipe pipe, | |
2942 | uint32_t interrupt_mask, | |
2943 | uint32_t enabled_irq_mask); | |
2944 | static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv, | |
2945 | enum pipe pipe, uint32_t bits) | |
2946 | { | |
2947 | bdw_update_pipe_irq(dev_priv, pipe, bits, bits); | |
2948 | } | |
2949 | static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv, | |
2950 | enum pipe pipe, uint32_t bits) | |
2951 | { | |
2952 | bdw_update_pipe_irq(dev_priv, pipe, bits, 0); | |
2953 | } | |
2954 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, | |
2955 | uint32_t interrupt_mask, | |
2956 | uint32_t enabled_irq_mask); | |
2957 | static inline void | |
2958 | ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
2959 | { | |
2960 | ibx_display_interrupt_update(dev_priv, bits, bits); | |
2961 | } | |
2962 | static inline void | |
2963 | ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
2964 | { | |
2965 | ibx_display_interrupt_update(dev_priv, bits, 0); | |
2966 | } | |
2967 | ||
2968 | /* i915_gem.c */ | |
2969 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
2970 | struct drm_file *file_priv); | |
2971 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
2972 | struct drm_file *file_priv); | |
2973 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
2974 | struct drm_file *file_priv); | |
2975 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
2976 | struct drm_file *file_priv); | |
2977 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
2978 | struct drm_file *file_priv); | |
2979 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
2980 | struct drm_file *file_priv); | |
2981 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
2982 | struct drm_file *file_priv); | |
2983 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
2984 | struct drm_file *file_priv); | |
2985 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
2986 | struct drm_file *file_priv); | |
2987 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
2988 | struct drm_file *file_priv); | |
2989 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, | |
2990 | struct drm_file *file); | |
2991 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
2992 | struct drm_file *file); | |
2993 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
2994 | struct drm_file *file_priv); | |
2995 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
2996 | struct drm_file *file_priv); | |
2997 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
2998 | struct drm_file *file_priv); | |
2999 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
3000 | struct drm_file *file_priv); | |
3001 | void i915_gem_init_userptr(struct drm_i915_private *dev_priv); | |
3002 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
3003 | struct drm_file *file); | |
3004 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
3005 | struct drm_file *file_priv); | |
3006 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, | |
3007 | struct drm_file *file_priv); | |
3008 | void i915_gem_load_init(struct drm_device *dev); | |
3009 | void i915_gem_load_cleanup(struct drm_device *dev); | |
3010 | void i915_gem_load_init_fences(struct drm_i915_private *dev_priv); | |
3011 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv); | |
3012 | ||
3013 | void *i915_gem_object_alloc(struct drm_device *dev); | |
3014 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
3015 | void i915_gem_object_init(struct drm_i915_gem_object *obj, | |
3016 | const struct drm_i915_gem_object_ops *ops); | |
3017 | struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev, | |
3018 | size_t size); | |
3019 | struct drm_i915_gem_object *i915_gem_object_create_from_data( | |
3020 | struct drm_device *dev, const void *data, size_t size); | |
3021 | void i915_gem_free_object(struct drm_gem_object *obj); | |
3022 | void i915_gem_vma_destroy(struct i915_vma *vma); | |
3023 | ||
3024 | /* Flags used by pin/bind&friends. */ | |
3025 | #define PIN_MAPPABLE (1<<0) | |
3026 | #define PIN_NONBLOCK (1<<1) | |
3027 | #define PIN_GLOBAL (1<<2) | |
3028 | #define PIN_OFFSET_BIAS (1<<3) | |
3029 | #define PIN_USER (1<<4) | |
3030 | #define PIN_UPDATE (1<<5) | |
3031 | #define PIN_ZONE_4G (1<<6) | |
3032 | #define PIN_HIGH (1<<7) | |
3033 | #define PIN_OFFSET_FIXED (1<<8) | |
3034 | #define PIN_OFFSET_MASK (~4095) | |
3035 | int __must_check | |
3036 | i915_gem_object_pin(struct drm_i915_gem_object *obj, | |
3037 | struct i915_address_space *vm, | |
3038 | uint32_t alignment, | |
3039 | uint64_t flags); | |
3040 | int __must_check | |
3041 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, | |
3042 | const struct i915_ggtt_view *view, | |
3043 | uint32_t alignment, | |
3044 | uint64_t flags); | |
3045 | ||
3046 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
3047 | u32 flags); | |
3048 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma); | |
3049 | int __must_check i915_vma_unbind(struct i915_vma *vma); | |
3050 | /* | |
3051 | * BEWARE: Do not use the function below unless you can _absolutely_ | |
3052 | * _guarantee_ VMA in question is _not in use_ anywhere. | |
3053 | */ | |
3054 | int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma); | |
3055 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); | |
3056 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); | |
3057 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); | |
3058 | ||
3059 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
3060 | int *needs_clflush); | |
3061 | ||
3062 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); | |
3063 | ||
3064 | static inline int __sg_page_count(struct scatterlist *sg) | |
3065 | { | |
3066 | return sg->length >> PAGE_SHIFT; | |
3067 | } | |
3068 | ||
3069 | struct page * | |
3070 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n); | |
3071 | ||
3072 | static inline dma_addr_t | |
3073 | i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, int n) | |
3074 | { | |
3075 | if (n < obj->get_page.last) { | |
3076 | obj->get_page.sg = obj->pages->sgl; | |
3077 | obj->get_page.last = 0; | |
3078 | } | |
3079 | ||
3080 | while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) { | |
3081 | obj->get_page.last += __sg_page_count(obj->get_page.sg++); | |
3082 | if (unlikely(sg_is_chain(obj->get_page.sg))) | |
3083 | obj->get_page.sg = sg_chain_ptr(obj->get_page.sg); | |
3084 | } | |
3085 | ||
3086 | return sg_dma_address(obj->get_page.sg) + ((n - obj->get_page.last) << PAGE_SHIFT); | |
3087 | } | |
3088 | ||
3089 | static inline struct page * | |
3090 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) | |
3091 | { | |
3092 | if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT)) | |
3093 | return NULL; | |
3094 | ||
3095 | if (n < obj->get_page.last) { | |
3096 | obj->get_page.sg = obj->pages->sgl; | |
3097 | obj->get_page.last = 0; | |
3098 | } | |
3099 | ||
3100 | while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) { | |
3101 | obj->get_page.last += __sg_page_count(obj->get_page.sg++); | |
3102 | if (unlikely(sg_is_chain(obj->get_page.sg))) | |
3103 | obj->get_page.sg = sg_chain_ptr(obj->get_page.sg); | |
3104 | } | |
3105 | ||
3106 | return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last); | |
3107 | } | |
3108 | ||
3109 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) | |
3110 | { | |
3111 | BUG_ON(obj->pages == NULL); | |
3112 | obj->pages_pin_count++; | |
3113 | } | |
3114 | ||
3115 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
3116 | { | |
3117 | BUG_ON(obj->pages_pin_count == 0); | |
3118 | obj->pages_pin_count--; | |
3119 | } | |
3120 | ||
3121 | /** | |
3122 | * i915_gem_object_pin_map - return a contiguous mapping of the entire object | |
3123 | * @obj - the object to map into kernel address space | |
3124 | * | |
3125 | * Calls i915_gem_object_pin_pages() to prevent reaping of the object's | |
3126 | * pages and then returns a contiguous mapping of the backing storage into | |
3127 | * the kernel address space. | |
3128 | * | |
3129 | * The caller must hold the struct_mutex, and is responsible for calling | |
3130 | * i915_gem_object_unpin_map() when the mapping is no longer required. | |
3131 | * | |
3132 | * Returns the pointer through which to access the mapped object, or an | |
3133 | * ERR_PTR() on error. | |
3134 | */ | |
3135 | void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj); | |
3136 | ||
3137 | /** | |
3138 | * i915_gem_object_unpin_map - releases an earlier mapping | |
3139 | * @obj - the object to unmap | |
3140 | * | |
3141 | * After pinning the object and mapping its pages, once you are finished | |
3142 | * with your access, call i915_gem_object_unpin_map() to release the pin | |
3143 | * upon the mapping. Once the pin count reaches zero, that mapping may be | |
3144 | * removed. | |
3145 | * | |
3146 | * The caller must hold the struct_mutex. | |
3147 | */ | |
3148 | static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj) | |
3149 | { | |
3150 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
3151 | i915_gem_object_unpin_pages(obj); | |
3152 | } | |
3153 | ||
3154 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); | |
3155 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
3156 | struct drm_i915_gem_request *to); | |
3157 | void i915_vma_move_to_active(struct i915_vma *vma, | |
3158 | struct drm_i915_gem_request *req); | |
3159 | int i915_gem_dumb_create(struct drm_file *file_priv, | |
3160 | struct drm_device *dev, | |
3161 | struct drm_mode_create_dumb *args); | |
3162 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, | |
3163 | uint32_t handle, uint64_t *offset); | |
3164 | ||
3165 | void i915_gem_track_fb(struct drm_i915_gem_object *old, | |
3166 | struct drm_i915_gem_object *new, | |
3167 | unsigned frontbuffer_bits); | |
3168 | ||
3169 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); | |
3170 | ||
3171 | struct drm_i915_gem_request * | |
3172 | i915_gem_find_active_request(struct intel_engine_cs *engine); | |
3173 | ||
3174 | void i915_gem_retire_requests(struct drm_i915_private *dev_priv); | |
3175 | void i915_gem_retire_requests_ring(struct intel_engine_cs *engine); | |
3176 | ||
3177 | static inline u32 i915_reset_counter(struct i915_gpu_error *error) | |
3178 | { | |
3179 | return atomic_read(&error->reset_counter); | |
3180 | } | |
3181 | ||
3182 | static inline bool __i915_reset_in_progress(u32 reset) | |
3183 | { | |
3184 | return unlikely(reset & I915_RESET_IN_PROGRESS_FLAG); | |
3185 | } | |
3186 | ||
3187 | static inline bool __i915_reset_in_progress_or_wedged(u32 reset) | |
3188 | { | |
3189 | return unlikely(reset & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); | |
3190 | } | |
3191 | ||
3192 | static inline bool __i915_terminally_wedged(u32 reset) | |
3193 | { | |
3194 | return unlikely(reset & I915_WEDGED); | |
3195 | } | |
3196 | ||
3197 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) | |
3198 | { | |
3199 | return __i915_reset_in_progress(i915_reset_counter(error)); | |
3200 | } | |
3201 | ||
3202 | static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error) | |
3203 | { | |
3204 | return __i915_reset_in_progress_or_wedged(i915_reset_counter(error)); | |
3205 | } | |
3206 | ||
3207 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) | |
3208 | { | |
3209 | return __i915_terminally_wedged(i915_reset_counter(error)); | |
3210 | } | |
3211 | ||
3212 | static inline u32 i915_reset_count(struct i915_gpu_error *error) | |
3213 | { | |
3214 | return ((i915_reset_counter(error) & ~I915_WEDGED) + 1) / 2; | |
3215 | } | |
3216 | ||
3217 | void i915_gem_reset(struct drm_device *dev); | |
3218 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); | |
3219 | int __must_check i915_gem_init(struct drm_device *dev); | |
3220 | int __must_check i915_gem_init_hw(struct drm_device *dev); | |
3221 | void i915_gem_init_swizzling(struct drm_device *dev); | |
3222 | void i915_gem_cleanup_engines(struct drm_device *dev); | |
3223 | int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv); | |
3224 | int __must_check i915_gem_suspend(struct drm_device *dev); | |
3225 | void i915_gem_resume(struct drm_device *dev); | |
3226 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); | |
3227 | int __must_check | |
3228 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
3229 | bool readonly); | |
3230 | int __must_check | |
3231 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, | |
3232 | bool write); | |
3233 | int __must_check | |
3234 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); | |
3235 | int __must_check | |
3236 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, | |
3237 | u32 alignment, | |
3238 | const struct i915_ggtt_view *view); | |
3239 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, | |
3240 | const struct i915_ggtt_view *view); | |
3241 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
3242 | int align); | |
3243 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); | |
3244 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); | |
3245 | ||
3246 | uint32_t | |
3247 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); | |
3248 | uint32_t | |
3249 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
3250 | int tiling_mode, bool fenced); | |
3251 | ||
3252 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, | |
3253 | enum i915_cache_level cache_level); | |
3254 | ||
3255 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, | |
3256 | struct dma_buf *dma_buf); | |
3257 | ||
3258 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
3259 | struct drm_gem_object *gem_obj, int flags); | |
3260 | ||
3261 | u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, | |
3262 | const struct i915_ggtt_view *view); | |
3263 | u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
3264 | struct i915_address_space *vm); | |
3265 | static inline u64 | |
3266 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o) | |
3267 | { | |
3268 | return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal); | |
3269 | } | |
3270 | ||
3271 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, | |
3272 | const struct i915_ggtt_view *view); | |
3273 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
3274 | struct i915_address_space *vm); | |
3275 | ||
3276 | struct i915_vma * | |
3277 | i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, | |
3278 | struct i915_address_space *vm); | |
3279 | struct i915_vma * | |
3280 | i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, | |
3281 | const struct i915_ggtt_view *view); | |
3282 | ||
3283 | struct i915_vma * | |
3284 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
3285 | struct i915_address_space *vm); | |
3286 | struct i915_vma * | |
3287 | i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, | |
3288 | const struct i915_ggtt_view *view); | |
3289 | ||
3290 | static inline struct i915_vma * | |
3291 | i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) | |
3292 | { | |
3293 | return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal); | |
3294 | } | |
3295 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj); | |
3296 | ||
3297 | /* Some GGTT VM helpers */ | |
3298 | static inline struct i915_hw_ppgtt * | |
3299 | i915_vm_to_ppgtt(struct i915_address_space *vm) | |
3300 | { | |
3301 | return container_of(vm, struct i915_hw_ppgtt, base); | |
3302 | } | |
3303 | ||
3304 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) | |
3305 | { | |
3306 | return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal); | |
3307 | } | |
3308 | ||
3309 | unsigned long | |
3310 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj); | |
3311 | ||
3312 | static inline int __must_check | |
3313 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, | |
3314 | uint32_t alignment, | |
3315 | unsigned flags) | |
3316 | { | |
3317 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); | |
3318 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
3319 | ||
3320 | return i915_gem_object_pin(obj, &ggtt->base, | |
3321 | alignment, flags | PIN_GLOBAL); | |
3322 | } | |
3323 | ||
3324 | void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, | |
3325 | const struct i915_ggtt_view *view); | |
3326 | static inline void | |
3327 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) | |
3328 | { | |
3329 | i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal); | |
3330 | } | |
3331 | ||
3332 | /* i915_gem_fence.c */ | |
3333 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); | |
3334 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); | |
3335 | ||
3336 | bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); | |
3337 | void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); | |
3338 | ||
3339 | void i915_gem_restore_fences(struct drm_device *dev); | |
3340 | ||
3341 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); | |
3342 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
3343 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
3344 | ||
3345 | /* i915_gem_context.c */ | |
3346 | int __must_check i915_gem_context_init(struct drm_device *dev); | |
3347 | void i915_gem_context_lost(struct drm_i915_private *dev_priv); | |
3348 | void i915_gem_context_fini(struct drm_device *dev); | |
3349 | void i915_gem_context_reset(struct drm_device *dev); | |
3350 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); | |
3351 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); | |
3352 | int i915_switch_context(struct drm_i915_gem_request *req); | |
3353 | int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv); | |
3354 | void i915_gem_context_free(struct kref *ctx_ref); | |
3355 | struct drm_i915_gem_object * | |
3356 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); | |
3357 | struct i915_gem_context * | |
3358 | i915_gem_context_create_gvt(struct drm_device *dev); | |
3359 | ||
3360 | static inline struct i915_gem_context * | |
3361 | i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id) | |
3362 | { | |
3363 | struct i915_gem_context *ctx; | |
3364 | ||
3365 | lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex); | |
3366 | ||
3367 | ctx = idr_find(&file_priv->context_idr, id); | |
3368 | if (!ctx) | |
3369 | return ERR_PTR(-ENOENT); | |
3370 | ||
3371 | return ctx; | |
3372 | } | |
3373 | ||
3374 | static inline struct i915_gem_context * | |
3375 | i915_gem_context_get(struct i915_gem_context *ctx) | |
3376 | { | |
3377 | kref_get(&ctx->ref); | |
3378 | return ctx; | |
3379 | } | |
3380 | ||
3381 | static inline void i915_gem_context_put(struct i915_gem_context *ctx) | |
3382 | { | |
3383 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); | |
3384 | kref_put(&ctx->ref, i915_gem_context_free); | |
3385 | } | |
3386 | ||
3387 | static inline bool i915_gem_context_is_default(const struct i915_gem_context *c) | |
3388 | { | |
3389 | return c->user_handle == DEFAULT_CONTEXT_HANDLE; | |
3390 | } | |
3391 | ||
3392 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, | |
3393 | struct drm_file *file); | |
3394 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
3395 | struct drm_file *file); | |
3396 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, | |
3397 | struct drm_file *file_priv); | |
3398 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
3399 | struct drm_file *file_priv); | |
3400 | int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data, | |
3401 | struct drm_file *file); | |
3402 | ||
3403 | /* i915_gem_evict.c */ | |
3404 | int __must_check i915_gem_evict_something(struct drm_device *dev, | |
3405 | struct i915_address_space *vm, | |
3406 | int min_size, | |
3407 | unsigned alignment, | |
3408 | unsigned cache_level, | |
3409 | unsigned long start, | |
3410 | unsigned long end, | |
3411 | unsigned flags); | |
3412 | int __must_check i915_gem_evict_for_vma(struct i915_vma *target); | |
3413 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); | |
3414 | ||
3415 | /* belongs in i915_gem_gtt.h */ | |
3416 | static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv) | |
3417 | { | |
3418 | if (INTEL_GEN(dev_priv) < 6) | |
3419 | intel_gtt_chipset_flush(); | |
3420 | } | |
3421 | ||
3422 | /* i915_gem_stolen.c */ | |
3423 | int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv, | |
3424 | struct drm_mm_node *node, u64 size, | |
3425 | unsigned alignment); | |
3426 | int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, | |
3427 | struct drm_mm_node *node, u64 size, | |
3428 | unsigned alignment, u64 start, | |
3429 | u64 end); | |
3430 | void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, | |
3431 | struct drm_mm_node *node); | |
3432 | int i915_gem_init_stolen(struct drm_device *dev); | |
3433 | void i915_gem_cleanup_stolen(struct drm_device *dev); | |
3434 | struct drm_i915_gem_object * | |
3435 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
3436 | struct drm_i915_gem_object * | |
3437 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, | |
3438 | u32 stolen_offset, | |
3439 | u32 gtt_offset, | |
3440 | u32 size); | |
3441 | ||
3442 | /* i915_gem_shrinker.c */ | |
3443 | unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, | |
3444 | unsigned long target, | |
3445 | unsigned flags); | |
3446 | #define I915_SHRINK_PURGEABLE 0x1 | |
3447 | #define I915_SHRINK_UNBOUND 0x2 | |
3448 | #define I915_SHRINK_BOUND 0x4 | |
3449 | #define I915_SHRINK_ACTIVE 0x8 | |
3450 | #define I915_SHRINK_VMAPS 0x10 | |
3451 | unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
3452 | void i915_gem_shrinker_init(struct drm_i915_private *dev_priv); | |
3453 | void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv); | |
3454 | ||
3455 | ||
3456 | /* i915_gem_tiling.c */ | |
3457 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) | |
3458 | { | |
3459 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); | |
3460 | ||
3461 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
3462 | obj->tiling_mode != I915_TILING_NONE; | |
3463 | } | |
3464 | ||
3465 | /* i915_gem_debug.c */ | |
3466 | #if WATCH_LISTS | |
3467 | int i915_verify_lists(struct drm_device *dev); | |
3468 | #else | |
3469 | #define i915_verify_lists(dev) 0 | |
3470 | #endif | |
3471 | ||
3472 | /* i915_debugfs.c */ | |
3473 | #ifdef CONFIG_DEBUG_FS | |
3474 | int i915_debugfs_register(struct drm_i915_private *dev_priv); | |
3475 | void i915_debugfs_unregister(struct drm_i915_private *dev_priv); | |
3476 | int i915_debugfs_connector_add(struct drm_connector *connector); | |
3477 | void intel_display_crc_init(struct drm_device *dev); | |
3478 | #else | |
3479 | static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;} | |
3480 | static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {} | |
3481 | static inline int i915_debugfs_connector_add(struct drm_connector *connector) | |
3482 | { return 0; } | |
3483 | static inline void intel_display_crc_init(struct drm_device *dev) {} | |
3484 | #endif | |
3485 | ||
3486 | /* i915_gpu_error.c */ | |
3487 | __printf(2, 3) | |
3488 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
3489 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, | |
3490 | const struct i915_error_state_file_priv *error); | |
3491 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, | |
3492 | struct drm_i915_private *i915, | |
3493 | size_t count, loff_t pos); | |
3494 | static inline void i915_error_state_buf_release( | |
3495 | struct drm_i915_error_state_buf *eb) | |
3496 | { | |
3497 | kfree(eb->buf); | |
3498 | } | |
3499 | void i915_capture_error_state(struct drm_i915_private *dev_priv, | |
3500 | u32 engine_mask, | |
3501 | const char *error_msg); | |
3502 | void i915_error_state_get(struct drm_device *dev, | |
3503 | struct i915_error_state_file_priv *error_priv); | |
3504 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); | |
3505 | void i915_destroy_error_state(struct drm_device *dev); | |
3506 | ||
3507 | void i915_get_extra_instdone(struct drm_i915_private *dev_priv, uint32_t *instdone); | |
3508 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type); | |
3509 | ||
3510 | /* i915_cmd_parser.c */ | |
3511 | int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); | |
3512 | int intel_engine_init_cmd_parser(struct intel_engine_cs *engine); | |
3513 | void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine); | |
3514 | bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine); | |
3515 | int intel_engine_cmd_parser(struct intel_engine_cs *engine, | |
3516 | struct drm_i915_gem_object *batch_obj, | |
3517 | struct drm_i915_gem_object *shadow_batch_obj, | |
3518 | u32 batch_start_offset, | |
3519 | u32 batch_len, | |
3520 | bool is_master); | |
3521 | ||
3522 | /* i915_suspend.c */ | |
3523 | extern int i915_save_state(struct drm_device *dev); | |
3524 | extern int i915_restore_state(struct drm_device *dev); | |
3525 | ||
3526 | /* i915_sysfs.c */ | |
3527 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
3528 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
3529 | ||
3530 | /* intel_i2c.c */ | |
3531 | extern int intel_setup_gmbus(struct drm_device *dev); | |
3532 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
3533 | extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, | |
3534 | unsigned int pin); | |
3535 | ||
3536 | extern struct i2c_adapter * | |
3537 | intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); | |
3538 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); | |
3539 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
3540 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) | |
3541 | { | |
3542 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
3543 | } | |
3544 | extern void intel_i2c_reset(struct drm_device *dev); | |
3545 | ||
3546 | /* intel_bios.c */ | |
3547 | int intel_bios_init(struct drm_i915_private *dev_priv); | |
3548 | bool intel_bios_is_valid_vbt(const void *buf, size_t size); | |
3549 | bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv); | |
3550 | bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin); | |
3551 | bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port); | |
3552 | bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port); | |
3553 | bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port); | |
3554 | bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port); | |
3555 | bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv, | |
3556 | enum port port); | |
3557 | ||
3558 | /* intel_opregion.c */ | |
3559 | #ifdef CONFIG_ACPI | |
3560 | extern int intel_opregion_setup(struct drm_i915_private *dev_priv); | |
3561 | extern void intel_opregion_register(struct drm_i915_private *dev_priv); | |
3562 | extern void intel_opregion_unregister(struct drm_i915_private *dev_priv); | |
3563 | extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv); | |
3564 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, | |
3565 | bool enable); | |
3566 | extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv, | |
3567 | pci_power_t state); | |
3568 | extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv); | |
3569 | #else | |
3570 | static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; } | |
3571 | static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { } | |
3572 | static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { } | |
3573 | static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv) | |
3574 | { | |
3575 | } | |
3576 | static inline int | |
3577 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) | |
3578 | { | |
3579 | return 0; | |
3580 | } | |
3581 | static inline int | |
3582 | intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state) | |
3583 | { | |
3584 | return 0; | |
3585 | } | |
3586 | static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev) | |
3587 | { | |
3588 | return -ENODEV; | |
3589 | } | |
3590 | #endif | |
3591 | ||
3592 | /* intel_acpi.c */ | |
3593 | #ifdef CONFIG_ACPI | |
3594 | extern void intel_register_dsm_handler(void); | |
3595 | extern void intel_unregister_dsm_handler(void); | |
3596 | #else | |
3597 | static inline void intel_register_dsm_handler(void) { return; } | |
3598 | static inline void intel_unregister_dsm_handler(void) { return; } | |
3599 | #endif /* CONFIG_ACPI */ | |
3600 | ||
3601 | /* intel_device_info.c */ | |
3602 | static inline struct intel_device_info * | |
3603 | mkwrite_device_info(struct drm_i915_private *dev_priv) | |
3604 | { | |
3605 | return (struct intel_device_info *)&dev_priv->info; | |
3606 | } | |
3607 | ||
3608 | void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); | |
3609 | void intel_device_info_dump(struct drm_i915_private *dev_priv); | |
3610 | ||
3611 | /* modesetting */ | |
3612 | extern void intel_modeset_init_hw(struct drm_device *dev); | |
3613 | extern void intel_modeset_init(struct drm_device *dev); | |
3614 | extern void intel_modeset_gem_init(struct drm_device *dev); | |
3615 | extern void intel_modeset_cleanup(struct drm_device *dev); | |
3616 | extern int intel_connector_register(struct drm_connector *); | |
3617 | extern void intel_connector_unregister(struct drm_connector *); | |
3618 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); | |
3619 | extern void intel_display_resume(struct drm_device *dev); | |
3620 | extern void i915_redisable_vga(struct drm_device *dev); | |
3621 | extern void i915_redisable_vga_power_on(struct drm_device *dev); | |
3622 | extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val); | |
3623 | extern void intel_init_pch_refclk(struct drm_device *dev); | |
3624 | extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val); | |
3625 | extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, | |
3626 | bool enable); | |
3627 | ||
3628 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, | |
3629 | struct drm_file *file); | |
3630 | ||
3631 | /* overlay */ | |
3632 | extern struct intel_overlay_error_state * | |
3633 | intel_overlay_capture_error_state(struct drm_i915_private *dev_priv); | |
3634 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, | |
3635 | struct intel_overlay_error_state *error); | |
3636 | ||
3637 | extern struct intel_display_error_state * | |
3638 | intel_display_capture_error_state(struct drm_i915_private *dev_priv); | |
3639 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, | |
3640 | struct drm_device *dev, | |
3641 | struct intel_display_error_state *error); | |
3642 | ||
3643 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); | |
3644 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); | |
3645 | ||
3646 | /* intel_sideband.c */ | |
3647 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); | |
3648 | void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); | |
3649 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); | |
3650 | u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg); | |
3651 | void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val); | |
3652 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); | |
3653 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3654 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
3655 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3656 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); | |
3657 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3658 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); | |
3659 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
3660 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, | |
3661 | enum intel_sbi_destination destination); | |
3662 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
3663 | enum intel_sbi_destination destination); | |
3664 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); | |
3665 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3666 | ||
3667 | /* intel_dpio_phy.c */ | |
3668 | void chv_set_phy_signal_level(struct intel_encoder *encoder, | |
3669 | u32 deemph_reg_value, u32 margin_reg_value, | |
3670 | bool uniq_trans_scale); | |
3671 | void chv_data_lane_soft_reset(struct intel_encoder *encoder, | |
3672 | bool reset); | |
3673 | void chv_phy_pre_pll_enable(struct intel_encoder *encoder); | |
3674 | void chv_phy_pre_encoder_enable(struct intel_encoder *encoder); | |
3675 | void chv_phy_release_cl2_override(struct intel_encoder *encoder); | |
3676 | void chv_phy_post_pll_disable(struct intel_encoder *encoder); | |
3677 | ||
3678 | void vlv_set_phy_signal_level(struct intel_encoder *encoder, | |
3679 | u32 demph_reg_value, u32 preemph_reg_value, | |
3680 | u32 uniqtranscale_reg_value, u32 tx3_demph); | |
3681 | void vlv_phy_pre_pll_enable(struct intel_encoder *encoder); | |
3682 | void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder); | |
3683 | void vlv_phy_reset_lanes(struct intel_encoder *encoder); | |
3684 | ||
3685 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); | |
3686 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); | |
3687 | ||
3688 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) | |
3689 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
3690 | ||
3691 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
3692 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
3693 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
3694 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
3695 | ||
3696 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
3697 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
3698 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
3699 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
3700 | ||
3701 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they | |
3702 | * will be implemented using 2 32-bit writes in an arbitrary order with | |
3703 | * an arbitrary delay between them. This can cause the hardware to | |
3704 | * act upon the intermediate value, possibly leading to corruption and | |
3705 | * machine death. You have been warned. | |
3706 | */ | |
3707 | #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) | |
3708 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) | |
3709 | ||
3710 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ | |
3711 | u32 upper, lower, old_upper, loop = 0; \ | |
3712 | upper = I915_READ(upper_reg); \ | |
3713 | do { \ | |
3714 | old_upper = upper; \ | |
3715 | lower = I915_READ(lower_reg); \ | |
3716 | upper = I915_READ(upper_reg); \ | |
3717 | } while (upper != old_upper && loop++ < 2); \ | |
3718 | (u64)upper << 32 | lower; }) | |
3719 | ||
3720 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) | |
3721 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
3722 | ||
3723 | #define __raw_read(x, s) \ | |
3724 | static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \ | |
3725 | i915_reg_t reg) \ | |
3726 | { \ | |
3727 | return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \ | |
3728 | } | |
3729 | ||
3730 | #define __raw_write(x, s) \ | |
3731 | static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \ | |
3732 | i915_reg_t reg, uint##x##_t val) \ | |
3733 | { \ | |
3734 | write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \ | |
3735 | } | |
3736 | __raw_read(8, b) | |
3737 | __raw_read(16, w) | |
3738 | __raw_read(32, l) | |
3739 | __raw_read(64, q) | |
3740 | ||
3741 | __raw_write(8, b) | |
3742 | __raw_write(16, w) | |
3743 | __raw_write(32, l) | |
3744 | __raw_write(64, q) | |
3745 | ||
3746 | #undef __raw_read | |
3747 | #undef __raw_write | |
3748 | ||
3749 | /* These are untraced mmio-accessors that are only valid to be used inside | |
3750 | * criticial sections inside IRQ handlers where forcewake is explicitly | |
3751 | * controlled. | |
3752 | * Think twice, and think again, before using these. | |
3753 | * Note: Should only be used between intel_uncore_forcewake_irqlock() and | |
3754 | * intel_uncore_forcewake_irqunlock(). | |
3755 | */ | |
3756 | #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__)) | |
3757 | #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__)) | |
3758 | #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__)) | |
3759 | #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) | |
3760 | ||
3761 | /* "Broadcast RGB" property */ | |
3762 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
3763 | #define INTEL_BROADCAST_RGB_FULL 1 | |
3764 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
3765 | ||
3766 | static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev) | |
3767 | { | |
3768 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) | |
3769 | return VLV_VGACNTRL; | |
3770 | else if (INTEL_INFO(dev)->gen >= 5) | |
3771 | return CPU_VGACNTRL; | |
3772 | else | |
3773 | return VGACNTRL; | |
3774 | } | |
3775 | ||
3776 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) | |
3777 | { | |
3778 | unsigned long j = msecs_to_jiffies(m); | |
3779 | ||
3780 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3781 | } | |
3782 | ||
3783 | static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) | |
3784 | { | |
3785 | return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); | |
3786 | } | |
3787 | ||
3788 | static inline unsigned long | |
3789 | timespec_to_jiffies_timeout(const struct timespec *value) | |
3790 | { | |
3791 | unsigned long j = timespec_to_jiffies(value); | |
3792 | ||
3793 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3794 | } | |
3795 | ||
3796 | /* | |
3797 | * If you need to wait X milliseconds between events A and B, but event B | |
3798 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of | |
3799 | * when event A happened, then just before event B you call this function and | |
3800 | * pass the timestamp as the first argument, and X as the second argument. | |
3801 | */ | |
3802 | static inline void | |
3803 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) | |
3804 | { | |
3805 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; | |
3806 | ||
3807 | /* | |
3808 | * Don't re-read the value of "jiffies" every time since it may change | |
3809 | * behind our back and break the math. | |
3810 | */ | |
3811 | tmp_jiffies = jiffies; | |
3812 | target_jiffies = timestamp_jiffies + | |
3813 | msecs_to_jiffies_timeout(to_wait_ms); | |
3814 | ||
3815 | if (time_after(target_jiffies, tmp_jiffies)) { | |
3816 | remaining_jiffies = target_jiffies - tmp_jiffies; | |
3817 | while (remaining_jiffies) | |
3818 | remaining_jiffies = | |
3819 | schedule_timeout_uninterruptible(remaining_jiffies); | |
3820 | } | |
3821 | } | |
3822 | static inline bool __i915_request_irq_complete(struct drm_i915_gem_request *req) | |
3823 | { | |
3824 | struct intel_engine_cs *engine = req->engine; | |
3825 | ||
3826 | /* Before we do the heavier coherent read of the seqno, | |
3827 | * check the value (hopefully) in the CPU cacheline. | |
3828 | */ | |
3829 | if (i915_gem_request_completed(req)) | |
3830 | return true; | |
3831 | ||
3832 | /* Ensure our read of the seqno is coherent so that we | |
3833 | * do not "miss an interrupt" (i.e. if this is the last | |
3834 | * request and the seqno write from the GPU is not visible | |
3835 | * by the time the interrupt fires, we will see that the | |
3836 | * request is incomplete and go back to sleep awaiting | |
3837 | * another interrupt that will never come.) | |
3838 | * | |
3839 | * Strictly, we only need to do this once after an interrupt, | |
3840 | * but it is easier and safer to do it every time the waiter | |
3841 | * is woken. | |
3842 | */ | |
3843 | if (engine->irq_seqno_barrier && | |
3844 | READ_ONCE(engine->breadcrumbs.irq_seqno_bh) == current && | |
3845 | cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) { | |
3846 | struct task_struct *tsk; | |
3847 | ||
3848 | /* The ordering of irq_posted versus applying the barrier | |
3849 | * is crucial. The clearing of the current irq_posted must | |
3850 | * be visible before we perform the barrier operation, | |
3851 | * such that if a subsequent interrupt arrives, irq_posted | |
3852 | * is reasserted and our task rewoken (which causes us to | |
3853 | * do another __i915_request_irq_complete() immediately | |
3854 | * and reapply the barrier). Conversely, if the clear | |
3855 | * occurs after the barrier, then an interrupt that arrived | |
3856 | * whilst we waited on the barrier would not trigger a | |
3857 | * barrier on the next pass, and the read may not see the | |
3858 | * seqno update. | |
3859 | */ | |
3860 | engine->irq_seqno_barrier(engine); | |
3861 | ||
3862 | /* If we consume the irq, but we are no longer the bottom-half, | |
3863 | * the real bottom-half may not have serialised their own | |
3864 | * seqno check with the irq-barrier (i.e. may have inspected | |
3865 | * the seqno before we believe it coherent since they see | |
3866 | * irq_posted == false but we are still running). | |
3867 | */ | |
3868 | rcu_read_lock(); | |
3869 | tsk = READ_ONCE(engine->breadcrumbs.irq_seqno_bh); | |
3870 | if (tsk && tsk != current) | |
3871 | /* Note that if the bottom-half is changed as we | |
3872 | * are sending the wake-up, the new bottom-half will | |
3873 | * be woken by whomever made the change. We only have | |
3874 | * to worry about when we steal the irq-posted for | |
3875 | * ourself. | |
3876 | */ | |
3877 | wake_up_process(tsk); | |
3878 | rcu_read_unlock(); | |
3879 | ||
3880 | if (i915_gem_request_completed(req)) | |
3881 | return true; | |
3882 | } | |
3883 | ||
3884 | /* We need to check whether any gpu reset happened in between | |
3885 | * the request being submitted and now. If a reset has occurred, | |
3886 | * the seqno will have been advance past ours and our request | |
3887 | * is complete. If we are in the process of handling a reset, | |
3888 | * the request is effectively complete as the rendering will | |
3889 | * be discarded, but we need to return in order to drop the | |
3890 | * struct_mutex. | |
3891 | */ | |
3892 | if (i915_reset_in_progress(&req->i915->gpu_error)) | |
3893 | return true; | |
3894 | ||
3895 | return false; | |
3896 | } | |
3897 | ||
3898 | #endif |