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1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- | |
2 | */ | |
3 | /* | |
4 | * | |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. | |
6 | * All Rights Reserved. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
28 | */ | |
29 | ||
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
33 | #include <uapi/drm/i915_drm.h> | |
34 | #include <uapi/drm/drm_fourcc.h> | |
35 | ||
36 | #include <linux/io-mapping.h> | |
37 | #include <linux/i2c.h> | |
38 | #include <linux/i2c-algo-bit.h> | |
39 | #include <linux/backlight.h> | |
40 | #include <linux/hash.h> | |
41 | #include <linux/intel-iommu.h> | |
42 | #include <linux/kref.h> | |
43 | #include <linux/pm_qos.h> | |
44 | #include <linux/reservation.h> | |
45 | #include <linux/shmem_fs.h> | |
46 | ||
47 | #include <drm/drmP.h> | |
48 | #include <drm/intel-gtt.h> | |
49 | #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ | |
50 | #include <drm/drm_gem.h> | |
51 | #include <drm/drm_auth.h> | |
52 | #include <drm/drm_cache.h> | |
53 | ||
54 | #include "i915_params.h" | |
55 | #include "i915_reg.h" | |
56 | #include "i915_utils.h" | |
57 | ||
58 | #include "intel_uncore.h" | |
59 | #include "intel_bios.h" | |
60 | #include "intel_dpll_mgr.h" | |
61 | #include "intel_uc.h" | |
62 | #include "intel_lrc.h" | |
63 | #include "intel_ringbuffer.h" | |
64 | ||
65 | #include "i915_gem.h" | |
66 | #include "i915_gem_context.h" | |
67 | #include "i915_gem_fence_reg.h" | |
68 | #include "i915_gem_object.h" | |
69 | #include "i915_gem_gtt.h" | |
70 | #include "i915_gem_render_state.h" | |
71 | #include "i915_gem_request.h" | |
72 | #include "i915_gem_timeline.h" | |
73 | ||
74 | #include "i915_vma.h" | |
75 | ||
76 | #include "intel_gvt.h" | |
77 | ||
78 | /* General customization: | |
79 | */ | |
80 | ||
81 | #define DRIVER_NAME "i915" | |
82 | #define DRIVER_DESC "Intel Graphics" | |
83 | #define DRIVER_DATE "20170929" | |
84 | #define DRIVER_TIMESTAMP 1506682238 | |
85 | ||
86 | /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and | |
87 | * WARN_ON()) for hw state sanity checks to check for unexpected conditions | |
88 | * which may not necessarily be a user visible problem. This will either | |
89 | * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to | |
90 | * enable distros and users to tailor their preferred amount of i915 abrt | |
91 | * spam. | |
92 | */ | |
93 | #define I915_STATE_WARN(condition, format...) ({ \ | |
94 | int __ret_warn_on = !!(condition); \ | |
95 | if (unlikely(__ret_warn_on)) \ | |
96 | if (!WARN(i915_modparams.verbose_state_checks, format)) \ | |
97 | DRM_ERROR(format); \ | |
98 | unlikely(__ret_warn_on); \ | |
99 | }) | |
100 | ||
101 | #define I915_STATE_WARN_ON(x) \ | |
102 | I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") | |
103 | ||
104 | bool __i915_inject_load_failure(const char *func, int line); | |
105 | #define i915_inject_load_failure() \ | |
106 | __i915_inject_load_failure(__func__, __LINE__) | |
107 | ||
108 | typedef struct { | |
109 | uint32_t val; | |
110 | } uint_fixed_16_16_t; | |
111 | ||
112 | #define FP_16_16_MAX ({ \ | |
113 | uint_fixed_16_16_t fp; \ | |
114 | fp.val = UINT_MAX; \ | |
115 | fp; \ | |
116 | }) | |
117 | ||
118 | static inline bool is_fixed16_zero(uint_fixed_16_16_t val) | |
119 | { | |
120 | if (val.val == 0) | |
121 | return true; | |
122 | return false; | |
123 | } | |
124 | ||
125 | static inline uint_fixed_16_16_t u32_to_fixed16(uint32_t val) | |
126 | { | |
127 | uint_fixed_16_16_t fp; | |
128 | ||
129 | WARN_ON(val > U16_MAX); | |
130 | ||
131 | fp.val = val << 16; | |
132 | return fp; | |
133 | } | |
134 | ||
135 | static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp) | |
136 | { | |
137 | return DIV_ROUND_UP(fp.val, 1 << 16); | |
138 | } | |
139 | ||
140 | static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp) | |
141 | { | |
142 | return fp.val >> 16; | |
143 | } | |
144 | ||
145 | static inline uint_fixed_16_16_t min_fixed16(uint_fixed_16_16_t min1, | |
146 | uint_fixed_16_16_t min2) | |
147 | { | |
148 | uint_fixed_16_16_t min; | |
149 | ||
150 | min.val = min(min1.val, min2.val); | |
151 | return min; | |
152 | } | |
153 | ||
154 | static inline uint_fixed_16_16_t max_fixed16(uint_fixed_16_16_t max1, | |
155 | uint_fixed_16_16_t max2) | |
156 | { | |
157 | uint_fixed_16_16_t max; | |
158 | ||
159 | max.val = max(max1.val, max2.val); | |
160 | return max; | |
161 | } | |
162 | ||
163 | static inline uint_fixed_16_16_t clamp_u64_to_fixed16(uint64_t val) | |
164 | { | |
165 | uint_fixed_16_16_t fp; | |
166 | WARN_ON(val > U32_MAX); | |
167 | fp.val = (uint32_t) val; | |
168 | return fp; | |
169 | } | |
170 | ||
171 | static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val, | |
172 | uint_fixed_16_16_t d) | |
173 | { | |
174 | return DIV_ROUND_UP(val.val, d.val); | |
175 | } | |
176 | ||
177 | static inline uint32_t mul_round_up_u32_fixed16(uint32_t val, | |
178 | uint_fixed_16_16_t mul) | |
179 | { | |
180 | uint64_t intermediate_val; | |
181 | ||
182 | intermediate_val = (uint64_t) val * mul.val; | |
183 | intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16); | |
184 | WARN_ON(intermediate_val > U32_MAX); | |
185 | return (uint32_t) intermediate_val; | |
186 | } | |
187 | ||
188 | static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val, | |
189 | uint_fixed_16_16_t mul) | |
190 | { | |
191 | uint64_t intermediate_val; | |
192 | ||
193 | intermediate_val = (uint64_t) val.val * mul.val; | |
194 | intermediate_val = intermediate_val >> 16; | |
195 | return clamp_u64_to_fixed16(intermediate_val); | |
196 | } | |
197 | ||
198 | static inline uint_fixed_16_16_t div_fixed16(uint32_t val, uint32_t d) | |
199 | { | |
200 | uint64_t interm_val; | |
201 | ||
202 | interm_val = (uint64_t)val << 16; | |
203 | interm_val = DIV_ROUND_UP_ULL(interm_val, d); | |
204 | return clamp_u64_to_fixed16(interm_val); | |
205 | } | |
206 | ||
207 | static inline uint32_t div_round_up_u32_fixed16(uint32_t val, | |
208 | uint_fixed_16_16_t d) | |
209 | { | |
210 | uint64_t interm_val; | |
211 | ||
212 | interm_val = (uint64_t)val << 16; | |
213 | interm_val = DIV_ROUND_UP_ULL(interm_val, d.val); | |
214 | WARN_ON(interm_val > U32_MAX); | |
215 | return (uint32_t) interm_val; | |
216 | } | |
217 | ||
218 | static inline uint_fixed_16_16_t mul_u32_fixed16(uint32_t val, | |
219 | uint_fixed_16_16_t mul) | |
220 | { | |
221 | uint64_t intermediate_val; | |
222 | ||
223 | intermediate_val = (uint64_t) val * mul.val; | |
224 | return clamp_u64_to_fixed16(intermediate_val); | |
225 | } | |
226 | ||
227 | static inline uint_fixed_16_16_t add_fixed16(uint_fixed_16_16_t add1, | |
228 | uint_fixed_16_16_t add2) | |
229 | { | |
230 | uint64_t interm_sum; | |
231 | ||
232 | interm_sum = (uint64_t) add1.val + add2.val; | |
233 | return clamp_u64_to_fixed16(interm_sum); | |
234 | } | |
235 | ||
236 | static inline uint_fixed_16_16_t add_fixed16_u32(uint_fixed_16_16_t add1, | |
237 | uint32_t add2) | |
238 | { | |
239 | uint64_t interm_sum; | |
240 | uint_fixed_16_16_t interm_add2 = u32_to_fixed16(add2); | |
241 | ||
242 | interm_sum = (uint64_t) add1.val + interm_add2.val; | |
243 | return clamp_u64_to_fixed16(interm_sum); | |
244 | } | |
245 | ||
246 | static inline const char *yesno(bool v) | |
247 | { | |
248 | return v ? "yes" : "no"; | |
249 | } | |
250 | ||
251 | static inline const char *onoff(bool v) | |
252 | { | |
253 | return v ? "on" : "off"; | |
254 | } | |
255 | ||
256 | static inline const char *enableddisabled(bool v) | |
257 | { | |
258 | return v ? "enabled" : "disabled"; | |
259 | } | |
260 | ||
261 | enum pipe { | |
262 | INVALID_PIPE = -1, | |
263 | PIPE_A = 0, | |
264 | PIPE_B, | |
265 | PIPE_C, | |
266 | _PIPE_EDP, | |
267 | I915_MAX_PIPES = _PIPE_EDP | |
268 | }; | |
269 | #define pipe_name(p) ((p) + 'A') | |
270 | ||
271 | enum transcoder { | |
272 | TRANSCODER_A = 0, | |
273 | TRANSCODER_B, | |
274 | TRANSCODER_C, | |
275 | TRANSCODER_EDP, | |
276 | TRANSCODER_DSI_A, | |
277 | TRANSCODER_DSI_C, | |
278 | I915_MAX_TRANSCODERS | |
279 | }; | |
280 | ||
281 | static inline const char *transcoder_name(enum transcoder transcoder) | |
282 | { | |
283 | switch (transcoder) { | |
284 | case TRANSCODER_A: | |
285 | return "A"; | |
286 | case TRANSCODER_B: | |
287 | return "B"; | |
288 | case TRANSCODER_C: | |
289 | return "C"; | |
290 | case TRANSCODER_EDP: | |
291 | return "EDP"; | |
292 | case TRANSCODER_DSI_A: | |
293 | return "DSI A"; | |
294 | case TRANSCODER_DSI_C: | |
295 | return "DSI C"; | |
296 | default: | |
297 | return "<invalid>"; | |
298 | } | |
299 | } | |
300 | ||
301 | static inline bool transcoder_is_dsi(enum transcoder transcoder) | |
302 | { | |
303 | return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; | |
304 | } | |
305 | ||
306 | /* | |
307 | * Global legacy plane identifier. Valid only for primary/sprite | |
308 | * planes on pre-g4x, and only for primary planes on g4x+. | |
309 | */ | |
310 | enum plane { | |
311 | PLANE_A, | |
312 | PLANE_B, | |
313 | PLANE_C, | |
314 | }; | |
315 | #define plane_name(p) ((p) + 'A') | |
316 | ||
317 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') | |
318 | ||
319 | /* | |
320 | * Per-pipe plane identifier. | |
321 | * I915_MAX_PLANES in the enum below is the maximum (across all platforms) | |
322 | * number of planes per CRTC. Not all platforms really have this many planes, | |
323 | * which means some arrays of size I915_MAX_PLANES may have unused entries | |
324 | * between the topmost sprite plane and the cursor plane. | |
325 | * | |
326 | * This is expected to be passed to various register macros | |
327 | * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care. | |
328 | */ | |
329 | enum plane_id { | |
330 | PLANE_PRIMARY, | |
331 | PLANE_SPRITE0, | |
332 | PLANE_SPRITE1, | |
333 | PLANE_SPRITE2, | |
334 | PLANE_CURSOR, | |
335 | I915_MAX_PLANES, | |
336 | }; | |
337 | ||
338 | #define for_each_plane_id_on_crtc(__crtc, __p) \ | |
339 | for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \ | |
340 | for_each_if ((__crtc)->plane_ids_mask & BIT(__p)) | |
341 | ||
342 | enum port { | |
343 | PORT_NONE = -1, | |
344 | PORT_A = 0, | |
345 | PORT_B, | |
346 | PORT_C, | |
347 | PORT_D, | |
348 | PORT_E, | |
349 | I915_MAX_PORTS | |
350 | }; | |
351 | #define port_name(p) ((p) + 'A') | |
352 | ||
353 | #define I915_NUM_PHYS_VLV 2 | |
354 | ||
355 | enum dpio_channel { | |
356 | DPIO_CH0, | |
357 | DPIO_CH1 | |
358 | }; | |
359 | ||
360 | enum dpio_phy { | |
361 | DPIO_PHY0, | |
362 | DPIO_PHY1, | |
363 | DPIO_PHY2, | |
364 | }; | |
365 | ||
366 | enum intel_display_power_domain { | |
367 | POWER_DOMAIN_PIPE_A, | |
368 | POWER_DOMAIN_PIPE_B, | |
369 | POWER_DOMAIN_PIPE_C, | |
370 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
371 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
372 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
373 | POWER_DOMAIN_TRANSCODER_A, | |
374 | POWER_DOMAIN_TRANSCODER_B, | |
375 | POWER_DOMAIN_TRANSCODER_C, | |
376 | POWER_DOMAIN_TRANSCODER_EDP, | |
377 | POWER_DOMAIN_TRANSCODER_DSI_A, | |
378 | POWER_DOMAIN_TRANSCODER_DSI_C, | |
379 | POWER_DOMAIN_PORT_DDI_A_LANES, | |
380 | POWER_DOMAIN_PORT_DDI_B_LANES, | |
381 | POWER_DOMAIN_PORT_DDI_C_LANES, | |
382 | POWER_DOMAIN_PORT_DDI_D_LANES, | |
383 | POWER_DOMAIN_PORT_DDI_E_LANES, | |
384 | POWER_DOMAIN_PORT_DDI_A_IO, | |
385 | POWER_DOMAIN_PORT_DDI_B_IO, | |
386 | POWER_DOMAIN_PORT_DDI_C_IO, | |
387 | POWER_DOMAIN_PORT_DDI_D_IO, | |
388 | POWER_DOMAIN_PORT_DDI_E_IO, | |
389 | POWER_DOMAIN_PORT_DSI, | |
390 | POWER_DOMAIN_PORT_CRT, | |
391 | POWER_DOMAIN_PORT_OTHER, | |
392 | POWER_DOMAIN_VGA, | |
393 | POWER_DOMAIN_AUDIO, | |
394 | POWER_DOMAIN_PLLS, | |
395 | POWER_DOMAIN_AUX_A, | |
396 | POWER_DOMAIN_AUX_B, | |
397 | POWER_DOMAIN_AUX_C, | |
398 | POWER_DOMAIN_AUX_D, | |
399 | POWER_DOMAIN_GMBUS, | |
400 | POWER_DOMAIN_MODESET, | |
401 | POWER_DOMAIN_INIT, | |
402 | ||
403 | POWER_DOMAIN_NUM, | |
404 | }; | |
405 | ||
406 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) | |
407 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
408 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
409 | #define POWER_DOMAIN_TRANSCODER(tran) \ | |
410 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ | |
411 | (tran) + POWER_DOMAIN_TRANSCODER_A) | |
412 | ||
413 | enum hpd_pin { | |
414 | HPD_NONE = 0, | |
415 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ | |
416 | HPD_CRT, | |
417 | HPD_SDVO_B, | |
418 | HPD_SDVO_C, | |
419 | HPD_PORT_A, | |
420 | HPD_PORT_B, | |
421 | HPD_PORT_C, | |
422 | HPD_PORT_D, | |
423 | HPD_PORT_E, | |
424 | HPD_NUM_PINS | |
425 | }; | |
426 | ||
427 | #define for_each_hpd_pin(__pin) \ | |
428 | for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) | |
429 | ||
430 | #define HPD_STORM_DEFAULT_THRESHOLD 5 | |
431 | ||
432 | struct i915_hotplug { | |
433 | struct work_struct hotplug_work; | |
434 | ||
435 | struct { | |
436 | unsigned long last_jiffies; | |
437 | int count; | |
438 | enum { | |
439 | HPD_ENABLED = 0, | |
440 | HPD_DISABLED = 1, | |
441 | HPD_MARK_DISABLED = 2 | |
442 | } state; | |
443 | } stats[HPD_NUM_PINS]; | |
444 | u32 event_bits; | |
445 | struct delayed_work reenable_work; | |
446 | ||
447 | struct intel_digital_port *irq_port[I915_MAX_PORTS]; | |
448 | u32 long_port_mask; | |
449 | u32 short_port_mask; | |
450 | struct work_struct dig_port_work; | |
451 | ||
452 | struct work_struct poll_init_work; | |
453 | bool poll_enabled; | |
454 | ||
455 | unsigned int hpd_storm_threshold; | |
456 | ||
457 | /* | |
458 | * if we get a HPD irq from DP and a HPD irq from non-DP | |
459 | * the non-DP HPD could block the workqueue on a mode config | |
460 | * mutex getting, that userspace may have taken. However | |
461 | * userspace is waiting on the DP workqueue to run which is | |
462 | * blocked behind the non-DP one. | |
463 | */ | |
464 | struct workqueue_struct *dp_wq; | |
465 | }; | |
466 | ||
467 | #define I915_GEM_GPU_DOMAINS \ | |
468 | (I915_GEM_DOMAIN_RENDER | \ | |
469 | I915_GEM_DOMAIN_SAMPLER | \ | |
470 | I915_GEM_DOMAIN_COMMAND | \ | |
471 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
472 | I915_GEM_DOMAIN_VERTEX) | |
473 | ||
474 | #define for_each_pipe(__dev_priv, __p) \ | |
475 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) | |
476 | #define for_each_pipe_masked(__dev_priv, __p, __mask) \ | |
477 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \ | |
478 | for_each_if ((__mask) & (1 << (__p))) | |
479 | #define for_each_universal_plane(__dev_priv, __pipe, __p) \ | |
480 | for ((__p) = 0; \ | |
481 | (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ | |
482 | (__p)++) | |
483 | #define for_each_sprite(__dev_priv, __p, __s) \ | |
484 | for ((__s) = 0; \ | |
485 | (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \ | |
486 | (__s)++) | |
487 | ||
488 | #define for_each_port_masked(__port, __ports_mask) \ | |
489 | for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ | |
490 | for_each_if ((__ports_mask) & (1 << (__port))) | |
491 | ||
492 | #define for_each_crtc(dev, crtc) \ | |
493 | list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) | |
494 | ||
495 | #define for_each_intel_plane(dev, intel_plane) \ | |
496 | list_for_each_entry(intel_plane, \ | |
497 | &(dev)->mode_config.plane_list, \ | |
498 | base.head) | |
499 | ||
500 | #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ | |
501 | list_for_each_entry(intel_plane, \ | |
502 | &(dev)->mode_config.plane_list, \ | |
503 | base.head) \ | |
504 | for_each_if ((plane_mask) & \ | |
505 | (1 << drm_plane_index(&intel_plane->base))) | |
506 | ||
507 | #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ | |
508 | list_for_each_entry(intel_plane, \ | |
509 | &(dev)->mode_config.plane_list, \ | |
510 | base.head) \ | |
511 | for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe) | |
512 | ||
513 | #define for_each_intel_crtc(dev, intel_crtc) \ | |
514 | list_for_each_entry(intel_crtc, \ | |
515 | &(dev)->mode_config.crtc_list, \ | |
516 | base.head) | |
517 | ||
518 | #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \ | |
519 | list_for_each_entry(intel_crtc, \ | |
520 | &(dev)->mode_config.crtc_list, \ | |
521 | base.head) \ | |
522 | for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base))) | |
523 | ||
524 | #define for_each_intel_encoder(dev, intel_encoder) \ | |
525 | list_for_each_entry(intel_encoder, \ | |
526 | &(dev)->mode_config.encoder_list, \ | |
527 | base.head) | |
528 | ||
529 | #define for_each_intel_connector_iter(intel_connector, iter) \ | |
530 | while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter)))) | |
531 | ||
532 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ | |
533 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
534 | for_each_if ((intel_encoder)->base.crtc == (__crtc)) | |
535 | ||
536 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ | |
537 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ | |
538 | for_each_if ((intel_connector)->base.encoder == (__encoder)) | |
539 | ||
540 | #define for_each_power_domain(domain, mask) \ | |
541 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
542 | for_each_if (BIT_ULL(domain) & (mask)) | |
543 | ||
544 | #define for_each_power_well(__dev_priv, __power_well) \ | |
545 | for ((__power_well) = (__dev_priv)->power_domains.power_wells; \ | |
546 | (__power_well) - (__dev_priv)->power_domains.power_wells < \ | |
547 | (__dev_priv)->power_domains.power_well_count; \ | |
548 | (__power_well)++) | |
549 | ||
550 | #define for_each_power_well_rev(__dev_priv, __power_well) \ | |
551 | for ((__power_well) = (__dev_priv)->power_domains.power_wells + \ | |
552 | (__dev_priv)->power_domains.power_well_count - 1; \ | |
553 | (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \ | |
554 | (__power_well)--) | |
555 | ||
556 | #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \ | |
557 | for_each_power_well(__dev_priv, __power_well) \ | |
558 | for_each_if ((__power_well)->domains & (__domain_mask)) | |
559 | ||
560 | #define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \ | |
561 | for_each_power_well_rev(__dev_priv, __power_well) \ | |
562 | for_each_if ((__power_well)->domains & (__domain_mask)) | |
563 | ||
564 | #define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \ | |
565 | for ((__i) = 0; \ | |
566 | (__i) < (__state)->base.dev->mode_config.num_total_plane && \ | |
567 | ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ | |
568 | (plane_state) = to_intel_plane_state((__state)->base.planes[__i].state), 1); \ | |
569 | (__i)++) \ | |
570 | for_each_if (plane_state) | |
571 | ||
572 | #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ | |
573 | for ((__i) = 0; \ | |
574 | (__i) < (__state)->base.dev->mode_config.num_crtc && \ | |
575 | ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ | |
576 | (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ | |
577 | (__i)++) \ | |
578 | for_each_if (crtc) | |
579 | ||
580 | ||
581 | #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \ | |
582 | for ((__i) = 0; \ | |
583 | (__i) < (__state)->base.dev->mode_config.num_total_plane && \ | |
584 | ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ | |
585 | (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \ | |
586 | (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ | |
587 | (__i)++) \ | |
588 | for_each_if (plane) | |
589 | ||
590 | struct drm_i915_private; | |
591 | struct i915_mm_struct; | |
592 | struct i915_mmu_object; | |
593 | ||
594 | struct drm_i915_file_private { | |
595 | struct drm_i915_private *dev_priv; | |
596 | struct drm_file *file; | |
597 | ||
598 | struct { | |
599 | spinlock_t lock; | |
600 | struct list_head request_list; | |
601 | /* 20ms is a fairly arbitrary limit (greater than the average frame time) | |
602 | * chosen to prevent the CPU getting more than a frame ahead of the GPU | |
603 | * (when using lax throttling for the frontbuffer). We also use it to | |
604 | * offer free GPU waitboosts for severely congested workloads. | |
605 | */ | |
606 | #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20) | |
607 | } mm; | |
608 | struct idr context_idr; | |
609 | ||
610 | struct intel_rps_client { | |
611 | atomic_t boosts; | |
612 | } rps; | |
613 | ||
614 | unsigned int bsd_engine; | |
615 | ||
616 | /* Client can have a maximum of 3 contexts banned before | |
617 | * it is denied of creating new contexts. As one context | |
618 | * ban needs 4 consecutive hangs, and more if there is | |
619 | * progress in between, this is a last resort stop gap measure | |
620 | * to limit the badly behaving clients access to gpu. | |
621 | */ | |
622 | #define I915_MAX_CLIENT_CONTEXT_BANS 3 | |
623 | atomic_t context_bans; | |
624 | }; | |
625 | ||
626 | /* Used by dp and fdi links */ | |
627 | struct intel_link_m_n { | |
628 | uint32_t tu; | |
629 | uint32_t gmch_m; | |
630 | uint32_t gmch_n; | |
631 | uint32_t link_m; | |
632 | uint32_t link_n; | |
633 | }; | |
634 | ||
635 | void intel_link_compute_m_n(int bpp, int nlanes, | |
636 | int pixel_clock, int link_clock, | |
637 | struct intel_link_m_n *m_n, | |
638 | bool reduce_m_n); | |
639 | ||
640 | /* Interface history: | |
641 | * | |
642 | * 1.1: Original. | |
643 | * 1.2: Add Power Management | |
644 | * 1.3: Add vblank support | |
645 | * 1.4: Fix cmdbuffer path, add heap destroy | |
646 | * 1.5: Add vblank pipe configuration | |
647 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank | |
648 | * - Support vertical blank on secondary display pipe | |
649 | */ | |
650 | #define DRIVER_MAJOR 1 | |
651 | #define DRIVER_MINOR 6 | |
652 | #define DRIVER_PATCHLEVEL 0 | |
653 | ||
654 | struct opregion_header; | |
655 | struct opregion_acpi; | |
656 | struct opregion_swsci; | |
657 | struct opregion_asle; | |
658 | ||
659 | struct intel_opregion { | |
660 | struct opregion_header *header; | |
661 | struct opregion_acpi *acpi; | |
662 | struct opregion_swsci *swsci; | |
663 | u32 swsci_gbda_sub_functions; | |
664 | u32 swsci_sbcb_sub_functions; | |
665 | struct opregion_asle *asle; | |
666 | void *rvda; | |
667 | void *vbt_firmware; | |
668 | const void *vbt; | |
669 | u32 vbt_size; | |
670 | u32 *lid_state; | |
671 | struct work_struct asle_work; | |
672 | }; | |
673 | #define OPREGION_SIZE (8*1024) | |
674 | ||
675 | struct intel_overlay; | |
676 | struct intel_overlay_error_state; | |
677 | ||
678 | struct sdvo_device_mapping { | |
679 | u8 initialized; | |
680 | u8 dvo_port; | |
681 | u8 slave_addr; | |
682 | u8 dvo_wiring; | |
683 | u8 i2c_pin; | |
684 | u8 ddc_pin; | |
685 | }; | |
686 | ||
687 | struct intel_connector; | |
688 | struct intel_encoder; | |
689 | struct intel_atomic_state; | |
690 | struct intel_crtc_state; | |
691 | struct intel_initial_plane_config; | |
692 | struct intel_crtc; | |
693 | struct intel_limit; | |
694 | struct dpll; | |
695 | struct intel_cdclk_state; | |
696 | ||
697 | struct drm_i915_display_funcs { | |
698 | void (*get_cdclk)(struct drm_i915_private *dev_priv, | |
699 | struct intel_cdclk_state *cdclk_state); | |
700 | void (*set_cdclk)(struct drm_i915_private *dev_priv, | |
701 | const struct intel_cdclk_state *cdclk_state); | |
702 | int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane); | |
703 | int (*compute_pipe_wm)(struct intel_crtc_state *cstate); | |
704 | int (*compute_intermediate_wm)(struct drm_device *dev, | |
705 | struct intel_crtc *intel_crtc, | |
706 | struct intel_crtc_state *newstate); | |
707 | void (*initial_watermarks)(struct intel_atomic_state *state, | |
708 | struct intel_crtc_state *cstate); | |
709 | void (*atomic_update_watermarks)(struct intel_atomic_state *state, | |
710 | struct intel_crtc_state *cstate); | |
711 | void (*optimize_watermarks)(struct intel_atomic_state *state, | |
712 | struct intel_crtc_state *cstate); | |
713 | int (*compute_global_watermarks)(struct drm_atomic_state *state); | |
714 | void (*update_wm)(struct intel_crtc *crtc); | |
715 | int (*modeset_calc_cdclk)(struct drm_atomic_state *state); | |
716 | /* Returns the active state of the crtc, and if the crtc is active, | |
717 | * fills out the pipe-config with the hw state. */ | |
718 | bool (*get_pipe_config)(struct intel_crtc *, | |
719 | struct intel_crtc_state *); | |
720 | void (*get_initial_plane_config)(struct intel_crtc *, | |
721 | struct intel_initial_plane_config *); | |
722 | int (*crtc_compute_clock)(struct intel_crtc *crtc, | |
723 | struct intel_crtc_state *crtc_state); | |
724 | void (*crtc_enable)(struct intel_crtc_state *pipe_config, | |
725 | struct drm_atomic_state *old_state); | |
726 | void (*crtc_disable)(struct intel_crtc_state *old_crtc_state, | |
727 | struct drm_atomic_state *old_state); | |
728 | void (*update_crtcs)(struct drm_atomic_state *state); | |
729 | void (*audio_codec_enable)(struct drm_connector *connector, | |
730 | struct intel_encoder *encoder, | |
731 | const struct drm_display_mode *adjusted_mode); | |
732 | void (*audio_codec_disable)(struct intel_encoder *encoder); | |
733 | void (*fdi_link_train)(struct intel_crtc *crtc, | |
734 | const struct intel_crtc_state *crtc_state); | |
735 | void (*init_clock_gating)(struct drm_i915_private *dev_priv); | |
736 | void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); | |
737 | /* clock updates for mode set */ | |
738 | /* cursor updates */ | |
739 | /* render clock increase/decrease */ | |
740 | /* display clock increase/decrease */ | |
741 | /* pll clock increase/decrease */ | |
742 | ||
743 | void (*load_csc_matrix)(struct drm_crtc_state *crtc_state); | |
744 | void (*load_luts)(struct drm_crtc_state *crtc_state); | |
745 | }; | |
746 | ||
747 | #define CSR_VERSION(major, minor) ((major) << 16 | (minor)) | |
748 | #define CSR_VERSION_MAJOR(version) ((version) >> 16) | |
749 | #define CSR_VERSION_MINOR(version) ((version) & 0xffff) | |
750 | ||
751 | struct intel_csr { | |
752 | struct work_struct work; | |
753 | const char *fw_path; | |
754 | uint32_t *dmc_payload; | |
755 | uint32_t dmc_fw_size; | |
756 | uint32_t version; | |
757 | uint32_t mmio_count; | |
758 | i915_reg_t mmioaddr[8]; | |
759 | uint32_t mmiodata[8]; | |
760 | uint32_t dc_state; | |
761 | uint32_t allowed_dc_mask; | |
762 | }; | |
763 | ||
764 | #define DEV_INFO_FOR_EACH_FLAG(func) \ | |
765 | func(is_mobile); \ | |
766 | func(is_lp); \ | |
767 | func(is_alpha_support); \ | |
768 | /* Keep has_* in alphabetical order */ \ | |
769 | func(has_64bit_reloc); \ | |
770 | func(has_aliasing_ppgtt); \ | |
771 | func(has_csr); \ | |
772 | func(has_ddi); \ | |
773 | func(has_dp_mst); \ | |
774 | func(has_reset_engine); \ | |
775 | func(has_fbc); \ | |
776 | func(has_fpga_dbg); \ | |
777 | func(has_full_ppgtt); \ | |
778 | func(has_full_48bit_ppgtt); \ | |
779 | func(has_gmch_display); \ | |
780 | func(has_guc); \ | |
781 | func(has_guc_ct); \ | |
782 | func(has_hotplug); \ | |
783 | func(has_l3_dpf); \ | |
784 | func(has_llc); \ | |
785 | func(has_logical_ring_contexts); \ | |
786 | func(has_logical_ring_preemption); \ | |
787 | func(has_overlay); \ | |
788 | func(has_pipe_cxsr); \ | |
789 | func(has_pooled_eu); \ | |
790 | func(has_psr); \ | |
791 | func(has_rc6); \ | |
792 | func(has_rc6p); \ | |
793 | func(has_resource_streamer); \ | |
794 | func(has_runtime_pm); \ | |
795 | func(has_snoop); \ | |
796 | func(unfenced_needs_alignment); \ | |
797 | func(cursor_needs_physical); \ | |
798 | func(hws_needs_physical); \ | |
799 | func(overlay_needs_physical); \ | |
800 | func(supports_tv); \ | |
801 | func(has_ipc); | |
802 | ||
803 | struct sseu_dev_info { | |
804 | u8 slice_mask; | |
805 | u8 subslice_mask; | |
806 | u8 eu_total; | |
807 | u8 eu_per_subslice; | |
808 | u8 min_eu_in_pool; | |
809 | /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ | |
810 | u8 subslice_7eu[3]; | |
811 | u8 has_slice_pg:1; | |
812 | u8 has_subslice_pg:1; | |
813 | u8 has_eu_pg:1; | |
814 | }; | |
815 | ||
816 | static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu) | |
817 | { | |
818 | return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask); | |
819 | } | |
820 | ||
821 | /* Keep in gen based order, and chronological order within a gen */ | |
822 | enum intel_platform { | |
823 | INTEL_PLATFORM_UNINITIALIZED = 0, | |
824 | INTEL_I830, | |
825 | INTEL_I845G, | |
826 | INTEL_I85X, | |
827 | INTEL_I865G, | |
828 | INTEL_I915G, | |
829 | INTEL_I915GM, | |
830 | INTEL_I945G, | |
831 | INTEL_I945GM, | |
832 | INTEL_G33, | |
833 | INTEL_PINEVIEW, | |
834 | INTEL_I965G, | |
835 | INTEL_I965GM, | |
836 | INTEL_G45, | |
837 | INTEL_GM45, | |
838 | INTEL_IRONLAKE, | |
839 | INTEL_SANDYBRIDGE, | |
840 | INTEL_IVYBRIDGE, | |
841 | INTEL_VALLEYVIEW, | |
842 | INTEL_HASWELL, | |
843 | INTEL_BROADWELL, | |
844 | INTEL_CHERRYVIEW, | |
845 | INTEL_SKYLAKE, | |
846 | INTEL_BROXTON, | |
847 | INTEL_KABYLAKE, | |
848 | INTEL_GEMINILAKE, | |
849 | INTEL_COFFEELAKE, | |
850 | INTEL_CANNONLAKE, | |
851 | INTEL_MAX_PLATFORMS | |
852 | }; | |
853 | ||
854 | struct intel_device_info { | |
855 | u16 device_id; | |
856 | u16 gen_mask; | |
857 | ||
858 | u8 gen; | |
859 | u8 gt; /* GT number, 0 if undefined */ | |
860 | u8 num_rings; | |
861 | u8 ring_mask; /* Rings supported by the HW */ | |
862 | ||
863 | enum intel_platform platform; | |
864 | u32 platform_mask; | |
865 | ||
866 | u32 display_mmio_offset; | |
867 | ||
868 | u8 num_pipes; | |
869 | u8 num_sprites[I915_MAX_PIPES]; | |
870 | u8 num_scalers[I915_MAX_PIPES]; | |
871 | ||
872 | #define DEFINE_FLAG(name) u8 name:1 | |
873 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); | |
874 | #undef DEFINE_FLAG | |
875 | u16 ddb_size; /* in blocks */ | |
876 | ||
877 | /* Register offsets for the various display pipes and transcoders */ | |
878 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
879 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
880 | int palette_offsets[I915_MAX_PIPES]; | |
881 | int cursor_offsets[I915_MAX_PIPES]; | |
882 | ||
883 | /* Slice/subslice/EU info */ | |
884 | struct sseu_dev_info sseu; | |
885 | ||
886 | struct color_luts { | |
887 | u16 degamma_lut_size; | |
888 | u16 gamma_lut_size; | |
889 | } color; | |
890 | }; | |
891 | ||
892 | struct intel_display_error_state; | |
893 | ||
894 | struct i915_gpu_state { | |
895 | struct kref ref; | |
896 | struct timeval time; | |
897 | struct timeval boottime; | |
898 | struct timeval uptime; | |
899 | ||
900 | struct drm_i915_private *i915; | |
901 | ||
902 | char error_msg[128]; | |
903 | bool simulated; | |
904 | bool awake; | |
905 | bool wakelock; | |
906 | bool suspended; | |
907 | int iommu; | |
908 | u32 reset_count; | |
909 | u32 suspend_count; | |
910 | struct intel_device_info device_info; | |
911 | struct i915_params params; | |
912 | ||
913 | /* Generic register state */ | |
914 | u32 eir; | |
915 | u32 pgtbl_er; | |
916 | u32 ier; | |
917 | u32 gtier[4], ngtier; | |
918 | u32 ccid; | |
919 | u32 derrmr; | |
920 | u32 forcewake; | |
921 | u32 error; /* gen6+ */ | |
922 | u32 err_int; /* gen7 */ | |
923 | u32 fault_data0; /* gen8, gen9 */ | |
924 | u32 fault_data1; /* gen8, gen9 */ | |
925 | u32 done_reg; | |
926 | u32 gac_eco; | |
927 | u32 gam_ecochk; | |
928 | u32 gab_ctl; | |
929 | u32 gfx_mode; | |
930 | ||
931 | u32 nfence; | |
932 | u64 fence[I915_MAX_NUM_FENCES]; | |
933 | struct intel_overlay_error_state *overlay; | |
934 | struct intel_display_error_state *display; | |
935 | struct drm_i915_error_object *semaphore; | |
936 | struct drm_i915_error_object *guc_log; | |
937 | ||
938 | struct drm_i915_error_engine { | |
939 | int engine_id; | |
940 | /* Software tracked state */ | |
941 | bool waiting; | |
942 | int num_waiters; | |
943 | unsigned long hangcheck_timestamp; | |
944 | bool hangcheck_stalled; | |
945 | enum intel_engine_hangcheck_action hangcheck_action; | |
946 | struct i915_address_space *vm; | |
947 | int num_requests; | |
948 | u32 reset_count; | |
949 | ||
950 | /* position of active request inside the ring */ | |
951 | u32 rq_head, rq_post, rq_tail; | |
952 | ||
953 | /* our own tracking of ring head and tail */ | |
954 | u32 cpu_ring_head; | |
955 | u32 cpu_ring_tail; | |
956 | ||
957 | u32 last_seqno; | |
958 | ||
959 | /* Register state */ | |
960 | u32 start; | |
961 | u32 tail; | |
962 | u32 head; | |
963 | u32 ctl; | |
964 | u32 mode; | |
965 | u32 hws; | |
966 | u32 ipeir; | |
967 | u32 ipehr; | |
968 | u32 bbstate; | |
969 | u32 instpm; | |
970 | u32 instps; | |
971 | u32 seqno; | |
972 | u64 bbaddr; | |
973 | u64 acthd; | |
974 | u32 fault_reg; | |
975 | u64 faddr; | |
976 | u32 rc_psmi; /* sleep state */ | |
977 | u32 semaphore_mboxes[I915_NUM_ENGINES - 1]; | |
978 | struct intel_instdone instdone; | |
979 | ||
980 | struct drm_i915_error_context { | |
981 | char comm[TASK_COMM_LEN]; | |
982 | pid_t pid; | |
983 | u32 handle; | |
984 | u32 hw_id; | |
985 | int ban_score; | |
986 | int active; | |
987 | int guilty; | |
988 | } context; | |
989 | ||
990 | struct drm_i915_error_object { | |
991 | u64 gtt_offset; | |
992 | u64 gtt_size; | |
993 | int page_count; | |
994 | int unused; | |
995 | u32 *pages[0]; | |
996 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; | |
997 | ||
998 | struct drm_i915_error_object **user_bo; | |
999 | long user_bo_count; | |
1000 | ||
1001 | struct drm_i915_error_object *wa_ctx; | |
1002 | ||
1003 | struct drm_i915_error_request { | |
1004 | long jiffies; | |
1005 | pid_t pid; | |
1006 | u32 context; | |
1007 | int ban_score; | |
1008 | u32 seqno; | |
1009 | u32 head; | |
1010 | u32 tail; | |
1011 | } *requests, execlist[EXECLIST_MAX_PORTS]; | |
1012 | unsigned int num_ports; | |
1013 | ||
1014 | struct drm_i915_error_waiter { | |
1015 | char comm[TASK_COMM_LEN]; | |
1016 | pid_t pid; | |
1017 | u32 seqno; | |
1018 | } *waiters; | |
1019 | ||
1020 | struct { | |
1021 | u32 gfx_mode; | |
1022 | union { | |
1023 | u64 pdp[4]; | |
1024 | u32 pp_dir_base; | |
1025 | }; | |
1026 | } vm_info; | |
1027 | } engine[I915_NUM_ENGINES]; | |
1028 | ||
1029 | struct drm_i915_error_buffer { | |
1030 | u32 size; | |
1031 | u32 name; | |
1032 | u32 rseqno[I915_NUM_ENGINES], wseqno; | |
1033 | u64 gtt_offset; | |
1034 | u32 read_domains; | |
1035 | u32 write_domain; | |
1036 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; | |
1037 | u32 tiling:2; | |
1038 | u32 dirty:1; | |
1039 | u32 purgeable:1; | |
1040 | u32 userptr:1; | |
1041 | s32 engine:4; | |
1042 | u32 cache_level:3; | |
1043 | } *active_bo[I915_NUM_ENGINES], *pinned_bo; | |
1044 | u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count; | |
1045 | struct i915_address_space *active_vm[I915_NUM_ENGINES]; | |
1046 | }; | |
1047 | ||
1048 | enum i915_cache_level { | |
1049 | I915_CACHE_NONE = 0, | |
1050 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ | |
1051 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
1052 | caches, eg sampler/render caches, and the | |
1053 | large Last-Level-Cache. LLC is coherent with | |
1054 | the CPU, but L3 is only visible to the GPU. */ | |
1055 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ | |
1056 | }; | |
1057 | ||
1058 | #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */ | |
1059 | ||
1060 | enum fb_op_origin { | |
1061 | ORIGIN_GTT, | |
1062 | ORIGIN_CPU, | |
1063 | ORIGIN_CS, | |
1064 | ORIGIN_FLIP, | |
1065 | ORIGIN_DIRTYFB, | |
1066 | }; | |
1067 | ||
1068 | struct intel_fbc { | |
1069 | /* This is always the inner lock when overlapping with struct_mutex and | |
1070 | * it's the outer lock when overlapping with stolen_lock. */ | |
1071 | struct mutex lock; | |
1072 | unsigned threshold; | |
1073 | unsigned int possible_framebuffer_bits; | |
1074 | unsigned int busy_bits; | |
1075 | unsigned int visible_pipes_mask; | |
1076 | struct intel_crtc *crtc; | |
1077 | ||
1078 | struct drm_mm_node compressed_fb; | |
1079 | struct drm_mm_node *compressed_llb; | |
1080 | ||
1081 | bool false_color; | |
1082 | ||
1083 | bool enabled; | |
1084 | bool active; | |
1085 | ||
1086 | bool underrun_detected; | |
1087 | struct work_struct underrun_work; | |
1088 | ||
1089 | /* | |
1090 | * Due to the atomic rules we can't access some structures without the | |
1091 | * appropriate locking, so we cache information here in order to avoid | |
1092 | * these problems. | |
1093 | */ | |
1094 | struct intel_fbc_state_cache { | |
1095 | struct i915_vma *vma; | |
1096 | ||
1097 | struct { | |
1098 | unsigned int mode_flags; | |
1099 | uint32_t hsw_bdw_pixel_rate; | |
1100 | } crtc; | |
1101 | ||
1102 | struct { | |
1103 | unsigned int rotation; | |
1104 | int src_w; | |
1105 | int src_h; | |
1106 | bool visible; | |
1107 | } plane; | |
1108 | ||
1109 | struct { | |
1110 | const struct drm_format_info *format; | |
1111 | unsigned int stride; | |
1112 | } fb; | |
1113 | } state_cache; | |
1114 | ||
1115 | /* | |
1116 | * This structure contains everything that's relevant to program the | |
1117 | * hardware registers. When we want to figure out if we need to disable | |
1118 | * and re-enable FBC for a new configuration we just check if there's | |
1119 | * something different in the struct. The genx_fbc_activate functions | |
1120 | * are supposed to read from it in order to program the registers. | |
1121 | */ | |
1122 | struct intel_fbc_reg_params { | |
1123 | struct i915_vma *vma; | |
1124 | ||
1125 | struct { | |
1126 | enum pipe pipe; | |
1127 | enum plane plane; | |
1128 | unsigned int fence_y_offset; | |
1129 | } crtc; | |
1130 | ||
1131 | struct { | |
1132 | const struct drm_format_info *format; | |
1133 | unsigned int stride; | |
1134 | } fb; | |
1135 | ||
1136 | int cfb_size; | |
1137 | unsigned int gen9_wa_cfb_stride; | |
1138 | } params; | |
1139 | ||
1140 | struct intel_fbc_work { | |
1141 | bool scheduled; | |
1142 | u32 scheduled_vblank; | |
1143 | struct work_struct work; | |
1144 | } work; | |
1145 | ||
1146 | const char *no_fbc_reason; | |
1147 | }; | |
1148 | ||
1149 | /* | |
1150 | * HIGH_RR is the highest eDP panel refresh rate read from EDID | |
1151 | * LOW_RR is the lowest eDP panel refresh rate found from EDID | |
1152 | * parsing for same resolution. | |
1153 | */ | |
1154 | enum drrs_refresh_rate_type { | |
1155 | DRRS_HIGH_RR, | |
1156 | DRRS_LOW_RR, | |
1157 | DRRS_MAX_RR, /* RR count */ | |
1158 | }; | |
1159 | ||
1160 | enum drrs_support_type { | |
1161 | DRRS_NOT_SUPPORTED = 0, | |
1162 | STATIC_DRRS_SUPPORT = 1, | |
1163 | SEAMLESS_DRRS_SUPPORT = 2 | |
1164 | }; | |
1165 | ||
1166 | struct intel_dp; | |
1167 | struct i915_drrs { | |
1168 | struct mutex mutex; | |
1169 | struct delayed_work work; | |
1170 | struct intel_dp *dp; | |
1171 | unsigned busy_frontbuffer_bits; | |
1172 | enum drrs_refresh_rate_type refresh_rate_type; | |
1173 | enum drrs_support_type type; | |
1174 | }; | |
1175 | ||
1176 | struct i915_psr { | |
1177 | struct mutex lock; | |
1178 | bool sink_support; | |
1179 | bool source_ok; | |
1180 | struct intel_dp *enabled; | |
1181 | bool active; | |
1182 | struct delayed_work work; | |
1183 | unsigned busy_frontbuffer_bits; | |
1184 | bool psr2_support; | |
1185 | bool aux_frame_sync; | |
1186 | bool link_standby; | |
1187 | bool y_cord_support; | |
1188 | bool colorimetry_support; | |
1189 | bool alpm; | |
1190 | ||
1191 | void (*enable_source)(struct intel_dp *, | |
1192 | const struct intel_crtc_state *); | |
1193 | void (*disable_source)(struct intel_dp *, | |
1194 | const struct intel_crtc_state *); | |
1195 | void (*enable_sink)(struct intel_dp *); | |
1196 | void (*activate)(struct intel_dp *); | |
1197 | void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *); | |
1198 | }; | |
1199 | ||
1200 | enum intel_pch { | |
1201 | PCH_NONE = 0, /* No PCH present */ | |
1202 | PCH_IBX, /* Ibexpeak PCH */ | |
1203 | PCH_CPT, /* Cougarpoint/Pantherpoint PCH */ | |
1204 | PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */ | |
1205 | PCH_SPT, /* Sunrisepoint PCH */ | |
1206 | PCH_KBP, /* Kaby Lake PCH */ | |
1207 | PCH_CNP, /* Cannon Lake PCH */ | |
1208 | PCH_NOP, | |
1209 | }; | |
1210 | ||
1211 | enum intel_sbi_destination { | |
1212 | SBI_ICLK, | |
1213 | SBI_MPHY, | |
1214 | }; | |
1215 | ||
1216 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) | |
1217 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) | |
1218 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) | |
1219 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) | |
1220 | #define QUIRK_INCREASE_T12_DELAY (1<<6) | |
1221 | ||
1222 | struct intel_fbdev; | |
1223 | struct intel_fbc_work; | |
1224 | ||
1225 | struct intel_gmbus { | |
1226 | struct i2c_adapter adapter; | |
1227 | #define GMBUS_FORCE_BIT_RETRY (1U << 31) | |
1228 | u32 force_bit; | |
1229 | u32 reg0; | |
1230 | i915_reg_t gpio_reg; | |
1231 | struct i2c_algo_bit_data bit_algo; | |
1232 | struct drm_i915_private *dev_priv; | |
1233 | }; | |
1234 | ||
1235 | struct i915_suspend_saved_registers { | |
1236 | u32 saveDSPARB; | |
1237 | u32 saveFBC_CONTROL; | |
1238 | u32 saveCACHE_MODE_0; | |
1239 | u32 saveMI_ARB_STATE; | |
1240 | u32 saveSWF0[16]; | |
1241 | u32 saveSWF1[16]; | |
1242 | u32 saveSWF3[3]; | |
1243 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; | |
1244 | u32 savePCH_PORT_HOTPLUG; | |
1245 | u16 saveGCDGMBUS; | |
1246 | }; | |
1247 | ||
1248 | struct vlv_s0ix_state { | |
1249 | /* GAM */ | |
1250 | u32 wr_watermark; | |
1251 | u32 gfx_prio_ctrl; | |
1252 | u32 arb_mode; | |
1253 | u32 gfx_pend_tlb0; | |
1254 | u32 gfx_pend_tlb1; | |
1255 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; | |
1256 | u32 media_max_req_count; | |
1257 | u32 gfx_max_req_count; | |
1258 | u32 render_hwsp; | |
1259 | u32 ecochk; | |
1260 | u32 bsd_hwsp; | |
1261 | u32 blt_hwsp; | |
1262 | u32 tlb_rd_addr; | |
1263 | ||
1264 | /* MBC */ | |
1265 | u32 g3dctl; | |
1266 | u32 gsckgctl; | |
1267 | u32 mbctl; | |
1268 | ||
1269 | /* GCP */ | |
1270 | u32 ucgctl1; | |
1271 | u32 ucgctl3; | |
1272 | u32 rcgctl1; | |
1273 | u32 rcgctl2; | |
1274 | u32 rstctl; | |
1275 | u32 misccpctl; | |
1276 | ||
1277 | /* GPM */ | |
1278 | u32 gfxpause; | |
1279 | u32 rpdeuhwtc; | |
1280 | u32 rpdeuc; | |
1281 | u32 ecobus; | |
1282 | u32 pwrdwnupctl; | |
1283 | u32 rp_down_timeout; | |
1284 | u32 rp_deucsw; | |
1285 | u32 rcubmabdtmr; | |
1286 | u32 rcedata; | |
1287 | u32 spare2gh; | |
1288 | ||
1289 | /* Display 1 CZ domain */ | |
1290 | u32 gt_imr; | |
1291 | u32 gt_ier; | |
1292 | u32 pm_imr; | |
1293 | u32 pm_ier; | |
1294 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; | |
1295 | ||
1296 | /* GT SA CZ domain */ | |
1297 | u32 tilectl; | |
1298 | u32 gt_fifoctl; | |
1299 | u32 gtlc_wake_ctrl; | |
1300 | u32 gtlc_survive; | |
1301 | u32 pmwgicz; | |
1302 | ||
1303 | /* Display 2 CZ domain */ | |
1304 | u32 gu_ctl0; | |
1305 | u32 gu_ctl1; | |
1306 | u32 pcbr; | |
1307 | u32 clock_gate_dis2; | |
1308 | }; | |
1309 | ||
1310 | struct intel_rps_ei { | |
1311 | ktime_t ktime; | |
1312 | u32 render_c0; | |
1313 | u32 media_c0; | |
1314 | }; | |
1315 | ||
1316 | struct intel_gen6_power_mgmt { | |
1317 | /* | |
1318 | * work, interrupts_enabled and pm_iir are protected by | |
1319 | * dev_priv->irq_lock | |
1320 | */ | |
1321 | struct work_struct work; | |
1322 | bool interrupts_enabled; | |
1323 | u32 pm_iir; | |
1324 | ||
1325 | /* PM interrupt bits that should never be masked */ | |
1326 | u32 pm_intrmsk_mbz; | |
1327 | ||
1328 | /* Frequencies are stored in potentially platform dependent multiples. | |
1329 | * In other words, *_freq needs to be multiplied by X to be interesting. | |
1330 | * Soft limits are those which are used for the dynamic reclocking done | |
1331 | * by the driver (raise frequencies under heavy loads, and lower for | |
1332 | * lighter loads). Hard limits are those imposed by the hardware. | |
1333 | * | |
1334 | * A distinction is made for overclocking, which is never enabled by | |
1335 | * default, and is considered to be above the hard limit if it's | |
1336 | * possible at all. | |
1337 | */ | |
1338 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ | |
1339 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ | |
1340 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ | |
1341 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ | |
1342 | u8 min_freq; /* AKA RPn. Minimum frequency */ | |
1343 | u8 boost_freq; /* Frequency to request when wait boosting */ | |
1344 | u8 idle_freq; /* Frequency to request when we are idle */ | |
1345 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ | |
1346 | u8 rp1_freq; /* "less than" RP0 power/freqency */ | |
1347 | u8 rp0_freq; /* Non-overclocked max frequency. */ | |
1348 | u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */ | |
1349 | ||
1350 | u8 up_threshold; /* Current %busy required to uplock */ | |
1351 | u8 down_threshold; /* Current %busy required to downclock */ | |
1352 | ||
1353 | int last_adj; | |
1354 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; | |
1355 | ||
1356 | bool enabled; | |
1357 | struct delayed_work autoenable_work; | |
1358 | atomic_t num_waiters; | |
1359 | atomic_t boosts; | |
1360 | ||
1361 | /* manual wa residency calculations */ | |
1362 | struct intel_rps_ei ei; | |
1363 | ||
1364 | /* | |
1365 | * Protects RPS/RC6 register access and PCU communication. | |
1366 | * Must be taken after struct_mutex if nested. Note that | |
1367 | * this lock may be held for long periods of time when | |
1368 | * talking to hw - so only take it when talking to hw! | |
1369 | */ | |
1370 | struct mutex hw_lock; | |
1371 | }; | |
1372 | ||
1373 | /* defined intel_pm.c */ | |
1374 | extern spinlock_t mchdev_lock; | |
1375 | ||
1376 | struct intel_ilk_power_mgmt { | |
1377 | u8 cur_delay; | |
1378 | u8 min_delay; | |
1379 | u8 max_delay; | |
1380 | u8 fmax; | |
1381 | u8 fstart; | |
1382 | ||
1383 | u64 last_count1; | |
1384 | unsigned long last_time1; | |
1385 | unsigned long chipset_power; | |
1386 | u64 last_count2; | |
1387 | u64 last_time2; | |
1388 | unsigned long gfx_power; | |
1389 | u8 corr; | |
1390 | ||
1391 | int c_m; | |
1392 | int r_t; | |
1393 | }; | |
1394 | ||
1395 | struct drm_i915_private; | |
1396 | struct i915_power_well; | |
1397 | ||
1398 | struct i915_power_well_ops { | |
1399 | /* | |
1400 | * Synchronize the well's hw state to match the current sw state, for | |
1401 | * example enable/disable it based on the current refcount. Called | |
1402 | * during driver init and resume time, possibly after first calling | |
1403 | * the enable/disable handlers. | |
1404 | */ | |
1405 | void (*sync_hw)(struct drm_i915_private *dev_priv, | |
1406 | struct i915_power_well *power_well); | |
1407 | /* | |
1408 | * Enable the well and resources that depend on it (for example | |
1409 | * interrupts located on the well). Called after the 0->1 refcount | |
1410 | * transition. | |
1411 | */ | |
1412 | void (*enable)(struct drm_i915_private *dev_priv, | |
1413 | struct i915_power_well *power_well); | |
1414 | /* | |
1415 | * Disable the well and resources that depend on it. Called after | |
1416 | * the 1->0 refcount transition. | |
1417 | */ | |
1418 | void (*disable)(struct drm_i915_private *dev_priv, | |
1419 | struct i915_power_well *power_well); | |
1420 | /* Returns the hw enabled state. */ | |
1421 | bool (*is_enabled)(struct drm_i915_private *dev_priv, | |
1422 | struct i915_power_well *power_well); | |
1423 | }; | |
1424 | ||
1425 | /* Power well structure for haswell */ | |
1426 | struct i915_power_well { | |
1427 | const char *name; | |
1428 | bool always_on; | |
1429 | /* power well enable/disable usage count */ | |
1430 | int count; | |
1431 | /* cached hw enabled state */ | |
1432 | bool hw_enabled; | |
1433 | u64 domains; | |
1434 | /* unique identifier for this power well */ | |
1435 | enum i915_power_well_id id; | |
1436 | /* | |
1437 | * Arbitraty data associated with this power well. Platform and power | |
1438 | * well specific. | |
1439 | */ | |
1440 | union { | |
1441 | struct { | |
1442 | enum dpio_phy phy; | |
1443 | } bxt; | |
1444 | struct { | |
1445 | /* Mask of pipes whose IRQ logic is backed by the pw */ | |
1446 | u8 irq_pipe_mask; | |
1447 | /* The pw is backing the VGA functionality */ | |
1448 | bool has_vga:1; | |
1449 | bool has_fuses:1; | |
1450 | } hsw; | |
1451 | }; | |
1452 | const struct i915_power_well_ops *ops; | |
1453 | }; | |
1454 | ||
1455 | struct i915_power_domains { | |
1456 | /* | |
1457 | * Power wells needed for initialization at driver init and suspend | |
1458 | * time are on. They are kept on until after the first modeset. | |
1459 | */ | |
1460 | bool init_power_on; | |
1461 | bool initializing; | |
1462 | int power_well_count; | |
1463 | ||
1464 | struct mutex lock; | |
1465 | int domain_use_count[POWER_DOMAIN_NUM]; | |
1466 | struct i915_power_well *power_wells; | |
1467 | }; | |
1468 | ||
1469 | #define MAX_L3_SLICES 2 | |
1470 | struct intel_l3_parity { | |
1471 | u32 *remap_info[MAX_L3_SLICES]; | |
1472 | struct work_struct error_work; | |
1473 | int which_slice; | |
1474 | }; | |
1475 | ||
1476 | struct i915_gem_mm { | |
1477 | /** Memory allocator for GTT stolen memory */ | |
1478 | struct drm_mm stolen; | |
1479 | /** Protects the usage of the GTT stolen memory allocator. This is | |
1480 | * always the inner lock when overlapping with struct_mutex. */ | |
1481 | struct mutex stolen_lock; | |
1482 | ||
1483 | /** List of all objects in gtt_space. Used to restore gtt | |
1484 | * mappings on resume */ | |
1485 | struct list_head bound_list; | |
1486 | /** | |
1487 | * List of objects which are not bound to the GTT (thus | |
1488 | * are idle and not used by the GPU). These objects may or may | |
1489 | * not actually have any pages attached. | |
1490 | */ | |
1491 | struct list_head unbound_list; | |
1492 | ||
1493 | /** List of all objects in gtt_space, currently mmaped by userspace. | |
1494 | * All objects within this list must also be on bound_list. | |
1495 | */ | |
1496 | struct list_head userfault_list; | |
1497 | ||
1498 | /** | |
1499 | * List of objects which are pending destruction. | |
1500 | */ | |
1501 | struct llist_head free_list; | |
1502 | struct work_struct free_work; | |
1503 | ||
1504 | /** | |
1505 | * Small stash of WC pages | |
1506 | */ | |
1507 | struct pagevec wc_stash; | |
1508 | ||
1509 | /** Usable portion of the GTT for GEM */ | |
1510 | dma_addr_t stolen_base; /* limited to low memory (32-bit) */ | |
1511 | ||
1512 | /** PPGTT used for aliasing the PPGTT with the GTT */ | |
1513 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
1514 | ||
1515 | struct notifier_block oom_notifier; | |
1516 | struct notifier_block vmap_notifier; | |
1517 | struct shrinker shrinker; | |
1518 | ||
1519 | /** LRU list of objects with fence regs on them. */ | |
1520 | struct list_head fence_list; | |
1521 | ||
1522 | /** | |
1523 | * Workqueue to fault in userptr pages, flushed by the execbuf | |
1524 | * when required but otherwise left to userspace to try again | |
1525 | * on EAGAIN. | |
1526 | */ | |
1527 | struct workqueue_struct *userptr_wq; | |
1528 | ||
1529 | u64 unordered_timeline; | |
1530 | ||
1531 | /* the indicator for dispatch video commands on two BSD rings */ | |
1532 | atomic_t bsd_engine_dispatch_index; | |
1533 | ||
1534 | /** Bit 6 swizzling required for X tiling */ | |
1535 | uint32_t bit_6_swizzle_x; | |
1536 | /** Bit 6 swizzling required for Y tiling */ | |
1537 | uint32_t bit_6_swizzle_y; | |
1538 | ||
1539 | /* accounting, useful for userland debugging */ | |
1540 | spinlock_t object_stat_lock; | |
1541 | u64 object_memory; | |
1542 | u32 object_count; | |
1543 | }; | |
1544 | ||
1545 | struct drm_i915_error_state_buf { | |
1546 | struct drm_i915_private *i915; | |
1547 | unsigned bytes; | |
1548 | unsigned size; | |
1549 | int err; | |
1550 | u8 *buf; | |
1551 | loff_t start; | |
1552 | loff_t pos; | |
1553 | }; | |
1554 | ||
1555 | #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */ | |
1556 | #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */ | |
1557 | ||
1558 | #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */ | |
1559 | #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */ | |
1560 | ||
1561 | struct i915_gpu_error { | |
1562 | /* For hangcheck timer */ | |
1563 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
1564 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
1565 | ||
1566 | struct delayed_work hangcheck_work; | |
1567 | ||
1568 | /* For reset and error_state handling. */ | |
1569 | spinlock_t lock; | |
1570 | /* Protected by the above dev->gpu_error.lock. */ | |
1571 | struct i915_gpu_state *first_error; | |
1572 | ||
1573 | atomic_t pending_fb_pin; | |
1574 | ||
1575 | unsigned long missed_irq_rings; | |
1576 | ||
1577 | /** | |
1578 | * State variable controlling the reset flow and count | |
1579 | * | |
1580 | * This is a counter which gets incremented when reset is triggered, | |
1581 | * | |
1582 | * Before the reset commences, the I915_RESET_BACKOFF bit is set | |
1583 | * meaning that any waiters holding onto the struct_mutex should | |
1584 | * relinquish the lock immediately in order for the reset to start. | |
1585 | * | |
1586 | * If reset is not completed succesfully, the I915_WEDGE bit is | |
1587 | * set meaning that hardware is terminally sour and there is no | |
1588 | * recovery. All waiters on the reset_queue will be woken when | |
1589 | * that happens. | |
1590 | * | |
1591 | * This counter is used by the wait_seqno code to notice that reset | |
1592 | * event happened and it needs to restart the entire ioctl (since most | |
1593 | * likely the seqno it waited for won't ever signal anytime soon). | |
1594 | * | |
1595 | * This is important for lock-free wait paths, where no contended lock | |
1596 | * naturally enforces the correct ordering between the bail-out of the | |
1597 | * waiter and the gpu reset work code. | |
1598 | */ | |
1599 | unsigned long reset_count; | |
1600 | ||
1601 | /** | |
1602 | * flags: Control various stages of the GPU reset | |
1603 | * | |
1604 | * #I915_RESET_BACKOFF - When we start a reset, we want to stop any | |
1605 | * other users acquiring the struct_mutex. To do this we set the | |
1606 | * #I915_RESET_BACKOFF bit in the error flags when we detect a reset | |
1607 | * and then check for that bit before acquiring the struct_mutex (in | |
1608 | * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a | |
1609 | * secondary role in preventing two concurrent global reset attempts. | |
1610 | * | |
1611 | * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the | |
1612 | * struct_mutex. We try to acquire the struct_mutex in the reset worker, | |
1613 | * but it may be held by some long running waiter (that we cannot | |
1614 | * interrupt without causing trouble). Once we are ready to do the GPU | |
1615 | * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If | |
1616 | * they already hold the struct_mutex and want to participate they can | |
1617 | * inspect the bit and do the reset directly, otherwise the worker | |
1618 | * waits for the struct_mutex. | |
1619 | * | |
1620 | * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to | |
1621 | * acquire the struct_mutex to reset an engine, we need an explicit | |
1622 | * flag to prevent two concurrent reset attempts in the same engine. | |
1623 | * As the number of engines continues to grow, allocate the flags from | |
1624 | * the most significant bits. | |
1625 | * | |
1626 | * #I915_WEDGED - If reset fails and we can no longer use the GPU, | |
1627 | * we set the #I915_WEDGED bit. Prior to command submission, e.g. | |
1628 | * i915_gem_request_alloc(), this bit is checked and the sequence | |
1629 | * aborted (with -EIO reported to userspace) if set. | |
1630 | */ | |
1631 | unsigned long flags; | |
1632 | #define I915_RESET_BACKOFF 0 | |
1633 | #define I915_RESET_HANDOFF 1 | |
1634 | #define I915_RESET_MODESET 2 | |
1635 | #define I915_WEDGED (BITS_PER_LONG - 1) | |
1636 | #define I915_RESET_ENGINE (I915_WEDGED - I915_NUM_ENGINES) | |
1637 | ||
1638 | /** Number of times an engine has been reset */ | |
1639 | u32 reset_engine_count[I915_NUM_ENGINES]; | |
1640 | ||
1641 | /** | |
1642 | * Waitqueue to signal when a hang is detected. Used to for waiters | |
1643 | * to release the struct_mutex for the reset to procede. | |
1644 | */ | |
1645 | wait_queue_head_t wait_queue; | |
1646 | ||
1647 | /** | |
1648 | * Waitqueue to signal when the reset has completed. Used by clients | |
1649 | * that wait for dev_priv->mm.wedged to settle. | |
1650 | */ | |
1651 | wait_queue_head_t reset_queue; | |
1652 | ||
1653 | /* For missed irq/seqno simulation. */ | |
1654 | unsigned long test_irq_rings; | |
1655 | }; | |
1656 | ||
1657 | enum modeset_restore { | |
1658 | MODESET_ON_LID_OPEN, | |
1659 | MODESET_DONE, | |
1660 | MODESET_SUSPENDED, | |
1661 | }; | |
1662 | ||
1663 | #define DP_AUX_A 0x40 | |
1664 | #define DP_AUX_B 0x10 | |
1665 | #define DP_AUX_C 0x20 | |
1666 | #define DP_AUX_D 0x30 | |
1667 | ||
1668 | #define DDC_PIN_B 0x05 | |
1669 | #define DDC_PIN_C 0x04 | |
1670 | #define DDC_PIN_D 0x06 | |
1671 | ||
1672 | struct ddi_vbt_port_info { | |
1673 | /* | |
1674 | * This is an index in the HDMI/DVI DDI buffer translation table. | |
1675 | * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't | |
1676 | * populate this field. | |
1677 | */ | |
1678 | #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff | |
1679 | uint8_t hdmi_level_shift; | |
1680 | ||
1681 | uint8_t supports_dvi:1; | |
1682 | uint8_t supports_hdmi:1; | |
1683 | uint8_t supports_dp:1; | |
1684 | uint8_t supports_edp:1; | |
1685 | ||
1686 | uint8_t alternate_aux_channel; | |
1687 | uint8_t alternate_ddc_pin; | |
1688 | ||
1689 | uint8_t dp_boost_level; | |
1690 | uint8_t hdmi_boost_level; | |
1691 | }; | |
1692 | ||
1693 | enum psr_lines_to_wait { | |
1694 | PSR_0_LINES_TO_WAIT = 0, | |
1695 | PSR_1_LINE_TO_WAIT, | |
1696 | PSR_4_LINES_TO_WAIT, | |
1697 | PSR_8_LINES_TO_WAIT | |
1698 | }; | |
1699 | ||
1700 | struct intel_vbt_data { | |
1701 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1702 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1703 | ||
1704 | /* Feature bits */ | |
1705 | unsigned int int_tv_support:1; | |
1706 | unsigned int lvds_dither:1; | |
1707 | unsigned int lvds_vbt:1; | |
1708 | unsigned int int_crt_support:1; | |
1709 | unsigned int lvds_use_ssc:1; | |
1710 | unsigned int display_clock_mode:1; | |
1711 | unsigned int fdi_rx_polarity_inverted:1; | |
1712 | unsigned int panel_type:4; | |
1713 | int lvds_ssc_freq; | |
1714 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1715 | ||
1716 | enum drrs_support_type drrs_type; | |
1717 | ||
1718 | struct { | |
1719 | int rate; | |
1720 | int lanes; | |
1721 | int preemphasis; | |
1722 | int vswing; | |
1723 | bool low_vswing; | |
1724 | bool initialized; | |
1725 | bool support; | |
1726 | int bpp; | |
1727 | struct edp_power_seq pps; | |
1728 | } edp; | |
1729 | ||
1730 | struct { | |
1731 | bool full_link; | |
1732 | bool require_aux_wakeup; | |
1733 | int idle_frames; | |
1734 | enum psr_lines_to_wait lines_to_wait; | |
1735 | int tp1_wakeup_time; | |
1736 | int tp2_tp3_wakeup_time; | |
1737 | } psr; | |
1738 | ||
1739 | struct { | |
1740 | u16 pwm_freq_hz; | |
1741 | bool present; | |
1742 | bool active_low_pwm; | |
1743 | u8 min_brightness; /* min_brightness/255 of max */ | |
1744 | u8 controller; /* brightness controller number */ | |
1745 | enum intel_backlight_type type; | |
1746 | } backlight; | |
1747 | ||
1748 | /* MIPI DSI */ | |
1749 | struct { | |
1750 | u16 panel_id; | |
1751 | struct mipi_config *config; | |
1752 | struct mipi_pps_data *pps; | |
1753 | u8 seq_version; | |
1754 | u32 size; | |
1755 | u8 *data; | |
1756 | const u8 *sequence[MIPI_SEQ_MAX]; | |
1757 | } dsi; | |
1758 | ||
1759 | int crt_ddc_pin; | |
1760 | ||
1761 | int child_dev_num; | |
1762 | struct child_device_config *child_dev; | |
1763 | ||
1764 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
1765 | struct sdvo_device_mapping sdvo_mappings[2]; | |
1766 | }; | |
1767 | ||
1768 | enum intel_ddb_partitioning { | |
1769 | INTEL_DDB_PART_1_2, | |
1770 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1771 | }; | |
1772 | ||
1773 | struct intel_wm_level { | |
1774 | bool enable; | |
1775 | uint32_t pri_val; | |
1776 | uint32_t spr_val; | |
1777 | uint32_t cur_val; | |
1778 | uint32_t fbc_val; | |
1779 | }; | |
1780 | ||
1781 | struct ilk_wm_values { | |
1782 | uint32_t wm_pipe[3]; | |
1783 | uint32_t wm_lp[3]; | |
1784 | uint32_t wm_lp_spr[3]; | |
1785 | uint32_t wm_linetime[3]; | |
1786 | bool enable_fbc_wm; | |
1787 | enum intel_ddb_partitioning partitioning; | |
1788 | }; | |
1789 | ||
1790 | struct g4x_pipe_wm { | |
1791 | uint16_t plane[I915_MAX_PLANES]; | |
1792 | uint16_t fbc; | |
1793 | }; | |
1794 | ||
1795 | struct g4x_sr_wm { | |
1796 | uint16_t plane; | |
1797 | uint16_t cursor; | |
1798 | uint16_t fbc; | |
1799 | }; | |
1800 | ||
1801 | struct vlv_wm_ddl_values { | |
1802 | uint8_t plane[I915_MAX_PLANES]; | |
1803 | }; | |
1804 | ||
1805 | struct vlv_wm_values { | |
1806 | struct g4x_pipe_wm pipe[3]; | |
1807 | struct g4x_sr_wm sr; | |
1808 | struct vlv_wm_ddl_values ddl[3]; | |
1809 | uint8_t level; | |
1810 | bool cxsr; | |
1811 | }; | |
1812 | ||
1813 | struct g4x_wm_values { | |
1814 | struct g4x_pipe_wm pipe[2]; | |
1815 | struct g4x_sr_wm sr; | |
1816 | struct g4x_sr_wm hpll; | |
1817 | bool cxsr; | |
1818 | bool hpll_en; | |
1819 | bool fbc_en; | |
1820 | }; | |
1821 | ||
1822 | struct skl_ddb_entry { | |
1823 | uint16_t start, end; /* in number of blocks, 'end' is exclusive */ | |
1824 | }; | |
1825 | ||
1826 | static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) | |
1827 | { | |
1828 | return entry->end - entry->start; | |
1829 | } | |
1830 | ||
1831 | static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, | |
1832 | const struct skl_ddb_entry *e2) | |
1833 | { | |
1834 | if (e1->start == e2->start && e1->end == e2->end) | |
1835 | return true; | |
1836 | ||
1837 | return false; | |
1838 | } | |
1839 | ||
1840 | struct skl_ddb_allocation { | |
1841 | struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */ | |
1842 | struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; | |
1843 | }; | |
1844 | ||
1845 | struct skl_wm_values { | |
1846 | unsigned dirty_pipes; | |
1847 | struct skl_ddb_allocation ddb; | |
1848 | }; | |
1849 | ||
1850 | struct skl_wm_level { | |
1851 | bool plane_en; | |
1852 | uint16_t plane_res_b; | |
1853 | uint8_t plane_res_l; | |
1854 | }; | |
1855 | ||
1856 | /* Stores plane specific WM parameters */ | |
1857 | struct skl_wm_params { | |
1858 | bool x_tiled, y_tiled; | |
1859 | bool rc_surface; | |
1860 | uint32_t width; | |
1861 | uint8_t cpp; | |
1862 | uint32_t plane_pixel_rate; | |
1863 | uint32_t y_min_scanlines; | |
1864 | uint32_t plane_bytes_per_line; | |
1865 | uint_fixed_16_16_t plane_blocks_per_line; | |
1866 | uint_fixed_16_16_t y_tile_minimum; | |
1867 | uint32_t linetime_us; | |
1868 | }; | |
1869 | ||
1870 | /* | |
1871 | * This struct helps tracking the state needed for runtime PM, which puts the | |
1872 | * device in PCI D3 state. Notice that when this happens, nothing on the | |
1873 | * graphics device works, even register access, so we don't get interrupts nor | |
1874 | * anything else. | |
1875 | * | |
1876 | * Every piece of our code that needs to actually touch the hardware needs to | |
1877 | * either call intel_runtime_pm_get or call intel_display_power_get with the | |
1878 | * appropriate power domain. | |
1879 | * | |
1880 | * Our driver uses the autosuspend delay feature, which means we'll only really | |
1881 | * suspend if we stay with zero refcount for a certain amount of time. The | |
1882 | * default value is currently very conservative (see intel_runtime_pm_enable), but | |
1883 | * it can be changed with the standard runtime PM files from sysfs. | |
1884 | * | |
1885 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1886 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1887 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1888 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
1889 | * case it happens. | |
1890 | * | |
1891 | * For more, read the Documentation/power/runtime_pm.txt. | |
1892 | */ | |
1893 | struct i915_runtime_pm { | |
1894 | atomic_t wakeref_count; | |
1895 | bool suspended; | |
1896 | bool irqs_enabled; | |
1897 | }; | |
1898 | ||
1899 | enum intel_pipe_crc_source { | |
1900 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1901 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1902 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1903 | INTEL_PIPE_CRC_SOURCE_PF, | |
1904 | INTEL_PIPE_CRC_SOURCE_PIPE, | |
1905 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ | |
1906 | INTEL_PIPE_CRC_SOURCE_TV, | |
1907 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1908 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1909 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
1910 | INTEL_PIPE_CRC_SOURCE_AUTO, | |
1911 | INTEL_PIPE_CRC_SOURCE_MAX, | |
1912 | }; | |
1913 | ||
1914 | struct intel_pipe_crc_entry { | |
1915 | uint32_t frame; | |
1916 | uint32_t crc[5]; | |
1917 | }; | |
1918 | ||
1919 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 | |
1920 | struct intel_pipe_crc { | |
1921 | spinlock_t lock; | |
1922 | bool opened; /* exclusive access to the result file */ | |
1923 | struct intel_pipe_crc_entry *entries; | |
1924 | enum intel_pipe_crc_source source; | |
1925 | int head, tail; | |
1926 | wait_queue_head_t wq; | |
1927 | int skipped; | |
1928 | }; | |
1929 | ||
1930 | struct i915_frontbuffer_tracking { | |
1931 | spinlock_t lock; | |
1932 | ||
1933 | /* | |
1934 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or | |
1935 | * scheduled flips. | |
1936 | */ | |
1937 | unsigned busy_bits; | |
1938 | unsigned flip_bits; | |
1939 | }; | |
1940 | ||
1941 | struct i915_wa_reg { | |
1942 | i915_reg_t addr; | |
1943 | u32 value; | |
1944 | /* bitmask representing WA bits */ | |
1945 | u32 mask; | |
1946 | }; | |
1947 | ||
1948 | /* | |
1949 | * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only | |
1950 | * allowing it for RCS as we don't foresee any requirement of having | |
1951 | * a whitelist for other engines. When it is really required for | |
1952 | * other engines then the limit need to be increased. | |
1953 | */ | |
1954 | #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS) | |
1955 | ||
1956 | struct i915_workarounds { | |
1957 | struct i915_wa_reg reg[I915_MAX_WA_REGS]; | |
1958 | u32 count; | |
1959 | u32 hw_whitelist_count[I915_NUM_ENGINES]; | |
1960 | }; | |
1961 | ||
1962 | struct i915_virtual_gpu { | |
1963 | bool active; | |
1964 | u32 caps; | |
1965 | }; | |
1966 | ||
1967 | /* used in computing the new watermarks state */ | |
1968 | struct intel_wm_config { | |
1969 | unsigned int num_pipes_active; | |
1970 | bool sprites_enabled; | |
1971 | bool sprites_scaled; | |
1972 | }; | |
1973 | ||
1974 | struct i915_oa_format { | |
1975 | u32 format; | |
1976 | int size; | |
1977 | }; | |
1978 | ||
1979 | struct i915_oa_reg { | |
1980 | i915_reg_t addr; | |
1981 | u32 value; | |
1982 | }; | |
1983 | ||
1984 | struct i915_oa_config { | |
1985 | char uuid[UUID_STRING_LEN + 1]; | |
1986 | int id; | |
1987 | ||
1988 | const struct i915_oa_reg *mux_regs; | |
1989 | u32 mux_regs_len; | |
1990 | const struct i915_oa_reg *b_counter_regs; | |
1991 | u32 b_counter_regs_len; | |
1992 | const struct i915_oa_reg *flex_regs; | |
1993 | u32 flex_regs_len; | |
1994 | ||
1995 | struct attribute_group sysfs_metric; | |
1996 | struct attribute *attrs[2]; | |
1997 | struct device_attribute sysfs_metric_id; | |
1998 | ||
1999 | atomic_t ref_count; | |
2000 | }; | |
2001 | ||
2002 | struct i915_perf_stream; | |
2003 | ||
2004 | /** | |
2005 | * struct i915_perf_stream_ops - the OPs to support a specific stream type | |
2006 | */ | |
2007 | struct i915_perf_stream_ops { | |
2008 | /** | |
2009 | * @enable: Enables the collection of HW samples, either in response to | |
2010 | * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened | |
2011 | * without `I915_PERF_FLAG_DISABLED`. | |
2012 | */ | |
2013 | void (*enable)(struct i915_perf_stream *stream); | |
2014 | ||
2015 | /** | |
2016 | * @disable: Disables the collection of HW samples, either in response | |
2017 | * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying | |
2018 | * the stream. | |
2019 | */ | |
2020 | void (*disable)(struct i915_perf_stream *stream); | |
2021 | ||
2022 | /** | |
2023 | * @poll_wait: Call poll_wait, passing a wait queue that will be woken | |
2024 | * once there is something ready to read() for the stream | |
2025 | */ | |
2026 | void (*poll_wait)(struct i915_perf_stream *stream, | |
2027 | struct file *file, | |
2028 | poll_table *wait); | |
2029 | ||
2030 | /** | |
2031 | * @wait_unlocked: For handling a blocking read, wait until there is | |
2032 | * something to ready to read() for the stream. E.g. wait on the same | |
2033 | * wait queue that would be passed to poll_wait(). | |
2034 | */ | |
2035 | int (*wait_unlocked)(struct i915_perf_stream *stream); | |
2036 | ||
2037 | /** | |
2038 | * @read: Copy buffered metrics as records to userspace | |
2039 | * **buf**: the userspace, destination buffer | |
2040 | * **count**: the number of bytes to copy, requested by userspace | |
2041 | * **offset**: zero at the start of the read, updated as the read | |
2042 | * proceeds, it represents how many bytes have been copied so far and | |
2043 | * the buffer offset for copying the next record. | |
2044 | * | |
2045 | * Copy as many buffered i915 perf samples and records for this stream | |
2046 | * to userspace as will fit in the given buffer. | |
2047 | * | |
2048 | * Only write complete records; returning -%ENOSPC if there isn't room | |
2049 | * for a complete record. | |
2050 | * | |
2051 | * Return any error condition that results in a short read such as | |
2052 | * -%ENOSPC or -%EFAULT, even though these may be squashed before | |
2053 | * returning to userspace. | |
2054 | */ | |
2055 | int (*read)(struct i915_perf_stream *stream, | |
2056 | char __user *buf, | |
2057 | size_t count, | |
2058 | size_t *offset); | |
2059 | ||
2060 | /** | |
2061 | * @destroy: Cleanup any stream specific resources. | |
2062 | * | |
2063 | * The stream will always be disabled before this is called. | |
2064 | */ | |
2065 | void (*destroy)(struct i915_perf_stream *stream); | |
2066 | }; | |
2067 | ||
2068 | /** | |
2069 | * struct i915_perf_stream - state for a single open stream FD | |
2070 | */ | |
2071 | struct i915_perf_stream { | |
2072 | /** | |
2073 | * @dev_priv: i915 drm device | |
2074 | */ | |
2075 | struct drm_i915_private *dev_priv; | |
2076 | ||
2077 | /** | |
2078 | * @link: Links the stream into ``&drm_i915_private->streams`` | |
2079 | */ | |
2080 | struct list_head link; | |
2081 | ||
2082 | /** | |
2083 | * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*` | |
2084 | * properties given when opening a stream, representing the contents | |
2085 | * of a single sample as read() by userspace. | |
2086 | */ | |
2087 | u32 sample_flags; | |
2088 | ||
2089 | /** | |
2090 | * @sample_size: Considering the configured contents of a sample | |
2091 | * combined with the required header size, this is the total size | |
2092 | * of a single sample record. | |
2093 | */ | |
2094 | int sample_size; | |
2095 | ||
2096 | /** | |
2097 | * @ctx: %NULL if measuring system-wide across all contexts or a | |
2098 | * specific context that is being monitored. | |
2099 | */ | |
2100 | struct i915_gem_context *ctx; | |
2101 | ||
2102 | /** | |
2103 | * @enabled: Whether the stream is currently enabled, considering | |
2104 | * whether the stream was opened in a disabled state and based | |
2105 | * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls. | |
2106 | */ | |
2107 | bool enabled; | |
2108 | ||
2109 | /** | |
2110 | * @ops: The callbacks providing the implementation of this specific | |
2111 | * type of configured stream. | |
2112 | */ | |
2113 | const struct i915_perf_stream_ops *ops; | |
2114 | ||
2115 | /** | |
2116 | * @oa_config: The OA configuration used by the stream. | |
2117 | */ | |
2118 | struct i915_oa_config *oa_config; | |
2119 | }; | |
2120 | ||
2121 | /** | |
2122 | * struct i915_oa_ops - Gen specific implementation of an OA unit stream | |
2123 | */ | |
2124 | struct i915_oa_ops { | |
2125 | /** | |
2126 | * @is_valid_b_counter_reg: Validates register's address for | |
2127 | * programming boolean counters for a particular platform. | |
2128 | */ | |
2129 | bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv, | |
2130 | u32 addr); | |
2131 | ||
2132 | /** | |
2133 | * @is_valid_mux_reg: Validates register's address for programming mux | |
2134 | * for a particular platform. | |
2135 | */ | |
2136 | bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr); | |
2137 | ||
2138 | /** | |
2139 | * @is_valid_flex_reg: Validates register's address for programming | |
2140 | * flex EU filtering for a particular platform. | |
2141 | */ | |
2142 | bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr); | |
2143 | ||
2144 | /** | |
2145 | * @init_oa_buffer: Resets the head and tail pointers of the | |
2146 | * circular buffer for periodic OA reports. | |
2147 | * | |
2148 | * Called when first opening a stream for OA metrics, but also may be | |
2149 | * called in response to an OA buffer overflow or other error | |
2150 | * condition. | |
2151 | * | |
2152 | * Note it may be necessary to clear the full OA buffer here as part of | |
2153 | * maintaining the invariable that new reports must be written to | |
2154 | * zeroed memory for us to be able to reliable detect if an expected | |
2155 | * report has not yet landed in memory. (At least on Haswell the OA | |
2156 | * buffer tail pointer is not synchronized with reports being visible | |
2157 | * to the CPU) | |
2158 | */ | |
2159 | void (*init_oa_buffer)(struct drm_i915_private *dev_priv); | |
2160 | ||
2161 | /** | |
2162 | * @enable_metric_set: Selects and applies any MUX configuration to set | |
2163 | * up the Boolean and Custom (B/C) counters that are part of the | |
2164 | * counter reports being sampled. May apply system constraints such as | |
2165 | * disabling EU clock gating as required. | |
2166 | */ | |
2167 | int (*enable_metric_set)(struct drm_i915_private *dev_priv, | |
2168 | const struct i915_oa_config *oa_config); | |
2169 | ||
2170 | /** | |
2171 | * @disable_metric_set: Remove system constraints associated with using | |
2172 | * the OA unit. | |
2173 | */ | |
2174 | void (*disable_metric_set)(struct drm_i915_private *dev_priv); | |
2175 | ||
2176 | /** | |
2177 | * @oa_enable: Enable periodic sampling | |
2178 | */ | |
2179 | void (*oa_enable)(struct drm_i915_private *dev_priv); | |
2180 | ||
2181 | /** | |
2182 | * @oa_disable: Disable periodic sampling | |
2183 | */ | |
2184 | void (*oa_disable)(struct drm_i915_private *dev_priv); | |
2185 | ||
2186 | /** | |
2187 | * @read: Copy data from the circular OA buffer into a given userspace | |
2188 | * buffer. | |
2189 | */ | |
2190 | int (*read)(struct i915_perf_stream *stream, | |
2191 | char __user *buf, | |
2192 | size_t count, | |
2193 | size_t *offset); | |
2194 | ||
2195 | /** | |
2196 | * @oa_hw_tail_read: read the OA tail pointer register | |
2197 | * | |
2198 | * In particular this enables us to share all the fiddly code for | |
2199 | * handling the OA unit tail pointer race that affects multiple | |
2200 | * generations. | |
2201 | */ | |
2202 | u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv); | |
2203 | }; | |
2204 | ||
2205 | struct intel_cdclk_state { | |
2206 | unsigned int cdclk, vco, ref; | |
2207 | }; | |
2208 | ||
2209 | struct drm_i915_private { | |
2210 | struct drm_device drm; | |
2211 | ||
2212 | struct kmem_cache *objects; | |
2213 | struct kmem_cache *vmas; | |
2214 | struct kmem_cache *luts; | |
2215 | struct kmem_cache *requests; | |
2216 | struct kmem_cache *dependencies; | |
2217 | struct kmem_cache *priorities; | |
2218 | ||
2219 | const struct intel_device_info info; | |
2220 | ||
2221 | void __iomem *regs; | |
2222 | ||
2223 | struct intel_uncore uncore; | |
2224 | ||
2225 | struct i915_virtual_gpu vgpu; | |
2226 | ||
2227 | struct intel_gvt *gvt; | |
2228 | ||
2229 | struct intel_huc huc; | |
2230 | struct intel_guc guc; | |
2231 | ||
2232 | struct intel_csr csr; | |
2233 | ||
2234 | struct intel_gmbus gmbus[GMBUS_NUM_PINS]; | |
2235 | ||
2236 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus | |
2237 | * controller on different i2c buses. */ | |
2238 | struct mutex gmbus_mutex; | |
2239 | ||
2240 | /** | |
2241 | * Base address of the gmbus and gpio block. | |
2242 | */ | |
2243 | uint32_t gpio_mmio_base; | |
2244 | ||
2245 | /* MMIO base address for MIPI regs */ | |
2246 | uint32_t mipi_mmio_base; | |
2247 | ||
2248 | uint32_t psr_mmio_base; | |
2249 | ||
2250 | uint32_t pps_mmio_base; | |
2251 | ||
2252 | wait_queue_head_t gmbus_wait_queue; | |
2253 | ||
2254 | struct pci_dev *bridge_dev; | |
2255 | struct intel_engine_cs *engine[I915_NUM_ENGINES]; | |
2256 | /* Context used internally to idle the GPU and setup initial state */ | |
2257 | struct i915_gem_context *kernel_context; | |
2258 | /* Context only to be used for injecting preemption commands */ | |
2259 | struct i915_gem_context *preempt_context; | |
2260 | struct i915_vma *semaphore; | |
2261 | ||
2262 | struct drm_dma_handle *status_page_dmah; | |
2263 | struct resource mch_res; | |
2264 | ||
2265 | /* protects the irq masks */ | |
2266 | spinlock_t irq_lock; | |
2267 | ||
2268 | bool display_irqs_enabled; | |
2269 | ||
2270 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ | |
2271 | struct pm_qos_request pm_qos; | |
2272 | ||
2273 | /* Sideband mailbox protection */ | |
2274 | struct mutex sb_lock; | |
2275 | ||
2276 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
2277 | union { | |
2278 | u32 irq_mask; | |
2279 | u32 de_irq_mask[I915_MAX_PIPES]; | |
2280 | }; | |
2281 | u32 gt_irq_mask; | |
2282 | u32 pm_imr; | |
2283 | u32 pm_ier; | |
2284 | u32 pm_rps_events; | |
2285 | u32 pm_guc_events; | |
2286 | u32 pipestat_irq_mask[I915_MAX_PIPES]; | |
2287 | ||
2288 | struct i915_hotplug hotplug; | |
2289 | struct intel_fbc fbc; | |
2290 | struct i915_drrs drrs; | |
2291 | struct intel_opregion opregion; | |
2292 | struct intel_vbt_data vbt; | |
2293 | ||
2294 | bool preserve_bios_swizzle; | |
2295 | ||
2296 | /* overlay */ | |
2297 | struct intel_overlay *overlay; | |
2298 | ||
2299 | /* backlight registers and fields in struct intel_panel */ | |
2300 | struct mutex backlight_lock; | |
2301 | ||
2302 | /* LVDS info */ | |
2303 | bool no_aux_handshake; | |
2304 | ||
2305 | /* protects panel power sequencer state */ | |
2306 | struct mutex pps_mutex; | |
2307 | ||
2308 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ | |
2309 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
2310 | ||
2311 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
2312 | unsigned int skl_preferred_vco_freq; | |
2313 | unsigned int max_cdclk_freq; | |
2314 | ||
2315 | unsigned int max_dotclk_freq; | |
2316 | unsigned int rawclk_freq; | |
2317 | unsigned int hpll_freq; | |
2318 | unsigned int czclk_freq; | |
2319 | ||
2320 | struct { | |
2321 | /* | |
2322 | * The current logical cdclk state. | |
2323 | * See intel_atomic_state.cdclk.logical | |
2324 | * | |
2325 | * For reading holding any crtc lock is sufficient, | |
2326 | * for writing must hold all of them. | |
2327 | */ | |
2328 | struct intel_cdclk_state logical; | |
2329 | /* | |
2330 | * The current actual cdclk state. | |
2331 | * See intel_atomic_state.cdclk.actual | |
2332 | */ | |
2333 | struct intel_cdclk_state actual; | |
2334 | /* The current hardware cdclk state */ | |
2335 | struct intel_cdclk_state hw; | |
2336 | } cdclk; | |
2337 | ||
2338 | /** | |
2339 | * wq - Driver workqueue for GEM. | |
2340 | * | |
2341 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
2342 | * locks, for otherwise the flushing done in the pageflip code will | |
2343 | * result in deadlocks. | |
2344 | */ | |
2345 | struct workqueue_struct *wq; | |
2346 | ||
2347 | /* Display functions */ | |
2348 | struct drm_i915_display_funcs display; | |
2349 | ||
2350 | /* PCH chipset type */ | |
2351 | enum intel_pch pch_type; | |
2352 | unsigned short pch_id; | |
2353 | ||
2354 | unsigned long quirks; | |
2355 | ||
2356 | enum modeset_restore modeset_restore; | |
2357 | struct mutex modeset_restore_lock; | |
2358 | struct drm_atomic_state *modeset_restore_state; | |
2359 | struct drm_modeset_acquire_ctx reset_ctx; | |
2360 | ||
2361 | struct list_head vm_list; /* Global list of all address spaces */ | |
2362 | struct i915_ggtt ggtt; /* VM representing the global address space */ | |
2363 | ||
2364 | struct i915_gem_mm mm; | |
2365 | DECLARE_HASHTABLE(mm_structs, 7); | |
2366 | struct mutex mm_lock; | |
2367 | ||
2368 | struct intel_ppat ppat; | |
2369 | ||
2370 | /* Kernel Modesetting */ | |
2371 | ||
2372 | struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; | |
2373 | struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; | |
2374 | ||
2375 | #ifdef CONFIG_DEBUG_FS | |
2376 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
2377 | #endif | |
2378 | ||
2379 | /* dpll and cdclk state is protected by connection_mutex */ | |
2380 | int num_shared_dpll; | |
2381 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
2382 | const struct intel_dpll_mgr *dpll_mgr; | |
2383 | ||
2384 | /* | |
2385 | * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll. | |
2386 | * Must be global rather than per dpll, because on some platforms | |
2387 | * plls share registers. | |
2388 | */ | |
2389 | struct mutex dpll_lock; | |
2390 | ||
2391 | unsigned int active_crtcs; | |
2392 | /* minimum acceptable cdclk for each pipe */ | |
2393 | int min_cdclk[I915_MAX_PIPES]; | |
2394 | ||
2395 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; | |
2396 | ||
2397 | struct i915_workarounds workarounds; | |
2398 | ||
2399 | struct i915_frontbuffer_tracking fb_tracking; | |
2400 | ||
2401 | struct intel_atomic_helper { | |
2402 | struct llist_head free_list; | |
2403 | struct work_struct free_work; | |
2404 | } atomic_helper; | |
2405 | ||
2406 | u16 orig_clock; | |
2407 | ||
2408 | bool mchbar_need_disable; | |
2409 | ||
2410 | struct intel_l3_parity l3_parity; | |
2411 | ||
2412 | /* Cannot be determined by PCIID. You must always read a register. */ | |
2413 | u32 edram_cap; | |
2414 | ||
2415 | /* gen6+ rps state */ | |
2416 | struct intel_gen6_power_mgmt rps; | |
2417 | ||
2418 | /* ilk-only ips/rps state. Everything in here is protected by the global | |
2419 | * mchdev_lock in intel_pm.c */ | |
2420 | struct intel_ilk_power_mgmt ips; | |
2421 | ||
2422 | struct i915_power_domains power_domains; | |
2423 | ||
2424 | struct i915_psr psr; | |
2425 | ||
2426 | struct i915_gpu_error gpu_error; | |
2427 | ||
2428 | struct drm_i915_gem_object *vlv_pctx; | |
2429 | ||
2430 | /* list of fbdev register on this device */ | |
2431 | struct intel_fbdev *fbdev; | |
2432 | struct work_struct fbdev_suspend_work; | |
2433 | ||
2434 | struct drm_property *broadcast_rgb_property; | |
2435 | struct drm_property *force_audio_property; | |
2436 | ||
2437 | /* hda/i915 audio component */ | |
2438 | struct i915_audio_component *audio_component; | |
2439 | bool audio_component_registered; | |
2440 | /** | |
2441 | * av_mutex - mutex for audio/video sync | |
2442 | * | |
2443 | */ | |
2444 | struct mutex av_mutex; | |
2445 | ||
2446 | struct { | |
2447 | struct list_head list; | |
2448 | struct llist_head free_list; | |
2449 | struct work_struct free_work; | |
2450 | ||
2451 | /* The hw wants to have a stable context identifier for the | |
2452 | * lifetime of the context (for OA, PASID, faults, etc). | |
2453 | * This is limited in execlists to 21 bits. | |
2454 | */ | |
2455 | struct ida hw_ida; | |
2456 | #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */ | |
2457 | } contexts; | |
2458 | ||
2459 | u32 fdi_rx_config; | |
2460 | ||
2461 | /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ | |
2462 | u32 chv_phy_control; | |
2463 | /* | |
2464 | * Shadows for CHV DPLL_MD regs to keep the state | |
2465 | * checker somewhat working in the presence hardware | |
2466 | * crappiness (can't read out DPLL_MD for pipes B & C). | |
2467 | */ | |
2468 | u32 chv_dpll_md[I915_MAX_PIPES]; | |
2469 | u32 bxt_phy_grc; | |
2470 | ||
2471 | u32 suspend_count; | |
2472 | bool suspended_to_idle; | |
2473 | struct i915_suspend_saved_registers regfile; | |
2474 | struct vlv_s0ix_state vlv_s0ix_state; | |
2475 | ||
2476 | enum { | |
2477 | I915_SAGV_UNKNOWN = 0, | |
2478 | I915_SAGV_DISABLED, | |
2479 | I915_SAGV_ENABLED, | |
2480 | I915_SAGV_NOT_CONTROLLED | |
2481 | } sagv_status; | |
2482 | ||
2483 | struct { | |
2484 | /* | |
2485 | * Raw watermark latency values: | |
2486 | * in 0.1us units for WM0, | |
2487 | * in 0.5us units for WM1+. | |
2488 | */ | |
2489 | /* primary */ | |
2490 | uint16_t pri_latency[5]; | |
2491 | /* sprite */ | |
2492 | uint16_t spr_latency[5]; | |
2493 | /* cursor */ | |
2494 | uint16_t cur_latency[5]; | |
2495 | /* | |
2496 | * Raw watermark memory latency values | |
2497 | * for SKL for all 8 levels | |
2498 | * in 1us units. | |
2499 | */ | |
2500 | uint16_t skl_latency[8]; | |
2501 | ||
2502 | /* current hardware state */ | |
2503 | union { | |
2504 | struct ilk_wm_values hw; | |
2505 | struct skl_wm_values skl_hw; | |
2506 | struct vlv_wm_values vlv; | |
2507 | struct g4x_wm_values g4x; | |
2508 | }; | |
2509 | ||
2510 | uint8_t max_level; | |
2511 | ||
2512 | /* | |
2513 | * Should be held around atomic WM register writing; also | |
2514 | * protects * intel_crtc->wm.active and | |
2515 | * cstate->wm.need_postvbl_update. | |
2516 | */ | |
2517 | struct mutex wm_mutex; | |
2518 | ||
2519 | /* | |
2520 | * Set during HW readout of watermarks/DDB. Some platforms | |
2521 | * need to know when we're still using BIOS-provided values | |
2522 | * (which we don't fully trust). | |
2523 | */ | |
2524 | bool distrust_bios_wm; | |
2525 | } wm; | |
2526 | ||
2527 | struct i915_runtime_pm pm; | |
2528 | ||
2529 | struct { | |
2530 | bool initialized; | |
2531 | ||
2532 | struct kobject *metrics_kobj; | |
2533 | struct ctl_table_header *sysctl_header; | |
2534 | ||
2535 | /* | |
2536 | * Lock associated with adding/modifying/removing OA configs | |
2537 | * in dev_priv->perf.metrics_idr. | |
2538 | */ | |
2539 | struct mutex metrics_lock; | |
2540 | ||
2541 | /* | |
2542 | * List of dynamic configurations, you need to hold | |
2543 | * dev_priv->perf.metrics_lock to access it. | |
2544 | */ | |
2545 | struct idr metrics_idr; | |
2546 | ||
2547 | /* | |
2548 | * Lock associated with anything below within this structure | |
2549 | * except exclusive_stream. | |
2550 | */ | |
2551 | struct mutex lock; | |
2552 | struct list_head streams; | |
2553 | ||
2554 | struct { | |
2555 | /* | |
2556 | * The stream currently using the OA unit. If accessed | |
2557 | * outside a syscall associated to its file | |
2558 | * descriptor, you need to hold | |
2559 | * dev_priv->drm.struct_mutex. | |
2560 | */ | |
2561 | struct i915_perf_stream *exclusive_stream; | |
2562 | ||
2563 | u32 specific_ctx_id; | |
2564 | ||
2565 | struct hrtimer poll_check_timer; | |
2566 | wait_queue_head_t poll_wq; | |
2567 | bool pollin; | |
2568 | ||
2569 | /** | |
2570 | * For rate limiting any notifications of spurious | |
2571 | * invalid OA reports | |
2572 | */ | |
2573 | struct ratelimit_state spurious_report_rs; | |
2574 | ||
2575 | bool periodic; | |
2576 | int period_exponent; | |
2577 | int timestamp_frequency; | |
2578 | ||
2579 | struct i915_oa_config test_config; | |
2580 | ||
2581 | struct { | |
2582 | struct i915_vma *vma; | |
2583 | u8 *vaddr; | |
2584 | u32 last_ctx_id; | |
2585 | int format; | |
2586 | int format_size; | |
2587 | ||
2588 | /** | |
2589 | * Locks reads and writes to all head/tail state | |
2590 | * | |
2591 | * Consider: the head and tail pointer state | |
2592 | * needs to be read consistently from a hrtimer | |
2593 | * callback (atomic context) and read() fop | |
2594 | * (user context) with tail pointer updates | |
2595 | * happening in atomic context and head updates | |
2596 | * in user context and the (unlikely) | |
2597 | * possibility of read() errors needing to | |
2598 | * reset all head/tail state. | |
2599 | * | |
2600 | * Note: Contention or performance aren't | |
2601 | * currently a significant concern here | |
2602 | * considering the relatively low frequency of | |
2603 | * hrtimer callbacks (5ms period) and that | |
2604 | * reads typically only happen in response to a | |
2605 | * hrtimer event and likely complete before the | |
2606 | * next callback. | |
2607 | * | |
2608 | * Note: This lock is not held *while* reading | |
2609 | * and copying data to userspace so the value | |
2610 | * of head observed in htrimer callbacks won't | |
2611 | * represent any partial consumption of data. | |
2612 | */ | |
2613 | spinlock_t ptr_lock; | |
2614 | ||
2615 | /** | |
2616 | * One 'aging' tail pointer and one 'aged' | |
2617 | * tail pointer ready to used for reading. | |
2618 | * | |
2619 | * Initial values of 0xffffffff are invalid | |
2620 | * and imply that an update is required | |
2621 | * (and should be ignored by an attempted | |
2622 | * read) | |
2623 | */ | |
2624 | struct { | |
2625 | u32 offset; | |
2626 | } tails[2]; | |
2627 | ||
2628 | /** | |
2629 | * Index for the aged tail ready to read() | |
2630 | * data up to. | |
2631 | */ | |
2632 | unsigned int aged_tail_idx; | |
2633 | ||
2634 | /** | |
2635 | * A monotonic timestamp for when the current | |
2636 | * aging tail pointer was read; used to | |
2637 | * determine when it is old enough to trust. | |
2638 | */ | |
2639 | u64 aging_timestamp; | |
2640 | ||
2641 | /** | |
2642 | * Although we can always read back the head | |
2643 | * pointer register, we prefer to avoid | |
2644 | * trusting the HW state, just to avoid any | |
2645 | * risk that some hardware condition could | |
2646 | * somehow bump the head pointer unpredictably | |
2647 | * and cause us to forward the wrong OA buffer | |
2648 | * data to userspace. | |
2649 | */ | |
2650 | u32 head; | |
2651 | } oa_buffer; | |
2652 | ||
2653 | u32 gen7_latched_oastatus1; | |
2654 | u32 ctx_oactxctrl_offset; | |
2655 | u32 ctx_flexeu0_offset; | |
2656 | ||
2657 | /** | |
2658 | * The RPT_ID/reason field for Gen8+ includes a bit | |
2659 | * to determine if the CTX ID in the report is valid | |
2660 | * but the specific bit differs between Gen 8 and 9 | |
2661 | */ | |
2662 | u32 gen8_valid_ctx_bit; | |
2663 | ||
2664 | struct i915_oa_ops ops; | |
2665 | const struct i915_oa_format *oa_formats; | |
2666 | } oa; | |
2667 | } perf; | |
2668 | ||
2669 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ | |
2670 | struct { | |
2671 | void (*resume)(struct drm_i915_private *); | |
2672 | void (*cleanup_engine)(struct intel_engine_cs *engine); | |
2673 | ||
2674 | struct list_head timelines; | |
2675 | struct i915_gem_timeline global_timeline; | |
2676 | u32 active_requests; | |
2677 | ||
2678 | /** | |
2679 | * Is the GPU currently considered idle, or busy executing | |
2680 | * userspace requests? Whilst idle, we allow runtime power | |
2681 | * management to power down the hardware and display clocks. | |
2682 | * In order to reduce the effect on performance, there | |
2683 | * is a slight delay before we do so. | |
2684 | */ | |
2685 | bool awake; | |
2686 | ||
2687 | /** | |
2688 | * We leave the user IRQ off as much as possible, | |
2689 | * but this means that requests will finish and never | |
2690 | * be retired once the system goes idle. Set a timer to | |
2691 | * fire periodically while the ring is running. When it | |
2692 | * fires, go retire requests. | |
2693 | */ | |
2694 | struct delayed_work retire_work; | |
2695 | ||
2696 | /** | |
2697 | * When we detect an idle GPU, we want to turn on | |
2698 | * powersaving features. So once we see that there | |
2699 | * are no more requests outstanding and no more | |
2700 | * arrive within a small period of time, we fire | |
2701 | * off the idle_work. | |
2702 | */ | |
2703 | struct delayed_work idle_work; | |
2704 | ||
2705 | ktime_t last_init_time; | |
2706 | } gt; | |
2707 | ||
2708 | /* perform PHY state sanity checks? */ | |
2709 | bool chv_phy_assert[2]; | |
2710 | ||
2711 | bool ipc_enabled; | |
2712 | ||
2713 | /* Used to save the pipe-to-encoder mapping for audio */ | |
2714 | struct intel_encoder *av_enc_map[I915_MAX_PIPES]; | |
2715 | ||
2716 | /* necessary resource sharing with HDMI LPE audio driver. */ | |
2717 | struct { | |
2718 | struct platform_device *platdev; | |
2719 | int irq; | |
2720 | } lpe_audio; | |
2721 | ||
2722 | /* | |
2723 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch | |
2724 | * will be rejected. Instead look for a better place. | |
2725 | */ | |
2726 | }; | |
2727 | ||
2728 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) | |
2729 | { | |
2730 | return container_of(dev, struct drm_i915_private, drm); | |
2731 | } | |
2732 | ||
2733 | static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) | |
2734 | { | |
2735 | return to_i915(dev_get_drvdata(kdev)); | |
2736 | } | |
2737 | ||
2738 | static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc) | |
2739 | { | |
2740 | return container_of(guc, struct drm_i915_private, guc); | |
2741 | } | |
2742 | ||
2743 | static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc) | |
2744 | { | |
2745 | return container_of(huc, struct drm_i915_private, huc); | |
2746 | } | |
2747 | ||
2748 | /* Simple iterator over all initialised engines */ | |
2749 | #define for_each_engine(engine__, dev_priv__, id__) \ | |
2750 | for ((id__) = 0; \ | |
2751 | (id__) < I915_NUM_ENGINES; \ | |
2752 | (id__)++) \ | |
2753 | for_each_if ((engine__) = (dev_priv__)->engine[(id__)]) | |
2754 | ||
2755 | /* Iterator over subset of engines selected by mask */ | |
2756 | #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \ | |
2757 | for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \ | |
2758 | tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; ) | |
2759 | ||
2760 | enum hdmi_force_audio { | |
2761 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
2762 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
2763 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
2764 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
2765 | }; | |
2766 | ||
2767 | #define I915_GTT_OFFSET_NONE ((u32)-1) | |
2768 | ||
2769 | /* | |
2770 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is | |
2771 | * considered to be the frontbuffer for the given plane interface-wise. This | |
2772 | * doesn't mean that the hw necessarily already scans it out, but that any | |
2773 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. | |
2774 | * | |
2775 | * We have one bit per pipe and per scanout plane type. | |
2776 | */ | |
2777 | #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5 | |
2778 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 | |
2779 | #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ | |
2780 | (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
2781 | #define INTEL_FRONTBUFFER_CURSOR(pipe) \ | |
2782 | (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
2783 | #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \ | |
2784 | (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
2785 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ | |
2786 | (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
2787 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ | |
2788 | (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
2789 | ||
2790 | /* | |
2791 | * Optimised SGL iterator for GEM objects | |
2792 | */ | |
2793 | static __always_inline struct sgt_iter { | |
2794 | struct scatterlist *sgp; | |
2795 | union { | |
2796 | unsigned long pfn; | |
2797 | dma_addr_t dma; | |
2798 | }; | |
2799 | unsigned int curr; | |
2800 | unsigned int max; | |
2801 | } __sgt_iter(struct scatterlist *sgl, bool dma) { | |
2802 | struct sgt_iter s = { .sgp = sgl }; | |
2803 | ||
2804 | if (s.sgp) { | |
2805 | s.max = s.curr = s.sgp->offset; | |
2806 | s.max += s.sgp->length; | |
2807 | if (dma) | |
2808 | s.dma = sg_dma_address(s.sgp); | |
2809 | else | |
2810 | s.pfn = page_to_pfn(sg_page(s.sgp)); | |
2811 | } | |
2812 | ||
2813 | return s; | |
2814 | } | |
2815 | ||
2816 | static inline struct scatterlist *____sg_next(struct scatterlist *sg) | |
2817 | { | |
2818 | ++sg; | |
2819 | if (unlikely(sg_is_chain(sg))) | |
2820 | sg = sg_chain_ptr(sg); | |
2821 | return sg; | |
2822 | } | |
2823 | ||
2824 | /** | |
2825 | * __sg_next - return the next scatterlist entry in a list | |
2826 | * @sg: The current sg entry | |
2827 | * | |
2828 | * Description: | |
2829 | * If the entry is the last, return NULL; otherwise, step to the next | |
2830 | * element in the array (@sg@+1). If that's a chain pointer, follow it; | |
2831 | * otherwise just return the pointer to the current element. | |
2832 | **/ | |
2833 | static inline struct scatterlist *__sg_next(struct scatterlist *sg) | |
2834 | { | |
2835 | #ifdef CONFIG_DEBUG_SG | |
2836 | BUG_ON(sg->sg_magic != SG_MAGIC); | |
2837 | #endif | |
2838 | return sg_is_last(sg) ? NULL : ____sg_next(sg); | |
2839 | } | |
2840 | ||
2841 | /** | |
2842 | * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table | |
2843 | * @__dmap: DMA address (output) | |
2844 | * @__iter: 'struct sgt_iter' (iterator state, internal) | |
2845 | * @__sgt: sg_table to iterate over (input) | |
2846 | */ | |
2847 | #define for_each_sgt_dma(__dmap, __iter, __sgt) \ | |
2848 | for ((__iter) = __sgt_iter((__sgt)->sgl, true); \ | |
2849 | ((__dmap) = (__iter).dma + (__iter).curr); \ | |
2850 | (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \ | |
2851 | (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0) | |
2852 | ||
2853 | /** | |
2854 | * for_each_sgt_page - iterate over the pages of the given sg_table | |
2855 | * @__pp: page pointer (output) | |
2856 | * @__iter: 'struct sgt_iter' (iterator state, internal) | |
2857 | * @__sgt: sg_table to iterate over (input) | |
2858 | */ | |
2859 | #define for_each_sgt_page(__pp, __iter, __sgt) \ | |
2860 | for ((__iter) = __sgt_iter((__sgt)->sgl, false); \ | |
2861 | ((__pp) = (__iter).pfn == 0 ? NULL : \ | |
2862 | pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \ | |
2863 | (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \ | |
2864 | (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0) | |
2865 | ||
2866 | static inline unsigned int i915_sg_segment_size(void) | |
2867 | { | |
2868 | unsigned int size = swiotlb_max_segment(); | |
2869 | ||
2870 | if (size == 0) | |
2871 | return SCATTERLIST_MAX_SEGMENT; | |
2872 | ||
2873 | size = rounddown(size, PAGE_SIZE); | |
2874 | /* swiotlb_max_segment_size can return 1 byte when it means one page. */ | |
2875 | if (size < PAGE_SIZE) | |
2876 | size = PAGE_SIZE; | |
2877 | ||
2878 | return size; | |
2879 | } | |
2880 | ||
2881 | static inline const struct intel_device_info * | |
2882 | intel_info(const struct drm_i915_private *dev_priv) | |
2883 | { | |
2884 | return &dev_priv->info; | |
2885 | } | |
2886 | ||
2887 | #define INTEL_INFO(dev_priv) intel_info((dev_priv)) | |
2888 | ||
2889 | #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen) | |
2890 | #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id) | |
2891 | ||
2892 | #define REVID_FOREVER 0xff | |
2893 | #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) | |
2894 | ||
2895 | #define GEN_FOREVER (0) | |
2896 | ||
2897 | #define INTEL_GEN_MASK(s, e) ( \ | |
2898 | BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \ | |
2899 | BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \ | |
2900 | GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \ | |
2901 | (s) != GEN_FOREVER ? (s) - 1 : 0) \ | |
2902 | ) | |
2903 | ||
2904 | /* | |
2905 | * Returns true if Gen is in inclusive range [Start, End]. | |
2906 | * | |
2907 | * Use GEN_FOREVER for unbound start and or end. | |
2908 | */ | |
2909 | #define IS_GEN(dev_priv, s, e) \ | |
2910 | (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e)))) | |
2911 | ||
2912 | /* | |
2913 | * Return true if revision is in range [since,until] inclusive. | |
2914 | * | |
2915 | * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. | |
2916 | */ | |
2917 | #define IS_REVID(p, since, until) \ | |
2918 | (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) | |
2919 | ||
2920 | #define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p)) | |
2921 | ||
2922 | #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) | |
2923 | #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) | |
2924 | #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) | |
2925 | #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) | |
2926 | #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) | |
2927 | #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM) | |
2928 | #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) | |
2929 | #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM) | |
2930 | #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) | |
2931 | #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM) | |
2932 | #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) | |
2933 | #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) | |
2934 | #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) | |
2935 | #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001) | |
2936 | #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011) | |
2937 | #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) | |
2938 | #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) | |
2939 | #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046) | |
2940 | #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) | |
2941 | #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ | |
2942 | (dev_priv)->info.gt == 1) | |
2943 | #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) | |
2944 | #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) | |
2945 | #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) | |
2946 | #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) | |
2947 | #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) | |
2948 | #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) | |
2949 | #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) | |
2950 | #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) | |
2951 | #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) | |
2952 | #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) | |
2953 | #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile) | |
2954 | #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ | |
2955 | (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) | |
2956 | #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \ | |
2957 | ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \ | |
2958 | (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \ | |
2959 | (INTEL_DEVID(dev_priv) & 0xf) == 0xe)) | |
2960 | /* ULX machines are also considered ULT. */ | |
2961 | #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \ | |
2962 | (INTEL_DEVID(dev_priv) & 0xf) == 0xe) | |
2963 | #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ | |
2964 | (dev_priv)->info.gt == 3) | |
2965 | #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \ | |
2966 | (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00) | |
2967 | #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ | |
2968 | (dev_priv)->info.gt == 3) | |
2969 | /* ULX machines are also considered ULT. */ | |
2970 | #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \ | |
2971 | INTEL_DEVID(dev_priv) == 0x0A1E) | |
2972 | #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \ | |
2973 | INTEL_DEVID(dev_priv) == 0x1913 || \ | |
2974 | INTEL_DEVID(dev_priv) == 0x1916 || \ | |
2975 | INTEL_DEVID(dev_priv) == 0x1921 || \ | |
2976 | INTEL_DEVID(dev_priv) == 0x1926) | |
2977 | #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \ | |
2978 | INTEL_DEVID(dev_priv) == 0x1915 || \ | |
2979 | INTEL_DEVID(dev_priv) == 0x191E) | |
2980 | #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \ | |
2981 | INTEL_DEVID(dev_priv) == 0x5913 || \ | |
2982 | INTEL_DEVID(dev_priv) == 0x5916 || \ | |
2983 | INTEL_DEVID(dev_priv) == 0x5921 || \ | |
2984 | INTEL_DEVID(dev_priv) == 0x5926) | |
2985 | #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \ | |
2986 | INTEL_DEVID(dev_priv) == 0x5915 || \ | |
2987 | INTEL_DEVID(dev_priv) == 0x591E) | |
2988 | #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ | |
2989 | (dev_priv)->info.gt == 2) | |
2990 | #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ | |
2991 | (dev_priv)->info.gt == 3) | |
2992 | #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ | |
2993 | (dev_priv)->info.gt == 4) | |
2994 | #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ | |
2995 | (dev_priv)->info.gt == 2) | |
2996 | #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ | |
2997 | (dev_priv)->info.gt == 3) | |
2998 | #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \ | |
2999 | (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0) | |
3000 | #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ | |
3001 | (dev_priv)->info.gt == 2) | |
3002 | ||
3003 | #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support) | |
3004 | ||
3005 | #define SKL_REVID_A0 0x0 | |
3006 | #define SKL_REVID_B0 0x1 | |
3007 | #define SKL_REVID_C0 0x2 | |
3008 | #define SKL_REVID_D0 0x3 | |
3009 | #define SKL_REVID_E0 0x4 | |
3010 | #define SKL_REVID_F0 0x5 | |
3011 | #define SKL_REVID_G0 0x6 | |
3012 | #define SKL_REVID_H0 0x7 | |
3013 | ||
3014 | #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) | |
3015 | ||
3016 | #define BXT_REVID_A0 0x0 | |
3017 | #define BXT_REVID_A1 0x1 | |
3018 | #define BXT_REVID_B0 0x3 | |
3019 | #define BXT_REVID_B_LAST 0x8 | |
3020 | #define BXT_REVID_C0 0x9 | |
3021 | ||
3022 | #define IS_BXT_REVID(dev_priv, since, until) \ | |
3023 | (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until)) | |
3024 | ||
3025 | #define KBL_REVID_A0 0x0 | |
3026 | #define KBL_REVID_B0 0x1 | |
3027 | #define KBL_REVID_C0 0x2 | |
3028 | #define KBL_REVID_D0 0x3 | |
3029 | #define KBL_REVID_E0 0x4 | |
3030 | ||
3031 | #define IS_KBL_REVID(dev_priv, since, until) \ | |
3032 | (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until)) | |
3033 | ||
3034 | #define GLK_REVID_A0 0x0 | |
3035 | #define GLK_REVID_A1 0x1 | |
3036 | ||
3037 | #define IS_GLK_REVID(dev_priv, since, until) \ | |
3038 | (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until)) | |
3039 | ||
3040 | #define CNL_REVID_A0 0x0 | |
3041 | #define CNL_REVID_B0 0x1 | |
3042 | ||
3043 | #define IS_CNL_REVID(p, since, until) \ | |
3044 | (IS_CANNONLAKE(p) && IS_REVID(p, since, until)) | |
3045 | ||
3046 | /* | |
3047 | * The genX designation typically refers to the render engine, so render | |
3048 | * capability related checks should use IS_GEN, while display and other checks | |
3049 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
3050 | * chips, etc.). | |
3051 | */ | |
3052 | #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1))) | |
3053 | #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2))) | |
3054 | #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3))) | |
3055 | #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4))) | |
3056 | #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5))) | |
3057 | #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6))) | |
3058 | #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7))) | |
3059 | #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8))) | |
3060 | #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9))) | |
3061 | ||
3062 | #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) | |
3063 | #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv)) | |
3064 | #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) | |
3065 | ||
3066 | #define ENGINE_MASK(id) BIT(id) | |
3067 | #define RENDER_RING ENGINE_MASK(RCS) | |
3068 | #define BSD_RING ENGINE_MASK(VCS) | |
3069 | #define BLT_RING ENGINE_MASK(BCS) | |
3070 | #define VEBOX_RING ENGINE_MASK(VECS) | |
3071 | #define BSD2_RING ENGINE_MASK(VCS2) | |
3072 | #define ALL_ENGINES (~0) | |
3073 | ||
3074 | #define HAS_ENGINE(dev_priv, id) \ | |
3075 | (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id))) | |
3076 | ||
3077 | #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS) | |
3078 | #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2) | |
3079 | #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS) | |
3080 | #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS) | |
3081 | ||
3082 | #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc) | |
3083 | #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop) | |
3084 | #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED)) | |
3085 | #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \ | |
3086 | IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv)) | |
3087 | ||
3088 | #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical) | |
3089 | ||
3090 | #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ | |
3091 | ((dev_priv)->info.has_logical_ring_contexts) | |
3092 | #define USES_PPGTT(dev_priv) (i915_modparams.enable_ppgtt) | |
3093 | #define USES_FULL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2) | |
3094 | #define USES_FULL_48BIT_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3) | |
3095 | ||
3096 | #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay) | |
3097 | #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ | |
3098 | ((dev_priv)->info.overlay_needs_physical) | |
3099 | ||
3100 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ | |
3101 | #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) | |
3102 | ||
3103 | /* WaRsDisableCoarsePowerGating:skl,bxt */ | |
3104 | #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ | |
3105 | (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv)) | |
3106 | ||
3107 | /* | |
3108 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts | |
3109 | * even when in MSI mode. This results in spurious interrupt warnings if the | |
3110 | * legacy irq no. is shared with another device. The kernel then disables that | |
3111 | * interrupt source and so prevents the other device from working properly. | |
3112 | * | |
3113 | * Since we don't enable MSI anymore on gen4, we can always use GMBUS/AUX | |
3114 | * interrupts. | |
3115 | */ | |
3116 | #define HAS_AUX_IRQ(dev_priv) true | |
3117 | #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4) | |
3118 | ||
3119 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte | |
3120 | * rows, which changed the alignment requirements and fence programming. | |
3121 | */ | |
3122 | #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \ | |
3123 | !(IS_I915G(dev_priv) || \ | |
3124 | IS_I915GM(dev_priv))) | |
3125 | #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv) | |
3126 | #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug) | |
3127 | ||
3128 | #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) | |
3129 | #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr) | |
3130 | #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc) | |
3131 | #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7) | |
3132 | ||
3133 | #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) | |
3134 | ||
3135 | #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst) | |
3136 | ||
3137 | #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi) | |
3138 | #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg) | |
3139 | #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr) | |
3140 | #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6) | |
3141 | #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p) | |
3142 | ||
3143 | #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr) | |
3144 | ||
3145 | #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm) | |
3146 | #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc) | |
3147 | ||
3148 | #define HAS_IPC(dev_priv) ((dev_priv)->info.has_ipc) | |
3149 | ||
3150 | /* | |
3151 | * For now, anything with a GuC requires uCode loading, and then supports | |
3152 | * command submission once loaded. But these are logically independent | |
3153 | * properties, so we have separate macros to test them. | |
3154 | */ | |
3155 | #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc) | |
3156 | #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct) | |
3157 | #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) | |
3158 | #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv)) | |
3159 | #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) | |
3160 | ||
3161 | #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer) | |
3162 | ||
3163 | #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu) | |
3164 | ||
3165 | #define INTEL_PCH_DEVICE_ID_MASK 0xff80 | |
3166 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
3167 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
3168 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
3169 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
3170 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
3171 | #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80 | |
3172 | #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80 | |
3173 | #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 | |
3174 | #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 | |
3175 | #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280 | |
3176 | #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300 | |
3177 | #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80 | |
3178 | #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 | |
3179 | #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 | |
3180 | #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ | |
3181 | ||
3182 | #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) | |
3183 | #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP) | |
3184 | #define HAS_PCH_CNP_LP(dev_priv) \ | |
3185 | ((dev_priv)->pch_id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) | |
3186 | #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP) | |
3187 | #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT) | |
3188 | #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT) | |
3189 | #define HAS_PCH_LPT_LP(dev_priv) \ | |
3190 | ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \ | |
3191 | (dev_priv)->pch_id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) | |
3192 | #define HAS_PCH_LPT_H(dev_priv) \ | |
3193 | ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE || \ | |
3194 | (dev_priv)->pch_id == INTEL_PCH_WPT_DEVICE_ID_TYPE) | |
3195 | #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT) | |
3196 | #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX) | |
3197 | #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP) | |
3198 | #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE) | |
3199 | ||
3200 | #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display) | |
3201 | ||
3202 | #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) | |
3203 | ||
3204 | /* DPF == dynamic parity feature */ | |
3205 | #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf) | |
3206 | #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ | |
3207 | 2 : HAS_L3_DPF(dev_priv)) | |
3208 | ||
3209 | #define GT_FREQUENCY_MULTIPLIER 50 | |
3210 | #define GEN9_FREQ_SCALER 3 | |
3211 | ||
3212 | #include "i915_trace.h" | |
3213 | ||
3214 | static inline bool intel_vtd_active(void) | |
3215 | { | |
3216 | #ifdef CONFIG_INTEL_IOMMU | |
3217 | if (intel_iommu_gfx_mapped) | |
3218 | return true; | |
3219 | #endif | |
3220 | return false; | |
3221 | } | |
3222 | ||
3223 | static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) | |
3224 | { | |
3225 | return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active(); | |
3226 | } | |
3227 | ||
3228 | static inline bool | |
3229 | intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv) | |
3230 | { | |
3231 | return IS_BROXTON(dev_priv) && intel_vtd_active(); | |
3232 | } | |
3233 | ||
3234 | int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, | |
3235 | int enable_ppgtt); | |
3236 | ||
3237 | bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value); | |
3238 | ||
3239 | /* i915_drv.c */ | |
3240 | void __printf(3, 4) | |
3241 | __i915_printk(struct drm_i915_private *dev_priv, const char *level, | |
3242 | const char *fmt, ...); | |
3243 | ||
3244 | #define i915_report_error(dev_priv, fmt, ...) \ | |
3245 | __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__) | |
3246 | ||
3247 | #ifdef CONFIG_COMPAT | |
3248 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, | |
3249 | unsigned long arg); | |
3250 | #else | |
3251 | #define i915_compat_ioctl NULL | |
3252 | #endif | |
3253 | extern const struct dev_pm_ops i915_pm_ops; | |
3254 | ||
3255 | extern int i915_driver_load(struct pci_dev *pdev, | |
3256 | const struct pci_device_id *ent); | |
3257 | extern void i915_driver_unload(struct drm_device *dev); | |
3258 | extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask); | |
3259 | extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv); | |
3260 | ||
3261 | #define I915_RESET_QUIET BIT(0) | |
3262 | extern void i915_reset(struct drm_i915_private *i915, unsigned int flags); | |
3263 | extern int i915_reset_engine(struct intel_engine_cs *engine, | |
3264 | unsigned int flags); | |
3265 | ||
3266 | extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv); | |
3267 | extern int intel_guc_reset(struct drm_i915_private *dev_priv); | |
3268 | extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine); | |
3269 | extern void intel_hangcheck_init(struct drm_i915_private *dev_priv); | |
3270 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); | |
3271 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
3272 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
3273 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
3274 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); | |
3275 | ||
3276 | int intel_engines_init_mmio(struct drm_i915_private *dev_priv); | |
3277 | int intel_engines_init(struct drm_i915_private *dev_priv); | |
3278 | ||
3279 | /* intel_hotplug.c */ | |
3280 | void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, | |
3281 | u32 pin_mask, u32 long_mask); | |
3282 | void intel_hpd_init(struct drm_i915_private *dev_priv); | |
3283 | void intel_hpd_init_work(struct drm_i915_private *dev_priv); | |
3284 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); | |
3285 | enum port intel_hpd_pin_to_port(enum hpd_pin pin); | |
3286 | enum hpd_pin intel_hpd_pin(enum port port); | |
3287 | bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin); | |
3288 | void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin); | |
3289 | ||
3290 | /* i915_irq.c */ | |
3291 | static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv) | |
3292 | { | |
3293 | unsigned long delay; | |
3294 | ||
3295 | if (unlikely(!i915_modparams.enable_hangcheck)) | |
3296 | return; | |
3297 | ||
3298 | /* Don't continually defer the hangcheck so that it is always run at | |
3299 | * least once after work has been scheduled on any ring. Otherwise, | |
3300 | * we will ignore a hung ring if a second ring is kept busy. | |
3301 | */ | |
3302 | ||
3303 | delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES); | |
3304 | queue_delayed_work(system_long_wq, | |
3305 | &dev_priv->gpu_error.hangcheck_work, delay); | |
3306 | } | |
3307 | ||
3308 | __printf(3, 4) | |
3309 | void i915_handle_error(struct drm_i915_private *dev_priv, | |
3310 | u32 engine_mask, | |
3311 | const char *fmt, ...); | |
3312 | ||
3313 | extern void intel_irq_init(struct drm_i915_private *dev_priv); | |
3314 | extern void intel_irq_fini(struct drm_i915_private *dev_priv); | |
3315 | int intel_irq_install(struct drm_i915_private *dev_priv); | |
3316 | void intel_irq_uninstall(struct drm_i915_private *dev_priv); | |
3317 | ||
3318 | static inline bool intel_gvt_active(struct drm_i915_private *dev_priv) | |
3319 | { | |
3320 | return dev_priv->gvt; | |
3321 | } | |
3322 | ||
3323 | static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv) | |
3324 | { | |
3325 | return dev_priv->vgpu.active; | |
3326 | } | |
3327 | ||
3328 | u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv, | |
3329 | enum pipe pipe); | |
3330 | void | |
3331 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
3332 | u32 status_mask); | |
3333 | ||
3334 | void | |
3335 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
3336 | u32 status_mask); | |
3337 | ||
3338 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); | |
3339 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); | |
3340 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, | |
3341 | uint32_t mask, | |
3342 | uint32_t bits); | |
3343 | void ilk_update_display_irq(struct drm_i915_private *dev_priv, | |
3344 | uint32_t interrupt_mask, | |
3345 | uint32_t enabled_irq_mask); | |
3346 | static inline void | |
3347 | ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
3348 | { | |
3349 | ilk_update_display_irq(dev_priv, bits, bits); | |
3350 | } | |
3351 | static inline void | |
3352 | ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
3353 | { | |
3354 | ilk_update_display_irq(dev_priv, bits, 0); | |
3355 | } | |
3356 | void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, | |
3357 | enum pipe pipe, | |
3358 | uint32_t interrupt_mask, | |
3359 | uint32_t enabled_irq_mask); | |
3360 | static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv, | |
3361 | enum pipe pipe, uint32_t bits) | |
3362 | { | |
3363 | bdw_update_pipe_irq(dev_priv, pipe, bits, bits); | |
3364 | } | |
3365 | static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv, | |
3366 | enum pipe pipe, uint32_t bits) | |
3367 | { | |
3368 | bdw_update_pipe_irq(dev_priv, pipe, bits, 0); | |
3369 | } | |
3370 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, | |
3371 | uint32_t interrupt_mask, | |
3372 | uint32_t enabled_irq_mask); | |
3373 | static inline void | |
3374 | ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
3375 | { | |
3376 | ibx_display_interrupt_update(dev_priv, bits, bits); | |
3377 | } | |
3378 | static inline void | |
3379 | ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
3380 | { | |
3381 | ibx_display_interrupt_update(dev_priv, bits, 0); | |
3382 | } | |
3383 | ||
3384 | /* i915_gem.c */ | |
3385 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
3386 | struct drm_file *file_priv); | |
3387 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
3388 | struct drm_file *file_priv); | |
3389 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
3390 | struct drm_file *file_priv); | |
3391 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
3392 | struct drm_file *file_priv); | |
3393 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
3394 | struct drm_file *file_priv); | |
3395 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
3396 | struct drm_file *file_priv); | |
3397 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
3398 | struct drm_file *file_priv); | |
3399 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
3400 | struct drm_file *file_priv); | |
3401 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
3402 | struct drm_file *file_priv); | |
3403 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
3404 | struct drm_file *file_priv); | |
3405 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, | |
3406 | struct drm_file *file); | |
3407 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
3408 | struct drm_file *file); | |
3409 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3410 | struct drm_file *file_priv); | |
3411 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3412 | struct drm_file *file_priv); | |
3413 | int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data, | |
3414 | struct drm_file *file_priv); | |
3415 | int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data, | |
3416 | struct drm_file *file_priv); | |
3417 | int i915_gem_init_userptr(struct drm_i915_private *dev_priv); | |
3418 | void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv); | |
3419 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
3420 | struct drm_file *file); | |
3421 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
3422 | struct drm_file *file_priv); | |
3423 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, | |
3424 | struct drm_file *file_priv); | |
3425 | void i915_gem_sanitize(struct drm_i915_private *i915); | |
3426 | int i915_gem_load_init(struct drm_i915_private *dev_priv); | |
3427 | void i915_gem_load_cleanup(struct drm_i915_private *dev_priv); | |
3428 | void i915_gem_load_init_fences(struct drm_i915_private *dev_priv); | |
3429 | int i915_gem_freeze(struct drm_i915_private *dev_priv); | |
3430 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv); | |
3431 | ||
3432 | void *i915_gem_object_alloc(struct drm_i915_private *dev_priv); | |
3433 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
3434 | void i915_gem_object_init(struct drm_i915_gem_object *obj, | |
3435 | const struct drm_i915_gem_object_ops *ops); | |
3436 | struct drm_i915_gem_object * | |
3437 | i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size); | |
3438 | struct drm_i915_gem_object * | |
3439 | i915_gem_object_create_from_data(struct drm_i915_private *dev_priv, | |
3440 | const void *data, size_t size); | |
3441 | void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file); | |
3442 | void i915_gem_free_object(struct drm_gem_object *obj); | |
3443 | ||
3444 | static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915) | |
3445 | { | |
3446 | /* A single pass should suffice to release all the freed objects (along | |
3447 | * most call paths) , but be a little more paranoid in that freeing | |
3448 | * the objects does take a little amount of time, during which the rcu | |
3449 | * callbacks could have added new objects into the freed list, and | |
3450 | * armed the work again. | |
3451 | */ | |
3452 | do { | |
3453 | rcu_barrier(); | |
3454 | } while (flush_work(&i915->mm.free_work)); | |
3455 | } | |
3456 | ||
3457 | static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915) | |
3458 | { | |
3459 | /* | |
3460 | * Similar to objects above (see i915_gem_drain_freed-objects), in | |
3461 | * general we have workers that are armed by RCU and then rearm | |
3462 | * themselves in their callbacks. To be paranoid, we need to | |
3463 | * drain the workqueue a second time after waiting for the RCU | |
3464 | * grace period so that we catch work queued via RCU from the first | |
3465 | * pass. As neither drain_workqueue() nor flush_workqueue() report | |
3466 | * a result, we make an assumption that we only don't require more | |
3467 | * than 2 passes to catch all recursive RCU delayed work. | |
3468 | * | |
3469 | */ | |
3470 | int pass = 2; | |
3471 | do { | |
3472 | rcu_barrier(); | |
3473 | drain_workqueue(i915->wq); | |
3474 | } while (--pass); | |
3475 | } | |
3476 | ||
3477 | struct i915_vma * __must_check | |
3478 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, | |
3479 | const struct i915_ggtt_view *view, | |
3480 | u64 size, | |
3481 | u64 alignment, | |
3482 | u64 flags); | |
3483 | ||
3484 | int i915_gem_object_unbind(struct drm_i915_gem_object *obj); | |
3485 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); | |
3486 | ||
3487 | void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv); | |
3488 | ||
3489 | static inline int __sg_page_count(const struct scatterlist *sg) | |
3490 | { | |
3491 | return sg->length >> PAGE_SHIFT; | |
3492 | } | |
3493 | ||
3494 | struct scatterlist * | |
3495 | i915_gem_object_get_sg(struct drm_i915_gem_object *obj, | |
3496 | unsigned int n, unsigned int *offset); | |
3497 | ||
3498 | struct page * | |
3499 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, | |
3500 | unsigned int n); | |
3501 | ||
3502 | struct page * | |
3503 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, | |
3504 | unsigned int n); | |
3505 | ||
3506 | dma_addr_t | |
3507 | i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, | |
3508 | unsigned long n); | |
3509 | ||
3510 | void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, | |
3511 | struct sg_table *pages); | |
3512 | int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj); | |
3513 | ||
3514 | static inline int __must_check | |
3515 | i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) | |
3516 | { | |
3517 | might_lock(&obj->mm.lock); | |
3518 | ||
3519 | if (atomic_inc_not_zero(&obj->mm.pages_pin_count)) | |
3520 | return 0; | |
3521 | ||
3522 | return __i915_gem_object_get_pages(obj); | |
3523 | } | |
3524 | ||
3525 | static inline void | |
3526 | __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) | |
3527 | { | |
3528 | GEM_BUG_ON(!obj->mm.pages); | |
3529 | ||
3530 | atomic_inc(&obj->mm.pages_pin_count); | |
3531 | } | |
3532 | ||
3533 | static inline bool | |
3534 | i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj) | |
3535 | { | |
3536 | return atomic_read(&obj->mm.pages_pin_count); | |
3537 | } | |
3538 | ||
3539 | static inline void | |
3540 | __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
3541 | { | |
3542 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); | |
3543 | GEM_BUG_ON(!obj->mm.pages); | |
3544 | ||
3545 | atomic_dec(&obj->mm.pages_pin_count); | |
3546 | } | |
3547 | ||
3548 | static inline void | |
3549 | i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
3550 | { | |
3551 | __i915_gem_object_unpin_pages(obj); | |
3552 | } | |
3553 | ||
3554 | enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */ | |
3555 | I915_MM_NORMAL = 0, | |
3556 | I915_MM_SHRINKER | |
3557 | }; | |
3558 | ||
3559 | void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj, | |
3560 | enum i915_mm_subclass subclass); | |
3561 | void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj); | |
3562 | ||
3563 | enum i915_map_type { | |
3564 | I915_MAP_WB = 0, | |
3565 | I915_MAP_WC, | |
3566 | #define I915_MAP_OVERRIDE BIT(31) | |
3567 | I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE, | |
3568 | I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE, | |
3569 | }; | |
3570 | ||
3571 | /** | |
3572 | * i915_gem_object_pin_map - return a contiguous mapping of the entire object | |
3573 | * @obj: the object to map into kernel address space | |
3574 | * @type: the type of mapping, used to select pgprot_t | |
3575 | * | |
3576 | * Calls i915_gem_object_pin_pages() to prevent reaping of the object's | |
3577 | * pages and then returns a contiguous mapping of the backing storage into | |
3578 | * the kernel address space. Based on the @type of mapping, the PTE will be | |
3579 | * set to either WriteBack or WriteCombine (via pgprot_t). | |
3580 | * | |
3581 | * The caller is responsible for calling i915_gem_object_unpin_map() when the | |
3582 | * mapping is no longer required. | |
3583 | * | |
3584 | * Returns the pointer through which to access the mapped object, or an | |
3585 | * ERR_PTR() on error. | |
3586 | */ | |
3587 | void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj, | |
3588 | enum i915_map_type type); | |
3589 | ||
3590 | /** | |
3591 | * i915_gem_object_unpin_map - releases an earlier mapping | |
3592 | * @obj: the object to unmap | |
3593 | * | |
3594 | * After pinning the object and mapping its pages, once you are finished | |
3595 | * with your access, call i915_gem_object_unpin_map() to release the pin | |
3596 | * upon the mapping. Once the pin count reaches zero, that mapping may be | |
3597 | * removed. | |
3598 | */ | |
3599 | static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj) | |
3600 | { | |
3601 | i915_gem_object_unpin_pages(obj); | |
3602 | } | |
3603 | ||
3604 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
3605 | unsigned int *needs_clflush); | |
3606 | int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, | |
3607 | unsigned int *needs_clflush); | |
3608 | #define CLFLUSH_BEFORE BIT(0) | |
3609 | #define CLFLUSH_AFTER BIT(1) | |
3610 | #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER) | |
3611 | ||
3612 | static inline void | |
3613 | i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj) | |
3614 | { | |
3615 | i915_gem_object_unpin_pages(obj); | |
3616 | } | |
3617 | ||
3618 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); | |
3619 | void i915_vma_move_to_active(struct i915_vma *vma, | |
3620 | struct drm_i915_gem_request *req, | |
3621 | unsigned int flags); | |
3622 | int i915_gem_dumb_create(struct drm_file *file_priv, | |
3623 | struct drm_device *dev, | |
3624 | struct drm_mode_create_dumb *args); | |
3625 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, | |
3626 | uint32_t handle, uint64_t *offset); | |
3627 | int i915_gem_mmap_gtt_version(void); | |
3628 | ||
3629 | void i915_gem_track_fb(struct drm_i915_gem_object *old, | |
3630 | struct drm_i915_gem_object *new, | |
3631 | unsigned frontbuffer_bits); | |
3632 | ||
3633 | int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno); | |
3634 | ||
3635 | struct drm_i915_gem_request * | |
3636 | i915_gem_find_active_request(struct intel_engine_cs *engine); | |
3637 | ||
3638 | void i915_gem_retire_requests(struct drm_i915_private *dev_priv); | |
3639 | ||
3640 | static inline bool i915_reset_backoff(struct i915_gpu_error *error) | |
3641 | { | |
3642 | return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags)); | |
3643 | } | |
3644 | ||
3645 | static inline bool i915_reset_handoff(struct i915_gpu_error *error) | |
3646 | { | |
3647 | return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags)); | |
3648 | } | |
3649 | ||
3650 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) | |
3651 | { | |
3652 | return unlikely(test_bit(I915_WEDGED, &error->flags)); | |
3653 | } | |
3654 | ||
3655 | static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error) | |
3656 | { | |
3657 | return i915_reset_backoff(error) | i915_terminally_wedged(error); | |
3658 | } | |
3659 | ||
3660 | static inline u32 i915_reset_count(struct i915_gpu_error *error) | |
3661 | { | |
3662 | return READ_ONCE(error->reset_count); | |
3663 | } | |
3664 | ||
3665 | static inline u32 i915_reset_engine_count(struct i915_gpu_error *error, | |
3666 | struct intel_engine_cs *engine) | |
3667 | { | |
3668 | return READ_ONCE(error->reset_engine_count[engine->id]); | |
3669 | } | |
3670 | ||
3671 | struct drm_i915_gem_request * | |
3672 | i915_gem_reset_prepare_engine(struct intel_engine_cs *engine); | |
3673 | int i915_gem_reset_prepare(struct drm_i915_private *dev_priv); | |
3674 | void i915_gem_reset(struct drm_i915_private *dev_priv); | |
3675 | void i915_gem_reset_finish_engine(struct intel_engine_cs *engine); | |
3676 | void i915_gem_reset_finish(struct drm_i915_private *dev_priv); | |
3677 | void i915_gem_set_wedged(struct drm_i915_private *dev_priv); | |
3678 | bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv); | |
3679 | void i915_gem_reset_engine(struct intel_engine_cs *engine, | |
3680 | struct drm_i915_gem_request *request); | |
3681 | ||
3682 | void i915_gem_init_mmio(struct drm_i915_private *i915); | |
3683 | int __must_check i915_gem_init(struct drm_i915_private *dev_priv); | |
3684 | int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv); | |
3685 | void i915_gem_init_swizzling(struct drm_i915_private *dev_priv); | |
3686 | void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv); | |
3687 | int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv, | |
3688 | unsigned int flags); | |
3689 | int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv); | |
3690 | void i915_gem_resume(struct drm_i915_private *dev_priv); | |
3691 | int i915_gem_fault(struct vm_fault *vmf); | |
3692 | int i915_gem_object_wait(struct drm_i915_gem_object *obj, | |
3693 | unsigned int flags, | |
3694 | long timeout, | |
3695 | struct intel_rps_client *rps); | |
3696 | int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, | |
3697 | unsigned int flags, | |
3698 | int priority); | |
3699 | #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX | |
3700 | ||
3701 | int __must_check | |
3702 | i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write); | |
3703 | int __must_check | |
3704 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write); | |
3705 | int __must_check | |
3706 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); | |
3707 | struct i915_vma * __must_check | |
3708 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, | |
3709 | u32 alignment, | |
3710 | const struct i915_ggtt_view *view); | |
3711 | void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma); | |
3712 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
3713 | int align); | |
3714 | int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file); | |
3715 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); | |
3716 | ||
3717 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, | |
3718 | enum i915_cache_level cache_level); | |
3719 | ||
3720 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, | |
3721 | struct dma_buf *dma_buf); | |
3722 | ||
3723 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
3724 | struct drm_gem_object *gem_obj, int flags); | |
3725 | ||
3726 | static inline struct i915_hw_ppgtt * | |
3727 | i915_vm_to_ppgtt(struct i915_address_space *vm) | |
3728 | { | |
3729 | return container_of(vm, struct i915_hw_ppgtt, base); | |
3730 | } | |
3731 | ||
3732 | /* i915_gem_fence_reg.c */ | |
3733 | int __must_check i915_vma_get_fence(struct i915_vma *vma); | |
3734 | int __must_check i915_vma_put_fence(struct i915_vma *vma); | |
3735 | struct drm_i915_fence_reg * | |
3736 | i915_reserve_fence(struct drm_i915_private *dev_priv); | |
3737 | void i915_unreserve_fence(struct drm_i915_fence_reg *fence); | |
3738 | ||
3739 | void i915_gem_revoke_fences(struct drm_i915_private *dev_priv); | |
3740 | void i915_gem_restore_fences(struct drm_i915_private *dev_priv); | |
3741 | ||
3742 | void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv); | |
3743 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj, | |
3744 | struct sg_table *pages); | |
3745 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj, | |
3746 | struct sg_table *pages); | |
3747 | ||
3748 | static inline struct i915_gem_context * | |
3749 | __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id) | |
3750 | { | |
3751 | return idr_find(&file_priv->context_idr, id); | |
3752 | } | |
3753 | ||
3754 | static inline struct i915_gem_context * | |
3755 | i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id) | |
3756 | { | |
3757 | struct i915_gem_context *ctx; | |
3758 | ||
3759 | rcu_read_lock(); | |
3760 | ctx = __i915_gem_context_lookup_rcu(file_priv, id); | |
3761 | if (ctx && !kref_get_unless_zero(&ctx->ref)) | |
3762 | ctx = NULL; | |
3763 | rcu_read_unlock(); | |
3764 | ||
3765 | return ctx; | |
3766 | } | |
3767 | ||
3768 | static inline struct intel_timeline * | |
3769 | i915_gem_context_lookup_timeline(struct i915_gem_context *ctx, | |
3770 | struct intel_engine_cs *engine) | |
3771 | { | |
3772 | struct i915_address_space *vm; | |
3773 | ||
3774 | vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base; | |
3775 | return &vm->timeline.engine[engine->id]; | |
3776 | } | |
3777 | ||
3778 | int i915_perf_open_ioctl(struct drm_device *dev, void *data, | |
3779 | struct drm_file *file); | |
3780 | int i915_perf_add_config_ioctl(struct drm_device *dev, void *data, | |
3781 | struct drm_file *file); | |
3782 | int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data, | |
3783 | struct drm_file *file); | |
3784 | void i915_oa_init_reg_state(struct intel_engine_cs *engine, | |
3785 | struct i915_gem_context *ctx, | |
3786 | uint32_t *reg_state); | |
3787 | ||
3788 | /* i915_gem_evict.c */ | |
3789 | int __must_check i915_gem_evict_something(struct i915_address_space *vm, | |
3790 | u64 min_size, u64 alignment, | |
3791 | unsigned cache_level, | |
3792 | u64 start, u64 end, | |
3793 | unsigned flags); | |
3794 | int __must_check i915_gem_evict_for_node(struct i915_address_space *vm, | |
3795 | struct drm_mm_node *node, | |
3796 | unsigned int flags); | |
3797 | int i915_gem_evict_vm(struct i915_address_space *vm); | |
3798 | ||
3799 | /* belongs in i915_gem_gtt.h */ | |
3800 | static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv) | |
3801 | { | |
3802 | wmb(); | |
3803 | if (INTEL_GEN(dev_priv) < 6) | |
3804 | intel_gtt_chipset_flush(); | |
3805 | } | |
3806 | ||
3807 | /* i915_gem_stolen.c */ | |
3808 | int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv, | |
3809 | struct drm_mm_node *node, u64 size, | |
3810 | unsigned alignment); | |
3811 | int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, | |
3812 | struct drm_mm_node *node, u64 size, | |
3813 | unsigned alignment, u64 start, | |
3814 | u64 end); | |
3815 | void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, | |
3816 | struct drm_mm_node *node); | |
3817 | int i915_gem_init_stolen(struct drm_i915_private *dev_priv); | |
3818 | void i915_gem_cleanup_stolen(struct drm_device *dev); | |
3819 | struct drm_i915_gem_object * | |
3820 | i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size); | |
3821 | struct drm_i915_gem_object * | |
3822 | i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv, | |
3823 | u32 stolen_offset, | |
3824 | u32 gtt_offset, | |
3825 | u32 size); | |
3826 | ||
3827 | /* i915_gem_internal.c */ | |
3828 | struct drm_i915_gem_object * | |
3829 | i915_gem_object_create_internal(struct drm_i915_private *dev_priv, | |
3830 | phys_addr_t size); | |
3831 | ||
3832 | /* i915_gem_shrinker.c */ | |
3833 | unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, | |
3834 | unsigned long target, | |
3835 | unsigned long *nr_scanned, | |
3836 | unsigned flags); | |
3837 | #define I915_SHRINK_PURGEABLE 0x1 | |
3838 | #define I915_SHRINK_UNBOUND 0x2 | |
3839 | #define I915_SHRINK_BOUND 0x4 | |
3840 | #define I915_SHRINK_ACTIVE 0x8 | |
3841 | #define I915_SHRINK_VMAPS 0x10 | |
3842 | unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
3843 | void i915_gem_shrinker_init(struct drm_i915_private *dev_priv); | |
3844 | void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv); | |
3845 | ||
3846 | ||
3847 | /* i915_gem_tiling.c */ | |
3848 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) | |
3849 | { | |
3850 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); | |
3851 | ||
3852 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
3853 | i915_gem_object_is_tiled(obj); | |
3854 | } | |
3855 | ||
3856 | u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size, | |
3857 | unsigned int tiling, unsigned int stride); | |
3858 | u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size, | |
3859 | unsigned int tiling, unsigned int stride); | |
3860 | ||
3861 | /* i915_debugfs.c */ | |
3862 | #ifdef CONFIG_DEBUG_FS | |
3863 | int i915_debugfs_register(struct drm_i915_private *dev_priv); | |
3864 | int i915_debugfs_connector_add(struct drm_connector *connector); | |
3865 | void intel_display_crc_init(struct drm_i915_private *dev_priv); | |
3866 | #else | |
3867 | static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;} | |
3868 | static inline int i915_debugfs_connector_add(struct drm_connector *connector) | |
3869 | { return 0; } | |
3870 | static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {} | |
3871 | #endif | |
3872 | ||
3873 | /* i915_gpu_error.c */ | |
3874 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) | |
3875 | ||
3876 | __printf(2, 3) | |
3877 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
3878 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, | |
3879 | const struct i915_gpu_state *gpu); | |
3880 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, | |
3881 | struct drm_i915_private *i915, | |
3882 | size_t count, loff_t pos); | |
3883 | static inline void i915_error_state_buf_release( | |
3884 | struct drm_i915_error_state_buf *eb) | |
3885 | { | |
3886 | kfree(eb->buf); | |
3887 | } | |
3888 | ||
3889 | struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915); | |
3890 | void i915_capture_error_state(struct drm_i915_private *dev_priv, | |
3891 | u32 engine_mask, | |
3892 | const char *error_msg); | |
3893 | ||
3894 | static inline struct i915_gpu_state * | |
3895 | i915_gpu_state_get(struct i915_gpu_state *gpu) | |
3896 | { | |
3897 | kref_get(&gpu->ref); | |
3898 | return gpu; | |
3899 | } | |
3900 | ||
3901 | void __i915_gpu_state_free(struct kref *kref); | |
3902 | static inline void i915_gpu_state_put(struct i915_gpu_state *gpu) | |
3903 | { | |
3904 | if (gpu) | |
3905 | kref_put(&gpu->ref, __i915_gpu_state_free); | |
3906 | } | |
3907 | ||
3908 | struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915); | |
3909 | void i915_reset_error_state(struct drm_i915_private *i915); | |
3910 | ||
3911 | #else | |
3912 | ||
3913 | static inline void i915_capture_error_state(struct drm_i915_private *dev_priv, | |
3914 | u32 engine_mask, | |
3915 | const char *error_msg) | |
3916 | { | |
3917 | } | |
3918 | ||
3919 | static inline struct i915_gpu_state * | |
3920 | i915_first_error_state(struct drm_i915_private *i915) | |
3921 | { | |
3922 | return NULL; | |
3923 | } | |
3924 | ||
3925 | static inline void i915_reset_error_state(struct drm_i915_private *i915) | |
3926 | { | |
3927 | } | |
3928 | ||
3929 | #endif | |
3930 | ||
3931 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type); | |
3932 | ||
3933 | /* i915_cmd_parser.c */ | |
3934 | int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); | |
3935 | void intel_engine_init_cmd_parser(struct intel_engine_cs *engine); | |
3936 | void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine); | |
3937 | int intel_engine_cmd_parser(struct intel_engine_cs *engine, | |
3938 | struct drm_i915_gem_object *batch_obj, | |
3939 | struct drm_i915_gem_object *shadow_batch_obj, | |
3940 | u32 batch_start_offset, | |
3941 | u32 batch_len, | |
3942 | bool is_master); | |
3943 | ||
3944 | /* i915_perf.c */ | |
3945 | extern void i915_perf_init(struct drm_i915_private *dev_priv); | |
3946 | extern void i915_perf_fini(struct drm_i915_private *dev_priv); | |
3947 | extern void i915_perf_register(struct drm_i915_private *dev_priv); | |
3948 | extern void i915_perf_unregister(struct drm_i915_private *dev_priv); | |
3949 | ||
3950 | /* i915_suspend.c */ | |
3951 | extern int i915_save_state(struct drm_i915_private *dev_priv); | |
3952 | extern int i915_restore_state(struct drm_i915_private *dev_priv); | |
3953 | ||
3954 | /* i915_sysfs.c */ | |
3955 | void i915_setup_sysfs(struct drm_i915_private *dev_priv); | |
3956 | void i915_teardown_sysfs(struct drm_i915_private *dev_priv); | |
3957 | ||
3958 | /* intel_lpe_audio.c */ | |
3959 | int intel_lpe_audio_init(struct drm_i915_private *dev_priv); | |
3960 | void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv); | |
3961 | void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv); | |
3962 | void intel_lpe_audio_notify(struct drm_i915_private *dev_priv, | |
3963 | enum pipe pipe, enum port port, | |
3964 | const void *eld, int ls_clock, bool dp_output); | |
3965 | ||
3966 | /* intel_i2c.c */ | |
3967 | extern int intel_setup_gmbus(struct drm_i915_private *dev_priv); | |
3968 | extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv); | |
3969 | extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, | |
3970 | unsigned int pin); | |
3971 | ||
3972 | extern struct i2c_adapter * | |
3973 | intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); | |
3974 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); | |
3975 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
3976 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) | |
3977 | { | |
3978 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
3979 | } | |
3980 | extern void intel_i2c_reset(struct drm_i915_private *dev_priv); | |
3981 | ||
3982 | /* intel_bios.c */ | |
3983 | void intel_bios_init(struct drm_i915_private *dev_priv); | |
3984 | bool intel_bios_is_valid_vbt(const void *buf, size_t size); | |
3985 | bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv); | |
3986 | bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin); | |
3987 | bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port); | |
3988 | bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port); | |
3989 | bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port); | |
3990 | bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port); | |
3991 | bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv, | |
3992 | enum port port); | |
3993 | bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv, | |
3994 | enum port port); | |
3995 | ||
3996 | ||
3997 | /* intel_opregion.c */ | |
3998 | #ifdef CONFIG_ACPI | |
3999 | extern int intel_opregion_setup(struct drm_i915_private *dev_priv); | |
4000 | extern void intel_opregion_register(struct drm_i915_private *dev_priv); | |
4001 | extern void intel_opregion_unregister(struct drm_i915_private *dev_priv); | |
4002 | extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv); | |
4003 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, | |
4004 | bool enable); | |
4005 | extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv, | |
4006 | pci_power_t state); | |
4007 | extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv); | |
4008 | #else | |
4009 | static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; } | |
4010 | static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { } | |
4011 | static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { } | |
4012 | static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv) | |
4013 | { | |
4014 | } | |
4015 | static inline int | |
4016 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) | |
4017 | { | |
4018 | return 0; | |
4019 | } | |
4020 | static inline int | |
4021 | intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state) | |
4022 | { | |
4023 | return 0; | |
4024 | } | |
4025 | static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev) | |
4026 | { | |
4027 | return -ENODEV; | |
4028 | } | |
4029 | #endif | |
4030 | ||
4031 | /* intel_acpi.c */ | |
4032 | #ifdef CONFIG_ACPI | |
4033 | extern void intel_register_dsm_handler(void); | |
4034 | extern void intel_unregister_dsm_handler(void); | |
4035 | #else | |
4036 | static inline void intel_register_dsm_handler(void) { return; } | |
4037 | static inline void intel_unregister_dsm_handler(void) { return; } | |
4038 | #endif /* CONFIG_ACPI */ | |
4039 | ||
4040 | /* intel_device_info.c */ | |
4041 | static inline struct intel_device_info * | |
4042 | mkwrite_device_info(struct drm_i915_private *dev_priv) | |
4043 | { | |
4044 | return (struct intel_device_info *)&dev_priv->info; | |
4045 | } | |
4046 | ||
4047 | const char *intel_platform_name(enum intel_platform platform); | |
4048 | void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); | |
4049 | void intel_device_info_dump(struct drm_i915_private *dev_priv); | |
4050 | ||
4051 | /* modesetting */ | |
4052 | extern void intel_modeset_init_hw(struct drm_device *dev); | |
4053 | extern int intel_modeset_init(struct drm_device *dev); | |
4054 | extern void intel_modeset_gem_init(struct drm_device *dev); | |
4055 | extern void intel_modeset_cleanup(struct drm_device *dev); | |
4056 | extern int intel_connector_register(struct drm_connector *); | |
4057 | extern void intel_connector_unregister(struct drm_connector *); | |
4058 | extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, | |
4059 | bool state); | |
4060 | extern void intel_display_resume(struct drm_device *dev); | |
4061 | extern void i915_redisable_vga(struct drm_i915_private *dev_priv); | |
4062 | extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv); | |
4063 | extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val); | |
4064 | extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv); | |
4065 | extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val); | |
4066 | extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, | |
4067 | bool enable); | |
4068 | ||
4069 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, | |
4070 | struct drm_file *file); | |
4071 | ||
4072 | /* overlay */ | |
4073 | extern struct intel_overlay_error_state * | |
4074 | intel_overlay_capture_error_state(struct drm_i915_private *dev_priv); | |
4075 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, | |
4076 | struct intel_overlay_error_state *error); | |
4077 | ||
4078 | extern struct intel_display_error_state * | |
4079 | intel_display_capture_error_state(struct drm_i915_private *dev_priv); | |
4080 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, | |
4081 | struct intel_display_error_state *error); | |
4082 | ||
4083 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); | |
4084 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); | |
4085 | int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request, | |
4086 | u32 reply_mask, u32 reply, int timeout_base_ms); | |
4087 | ||
4088 | /* intel_sideband.c */ | |
4089 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); | |
4090 | int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); | |
4091 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); | |
4092 | u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg); | |
4093 | void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val); | |
4094 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); | |
4095 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
4096 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
4097 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
4098 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); | |
4099 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
4100 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); | |
4101 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
4102 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, | |
4103 | enum intel_sbi_destination destination); | |
4104 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
4105 | enum intel_sbi_destination destination); | |
4106 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); | |
4107 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
4108 | ||
4109 | /* intel_dpio_phy.c */ | |
4110 | void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, | |
4111 | enum dpio_phy *phy, enum dpio_channel *ch); | |
4112 | void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv, | |
4113 | enum port port, u32 margin, u32 scale, | |
4114 | u32 enable, u32 deemphasis); | |
4115 | void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy); | |
4116 | void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy); | |
4117 | bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, | |
4118 | enum dpio_phy phy); | |
4119 | bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv, | |
4120 | enum dpio_phy phy); | |
4121 | uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder, | |
4122 | uint8_t lane_count); | |
4123 | void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder, | |
4124 | uint8_t lane_lat_optim_mask); | |
4125 | uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder); | |
4126 | ||
4127 | void chv_set_phy_signal_level(struct intel_encoder *encoder, | |
4128 | u32 deemph_reg_value, u32 margin_reg_value, | |
4129 | bool uniq_trans_scale); | |
4130 | void chv_data_lane_soft_reset(struct intel_encoder *encoder, | |
4131 | bool reset); | |
4132 | void chv_phy_pre_pll_enable(struct intel_encoder *encoder); | |
4133 | void chv_phy_pre_encoder_enable(struct intel_encoder *encoder); | |
4134 | void chv_phy_release_cl2_override(struct intel_encoder *encoder); | |
4135 | void chv_phy_post_pll_disable(struct intel_encoder *encoder); | |
4136 | ||
4137 | void vlv_set_phy_signal_level(struct intel_encoder *encoder, | |
4138 | u32 demph_reg_value, u32 preemph_reg_value, | |
4139 | u32 uniqtranscale_reg_value, u32 tx3_demph); | |
4140 | void vlv_phy_pre_pll_enable(struct intel_encoder *encoder); | |
4141 | void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder); | |
4142 | void vlv_phy_reset_lanes(struct intel_encoder *encoder); | |
4143 | ||
4144 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); | |
4145 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); | |
4146 | u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, | |
4147 | const i915_reg_t reg); | |
4148 | ||
4149 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) | |
4150 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
4151 | ||
4152 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
4153 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
4154 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
4155 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
4156 | ||
4157 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
4158 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
4159 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
4160 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
4161 | ||
4162 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they | |
4163 | * will be implemented using 2 32-bit writes in an arbitrary order with | |
4164 | * an arbitrary delay between them. This can cause the hardware to | |
4165 | * act upon the intermediate value, possibly leading to corruption and | |
4166 | * machine death. For this reason we do not support I915_WRITE64, or | |
4167 | * dev_priv->uncore.funcs.mmio_writeq. | |
4168 | * | |
4169 | * When reading a 64-bit value as two 32-bit values, the delay may cause | |
4170 | * the two reads to mismatch, e.g. a timestamp overflowing. Also note that | |
4171 | * occasionally a 64-bit register does not actualy support a full readq | |
4172 | * and must be read using two 32-bit reads. | |
4173 | * | |
4174 | * You have been warned. | |
4175 | */ | |
4176 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) | |
4177 | ||
4178 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ | |
4179 | u32 upper, lower, old_upper, loop = 0; \ | |
4180 | upper = I915_READ(upper_reg); \ | |
4181 | do { \ | |
4182 | old_upper = upper; \ | |
4183 | lower = I915_READ(lower_reg); \ | |
4184 | upper = I915_READ(upper_reg); \ | |
4185 | } while (upper != old_upper && loop++ < 2); \ | |
4186 | (u64)upper << 32 | lower; }) | |
4187 | ||
4188 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) | |
4189 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
4190 | ||
4191 | #define __raw_read(x, s) \ | |
4192 | static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \ | |
4193 | i915_reg_t reg) \ | |
4194 | { \ | |
4195 | return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \ | |
4196 | } | |
4197 | ||
4198 | #define __raw_write(x, s) \ | |
4199 | static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \ | |
4200 | i915_reg_t reg, uint##x##_t val) \ | |
4201 | { \ | |
4202 | write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \ | |
4203 | } | |
4204 | __raw_read(8, b) | |
4205 | __raw_read(16, w) | |
4206 | __raw_read(32, l) | |
4207 | __raw_read(64, q) | |
4208 | ||
4209 | __raw_write(8, b) | |
4210 | __raw_write(16, w) | |
4211 | __raw_write(32, l) | |
4212 | __raw_write(64, q) | |
4213 | ||
4214 | #undef __raw_read | |
4215 | #undef __raw_write | |
4216 | ||
4217 | /* These are untraced mmio-accessors that are only valid to be used inside | |
4218 | * critical sections, such as inside IRQ handlers, where forcewake is explicitly | |
4219 | * controlled. | |
4220 | * | |
4221 | * Think twice, and think again, before using these. | |
4222 | * | |
4223 | * As an example, these accessors can possibly be used between: | |
4224 | * | |
4225 | * spin_lock_irq(&dev_priv->uncore.lock); | |
4226 | * intel_uncore_forcewake_get__locked(); | |
4227 | * | |
4228 | * and | |
4229 | * | |
4230 | * intel_uncore_forcewake_put__locked(); | |
4231 | * spin_unlock_irq(&dev_priv->uncore.lock); | |
4232 | * | |
4233 | * | |
4234 | * Note: some registers may not need forcewake held, so | |
4235 | * intel_uncore_forcewake_{get,put} can be omitted, see | |
4236 | * intel_uncore_forcewake_for_reg(). | |
4237 | * | |
4238 | * Certain architectures will die if the same cacheline is concurrently accessed | |
4239 | * by different clients (e.g. on Ivybridge). Access to registers should | |
4240 | * therefore generally be serialised, by either the dev_priv->uncore.lock or | |
4241 | * a more localised lock guarding all access to that bank of registers. | |
4242 | */ | |
4243 | #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__)) | |
4244 | #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__)) | |
4245 | #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__)) | |
4246 | #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) | |
4247 | ||
4248 | /* "Broadcast RGB" property */ | |
4249 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
4250 | #define INTEL_BROADCAST_RGB_FULL 1 | |
4251 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
4252 | ||
4253 | static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv) | |
4254 | { | |
4255 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
4256 | return VLV_VGACNTRL; | |
4257 | else if (INTEL_GEN(dev_priv) >= 5) | |
4258 | return CPU_VGACNTRL; | |
4259 | else | |
4260 | return VGACNTRL; | |
4261 | } | |
4262 | ||
4263 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) | |
4264 | { | |
4265 | unsigned long j = msecs_to_jiffies(m); | |
4266 | ||
4267 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
4268 | } | |
4269 | ||
4270 | static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) | |
4271 | { | |
4272 | /* nsecs_to_jiffies64() does not guard against overflow */ | |
4273 | if (NSEC_PER_SEC % HZ && | |
4274 | div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ) | |
4275 | return MAX_JIFFY_OFFSET; | |
4276 | ||
4277 | return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); | |
4278 | } | |
4279 | ||
4280 | static inline unsigned long | |
4281 | timespec_to_jiffies_timeout(const struct timespec *value) | |
4282 | { | |
4283 | unsigned long j = timespec_to_jiffies(value); | |
4284 | ||
4285 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
4286 | } | |
4287 | ||
4288 | /* | |
4289 | * If you need to wait X milliseconds between events A and B, but event B | |
4290 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of | |
4291 | * when event A happened, then just before event B you call this function and | |
4292 | * pass the timestamp as the first argument, and X as the second argument. | |
4293 | */ | |
4294 | static inline void | |
4295 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) | |
4296 | { | |
4297 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; | |
4298 | ||
4299 | /* | |
4300 | * Don't re-read the value of "jiffies" every time since it may change | |
4301 | * behind our back and break the math. | |
4302 | */ | |
4303 | tmp_jiffies = jiffies; | |
4304 | target_jiffies = timestamp_jiffies + | |
4305 | msecs_to_jiffies_timeout(to_wait_ms); | |
4306 | ||
4307 | if (time_after(target_jiffies, tmp_jiffies)) { | |
4308 | remaining_jiffies = target_jiffies - tmp_jiffies; | |
4309 | while (remaining_jiffies) | |
4310 | remaining_jiffies = | |
4311 | schedule_timeout_uninterruptible(remaining_jiffies); | |
4312 | } | |
4313 | } | |
4314 | ||
4315 | static inline bool | |
4316 | __i915_request_irq_complete(const struct drm_i915_gem_request *req) | |
4317 | { | |
4318 | struct intel_engine_cs *engine = req->engine; | |
4319 | u32 seqno; | |
4320 | ||
4321 | /* Note that the engine may have wrapped around the seqno, and | |
4322 | * so our request->global_seqno will be ahead of the hardware, | |
4323 | * even though it completed the request before wrapping. We catch | |
4324 | * this by kicking all the waiters before resetting the seqno | |
4325 | * in hardware, and also signal the fence. | |
4326 | */ | |
4327 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &req->fence.flags)) | |
4328 | return true; | |
4329 | ||
4330 | /* The request was dequeued before we were awoken. We check after | |
4331 | * inspecting the hw to confirm that this was the same request | |
4332 | * that generated the HWS update. The memory barriers within | |
4333 | * the request execution are sufficient to ensure that a check | |
4334 | * after reading the value from hw matches this request. | |
4335 | */ | |
4336 | seqno = i915_gem_request_global_seqno(req); | |
4337 | if (!seqno) | |
4338 | return false; | |
4339 | ||
4340 | /* Before we do the heavier coherent read of the seqno, | |
4341 | * check the value (hopefully) in the CPU cacheline. | |
4342 | */ | |
4343 | if (__i915_gem_request_completed(req, seqno)) | |
4344 | return true; | |
4345 | ||
4346 | /* Ensure our read of the seqno is coherent so that we | |
4347 | * do not "miss an interrupt" (i.e. if this is the last | |
4348 | * request and the seqno write from the GPU is not visible | |
4349 | * by the time the interrupt fires, we will see that the | |
4350 | * request is incomplete and go back to sleep awaiting | |
4351 | * another interrupt that will never come.) | |
4352 | * | |
4353 | * Strictly, we only need to do this once after an interrupt, | |
4354 | * but it is easier and safer to do it every time the waiter | |
4355 | * is woken. | |
4356 | */ | |
4357 | if (engine->irq_seqno_barrier && | |
4358 | test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) { | |
4359 | struct intel_breadcrumbs *b = &engine->breadcrumbs; | |
4360 | ||
4361 | /* The ordering of irq_posted versus applying the barrier | |
4362 | * is crucial. The clearing of the current irq_posted must | |
4363 | * be visible before we perform the barrier operation, | |
4364 | * such that if a subsequent interrupt arrives, irq_posted | |
4365 | * is reasserted and our task rewoken (which causes us to | |
4366 | * do another __i915_request_irq_complete() immediately | |
4367 | * and reapply the barrier). Conversely, if the clear | |
4368 | * occurs after the barrier, then an interrupt that arrived | |
4369 | * whilst we waited on the barrier would not trigger a | |
4370 | * barrier on the next pass, and the read may not see the | |
4371 | * seqno update. | |
4372 | */ | |
4373 | engine->irq_seqno_barrier(engine); | |
4374 | ||
4375 | /* If we consume the irq, but we are no longer the bottom-half, | |
4376 | * the real bottom-half may not have serialised their own | |
4377 | * seqno check with the irq-barrier (i.e. may have inspected | |
4378 | * the seqno before we believe it coherent since they see | |
4379 | * irq_posted == false but we are still running). | |
4380 | */ | |
4381 | spin_lock_irq(&b->irq_lock); | |
4382 | if (b->irq_wait && b->irq_wait->tsk != current) | |
4383 | /* Note that if the bottom-half is changed as we | |
4384 | * are sending the wake-up, the new bottom-half will | |
4385 | * be woken by whomever made the change. We only have | |
4386 | * to worry about when we steal the irq-posted for | |
4387 | * ourself. | |
4388 | */ | |
4389 | wake_up_process(b->irq_wait->tsk); | |
4390 | spin_unlock_irq(&b->irq_lock); | |
4391 | ||
4392 | if (__i915_gem_request_completed(req, seqno)) | |
4393 | return true; | |
4394 | } | |
4395 | ||
4396 | return false; | |
4397 | } | |
4398 | ||
4399 | void i915_memcpy_init_early(struct drm_i915_private *dev_priv); | |
4400 | bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len); | |
4401 | ||
4402 | /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment, | |
4403 | * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot | |
4404 | * perform the operation. To check beforehand, pass in the parameters to | |
4405 | * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits, | |
4406 | * you only need to pass in the minor offsets, page-aligned pointers are | |
4407 | * always valid. | |
4408 | * | |
4409 | * For just checking for SSE4.1, in the foreknowledge that the future use | |
4410 | * will be correctly aligned, just use i915_has_memcpy_from_wc(). | |
4411 | */ | |
4412 | #define i915_can_memcpy_from_wc(dst, src, len) \ | |
4413 | i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0) | |
4414 | ||
4415 | #define i915_has_memcpy_from_wc() \ | |
4416 | i915_memcpy_from_wc(NULL, NULL, 0) | |
4417 | ||
4418 | /* i915_mm.c */ | |
4419 | int remap_io_mapping(struct vm_area_struct *vma, | |
4420 | unsigned long addr, unsigned long pfn, unsigned long size, | |
4421 | struct io_mapping *iomap); | |
4422 | ||
4423 | static inline int intel_hws_csb_write_index(struct drm_i915_private *i915) | |
4424 | { | |
4425 | if (INTEL_GEN(i915) >= 10) | |
4426 | return CNL_HWS_CSB_WRITE_INDEX; | |
4427 | else | |
4428 | return I915_HWS_CSB_WRITE_INDEX; | |
4429 | } | |
4430 | ||
4431 | #endif |