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1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- | |
2 | */ | |
3 | /* | |
4 | * | |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. | |
6 | * All Rights Reserved. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
28 | */ | |
29 | ||
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
33 | #include <uapi/drm/i915_drm.h> | |
34 | ||
35 | #include "i915_reg.h" | |
36 | #include "intel_bios.h" | |
37 | #include "intel_ringbuffer.h" | |
38 | #include "intel_lrc.h" | |
39 | #include "i915_gem_gtt.h" | |
40 | #include "i915_gem_render_state.h" | |
41 | #include <linux/io-mapping.h> | |
42 | #include <linux/i2c.h> | |
43 | #include <linux/i2c-algo-bit.h> | |
44 | #include <drm/intel-gtt.h> | |
45 | #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ | |
46 | #include <drm/drm_gem.h> | |
47 | #include <linux/backlight.h> | |
48 | #include <linux/hashtable.h> | |
49 | #include <linux/intel-iommu.h> | |
50 | #include <linux/kref.h> | |
51 | #include <linux/pm_qos.h> | |
52 | ||
53 | /* General customization: | |
54 | */ | |
55 | ||
56 | #define DRIVER_NAME "i915" | |
57 | #define DRIVER_DESC "Intel Graphics" | |
58 | #define DRIVER_DATE "20150117" | |
59 | ||
60 | #undef WARN_ON | |
61 | /* Many gcc seem to no see through this and fall over :( */ | |
62 | #if 0 | |
63 | #define WARN_ON(x) ({ \ | |
64 | bool __i915_warn_cond = (x); \ | |
65 | if (__builtin_constant_p(__i915_warn_cond)) \ | |
66 | BUILD_BUG_ON(__i915_warn_cond); \ | |
67 | WARN(__i915_warn_cond, "WARN_ON(" #x ")"); }) | |
68 | #else | |
69 | #define WARN_ON(x) WARN((x), "WARN_ON(" #x ")") | |
70 | #endif | |
71 | ||
72 | #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \ | |
73 | (long) (x), __func__); | |
74 | ||
75 | /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and | |
76 | * WARN_ON()) for hw state sanity checks to check for unexpected conditions | |
77 | * which may not necessarily be a user visible problem. This will either | |
78 | * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to | |
79 | * enable distros and users to tailor their preferred amount of i915 abrt | |
80 | * spam. | |
81 | */ | |
82 | #define I915_STATE_WARN(condition, format...) ({ \ | |
83 | int __ret_warn_on = !!(condition); \ | |
84 | if (unlikely(__ret_warn_on)) { \ | |
85 | if (i915.verbose_state_checks) \ | |
86 | WARN(1, format); \ | |
87 | else \ | |
88 | DRM_ERROR(format); \ | |
89 | } \ | |
90 | unlikely(__ret_warn_on); \ | |
91 | }) | |
92 | ||
93 | #define I915_STATE_WARN_ON(condition) ({ \ | |
94 | int __ret_warn_on = !!(condition); \ | |
95 | if (unlikely(__ret_warn_on)) { \ | |
96 | if (i915.verbose_state_checks) \ | |
97 | WARN(1, "WARN_ON(" #condition ")\n"); \ | |
98 | else \ | |
99 | DRM_ERROR("WARN_ON(" #condition ")\n"); \ | |
100 | } \ | |
101 | unlikely(__ret_warn_on); \ | |
102 | }) | |
103 | ||
104 | enum pipe { | |
105 | INVALID_PIPE = -1, | |
106 | PIPE_A = 0, | |
107 | PIPE_B, | |
108 | PIPE_C, | |
109 | _PIPE_EDP, | |
110 | I915_MAX_PIPES = _PIPE_EDP | |
111 | }; | |
112 | #define pipe_name(p) ((p) + 'A') | |
113 | ||
114 | enum transcoder { | |
115 | TRANSCODER_A = 0, | |
116 | TRANSCODER_B, | |
117 | TRANSCODER_C, | |
118 | TRANSCODER_EDP, | |
119 | I915_MAX_TRANSCODERS | |
120 | }; | |
121 | #define transcoder_name(t) ((t) + 'A') | |
122 | ||
123 | /* | |
124 | * This is the maximum (across all platforms) number of planes (primary + | |
125 | * sprites) that can be active at the same time on one pipe. | |
126 | * | |
127 | * This value doesn't count the cursor plane. | |
128 | */ | |
129 | #define I915_MAX_PLANES 3 | |
130 | ||
131 | enum plane { | |
132 | PLANE_A = 0, | |
133 | PLANE_B, | |
134 | PLANE_C, | |
135 | }; | |
136 | #define plane_name(p) ((p) + 'A') | |
137 | ||
138 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') | |
139 | ||
140 | enum port { | |
141 | PORT_A = 0, | |
142 | PORT_B, | |
143 | PORT_C, | |
144 | PORT_D, | |
145 | PORT_E, | |
146 | I915_MAX_PORTS | |
147 | }; | |
148 | #define port_name(p) ((p) + 'A') | |
149 | ||
150 | #define I915_NUM_PHYS_VLV 2 | |
151 | ||
152 | enum dpio_channel { | |
153 | DPIO_CH0, | |
154 | DPIO_CH1 | |
155 | }; | |
156 | ||
157 | enum dpio_phy { | |
158 | DPIO_PHY0, | |
159 | DPIO_PHY1 | |
160 | }; | |
161 | ||
162 | enum intel_display_power_domain { | |
163 | POWER_DOMAIN_PIPE_A, | |
164 | POWER_DOMAIN_PIPE_B, | |
165 | POWER_DOMAIN_PIPE_C, | |
166 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
167 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
168 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
169 | POWER_DOMAIN_TRANSCODER_A, | |
170 | POWER_DOMAIN_TRANSCODER_B, | |
171 | POWER_DOMAIN_TRANSCODER_C, | |
172 | POWER_DOMAIN_TRANSCODER_EDP, | |
173 | POWER_DOMAIN_PORT_DDI_A_2_LANES, | |
174 | POWER_DOMAIN_PORT_DDI_A_4_LANES, | |
175 | POWER_DOMAIN_PORT_DDI_B_2_LANES, | |
176 | POWER_DOMAIN_PORT_DDI_B_4_LANES, | |
177 | POWER_DOMAIN_PORT_DDI_C_2_LANES, | |
178 | POWER_DOMAIN_PORT_DDI_C_4_LANES, | |
179 | POWER_DOMAIN_PORT_DDI_D_2_LANES, | |
180 | POWER_DOMAIN_PORT_DDI_D_4_LANES, | |
181 | POWER_DOMAIN_PORT_DSI, | |
182 | POWER_DOMAIN_PORT_CRT, | |
183 | POWER_DOMAIN_PORT_OTHER, | |
184 | POWER_DOMAIN_VGA, | |
185 | POWER_DOMAIN_AUDIO, | |
186 | POWER_DOMAIN_PLLS, | |
187 | POWER_DOMAIN_INIT, | |
188 | ||
189 | POWER_DOMAIN_NUM, | |
190 | }; | |
191 | ||
192 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) | |
193 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
194 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
195 | #define POWER_DOMAIN_TRANSCODER(tran) \ | |
196 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ | |
197 | (tran) + POWER_DOMAIN_TRANSCODER_A) | |
198 | ||
199 | enum hpd_pin { | |
200 | HPD_NONE = 0, | |
201 | HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ | |
202 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ | |
203 | HPD_CRT, | |
204 | HPD_SDVO_B, | |
205 | HPD_SDVO_C, | |
206 | HPD_PORT_B, | |
207 | HPD_PORT_C, | |
208 | HPD_PORT_D, | |
209 | HPD_NUM_PINS | |
210 | }; | |
211 | ||
212 | #define I915_GEM_GPU_DOMAINS \ | |
213 | (I915_GEM_DOMAIN_RENDER | \ | |
214 | I915_GEM_DOMAIN_SAMPLER | \ | |
215 | I915_GEM_DOMAIN_COMMAND | \ | |
216 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
217 | I915_GEM_DOMAIN_VERTEX) | |
218 | ||
219 | #define for_each_pipe(__dev_priv, __p) \ | |
220 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) | |
221 | #define for_each_plane(pipe, p) \ | |
222 | for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++) | |
223 | #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++) | |
224 | ||
225 | #define for_each_crtc(dev, crtc) \ | |
226 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
227 | ||
228 | #define for_each_intel_crtc(dev, intel_crtc) \ | |
229 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) | |
230 | ||
231 | #define for_each_intel_encoder(dev, intel_encoder) \ | |
232 | list_for_each_entry(intel_encoder, \ | |
233 | &(dev)->mode_config.encoder_list, \ | |
234 | base.head) | |
235 | ||
236 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ | |
237 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
238 | if ((intel_encoder)->base.crtc == (__crtc)) | |
239 | ||
240 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ | |
241 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ | |
242 | if ((intel_connector)->base.encoder == (__encoder)) | |
243 | ||
244 | #define for_each_power_domain(domain, mask) \ | |
245 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
246 | if ((1 << (domain)) & (mask)) | |
247 | ||
248 | struct drm_i915_private; | |
249 | struct i915_mm_struct; | |
250 | struct i915_mmu_object; | |
251 | ||
252 | enum intel_dpll_id { | |
253 | DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ | |
254 | /* real shared dpll ids must be >= 0 */ | |
255 | DPLL_ID_PCH_PLL_A = 0, | |
256 | DPLL_ID_PCH_PLL_B = 1, | |
257 | /* hsw/bdw */ | |
258 | DPLL_ID_WRPLL1 = 0, | |
259 | DPLL_ID_WRPLL2 = 1, | |
260 | /* skl */ | |
261 | DPLL_ID_SKL_DPLL1 = 0, | |
262 | DPLL_ID_SKL_DPLL2 = 1, | |
263 | DPLL_ID_SKL_DPLL3 = 2, | |
264 | }; | |
265 | #define I915_NUM_PLLS 3 | |
266 | ||
267 | struct intel_dpll_hw_state { | |
268 | /* i9xx, pch plls */ | |
269 | uint32_t dpll; | |
270 | uint32_t dpll_md; | |
271 | uint32_t fp0; | |
272 | uint32_t fp1; | |
273 | ||
274 | /* hsw, bdw */ | |
275 | uint32_t wrpll; | |
276 | ||
277 | /* skl */ | |
278 | /* | |
279 | * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in | |
280 | * lower part of crtl1 and they get shifted into position when writing | |
281 | * the register. This allows us to easily compare the state to share | |
282 | * the DPLL. | |
283 | */ | |
284 | uint32_t ctrl1; | |
285 | /* HDMI only, 0 when used for DP */ | |
286 | uint32_t cfgcr1, cfgcr2; | |
287 | }; | |
288 | ||
289 | struct intel_shared_dpll_config { | |
290 | unsigned crtc_mask; /* mask of CRTCs sharing this PLL */ | |
291 | struct intel_dpll_hw_state hw_state; | |
292 | }; | |
293 | ||
294 | struct intel_shared_dpll { | |
295 | struct intel_shared_dpll_config config; | |
296 | struct intel_shared_dpll_config *new_config; | |
297 | ||
298 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ | |
299 | bool on; /* is the PLL actually active? Disabled during modeset */ | |
300 | const char *name; | |
301 | /* should match the index in the dev_priv->shared_dplls array */ | |
302 | enum intel_dpll_id id; | |
303 | /* The mode_set hook is optional and should be used together with the | |
304 | * intel_prepare_shared_dpll function. */ | |
305 | void (*mode_set)(struct drm_i915_private *dev_priv, | |
306 | struct intel_shared_dpll *pll); | |
307 | void (*enable)(struct drm_i915_private *dev_priv, | |
308 | struct intel_shared_dpll *pll); | |
309 | void (*disable)(struct drm_i915_private *dev_priv, | |
310 | struct intel_shared_dpll *pll); | |
311 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, | |
312 | struct intel_shared_dpll *pll, | |
313 | struct intel_dpll_hw_state *hw_state); | |
314 | }; | |
315 | ||
316 | #define SKL_DPLL0 0 | |
317 | #define SKL_DPLL1 1 | |
318 | #define SKL_DPLL2 2 | |
319 | #define SKL_DPLL3 3 | |
320 | ||
321 | /* Used by dp and fdi links */ | |
322 | struct intel_link_m_n { | |
323 | uint32_t tu; | |
324 | uint32_t gmch_m; | |
325 | uint32_t gmch_n; | |
326 | uint32_t link_m; | |
327 | uint32_t link_n; | |
328 | }; | |
329 | ||
330 | void intel_link_compute_m_n(int bpp, int nlanes, | |
331 | int pixel_clock, int link_clock, | |
332 | struct intel_link_m_n *m_n); | |
333 | ||
334 | /* Interface history: | |
335 | * | |
336 | * 1.1: Original. | |
337 | * 1.2: Add Power Management | |
338 | * 1.3: Add vblank support | |
339 | * 1.4: Fix cmdbuffer path, add heap destroy | |
340 | * 1.5: Add vblank pipe configuration | |
341 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank | |
342 | * - Support vertical blank on secondary display pipe | |
343 | */ | |
344 | #define DRIVER_MAJOR 1 | |
345 | #define DRIVER_MINOR 6 | |
346 | #define DRIVER_PATCHLEVEL 0 | |
347 | ||
348 | #define WATCH_LISTS 0 | |
349 | ||
350 | struct opregion_header; | |
351 | struct opregion_acpi; | |
352 | struct opregion_swsci; | |
353 | struct opregion_asle; | |
354 | ||
355 | struct intel_opregion { | |
356 | struct opregion_header __iomem *header; | |
357 | struct opregion_acpi __iomem *acpi; | |
358 | struct opregion_swsci __iomem *swsci; | |
359 | u32 swsci_gbda_sub_functions; | |
360 | u32 swsci_sbcb_sub_functions; | |
361 | struct opregion_asle __iomem *asle; | |
362 | void __iomem *vbt; | |
363 | u32 __iomem *lid_state; | |
364 | struct work_struct asle_work; | |
365 | }; | |
366 | #define OPREGION_SIZE (8*1024) | |
367 | ||
368 | struct intel_overlay; | |
369 | struct intel_overlay_error_state; | |
370 | ||
371 | #define I915_FENCE_REG_NONE -1 | |
372 | #define I915_MAX_NUM_FENCES 32 | |
373 | /* 32 fences + sign bit for FENCE_REG_NONE */ | |
374 | #define I915_MAX_NUM_FENCE_BITS 6 | |
375 | ||
376 | struct drm_i915_fence_reg { | |
377 | struct list_head lru_list; | |
378 | struct drm_i915_gem_object *obj; | |
379 | int pin_count; | |
380 | }; | |
381 | ||
382 | struct sdvo_device_mapping { | |
383 | u8 initialized; | |
384 | u8 dvo_port; | |
385 | u8 slave_addr; | |
386 | u8 dvo_wiring; | |
387 | u8 i2c_pin; | |
388 | u8 ddc_pin; | |
389 | }; | |
390 | ||
391 | struct intel_display_error_state; | |
392 | ||
393 | struct drm_i915_error_state { | |
394 | struct kref ref; | |
395 | struct timeval time; | |
396 | ||
397 | char error_msg[128]; | |
398 | u32 reset_count; | |
399 | u32 suspend_count; | |
400 | ||
401 | /* Generic register state */ | |
402 | u32 eir; | |
403 | u32 pgtbl_er; | |
404 | u32 ier; | |
405 | u32 gtier[4]; | |
406 | u32 ccid; | |
407 | u32 derrmr; | |
408 | u32 forcewake; | |
409 | u32 error; /* gen6+ */ | |
410 | u32 err_int; /* gen7 */ | |
411 | u32 done_reg; | |
412 | u32 gac_eco; | |
413 | u32 gam_ecochk; | |
414 | u32 gab_ctl; | |
415 | u32 gfx_mode; | |
416 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; | |
417 | u64 fence[I915_MAX_NUM_FENCES]; | |
418 | struct intel_overlay_error_state *overlay; | |
419 | struct intel_display_error_state *display; | |
420 | struct drm_i915_error_object *semaphore_obj; | |
421 | ||
422 | struct drm_i915_error_ring { | |
423 | bool valid; | |
424 | /* Software tracked state */ | |
425 | bool waiting; | |
426 | int hangcheck_score; | |
427 | enum intel_ring_hangcheck_action hangcheck_action; | |
428 | int num_requests; | |
429 | ||
430 | /* our own tracking of ring head and tail */ | |
431 | u32 cpu_ring_head; | |
432 | u32 cpu_ring_tail; | |
433 | ||
434 | u32 semaphore_seqno[I915_NUM_RINGS - 1]; | |
435 | ||
436 | /* Register state */ | |
437 | u32 tail; | |
438 | u32 head; | |
439 | u32 ctl; | |
440 | u32 hws; | |
441 | u32 ipeir; | |
442 | u32 ipehr; | |
443 | u32 instdone; | |
444 | u32 bbstate; | |
445 | u32 instpm; | |
446 | u32 instps; | |
447 | u32 seqno; | |
448 | u64 bbaddr; | |
449 | u64 acthd; | |
450 | u32 fault_reg; | |
451 | u64 faddr; | |
452 | u32 rc_psmi; /* sleep state */ | |
453 | u32 semaphore_mboxes[I915_NUM_RINGS - 1]; | |
454 | ||
455 | struct drm_i915_error_object { | |
456 | int page_count; | |
457 | u32 gtt_offset; | |
458 | u32 *pages[0]; | |
459 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; | |
460 | ||
461 | struct drm_i915_error_request { | |
462 | long jiffies; | |
463 | u32 seqno; | |
464 | u32 tail; | |
465 | } *requests; | |
466 | ||
467 | struct { | |
468 | u32 gfx_mode; | |
469 | union { | |
470 | u64 pdp[4]; | |
471 | u32 pp_dir_base; | |
472 | }; | |
473 | } vm_info; | |
474 | ||
475 | pid_t pid; | |
476 | char comm[TASK_COMM_LEN]; | |
477 | } ring[I915_NUM_RINGS]; | |
478 | ||
479 | struct drm_i915_error_buffer { | |
480 | u32 size; | |
481 | u32 name; | |
482 | u32 rseqno, wseqno; | |
483 | u32 gtt_offset; | |
484 | u32 read_domains; | |
485 | u32 write_domain; | |
486 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; | |
487 | s32 pinned:2; | |
488 | u32 tiling:2; | |
489 | u32 dirty:1; | |
490 | u32 purgeable:1; | |
491 | u32 userptr:1; | |
492 | s32 ring:4; | |
493 | u32 cache_level:3; | |
494 | } **active_bo, **pinned_bo; | |
495 | ||
496 | u32 *active_bo_count, *pinned_bo_count; | |
497 | u32 vm_count; | |
498 | }; | |
499 | ||
500 | struct intel_connector; | |
501 | struct intel_encoder; | |
502 | struct intel_crtc_state; | |
503 | struct intel_plane_config; | |
504 | struct intel_crtc; | |
505 | struct intel_limit; | |
506 | struct dpll; | |
507 | ||
508 | struct drm_i915_display_funcs { | |
509 | bool (*fbc_enabled)(struct drm_device *dev); | |
510 | void (*enable_fbc)(struct drm_crtc *crtc); | |
511 | void (*disable_fbc)(struct drm_device *dev); | |
512 | int (*get_display_clock_speed)(struct drm_device *dev); | |
513 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
514 | /** | |
515 | * find_dpll() - Find the best values for the PLL | |
516 | * @limit: limits for the PLL | |
517 | * @crtc: current CRTC | |
518 | * @target: target frequency in kHz | |
519 | * @refclk: reference clock frequency in kHz | |
520 | * @match_clock: if provided, @best_clock P divider must | |
521 | * match the P divider from @match_clock | |
522 | * used for LVDS downclocking | |
523 | * @best_clock: best PLL values found | |
524 | * | |
525 | * Returns true on success, false on failure. | |
526 | */ | |
527 | bool (*find_dpll)(const struct intel_limit *limit, | |
528 | struct intel_crtc *crtc, | |
529 | int target, int refclk, | |
530 | struct dpll *match_clock, | |
531 | struct dpll *best_clock); | |
532 | void (*update_wm)(struct drm_crtc *crtc); | |
533 | void (*update_sprite_wm)(struct drm_plane *plane, | |
534 | struct drm_crtc *crtc, | |
535 | uint32_t sprite_width, uint32_t sprite_height, | |
536 | int pixel_size, bool enable, bool scaled); | |
537 | void (*modeset_global_resources)(struct drm_device *dev); | |
538 | /* Returns the active state of the crtc, and if the crtc is active, | |
539 | * fills out the pipe-config with the hw state. */ | |
540 | bool (*get_pipe_config)(struct intel_crtc *, | |
541 | struct intel_crtc_state *); | |
542 | void (*get_plane_config)(struct intel_crtc *, | |
543 | struct intel_plane_config *); | |
544 | int (*crtc_compute_clock)(struct intel_crtc *crtc, | |
545 | struct intel_crtc_state *crtc_state); | |
546 | void (*crtc_enable)(struct drm_crtc *crtc); | |
547 | void (*crtc_disable)(struct drm_crtc *crtc); | |
548 | void (*off)(struct drm_crtc *crtc); | |
549 | void (*audio_codec_enable)(struct drm_connector *connector, | |
550 | struct intel_encoder *encoder, | |
551 | struct drm_display_mode *mode); | |
552 | void (*audio_codec_disable)(struct intel_encoder *encoder); | |
553 | void (*fdi_link_train)(struct drm_crtc *crtc); | |
554 | void (*init_clock_gating)(struct drm_device *dev); | |
555 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, | |
556 | struct drm_framebuffer *fb, | |
557 | struct drm_i915_gem_object *obj, | |
558 | struct intel_engine_cs *ring, | |
559 | uint32_t flags); | |
560 | void (*update_primary_plane)(struct drm_crtc *crtc, | |
561 | struct drm_framebuffer *fb, | |
562 | int x, int y); | |
563 | void (*hpd_irq_setup)(struct drm_device *dev); | |
564 | /* clock updates for mode set */ | |
565 | /* cursor updates */ | |
566 | /* render clock increase/decrease */ | |
567 | /* display clock increase/decrease */ | |
568 | /* pll clock increase/decrease */ | |
569 | ||
570 | int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe); | |
571 | uint32_t (*get_backlight)(struct intel_connector *connector); | |
572 | void (*set_backlight)(struct intel_connector *connector, | |
573 | uint32_t level); | |
574 | void (*disable_backlight)(struct intel_connector *connector); | |
575 | void (*enable_backlight)(struct intel_connector *connector); | |
576 | }; | |
577 | ||
578 | struct intel_uncore_funcs { | |
579 | void (*force_wake_get)(struct drm_i915_private *dev_priv, | |
580 | int fw_engine); | |
581 | void (*force_wake_put)(struct drm_i915_private *dev_priv, | |
582 | int fw_engine); | |
583 | ||
584 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
585 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
586 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
587 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
588 | ||
589 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, | |
590 | uint8_t val, bool trace); | |
591 | void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, | |
592 | uint16_t val, bool trace); | |
593 | void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, | |
594 | uint32_t val, bool trace); | |
595 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, | |
596 | uint64_t val, bool trace); | |
597 | }; | |
598 | ||
599 | enum { | |
600 | FW_DOMAIN_ID_RENDER = 0, | |
601 | FW_DOMAIN_ID_BLITTER, | |
602 | FW_DOMAIN_ID_MEDIA, | |
603 | ||
604 | FW_DOMAIN_ID_COUNT | |
605 | }; | |
606 | ||
607 | struct intel_uncore { | |
608 | spinlock_t lock; /** lock is also taken in irq contexts. */ | |
609 | ||
610 | struct intel_uncore_funcs funcs; | |
611 | ||
612 | unsigned fifo_count; | |
613 | unsigned fw_domains; | |
614 | ||
615 | struct intel_uncore_forcewake_domain { | |
616 | struct drm_i915_private *i915; | |
617 | int id; | |
618 | unsigned wake_count; | |
619 | struct timer_list timer; | |
620 | u32 reg_set; | |
621 | u32 val_set; | |
622 | u32 val_clear; | |
623 | u32 reg_ack; | |
624 | u32 reg_post; | |
625 | u32 val_reset; | |
626 | } fw_domain[FW_DOMAIN_ID_COUNT]; | |
627 | #define FORCEWAKE_RENDER (1 << FW_DOMAIN_ID_RENDER) | |
628 | #define FORCEWAKE_BLITTER (1 << FW_DOMAIN_ID_BLITTER) | |
629 | #define FORCEWAKE_MEDIA (1 << FW_DOMAIN_ID_MEDIA) | |
630 | #define FORCEWAKE_ALL (FORCEWAKE_RENDER | \ | |
631 | FORCEWAKE_BLITTER | \ | |
632 | FORCEWAKE_MEDIA) | |
633 | }; | |
634 | ||
635 | /* Iterate over initialised fw domains */ | |
636 | #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \ | |
637 | for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \ | |
638 | (i__) < FW_DOMAIN_ID_COUNT; \ | |
639 | (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \ | |
640 | if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__))) | |
641 | ||
642 | #define for_each_fw_domain(domain__, dev_priv__, i__) \ | |
643 | for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__) | |
644 | ||
645 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ | |
646 | func(is_mobile) sep \ | |
647 | func(is_i85x) sep \ | |
648 | func(is_i915g) sep \ | |
649 | func(is_i945gm) sep \ | |
650 | func(is_g33) sep \ | |
651 | func(need_gfx_hws) sep \ | |
652 | func(is_g4x) sep \ | |
653 | func(is_pineview) sep \ | |
654 | func(is_broadwater) sep \ | |
655 | func(is_crestline) sep \ | |
656 | func(is_ivybridge) sep \ | |
657 | func(is_valleyview) sep \ | |
658 | func(is_haswell) sep \ | |
659 | func(is_skylake) sep \ | |
660 | func(is_preliminary) sep \ | |
661 | func(has_fbc) sep \ | |
662 | func(has_pipe_cxsr) sep \ | |
663 | func(has_hotplug) sep \ | |
664 | func(cursor_needs_physical) sep \ | |
665 | func(has_overlay) sep \ | |
666 | func(overlay_needs_physical) sep \ | |
667 | func(supports_tv) sep \ | |
668 | func(has_llc) sep \ | |
669 | func(has_ddi) sep \ | |
670 | func(has_fpga_dbg) | |
671 | ||
672 | #define DEFINE_FLAG(name) u8 name:1 | |
673 | #define SEP_SEMICOLON ; | |
674 | ||
675 | struct intel_device_info { | |
676 | u32 display_mmio_offset; | |
677 | u16 device_id; | |
678 | u8 num_pipes:3; | |
679 | u8 num_sprites[I915_MAX_PIPES]; | |
680 | u8 gen; | |
681 | u8 ring_mask; /* Rings supported by the HW */ | |
682 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); | |
683 | /* Register offsets for the various display pipes and transcoders */ | |
684 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
685 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
686 | int palette_offsets[I915_MAX_PIPES]; | |
687 | int cursor_offsets[I915_MAX_PIPES]; | |
688 | unsigned int eu_total; | |
689 | }; | |
690 | ||
691 | #undef DEFINE_FLAG | |
692 | #undef SEP_SEMICOLON | |
693 | ||
694 | enum i915_cache_level { | |
695 | I915_CACHE_NONE = 0, | |
696 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ | |
697 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
698 | caches, eg sampler/render caches, and the | |
699 | large Last-Level-Cache. LLC is coherent with | |
700 | the CPU, but L3 is only visible to the GPU. */ | |
701 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ | |
702 | }; | |
703 | ||
704 | struct i915_ctx_hang_stats { | |
705 | /* This context had batch pending when hang was declared */ | |
706 | unsigned batch_pending; | |
707 | ||
708 | /* This context had batch active when hang was declared */ | |
709 | unsigned batch_active; | |
710 | ||
711 | /* Time when this context was last blamed for a GPU reset */ | |
712 | unsigned long guilty_ts; | |
713 | ||
714 | /* If the contexts causes a second GPU hang within this time, | |
715 | * it is permanently banned from submitting any more work. | |
716 | */ | |
717 | unsigned long ban_period_seconds; | |
718 | ||
719 | /* This context is banned to submit more work */ | |
720 | bool banned; | |
721 | }; | |
722 | ||
723 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
724 | #define DEFAULT_CONTEXT_HANDLE 0 | |
725 | /** | |
726 | * struct intel_context - as the name implies, represents a context. | |
727 | * @ref: reference count. | |
728 | * @user_handle: userspace tracking identity for this context. | |
729 | * @remap_slice: l3 row remapping information. | |
730 | * @file_priv: filp associated with this context (NULL for global default | |
731 | * context). | |
732 | * @hang_stats: information about the role of this context in possible GPU | |
733 | * hangs. | |
734 | * @vm: virtual memory space used by this context. | |
735 | * @legacy_hw_ctx: render context backing object and whether it is correctly | |
736 | * initialized (legacy ring submission mechanism only). | |
737 | * @link: link in the global list of contexts. | |
738 | * | |
739 | * Contexts are memory images used by the hardware to store copies of their | |
740 | * internal state. | |
741 | */ | |
742 | struct intel_context { | |
743 | struct kref ref; | |
744 | int user_handle; | |
745 | uint8_t remap_slice; | |
746 | struct drm_i915_file_private *file_priv; | |
747 | struct i915_ctx_hang_stats hang_stats; | |
748 | struct i915_hw_ppgtt *ppgtt; | |
749 | ||
750 | /* Legacy ring buffer submission */ | |
751 | struct { | |
752 | struct drm_i915_gem_object *rcs_state; | |
753 | bool initialized; | |
754 | } legacy_hw_ctx; | |
755 | ||
756 | /* Execlists */ | |
757 | bool rcs_initialized; | |
758 | struct { | |
759 | struct drm_i915_gem_object *state; | |
760 | struct intel_ringbuffer *ringbuf; | |
761 | int unpin_count; | |
762 | } engine[I915_NUM_RINGS]; | |
763 | ||
764 | struct list_head link; | |
765 | }; | |
766 | ||
767 | struct i915_fbc { | |
768 | unsigned long size; | |
769 | unsigned threshold; | |
770 | unsigned int fb_id; | |
771 | enum plane plane; | |
772 | int y; | |
773 | ||
774 | struct drm_mm_node compressed_fb; | |
775 | struct drm_mm_node *compressed_llb; | |
776 | ||
777 | bool false_color; | |
778 | ||
779 | /* Tracks whether the HW is actually enabled, not whether the feature is | |
780 | * possible. */ | |
781 | bool enabled; | |
782 | ||
783 | /* On gen8 some rings cannont perform fbc clean operation so for now | |
784 | * we are doing this on SW with mmio. | |
785 | * This variable works in the opposite information direction | |
786 | * of ring->fbc_dirty telling software on frontbuffer tracking | |
787 | * to perform the cache clean on sw side. | |
788 | */ | |
789 | bool need_sw_cache_clean; | |
790 | ||
791 | struct intel_fbc_work { | |
792 | struct delayed_work work; | |
793 | struct drm_crtc *crtc; | |
794 | struct drm_framebuffer *fb; | |
795 | } *fbc_work; | |
796 | ||
797 | enum no_fbc_reason { | |
798 | FBC_OK, /* FBC is enabled */ | |
799 | FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ | |
800 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ | |
801 | FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ | |
802 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
803 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
804 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
805 | FBC_NOT_TILED, /* buffer not tiled */ | |
806 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ | |
807 | FBC_MODULE_PARAM, | |
808 | FBC_CHIP_DEFAULT, /* disabled by default on this chip */ | |
809 | } no_fbc_reason; | |
810 | }; | |
811 | ||
812 | /** | |
813 | * HIGH_RR is the highest eDP panel refresh rate read from EDID | |
814 | * LOW_RR is the lowest eDP panel refresh rate found from EDID | |
815 | * parsing for same resolution. | |
816 | */ | |
817 | enum drrs_refresh_rate_type { | |
818 | DRRS_HIGH_RR, | |
819 | DRRS_LOW_RR, | |
820 | DRRS_MAX_RR, /* RR count */ | |
821 | }; | |
822 | ||
823 | enum drrs_support_type { | |
824 | DRRS_NOT_SUPPORTED = 0, | |
825 | STATIC_DRRS_SUPPORT = 1, | |
826 | SEAMLESS_DRRS_SUPPORT = 2 | |
827 | }; | |
828 | ||
829 | struct intel_dp; | |
830 | struct i915_drrs { | |
831 | struct mutex mutex; | |
832 | struct delayed_work work; | |
833 | struct intel_dp *dp; | |
834 | unsigned busy_frontbuffer_bits; | |
835 | enum drrs_refresh_rate_type refresh_rate_type; | |
836 | enum drrs_support_type type; | |
837 | }; | |
838 | ||
839 | struct i915_psr { | |
840 | struct mutex lock; | |
841 | bool sink_support; | |
842 | bool source_ok; | |
843 | struct intel_dp *enabled; | |
844 | bool active; | |
845 | struct delayed_work work; | |
846 | unsigned busy_frontbuffer_bits; | |
847 | bool link_standby; | |
848 | }; | |
849 | ||
850 | enum intel_pch { | |
851 | PCH_NONE = 0, /* No PCH present */ | |
852 | PCH_IBX, /* Ibexpeak PCH */ | |
853 | PCH_CPT, /* Cougarpoint PCH */ | |
854 | PCH_LPT, /* Lynxpoint PCH */ | |
855 | PCH_SPT, /* Sunrisepoint PCH */ | |
856 | PCH_NOP, | |
857 | }; | |
858 | ||
859 | enum intel_sbi_destination { | |
860 | SBI_ICLK, | |
861 | SBI_MPHY, | |
862 | }; | |
863 | ||
864 | #define QUIRK_PIPEA_FORCE (1<<0) | |
865 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) | |
866 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) | |
867 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) | |
868 | #define QUIRK_PIPEB_FORCE (1<<4) | |
869 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) | |
870 | ||
871 | struct intel_fbdev; | |
872 | struct intel_fbc_work; | |
873 | ||
874 | struct intel_gmbus { | |
875 | struct i2c_adapter adapter; | |
876 | u32 force_bit; | |
877 | u32 reg0; | |
878 | u32 gpio_reg; | |
879 | struct i2c_algo_bit_data bit_algo; | |
880 | struct drm_i915_private *dev_priv; | |
881 | }; | |
882 | ||
883 | struct i915_suspend_saved_registers { | |
884 | u8 saveLBB; | |
885 | u32 saveDSPACNTR; | |
886 | u32 saveDSPBCNTR; | |
887 | u32 saveDSPARB; | |
888 | u32 savePIPEACONF; | |
889 | u32 savePIPEBCONF; | |
890 | u32 savePIPEASRC; | |
891 | u32 savePIPEBSRC; | |
892 | u32 saveFPA0; | |
893 | u32 saveFPA1; | |
894 | u32 saveDPLL_A; | |
895 | u32 saveDPLL_A_MD; | |
896 | u32 saveHTOTAL_A; | |
897 | u32 saveHBLANK_A; | |
898 | u32 saveHSYNC_A; | |
899 | u32 saveVTOTAL_A; | |
900 | u32 saveVBLANK_A; | |
901 | u32 saveVSYNC_A; | |
902 | u32 saveBCLRPAT_A; | |
903 | u32 saveTRANSACONF; | |
904 | u32 saveTRANS_HTOTAL_A; | |
905 | u32 saveTRANS_HBLANK_A; | |
906 | u32 saveTRANS_HSYNC_A; | |
907 | u32 saveTRANS_VTOTAL_A; | |
908 | u32 saveTRANS_VBLANK_A; | |
909 | u32 saveTRANS_VSYNC_A; | |
910 | u32 savePIPEASTAT; | |
911 | u32 saveDSPASTRIDE; | |
912 | u32 saveDSPASIZE; | |
913 | u32 saveDSPAPOS; | |
914 | u32 saveDSPAADDR; | |
915 | u32 saveDSPASURF; | |
916 | u32 saveDSPATILEOFF; | |
917 | u32 savePFIT_PGM_RATIOS; | |
918 | u32 saveBLC_HIST_CTL; | |
919 | u32 saveBLC_PWM_CTL; | |
920 | u32 saveBLC_PWM_CTL2; | |
921 | u32 saveBLC_CPU_PWM_CTL; | |
922 | u32 saveBLC_CPU_PWM_CTL2; | |
923 | u32 saveFPB0; | |
924 | u32 saveFPB1; | |
925 | u32 saveDPLL_B; | |
926 | u32 saveDPLL_B_MD; | |
927 | u32 saveHTOTAL_B; | |
928 | u32 saveHBLANK_B; | |
929 | u32 saveHSYNC_B; | |
930 | u32 saveVTOTAL_B; | |
931 | u32 saveVBLANK_B; | |
932 | u32 saveVSYNC_B; | |
933 | u32 saveBCLRPAT_B; | |
934 | u32 saveTRANSBCONF; | |
935 | u32 saveTRANS_HTOTAL_B; | |
936 | u32 saveTRANS_HBLANK_B; | |
937 | u32 saveTRANS_HSYNC_B; | |
938 | u32 saveTRANS_VTOTAL_B; | |
939 | u32 saveTRANS_VBLANK_B; | |
940 | u32 saveTRANS_VSYNC_B; | |
941 | u32 savePIPEBSTAT; | |
942 | u32 saveDSPBSTRIDE; | |
943 | u32 saveDSPBSIZE; | |
944 | u32 saveDSPBPOS; | |
945 | u32 saveDSPBADDR; | |
946 | u32 saveDSPBSURF; | |
947 | u32 saveDSPBTILEOFF; | |
948 | u32 saveVGA0; | |
949 | u32 saveVGA1; | |
950 | u32 saveVGA_PD; | |
951 | u32 saveVGACNTRL; | |
952 | u32 saveADPA; | |
953 | u32 saveLVDS; | |
954 | u32 savePP_ON_DELAYS; | |
955 | u32 savePP_OFF_DELAYS; | |
956 | u32 saveDVOA; | |
957 | u32 saveDVOB; | |
958 | u32 saveDVOC; | |
959 | u32 savePP_ON; | |
960 | u32 savePP_OFF; | |
961 | u32 savePP_CONTROL; | |
962 | u32 savePP_DIVISOR; | |
963 | u32 savePFIT_CONTROL; | |
964 | u32 save_palette_a[256]; | |
965 | u32 save_palette_b[256]; | |
966 | u32 saveFBC_CONTROL; | |
967 | u32 saveIER; | |
968 | u32 saveIIR; | |
969 | u32 saveIMR; | |
970 | u32 saveDEIER; | |
971 | u32 saveDEIMR; | |
972 | u32 saveGTIER; | |
973 | u32 saveGTIMR; | |
974 | u32 saveFDI_RXA_IMR; | |
975 | u32 saveFDI_RXB_IMR; | |
976 | u32 saveCACHE_MODE_0; | |
977 | u32 saveMI_ARB_STATE; | |
978 | u32 saveSWF0[16]; | |
979 | u32 saveSWF1[16]; | |
980 | u32 saveSWF2[3]; | |
981 | u8 saveMSR; | |
982 | u8 saveSR[8]; | |
983 | u8 saveGR[25]; | |
984 | u8 saveAR_INDEX; | |
985 | u8 saveAR[21]; | |
986 | u8 saveDACMASK; | |
987 | u8 saveCR[37]; | |
988 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; | |
989 | u32 saveCURACNTR; | |
990 | u32 saveCURAPOS; | |
991 | u32 saveCURABASE; | |
992 | u32 saveCURBCNTR; | |
993 | u32 saveCURBPOS; | |
994 | u32 saveCURBBASE; | |
995 | u32 saveCURSIZE; | |
996 | u32 saveDP_B; | |
997 | u32 saveDP_C; | |
998 | u32 saveDP_D; | |
999 | u32 savePIPEA_GMCH_DATA_M; | |
1000 | u32 savePIPEB_GMCH_DATA_M; | |
1001 | u32 savePIPEA_GMCH_DATA_N; | |
1002 | u32 savePIPEB_GMCH_DATA_N; | |
1003 | u32 savePIPEA_DP_LINK_M; | |
1004 | u32 savePIPEB_DP_LINK_M; | |
1005 | u32 savePIPEA_DP_LINK_N; | |
1006 | u32 savePIPEB_DP_LINK_N; | |
1007 | u32 saveFDI_RXA_CTL; | |
1008 | u32 saveFDI_TXA_CTL; | |
1009 | u32 saveFDI_RXB_CTL; | |
1010 | u32 saveFDI_TXB_CTL; | |
1011 | u32 savePFA_CTL_1; | |
1012 | u32 savePFB_CTL_1; | |
1013 | u32 savePFA_WIN_SZ; | |
1014 | u32 savePFB_WIN_SZ; | |
1015 | u32 savePFA_WIN_POS; | |
1016 | u32 savePFB_WIN_POS; | |
1017 | u32 savePCH_DREF_CONTROL; | |
1018 | u32 saveDISP_ARB_CTL; | |
1019 | u32 savePIPEA_DATA_M1; | |
1020 | u32 savePIPEA_DATA_N1; | |
1021 | u32 savePIPEA_LINK_M1; | |
1022 | u32 savePIPEA_LINK_N1; | |
1023 | u32 savePIPEB_DATA_M1; | |
1024 | u32 savePIPEB_DATA_N1; | |
1025 | u32 savePIPEB_LINK_M1; | |
1026 | u32 savePIPEB_LINK_N1; | |
1027 | u32 saveMCHBAR_RENDER_STANDBY; | |
1028 | u32 savePCH_PORT_HOTPLUG; | |
1029 | u16 saveGCDGMBUS; | |
1030 | }; | |
1031 | ||
1032 | struct vlv_s0ix_state { | |
1033 | /* GAM */ | |
1034 | u32 wr_watermark; | |
1035 | u32 gfx_prio_ctrl; | |
1036 | u32 arb_mode; | |
1037 | u32 gfx_pend_tlb0; | |
1038 | u32 gfx_pend_tlb1; | |
1039 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; | |
1040 | u32 media_max_req_count; | |
1041 | u32 gfx_max_req_count; | |
1042 | u32 render_hwsp; | |
1043 | u32 ecochk; | |
1044 | u32 bsd_hwsp; | |
1045 | u32 blt_hwsp; | |
1046 | u32 tlb_rd_addr; | |
1047 | ||
1048 | /* MBC */ | |
1049 | u32 g3dctl; | |
1050 | u32 gsckgctl; | |
1051 | u32 mbctl; | |
1052 | ||
1053 | /* GCP */ | |
1054 | u32 ucgctl1; | |
1055 | u32 ucgctl3; | |
1056 | u32 rcgctl1; | |
1057 | u32 rcgctl2; | |
1058 | u32 rstctl; | |
1059 | u32 misccpctl; | |
1060 | ||
1061 | /* GPM */ | |
1062 | u32 gfxpause; | |
1063 | u32 rpdeuhwtc; | |
1064 | u32 rpdeuc; | |
1065 | u32 ecobus; | |
1066 | u32 pwrdwnupctl; | |
1067 | u32 rp_down_timeout; | |
1068 | u32 rp_deucsw; | |
1069 | u32 rcubmabdtmr; | |
1070 | u32 rcedata; | |
1071 | u32 spare2gh; | |
1072 | ||
1073 | /* Display 1 CZ domain */ | |
1074 | u32 gt_imr; | |
1075 | u32 gt_ier; | |
1076 | u32 pm_imr; | |
1077 | u32 pm_ier; | |
1078 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; | |
1079 | ||
1080 | /* GT SA CZ domain */ | |
1081 | u32 tilectl; | |
1082 | u32 gt_fifoctl; | |
1083 | u32 gtlc_wake_ctrl; | |
1084 | u32 gtlc_survive; | |
1085 | u32 pmwgicz; | |
1086 | ||
1087 | /* Display 2 CZ domain */ | |
1088 | u32 gu_ctl0; | |
1089 | u32 gu_ctl1; | |
1090 | u32 clock_gate_dis2; | |
1091 | }; | |
1092 | ||
1093 | struct intel_rps_ei { | |
1094 | u32 cz_clock; | |
1095 | u32 render_c0; | |
1096 | u32 media_c0; | |
1097 | }; | |
1098 | ||
1099 | struct intel_gen6_power_mgmt { | |
1100 | /* | |
1101 | * work, interrupts_enabled and pm_iir are protected by | |
1102 | * dev_priv->irq_lock | |
1103 | */ | |
1104 | struct work_struct work; | |
1105 | bool interrupts_enabled; | |
1106 | u32 pm_iir; | |
1107 | ||
1108 | /* Frequencies are stored in potentially platform dependent multiples. | |
1109 | * In other words, *_freq needs to be multiplied by X to be interesting. | |
1110 | * Soft limits are those which are used for the dynamic reclocking done | |
1111 | * by the driver (raise frequencies under heavy loads, and lower for | |
1112 | * lighter loads). Hard limits are those imposed by the hardware. | |
1113 | * | |
1114 | * A distinction is made for overclocking, which is never enabled by | |
1115 | * default, and is considered to be above the hard limit if it's | |
1116 | * possible at all. | |
1117 | */ | |
1118 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ | |
1119 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ | |
1120 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ | |
1121 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ | |
1122 | u8 min_freq; /* AKA RPn. Minimum frequency */ | |
1123 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ | |
1124 | u8 rp1_freq; /* "less than" RP0 power/freqency */ | |
1125 | u8 rp0_freq; /* Non-overclocked max frequency. */ | |
1126 | u32 cz_freq; | |
1127 | ||
1128 | u32 ei_interrupt_count; | |
1129 | ||
1130 | int last_adj; | |
1131 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; | |
1132 | ||
1133 | bool enabled; | |
1134 | struct delayed_work delayed_resume_work; | |
1135 | ||
1136 | /* manual wa residency calculations */ | |
1137 | struct intel_rps_ei up_ei, down_ei; | |
1138 | ||
1139 | /* | |
1140 | * Protects RPS/RC6 register access and PCU communication. | |
1141 | * Must be taken after struct_mutex if nested. | |
1142 | */ | |
1143 | struct mutex hw_lock; | |
1144 | }; | |
1145 | ||
1146 | /* defined intel_pm.c */ | |
1147 | extern spinlock_t mchdev_lock; | |
1148 | ||
1149 | struct intel_ilk_power_mgmt { | |
1150 | u8 cur_delay; | |
1151 | u8 min_delay; | |
1152 | u8 max_delay; | |
1153 | u8 fmax; | |
1154 | u8 fstart; | |
1155 | ||
1156 | u64 last_count1; | |
1157 | unsigned long last_time1; | |
1158 | unsigned long chipset_power; | |
1159 | u64 last_count2; | |
1160 | u64 last_time2; | |
1161 | unsigned long gfx_power; | |
1162 | u8 corr; | |
1163 | ||
1164 | int c_m; | |
1165 | int r_t; | |
1166 | ||
1167 | struct drm_i915_gem_object *pwrctx; | |
1168 | struct drm_i915_gem_object *renderctx; | |
1169 | }; | |
1170 | ||
1171 | struct drm_i915_private; | |
1172 | struct i915_power_well; | |
1173 | ||
1174 | struct i915_power_well_ops { | |
1175 | /* | |
1176 | * Synchronize the well's hw state to match the current sw state, for | |
1177 | * example enable/disable it based on the current refcount. Called | |
1178 | * during driver init and resume time, possibly after first calling | |
1179 | * the enable/disable handlers. | |
1180 | */ | |
1181 | void (*sync_hw)(struct drm_i915_private *dev_priv, | |
1182 | struct i915_power_well *power_well); | |
1183 | /* | |
1184 | * Enable the well and resources that depend on it (for example | |
1185 | * interrupts located on the well). Called after the 0->1 refcount | |
1186 | * transition. | |
1187 | */ | |
1188 | void (*enable)(struct drm_i915_private *dev_priv, | |
1189 | struct i915_power_well *power_well); | |
1190 | /* | |
1191 | * Disable the well and resources that depend on it. Called after | |
1192 | * the 1->0 refcount transition. | |
1193 | */ | |
1194 | void (*disable)(struct drm_i915_private *dev_priv, | |
1195 | struct i915_power_well *power_well); | |
1196 | /* Returns the hw enabled state. */ | |
1197 | bool (*is_enabled)(struct drm_i915_private *dev_priv, | |
1198 | struct i915_power_well *power_well); | |
1199 | }; | |
1200 | ||
1201 | /* Power well structure for haswell */ | |
1202 | struct i915_power_well { | |
1203 | const char *name; | |
1204 | bool always_on; | |
1205 | /* power well enable/disable usage count */ | |
1206 | int count; | |
1207 | /* cached hw enabled state */ | |
1208 | bool hw_enabled; | |
1209 | unsigned long domains; | |
1210 | unsigned long data; | |
1211 | const struct i915_power_well_ops *ops; | |
1212 | }; | |
1213 | ||
1214 | struct i915_power_domains { | |
1215 | /* | |
1216 | * Power wells needed for initialization at driver init and suspend | |
1217 | * time are on. They are kept on until after the first modeset. | |
1218 | */ | |
1219 | bool init_power_on; | |
1220 | bool initializing; | |
1221 | int power_well_count; | |
1222 | ||
1223 | struct mutex lock; | |
1224 | int domain_use_count[POWER_DOMAIN_NUM]; | |
1225 | struct i915_power_well *power_wells; | |
1226 | }; | |
1227 | ||
1228 | #define MAX_L3_SLICES 2 | |
1229 | struct intel_l3_parity { | |
1230 | u32 *remap_info[MAX_L3_SLICES]; | |
1231 | struct work_struct error_work; | |
1232 | int which_slice; | |
1233 | }; | |
1234 | ||
1235 | struct i915_gem_batch_pool { | |
1236 | struct drm_device *dev; | |
1237 | struct list_head cache_list; | |
1238 | }; | |
1239 | ||
1240 | struct i915_gem_mm { | |
1241 | /** Memory allocator for GTT stolen memory */ | |
1242 | struct drm_mm stolen; | |
1243 | /** List of all objects in gtt_space. Used to restore gtt | |
1244 | * mappings on resume */ | |
1245 | struct list_head bound_list; | |
1246 | /** | |
1247 | * List of objects which are not bound to the GTT (thus | |
1248 | * are idle and not used by the GPU) but still have | |
1249 | * (presumably uncached) pages still attached. | |
1250 | */ | |
1251 | struct list_head unbound_list; | |
1252 | ||
1253 | /* | |
1254 | * A pool of objects to use as shadow copies of client batch buffers | |
1255 | * when the command parser is enabled. Prevents the client from | |
1256 | * modifying the batch contents after software parsing. | |
1257 | */ | |
1258 | struct i915_gem_batch_pool batch_pool; | |
1259 | ||
1260 | /** Usable portion of the GTT for GEM */ | |
1261 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
1262 | ||
1263 | /** PPGTT used for aliasing the PPGTT with the GTT */ | |
1264 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
1265 | ||
1266 | struct notifier_block oom_notifier; | |
1267 | struct shrinker shrinker; | |
1268 | bool shrinker_no_lock_stealing; | |
1269 | ||
1270 | /** LRU list of objects with fence regs on them. */ | |
1271 | struct list_head fence_list; | |
1272 | ||
1273 | /** | |
1274 | * We leave the user IRQ off as much as possible, | |
1275 | * but this means that requests will finish and never | |
1276 | * be retired once the system goes idle. Set a timer to | |
1277 | * fire periodically while the ring is running. When it | |
1278 | * fires, go retire requests. | |
1279 | */ | |
1280 | struct delayed_work retire_work; | |
1281 | ||
1282 | /** | |
1283 | * When we detect an idle GPU, we want to turn on | |
1284 | * powersaving features. So once we see that there | |
1285 | * are no more requests outstanding and no more | |
1286 | * arrive within a small period of time, we fire | |
1287 | * off the idle_work. | |
1288 | */ | |
1289 | struct delayed_work idle_work; | |
1290 | ||
1291 | /** | |
1292 | * Are we in a non-interruptible section of code like | |
1293 | * modesetting? | |
1294 | */ | |
1295 | bool interruptible; | |
1296 | ||
1297 | /** | |
1298 | * Is the GPU currently considered idle, or busy executing userspace | |
1299 | * requests? Whilst idle, we attempt to power down the hardware and | |
1300 | * display clocks. In order to reduce the effect on performance, there | |
1301 | * is a slight delay before we do so. | |
1302 | */ | |
1303 | bool busy; | |
1304 | ||
1305 | /* the indicator for dispatch video commands on two BSD rings */ | |
1306 | int bsd_ring_dispatch_index; | |
1307 | ||
1308 | /** Bit 6 swizzling required for X tiling */ | |
1309 | uint32_t bit_6_swizzle_x; | |
1310 | /** Bit 6 swizzling required for Y tiling */ | |
1311 | uint32_t bit_6_swizzle_y; | |
1312 | ||
1313 | /* accounting, useful for userland debugging */ | |
1314 | spinlock_t object_stat_lock; | |
1315 | size_t object_memory; | |
1316 | u32 object_count; | |
1317 | }; | |
1318 | ||
1319 | struct drm_i915_error_state_buf { | |
1320 | struct drm_i915_private *i915; | |
1321 | unsigned bytes; | |
1322 | unsigned size; | |
1323 | int err; | |
1324 | u8 *buf; | |
1325 | loff_t start; | |
1326 | loff_t pos; | |
1327 | }; | |
1328 | ||
1329 | struct i915_error_state_file_priv { | |
1330 | struct drm_device *dev; | |
1331 | struct drm_i915_error_state *error; | |
1332 | }; | |
1333 | ||
1334 | struct i915_gpu_error { | |
1335 | /* For hangcheck timer */ | |
1336 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
1337 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
1338 | /* Hang gpu twice in this window and your context gets banned */ | |
1339 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) | |
1340 | ||
1341 | struct timer_list hangcheck_timer; | |
1342 | ||
1343 | /* For reset and error_state handling. */ | |
1344 | spinlock_t lock; | |
1345 | /* Protected by the above dev->gpu_error.lock. */ | |
1346 | struct drm_i915_error_state *first_error; | |
1347 | struct work_struct work; | |
1348 | ||
1349 | ||
1350 | unsigned long missed_irq_rings; | |
1351 | ||
1352 | /** | |
1353 | * State variable controlling the reset flow and count | |
1354 | * | |
1355 | * This is a counter which gets incremented when reset is triggered, | |
1356 | * and again when reset has been handled. So odd values (lowest bit set) | |
1357 | * means that reset is in progress and even values that | |
1358 | * (reset_counter >> 1):th reset was successfully completed. | |
1359 | * | |
1360 | * If reset is not completed succesfully, the I915_WEDGE bit is | |
1361 | * set meaning that hardware is terminally sour and there is no | |
1362 | * recovery. All waiters on the reset_queue will be woken when | |
1363 | * that happens. | |
1364 | * | |
1365 | * This counter is used by the wait_seqno code to notice that reset | |
1366 | * event happened and it needs to restart the entire ioctl (since most | |
1367 | * likely the seqno it waited for won't ever signal anytime soon). | |
1368 | * | |
1369 | * This is important for lock-free wait paths, where no contended lock | |
1370 | * naturally enforces the correct ordering between the bail-out of the | |
1371 | * waiter and the gpu reset work code. | |
1372 | */ | |
1373 | atomic_t reset_counter; | |
1374 | ||
1375 | #define I915_RESET_IN_PROGRESS_FLAG 1 | |
1376 | #define I915_WEDGED (1 << 31) | |
1377 | ||
1378 | /** | |
1379 | * Waitqueue to signal when the reset has completed. Used by clients | |
1380 | * that wait for dev_priv->mm.wedged to settle. | |
1381 | */ | |
1382 | wait_queue_head_t reset_queue; | |
1383 | ||
1384 | /* Userspace knobs for gpu hang simulation; | |
1385 | * combines both a ring mask, and extra flags | |
1386 | */ | |
1387 | u32 stop_rings; | |
1388 | #define I915_STOP_RING_ALLOW_BAN (1 << 31) | |
1389 | #define I915_STOP_RING_ALLOW_WARN (1 << 30) | |
1390 | ||
1391 | /* For missed irq/seqno simulation. */ | |
1392 | unsigned int test_irq_rings; | |
1393 | ||
1394 | /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ | |
1395 | bool reload_in_reset; | |
1396 | }; | |
1397 | ||
1398 | enum modeset_restore { | |
1399 | MODESET_ON_LID_OPEN, | |
1400 | MODESET_DONE, | |
1401 | MODESET_SUSPENDED, | |
1402 | }; | |
1403 | ||
1404 | struct ddi_vbt_port_info { | |
1405 | /* | |
1406 | * This is an index in the HDMI/DVI DDI buffer translation table. | |
1407 | * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't | |
1408 | * populate this field. | |
1409 | */ | |
1410 | #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff | |
1411 | uint8_t hdmi_level_shift; | |
1412 | ||
1413 | uint8_t supports_dvi:1; | |
1414 | uint8_t supports_hdmi:1; | |
1415 | uint8_t supports_dp:1; | |
1416 | }; | |
1417 | ||
1418 | enum psr_lines_to_wait { | |
1419 | PSR_0_LINES_TO_WAIT = 0, | |
1420 | PSR_1_LINE_TO_WAIT, | |
1421 | PSR_4_LINES_TO_WAIT, | |
1422 | PSR_8_LINES_TO_WAIT | |
1423 | }; | |
1424 | ||
1425 | struct intel_vbt_data { | |
1426 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1427 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1428 | ||
1429 | /* Feature bits */ | |
1430 | unsigned int int_tv_support:1; | |
1431 | unsigned int lvds_dither:1; | |
1432 | unsigned int lvds_vbt:1; | |
1433 | unsigned int int_crt_support:1; | |
1434 | unsigned int lvds_use_ssc:1; | |
1435 | unsigned int display_clock_mode:1; | |
1436 | unsigned int fdi_rx_polarity_inverted:1; | |
1437 | unsigned int has_mipi:1; | |
1438 | int lvds_ssc_freq; | |
1439 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1440 | ||
1441 | enum drrs_support_type drrs_type; | |
1442 | ||
1443 | /* eDP */ | |
1444 | int edp_rate; | |
1445 | int edp_lanes; | |
1446 | int edp_preemphasis; | |
1447 | int edp_vswing; | |
1448 | bool edp_initialized; | |
1449 | bool edp_support; | |
1450 | int edp_bpp; | |
1451 | struct edp_power_seq edp_pps; | |
1452 | ||
1453 | struct { | |
1454 | bool full_link; | |
1455 | bool require_aux_wakeup; | |
1456 | int idle_frames; | |
1457 | enum psr_lines_to_wait lines_to_wait; | |
1458 | int tp1_wakeup_time; | |
1459 | int tp2_tp3_wakeup_time; | |
1460 | } psr; | |
1461 | ||
1462 | struct { | |
1463 | u16 pwm_freq_hz; | |
1464 | bool present; | |
1465 | bool active_low_pwm; | |
1466 | u8 min_brightness; /* min_brightness/255 of max */ | |
1467 | } backlight; | |
1468 | ||
1469 | /* MIPI DSI */ | |
1470 | struct { | |
1471 | u16 port; | |
1472 | u16 panel_id; | |
1473 | struct mipi_config *config; | |
1474 | struct mipi_pps_data *pps; | |
1475 | u8 seq_version; | |
1476 | u32 size; | |
1477 | u8 *data; | |
1478 | u8 *sequence[MIPI_SEQ_MAX]; | |
1479 | } dsi; | |
1480 | ||
1481 | int crt_ddc_pin; | |
1482 | ||
1483 | int child_dev_num; | |
1484 | union child_device_config *child_dev; | |
1485 | ||
1486 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
1487 | }; | |
1488 | ||
1489 | enum intel_ddb_partitioning { | |
1490 | INTEL_DDB_PART_1_2, | |
1491 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1492 | }; | |
1493 | ||
1494 | struct intel_wm_level { | |
1495 | bool enable; | |
1496 | uint32_t pri_val; | |
1497 | uint32_t spr_val; | |
1498 | uint32_t cur_val; | |
1499 | uint32_t fbc_val; | |
1500 | }; | |
1501 | ||
1502 | struct ilk_wm_values { | |
1503 | uint32_t wm_pipe[3]; | |
1504 | uint32_t wm_lp[3]; | |
1505 | uint32_t wm_lp_spr[3]; | |
1506 | uint32_t wm_linetime[3]; | |
1507 | bool enable_fbc_wm; | |
1508 | enum intel_ddb_partitioning partitioning; | |
1509 | }; | |
1510 | ||
1511 | struct skl_ddb_entry { | |
1512 | uint16_t start, end; /* in number of blocks, 'end' is exclusive */ | |
1513 | }; | |
1514 | ||
1515 | static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) | |
1516 | { | |
1517 | return entry->end - entry->start; | |
1518 | } | |
1519 | ||
1520 | static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, | |
1521 | const struct skl_ddb_entry *e2) | |
1522 | { | |
1523 | if (e1->start == e2->start && e1->end == e2->end) | |
1524 | return true; | |
1525 | ||
1526 | return false; | |
1527 | } | |
1528 | ||
1529 | struct skl_ddb_allocation { | |
1530 | struct skl_ddb_entry pipe[I915_MAX_PIPES]; | |
1531 | struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; | |
1532 | struct skl_ddb_entry cursor[I915_MAX_PIPES]; | |
1533 | }; | |
1534 | ||
1535 | struct skl_wm_values { | |
1536 | bool dirty[I915_MAX_PIPES]; | |
1537 | struct skl_ddb_allocation ddb; | |
1538 | uint32_t wm_linetime[I915_MAX_PIPES]; | |
1539 | uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; | |
1540 | uint32_t cursor[I915_MAX_PIPES][8]; | |
1541 | uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES]; | |
1542 | uint32_t cursor_trans[I915_MAX_PIPES]; | |
1543 | }; | |
1544 | ||
1545 | struct skl_wm_level { | |
1546 | bool plane_en[I915_MAX_PLANES]; | |
1547 | bool cursor_en; | |
1548 | uint16_t plane_res_b[I915_MAX_PLANES]; | |
1549 | uint8_t plane_res_l[I915_MAX_PLANES]; | |
1550 | uint16_t cursor_res_b; | |
1551 | uint8_t cursor_res_l; | |
1552 | }; | |
1553 | ||
1554 | /* | |
1555 | * This struct helps tracking the state needed for runtime PM, which puts the | |
1556 | * device in PCI D3 state. Notice that when this happens, nothing on the | |
1557 | * graphics device works, even register access, so we don't get interrupts nor | |
1558 | * anything else. | |
1559 | * | |
1560 | * Every piece of our code that needs to actually touch the hardware needs to | |
1561 | * either call intel_runtime_pm_get or call intel_display_power_get with the | |
1562 | * appropriate power domain. | |
1563 | * | |
1564 | * Our driver uses the autosuspend delay feature, which means we'll only really | |
1565 | * suspend if we stay with zero refcount for a certain amount of time. The | |
1566 | * default value is currently very conservative (see intel_runtime_pm_enable), but | |
1567 | * it can be changed with the standard runtime PM files from sysfs. | |
1568 | * | |
1569 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1570 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1571 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1572 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
1573 | * case it happens. | |
1574 | * | |
1575 | * For more, read the Documentation/power/runtime_pm.txt. | |
1576 | */ | |
1577 | struct i915_runtime_pm { | |
1578 | bool suspended; | |
1579 | bool irqs_enabled; | |
1580 | }; | |
1581 | ||
1582 | enum intel_pipe_crc_source { | |
1583 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1584 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1585 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1586 | INTEL_PIPE_CRC_SOURCE_PF, | |
1587 | INTEL_PIPE_CRC_SOURCE_PIPE, | |
1588 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ | |
1589 | INTEL_PIPE_CRC_SOURCE_TV, | |
1590 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1591 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1592 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
1593 | INTEL_PIPE_CRC_SOURCE_AUTO, | |
1594 | INTEL_PIPE_CRC_SOURCE_MAX, | |
1595 | }; | |
1596 | ||
1597 | struct intel_pipe_crc_entry { | |
1598 | uint32_t frame; | |
1599 | uint32_t crc[5]; | |
1600 | }; | |
1601 | ||
1602 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 | |
1603 | struct intel_pipe_crc { | |
1604 | spinlock_t lock; | |
1605 | bool opened; /* exclusive access to the result file */ | |
1606 | struct intel_pipe_crc_entry *entries; | |
1607 | enum intel_pipe_crc_source source; | |
1608 | int head, tail; | |
1609 | wait_queue_head_t wq; | |
1610 | }; | |
1611 | ||
1612 | struct i915_frontbuffer_tracking { | |
1613 | struct mutex lock; | |
1614 | ||
1615 | /* | |
1616 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or | |
1617 | * scheduled flips. | |
1618 | */ | |
1619 | unsigned busy_bits; | |
1620 | unsigned flip_bits; | |
1621 | }; | |
1622 | ||
1623 | struct i915_wa_reg { | |
1624 | u32 addr; | |
1625 | u32 value; | |
1626 | /* bitmask representing WA bits */ | |
1627 | u32 mask; | |
1628 | }; | |
1629 | ||
1630 | #define I915_MAX_WA_REGS 16 | |
1631 | ||
1632 | struct i915_workarounds { | |
1633 | struct i915_wa_reg reg[I915_MAX_WA_REGS]; | |
1634 | u32 count; | |
1635 | }; | |
1636 | ||
1637 | struct drm_i915_private { | |
1638 | struct drm_device *dev; | |
1639 | struct kmem_cache *slab; | |
1640 | ||
1641 | const struct intel_device_info info; | |
1642 | ||
1643 | int relative_constants_mode; | |
1644 | ||
1645 | void __iomem *regs; | |
1646 | ||
1647 | struct intel_uncore uncore; | |
1648 | ||
1649 | struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; | |
1650 | ||
1651 | ||
1652 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus | |
1653 | * controller on different i2c buses. */ | |
1654 | struct mutex gmbus_mutex; | |
1655 | ||
1656 | /** | |
1657 | * Base address of the gmbus and gpio block. | |
1658 | */ | |
1659 | uint32_t gpio_mmio_base; | |
1660 | ||
1661 | /* MMIO base address for MIPI regs */ | |
1662 | uint32_t mipi_mmio_base; | |
1663 | ||
1664 | wait_queue_head_t gmbus_wait_queue; | |
1665 | ||
1666 | struct pci_dev *bridge_dev; | |
1667 | struct intel_engine_cs ring[I915_NUM_RINGS]; | |
1668 | struct drm_i915_gem_object *semaphore_obj; | |
1669 | uint32_t last_seqno, next_seqno; | |
1670 | ||
1671 | struct drm_dma_handle *status_page_dmah; | |
1672 | struct resource mch_res; | |
1673 | ||
1674 | /* protects the irq masks */ | |
1675 | spinlock_t irq_lock; | |
1676 | ||
1677 | /* protects the mmio flip data */ | |
1678 | spinlock_t mmio_flip_lock; | |
1679 | ||
1680 | bool display_irqs_enabled; | |
1681 | ||
1682 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ | |
1683 | struct pm_qos_request pm_qos; | |
1684 | ||
1685 | /* DPIO indirect register protection */ | |
1686 | struct mutex dpio_lock; | |
1687 | ||
1688 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
1689 | union { | |
1690 | u32 irq_mask; | |
1691 | u32 de_irq_mask[I915_MAX_PIPES]; | |
1692 | }; | |
1693 | u32 gt_irq_mask; | |
1694 | u32 pm_irq_mask; | |
1695 | u32 pm_rps_events; | |
1696 | u32 pipestat_irq_mask[I915_MAX_PIPES]; | |
1697 | ||
1698 | struct work_struct hotplug_work; | |
1699 | struct { | |
1700 | unsigned long hpd_last_jiffies; | |
1701 | int hpd_cnt; | |
1702 | enum { | |
1703 | HPD_ENABLED = 0, | |
1704 | HPD_DISABLED = 1, | |
1705 | HPD_MARK_DISABLED = 2 | |
1706 | } hpd_mark; | |
1707 | } hpd_stats[HPD_NUM_PINS]; | |
1708 | u32 hpd_event_bits; | |
1709 | struct delayed_work hotplug_reenable_work; | |
1710 | ||
1711 | struct i915_fbc fbc; | |
1712 | struct i915_drrs drrs; | |
1713 | struct intel_opregion opregion; | |
1714 | struct intel_vbt_data vbt; | |
1715 | ||
1716 | bool preserve_bios_swizzle; | |
1717 | ||
1718 | /* overlay */ | |
1719 | struct intel_overlay *overlay; | |
1720 | ||
1721 | /* backlight registers and fields in struct intel_panel */ | |
1722 | struct mutex backlight_lock; | |
1723 | ||
1724 | /* LVDS info */ | |
1725 | bool no_aux_handshake; | |
1726 | ||
1727 | /* protects panel power sequencer state */ | |
1728 | struct mutex pps_mutex; | |
1729 | ||
1730 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ | |
1731 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
1732 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
1733 | ||
1734 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
1735 | unsigned int vlv_cdclk_freq; | |
1736 | unsigned int hpll_freq; | |
1737 | ||
1738 | /** | |
1739 | * wq - Driver workqueue for GEM. | |
1740 | * | |
1741 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
1742 | * locks, for otherwise the flushing done in the pageflip code will | |
1743 | * result in deadlocks. | |
1744 | */ | |
1745 | struct workqueue_struct *wq; | |
1746 | ||
1747 | /* Display functions */ | |
1748 | struct drm_i915_display_funcs display; | |
1749 | ||
1750 | /* PCH chipset type */ | |
1751 | enum intel_pch pch_type; | |
1752 | unsigned short pch_id; | |
1753 | ||
1754 | unsigned long quirks; | |
1755 | ||
1756 | enum modeset_restore modeset_restore; | |
1757 | struct mutex modeset_restore_lock; | |
1758 | ||
1759 | struct list_head vm_list; /* Global list of all address spaces */ | |
1760 | struct i915_gtt gtt; /* VM representing the global address space */ | |
1761 | ||
1762 | struct i915_gem_mm mm; | |
1763 | DECLARE_HASHTABLE(mm_structs, 7); | |
1764 | struct mutex mm_lock; | |
1765 | ||
1766 | /* Kernel Modesetting */ | |
1767 | ||
1768 | struct sdvo_device_mapping sdvo_mappings[2]; | |
1769 | ||
1770 | struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; | |
1771 | struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; | |
1772 | wait_queue_head_t pending_flip_queue; | |
1773 | ||
1774 | #ifdef CONFIG_DEBUG_FS | |
1775 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
1776 | #endif | |
1777 | ||
1778 | int num_shared_dpll; | |
1779 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
1780 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; | |
1781 | ||
1782 | struct i915_workarounds workarounds; | |
1783 | ||
1784 | /* Reclocking support */ | |
1785 | bool render_reclock_avail; | |
1786 | bool lvds_downclock_avail; | |
1787 | /* indicates the reduced downclock for LVDS*/ | |
1788 | int lvds_downclock; | |
1789 | ||
1790 | struct i915_frontbuffer_tracking fb_tracking; | |
1791 | ||
1792 | u16 orig_clock; | |
1793 | ||
1794 | bool mchbar_need_disable; | |
1795 | ||
1796 | struct intel_l3_parity l3_parity; | |
1797 | ||
1798 | /* Cannot be determined by PCIID. You must always read a register. */ | |
1799 | size_t ellc_size; | |
1800 | ||
1801 | /* gen6+ rps state */ | |
1802 | struct intel_gen6_power_mgmt rps; | |
1803 | ||
1804 | /* ilk-only ips/rps state. Everything in here is protected by the global | |
1805 | * mchdev_lock in intel_pm.c */ | |
1806 | struct intel_ilk_power_mgmt ips; | |
1807 | ||
1808 | struct i915_power_domains power_domains; | |
1809 | ||
1810 | struct i915_psr psr; | |
1811 | ||
1812 | struct i915_gpu_error gpu_error; | |
1813 | ||
1814 | struct drm_i915_gem_object *vlv_pctx; | |
1815 | ||
1816 | #ifdef CONFIG_DRM_I915_FBDEV | |
1817 | /* list of fbdev register on this device */ | |
1818 | struct intel_fbdev *fbdev; | |
1819 | struct work_struct fbdev_suspend_work; | |
1820 | #endif | |
1821 | ||
1822 | struct drm_property *broadcast_rgb_property; | |
1823 | struct drm_property *force_audio_property; | |
1824 | ||
1825 | /* hda/i915 audio component */ | |
1826 | bool audio_component_registered; | |
1827 | ||
1828 | uint32_t hw_context_size; | |
1829 | struct list_head context_list; | |
1830 | ||
1831 | u32 fdi_rx_config; | |
1832 | ||
1833 | u32 suspend_count; | |
1834 | struct i915_suspend_saved_registers regfile; | |
1835 | struct vlv_s0ix_state vlv_s0ix_state; | |
1836 | ||
1837 | struct { | |
1838 | /* | |
1839 | * Raw watermark latency values: | |
1840 | * in 0.1us units for WM0, | |
1841 | * in 0.5us units for WM1+. | |
1842 | */ | |
1843 | /* primary */ | |
1844 | uint16_t pri_latency[5]; | |
1845 | /* sprite */ | |
1846 | uint16_t spr_latency[5]; | |
1847 | /* cursor */ | |
1848 | uint16_t cur_latency[5]; | |
1849 | /* | |
1850 | * Raw watermark memory latency values | |
1851 | * for SKL for all 8 levels | |
1852 | * in 1us units. | |
1853 | */ | |
1854 | uint16_t skl_latency[8]; | |
1855 | ||
1856 | /* | |
1857 | * The skl_wm_values structure is a bit too big for stack | |
1858 | * allocation, so we keep the staging struct where we store | |
1859 | * intermediate results here instead. | |
1860 | */ | |
1861 | struct skl_wm_values skl_results; | |
1862 | ||
1863 | /* current hardware state */ | |
1864 | union { | |
1865 | struct ilk_wm_values hw; | |
1866 | struct skl_wm_values skl_hw; | |
1867 | }; | |
1868 | } wm; | |
1869 | ||
1870 | struct i915_runtime_pm pm; | |
1871 | ||
1872 | struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS]; | |
1873 | u32 long_hpd_port_mask; | |
1874 | u32 short_hpd_port_mask; | |
1875 | struct work_struct dig_port_work; | |
1876 | ||
1877 | /* | |
1878 | * if we get a HPD irq from DP and a HPD irq from non-DP | |
1879 | * the non-DP HPD could block the workqueue on a mode config | |
1880 | * mutex getting, that userspace may have taken. However | |
1881 | * userspace is waiting on the DP workqueue to run which is | |
1882 | * blocked behind the non-DP one. | |
1883 | */ | |
1884 | struct workqueue_struct *dp_wq; | |
1885 | ||
1886 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ | |
1887 | struct { | |
1888 | int (*do_execbuf)(struct drm_device *dev, struct drm_file *file, | |
1889 | struct intel_engine_cs *ring, | |
1890 | struct intel_context *ctx, | |
1891 | struct drm_i915_gem_execbuffer2 *args, | |
1892 | struct list_head *vmas, | |
1893 | struct drm_i915_gem_object *batch_obj, | |
1894 | u64 exec_start, u32 flags); | |
1895 | int (*init_rings)(struct drm_device *dev); | |
1896 | void (*cleanup_ring)(struct intel_engine_cs *ring); | |
1897 | void (*stop_ring)(struct intel_engine_cs *ring); | |
1898 | } gt; | |
1899 | ||
1900 | uint32_t request_uniq; | |
1901 | ||
1902 | /* | |
1903 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch | |
1904 | * will be rejected. Instead look for a better place. | |
1905 | */ | |
1906 | }; | |
1907 | ||
1908 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) | |
1909 | { | |
1910 | return dev->dev_private; | |
1911 | } | |
1912 | ||
1913 | static inline struct drm_i915_private *dev_to_i915(struct device *dev) | |
1914 | { | |
1915 | return to_i915(dev_get_drvdata(dev)); | |
1916 | } | |
1917 | ||
1918 | /* Iterate over initialised rings */ | |
1919 | #define for_each_ring(ring__, dev_priv__, i__) \ | |
1920 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ | |
1921 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) | |
1922 | ||
1923 | enum hdmi_force_audio { | |
1924 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
1925 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
1926 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
1927 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
1928 | }; | |
1929 | ||
1930 | #define I915_GTT_OFFSET_NONE ((u32)-1) | |
1931 | ||
1932 | struct drm_i915_gem_object_ops { | |
1933 | /* Interface between the GEM object and its backing storage. | |
1934 | * get_pages() is called once prior to the use of the associated set | |
1935 | * of pages before to binding them into the GTT, and put_pages() is | |
1936 | * called after we no longer need them. As we expect there to be | |
1937 | * associated cost with migrating pages between the backing storage | |
1938 | * and making them available for the GPU (e.g. clflush), we may hold | |
1939 | * onto the pages after they are no longer referenced by the GPU | |
1940 | * in case they may be used again shortly (for example migrating the | |
1941 | * pages to a different memory domain within the GTT). put_pages() | |
1942 | * will therefore most likely be called when the object itself is | |
1943 | * being released or under memory pressure (where we attempt to | |
1944 | * reap pages for the shrinker). | |
1945 | */ | |
1946 | int (*get_pages)(struct drm_i915_gem_object *); | |
1947 | void (*put_pages)(struct drm_i915_gem_object *); | |
1948 | int (*dmabuf_export)(struct drm_i915_gem_object *); | |
1949 | void (*release)(struct drm_i915_gem_object *); | |
1950 | }; | |
1951 | ||
1952 | /* | |
1953 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is | |
1954 | * considered to be the frontbuffer for the given plane interface-vise. This | |
1955 | * doesn't mean that the hw necessarily already scans it out, but that any | |
1956 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. | |
1957 | * | |
1958 | * We have one bit per pipe and per scanout plane type. | |
1959 | */ | |
1960 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4 | |
1961 | #define INTEL_FRONTBUFFER_BITS \ | |
1962 | (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES) | |
1963 | #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ | |
1964 | (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
1965 | #define INTEL_FRONTBUFFER_CURSOR(pipe) \ | |
1966 | (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
1967 | #define INTEL_FRONTBUFFER_SPRITE(pipe) \ | |
1968 | (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
1969 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ | |
1970 | (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
1971 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ | |
1972 | (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
1973 | ||
1974 | struct drm_i915_gem_object { | |
1975 | struct drm_gem_object base; | |
1976 | ||
1977 | const struct drm_i915_gem_object_ops *ops; | |
1978 | ||
1979 | /** List of VMAs backed by this object */ | |
1980 | struct list_head vma_list; | |
1981 | ||
1982 | /** Stolen memory for this object, instead of being backed by shmem. */ | |
1983 | struct drm_mm_node *stolen; | |
1984 | struct list_head global_list; | |
1985 | ||
1986 | struct list_head ring_list; | |
1987 | /** Used in execbuf to temporarily hold a ref */ | |
1988 | struct list_head obj_exec_link; | |
1989 | ||
1990 | struct list_head batch_pool_list; | |
1991 | ||
1992 | /** | |
1993 | * This is set if the object is on the active lists (has pending | |
1994 | * rendering and so a non-zero seqno), and is not set if it i s on | |
1995 | * inactive (ready to be unbound) list. | |
1996 | */ | |
1997 | unsigned int active:1; | |
1998 | ||
1999 | /** | |
2000 | * This is set if the object has been written to since last bound | |
2001 | * to the GTT | |
2002 | */ | |
2003 | unsigned int dirty:1; | |
2004 | ||
2005 | /** | |
2006 | * Fence register bits (if any) for this object. Will be set | |
2007 | * as needed when mapped into the GTT. | |
2008 | * Protected by dev->struct_mutex. | |
2009 | */ | |
2010 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; | |
2011 | ||
2012 | /** | |
2013 | * Advice: are the backing pages purgeable? | |
2014 | */ | |
2015 | unsigned int madv:2; | |
2016 | ||
2017 | /** | |
2018 | * Current tiling mode for the object. | |
2019 | */ | |
2020 | unsigned int tiling_mode:2; | |
2021 | /** | |
2022 | * Whether the tiling parameters for the currently associated fence | |
2023 | * register have changed. Note that for the purposes of tracking | |
2024 | * tiling changes we also treat the unfenced register, the register | |
2025 | * slot that the object occupies whilst it executes a fenced | |
2026 | * command (such as BLT on gen2/3), as a "fence". | |
2027 | */ | |
2028 | unsigned int fence_dirty:1; | |
2029 | ||
2030 | /** | |
2031 | * Is the object at the current location in the gtt mappable and | |
2032 | * fenceable? Used to avoid costly recalculations. | |
2033 | */ | |
2034 | unsigned int map_and_fenceable:1; | |
2035 | ||
2036 | /** | |
2037 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
2038 | * mappable by accident). Track pin and fault separate for a more | |
2039 | * accurate mappable working set. | |
2040 | */ | |
2041 | unsigned int fault_mappable:1; | |
2042 | unsigned int pin_mappable:1; | |
2043 | unsigned int pin_display:1; | |
2044 | ||
2045 | /* | |
2046 | * Is the object to be mapped as read-only to the GPU | |
2047 | * Only honoured if hardware has relevant pte bit | |
2048 | */ | |
2049 | unsigned long gt_ro:1; | |
2050 | unsigned int cache_level:3; | |
2051 | ||
2052 | unsigned int has_dma_mapping:1; | |
2053 | ||
2054 | unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS; | |
2055 | ||
2056 | struct sg_table *pages; | |
2057 | int pages_pin_count; | |
2058 | ||
2059 | /* prime dma-buf support */ | |
2060 | void *dma_buf_vmapping; | |
2061 | int vmapping_count; | |
2062 | ||
2063 | /** Breadcrumb of last rendering to the buffer. */ | |
2064 | struct drm_i915_gem_request *last_read_req; | |
2065 | struct drm_i915_gem_request *last_write_req; | |
2066 | /** Breadcrumb of last fenced GPU access to the buffer. */ | |
2067 | struct drm_i915_gem_request *last_fenced_req; | |
2068 | ||
2069 | /** Current tiling stride for the object, if it's tiled. */ | |
2070 | uint32_t stride; | |
2071 | ||
2072 | /** References from framebuffers, locks out tiling changes. */ | |
2073 | unsigned long framebuffer_references; | |
2074 | ||
2075 | /** Record of address bit 17 of each page at last unbind. */ | |
2076 | unsigned long *bit_17; | |
2077 | ||
2078 | union { | |
2079 | /** for phy allocated objects */ | |
2080 | struct drm_dma_handle *phys_handle; | |
2081 | ||
2082 | struct i915_gem_userptr { | |
2083 | uintptr_t ptr; | |
2084 | unsigned read_only :1; | |
2085 | unsigned workers :4; | |
2086 | #define I915_GEM_USERPTR_MAX_WORKERS 15 | |
2087 | ||
2088 | struct i915_mm_struct *mm; | |
2089 | struct i915_mmu_object *mmu_object; | |
2090 | struct work_struct *work; | |
2091 | } userptr; | |
2092 | }; | |
2093 | }; | |
2094 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) | |
2095 | ||
2096 | void i915_gem_track_fb(struct drm_i915_gem_object *old, | |
2097 | struct drm_i915_gem_object *new, | |
2098 | unsigned frontbuffer_bits); | |
2099 | ||
2100 | /** | |
2101 | * Request queue structure. | |
2102 | * | |
2103 | * The request queue allows us to note sequence numbers that have been emitted | |
2104 | * and may be associated with active buffers to be retired. | |
2105 | * | |
2106 | * By keeping this list, we can avoid having to do questionable sequence | |
2107 | * number comparisons on buffer last_read|write_seqno. It also allows an | |
2108 | * emission time to be associated with the request for tracking how far ahead | |
2109 | * of the GPU the submission is. | |
2110 | */ | |
2111 | struct drm_i915_gem_request { | |
2112 | struct kref ref; | |
2113 | ||
2114 | /** On Which ring this request was generated */ | |
2115 | struct intel_engine_cs *ring; | |
2116 | ||
2117 | /** GEM sequence number associated with this request. */ | |
2118 | uint32_t seqno; | |
2119 | ||
2120 | /** Position in the ringbuffer of the start of the request */ | |
2121 | u32 head; | |
2122 | ||
2123 | /** | |
2124 | * Position in the ringbuffer of the start of the postfix. | |
2125 | * This is required to calculate the maximum available ringbuffer | |
2126 | * space without overwriting the postfix. | |
2127 | */ | |
2128 | u32 postfix; | |
2129 | ||
2130 | /** Position in the ringbuffer of the end of the whole request */ | |
2131 | u32 tail; | |
2132 | ||
2133 | /** Context related to this request */ | |
2134 | struct intel_context *ctx; | |
2135 | ||
2136 | /** Batch buffer related to this request if any */ | |
2137 | struct drm_i915_gem_object *batch_obj; | |
2138 | ||
2139 | /** Time at which this request was emitted, in jiffies. */ | |
2140 | unsigned long emitted_jiffies; | |
2141 | ||
2142 | /** global list entry for this request */ | |
2143 | struct list_head list; | |
2144 | ||
2145 | struct drm_i915_file_private *file_priv; | |
2146 | /** file_priv list entry for this request */ | |
2147 | struct list_head client_list; | |
2148 | ||
2149 | uint32_t uniq; | |
2150 | ||
2151 | /** | |
2152 | * The ELSP only accepts two elements at a time, so we queue | |
2153 | * context/tail pairs on a given queue (ring->execlist_queue) until the | |
2154 | * hardware is available. The queue serves a double purpose: we also use | |
2155 | * it to keep track of the up to 2 contexts currently in the hardware | |
2156 | * (usually one in execution and the other queued up by the GPU): We | |
2157 | * only remove elements from the head of the queue when the hardware | |
2158 | * informs us that an element has been completed. | |
2159 | * | |
2160 | * All accesses to the queue are mediated by a spinlock | |
2161 | * (ring->execlist_lock). | |
2162 | */ | |
2163 | ||
2164 | /** Execlist link in the submission queue.*/ | |
2165 | struct list_head execlist_link; | |
2166 | ||
2167 | /** Execlists no. of times this request has been sent to the ELSP */ | |
2168 | int elsp_submitted; | |
2169 | ||
2170 | }; | |
2171 | ||
2172 | void i915_gem_request_free(struct kref *req_ref); | |
2173 | ||
2174 | static inline uint32_t | |
2175 | i915_gem_request_get_seqno(struct drm_i915_gem_request *req) | |
2176 | { | |
2177 | return req ? req->seqno : 0; | |
2178 | } | |
2179 | ||
2180 | static inline struct intel_engine_cs * | |
2181 | i915_gem_request_get_ring(struct drm_i915_gem_request *req) | |
2182 | { | |
2183 | return req ? req->ring : NULL; | |
2184 | } | |
2185 | ||
2186 | static inline void | |
2187 | i915_gem_request_reference(struct drm_i915_gem_request *req) | |
2188 | { | |
2189 | kref_get(&req->ref); | |
2190 | } | |
2191 | ||
2192 | static inline void | |
2193 | i915_gem_request_unreference(struct drm_i915_gem_request *req) | |
2194 | { | |
2195 | WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex)); | |
2196 | kref_put(&req->ref, i915_gem_request_free); | |
2197 | } | |
2198 | ||
2199 | static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst, | |
2200 | struct drm_i915_gem_request *src) | |
2201 | { | |
2202 | if (src) | |
2203 | i915_gem_request_reference(src); | |
2204 | ||
2205 | if (*pdst) | |
2206 | i915_gem_request_unreference(*pdst); | |
2207 | ||
2208 | *pdst = src; | |
2209 | } | |
2210 | ||
2211 | /* | |
2212 | * XXX: i915_gem_request_completed should be here but currently needs the | |
2213 | * definition of i915_seqno_passed() which is below. It will be moved in | |
2214 | * a later patch when the call to i915_seqno_passed() is obsoleted... | |
2215 | */ | |
2216 | ||
2217 | struct drm_i915_file_private { | |
2218 | struct drm_i915_private *dev_priv; | |
2219 | struct drm_file *file; | |
2220 | ||
2221 | struct { | |
2222 | spinlock_t lock; | |
2223 | struct list_head request_list; | |
2224 | struct delayed_work idle_work; | |
2225 | } mm; | |
2226 | struct idr context_idr; | |
2227 | ||
2228 | atomic_t rps_wait_boost; | |
2229 | struct intel_engine_cs *bsd_ring; | |
2230 | }; | |
2231 | ||
2232 | /* | |
2233 | * A command that requires special handling by the command parser. | |
2234 | */ | |
2235 | struct drm_i915_cmd_descriptor { | |
2236 | /* | |
2237 | * Flags describing how the command parser processes the command. | |
2238 | * | |
2239 | * CMD_DESC_FIXED: The command has a fixed length if this is set, | |
2240 | * a length mask if not set | |
2241 | * CMD_DESC_SKIP: The command is allowed but does not follow the | |
2242 | * standard length encoding for the opcode range in | |
2243 | * which it falls | |
2244 | * CMD_DESC_REJECT: The command is never allowed | |
2245 | * CMD_DESC_REGISTER: The command should be checked against the | |
2246 | * register whitelist for the appropriate ring | |
2247 | * CMD_DESC_MASTER: The command is allowed if the submitting process | |
2248 | * is the DRM master | |
2249 | */ | |
2250 | u32 flags; | |
2251 | #define CMD_DESC_FIXED (1<<0) | |
2252 | #define CMD_DESC_SKIP (1<<1) | |
2253 | #define CMD_DESC_REJECT (1<<2) | |
2254 | #define CMD_DESC_REGISTER (1<<3) | |
2255 | #define CMD_DESC_BITMASK (1<<4) | |
2256 | #define CMD_DESC_MASTER (1<<5) | |
2257 | ||
2258 | /* | |
2259 | * The command's unique identification bits and the bitmask to get them. | |
2260 | * This isn't strictly the opcode field as defined in the spec and may | |
2261 | * also include type, subtype, and/or subop fields. | |
2262 | */ | |
2263 | struct { | |
2264 | u32 value; | |
2265 | u32 mask; | |
2266 | } cmd; | |
2267 | ||
2268 | /* | |
2269 | * The command's length. The command is either fixed length (i.e. does | |
2270 | * not include a length field) or has a length field mask. The flag | |
2271 | * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has | |
2272 | * a length mask. All command entries in a command table must include | |
2273 | * length information. | |
2274 | */ | |
2275 | union { | |
2276 | u32 fixed; | |
2277 | u32 mask; | |
2278 | } length; | |
2279 | ||
2280 | /* | |
2281 | * Describes where to find a register address in the command to check | |
2282 | * against the ring's register whitelist. Only valid if flags has the | |
2283 | * CMD_DESC_REGISTER bit set. | |
2284 | */ | |
2285 | struct { | |
2286 | u32 offset; | |
2287 | u32 mask; | |
2288 | } reg; | |
2289 | ||
2290 | #define MAX_CMD_DESC_BITMASKS 3 | |
2291 | /* | |
2292 | * Describes command checks where a particular dword is masked and | |
2293 | * compared against an expected value. If the command does not match | |
2294 | * the expected value, the parser rejects it. Only valid if flags has | |
2295 | * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero | |
2296 | * are valid. | |
2297 | * | |
2298 | * If the check specifies a non-zero condition_mask then the parser | |
2299 | * only performs the check when the bits specified by condition_mask | |
2300 | * are non-zero. | |
2301 | */ | |
2302 | struct { | |
2303 | u32 offset; | |
2304 | u32 mask; | |
2305 | u32 expected; | |
2306 | u32 condition_offset; | |
2307 | u32 condition_mask; | |
2308 | } bits[MAX_CMD_DESC_BITMASKS]; | |
2309 | }; | |
2310 | ||
2311 | /* | |
2312 | * A table of commands requiring special handling by the command parser. | |
2313 | * | |
2314 | * Each ring has an array of tables. Each table consists of an array of command | |
2315 | * descriptors, which must be sorted with command opcodes in ascending order. | |
2316 | */ | |
2317 | struct drm_i915_cmd_table { | |
2318 | const struct drm_i915_cmd_descriptor *table; | |
2319 | int count; | |
2320 | }; | |
2321 | ||
2322 | /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ | |
2323 | #define __I915__(p) ({ \ | |
2324 | struct drm_i915_private *__p; \ | |
2325 | if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ | |
2326 | __p = (struct drm_i915_private *)p; \ | |
2327 | else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ | |
2328 | __p = to_i915((struct drm_device *)p); \ | |
2329 | else \ | |
2330 | BUILD_BUG(); \ | |
2331 | __p; \ | |
2332 | }) | |
2333 | #define INTEL_INFO(p) (&__I915__(p)->info) | |
2334 | #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) | |
2335 | ||
2336 | #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) | |
2337 | #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) | |
2338 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) | |
2339 | #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) | |
2340 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) | |
2341 | #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) | |
2342 | #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) | |
2343 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) | |
2344 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
2345 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
2346 | #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) | |
2347 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) | |
2348 | #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) | |
2349 | #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) | |
2350 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) | |
2351 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
2352 | #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) | |
2353 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) | |
2354 | #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ | |
2355 | INTEL_DEVID(dev) == 0x0152 || \ | |
2356 | INTEL_DEVID(dev) == 0x015a) | |
2357 | #define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \ | |
2358 | INTEL_DEVID(dev) == 0x0106 || \ | |
2359 | INTEL_DEVID(dev) == 0x010A) | |
2360 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) | |
2361 | #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) | |
2362 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) | |
2363 | #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) | |
2364 | #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) | |
2365 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) | |
2366 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ | |
2367 | (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) | |
2368 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ | |
2369 | ((INTEL_DEVID(dev) & 0xf) == 0x2 || \ | |
2370 | (INTEL_DEVID(dev) & 0xf) == 0x6 || \ | |
2371 | (INTEL_DEVID(dev) & 0xf) == 0xe)) | |
2372 | #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ | |
2373 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
2374 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ | |
2375 | (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) | |
2376 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ | |
2377 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
2378 | /* ULX machines are also considered ULT. */ | |
2379 | #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ | |
2380 | INTEL_DEVID(dev) == 0x0A1E) | |
2381 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) | |
2382 | ||
2383 | /* | |
2384 | * The genX designation typically refers to the render engine, so render | |
2385 | * capability related checks should use IS_GEN, while display and other checks | |
2386 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
2387 | * chips, etc.). | |
2388 | */ | |
2389 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) | |
2390 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
2391 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
2392 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
2393 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
2394 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) | |
2395 | #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) | |
2396 | #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9) | |
2397 | ||
2398 | #define RENDER_RING (1<<RCS) | |
2399 | #define BSD_RING (1<<VCS) | |
2400 | #define BLT_RING (1<<BCS) | |
2401 | #define VEBOX_RING (1<<VECS) | |
2402 | #define BSD2_RING (1<<VCS2) | |
2403 | #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) | |
2404 | #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING) | |
2405 | #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) | |
2406 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) | |
2407 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) | |
2408 | #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ | |
2409 | __I915__(dev)->ellc_size) | |
2410 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) | |
2411 | ||
2412 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) | |
2413 | #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8) | |
2414 | #define USES_PPGTT(dev) (i915.enable_ppgtt) | |
2415 | #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2) | |
2416 | ||
2417 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) | |
2418 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) | |
2419 | ||
2420 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ | |
2421 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) | |
2422 | /* | |
2423 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts | |
2424 | * even when in MSI mode. This results in spurious interrupt warnings if the | |
2425 | * legacy irq no. is shared with another device. The kernel then disables that | |
2426 | * interrupt source and so prevents the other device from working properly. | |
2427 | */ | |
2428 | #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
2429 | #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
2430 | ||
2431 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte | |
2432 | * rows, which changed the alignment requirements and fence programming. | |
2433 | */ | |
2434 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
2435 | IS_I915GM(dev))) | |
2436 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) | |
2437 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
2438 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
2439 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) | |
2440 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
2441 | ||
2442 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
2443 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
2444 | #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) | |
2445 | ||
2446 | #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) | |
2447 | ||
2448 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) | |
2449 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) | |
2450 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ | |
2451 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) | |
2452 | #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ | |
2453 | IS_BROADWELL(dev) || IS_VALLEYVIEW(dev)) | |
2454 | #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) | |
2455 | #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) | |
2456 | ||
2457 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 | |
2458 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
2459 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
2460 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
2461 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
2462 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
2463 | #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 | |
2464 | #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 | |
2465 | ||
2466 | #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) | |
2467 | #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT) | |
2468 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) | |
2469 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) | |
2470 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
2471 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) | |
2472 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) | |
2473 | ||
2474 | #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)) | |
2475 | ||
2476 | /* DPF == dynamic parity feature */ | |
2477 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
2478 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) | |
2479 | ||
2480 | #define GT_FREQUENCY_MULTIPLIER 50 | |
2481 | ||
2482 | #include "i915_trace.h" | |
2483 | ||
2484 | extern const struct drm_ioctl_desc i915_ioctls[]; | |
2485 | extern int i915_max_ioctl; | |
2486 | ||
2487 | extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state); | |
2488 | extern int i915_resume_legacy(struct drm_device *dev); | |
2489 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); | |
2490 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
2491 | ||
2492 | /* i915_params.c */ | |
2493 | struct i915_params { | |
2494 | int modeset; | |
2495 | int panel_ignore_lid; | |
2496 | unsigned int powersave; | |
2497 | int semaphores; | |
2498 | unsigned int lvds_downclock; | |
2499 | int lvds_channel_mode; | |
2500 | int panel_use_ssc; | |
2501 | int vbt_sdvo_panel_type; | |
2502 | int enable_rc6; | |
2503 | int enable_fbc; | |
2504 | int enable_ppgtt; | |
2505 | int enable_execlists; | |
2506 | int enable_psr; | |
2507 | unsigned int preliminary_hw_support; | |
2508 | int disable_power_well; | |
2509 | int enable_ips; | |
2510 | int invert_brightness; | |
2511 | int enable_cmd_parser; | |
2512 | /* leave bools at the end to not create holes */ | |
2513 | bool enable_hangcheck; | |
2514 | bool fastboot; | |
2515 | bool prefault_disable; | |
2516 | bool reset; | |
2517 | bool disable_display; | |
2518 | bool disable_vtd_wa; | |
2519 | int use_mmio_flip; | |
2520 | bool mmio_debug; | |
2521 | bool verbose_state_checks; | |
2522 | }; | |
2523 | extern struct i915_params i915 __read_mostly; | |
2524 | ||
2525 | /* i915_dma.c */ | |
2526 | extern int i915_driver_load(struct drm_device *, unsigned long flags); | |
2527 | extern int i915_driver_unload(struct drm_device *); | |
2528 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file); | |
2529 | extern void i915_driver_lastclose(struct drm_device * dev); | |
2530 | extern void i915_driver_preclose(struct drm_device *dev, | |
2531 | struct drm_file *file); | |
2532 | extern void i915_driver_postclose(struct drm_device *dev, | |
2533 | struct drm_file *file); | |
2534 | extern int i915_driver_device_is_agp(struct drm_device * dev); | |
2535 | #ifdef CONFIG_COMPAT | |
2536 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, | |
2537 | unsigned long arg); | |
2538 | #endif | |
2539 | extern int intel_gpu_reset(struct drm_device *dev); | |
2540 | extern int i915_reset(struct drm_device *dev); | |
2541 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); | |
2542 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
2543 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
2544 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
2545 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); | |
2546 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); | |
2547 | ||
2548 | /* i915_irq.c */ | |
2549 | void i915_queue_hangcheck(struct drm_device *dev); | |
2550 | __printf(3, 4) | |
2551 | void i915_handle_error(struct drm_device *dev, bool wedged, | |
2552 | const char *fmt, ...); | |
2553 | ||
2554 | extern void intel_irq_init(struct drm_i915_private *dev_priv); | |
2555 | extern void intel_hpd_init(struct drm_i915_private *dev_priv); | |
2556 | int intel_irq_install(struct drm_i915_private *dev_priv); | |
2557 | void intel_irq_uninstall(struct drm_i915_private *dev_priv); | |
2558 | ||
2559 | extern void intel_uncore_sanitize(struct drm_device *dev); | |
2560 | extern void intel_uncore_early_sanitize(struct drm_device *dev, | |
2561 | bool restore_forcewake); | |
2562 | extern void intel_uncore_init(struct drm_device *dev); | |
2563 | extern void intel_uncore_check_errors(struct drm_device *dev); | |
2564 | extern void intel_uncore_fini(struct drm_device *dev); | |
2565 | extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore); | |
2566 | const char *intel_uncore_forcewake_domain_to_str(const int domain_id); | |
2567 | void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, | |
2568 | unsigned fw_domains); | |
2569 | void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, | |
2570 | unsigned fw_domains); | |
2571 | void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); | |
2572 | ||
2573 | void | |
2574 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
2575 | u32 status_mask); | |
2576 | ||
2577 | void | |
2578 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
2579 | u32 status_mask); | |
2580 | ||
2581 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); | |
2582 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); | |
2583 | void | |
2584 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask); | |
2585 | void | |
2586 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask); | |
2587 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, | |
2588 | uint32_t interrupt_mask, | |
2589 | uint32_t enabled_irq_mask); | |
2590 | #define ibx_enable_display_interrupt(dev_priv, bits) \ | |
2591 | ibx_display_interrupt_update((dev_priv), (bits), (bits)) | |
2592 | #define ibx_disable_display_interrupt(dev_priv, bits) \ | |
2593 | ibx_display_interrupt_update((dev_priv), (bits), 0) | |
2594 | ||
2595 | /* i915_gem.c */ | |
2596 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
2597 | struct drm_file *file_priv); | |
2598 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
2599 | struct drm_file *file_priv); | |
2600 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
2601 | struct drm_file *file_priv); | |
2602 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
2603 | struct drm_file *file_priv); | |
2604 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
2605 | struct drm_file *file_priv); | |
2606 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
2607 | struct drm_file *file_priv); | |
2608 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
2609 | struct drm_file *file_priv); | |
2610 | void i915_gem_execbuffer_move_to_active(struct list_head *vmas, | |
2611 | struct intel_engine_cs *ring); | |
2612 | void i915_gem_execbuffer_retire_commands(struct drm_device *dev, | |
2613 | struct drm_file *file, | |
2614 | struct intel_engine_cs *ring, | |
2615 | struct drm_i915_gem_object *obj); | |
2616 | int i915_gem_ringbuffer_submission(struct drm_device *dev, | |
2617 | struct drm_file *file, | |
2618 | struct intel_engine_cs *ring, | |
2619 | struct intel_context *ctx, | |
2620 | struct drm_i915_gem_execbuffer2 *args, | |
2621 | struct list_head *vmas, | |
2622 | struct drm_i915_gem_object *batch_obj, | |
2623 | u64 exec_start, u32 flags); | |
2624 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
2625 | struct drm_file *file_priv); | |
2626 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
2627 | struct drm_file *file_priv); | |
2628 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
2629 | struct drm_file *file_priv); | |
2630 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, | |
2631 | struct drm_file *file); | |
2632 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
2633 | struct drm_file *file); | |
2634 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
2635 | struct drm_file *file_priv); | |
2636 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
2637 | struct drm_file *file_priv); | |
2638 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
2639 | struct drm_file *file_priv); | |
2640 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
2641 | struct drm_file *file_priv); | |
2642 | int i915_gem_init_userptr(struct drm_device *dev); | |
2643 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
2644 | struct drm_file *file); | |
2645 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
2646 | struct drm_file *file_priv); | |
2647 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, | |
2648 | struct drm_file *file_priv); | |
2649 | void i915_gem_load(struct drm_device *dev); | |
2650 | unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, | |
2651 | long target, | |
2652 | unsigned flags); | |
2653 | #define I915_SHRINK_PURGEABLE 0x1 | |
2654 | #define I915_SHRINK_UNBOUND 0x2 | |
2655 | #define I915_SHRINK_BOUND 0x4 | |
2656 | void *i915_gem_object_alloc(struct drm_device *dev); | |
2657 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
2658 | void i915_gem_object_init(struct drm_i915_gem_object *obj, | |
2659 | const struct drm_i915_gem_object_ops *ops); | |
2660 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, | |
2661 | size_t size); | |
2662 | void i915_init_vm(struct drm_i915_private *dev_priv, | |
2663 | struct i915_address_space *vm); | |
2664 | void i915_gem_free_object(struct drm_gem_object *obj); | |
2665 | void i915_gem_vma_destroy(struct i915_vma *vma); | |
2666 | ||
2667 | #define PIN_MAPPABLE 0x1 | |
2668 | #define PIN_NONBLOCK 0x2 | |
2669 | #define PIN_GLOBAL 0x4 | |
2670 | #define PIN_OFFSET_BIAS 0x8 | |
2671 | #define PIN_OFFSET_MASK (~4095) | |
2672 | int __must_check i915_gem_object_pin_view(struct drm_i915_gem_object *obj, | |
2673 | struct i915_address_space *vm, | |
2674 | uint32_t alignment, | |
2675 | uint64_t flags, | |
2676 | const struct i915_ggtt_view *view); | |
2677 | static inline | |
2678 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, | |
2679 | struct i915_address_space *vm, | |
2680 | uint32_t alignment, | |
2681 | uint64_t flags) | |
2682 | { | |
2683 | return i915_gem_object_pin_view(obj, vm, alignment, flags, | |
2684 | &i915_ggtt_view_normal); | |
2685 | } | |
2686 | ||
2687 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
2688 | u32 flags); | |
2689 | int __must_check i915_vma_unbind(struct i915_vma *vma); | |
2690 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); | |
2691 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); | |
2692 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); | |
2693 | ||
2694 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
2695 | int *needs_clflush); | |
2696 | ||
2697 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); | |
2698 | static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) | |
2699 | { | |
2700 | struct sg_page_iter sg_iter; | |
2701 | ||
2702 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) | |
2703 | return sg_page_iter_page(&sg_iter); | |
2704 | ||
2705 | return NULL; | |
2706 | } | |
2707 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) | |
2708 | { | |
2709 | BUG_ON(obj->pages == NULL); | |
2710 | obj->pages_pin_count++; | |
2711 | } | |
2712 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
2713 | { | |
2714 | BUG_ON(obj->pages_pin_count == 0); | |
2715 | obj->pages_pin_count--; | |
2716 | } | |
2717 | ||
2718 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); | |
2719 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2720 | struct intel_engine_cs *to); | |
2721 | void i915_vma_move_to_active(struct i915_vma *vma, | |
2722 | struct intel_engine_cs *ring); | |
2723 | int i915_gem_dumb_create(struct drm_file *file_priv, | |
2724 | struct drm_device *dev, | |
2725 | struct drm_mode_create_dumb *args); | |
2726 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, | |
2727 | uint32_t handle, uint64_t *offset); | |
2728 | /** | |
2729 | * Returns true if seq1 is later than seq2. | |
2730 | */ | |
2731 | static inline bool | |
2732 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
2733 | { | |
2734 | return (int32_t)(seq1 - seq2) >= 0; | |
2735 | } | |
2736 | ||
2737 | static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req, | |
2738 | bool lazy_coherency) | |
2739 | { | |
2740 | u32 seqno; | |
2741 | ||
2742 | BUG_ON(req == NULL); | |
2743 | ||
2744 | seqno = req->ring->get_seqno(req->ring, lazy_coherency); | |
2745 | ||
2746 | return i915_seqno_passed(seqno, req->seqno); | |
2747 | } | |
2748 | ||
2749 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); | |
2750 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); | |
2751 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); | |
2752 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); | |
2753 | ||
2754 | bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); | |
2755 | void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); | |
2756 | ||
2757 | struct drm_i915_gem_request * | |
2758 | i915_gem_find_active_request(struct intel_engine_cs *ring); | |
2759 | ||
2760 | bool i915_gem_retire_requests(struct drm_device *dev); | |
2761 | void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); | |
2762 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, | |
2763 | bool interruptible); | |
2764 | int __must_check i915_gem_check_olr(struct drm_i915_gem_request *req); | |
2765 | ||
2766 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) | |
2767 | { | |
2768 | return unlikely(atomic_read(&error->reset_counter) | |
2769 | & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); | |
2770 | } | |
2771 | ||
2772 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) | |
2773 | { | |
2774 | return atomic_read(&error->reset_counter) & I915_WEDGED; | |
2775 | } | |
2776 | ||
2777 | static inline u32 i915_reset_count(struct i915_gpu_error *error) | |
2778 | { | |
2779 | return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; | |
2780 | } | |
2781 | ||
2782 | static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) | |
2783 | { | |
2784 | return dev_priv->gpu_error.stop_rings == 0 || | |
2785 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN; | |
2786 | } | |
2787 | ||
2788 | static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv) | |
2789 | { | |
2790 | return dev_priv->gpu_error.stop_rings == 0 || | |
2791 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN; | |
2792 | } | |
2793 | ||
2794 | void i915_gem_reset(struct drm_device *dev); | |
2795 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); | |
2796 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); | |
2797 | int __must_check i915_gem_init(struct drm_device *dev); | |
2798 | int i915_gem_init_rings(struct drm_device *dev); | |
2799 | int __must_check i915_gem_init_hw(struct drm_device *dev); | |
2800 | int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice); | |
2801 | void i915_gem_init_swizzling(struct drm_device *dev); | |
2802 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); | |
2803 | int __must_check i915_gpu_idle(struct drm_device *dev); | |
2804 | int __must_check i915_gem_suspend(struct drm_device *dev); | |
2805 | int __i915_add_request(struct intel_engine_cs *ring, | |
2806 | struct drm_file *file, | |
2807 | struct drm_i915_gem_object *batch_obj); | |
2808 | #define i915_add_request(ring) \ | |
2809 | __i915_add_request(ring, NULL, NULL) | |
2810 | int __i915_wait_request(struct drm_i915_gem_request *req, | |
2811 | unsigned reset_counter, | |
2812 | bool interruptible, | |
2813 | s64 *timeout, | |
2814 | struct drm_i915_file_private *file_priv); | |
2815 | int __must_check i915_wait_request(struct drm_i915_gem_request *req); | |
2816 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); | |
2817 | int __must_check | |
2818 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, | |
2819 | bool write); | |
2820 | int __must_check | |
2821 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); | |
2822 | int __must_check | |
2823 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, | |
2824 | u32 alignment, | |
2825 | struct intel_engine_cs *pipelined); | |
2826 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj); | |
2827 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
2828 | int align); | |
2829 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); | |
2830 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); | |
2831 | ||
2832 | uint32_t | |
2833 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); | |
2834 | uint32_t | |
2835 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
2836 | int tiling_mode, bool fenced); | |
2837 | ||
2838 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, | |
2839 | enum i915_cache_level cache_level); | |
2840 | ||
2841 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, | |
2842 | struct dma_buf *dma_buf); | |
2843 | ||
2844 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
2845 | struct drm_gem_object *gem_obj, int flags); | |
2846 | ||
2847 | void i915_gem_restore_fences(struct drm_device *dev); | |
2848 | ||
2849 | unsigned long i915_gem_obj_offset_view(struct drm_i915_gem_object *o, | |
2850 | struct i915_address_space *vm, | |
2851 | enum i915_ggtt_view_type view); | |
2852 | static inline | |
2853 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
2854 | struct i915_address_space *vm) | |
2855 | { | |
2856 | return i915_gem_obj_offset_view(o, vm, I915_GGTT_VIEW_NORMAL); | |
2857 | } | |
2858 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); | |
2859 | bool i915_gem_obj_bound_view(struct drm_i915_gem_object *o, | |
2860 | struct i915_address_space *vm, | |
2861 | enum i915_ggtt_view_type view); | |
2862 | static inline | |
2863 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
2864 | struct i915_address_space *vm) | |
2865 | { | |
2866 | return i915_gem_obj_bound_view(o, vm, I915_GGTT_VIEW_NORMAL); | |
2867 | } | |
2868 | ||
2869 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
2870 | struct i915_address_space *vm); | |
2871 | struct i915_vma *i915_gem_obj_to_vma_view(struct drm_i915_gem_object *obj, | |
2872 | struct i915_address_space *vm, | |
2873 | const struct i915_ggtt_view *view); | |
2874 | static inline | |
2875 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, | |
2876 | struct i915_address_space *vm) | |
2877 | { | |
2878 | return i915_gem_obj_to_vma_view(obj, vm, &i915_ggtt_view_normal); | |
2879 | } | |
2880 | ||
2881 | struct i915_vma * | |
2882 | i915_gem_obj_lookup_or_create_vma_view(struct drm_i915_gem_object *obj, | |
2883 | struct i915_address_space *vm, | |
2884 | const struct i915_ggtt_view *view); | |
2885 | ||
2886 | static inline | |
2887 | struct i915_vma * | |
2888 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
2889 | struct i915_address_space *vm) | |
2890 | { | |
2891 | return i915_gem_obj_lookup_or_create_vma_view(obj, vm, | |
2892 | &i915_ggtt_view_normal); | |
2893 | } | |
2894 | ||
2895 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj); | |
2896 | static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) { | |
2897 | struct i915_vma *vma; | |
2898 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
2899 | if (vma->pin_count > 0) | |
2900 | return true; | |
2901 | return false; | |
2902 | } | |
2903 | ||
2904 | /* Some GGTT VM helpers */ | |
2905 | #define i915_obj_to_ggtt(obj) \ | |
2906 | (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) | |
2907 | static inline bool i915_is_ggtt(struct i915_address_space *vm) | |
2908 | { | |
2909 | struct i915_address_space *ggtt = | |
2910 | &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; | |
2911 | return vm == ggtt; | |
2912 | } | |
2913 | ||
2914 | static inline struct i915_hw_ppgtt * | |
2915 | i915_vm_to_ppgtt(struct i915_address_space *vm) | |
2916 | { | |
2917 | WARN_ON(i915_is_ggtt(vm)); | |
2918 | ||
2919 | return container_of(vm, struct i915_hw_ppgtt, base); | |
2920 | } | |
2921 | ||
2922 | ||
2923 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) | |
2924 | { | |
2925 | return i915_gem_obj_bound(obj, i915_obj_to_ggtt(obj)); | |
2926 | } | |
2927 | ||
2928 | static inline unsigned long | |
2929 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj) | |
2930 | { | |
2931 | return i915_gem_obj_offset(obj, i915_obj_to_ggtt(obj)); | |
2932 | } | |
2933 | ||
2934 | static inline unsigned long | |
2935 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) | |
2936 | { | |
2937 | return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj)); | |
2938 | } | |
2939 | ||
2940 | static inline int __must_check | |
2941 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, | |
2942 | uint32_t alignment, | |
2943 | unsigned flags) | |
2944 | { | |
2945 | return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj), | |
2946 | alignment, flags | PIN_GLOBAL); | |
2947 | } | |
2948 | ||
2949 | static inline int | |
2950 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) | |
2951 | { | |
2952 | return i915_vma_unbind(i915_gem_obj_to_ggtt(obj)); | |
2953 | } | |
2954 | ||
2955 | void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj); | |
2956 | ||
2957 | /* i915_gem_context.c */ | |
2958 | int __must_check i915_gem_context_init(struct drm_device *dev); | |
2959 | void i915_gem_context_fini(struct drm_device *dev); | |
2960 | void i915_gem_context_reset(struct drm_device *dev); | |
2961 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); | |
2962 | int i915_gem_context_enable(struct drm_i915_private *dev_priv); | |
2963 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); | |
2964 | int i915_switch_context(struct intel_engine_cs *ring, | |
2965 | struct intel_context *to); | |
2966 | struct intel_context * | |
2967 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); | |
2968 | void i915_gem_context_free(struct kref *ctx_ref); | |
2969 | struct drm_i915_gem_object * | |
2970 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); | |
2971 | static inline void i915_gem_context_reference(struct intel_context *ctx) | |
2972 | { | |
2973 | kref_get(&ctx->ref); | |
2974 | } | |
2975 | ||
2976 | static inline void i915_gem_context_unreference(struct intel_context *ctx) | |
2977 | { | |
2978 | kref_put(&ctx->ref, i915_gem_context_free); | |
2979 | } | |
2980 | ||
2981 | static inline bool i915_gem_context_is_default(const struct intel_context *c) | |
2982 | { | |
2983 | return c->user_handle == DEFAULT_CONTEXT_HANDLE; | |
2984 | } | |
2985 | ||
2986 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, | |
2987 | struct drm_file *file); | |
2988 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
2989 | struct drm_file *file); | |
2990 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, | |
2991 | struct drm_file *file_priv); | |
2992 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
2993 | struct drm_file *file_priv); | |
2994 | ||
2995 | /* i915_gem_evict.c */ | |
2996 | int __must_check i915_gem_evict_something(struct drm_device *dev, | |
2997 | struct i915_address_space *vm, | |
2998 | int min_size, | |
2999 | unsigned alignment, | |
3000 | unsigned cache_level, | |
3001 | unsigned long start, | |
3002 | unsigned long end, | |
3003 | unsigned flags); | |
3004 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); | |
3005 | int i915_gem_evict_everything(struct drm_device *dev); | |
3006 | ||
3007 | /* belongs in i915_gem_gtt.h */ | |
3008 | static inline void i915_gem_chipset_flush(struct drm_device *dev) | |
3009 | { | |
3010 | if (INTEL_INFO(dev)->gen < 6) | |
3011 | intel_gtt_chipset_flush(); | |
3012 | } | |
3013 | ||
3014 | /* i915_gem_stolen.c */ | |
3015 | int i915_gem_init_stolen(struct drm_device *dev); | |
3016 | int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp); | |
3017 | void i915_gem_stolen_cleanup_compression(struct drm_device *dev); | |
3018 | void i915_gem_cleanup_stolen(struct drm_device *dev); | |
3019 | struct drm_i915_gem_object * | |
3020 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
3021 | struct drm_i915_gem_object * | |
3022 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, | |
3023 | u32 stolen_offset, | |
3024 | u32 gtt_offset, | |
3025 | u32 size); | |
3026 | ||
3027 | /* i915_gem_tiling.c */ | |
3028 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) | |
3029 | { | |
3030 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
3031 | ||
3032 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
3033 | obj->tiling_mode != I915_TILING_NONE; | |
3034 | } | |
3035 | ||
3036 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); | |
3037 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
3038 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
3039 | ||
3040 | /* i915_gem_debug.c */ | |
3041 | #if WATCH_LISTS | |
3042 | int i915_verify_lists(struct drm_device *dev); | |
3043 | #else | |
3044 | #define i915_verify_lists(dev) 0 | |
3045 | #endif | |
3046 | ||
3047 | /* i915_debugfs.c */ | |
3048 | int i915_debugfs_init(struct drm_minor *minor); | |
3049 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
3050 | #ifdef CONFIG_DEBUG_FS | |
3051 | void intel_display_crc_init(struct drm_device *dev); | |
3052 | #else | |
3053 | static inline void intel_display_crc_init(struct drm_device *dev) {} | |
3054 | #endif | |
3055 | ||
3056 | /* i915_gpu_error.c */ | |
3057 | __printf(2, 3) | |
3058 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
3059 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, | |
3060 | const struct i915_error_state_file_priv *error); | |
3061 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, | |
3062 | struct drm_i915_private *i915, | |
3063 | size_t count, loff_t pos); | |
3064 | static inline void i915_error_state_buf_release( | |
3065 | struct drm_i915_error_state_buf *eb) | |
3066 | { | |
3067 | kfree(eb->buf); | |
3068 | } | |
3069 | void i915_capture_error_state(struct drm_device *dev, bool wedge, | |
3070 | const char *error_msg); | |
3071 | void i915_error_state_get(struct drm_device *dev, | |
3072 | struct i915_error_state_file_priv *error_priv); | |
3073 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); | |
3074 | void i915_destroy_error_state(struct drm_device *dev); | |
3075 | ||
3076 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); | |
3077 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type); | |
3078 | ||
3079 | /* i915_gem_batch_pool.c */ | |
3080 | void i915_gem_batch_pool_init(struct drm_device *dev, | |
3081 | struct i915_gem_batch_pool *pool); | |
3082 | void i915_gem_batch_pool_fini(struct i915_gem_batch_pool *pool); | |
3083 | struct drm_i915_gem_object* | |
3084 | i915_gem_batch_pool_get(struct i915_gem_batch_pool *pool, size_t size); | |
3085 | ||
3086 | /* i915_cmd_parser.c */ | |
3087 | int i915_cmd_parser_get_version(void); | |
3088 | int i915_cmd_parser_init_ring(struct intel_engine_cs *ring); | |
3089 | void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring); | |
3090 | bool i915_needs_cmd_parser(struct intel_engine_cs *ring); | |
3091 | int i915_parse_cmds(struct intel_engine_cs *ring, | |
3092 | struct drm_i915_gem_object *batch_obj, | |
3093 | struct drm_i915_gem_object *shadow_batch_obj, | |
3094 | u32 batch_start_offset, | |
3095 | u32 batch_len, | |
3096 | bool is_master); | |
3097 | ||
3098 | /* i915_suspend.c */ | |
3099 | extern int i915_save_state(struct drm_device *dev); | |
3100 | extern int i915_restore_state(struct drm_device *dev); | |
3101 | ||
3102 | /* i915_ums.c */ | |
3103 | void i915_save_display_reg(struct drm_device *dev); | |
3104 | void i915_restore_display_reg(struct drm_device *dev); | |
3105 | ||
3106 | /* i915_sysfs.c */ | |
3107 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
3108 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
3109 | ||
3110 | /* intel_i2c.c */ | |
3111 | extern int intel_setup_gmbus(struct drm_device *dev); | |
3112 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
3113 | static inline bool intel_gmbus_is_port_valid(unsigned port) | |
3114 | { | |
3115 | return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); | |
3116 | } | |
3117 | ||
3118 | extern struct i2c_adapter *intel_gmbus_get_adapter( | |
3119 | struct drm_i915_private *dev_priv, unsigned port); | |
3120 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); | |
3121 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
3122 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) | |
3123 | { | |
3124 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
3125 | } | |
3126 | extern void intel_i2c_reset(struct drm_device *dev); | |
3127 | ||
3128 | /* intel_opregion.c */ | |
3129 | #ifdef CONFIG_ACPI | |
3130 | extern int intel_opregion_setup(struct drm_device *dev); | |
3131 | extern void intel_opregion_init(struct drm_device *dev); | |
3132 | extern void intel_opregion_fini(struct drm_device *dev); | |
3133 | extern void intel_opregion_asle_intr(struct drm_device *dev); | |
3134 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, | |
3135 | bool enable); | |
3136 | extern int intel_opregion_notify_adapter(struct drm_device *dev, | |
3137 | pci_power_t state); | |
3138 | #else | |
3139 | static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } | |
3140 | static inline void intel_opregion_init(struct drm_device *dev) { return; } | |
3141 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3142 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } | |
3143 | static inline int | |
3144 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) | |
3145 | { | |
3146 | return 0; | |
3147 | } | |
3148 | static inline int | |
3149 | intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) | |
3150 | { | |
3151 | return 0; | |
3152 | } | |
3153 | #endif | |
3154 | ||
3155 | /* intel_acpi.c */ | |
3156 | #ifdef CONFIG_ACPI | |
3157 | extern void intel_register_dsm_handler(void); | |
3158 | extern void intel_unregister_dsm_handler(void); | |
3159 | #else | |
3160 | static inline void intel_register_dsm_handler(void) { return; } | |
3161 | static inline void intel_unregister_dsm_handler(void) { return; } | |
3162 | #endif /* CONFIG_ACPI */ | |
3163 | ||
3164 | /* modesetting */ | |
3165 | extern void intel_modeset_init_hw(struct drm_device *dev); | |
3166 | extern void intel_modeset_init(struct drm_device *dev); | |
3167 | extern void intel_modeset_gem_init(struct drm_device *dev); | |
3168 | extern void intel_modeset_cleanup(struct drm_device *dev); | |
3169 | extern void intel_connector_unregister(struct intel_connector *); | |
3170 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); | |
3171 | extern void intel_modeset_setup_hw_state(struct drm_device *dev, | |
3172 | bool force_restore); | |
3173 | extern void i915_redisable_vga(struct drm_device *dev); | |
3174 | extern void i915_redisable_vga_power_on(struct drm_device *dev); | |
3175 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); | |
3176 | extern void intel_init_pch_refclk(struct drm_device *dev); | |
3177 | extern void gen6_set_rps(struct drm_device *dev, u8 val); | |
3178 | extern void valleyview_set_rps(struct drm_device *dev, u8 val); | |
3179 | extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, | |
3180 | bool enable); | |
3181 | extern void intel_detect_pch(struct drm_device *dev); | |
3182 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); | |
3183 | extern int intel_enable_rc6(const struct drm_device *dev); | |
3184 | ||
3185 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); | |
3186 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, | |
3187 | struct drm_file *file); | |
3188 | int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, | |
3189 | struct drm_file *file); | |
3190 | ||
3191 | void intel_notify_mmio_flip(struct intel_engine_cs *ring); | |
3192 | ||
3193 | /* overlay */ | |
3194 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); | |
3195 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, | |
3196 | struct intel_overlay_error_state *error); | |
3197 | ||
3198 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
3199 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, | |
3200 | struct drm_device *dev, | |
3201 | struct intel_display_error_state *error); | |
3202 | ||
3203 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); | |
3204 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); | |
3205 | ||
3206 | /* intel_sideband.c */ | |
3207 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); | |
3208 | void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); | |
3209 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); | |
3210 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); | |
3211 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3212 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); | |
3213 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3214 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
3215 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3216 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); | |
3217 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3218 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); | |
3219 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3220 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); | |
3221 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
3222 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, | |
3223 | enum intel_sbi_destination destination); | |
3224 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
3225 | enum intel_sbi_destination destination); | |
3226 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); | |
3227 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3228 | ||
3229 | int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val); | |
3230 | int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val); | |
3231 | ||
3232 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) | |
3233 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
3234 | ||
3235 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
3236 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
3237 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
3238 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
3239 | ||
3240 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
3241 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
3242 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
3243 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
3244 | ||
3245 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they | |
3246 | * will be implemented using 2 32-bit writes in an arbitrary order with | |
3247 | * an arbitrary delay between them. This can cause the hardware to | |
3248 | * act upon the intermediate value, possibly leading to corruption and | |
3249 | * machine death. You have been warned. | |
3250 | */ | |
3251 | #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) | |
3252 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) | |
3253 | ||
3254 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ | |
3255 | u32 upper = I915_READ(upper_reg); \ | |
3256 | u32 lower = I915_READ(lower_reg); \ | |
3257 | u32 tmp = I915_READ(upper_reg); \ | |
3258 | if (upper != tmp) { \ | |
3259 | upper = tmp; \ | |
3260 | lower = I915_READ(lower_reg); \ | |
3261 | WARN_ON(I915_READ(upper_reg) != upper); \ | |
3262 | } \ | |
3263 | (u64)upper << 32 | lower; }) | |
3264 | ||
3265 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) | |
3266 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
3267 | ||
3268 | /* "Broadcast RGB" property */ | |
3269 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
3270 | #define INTEL_BROADCAST_RGB_FULL 1 | |
3271 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
3272 | ||
3273 | static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) | |
3274 | { | |
3275 | if (IS_VALLEYVIEW(dev)) | |
3276 | return VLV_VGACNTRL; | |
3277 | else if (INTEL_INFO(dev)->gen >= 5) | |
3278 | return CPU_VGACNTRL; | |
3279 | else | |
3280 | return VGACNTRL; | |
3281 | } | |
3282 | ||
3283 | static inline void __user *to_user_ptr(u64 address) | |
3284 | { | |
3285 | return (void __user *)(uintptr_t)address; | |
3286 | } | |
3287 | ||
3288 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) | |
3289 | { | |
3290 | unsigned long j = msecs_to_jiffies(m); | |
3291 | ||
3292 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3293 | } | |
3294 | ||
3295 | static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) | |
3296 | { | |
3297 | return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); | |
3298 | } | |
3299 | ||
3300 | static inline unsigned long | |
3301 | timespec_to_jiffies_timeout(const struct timespec *value) | |
3302 | { | |
3303 | unsigned long j = timespec_to_jiffies(value); | |
3304 | ||
3305 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3306 | } | |
3307 | ||
3308 | /* | |
3309 | * If you need to wait X milliseconds between events A and B, but event B | |
3310 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of | |
3311 | * when event A happened, then just before event B you call this function and | |
3312 | * pass the timestamp as the first argument, and X as the second argument. | |
3313 | */ | |
3314 | static inline void | |
3315 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) | |
3316 | { | |
3317 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; | |
3318 | ||
3319 | /* | |
3320 | * Don't re-read the value of "jiffies" every time since it may change | |
3321 | * behind our back and break the math. | |
3322 | */ | |
3323 | tmp_jiffies = jiffies; | |
3324 | target_jiffies = timestamp_jiffies + | |
3325 | msecs_to_jiffies_timeout(to_wait_ms); | |
3326 | ||
3327 | if (time_after(target_jiffies, tmp_jiffies)) { | |
3328 | remaining_jiffies = target_jiffies - tmp_jiffies; | |
3329 | while (remaining_jiffies) | |
3330 | remaining_jiffies = | |
3331 | schedule_timeout_uninterruptible(remaining_jiffies); | |
3332 | } | |
3333 | } | |
3334 | ||
3335 | static inline void i915_trace_irq_get(struct intel_engine_cs *ring, | |
3336 | struct drm_i915_gem_request *req) | |
3337 | { | |
3338 | if (ring->trace_irq_req == NULL && ring->irq_get(ring)) | |
3339 | i915_gem_request_assign(&ring->trace_irq_req, req); | |
3340 | } | |
3341 | ||
3342 | #endif |