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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_drv.h
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1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include "i915_reg.h"
34#include "intel_bios.h"
35#include "intel_ringbuffer.h"
36#include <linux/io-mapping.h>
37#include <linux/i2c.h>
38#include <drm/intel-gtt.h>
39#include <linux/backlight.h>
40
41/* General customization:
42 */
43
44#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
45
46#define DRIVER_NAME "i915"
47#define DRIVER_DESC "Intel Graphics"
48#define DRIVER_DATE "20080730"
49
50enum pipe {
51 PIPE_A = 0,
52 PIPE_B,
53 PIPE_C,
54 I915_MAX_PIPES
55};
56#define pipe_name(p) ((p) + 'A')
57
58enum plane {
59 PLANE_A = 0,
60 PLANE_B,
61 PLANE_C,
62};
63#define plane_name(p) ((p) + 'A')
64
65#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
66
67#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
68
69/* Interface history:
70 *
71 * 1.1: Original.
72 * 1.2: Add Power Management
73 * 1.3: Add vblank support
74 * 1.4: Fix cmdbuffer path, add heap destroy
75 * 1.5: Add vblank pipe configuration
76 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
77 * - Support vertical blank on secondary display pipe
78 */
79#define DRIVER_MAJOR 1
80#define DRIVER_MINOR 6
81#define DRIVER_PATCHLEVEL 0
82
83#define WATCH_COHERENCY 0
84#define WATCH_LISTS 0
85
86#define I915_GEM_PHYS_CURSOR_0 1
87#define I915_GEM_PHYS_CURSOR_1 2
88#define I915_GEM_PHYS_OVERLAY_REGS 3
89#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
90
91struct drm_i915_gem_phys_object {
92 int id;
93 struct page **page_list;
94 drm_dma_handle_t *handle;
95 struct drm_i915_gem_object *cur_obj;
96};
97
98struct mem_block {
99 struct mem_block *next;
100 struct mem_block *prev;
101 int start;
102 int size;
103 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
104};
105
106struct opregion_header;
107struct opregion_acpi;
108struct opregion_swsci;
109struct opregion_asle;
110struct drm_i915_private;
111
112struct intel_opregion {
113 struct opregion_header *header;
114 struct opregion_acpi *acpi;
115 struct opregion_swsci *swsci;
116 struct opregion_asle *asle;
117 void *vbt;
118 u32 __iomem *lid_state;
119};
120#define OPREGION_SIZE (8*1024)
121
122struct intel_overlay;
123struct intel_overlay_error_state;
124
125struct drm_i915_master_private {
126 drm_local_map_t *sarea;
127 struct _drm_i915_sarea *sarea_priv;
128};
129#define I915_FENCE_REG_NONE -1
130#define I915_MAX_NUM_FENCES 16
131/* 16 fences + sign bit for FENCE_REG_NONE */
132#define I915_MAX_NUM_FENCE_BITS 5
133
134struct drm_i915_fence_reg {
135 struct list_head lru_list;
136 struct drm_i915_gem_object *obj;
137 uint32_t setup_seqno;
138};
139
140struct sdvo_device_mapping {
141 u8 initialized;
142 u8 dvo_port;
143 u8 slave_addr;
144 u8 dvo_wiring;
145 u8 i2c_pin;
146 u8 ddc_pin;
147};
148
149struct intel_display_error_state;
150
151struct drm_i915_error_state {
152 u32 eir;
153 u32 pgtbl_er;
154 u32 pipestat[I915_MAX_PIPES];
155 u32 ipeir;
156 u32 ipehr;
157 u32 instdone;
158 u32 acthd;
159 u32 error; /* gen6+ */
160 u32 bcs_acthd; /* gen6+ blt engine */
161 u32 bcs_ipehr;
162 u32 bcs_ipeir;
163 u32 bcs_instdone;
164 u32 bcs_seqno;
165 u32 vcs_acthd; /* gen6+ bsd engine */
166 u32 vcs_ipehr;
167 u32 vcs_ipeir;
168 u32 vcs_instdone;
169 u32 vcs_seqno;
170 u32 instpm;
171 u32 instps;
172 u32 instdone1;
173 u32 seqno;
174 u64 bbaddr;
175 u64 fence[I915_MAX_NUM_FENCES];
176 struct timeval time;
177 struct drm_i915_error_object {
178 int page_count;
179 u32 gtt_offset;
180 u32 *pages[0];
181 } *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS];
182 struct drm_i915_error_buffer {
183 u32 size;
184 u32 name;
185 u32 seqno;
186 u32 gtt_offset;
187 u32 read_domains;
188 u32 write_domain;
189 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
190 s32 pinned:2;
191 u32 tiling:2;
192 u32 dirty:1;
193 u32 purgeable:1;
194 u32 ring:4;
195 u32 cache_level:2;
196 } *active_bo, *pinned_bo;
197 u32 active_bo_count, pinned_bo_count;
198 struct intel_overlay_error_state *overlay;
199 struct intel_display_error_state *display;
200};
201
202struct drm_i915_display_funcs {
203 void (*dpms)(struct drm_crtc *crtc, int mode);
204 bool (*fbc_enabled)(struct drm_device *dev);
205 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
206 void (*disable_fbc)(struct drm_device *dev);
207 int (*get_display_clock_speed)(struct drm_device *dev);
208 int (*get_fifo_size)(struct drm_device *dev, int plane);
209 void (*update_wm)(struct drm_device *dev);
210 int (*crtc_mode_set)(struct drm_crtc *crtc,
211 struct drm_display_mode *mode,
212 struct drm_display_mode *adjusted_mode,
213 int x, int y,
214 struct drm_framebuffer *old_fb);
215 void (*write_eld)(struct drm_connector *connector,
216 struct drm_crtc *crtc);
217 void (*fdi_link_train)(struct drm_crtc *crtc);
218 void (*init_clock_gating)(struct drm_device *dev);
219 void (*init_pch_clock_gating)(struct drm_device *dev);
220 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
221 struct drm_framebuffer *fb,
222 struct drm_i915_gem_object *obj);
223 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
224 int x, int y);
225 void (*force_wake_get)(struct drm_i915_private *dev_priv);
226 void (*force_wake_put)(struct drm_i915_private *dev_priv);
227 /* clock updates for mode set */
228 /* cursor updates */
229 /* render clock increase/decrease */
230 /* display clock increase/decrease */
231 /* pll clock increase/decrease */
232};
233
234struct intel_device_info {
235 u8 gen;
236 u8 is_mobile:1;
237 u8 is_i85x:1;
238 u8 is_i915g:1;
239 u8 is_i945gm:1;
240 u8 is_g33:1;
241 u8 need_gfx_hws:1;
242 u8 is_g4x:1;
243 u8 is_pineview:1;
244 u8 is_broadwater:1;
245 u8 is_crestline:1;
246 u8 is_ivybridge:1;
247 u8 has_fbc:1;
248 u8 has_pipe_cxsr:1;
249 u8 has_hotplug:1;
250 u8 cursor_needs_physical:1;
251 u8 has_overlay:1;
252 u8 overlay_needs_physical:1;
253 u8 supports_tv:1;
254 u8 has_bsd_ring:1;
255 u8 has_blt_ring:1;
256};
257
258enum no_fbc_reason {
259 FBC_NO_OUTPUT, /* no outputs enabled to compress */
260 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
261 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
262 FBC_MODE_TOO_LARGE, /* mode too large for compression */
263 FBC_BAD_PLANE, /* fbc not supported on plane */
264 FBC_NOT_TILED, /* buffer not tiled */
265 FBC_MULTIPLE_PIPES, /* more than one pipe active */
266 FBC_MODULE_PARAM,
267};
268
269enum intel_pch {
270 PCH_IBX, /* Ibexpeak PCH */
271 PCH_CPT, /* Cougarpoint PCH */
272};
273
274#define QUIRK_PIPEA_FORCE (1<<0)
275#define QUIRK_LVDS_SSC_DISABLE (1<<1)
276
277struct intel_fbdev;
278struct intel_fbc_work;
279
280typedef struct drm_i915_private {
281 struct drm_device *dev;
282
283 const struct intel_device_info *info;
284
285 int has_gem;
286 int relative_constants_mode;
287
288 void __iomem *regs;
289 u32 gt_fifo_count;
290
291 struct intel_gmbus {
292 struct i2c_adapter adapter;
293 struct i2c_adapter *force_bit;
294 u32 reg0;
295 } *gmbus;
296
297 struct pci_dev *bridge_dev;
298 struct intel_ring_buffer ring[I915_NUM_RINGS];
299 uint32_t next_seqno;
300
301 drm_dma_handle_t *status_page_dmah;
302 uint32_t counter;
303 drm_local_map_t hws_map;
304 struct drm_i915_gem_object *pwrctx;
305 struct drm_i915_gem_object *renderctx;
306
307 struct resource mch_res;
308
309 unsigned int cpp;
310 int back_offset;
311 int front_offset;
312 int current_page;
313 int page_flipping;
314
315 atomic_t irq_received;
316
317 /* protects the irq masks */
318 spinlock_t irq_lock;
319 /** Cached value of IMR to avoid reads in updating the bitfield */
320 u32 pipestat[2];
321 u32 irq_mask;
322 u32 gt_irq_mask;
323 u32 pch_irq_mask;
324
325 u32 hotplug_supported_mask;
326 struct work_struct hotplug_work;
327
328 int tex_lru_log_granularity;
329 int allow_batchbuffer;
330 struct mem_block *agp_heap;
331 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
332 int vblank_pipe;
333 int num_pipe;
334
335 /* For hangcheck timer */
336#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
337 struct timer_list hangcheck_timer;
338 int hangcheck_count;
339 uint32_t last_acthd;
340 uint32_t last_instdone;
341 uint32_t last_instdone1;
342
343 unsigned long cfb_size;
344 unsigned int cfb_fb;
345 enum plane cfb_plane;
346 int cfb_y;
347 struct intel_fbc_work *fbc_work;
348
349 struct intel_opregion opregion;
350
351 /* overlay */
352 struct intel_overlay *overlay;
353
354 /* LVDS info */
355 int backlight_level; /* restore backlight to this value */
356 bool backlight_enabled;
357 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
358 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
359
360 /* Feature bits from the VBIOS */
361 unsigned int int_tv_support:1;
362 unsigned int lvds_dither:1;
363 unsigned int lvds_vbt:1;
364 unsigned int int_crt_support:1;
365 unsigned int lvds_use_ssc:1;
366 unsigned int display_clock_mode:1;
367 int lvds_ssc_freq;
368 struct {
369 int rate;
370 int lanes;
371 int preemphasis;
372 int vswing;
373
374 bool initialized;
375 bool support;
376 int bpp;
377 struct edp_power_seq pps;
378 } edp;
379 bool no_aux_handshake;
380
381 struct notifier_block lid_notifier;
382
383 int crt_ddc_pin;
384 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
385 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
386 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
387
388 unsigned int fsb_freq, mem_freq, is_ddr3;
389
390 spinlock_t error_lock;
391 struct drm_i915_error_state *first_error;
392 struct work_struct error_work;
393 struct completion error_completion;
394 struct workqueue_struct *wq;
395
396 /* Display functions */
397 struct drm_i915_display_funcs display;
398
399 /* PCH chipset type */
400 enum intel_pch pch_type;
401
402 unsigned long quirks;
403
404 /* Register state */
405 bool modeset_on_lid;
406 u8 saveLBB;
407 u32 saveDSPACNTR;
408 u32 saveDSPBCNTR;
409 u32 saveDSPARB;
410 u32 saveHWS;
411 u32 savePIPEACONF;
412 u32 savePIPEBCONF;
413 u32 savePIPEASRC;
414 u32 savePIPEBSRC;
415 u32 saveFPA0;
416 u32 saveFPA1;
417 u32 saveDPLL_A;
418 u32 saveDPLL_A_MD;
419 u32 saveHTOTAL_A;
420 u32 saveHBLANK_A;
421 u32 saveHSYNC_A;
422 u32 saveVTOTAL_A;
423 u32 saveVBLANK_A;
424 u32 saveVSYNC_A;
425 u32 saveBCLRPAT_A;
426 u32 saveTRANSACONF;
427 u32 saveTRANS_HTOTAL_A;
428 u32 saveTRANS_HBLANK_A;
429 u32 saveTRANS_HSYNC_A;
430 u32 saveTRANS_VTOTAL_A;
431 u32 saveTRANS_VBLANK_A;
432 u32 saveTRANS_VSYNC_A;
433 u32 savePIPEASTAT;
434 u32 saveDSPASTRIDE;
435 u32 saveDSPASIZE;
436 u32 saveDSPAPOS;
437 u32 saveDSPAADDR;
438 u32 saveDSPASURF;
439 u32 saveDSPATILEOFF;
440 u32 savePFIT_PGM_RATIOS;
441 u32 saveBLC_HIST_CTL;
442 u32 saveBLC_PWM_CTL;
443 u32 saveBLC_PWM_CTL2;
444 u32 saveBLC_CPU_PWM_CTL;
445 u32 saveBLC_CPU_PWM_CTL2;
446 u32 saveFPB0;
447 u32 saveFPB1;
448 u32 saveDPLL_B;
449 u32 saveDPLL_B_MD;
450 u32 saveHTOTAL_B;
451 u32 saveHBLANK_B;
452 u32 saveHSYNC_B;
453 u32 saveVTOTAL_B;
454 u32 saveVBLANK_B;
455 u32 saveVSYNC_B;
456 u32 saveBCLRPAT_B;
457 u32 saveTRANSBCONF;
458 u32 saveTRANS_HTOTAL_B;
459 u32 saveTRANS_HBLANK_B;
460 u32 saveTRANS_HSYNC_B;
461 u32 saveTRANS_VTOTAL_B;
462 u32 saveTRANS_VBLANK_B;
463 u32 saveTRANS_VSYNC_B;
464 u32 savePIPEBSTAT;
465 u32 saveDSPBSTRIDE;
466 u32 saveDSPBSIZE;
467 u32 saveDSPBPOS;
468 u32 saveDSPBADDR;
469 u32 saveDSPBSURF;
470 u32 saveDSPBTILEOFF;
471 u32 saveVGA0;
472 u32 saveVGA1;
473 u32 saveVGA_PD;
474 u32 saveVGACNTRL;
475 u32 saveADPA;
476 u32 saveLVDS;
477 u32 savePP_ON_DELAYS;
478 u32 savePP_OFF_DELAYS;
479 u32 saveDVOA;
480 u32 saveDVOB;
481 u32 saveDVOC;
482 u32 savePP_ON;
483 u32 savePP_OFF;
484 u32 savePP_CONTROL;
485 u32 savePP_DIVISOR;
486 u32 savePFIT_CONTROL;
487 u32 save_palette_a[256];
488 u32 save_palette_b[256];
489 u32 saveDPFC_CB_BASE;
490 u32 saveFBC_CFB_BASE;
491 u32 saveFBC_LL_BASE;
492 u32 saveFBC_CONTROL;
493 u32 saveFBC_CONTROL2;
494 u32 saveIER;
495 u32 saveIIR;
496 u32 saveIMR;
497 u32 saveDEIER;
498 u32 saveDEIMR;
499 u32 saveGTIER;
500 u32 saveGTIMR;
501 u32 saveFDI_RXA_IMR;
502 u32 saveFDI_RXB_IMR;
503 u32 saveCACHE_MODE_0;
504 u32 saveMI_ARB_STATE;
505 u32 saveSWF0[16];
506 u32 saveSWF1[16];
507 u32 saveSWF2[3];
508 u8 saveMSR;
509 u8 saveSR[8];
510 u8 saveGR[25];
511 u8 saveAR_INDEX;
512 u8 saveAR[21];
513 u8 saveDACMASK;
514 u8 saveCR[37];
515 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
516 u32 saveCURACNTR;
517 u32 saveCURAPOS;
518 u32 saveCURABASE;
519 u32 saveCURBCNTR;
520 u32 saveCURBPOS;
521 u32 saveCURBBASE;
522 u32 saveCURSIZE;
523 u32 saveDP_B;
524 u32 saveDP_C;
525 u32 saveDP_D;
526 u32 savePIPEA_GMCH_DATA_M;
527 u32 savePIPEB_GMCH_DATA_M;
528 u32 savePIPEA_GMCH_DATA_N;
529 u32 savePIPEB_GMCH_DATA_N;
530 u32 savePIPEA_DP_LINK_M;
531 u32 savePIPEB_DP_LINK_M;
532 u32 savePIPEA_DP_LINK_N;
533 u32 savePIPEB_DP_LINK_N;
534 u32 saveFDI_RXA_CTL;
535 u32 saveFDI_TXA_CTL;
536 u32 saveFDI_RXB_CTL;
537 u32 saveFDI_TXB_CTL;
538 u32 savePFA_CTL_1;
539 u32 savePFB_CTL_1;
540 u32 savePFA_WIN_SZ;
541 u32 savePFB_WIN_SZ;
542 u32 savePFA_WIN_POS;
543 u32 savePFB_WIN_POS;
544 u32 savePCH_DREF_CONTROL;
545 u32 saveDISP_ARB_CTL;
546 u32 savePIPEA_DATA_M1;
547 u32 savePIPEA_DATA_N1;
548 u32 savePIPEA_LINK_M1;
549 u32 savePIPEA_LINK_N1;
550 u32 savePIPEB_DATA_M1;
551 u32 savePIPEB_DATA_N1;
552 u32 savePIPEB_LINK_M1;
553 u32 savePIPEB_LINK_N1;
554 u32 saveMCHBAR_RENDER_STANDBY;
555 u32 savePCH_PORT_HOTPLUG;
556
557 struct {
558 /** Bridge to intel-gtt-ko */
559 const struct intel_gtt *gtt;
560 /** Memory allocator for GTT stolen memory */
561 struct drm_mm stolen;
562 /** Memory allocator for GTT */
563 struct drm_mm gtt_space;
564 /** List of all objects in gtt_space. Used to restore gtt
565 * mappings on resume */
566 struct list_head gtt_list;
567
568 /** Usable portion of the GTT for GEM */
569 unsigned long gtt_start;
570 unsigned long gtt_mappable_end;
571 unsigned long gtt_end;
572
573 struct io_mapping *gtt_mapping;
574 int gtt_mtrr;
575
576 struct shrinker inactive_shrinker;
577
578 /**
579 * List of objects currently involved in rendering.
580 *
581 * Includes buffers having the contents of their GPU caches
582 * flushed, not necessarily primitives. last_rendering_seqno
583 * represents when the rendering involved will be completed.
584 *
585 * A reference is held on the buffer while on this list.
586 */
587 struct list_head active_list;
588
589 /**
590 * List of objects which are not in the ringbuffer but which
591 * still have a write_domain which needs to be flushed before
592 * unbinding.
593 *
594 * last_rendering_seqno is 0 while an object is in this list.
595 *
596 * A reference is held on the buffer while on this list.
597 */
598 struct list_head flushing_list;
599
600 /**
601 * LRU list of objects which are not in the ringbuffer and
602 * are ready to unbind, but are still in the GTT.
603 *
604 * last_rendering_seqno is 0 while an object is in this list.
605 *
606 * A reference is not held on the buffer while on this list,
607 * as merely being GTT-bound shouldn't prevent its being
608 * freed, and we'll pull it off the list in the free path.
609 */
610 struct list_head inactive_list;
611
612 /**
613 * LRU list of objects which are not in the ringbuffer but
614 * are still pinned in the GTT.
615 */
616 struct list_head pinned_list;
617
618 /** LRU list of objects with fence regs on them. */
619 struct list_head fence_list;
620
621 /**
622 * List of objects currently pending being freed.
623 *
624 * These objects are no longer in use, but due to a signal
625 * we were prevented from freeing them at the appointed time.
626 */
627 struct list_head deferred_free_list;
628
629 /**
630 * We leave the user IRQ off as much as possible,
631 * but this means that requests will finish and never
632 * be retired once the system goes idle. Set a timer to
633 * fire periodically while the ring is running. When it
634 * fires, go retire requests.
635 */
636 struct delayed_work retire_work;
637
638 /**
639 * Are we in a non-interruptible section of code like
640 * modesetting?
641 */
642 bool interruptible;
643
644 /**
645 * Flag if the X Server, and thus DRM, is not currently in
646 * control of the device.
647 *
648 * This is set between LeaveVT and EnterVT. It needs to be
649 * replaced with a semaphore. It also needs to be
650 * transitioned away from for kernel modesetting.
651 */
652 int suspended;
653
654 /**
655 * Flag if the hardware appears to be wedged.
656 *
657 * This is set when attempts to idle the device timeout.
658 * It prevents command submission from occurring and makes
659 * every pending request fail
660 */
661 atomic_t wedged;
662
663 /** Bit 6 swizzling required for X tiling */
664 uint32_t bit_6_swizzle_x;
665 /** Bit 6 swizzling required for Y tiling */
666 uint32_t bit_6_swizzle_y;
667
668 /* storage for physical objects */
669 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
670
671 /* accounting, useful for userland debugging */
672 size_t gtt_total;
673 size_t mappable_gtt_total;
674 size_t object_memory;
675 u32 object_count;
676 } mm;
677 struct sdvo_device_mapping sdvo_mappings[2];
678 /* indicate whether the LVDS_BORDER should be enabled or not */
679 unsigned int lvds_border_bits;
680 /* Panel fitter placement and size for Ironlake+ */
681 u32 pch_pf_pos, pch_pf_size;
682
683 struct drm_crtc *plane_to_crtc_mapping[3];
684 struct drm_crtc *pipe_to_crtc_mapping[3];
685 wait_queue_head_t pending_flip_queue;
686 bool flip_pending_is_done;
687
688 /* Reclocking support */
689 bool render_reclock_avail;
690 bool lvds_downclock_avail;
691 /* indicates the reduced downclock for LVDS*/
692 int lvds_downclock;
693 struct work_struct idle_work;
694 struct timer_list idle_timer;
695 bool busy;
696 u16 orig_clock;
697 int child_dev_num;
698 struct child_device_config *child_dev;
699 struct drm_connector *int_lvds_connector;
700 struct drm_connector *int_edp_connector;
701
702 bool mchbar_need_disable;
703
704 struct work_struct rps_work;
705 spinlock_t rps_lock;
706 u32 pm_iir;
707
708 u8 cur_delay;
709 u8 min_delay;
710 u8 max_delay;
711 u8 fmax;
712 u8 fstart;
713
714 u64 last_count1;
715 unsigned long last_time1;
716 unsigned long chipset_power;
717 u64 last_count2;
718 struct timespec last_time2;
719 unsigned long gfx_power;
720 int c_m;
721 int r_t;
722 u8 corr;
723 spinlock_t *mchdev_lock;
724
725 enum no_fbc_reason no_fbc_reason;
726
727 struct drm_mm_node *compressed_fb;
728 struct drm_mm_node *compressed_llb;
729
730 unsigned long last_gpu_reset;
731
732 /* list of fbdev register on this device */
733 struct intel_fbdev *fbdev;
734
735 struct backlight_device *backlight;
736
737 struct drm_property *broadcast_rgb_property;
738 struct drm_property *force_audio_property;
739
740 atomic_t forcewake_count;
741} drm_i915_private_t;
742
743enum i915_cache_level {
744 I915_CACHE_NONE,
745 I915_CACHE_LLC,
746 I915_CACHE_LLC_MLC, /* gen6+ */
747};
748
749struct drm_i915_gem_object {
750 struct drm_gem_object base;
751
752 /** Current space allocated to this object in the GTT, if any. */
753 struct drm_mm_node *gtt_space;
754 struct list_head gtt_list;
755
756 /** This object's place on the active/flushing/inactive lists */
757 struct list_head ring_list;
758 struct list_head mm_list;
759 /** This object's place on GPU write list */
760 struct list_head gpu_write_list;
761 /** This object's place in the batchbuffer or on the eviction list */
762 struct list_head exec_list;
763
764 /**
765 * This is set if the object is on the active or flushing lists
766 * (has pending rendering), and is not set if it's on inactive (ready
767 * to be unbound).
768 */
769 unsigned int active:1;
770
771 /**
772 * This is set if the object has been written to since last bound
773 * to the GTT
774 */
775 unsigned int dirty:1;
776
777 /**
778 * This is set if the object has been written to since the last
779 * GPU flush.
780 */
781 unsigned int pending_gpu_write:1;
782
783 /**
784 * Fence register bits (if any) for this object. Will be set
785 * as needed when mapped into the GTT.
786 * Protected by dev->struct_mutex.
787 */
788 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
789
790 /**
791 * Advice: are the backing pages purgeable?
792 */
793 unsigned int madv:2;
794
795 /**
796 * Current tiling mode for the object.
797 */
798 unsigned int tiling_mode:2;
799 unsigned int tiling_changed:1;
800
801 /** How many users have pinned this object in GTT space. The following
802 * users can each hold at most one reference: pwrite/pread, pin_ioctl
803 * (via user_pin_count), execbuffer (objects are not allowed multiple
804 * times for the same batchbuffer), and the framebuffer code. When
805 * switching/pageflipping, the framebuffer code has at most two buffers
806 * pinned per crtc.
807 *
808 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
809 * bits with absolutely no headroom. So use 4 bits. */
810 unsigned int pin_count:4;
811#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
812
813 /**
814 * Is the object at the current location in the gtt mappable and
815 * fenceable? Used to avoid costly recalculations.
816 */
817 unsigned int map_and_fenceable:1;
818
819 /**
820 * Whether the current gtt mapping needs to be mappable (and isn't just
821 * mappable by accident). Track pin and fault separate for a more
822 * accurate mappable working set.
823 */
824 unsigned int fault_mappable:1;
825 unsigned int pin_mappable:1;
826
827 /*
828 * Is the GPU currently using a fence to access this buffer,
829 */
830 unsigned int pending_fenced_gpu_access:1;
831 unsigned int fenced_gpu_access:1;
832
833 unsigned int cache_level:2;
834
835 struct page **pages;
836
837 /**
838 * DMAR support
839 */
840 struct scatterlist *sg_list;
841 int num_sg;
842
843 /**
844 * Used for performing relocations during execbuffer insertion.
845 */
846 struct hlist_node exec_node;
847 unsigned long exec_handle;
848 struct drm_i915_gem_exec_object2 *exec_entry;
849
850 /**
851 * Current offset of the object in GTT space.
852 *
853 * This is the same as gtt_space->start
854 */
855 uint32_t gtt_offset;
856
857 /** Breadcrumb of last rendering to the buffer. */
858 uint32_t last_rendering_seqno;
859 struct intel_ring_buffer *ring;
860
861 /** Breadcrumb of last fenced GPU access to the buffer. */
862 uint32_t last_fenced_seqno;
863 struct intel_ring_buffer *last_fenced_ring;
864
865 /** Current tiling stride for the object, if it's tiled. */
866 uint32_t stride;
867
868 /** Record of address bit 17 of each page at last unbind. */
869 unsigned long *bit_17;
870
871
872 /**
873 * If present, while GEM_DOMAIN_CPU is in the read domain this array
874 * flags which individual pages are valid.
875 */
876 uint8_t *page_cpu_valid;
877
878 /** User space pin count and filp owning the pin */
879 uint32_t user_pin_count;
880 struct drm_file *pin_filp;
881
882 /** for phy allocated objects */
883 struct drm_i915_gem_phys_object *phys_obj;
884
885 /**
886 * Number of crtcs where this object is currently the fb, but
887 * will be page flipped away on the next vblank. When it
888 * reaches 0, dev_priv->pending_flip_queue will be woken up.
889 */
890 atomic_t pending_flip;
891};
892
893#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
894
895/**
896 * Request queue structure.
897 *
898 * The request queue allows us to note sequence numbers that have been emitted
899 * and may be associated with active buffers to be retired.
900 *
901 * By keeping this list, we can avoid having to do questionable
902 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
903 * an emission time with seqnos for tracking how far ahead of the GPU we are.
904 */
905struct drm_i915_gem_request {
906 /** On Which ring this request was generated */
907 struct intel_ring_buffer *ring;
908
909 /** GEM sequence number associated with this request. */
910 uint32_t seqno;
911
912 /** Time at which this request was emitted, in jiffies. */
913 unsigned long emitted_jiffies;
914
915 /** global list entry for this request */
916 struct list_head list;
917
918 struct drm_i915_file_private *file_priv;
919 /** file_priv list entry for this request */
920 struct list_head client_list;
921};
922
923struct drm_i915_file_private {
924 struct {
925 struct spinlock lock;
926 struct list_head request_list;
927 } mm;
928};
929
930#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
931
932#define IS_I830(dev) ((dev)->pci_device == 0x3577)
933#define IS_845G(dev) ((dev)->pci_device == 0x2562)
934#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
935#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
936#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
937#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
938#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
939#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
940#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
941#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
942#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
943#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
944#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
945#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
946#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
947#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
948#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
949#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
950#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
951#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
952
953/*
954 * The genX designation typically refers to the render engine, so render
955 * capability related checks should use IS_GEN, while display and other checks
956 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
957 * chips, etc.).
958 */
959#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
960#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
961#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
962#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
963#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
964#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
965
966#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
967#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
968#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
969
970#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
971#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
972
973/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
974 * rows, which changed the alignment requirements and fence programming.
975 */
976#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
977 IS_I915GM(dev)))
978#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
979#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
980#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
981#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
982#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
983#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
984/* dsparb controlled by hw only */
985#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
986
987#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
988#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
989#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
990
991#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
992#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
993
994#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
995#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
996#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
997
998#include "i915_trace.h"
999
1000extern struct drm_ioctl_desc i915_ioctls[];
1001extern int i915_max_ioctl;
1002extern unsigned int i915_fbpercrtc __always_unused;
1003extern int i915_panel_ignore_lid __read_mostly;
1004extern unsigned int i915_powersave __read_mostly;
1005extern unsigned int i915_semaphores __read_mostly;
1006extern unsigned int i915_lvds_downclock __read_mostly;
1007extern int i915_panel_use_ssc __read_mostly;
1008extern int i915_vbt_sdvo_panel_type __read_mostly;
1009extern unsigned int i915_enable_rc6 __read_mostly;
1010extern int i915_enable_fbc __read_mostly;
1011extern bool i915_enable_hangcheck __read_mostly;
1012
1013extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1014extern int i915_resume(struct drm_device *dev);
1015extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1016extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1017
1018 /* i915_dma.c */
1019extern void i915_kernel_lost_context(struct drm_device * dev);
1020extern int i915_driver_load(struct drm_device *, unsigned long flags);
1021extern int i915_driver_unload(struct drm_device *);
1022extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1023extern void i915_driver_lastclose(struct drm_device * dev);
1024extern void i915_driver_preclose(struct drm_device *dev,
1025 struct drm_file *file_priv);
1026extern void i915_driver_postclose(struct drm_device *dev,
1027 struct drm_file *file_priv);
1028extern int i915_driver_device_is_agp(struct drm_device * dev);
1029extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1030 unsigned long arg);
1031extern int i915_emit_box(struct drm_device *dev,
1032 struct drm_clip_rect *box,
1033 int DR1, int DR4);
1034extern int i915_reset(struct drm_device *dev, u8 flags);
1035extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1036extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1037extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1038extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1039
1040
1041/* i915_irq.c */
1042void i915_hangcheck_elapsed(unsigned long data);
1043void i915_handle_error(struct drm_device *dev, bool wedged);
1044extern int i915_irq_emit(struct drm_device *dev, void *data,
1045 struct drm_file *file_priv);
1046extern int i915_irq_wait(struct drm_device *dev, void *data,
1047 struct drm_file *file_priv);
1048
1049extern void intel_irq_init(struct drm_device *dev);
1050
1051extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1052 struct drm_file *file_priv);
1053extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1054 struct drm_file *file_priv);
1055extern int i915_vblank_swap(struct drm_device *dev, void *data,
1056 struct drm_file *file_priv);
1057
1058void
1059i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1060
1061void
1062i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1063
1064void intel_enable_asle(struct drm_device *dev);
1065
1066#ifdef CONFIG_DEBUG_FS
1067extern void i915_destroy_error_state(struct drm_device *dev);
1068#else
1069#define i915_destroy_error_state(x)
1070#endif
1071
1072
1073/* i915_mem.c */
1074extern int i915_mem_alloc(struct drm_device *dev, void *data,
1075 struct drm_file *file_priv);
1076extern int i915_mem_free(struct drm_device *dev, void *data,
1077 struct drm_file *file_priv);
1078extern int i915_mem_init_heap(struct drm_device *dev, void *data,
1079 struct drm_file *file_priv);
1080extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
1081 struct drm_file *file_priv);
1082extern void i915_mem_takedown(struct mem_block **heap);
1083extern void i915_mem_release(struct drm_device * dev,
1084 struct drm_file *file_priv, struct mem_block *heap);
1085/* i915_gem.c */
1086int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1087 struct drm_file *file_priv);
1088int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1089 struct drm_file *file_priv);
1090int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1091 struct drm_file *file_priv);
1092int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1093 struct drm_file *file_priv);
1094int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1095 struct drm_file *file_priv);
1096int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1097 struct drm_file *file_priv);
1098int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1099 struct drm_file *file_priv);
1100int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1101 struct drm_file *file_priv);
1102int i915_gem_execbuffer(struct drm_device *dev, void *data,
1103 struct drm_file *file_priv);
1104int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1105 struct drm_file *file_priv);
1106int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1107 struct drm_file *file_priv);
1108int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1109 struct drm_file *file_priv);
1110int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1111 struct drm_file *file_priv);
1112int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1113 struct drm_file *file_priv);
1114int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1115 struct drm_file *file_priv);
1116int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1117 struct drm_file *file_priv);
1118int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1119 struct drm_file *file_priv);
1120int i915_gem_set_tiling(struct drm_device *dev, void *data,
1121 struct drm_file *file_priv);
1122int i915_gem_get_tiling(struct drm_device *dev, void *data,
1123 struct drm_file *file_priv);
1124int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1125 struct drm_file *file_priv);
1126void i915_gem_load(struct drm_device *dev);
1127int i915_gem_init_object(struct drm_gem_object *obj);
1128int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring,
1129 uint32_t invalidate_domains,
1130 uint32_t flush_domains);
1131struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1132 size_t size);
1133void i915_gem_free_object(struct drm_gem_object *obj);
1134int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1135 uint32_t alignment,
1136 bool map_and_fenceable);
1137void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1138int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1139void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1140void i915_gem_lastclose(struct drm_device *dev);
1141
1142int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1143int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj);
1144void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1145 struct intel_ring_buffer *ring,
1146 u32 seqno);
1147
1148int i915_gem_dumb_create(struct drm_file *file_priv,
1149 struct drm_device *dev,
1150 struct drm_mode_create_dumb *args);
1151int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1152 uint32_t handle, uint64_t *offset);
1153int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1154 uint32_t handle);
1155/**
1156 * Returns true if seq1 is later than seq2.
1157 */
1158static inline bool
1159i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1160{
1161 return (int32_t)(seq1 - seq2) >= 0;
1162}
1163
1164static inline u32
1165i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
1166{
1167 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1168 return ring->outstanding_lazy_request = dev_priv->next_seqno;
1169}
1170
1171int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
1172 struct intel_ring_buffer *pipelined);
1173int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1174
1175void i915_gem_retire_requests(struct drm_device *dev);
1176void i915_gem_reset(struct drm_device *dev);
1177void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1178int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1179 uint32_t read_domains,
1180 uint32_t write_domain);
1181int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1182int __must_check i915_gem_init_ringbuffer(struct drm_device *dev);
1183void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1184void i915_gem_do_init(struct drm_device *dev,
1185 unsigned long start,
1186 unsigned long mappable_end,
1187 unsigned long end);
1188int __must_check i915_gpu_idle(struct drm_device *dev);
1189int __must_check i915_gem_idle(struct drm_device *dev);
1190int __must_check i915_add_request(struct intel_ring_buffer *ring,
1191 struct drm_file *file,
1192 struct drm_i915_gem_request *request);
1193int __must_check i915_wait_request(struct intel_ring_buffer *ring,
1194 uint32_t seqno);
1195int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1196int __must_check
1197i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1198 bool write);
1199int __must_check
1200i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1201 u32 alignment,
1202 struct intel_ring_buffer *pipelined);
1203int i915_gem_attach_phys_object(struct drm_device *dev,
1204 struct drm_i915_gem_object *obj,
1205 int id,
1206 int align);
1207void i915_gem_detach_phys_object(struct drm_device *dev,
1208 struct drm_i915_gem_object *obj);
1209void i915_gem_free_all_phys_object(struct drm_device *dev);
1210void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1211
1212uint32_t
1213i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1214 uint32_t size,
1215 int tiling_mode);
1216
1217int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1218 enum i915_cache_level cache_level);
1219
1220/* i915_gem_gtt.c */
1221void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1222int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
1223void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
1224 enum i915_cache_level cache_level);
1225void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1226
1227/* i915_gem_evict.c */
1228int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1229 unsigned alignment, bool mappable);
1230int __must_check i915_gem_evict_everything(struct drm_device *dev,
1231 bool purgeable_only);
1232int __must_check i915_gem_evict_inactive(struct drm_device *dev,
1233 bool purgeable_only);
1234
1235/* i915_gem_tiling.c */
1236void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1237void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1238void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1239
1240/* i915_gem_debug.c */
1241void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1242 const char *where, uint32_t mark);
1243#if WATCH_LISTS
1244int i915_verify_lists(struct drm_device *dev);
1245#else
1246#define i915_verify_lists(dev) 0
1247#endif
1248void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1249 int handle);
1250void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1251 const char *where, uint32_t mark);
1252
1253/* i915_debugfs.c */
1254int i915_debugfs_init(struct drm_minor *minor);
1255void i915_debugfs_cleanup(struct drm_minor *minor);
1256
1257/* i915_suspend.c */
1258extern int i915_save_state(struct drm_device *dev);
1259extern int i915_restore_state(struct drm_device *dev);
1260
1261/* i915_suspend.c */
1262extern int i915_save_state(struct drm_device *dev);
1263extern int i915_restore_state(struct drm_device *dev);
1264
1265/* intel_i2c.c */
1266extern int intel_setup_gmbus(struct drm_device *dev);
1267extern void intel_teardown_gmbus(struct drm_device *dev);
1268extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1269extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1270extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1271{
1272 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1273}
1274extern void intel_i2c_reset(struct drm_device *dev);
1275
1276/* intel_opregion.c */
1277extern int intel_opregion_setup(struct drm_device *dev);
1278#ifdef CONFIG_ACPI
1279extern void intel_opregion_init(struct drm_device *dev);
1280extern void intel_opregion_fini(struct drm_device *dev);
1281extern void intel_opregion_asle_intr(struct drm_device *dev);
1282extern void intel_opregion_gse_intr(struct drm_device *dev);
1283extern void intel_opregion_enable_asle(struct drm_device *dev);
1284#else
1285static inline void intel_opregion_init(struct drm_device *dev) { return; }
1286static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1287static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1288static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1289static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1290#endif
1291
1292/* intel_acpi.c */
1293#ifdef CONFIG_ACPI
1294extern void intel_register_dsm_handler(void);
1295extern void intel_unregister_dsm_handler(void);
1296#else
1297static inline void intel_register_dsm_handler(void) { return; }
1298static inline void intel_unregister_dsm_handler(void) { return; }
1299#endif /* CONFIG_ACPI */
1300
1301/* modesetting */
1302extern void intel_modeset_init(struct drm_device *dev);
1303extern void intel_modeset_gem_init(struct drm_device *dev);
1304extern void intel_modeset_cleanup(struct drm_device *dev);
1305extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1306extern bool intel_fbc_enabled(struct drm_device *dev);
1307extern void intel_disable_fbc(struct drm_device *dev);
1308extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1309extern void ironlake_init_pch_refclk(struct drm_device *dev);
1310extern void ironlake_enable_rc6(struct drm_device *dev);
1311extern void gen6_set_rps(struct drm_device *dev, u8 val);
1312extern void intel_detect_pch(struct drm_device *dev);
1313extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1314
1315extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1316extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv);
1317extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1318extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv);
1319
1320/* overlay */
1321#ifdef CONFIG_DEBUG_FS
1322extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1323extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1324
1325extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1326extern void intel_display_print_error_state(struct seq_file *m,
1327 struct drm_device *dev,
1328 struct intel_display_error_state *error);
1329#endif
1330
1331#define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1332
1333#define BEGIN_LP_RING(n) \
1334 intel_ring_begin(LP_RING(dev_priv), (n))
1335
1336#define OUT_RING(x) \
1337 intel_ring_emit(LP_RING(dev_priv), x)
1338
1339#define ADVANCE_LP_RING() \
1340 intel_ring_advance(LP_RING(dev_priv))
1341
1342/**
1343 * Lock test for when it's just for synchronization of ring access.
1344 *
1345 * In that case, we don't need to do it when GEM is initialized as nobody else
1346 * has access to the ring.
1347 */
1348#define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
1349 if (LP_RING(dev->dev_private)->obj == NULL) \
1350 LOCK_TEST_WITH_RETURN(dev, file); \
1351} while (0)
1352
1353/* On SNB platform, before reading ring registers forcewake bit
1354 * must be set to prevent GT core from power down and stale values being
1355 * returned.
1356 */
1357void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1358void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1359void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1360
1361/* We give fast paths for the really cool registers */
1362#define NEEDS_FORCE_WAKE(dev_priv, reg) \
1363 (((dev_priv)->info->gen >= 6) && \
1364 ((reg) < 0x40000) && \
1365 ((reg) != FORCEWAKE) && \
1366 ((reg) != ECOBUS))
1367
1368#define __i915_read(x, y) \
1369 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1370
1371__i915_read(8, b)
1372__i915_read(16, w)
1373__i915_read(32, l)
1374__i915_read(64, q)
1375#undef __i915_read
1376
1377#define __i915_write(x, y) \
1378 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1379
1380__i915_write(8, b)
1381__i915_write(16, w)
1382__i915_write(32, l)
1383__i915_write(64, q)
1384#undef __i915_write
1385
1386#define I915_READ8(reg) i915_read8(dev_priv, (reg))
1387#define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1388
1389#define I915_READ16(reg) i915_read16(dev_priv, (reg))
1390#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1391#define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1392#define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1393
1394#define I915_READ(reg) i915_read32(dev_priv, (reg))
1395#define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1396#define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1397#define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1398
1399#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1400#define I915_READ64(reg) i915_read64(dev_priv, (reg))
1401
1402#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1403#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1404
1405
1406#endif
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