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drm/i915: Set initial seqno value close to wrap boundary
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_drv.h
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1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include <uapi/drm/i915_drm.h>
34
35#include "i915_reg.h"
36#include "intel_bios.h"
37#include "intel_ringbuffer.h"
38#include <linux/io-mapping.h>
39#include <linux/i2c.h>
40#include <linux/i2c-algo-bit.h>
41#include <drm/intel-gtt.h>
42#include <linux/backlight.h>
43#include <linux/intel-iommu.h>
44#include <linux/kref.h>
45#include <linux/pm_qos.h>
46
47/* General customization:
48 */
49
50#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
51
52#define DRIVER_NAME "i915"
53#define DRIVER_DESC "Intel Graphics"
54#define DRIVER_DATE "20080730"
55
56enum pipe {
57 PIPE_A = 0,
58 PIPE_B,
59 PIPE_C,
60 I915_MAX_PIPES
61};
62#define pipe_name(p) ((p) + 'A')
63
64enum transcoder {
65 TRANSCODER_A = 0,
66 TRANSCODER_B,
67 TRANSCODER_C,
68 TRANSCODER_EDP = 0xF,
69};
70#define transcoder_name(t) ((t) + 'A')
71
72enum plane {
73 PLANE_A = 0,
74 PLANE_B,
75 PLANE_C,
76};
77#define plane_name(p) ((p) + 'A')
78
79enum port {
80 PORT_A = 0,
81 PORT_B,
82 PORT_C,
83 PORT_D,
84 PORT_E,
85 I915_MAX_PORTS
86};
87#define port_name(p) ((p) + 'A')
88
89#define I915_GEM_GPU_DOMAINS \
90 (I915_GEM_DOMAIN_RENDER | \
91 I915_GEM_DOMAIN_SAMPLER | \
92 I915_GEM_DOMAIN_COMMAND | \
93 I915_GEM_DOMAIN_INSTRUCTION | \
94 I915_GEM_DOMAIN_VERTEX)
95
96#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
97
98#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
99 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
100 if ((intel_encoder)->base.crtc == (__crtc))
101
102struct intel_pch_pll {
103 int refcount; /* count of number of CRTCs sharing this PLL */
104 int active; /* count of number of active CRTCs (i.e. DPMS on) */
105 bool on; /* is the PLL actually active? Disabled during modeset */
106 int pll_reg;
107 int fp0_reg;
108 int fp1_reg;
109};
110#define I915_NUM_PLLS 2
111
112/* Used by dp and fdi links */
113struct intel_link_m_n {
114 uint32_t tu;
115 uint32_t gmch_m;
116 uint32_t gmch_n;
117 uint32_t link_m;
118 uint32_t link_n;
119};
120
121void intel_link_compute_m_n(int bpp, int nlanes,
122 int pixel_clock, int link_clock,
123 struct intel_link_m_n *m_n);
124
125struct intel_ddi_plls {
126 int spll_refcount;
127 int wrpll1_refcount;
128 int wrpll2_refcount;
129};
130
131/* Interface history:
132 *
133 * 1.1: Original.
134 * 1.2: Add Power Management
135 * 1.3: Add vblank support
136 * 1.4: Fix cmdbuffer path, add heap destroy
137 * 1.5: Add vblank pipe configuration
138 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
139 * - Support vertical blank on secondary display pipe
140 */
141#define DRIVER_MAJOR 1
142#define DRIVER_MINOR 6
143#define DRIVER_PATCHLEVEL 0
144
145#define WATCH_COHERENCY 0
146#define WATCH_LISTS 0
147#define WATCH_GTT 0
148
149#define I915_GEM_PHYS_CURSOR_0 1
150#define I915_GEM_PHYS_CURSOR_1 2
151#define I915_GEM_PHYS_OVERLAY_REGS 3
152#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
153
154struct drm_i915_gem_phys_object {
155 int id;
156 struct page **page_list;
157 drm_dma_handle_t *handle;
158 struct drm_i915_gem_object *cur_obj;
159};
160
161struct opregion_header;
162struct opregion_acpi;
163struct opregion_swsci;
164struct opregion_asle;
165struct drm_i915_private;
166
167struct intel_opregion {
168 struct opregion_header __iomem *header;
169 struct opregion_acpi __iomem *acpi;
170 struct opregion_swsci __iomem *swsci;
171 struct opregion_asle __iomem *asle;
172 void __iomem *vbt;
173 u32 __iomem *lid_state;
174};
175#define OPREGION_SIZE (8*1024)
176
177struct intel_overlay;
178struct intel_overlay_error_state;
179
180struct drm_i915_master_private {
181 drm_local_map_t *sarea;
182 struct _drm_i915_sarea *sarea_priv;
183};
184#define I915_FENCE_REG_NONE -1
185#define I915_MAX_NUM_FENCES 16
186/* 16 fences + sign bit for FENCE_REG_NONE */
187#define I915_MAX_NUM_FENCE_BITS 5
188
189struct drm_i915_fence_reg {
190 struct list_head lru_list;
191 struct drm_i915_gem_object *obj;
192 int pin_count;
193};
194
195struct sdvo_device_mapping {
196 u8 initialized;
197 u8 dvo_port;
198 u8 slave_addr;
199 u8 dvo_wiring;
200 u8 i2c_pin;
201 u8 ddc_pin;
202};
203
204struct intel_display_error_state;
205
206struct drm_i915_error_state {
207 struct kref ref;
208 u32 eir;
209 u32 pgtbl_er;
210 u32 ier;
211 u32 ccid;
212 bool waiting[I915_NUM_RINGS];
213 u32 pipestat[I915_MAX_PIPES];
214 u32 tail[I915_NUM_RINGS];
215 u32 head[I915_NUM_RINGS];
216 u32 ipeir[I915_NUM_RINGS];
217 u32 ipehr[I915_NUM_RINGS];
218 u32 instdone[I915_NUM_RINGS];
219 u32 acthd[I915_NUM_RINGS];
220 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
221 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
222 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
223 /* our own tracking of ring head and tail */
224 u32 cpu_ring_head[I915_NUM_RINGS];
225 u32 cpu_ring_tail[I915_NUM_RINGS];
226 u32 error; /* gen6+ */
227 u32 err_int; /* gen7 */
228 u32 instpm[I915_NUM_RINGS];
229 u32 instps[I915_NUM_RINGS];
230 u32 extra_instdone[I915_NUM_INSTDONE_REG];
231 u32 seqno[I915_NUM_RINGS];
232 u64 bbaddr;
233 u32 fault_reg[I915_NUM_RINGS];
234 u32 done_reg;
235 u32 faddr[I915_NUM_RINGS];
236 u64 fence[I915_MAX_NUM_FENCES];
237 struct timeval time;
238 struct drm_i915_error_ring {
239 struct drm_i915_error_object {
240 int page_count;
241 u32 gtt_offset;
242 u32 *pages[0];
243 } *ringbuffer, *batchbuffer;
244 struct drm_i915_error_request {
245 long jiffies;
246 u32 seqno;
247 u32 tail;
248 } *requests;
249 int num_requests;
250 } ring[I915_NUM_RINGS];
251 struct drm_i915_error_buffer {
252 u32 size;
253 u32 name;
254 u32 rseqno, wseqno;
255 u32 gtt_offset;
256 u32 read_domains;
257 u32 write_domain;
258 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
259 s32 pinned:2;
260 u32 tiling:2;
261 u32 dirty:1;
262 u32 purgeable:1;
263 s32 ring:4;
264 u32 cache_level:2;
265 } *active_bo, *pinned_bo;
266 u32 active_bo_count, pinned_bo_count;
267 struct intel_overlay_error_state *overlay;
268 struct intel_display_error_state *display;
269};
270
271struct drm_i915_display_funcs {
272 bool (*fbc_enabled)(struct drm_device *dev);
273 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
274 void (*disable_fbc)(struct drm_device *dev);
275 int (*get_display_clock_speed)(struct drm_device *dev);
276 int (*get_fifo_size)(struct drm_device *dev, int plane);
277 void (*update_wm)(struct drm_device *dev);
278 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
279 uint32_t sprite_width, int pixel_size);
280 void (*update_linetime_wm)(struct drm_device *dev, int pipe,
281 struct drm_display_mode *mode);
282 void (*modeset_global_resources)(struct drm_device *dev);
283 int (*crtc_mode_set)(struct drm_crtc *crtc,
284 struct drm_display_mode *mode,
285 struct drm_display_mode *adjusted_mode,
286 int x, int y,
287 struct drm_framebuffer *old_fb);
288 void (*crtc_enable)(struct drm_crtc *crtc);
289 void (*crtc_disable)(struct drm_crtc *crtc);
290 void (*off)(struct drm_crtc *crtc);
291 void (*write_eld)(struct drm_connector *connector,
292 struct drm_crtc *crtc);
293 void (*fdi_link_train)(struct drm_crtc *crtc);
294 void (*init_clock_gating)(struct drm_device *dev);
295 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
296 struct drm_framebuffer *fb,
297 struct drm_i915_gem_object *obj);
298 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
299 int x, int y);
300 /* clock updates for mode set */
301 /* cursor updates */
302 /* render clock increase/decrease */
303 /* display clock increase/decrease */
304 /* pll clock increase/decrease */
305};
306
307struct drm_i915_gt_funcs {
308 void (*force_wake_get)(struct drm_i915_private *dev_priv);
309 void (*force_wake_put)(struct drm_i915_private *dev_priv);
310};
311
312#define DEV_INFO_FLAGS \
313 DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \
314 DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \
315 DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \
316 DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \
317 DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \
318 DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \
319 DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \
320 DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \
321 DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \
322 DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \
323 DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \
324 DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \
325 DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \
326 DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \
327 DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \
328 DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \
329 DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \
330 DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \
331 DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \
332 DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \
333 DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \
334 DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \
335 DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \
336 DEV_INFO_FLAG(has_llc)
337
338struct intel_device_info {
339 u8 gen;
340 u8 is_mobile:1;
341 u8 is_i85x:1;
342 u8 is_i915g:1;
343 u8 is_i945gm:1;
344 u8 is_g33:1;
345 u8 need_gfx_hws:1;
346 u8 is_g4x:1;
347 u8 is_pineview:1;
348 u8 is_broadwater:1;
349 u8 is_crestline:1;
350 u8 is_ivybridge:1;
351 u8 is_valleyview:1;
352 u8 has_force_wake:1;
353 u8 is_haswell:1;
354 u8 has_fbc:1;
355 u8 has_pipe_cxsr:1;
356 u8 has_hotplug:1;
357 u8 cursor_needs_physical:1;
358 u8 has_overlay:1;
359 u8 overlay_needs_physical:1;
360 u8 supports_tv:1;
361 u8 has_bsd_ring:1;
362 u8 has_blt_ring:1;
363 u8 has_llc:1;
364};
365
366#define I915_PPGTT_PD_ENTRIES 512
367#define I915_PPGTT_PT_ENTRIES 1024
368struct i915_hw_ppgtt {
369 struct drm_device *dev;
370 unsigned num_pd_entries;
371 struct page **pt_pages;
372 uint32_t pd_offset;
373 dma_addr_t *pt_dma_addr;
374 dma_addr_t scratch_page_dma_addr;
375};
376
377
378/* This must match up with the value previously used for execbuf2.rsvd1. */
379#define DEFAULT_CONTEXT_ID 0
380struct i915_hw_context {
381 int id;
382 bool is_initialized;
383 struct drm_i915_file_private *file_priv;
384 struct intel_ring_buffer *ring;
385 struct drm_i915_gem_object *obj;
386};
387
388enum no_fbc_reason {
389 FBC_NO_OUTPUT, /* no outputs enabled to compress */
390 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
391 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
392 FBC_MODE_TOO_LARGE, /* mode too large for compression */
393 FBC_BAD_PLANE, /* fbc not supported on plane */
394 FBC_NOT_TILED, /* buffer not tiled */
395 FBC_MULTIPLE_PIPES, /* more than one pipe active */
396 FBC_MODULE_PARAM,
397};
398
399enum intel_pch {
400 PCH_NONE = 0, /* No PCH present */
401 PCH_IBX, /* Ibexpeak PCH */
402 PCH_CPT, /* Cougarpoint PCH */
403 PCH_LPT, /* Lynxpoint PCH */
404};
405
406#define QUIRK_PIPEA_FORCE (1<<0)
407#define QUIRK_LVDS_SSC_DISABLE (1<<1)
408#define QUIRK_INVERT_BRIGHTNESS (1<<2)
409
410struct intel_fbdev;
411struct intel_fbc_work;
412
413struct intel_gmbus {
414 struct i2c_adapter adapter;
415 u32 force_bit;
416 u32 reg0;
417 u32 gpio_reg;
418 struct i2c_algo_bit_data bit_algo;
419 struct drm_i915_private *dev_priv;
420};
421
422struct i915_suspend_saved_registers {
423 u8 saveLBB;
424 u32 saveDSPACNTR;
425 u32 saveDSPBCNTR;
426 u32 saveDSPARB;
427 u32 savePIPEACONF;
428 u32 savePIPEBCONF;
429 u32 savePIPEASRC;
430 u32 savePIPEBSRC;
431 u32 saveFPA0;
432 u32 saveFPA1;
433 u32 saveDPLL_A;
434 u32 saveDPLL_A_MD;
435 u32 saveHTOTAL_A;
436 u32 saveHBLANK_A;
437 u32 saveHSYNC_A;
438 u32 saveVTOTAL_A;
439 u32 saveVBLANK_A;
440 u32 saveVSYNC_A;
441 u32 saveBCLRPAT_A;
442 u32 saveTRANSACONF;
443 u32 saveTRANS_HTOTAL_A;
444 u32 saveTRANS_HBLANK_A;
445 u32 saveTRANS_HSYNC_A;
446 u32 saveTRANS_VTOTAL_A;
447 u32 saveTRANS_VBLANK_A;
448 u32 saveTRANS_VSYNC_A;
449 u32 savePIPEASTAT;
450 u32 saveDSPASTRIDE;
451 u32 saveDSPASIZE;
452 u32 saveDSPAPOS;
453 u32 saveDSPAADDR;
454 u32 saveDSPASURF;
455 u32 saveDSPATILEOFF;
456 u32 savePFIT_PGM_RATIOS;
457 u32 saveBLC_HIST_CTL;
458 u32 saveBLC_PWM_CTL;
459 u32 saveBLC_PWM_CTL2;
460 u32 saveBLC_CPU_PWM_CTL;
461 u32 saveBLC_CPU_PWM_CTL2;
462 u32 saveFPB0;
463 u32 saveFPB1;
464 u32 saveDPLL_B;
465 u32 saveDPLL_B_MD;
466 u32 saveHTOTAL_B;
467 u32 saveHBLANK_B;
468 u32 saveHSYNC_B;
469 u32 saveVTOTAL_B;
470 u32 saveVBLANK_B;
471 u32 saveVSYNC_B;
472 u32 saveBCLRPAT_B;
473 u32 saveTRANSBCONF;
474 u32 saveTRANS_HTOTAL_B;
475 u32 saveTRANS_HBLANK_B;
476 u32 saveTRANS_HSYNC_B;
477 u32 saveTRANS_VTOTAL_B;
478 u32 saveTRANS_VBLANK_B;
479 u32 saveTRANS_VSYNC_B;
480 u32 savePIPEBSTAT;
481 u32 saveDSPBSTRIDE;
482 u32 saveDSPBSIZE;
483 u32 saveDSPBPOS;
484 u32 saveDSPBADDR;
485 u32 saveDSPBSURF;
486 u32 saveDSPBTILEOFF;
487 u32 saveVGA0;
488 u32 saveVGA1;
489 u32 saveVGA_PD;
490 u32 saveVGACNTRL;
491 u32 saveADPA;
492 u32 saveLVDS;
493 u32 savePP_ON_DELAYS;
494 u32 savePP_OFF_DELAYS;
495 u32 saveDVOA;
496 u32 saveDVOB;
497 u32 saveDVOC;
498 u32 savePP_ON;
499 u32 savePP_OFF;
500 u32 savePP_CONTROL;
501 u32 savePP_DIVISOR;
502 u32 savePFIT_CONTROL;
503 u32 save_palette_a[256];
504 u32 save_palette_b[256];
505 u32 saveDPFC_CB_BASE;
506 u32 saveFBC_CFB_BASE;
507 u32 saveFBC_LL_BASE;
508 u32 saveFBC_CONTROL;
509 u32 saveFBC_CONTROL2;
510 u32 saveIER;
511 u32 saveIIR;
512 u32 saveIMR;
513 u32 saveDEIER;
514 u32 saveDEIMR;
515 u32 saveGTIER;
516 u32 saveGTIMR;
517 u32 saveFDI_RXA_IMR;
518 u32 saveFDI_RXB_IMR;
519 u32 saveCACHE_MODE_0;
520 u32 saveMI_ARB_STATE;
521 u32 saveSWF0[16];
522 u32 saveSWF1[16];
523 u32 saveSWF2[3];
524 u8 saveMSR;
525 u8 saveSR[8];
526 u8 saveGR[25];
527 u8 saveAR_INDEX;
528 u8 saveAR[21];
529 u8 saveDACMASK;
530 u8 saveCR[37];
531 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
532 u32 saveCURACNTR;
533 u32 saveCURAPOS;
534 u32 saveCURABASE;
535 u32 saveCURBCNTR;
536 u32 saveCURBPOS;
537 u32 saveCURBBASE;
538 u32 saveCURSIZE;
539 u32 saveDP_B;
540 u32 saveDP_C;
541 u32 saveDP_D;
542 u32 savePIPEA_GMCH_DATA_M;
543 u32 savePIPEB_GMCH_DATA_M;
544 u32 savePIPEA_GMCH_DATA_N;
545 u32 savePIPEB_GMCH_DATA_N;
546 u32 savePIPEA_DP_LINK_M;
547 u32 savePIPEB_DP_LINK_M;
548 u32 savePIPEA_DP_LINK_N;
549 u32 savePIPEB_DP_LINK_N;
550 u32 saveFDI_RXA_CTL;
551 u32 saveFDI_TXA_CTL;
552 u32 saveFDI_RXB_CTL;
553 u32 saveFDI_TXB_CTL;
554 u32 savePFA_CTL_1;
555 u32 savePFB_CTL_1;
556 u32 savePFA_WIN_SZ;
557 u32 savePFB_WIN_SZ;
558 u32 savePFA_WIN_POS;
559 u32 savePFB_WIN_POS;
560 u32 savePCH_DREF_CONTROL;
561 u32 saveDISP_ARB_CTL;
562 u32 savePIPEA_DATA_M1;
563 u32 savePIPEA_DATA_N1;
564 u32 savePIPEA_LINK_M1;
565 u32 savePIPEA_LINK_N1;
566 u32 savePIPEB_DATA_M1;
567 u32 savePIPEB_DATA_N1;
568 u32 savePIPEB_LINK_M1;
569 u32 savePIPEB_LINK_N1;
570 u32 saveMCHBAR_RENDER_STANDBY;
571 u32 savePCH_PORT_HOTPLUG;
572};
573
574struct intel_gen6_power_mgmt {
575 struct work_struct work;
576 u32 pm_iir;
577 /* lock - irqsave spinlock that protectects the work_struct and
578 * pm_iir. */
579 spinlock_t lock;
580
581 /* The below variables an all the rps hw state are protected by
582 * dev->struct mutext. */
583 u8 cur_delay;
584 u8 min_delay;
585 u8 max_delay;
586
587 struct delayed_work delayed_resume_work;
588
589 /*
590 * Protects RPS/RC6 register access and PCU communication.
591 * Must be taken after struct_mutex if nested.
592 */
593 struct mutex hw_lock;
594};
595
596/* defined intel_pm.c */
597extern spinlock_t mchdev_lock;
598
599struct intel_ilk_power_mgmt {
600 u8 cur_delay;
601 u8 min_delay;
602 u8 max_delay;
603 u8 fmax;
604 u8 fstart;
605
606 u64 last_count1;
607 unsigned long last_time1;
608 unsigned long chipset_power;
609 u64 last_count2;
610 struct timespec last_time2;
611 unsigned long gfx_power;
612 u8 corr;
613
614 int c_m;
615 int r_t;
616
617 struct drm_i915_gem_object *pwrctx;
618 struct drm_i915_gem_object *renderctx;
619};
620
621struct i915_dri1_state {
622 unsigned allow_batchbuffer : 1;
623 u32 __iomem *gfx_hws_cpu_addr;
624
625 unsigned int cpp;
626 int back_offset;
627 int front_offset;
628 int current_page;
629 int page_flipping;
630
631 uint32_t counter;
632};
633
634struct intel_l3_parity {
635 u32 *remap_info;
636 struct work_struct error_work;
637};
638
639typedef struct drm_i915_private {
640 struct drm_device *dev;
641 struct kmem_cache *slab;
642
643 const struct intel_device_info *info;
644
645 int relative_constants_mode;
646
647 void __iomem *regs;
648
649 struct drm_i915_gt_funcs gt;
650 /** gt_fifo_count and the subsequent register write are synchronized
651 * with dev->struct_mutex. */
652 unsigned gt_fifo_count;
653 /** forcewake_count is protected by gt_lock */
654 unsigned forcewake_count;
655 /** gt_lock is also taken in irq contexts. */
656 spinlock_t gt_lock;
657
658 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
659
660
661 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
662 * controller on different i2c buses. */
663 struct mutex gmbus_mutex;
664
665 /**
666 * Base address of the gmbus and gpio block.
667 */
668 uint32_t gpio_mmio_base;
669
670 wait_queue_head_t gmbus_wait_queue;
671
672 struct pci_dev *bridge_dev;
673 struct intel_ring_buffer ring[I915_NUM_RINGS];
674 uint32_t last_seqno, next_seqno;
675
676 drm_dma_handle_t *status_page_dmah;
677 struct resource mch_res;
678
679 atomic_t irq_received;
680
681 /* protects the irq masks */
682 spinlock_t irq_lock;
683
684 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
685 struct pm_qos_request pm_qos;
686
687 /* DPIO indirect register protection */
688 spinlock_t dpio_lock;
689
690 /** Cached value of IMR to avoid reads in updating the bitfield */
691 u32 pipestat[2];
692 u32 irq_mask;
693 u32 gt_irq_mask;
694 u32 pch_irq_mask;
695
696 u32 hotplug_supported_mask;
697 struct work_struct hotplug_work;
698 bool enable_hotplug_processing;
699
700 int num_pipe;
701 int num_pch_pll;
702
703 /* For hangcheck timer */
704#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
705#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
706 struct timer_list hangcheck_timer;
707 int hangcheck_count;
708 uint32_t last_acthd[I915_NUM_RINGS];
709 uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
710
711 unsigned int stop_rings;
712
713 unsigned long cfb_size;
714 unsigned int cfb_fb;
715 enum plane cfb_plane;
716 int cfb_y;
717 struct intel_fbc_work *fbc_work;
718
719 struct intel_opregion opregion;
720
721 /* overlay */
722 struct intel_overlay *overlay;
723 bool sprite_scaling_enabled;
724
725 /* LVDS info */
726 int backlight_level; /* restore backlight to this value */
727 bool backlight_enabled;
728 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
729 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
730
731 /* Feature bits from the VBIOS */
732 unsigned int int_tv_support:1;
733 unsigned int lvds_dither:1;
734 unsigned int lvds_vbt:1;
735 unsigned int int_crt_support:1;
736 unsigned int lvds_use_ssc:1;
737 unsigned int display_clock_mode:1;
738 int lvds_ssc_freq;
739 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
740 struct {
741 int rate;
742 int lanes;
743 int preemphasis;
744 int vswing;
745
746 bool initialized;
747 bool support;
748 int bpp;
749 struct edp_power_seq pps;
750 } edp;
751 bool no_aux_handshake;
752
753 int crt_ddc_pin;
754 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
755 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
756 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
757
758 unsigned int fsb_freq, mem_freq, is_ddr3;
759
760 spinlock_t error_lock;
761 /* Protected by dev->error_lock. */
762 struct drm_i915_error_state *first_error;
763 struct work_struct error_work;
764 struct completion error_completion;
765 struct workqueue_struct *wq;
766
767 /* Display functions */
768 struct drm_i915_display_funcs display;
769
770 /* PCH chipset type */
771 enum intel_pch pch_type;
772 unsigned short pch_id;
773
774 unsigned long quirks;
775
776 /* Register state */
777 bool modeset_on_lid;
778
779 struct {
780 /** Bridge to intel-gtt-ko */
781 struct intel_gtt *gtt;
782 /** Memory allocator for GTT stolen memory */
783 struct drm_mm stolen;
784 /** Memory allocator for GTT */
785 struct drm_mm gtt_space;
786 /** List of all objects in gtt_space. Used to restore gtt
787 * mappings on resume */
788 struct list_head bound_list;
789 /**
790 * List of objects which are not bound to the GTT (thus
791 * are idle and not used by the GPU) but still have
792 * (presumably uncached) pages still attached.
793 */
794 struct list_head unbound_list;
795
796 /** Usable portion of the GTT for GEM */
797 unsigned long gtt_start;
798 unsigned long gtt_mappable_end;
799 unsigned long gtt_end;
800 unsigned long stolen_base; /* limited to low memory (32-bit) */
801
802 struct io_mapping *gtt_mapping;
803 phys_addr_t gtt_base_addr;
804 int gtt_mtrr;
805
806 /** PPGTT used for aliasing the PPGTT with the GTT */
807 struct i915_hw_ppgtt *aliasing_ppgtt;
808
809 struct shrinker inactive_shrinker;
810
811 /**
812 * List of objects currently involved in rendering.
813 *
814 * Includes buffers having the contents of their GPU caches
815 * flushed, not necessarily primitives. last_rendering_seqno
816 * represents when the rendering involved will be completed.
817 *
818 * A reference is held on the buffer while on this list.
819 */
820 struct list_head active_list;
821
822 /**
823 * LRU list of objects which are not in the ringbuffer and
824 * are ready to unbind, but are still in the GTT.
825 *
826 * last_rendering_seqno is 0 while an object is in this list.
827 *
828 * A reference is not held on the buffer while on this list,
829 * as merely being GTT-bound shouldn't prevent its being
830 * freed, and we'll pull it off the list in the free path.
831 */
832 struct list_head inactive_list;
833
834 /** LRU list of objects with fence regs on them. */
835 struct list_head fence_list;
836
837 /**
838 * We leave the user IRQ off as much as possible,
839 * but this means that requests will finish and never
840 * be retired once the system goes idle. Set a timer to
841 * fire periodically while the ring is running. When it
842 * fires, go retire requests.
843 */
844 struct delayed_work retire_work;
845
846 /**
847 * Are we in a non-interruptible section of code like
848 * modesetting?
849 */
850 bool interruptible;
851
852 /**
853 * Flag if the X Server, and thus DRM, is not currently in
854 * control of the device.
855 *
856 * This is set between LeaveVT and EnterVT. It needs to be
857 * replaced with a semaphore. It also needs to be
858 * transitioned away from for kernel modesetting.
859 */
860 int suspended;
861
862 /**
863 * Flag if the hardware appears to be wedged.
864 *
865 * This is set when attempts to idle the device timeout.
866 * It prevents command submission from occurring and makes
867 * every pending request fail
868 */
869 atomic_t wedged;
870
871 /** Bit 6 swizzling required for X tiling */
872 uint32_t bit_6_swizzle_x;
873 /** Bit 6 swizzling required for Y tiling */
874 uint32_t bit_6_swizzle_y;
875
876 /* storage for physical objects */
877 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
878
879 /* accounting, useful for userland debugging */
880 size_t gtt_total;
881 size_t mappable_gtt_total;
882 size_t object_memory;
883 u32 object_count;
884 } mm;
885
886 /* Kernel Modesetting */
887
888 struct sdvo_device_mapping sdvo_mappings[2];
889 /* indicate whether the LVDS_BORDER should be enabled or not */
890 unsigned int lvds_border_bits;
891 /* Panel fitter placement and size for Ironlake+ */
892 u32 pch_pf_pos, pch_pf_size;
893
894 struct drm_crtc *plane_to_crtc_mapping[3];
895 struct drm_crtc *pipe_to_crtc_mapping[3];
896 wait_queue_head_t pending_flip_queue;
897
898 struct intel_pch_pll pch_plls[I915_NUM_PLLS];
899 struct intel_ddi_plls ddi_plls;
900
901 /* Reclocking support */
902 bool render_reclock_avail;
903 bool lvds_downclock_avail;
904 /* indicates the reduced downclock for LVDS*/
905 int lvds_downclock;
906 u16 orig_clock;
907 int child_dev_num;
908 struct child_device_config *child_dev;
909
910 bool mchbar_need_disable;
911
912 struct intel_l3_parity l3_parity;
913
914 /* gen6+ rps state */
915 struct intel_gen6_power_mgmt rps;
916
917 /* ilk-only ips/rps state. Everything in here is protected by the global
918 * mchdev_lock in intel_pm.c */
919 struct intel_ilk_power_mgmt ips;
920
921 enum no_fbc_reason no_fbc_reason;
922
923 struct drm_mm_node *compressed_fb;
924 struct drm_mm_node *compressed_llb;
925
926 unsigned long last_gpu_reset;
927
928 /* list of fbdev register on this device */
929 struct intel_fbdev *fbdev;
930
931 /*
932 * The console may be contended at resume, but we don't
933 * want it to block on it.
934 */
935 struct work_struct console_resume_work;
936
937 struct backlight_device *backlight;
938
939 struct drm_property *broadcast_rgb_property;
940 struct drm_property *force_audio_property;
941
942 bool hw_contexts_disabled;
943 uint32_t hw_context_size;
944
945 struct i915_suspend_saved_registers regfile;
946
947 /* Old dri1 support infrastructure, beware the dragons ya fools entering
948 * here! */
949 struct i915_dri1_state dri1;
950} drm_i915_private_t;
951
952/* Iterate over initialised rings */
953#define for_each_ring(ring__, dev_priv__, i__) \
954 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
955 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
956
957enum hdmi_force_audio {
958 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
959 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
960 HDMI_AUDIO_AUTO, /* trust EDID */
961 HDMI_AUDIO_ON, /* force turn on HDMI audio */
962};
963
964enum i915_cache_level {
965 I915_CACHE_NONE = 0,
966 I915_CACHE_LLC,
967 I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
968};
969
970#define I915_GTT_RESERVED ((struct drm_mm_node *)0x1)
971
972struct drm_i915_gem_object_ops {
973 /* Interface between the GEM object and its backing storage.
974 * get_pages() is called once prior to the use of the associated set
975 * of pages before to binding them into the GTT, and put_pages() is
976 * called after we no longer need them. As we expect there to be
977 * associated cost with migrating pages between the backing storage
978 * and making them available for the GPU (e.g. clflush), we may hold
979 * onto the pages after they are no longer referenced by the GPU
980 * in case they may be used again shortly (for example migrating the
981 * pages to a different memory domain within the GTT). put_pages()
982 * will therefore most likely be called when the object itself is
983 * being released or under memory pressure (where we attempt to
984 * reap pages for the shrinker).
985 */
986 int (*get_pages)(struct drm_i915_gem_object *);
987 void (*put_pages)(struct drm_i915_gem_object *);
988};
989
990struct drm_i915_gem_object {
991 struct drm_gem_object base;
992
993 const struct drm_i915_gem_object_ops *ops;
994
995 /** Current space allocated to this object in the GTT, if any. */
996 struct drm_mm_node *gtt_space;
997 /** Stolen memory for this object, instead of being backed by shmem. */
998 struct drm_mm_node *stolen;
999 struct list_head gtt_list;
1000
1001 /** This object's place on the active/inactive lists */
1002 struct list_head ring_list;
1003 struct list_head mm_list;
1004 /** This object's place in the batchbuffer or on the eviction list */
1005 struct list_head exec_list;
1006
1007 /**
1008 * This is set if the object is on the active lists (has pending
1009 * rendering and so a non-zero seqno), and is not set if it i s on
1010 * inactive (ready to be unbound) list.
1011 */
1012 unsigned int active:1;
1013
1014 /**
1015 * This is set if the object has been written to since last bound
1016 * to the GTT
1017 */
1018 unsigned int dirty:1;
1019
1020 /**
1021 * Fence register bits (if any) for this object. Will be set
1022 * as needed when mapped into the GTT.
1023 * Protected by dev->struct_mutex.
1024 */
1025 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1026
1027 /**
1028 * Advice: are the backing pages purgeable?
1029 */
1030 unsigned int madv:2;
1031
1032 /**
1033 * Current tiling mode for the object.
1034 */
1035 unsigned int tiling_mode:2;
1036 /**
1037 * Whether the tiling parameters for the currently associated fence
1038 * register have changed. Note that for the purposes of tracking
1039 * tiling changes we also treat the unfenced register, the register
1040 * slot that the object occupies whilst it executes a fenced
1041 * command (such as BLT on gen2/3), as a "fence".
1042 */
1043 unsigned int fence_dirty:1;
1044
1045 /** How many users have pinned this object in GTT space. The following
1046 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1047 * (via user_pin_count), execbuffer (objects are not allowed multiple
1048 * times for the same batchbuffer), and the framebuffer code. When
1049 * switching/pageflipping, the framebuffer code has at most two buffers
1050 * pinned per crtc.
1051 *
1052 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1053 * bits with absolutely no headroom. So use 4 bits. */
1054 unsigned int pin_count:4;
1055#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1056
1057 /**
1058 * Is the object at the current location in the gtt mappable and
1059 * fenceable? Used to avoid costly recalculations.
1060 */
1061 unsigned int map_and_fenceable:1;
1062
1063 /**
1064 * Whether the current gtt mapping needs to be mappable (and isn't just
1065 * mappable by accident). Track pin and fault separate for a more
1066 * accurate mappable working set.
1067 */
1068 unsigned int fault_mappable:1;
1069 unsigned int pin_mappable:1;
1070
1071 /*
1072 * Is the GPU currently using a fence to access this buffer,
1073 */
1074 unsigned int pending_fenced_gpu_access:1;
1075 unsigned int fenced_gpu_access:1;
1076
1077 unsigned int cache_level:2;
1078
1079 unsigned int has_aliasing_ppgtt_mapping:1;
1080 unsigned int has_global_gtt_mapping:1;
1081 unsigned int has_dma_mapping:1;
1082
1083 struct sg_table *pages;
1084 int pages_pin_count;
1085
1086 /* prime dma-buf support */
1087 void *dma_buf_vmapping;
1088 int vmapping_count;
1089
1090 /**
1091 * Used for performing relocations during execbuffer insertion.
1092 */
1093 struct hlist_node exec_node;
1094 unsigned long exec_handle;
1095 struct drm_i915_gem_exec_object2 *exec_entry;
1096
1097 /**
1098 * Current offset of the object in GTT space.
1099 *
1100 * This is the same as gtt_space->start
1101 */
1102 uint32_t gtt_offset;
1103
1104 struct intel_ring_buffer *ring;
1105
1106 /** Breadcrumb of last rendering to the buffer. */
1107 uint32_t last_read_seqno;
1108 uint32_t last_write_seqno;
1109 /** Breadcrumb of last fenced GPU access to the buffer. */
1110 uint32_t last_fenced_seqno;
1111
1112 /** Current tiling stride for the object, if it's tiled. */
1113 uint32_t stride;
1114
1115 /** Record of address bit 17 of each page at last unbind. */
1116 unsigned long *bit_17;
1117
1118 /** User space pin count and filp owning the pin */
1119 uint32_t user_pin_count;
1120 struct drm_file *pin_filp;
1121
1122 /** for phy allocated objects */
1123 struct drm_i915_gem_phys_object *phys_obj;
1124
1125 /**
1126 * Number of crtcs where this object is currently the fb, but
1127 * will be page flipped away on the next vblank. When it
1128 * reaches 0, dev_priv->pending_flip_queue will be woken up.
1129 */
1130 atomic_t pending_flip;
1131};
1132
1133#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1134
1135/**
1136 * Request queue structure.
1137 *
1138 * The request queue allows us to note sequence numbers that have been emitted
1139 * and may be associated with active buffers to be retired.
1140 *
1141 * By keeping this list, we can avoid having to do questionable
1142 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1143 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1144 */
1145struct drm_i915_gem_request {
1146 /** On Which ring this request was generated */
1147 struct intel_ring_buffer *ring;
1148
1149 /** GEM sequence number associated with this request. */
1150 uint32_t seqno;
1151
1152 /** Postion in the ringbuffer of the end of the request */
1153 u32 tail;
1154
1155 /** Time at which this request was emitted, in jiffies. */
1156 unsigned long emitted_jiffies;
1157
1158 /** global list entry for this request */
1159 struct list_head list;
1160
1161 struct drm_i915_file_private *file_priv;
1162 /** file_priv list entry for this request */
1163 struct list_head client_list;
1164};
1165
1166struct drm_i915_file_private {
1167 struct {
1168 spinlock_t lock;
1169 struct list_head request_list;
1170 } mm;
1171 struct idr context_idr;
1172};
1173
1174#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1175
1176#define IS_I830(dev) ((dev)->pci_device == 0x3577)
1177#define IS_845G(dev) ((dev)->pci_device == 0x2562)
1178#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1179#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1180#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1181#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1182#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1183#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1184#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1185#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1186#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1187#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1188#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1189#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1190#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1191#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1192#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1193#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1194#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1195#define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1196 (dev)->pci_device == 0x0152 || \
1197 (dev)->pci_device == 0x015a)
1198#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1199#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1200#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1201#define IS_ULT(dev) (IS_HASWELL(dev) && \
1202 ((dev)->pci_device & 0xFF00) == 0x0A00)
1203
1204/*
1205 * The genX designation typically refers to the render engine, so render
1206 * capability related checks should use IS_GEN, while display and other checks
1207 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1208 * chips, etc.).
1209 */
1210#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1211#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1212#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1213#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1214#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1215#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1216
1217#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1218#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1219#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1220#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1221
1222#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1223#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1224
1225#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1226#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1227
1228/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1229 * rows, which changed the alignment requirements and fence programming.
1230 */
1231#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1232 IS_I915GM(dev)))
1233#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1234#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1235#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1236#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1237#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1238#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1239/* dsparb controlled by hw only */
1240#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1241
1242#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1243#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1244#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1245
1246#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1247
1248#define HAS_DDI(dev) (IS_HASWELL(dev))
1249
1250#define INTEL_PCH_DEVICE_ID_MASK 0xff00
1251#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1252#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1253#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1254#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1255#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1256
1257#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1258#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1259#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1260#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1261#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1262
1263#define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1264
1265#define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1266
1267#define GT_FREQUENCY_MULTIPLIER 50
1268
1269#include "i915_trace.h"
1270
1271/**
1272 * RC6 is a special power stage which allows the GPU to enter an very
1273 * low-voltage mode when idle, using down to 0V while at this stage. This
1274 * stage is entered automatically when the GPU is idle when RC6 support is
1275 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1276 *
1277 * There are different RC6 modes available in Intel GPU, which differentiate
1278 * among each other with the latency required to enter and leave RC6 and
1279 * voltage consumed by the GPU in different states.
1280 *
1281 * The combination of the following flags define which states GPU is allowed
1282 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1283 * RC6pp is deepest RC6. Their support by hardware varies according to the
1284 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1285 * which brings the most power savings; deeper states save more power, but
1286 * require higher latency to switch to and wake up.
1287 */
1288#define INTEL_RC6_ENABLE (1<<0)
1289#define INTEL_RC6p_ENABLE (1<<1)
1290#define INTEL_RC6pp_ENABLE (1<<2)
1291
1292extern struct drm_ioctl_desc i915_ioctls[];
1293extern int i915_max_ioctl;
1294extern unsigned int i915_fbpercrtc __always_unused;
1295extern int i915_panel_ignore_lid __read_mostly;
1296extern unsigned int i915_powersave __read_mostly;
1297extern int i915_semaphores __read_mostly;
1298extern unsigned int i915_lvds_downclock __read_mostly;
1299extern int i915_lvds_channel_mode __read_mostly;
1300extern int i915_panel_use_ssc __read_mostly;
1301extern int i915_vbt_sdvo_panel_type __read_mostly;
1302extern int i915_enable_rc6 __read_mostly;
1303extern int i915_enable_fbc __read_mostly;
1304extern bool i915_enable_hangcheck __read_mostly;
1305extern int i915_enable_ppgtt __read_mostly;
1306extern unsigned int i915_preliminary_hw_support __read_mostly;
1307
1308extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1309extern int i915_resume(struct drm_device *dev);
1310extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1311extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1312
1313 /* i915_dma.c */
1314void i915_update_dri1_breadcrumb(struct drm_device *dev);
1315extern void i915_kernel_lost_context(struct drm_device * dev);
1316extern int i915_driver_load(struct drm_device *, unsigned long flags);
1317extern int i915_driver_unload(struct drm_device *);
1318extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1319extern void i915_driver_lastclose(struct drm_device * dev);
1320extern void i915_driver_preclose(struct drm_device *dev,
1321 struct drm_file *file_priv);
1322extern void i915_driver_postclose(struct drm_device *dev,
1323 struct drm_file *file_priv);
1324extern int i915_driver_device_is_agp(struct drm_device * dev);
1325#ifdef CONFIG_COMPAT
1326extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1327 unsigned long arg);
1328#endif
1329extern int i915_emit_box(struct drm_device *dev,
1330 struct drm_clip_rect *box,
1331 int DR1, int DR4);
1332extern int intel_gpu_reset(struct drm_device *dev);
1333extern int i915_reset(struct drm_device *dev);
1334extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1335extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1336extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1337extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1338
1339extern void intel_console_resume(struct work_struct *work);
1340
1341/* i915_irq.c */
1342void i915_hangcheck_elapsed(unsigned long data);
1343void i915_handle_error(struct drm_device *dev, bool wedged);
1344
1345extern void intel_irq_init(struct drm_device *dev);
1346extern void intel_gt_init(struct drm_device *dev);
1347extern void intel_gt_reset(struct drm_device *dev);
1348
1349void i915_error_state_free(struct kref *error_ref);
1350
1351void
1352i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1353
1354void
1355i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1356
1357void intel_enable_asle(struct drm_device *dev);
1358
1359#ifdef CONFIG_DEBUG_FS
1360extern void i915_destroy_error_state(struct drm_device *dev);
1361#else
1362#define i915_destroy_error_state(x)
1363#endif
1364
1365
1366/* i915_gem.c */
1367int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1368 struct drm_file *file_priv);
1369int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1370 struct drm_file *file_priv);
1371int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1372 struct drm_file *file_priv);
1373int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1374 struct drm_file *file_priv);
1375int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1376 struct drm_file *file_priv);
1377int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1378 struct drm_file *file_priv);
1379int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1380 struct drm_file *file_priv);
1381int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1382 struct drm_file *file_priv);
1383int i915_gem_execbuffer(struct drm_device *dev, void *data,
1384 struct drm_file *file_priv);
1385int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1386 struct drm_file *file_priv);
1387int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1388 struct drm_file *file_priv);
1389int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1390 struct drm_file *file_priv);
1391int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1392 struct drm_file *file_priv);
1393int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1394 struct drm_file *file);
1395int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1396 struct drm_file *file);
1397int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1398 struct drm_file *file_priv);
1399int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1400 struct drm_file *file_priv);
1401int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1402 struct drm_file *file_priv);
1403int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1404 struct drm_file *file_priv);
1405int i915_gem_set_tiling(struct drm_device *dev, void *data,
1406 struct drm_file *file_priv);
1407int i915_gem_get_tiling(struct drm_device *dev, void *data,
1408 struct drm_file *file_priv);
1409int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1410 struct drm_file *file_priv);
1411int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1412 struct drm_file *file_priv);
1413void i915_gem_load(struct drm_device *dev);
1414void *i915_gem_object_alloc(struct drm_device *dev);
1415void i915_gem_object_free(struct drm_i915_gem_object *obj);
1416int i915_gem_init_object(struct drm_gem_object *obj);
1417void i915_gem_object_init(struct drm_i915_gem_object *obj,
1418 const struct drm_i915_gem_object_ops *ops);
1419struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1420 size_t size);
1421void i915_gem_free_object(struct drm_gem_object *obj);
1422
1423int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1424 uint32_t alignment,
1425 bool map_and_fenceable,
1426 bool nonblocking);
1427void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1428int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1429void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1430void i915_gem_lastclose(struct drm_device *dev);
1431
1432int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
1433static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
1434{
1435 struct scatterlist *sg = obj->pages->sgl;
1436 int nents = obj->pages->nents;
1437 while (nents > SG_MAX_SINGLE_ALLOC) {
1438 if (n < SG_MAX_SINGLE_ALLOC - 1)
1439 break;
1440
1441 sg = sg_chain_ptr(sg + SG_MAX_SINGLE_ALLOC - 1);
1442 n -= SG_MAX_SINGLE_ALLOC - 1;
1443 nents -= SG_MAX_SINGLE_ALLOC - 1;
1444 }
1445 return sg_page(sg+n);
1446}
1447static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
1448{
1449 BUG_ON(obj->pages == NULL);
1450 obj->pages_pin_count++;
1451}
1452static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
1453{
1454 BUG_ON(obj->pages_pin_count == 0);
1455 obj->pages_pin_count--;
1456}
1457
1458int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1459int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1460 struct intel_ring_buffer *to);
1461void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1462 struct intel_ring_buffer *ring);
1463
1464int i915_gem_dumb_create(struct drm_file *file_priv,
1465 struct drm_device *dev,
1466 struct drm_mode_create_dumb *args);
1467int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1468 uint32_t handle, uint64_t *offset);
1469int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1470 uint32_t handle);
1471/**
1472 * Returns true if seq1 is later than seq2.
1473 */
1474static inline bool
1475i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1476{
1477 return (int32_t)(seq1 - seq2) >= 0;
1478}
1479
1480extern int i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
1481
1482int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1483int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1484
1485static inline bool
1486i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1487{
1488 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1489 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1490 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1491 return true;
1492 } else
1493 return false;
1494}
1495
1496static inline void
1497i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1498{
1499 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1500 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1501 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1502 }
1503}
1504
1505void i915_gem_retire_requests(struct drm_device *dev);
1506void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1507int __must_check i915_gem_check_wedge(struct drm_i915_private *dev_priv,
1508 bool interruptible);
1509
1510void i915_gem_reset(struct drm_device *dev);
1511void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1512int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1513 uint32_t read_domains,
1514 uint32_t write_domain);
1515int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1516int __must_check i915_gem_init(struct drm_device *dev);
1517int __must_check i915_gem_init_hw(struct drm_device *dev);
1518void i915_gem_l3_remap(struct drm_device *dev);
1519void i915_gem_init_swizzling(struct drm_device *dev);
1520void i915_gem_init_ppgtt(struct drm_device *dev);
1521void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1522int __must_check i915_gpu_idle(struct drm_device *dev);
1523int __must_check i915_gem_idle(struct drm_device *dev);
1524int i915_add_request(struct intel_ring_buffer *ring,
1525 struct drm_file *file,
1526 u32 *seqno);
1527int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1528 uint32_t seqno);
1529int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1530int __must_check
1531i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1532 bool write);
1533int __must_check
1534i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1535int __must_check
1536i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1537 u32 alignment,
1538 struct intel_ring_buffer *pipelined);
1539int i915_gem_attach_phys_object(struct drm_device *dev,
1540 struct drm_i915_gem_object *obj,
1541 int id,
1542 int align);
1543void i915_gem_detach_phys_object(struct drm_device *dev,
1544 struct drm_i915_gem_object *obj);
1545void i915_gem_free_all_phys_object(struct drm_device *dev);
1546void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1547
1548uint32_t
1549i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1550 uint32_t size,
1551 int tiling_mode);
1552
1553int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1554 enum i915_cache_level cache_level);
1555
1556struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1557 struct dma_buf *dma_buf);
1558
1559struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1560 struct drm_gem_object *gem_obj, int flags);
1561
1562/* i915_gem_context.c */
1563void i915_gem_context_init(struct drm_device *dev);
1564void i915_gem_context_fini(struct drm_device *dev);
1565void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
1566int i915_switch_context(struct intel_ring_buffer *ring,
1567 struct drm_file *file, int to_id);
1568int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1569 struct drm_file *file);
1570int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1571 struct drm_file *file);
1572
1573/* i915_gem_gtt.c */
1574int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
1575void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1576void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1577 struct drm_i915_gem_object *obj,
1578 enum i915_cache_level cache_level);
1579void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1580 struct drm_i915_gem_object *obj);
1581
1582void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1583int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1584void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1585 enum i915_cache_level cache_level);
1586void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1587void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1588void i915_gem_init_global_gtt(struct drm_device *dev,
1589 unsigned long start,
1590 unsigned long mappable_end,
1591 unsigned long end);
1592int i915_gem_gtt_init(struct drm_device *dev);
1593void i915_gem_gtt_fini(struct drm_device *dev);
1594static inline void i915_gem_chipset_flush(struct drm_device *dev)
1595{
1596 if (INTEL_INFO(dev)->gen < 6)
1597 intel_gtt_chipset_flush();
1598}
1599
1600
1601/* i915_gem_evict.c */
1602int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1603 unsigned alignment,
1604 unsigned cache_level,
1605 bool mappable,
1606 bool nonblock);
1607int i915_gem_evict_everything(struct drm_device *dev);
1608
1609/* i915_gem_stolen.c */
1610int i915_gem_init_stolen(struct drm_device *dev);
1611int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
1612void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
1613void i915_gem_cleanup_stolen(struct drm_device *dev);
1614struct drm_i915_gem_object *
1615i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
1616void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
1617
1618/* i915_gem_tiling.c */
1619inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1620{
1621 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
1622
1623 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1624 obj->tiling_mode != I915_TILING_NONE;
1625}
1626
1627void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1628void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1629void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1630
1631/* i915_gem_debug.c */
1632void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1633 const char *where, uint32_t mark);
1634#if WATCH_LISTS
1635int i915_verify_lists(struct drm_device *dev);
1636#else
1637#define i915_verify_lists(dev) 0
1638#endif
1639void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1640 int handle);
1641void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1642 const char *where, uint32_t mark);
1643
1644/* i915_debugfs.c */
1645int i915_debugfs_init(struct drm_minor *minor);
1646void i915_debugfs_cleanup(struct drm_minor *minor);
1647
1648/* i915_suspend.c */
1649extern int i915_save_state(struct drm_device *dev);
1650extern int i915_restore_state(struct drm_device *dev);
1651
1652/* i915_suspend.c */
1653extern int i915_save_state(struct drm_device *dev);
1654extern int i915_restore_state(struct drm_device *dev);
1655
1656/* i915_sysfs.c */
1657void i915_setup_sysfs(struct drm_device *dev_priv);
1658void i915_teardown_sysfs(struct drm_device *dev_priv);
1659
1660/* intel_i2c.c */
1661extern int intel_setup_gmbus(struct drm_device *dev);
1662extern void intel_teardown_gmbus(struct drm_device *dev);
1663extern inline bool intel_gmbus_is_port_valid(unsigned port)
1664{
1665 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1666}
1667
1668extern struct i2c_adapter *intel_gmbus_get_adapter(
1669 struct drm_i915_private *dev_priv, unsigned port);
1670extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1671extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1672extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1673{
1674 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1675}
1676extern void intel_i2c_reset(struct drm_device *dev);
1677
1678/* intel_opregion.c */
1679extern int intel_opregion_setup(struct drm_device *dev);
1680#ifdef CONFIG_ACPI
1681extern void intel_opregion_init(struct drm_device *dev);
1682extern void intel_opregion_fini(struct drm_device *dev);
1683extern void intel_opregion_asle_intr(struct drm_device *dev);
1684extern void intel_opregion_gse_intr(struct drm_device *dev);
1685extern void intel_opregion_enable_asle(struct drm_device *dev);
1686#else
1687static inline void intel_opregion_init(struct drm_device *dev) { return; }
1688static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1689static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1690static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1691static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1692#endif
1693
1694/* intel_acpi.c */
1695#ifdef CONFIG_ACPI
1696extern void intel_register_dsm_handler(void);
1697extern void intel_unregister_dsm_handler(void);
1698#else
1699static inline void intel_register_dsm_handler(void) { return; }
1700static inline void intel_unregister_dsm_handler(void) { return; }
1701#endif /* CONFIG_ACPI */
1702
1703/* modesetting */
1704extern void intel_modeset_init_hw(struct drm_device *dev);
1705extern void intel_modeset_init(struct drm_device *dev);
1706extern void intel_modeset_gem_init(struct drm_device *dev);
1707extern void intel_modeset_cleanup(struct drm_device *dev);
1708extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1709extern void intel_modeset_setup_hw_state(struct drm_device *dev,
1710 bool force_restore);
1711extern bool intel_fbc_enabled(struct drm_device *dev);
1712extern void intel_disable_fbc(struct drm_device *dev);
1713extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1714extern void ironlake_init_pch_refclk(struct drm_device *dev);
1715extern void gen6_set_rps(struct drm_device *dev, u8 val);
1716extern void intel_detect_pch(struct drm_device *dev);
1717extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1718extern int intel_enable_rc6(const struct drm_device *dev);
1719
1720extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1721int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1722 struct drm_file *file);
1723
1724/* overlay */
1725#ifdef CONFIG_DEBUG_FS
1726extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1727extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1728
1729extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1730extern void intel_display_print_error_state(struct seq_file *m,
1731 struct drm_device *dev,
1732 struct intel_display_error_state *error);
1733#endif
1734
1735/* On SNB platform, before reading ring registers forcewake bit
1736 * must be set to prevent GT core from power down and stale values being
1737 * returned.
1738 */
1739void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1740void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1741int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1742
1743int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
1744int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
1745
1746#define __i915_read(x, y) \
1747 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1748
1749__i915_read(8, b)
1750__i915_read(16, w)
1751__i915_read(32, l)
1752__i915_read(64, q)
1753#undef __i915_read
1754
1755#define __i915_write(x, y) \
1756 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1757
1758__i915_write(8, b)
1759__i915_write(16, w)
1760__i915_write(32, l)
1761__i915_write(64, q)
1762#undef __i915_write
1763
1764#define I915_READ8(reg) i915_read8(dev_priv, (reg))
1765#define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1766
1767#define I915_READ16(reg) i915_read16(dev_priv, (reg))
1768#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1769#define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1770#define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1771
1772#define I915_READ(reg) i915_read32(dev_priv, (reg))
1773#define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1774#define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1775#define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1776
1777#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1778#define I915_READ64(reg) i915_read64(dev_priv, (reg))
1779
1780#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1781#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1782
1783
1784#endif
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