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drm/i915: clear the entire gtt when using gem
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1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include "i915_reg.h"
34#include "intel_bios.h"
35#include "intel_ringbuffer.h"
36#include <linux/io-mapping.h>
37#include <linux/i2c.h>
38#include <linux/i2c-algo-bit.h>
39#include <drm/intel-gtt.h>
40#include <linux/backlight.h>
41
42/* General customization:
43 */
44
45#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
46
47#define DRIVER_NAME "i915"
48#define DRIVER_DESC "Intel Graphics"
49#define DRIVER_DATE "20080730"
50
51enum pipe {
52 PIPE_A = 0,
53 PIPE_B,
54 PIPE_C,
55 I915_MAX_PIPES
56};
57#define pipe_name(p) ((p) + 'A')
58
59enum plane {
60 PLANE_A = 0,
61 PLANE_B,
62 PLANE_C,
63};
64#define plane_name(p) ((p) + 'A')
65
66#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
67
68#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
69
70/* Interface history:
71 *
72 * 1.1: Original.
73 * 1.2: Add Power Management
74 * 1.3: Add vblank support
75 * 1.4: Fix cmdbuffer path, add heap destroy
76 * 1.5: Add vblank pipe configuration
77 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
78 * - Support vertical blank on secondary display pipe
79 */
80#define DRIVER_MAJOR 1
81#define DRIVER_MINOR 6
82#define DRIVER_PATCHLEVEL 0
83
84#define WATCH_COHERENCY 0
85#define WATCH_LISTS 0
86
87#define I915_GEM_PHYS_CURSOR_0 1
88#define I915_GEM_PHYS_CURSOR_1 2
89#define I915_GEM_PHYS_OVERLAY_REGS 3
90#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
91
92struct drm_i915_gem_phys_object {
93 int id;
94 struct page **page_list;
95 drm_dma_handle_t *handle;
96 struct drm_i915_gem_object *cur_obj;
97};
98
99struct mem_block {
100 struct mem_block *next;
101 struct mem_block *prev;
102 int start;
103 int size;
104 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
105};
106
107struct opregion_header;
108struct opregion_acpi;
109struct opregion_swsci;
110struct opregion_asle;
111struct drm_i915_private;
112
113struct intel_opregion {
114 struct opregion_header *header;
115 struct opregion_acpi *acpi;
116 struct opregion_swsci *swsci;
117 struct opregion_asle *asle;
118 void *vbt;
119 u32 __iomem *lid_state;
120};
121#define OPREGION_SIZE (8*1024)
122
123struct intel_overlay;
124struct intel_overlay_error_state;
125
126struct drm_i915_master_private {
127 drm_local_map_t *sarea;
128 struct _drm_i915_sarea *sarea_priv;
129};
130#define I915_FENCE_REG_NONE -1
131#define I915_MAX_NUM_FENCES 16
132/* 16 fences + sign bit for FENCE_REG_NONE */
133#define I915_MAX_NUM_FENCE_BITS 5
134
135struct drm_i915_fence_reg {
136 struct list_head lru_list;
137 struct drm_i915_gem_object *obj;
138 uint32_t setup_seqno;
139 int pin_count;
140};
141
142struct sdvo_device_mapping {
143 u8 initialized;
144 u8 dvo_port;
145 u8 slave_addr;
146 u8 dvo_wiring;
147 u8 i2c_pin;
148 u8 ddc_pin;
149};
150
151struct intel_display_error_state;
152
153struct drm_i915_error_state {
154 u32 eir;
155 u32 pgtbl_er;
156 u32 pipestat[I915_MAX_PIPES];
157 u32 tail[I915_NUM_RINGS];
158 u32 head[I915_NUM_RINGS];
159 u32 ipeir[I915_NUM_RINGS];
160 u32 ipehr[I915_NUM_RINGS];
161 u32 instdone[I915_NUM_RINGS];
162 u32 acthd[I915_NUM_RINGS];
163 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
164 /* our own tracking of ring head and tail */
165 u32 cpu_ring_head[I915_NUM_RINGS];
166 u32 cpu_ring_tail[I915_NUM_RINGS];
167 u32 error; /* gen6+ */
168 u32 instpm[I915_NUM_RINGS];
169 u32 instps[I915_NUM_RINGS];
170 u32 instdone1;
171 u32 seqno[I915_NUM_RINGS];
172 u64 bbaddr;
173 u32 fault_reg[I915_NUM_RINGS];
174 u32 done_reg;
175 u32 faddr[I915_NUM_RINGS];
176 u64 fence[I915_MAX_NUM_FENCES];
177 struct timeval time;
178 struct drm_i915_error_ring {
179 struct drm_i915_error_object {
180 int page_count;
181 u32 gtt_offset;
182 u32 *pages[0];
183 } *ringbuffer, *batchbuffer;
184 struct drm_i915_error_request {
185 long jiffies;
186 u32 seqno;
187 u32 tail;
188 } *requests;
189 int num_requests;
190 } ring[I915_NUM_RINGS];
191 struct drm_i915_error_buffer {
192 u32 size;
193 u32 name;
194 u32 seqno;
195 u32 gtt_offset;
196 u32 read_domains;
197 u32 write_domain;
198 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
199 s32 pinned:2;
200 u32 tiling:2;
201 u32 dirty:1;
202 u32 purgeable:1;
203 s32 ring:4;
204 u32 cache_level:2;
205 } *active_bo, *pinned_bo;
206 u32 active_bo_count, pinned_bo_count;
207 struct intel_overlay_error_state *overlay;
208 struct intel_display_error_state *display;
209};
210
211struct drm_i915_display_funcs {
212 void (*dpms)(struct drm_crtc *crtc, int mode);
213 bool (*fbc_enabled)(struct drm_device *dev);
214 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
215 void (*disable_fbc)(struct drm_device *dev);
216 int (*get_display_clock_speed)(struct drm_device *dev);
217 int (*get_fifo_size)(struct drm_device *dev, int plane);
218 void (*update_wm)(struct drm_device *dev);
219 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
220 uint32_t sprite_width, int pixel_size);
221 int (*crtc_mode_set)(struct drm_crtc *crtc,
222 struct drm_display_mode *mode,
223 struct drm_display_mode *adjusted_mode,
224 int x, int y,
225 struct drm_framebuffer *old_fb);
226 void (*write_eld)(struct drm_connector *connector,
227 struct drm_crtc *crtc);
228 void (*fdi_link_train)(struct drm_crtc *crtc);
229 void (*init_clock_gating)(struct drm_device *dev);
230 void (*init_pch_clock_gating)(struct drm_device *dev);
231 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
232 struct drm_framebuffer *fb,
233 struct drm_i915_gem_object *obj);
234 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
235 int x, int y);
236 void (*force_wake_get)(struct drm_i915_private *dev_priv);
237 void (*force_wake_put)(struct drm_i915_private *dev_priv);
238 /* clock updates for mode set */
239 /* cursor updates */
240 /* render clock increase/decrease */
241 /* display clock increase/decrease */
242 /* pll clock increase/decrease */
243};
244
245struct intel_device_info {
246 u8 gen;
247 u8 is_mobile:1;
248 u8 is_i85x:1;
249 u8 is_i915g:1;
250 u8 is_i945gm:1;
251 u8 is_g33:1;
252 u8 need_gfx_hws:1;
253 u8 is_g4x:1;
254 u8 is_pineview:1;
255 u8 is_broadwater:1;
256 u8 is_crestline:1;
257 u8 is_ivybridge:1;
258 u8 has_fbc:1;
259 u8 has_pipe_cxsr:1;
260 u8 has_hotplug:1;
261 u8 cursor_needs_physical:1;
262 u8 has_overlay:1;
263 u8 overlay_needs_physical:1;
264 u8 supports_tv:1;
265 u8 has_bsd_ring:1;
266 u8 has_blt_ring:1;
267 u8 has_llc:1;
268};
269
270#define I915_PPGTT_PD_ENTRIES 512
271#define I915_PPGTT_PT_ENTRIES 1024
272struct i915_hw_ppgtt {
273 unsigned num_pd_entries;
274 struct page **pt_pages;
275 uint32_t pd_offset;
276 dma_addr_t *pt_dma_addr;
277 dma_addr_t scratch_page_dma_addr;
278};
279
280enum no_fbc_reason {
281 FBC_NO_OUTPUT, /* no outputs enabled to compress */
282 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
283 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
284 FBC_MODE_TOO_LARGE, /* mode too large for compression */
285 FBC_BAD_PLANE, /* fbc not supported on plane */
286 FBC_NOT_TILED, /* buffer not tiled */
287 FBC_MULTIPLE_PIPES, /* more than one pipe active */
288 FBC_MODULE_PARAM,
289};
290
291enum intel_pch {
292 PCH_IBX, /* Ibexpeak PCH */
293 PCH_CPT, /* Cougarpoint PCH */
294};
295
296#define QUIRK_PIPEA_FORCE (1<<0)
297#define QUIRK_LVDS_SSC_DISABLE (1<<1)
298#define QUIRK_INVERT_BRIGHTNESS (1<<2)
299
300struct intel_fbdev;
301struct intel_fbc_work;
302
303struct intel_gmbus {
304 struct i2c_adapter adapter;
305 bool force_bit;
306 bool has_gpio;
307 u32 reg0;
308 u32 gpio_reg;
309 struct i2c_algo_bit_data bit_algo;
310 struct drm_i915_private *dev_priv;
311};
312
313typedef struct drm_i915_private {
314 struct drm_device *dev;
315
316 const struct intel_device_info *info;
317
318 int has_gem;
319 int relative_constants_mode;
320
321 void __iomem *regs;
322 /** gt_fifo_count and the subsequent register write are synchronized
323 * with dev->struct_mutex. */
324 unsigned gt_fifo_count;
325 /** forcewake_count is protected by gt_lock */
326 unsigned forcewake_count;
327 /** gt_lock is also taken in irq contexts. */
328 struct spinlock gt_lock;
329
330 struct intel_gmbus *gmbus;
331
332 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
333 * controller on different i2c buses. */
334 struct mutex gmbus_mutex;
335
336 /**
337 * Base address of the gmbus and gpio block.
338 */
339 uint32_t gpio_mmio_base;
340
341 struct pci_dev *bridge_dev;
342 struct intel_ring_buffer ring[I915_NUM_RINGS];
343 uint32_t next_seqno;
344
345 drm_dma_handle_t *status_page_dmah;
346 uint32_t counter;
347 drm_local_map_t hws_map;
348 struct drm_i915_gem_object *pwrctx;
349 struct drm_i915_gem_object *renderctx;
350
351 struct resource mch_res;
352
353 unsigned int cpp;
354 int back_offset;
355 int front_offset;
356 int current_page;
357 int page_flipping;
358
359 atomic_t irq_received;
360
361 /* protects the irq masks */
362 spinlock_t irq_lock;
363 /** Cached value of IMR to avoid reads in updating the bitfield */
364 u32 pipestat[2];
365 u32 irq_mask;
366 u32 gt_irq_mask;
367 u32 pch_irq_mask;
368
369 u32 hotplug_supported_mask;
370 struct work_struct hotplug_work;
371
372 int tex_lru_log_granularity;
373 int allow_batchbuffer;
374 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
375 int vblank_pipe;
376 int num_pipe;
377
378 /* For hangcheck timer */
379#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
380 struct timer_list hangcheck_timer;
381 int hangcheck_count;
382 uint32_t last_acthd;
383 uint32_t last_acthd_bsd;
384 uint32_t last_acthd_blt;
385 uint32_t last_instdone;
386 uint32_t last_instdone1;
387
388 unsigned long cfb_size;
389 unsigned int cfb_fb;
390 enum plane cfb_plane;
391 int cfb_y;
392 struct intel_fbc_work *fbc_work;
393
394 struct intel_opregion opregion;
395
396 /* overlay */
397 struct intel_overlay *overlay;
398 bool sprite_scaling_enabled;
399
400 /* LVDS info */
401 int backlight_level; /* restore backlight to this value */
402 bool backlight_enabled;
403 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
404 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
405
406 /* Feature bits from the VBIOS */
407 unsigned int int_tv_support:1;
408 unsigned int lvds_dither:1;
409 unsigned int lvds_vbt:1;
410 unsigned int int_crt_support:1;
411 unsigned int lvds_use_ssc:1;
412 unsigned int display_clock_mode:1;
413 int lvds_ssc_freq;
414 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
415 unsigned int lvds_val; /* used for checking LVDS channel mode */
416 struct {
417 int rate;
418 int lanes;
419 int preemphasis;
420 int vswing;
421
422 bool initialized;
423 bool support;
424 int bpp;
425 struct edp_power_seq pps;
426 } edp;
427 bool no_aux_handshake;
428
429 struct notifier_block lid_notifier;
430
431 int crt_ddc_pin;
432 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
433 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
434 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
435
436 unsigned int fsb_freq, mem_freq, is_ddr3;
437
438 spinlock_t error_lock;
439 struct drm_i915_error_state *first_error;
440 struct work_struct error_work;
441 struct completion error_completion;
442 struct workqueue_struct *wq;
443
444 /* Display functions */
445 struct drm_i915_display_funcs display;
446
447 /* PCH chipset type */
448 enum intel_pch pch_type;
449
450 unsigned long quirks;
451
452 /* Register state */
453 bool modeset_on_lid;
454 u8 saveLBB;
455 u32 saveDSPACNTR;
456 u32 saveDSPBCNTR;
457 u32 saveDSPARB;
458 u32 saveHWS;
459 u32 savePIPEACONF;
460 u32 savePIPEBCONF;
461 u32 savePIPEASRC;
462 u32 savePIPEBSRC;
463 u32 saveFPA0;
464 u32 saveFPA1;
465 u32 saveDPLL_A;
466 u32 saveDPLL_A_MD;
467 u32 saveHTOTAL_A;
468 u32 saveHBLANK_A;
469 u32 saveHSYNC_A;
470 u32 saveVTOTAL_A;
471 u32 saveVBLANK_A;
472 u32 saveVSYNC_A;
473 u32 saveBCLRPAT_A;
474 u32 saveTRANSACONF;
475 u32 saveTRANS_HTOTAL_A;
476 u32 saveTRANS_HBLANK_A;
477 u32 saveTRANS_HSYNC_A;
478 u32 saveTRANS_VTOTAL_A;
479 u32 saveTRANS_VBLANK_A;
480 u32 saveTRANS_VSYNC_A;
481 u32 savePIPEASTAT;
482 u32 saveDSPASTRIDE;
483 u32 saveDSPASIZE;
484 u32 saveDSPAPOS;
485 u32 saveDSPAADDR;
486 u32 saveDSPASURF;
487 u32 saveDSPATILEOFF;
488 u32 savePFIT_PGM_RATIOS;
489 u32 saveBLC_HIST_CTL;
490 u32 saveBLC_PWM_CTL;
491 u32 saveBLC_PWM_CTL2;
492 u32 saveBLC_CPU_PWM_CTL;
493 u32 saveBLC_CPU_PWM_CTL2;
494 u32 saveFPB0;
495 u32 saveFPB1;
496 u32 saveDPLL_B;
497 u32 saveDPLL_B_MD;
498 u32 saveHTOTAL_B;
499 u32 saveHBLANK_B;
500 u32 saveHSYNC_B;
501 u32 saveVTOTAL_B;
502 u32 saveVBLANK_B;
503 u32 saveVSYNC_B;
504 u32 saveBCLRPAT_B;
505 u32 saveTRANSBCONF;
506 u32 saveTRANS_HTOTAL_B;
507 u32 saveTRANS_HBLANK_B;
508 u32 saveTRANS_HSYNC_B;
509 u32 saveTRANS_VTOTAL_B;
510 u32 saveTRANS_VBLANK_B;
511 u32 saveTRANS_VSYNC_B;
512 u32 savePIPEBSTAT;
513 u32 saveDSPBSTRIDE;
514 u32 saveDSPBSIZE;
515 u32 saveDSPBPOS;
516 u32 saveDSPBADDR;
517 u32 saveDSPBSURF;
518 u32 saveDSPBTILEOFF;
519 u32 saveVGA0;
520 u32 saveVGA1;
521 u32 saveVGA_PD;
522 u32 saveVGACNTRL;
523 u32 saveADPA;
524 u32 saveLVDS;
525 u32 savePP_ON_DELAYS;
526 u32 savePP_OFF_DELAYS;
527 u32 saveDVOA;
528 u32 saveDVOB;
529 u32 saveDVOC;
530 u32 savePP_ON;
531 u32 savePP_OFF;
532 u32 savePP_CONTROL;
533 u32 savePP_DIVISOR;
534 u32 savePFIT_CONTROL;
535 u32 save_palette_a[256];
536 u32 save_palette_b[256];
537 u32 saveDPFC_CB_BASE;
538 u32 saveFBC_CFB_BASE;
539 u32 saveFBC_LL_BASE;
540 u32 saveFBC_CONTROL;
541 u32 saveFBC_CONTROL2;
542 u32 saveIER;
543 u32 saveIIR;
544 u32 saveIMR;
545 u32 saveDEIER;
546 u32 saveDEIMR;
547 u32 saveGTIER;
548 u32 saveGTIMR;
549 u32 saveFDI_RXA_IMR;
550 u32 saveFDI_RXB_IMR;
551 u32 saveCACHE_MODE_0;
552 u32 saveMI_ARB_STATE;
553 u32 saveSWF0[16];
554 u32 saveSWF1[16];
555 u32 saveSWF2[3];
556 u8 saveMSR;
557 u8 saveSR[8];
558 u8 saveGR[25];
559 u8 saveAR_INDEX;
560 u8 saveAR[21];
561 u8 saveDACMASK;
562 u8 saveCR[37];
563 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
564 u32 saveCURACNTR;
565 u32 saveCURAPOS;
566 u32 saveCURABASE;
567 u32 saveCURBCNTR;
568 u32 saveCURBPOS;
569 u32 saveCURBBASE;
570 u32 saveCURSIZE;
571 u32 saveDP_B;
572 u32 saveDP_C;
573 u32 saveDP_D;
574 u32 savePIPEA_GMCH_DATA_M;
575 u32 savePIPEB_GMCH_DATA_M;
576 u32 savePIPEA_GMCH_DATA_N;
577 u32 savePIPEB_GMCH_DATA_N;
578 u32 savePIPEA_DP_LINK_M;
579 u32 savePIPEB_DP_LINK_M;
580 u32 savePIPEA_DP_LINK_N;
581 u32 savePIPEB_DP_LINK_N;
582 u32 saveFDI_RXA_CTL;
583 u32 saveFDI_TXA_CTL;
584 u32 saveFDI_RXB_CTL;
585 u32 saveFDI_TXB_CTL;
586 u32 savePFA_CTL_1;
587 u32 savePFB_CTL_1;
588 u32 savePFA_WIN_SZ;
589 u32 savePFB_WIN_SZ;
590 u32 savePFA_WIN_POS;
591 u32 savePFB_WIN_POS;
592 u32 savePCH_DREF_CONTROL;
593 u32 saveDISP_ARB_CTL;
594 u32 savePIPEA_DATA_M1;
595 u32 savePIPEA_DATA_N1;
596 u32 savePIPEA_LINK_M1;
597 u32 savePIPEA_LINK_N1;
598 u32 savePIPEB_DATA_M1;
599 u32 savePIPEB_DATA_N1;
600 u32 savePIPEB_LINK_M1;
601 u32 savePIPEB_LINK_N1;
602 u32 saveMCHBAR_RENDER_STANDBY;
603 u32 savePCH_PORT_HOTPLUG;
604
605 struct {
606 /** Bridge to intel-gtt-ko */
607 const struct intel_gtt *gtt;
608 /** Memory allocator for GTT stolen memory */
609 struct drm_mm stolen;
610 /** Memory allocator for GTT */
611 struct drm_mm gtt_space;
612 /** List of all objects in gtt_space. Used to restore gtt
613 * mappings on resume */
614 struct list_head gtt_list;
615
616 /** Usable portion of the GTT for GEM */
617 unsigned long gtt_start;
618 unsigned long gtt_mappable_end;
619 unsigned long gtt_end;
620
621 struct io_mapping *gtt_mapping;
622 int gtt_mtrr;
623
624 /** PPGTT used for aliasing the PPGTT with the GTT */
625 struct i915_hw_ppgtt *aliasing_ppgtt;
626
627 struct shrinker inactive_shrinker;
628
629 /**
630 * List of objects currently involved in rendering.
631 *
632 * Includes buffers having the contents of their GPU caches
633 * flushed, not necessarily primitives. last_rendering_seqno
634 * represents when the rendering involved will be completed.
635 *
636 * A reference is held on the buffer while on this list.
637 */
638 struct list_head active_list;
639
640 /**
641 * List of objects which are not in the ringbuffer but which
642 * still have a write_domain which needs to be flushed before
643 * unbinding.
644 *
645 * last_rendering_seqno is 0 while an object is in this list.
646 *
647 * A reference is held on the buffer while on this list.
648 */
649 struct list_head flushing_list;
650
651 /**
652 * LRU list of objects which are not in the ringbuffer and
653 * are ready to unbind, but are still in the GTT.
654 *
655 * last_rendering_seqno is 0 while an object is in this list.
656 *
657 * A reference is not held on the buffer while on this list,
658 * as merely being GTT-bound shouldn't prevent its being
659 * freed, and we'll pull it off the list in the free path.
660 */
661 struct list_head inactive_list;
662
663 /**
664 * LRU list of objects which are not in the ringbuffer but
665 * are still pinned in the GTT.
666 */
667 struct list_head pinned_list;
668
669 /** LRU list of objects with fence regs on them. */
670 struct list_head fence_list;
671
672 /**
673 * List of objects currently pending being freed.
674 *
675 * These objects are no longer in use, but due to a signal
676 * we were prevented from freeing them at the appointed time.
677 */
678 struct list_head deferred_free_list;
679
680 /**
681 * We leave the user IRQ off as much as possible,
682 * but this means that requests will finish and never
683 * be retired once the system goes idle. Set a timer to
684 * fire periodically while the ring is running. When it
685 * fires, go retire requests.
686 */
687 struct delayed_work retire_work;
688
689 /**
690 * Are we in a non-interruptible section of code like
691 * modesetting?
692 */
693 bool interruptible;
694
695 /**
696 * Flag if the X Server, and thus DRM, is not currently in
697 * control of the device.
698 *
699 * This is set between LeaveVT and EnterVT. It needs to be
700 * replaced with a semaphore. It also needs to be
701 * transitioned away from for kernel modesetting.
702 */
703 int suspended;
704
705 /**
706 * Flag if the hardware appears to be wedged.
707 *
708 * This is set when attempts to idle the device timeout.
709 * It prevents command submission from occurring and makes
710 * every pending request fail
711 */
712 atomic_t wedged;
713
714 /** Bit 6 swizzling required for X tiling */
715 uint32_t bit_6_swizzle_x;
716 /** Bit 6 swizzling required for Y tiling */
717 uint32_t bit_6_swizzle_y;
718
719 /* storage for physical objects */
720 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
721
722 /* accounting, useful for userland debugging */
723 size_t gtt_total;
724 size_t mappable_gtt_total;
725 size_t object_memory;
726 u32 object_count;
727 } mm;
728 struct sdvo_device_mapping sdvo_mappings[2];
729 /* indicate whether the LVDS_BORDER should be enabled or not */
730 unsigned int lvds_border_bits;
731 /* Panel fitter placement and size for Ironlake+ */
732 u32 pch_pf_pos, pch_pf_size;
733
734 struct drm_crtc *plane_to_crtc_mapping[3];
735 struct drm_crtc *pipe_to_crtc_mapping[3];
736 wait_queue_head_t pending_flip_queue;
737 bool flip_pending_is_done;
738
739 /* Reclocking support */
740 bool render_reclock_avail;
741 bool lvds_downclock_avail;
742 /* indicates the reduced downclock for LVDS*/
743 int lvds_downclock;
744 struct work_struct idle_work;
745 struct timer_list idle_timer;
746 bool busy;
747 u16 orig_clock;
748 int child_dev_num;
749 struct child_device_config *child_dev;
750 struct drm_connector *int_lvds_connector;
751 struct drm_connector *int_edp_connector;
752
753 bool mchbar_need_disable;
754
755 struct work_struct rps_work;
756 spinlock_t rps_lock;
757 u32 pm_iir;
758
759 u8 cur_delay;
760 u8 min_delay;
761 u8 max_delay;
762 u8 fmax;
763 u8 fstart;
764
765 u64 last_count1;
766 unsigned long last_time1;
767 unsigned long chipset_power;
768 u64 last_count2;
769 struct timespec last_time2;
770 unsigned long gfx_power;
771 int c_m;
772 int r_t;
773 u8 corr;
774 spinlock_t *mchdev_lock;
775
776 enum no_fbc_reason no_fbc_reason;
777
778 struct drm_mm_node *compressed_fb;
779 struct drm_mm_node *compressed_llb;
780
781 unsigned long last_gpu_reset;
782
783 /* list of fbdev register on this device */
784 struct intel_fbdev *fbdev;
785
786 struct backlight_device *backlight;
787
788 struct drm_property *broadcast_rgb_property;
789 struct drm_property *force_audio_property;
790} drm_i915_private_t;
791
792enum hdmi_force_audio {
793 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
794 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
795 HDMI_AUDIO_AUTO, /* trust EDID */
796 HDMI_AUDIO_ON, /* force turn on HDMI audio */
797};
798
799enum i915_cache_level {
800 I915_CACHE_NONE,
801 I915_CACHE_LLC,
802 I915_CACHE_LLC_MLC, /* gen6+ */
803};
804
805struct drm_i915_gem_object {
806 struct drm_gem_object base;
807
808 /** Current space allocated to this object in the GTT, if any. */
809 struct drm_mm_node *gtt_space;
810 struct list_head gtt_list;
811
812 /** This object's place on the active/flushing/inactive lists */
813 struct list_head ring_list;
814 struct list_head mm_list;
815 /** This object's place on GPU write list */
816 struct list_head gpu_write_list;
817 /** This object's place in the batchbuffer or on the eviction list */
818 struct list_head exec_list;
819
820 /**
821 * This is set if the object is on the active or flushing lists
822 * (has pending rendering), and is not set if it's on inactive (ready
823 * to be unbound).
824 */
825 unsigned int active:1;
826
827 /**
828 * This is set if the object has been written to since last bound
829 * to the GTT
830 */
831 unsigned int dirty:1;
832
833 /**
834 * This is set if the object has been written to since the last
835 * GPU flush.
836 */
837 unsigned int pending_gpu_write:1;
838
839 /**
840 * Fence register bits (if any) for this object. Will be set
841 * as needed when mapped into the GTT.
842 * Protected by dev->struct_mutex.
843 */
844 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
845
846 /**
847 * Advice: are the backing pages purgeable?
848 */
849 unsigned int madv:2;
850
851 /**
852 * Current tiling mode for the object.
853 */
854 unsigned int tiling_mode:2;
855 unsigned int tiling_changed:1;
856
857 /** How many users have pinned this object in GTT space. The following
858 * users can each hold at most one reference: pwrite/pread, pin_ioctl
859 * (via user_pin_count), execbuffer (objects are not allowed multiple
860 * times for the same batchbuffer), and the framebuffer code. When
861 * switching/pageflipping, the framebuffer code has at most two buffers
862 * pinned per crtc.
863 *
864 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
865 * bits with absolutely no headroom. So use 4 bits. */
866 unsigned int pin_count:4;
867#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
868
869 /**
870 * Is the object at the current location in the gtt mappable and
871 * fenceable? Used to avoid costly recalculations.
872 */
873 unsigned int map_and_fenceable:1;
874
875 /**
876 * Whether the current gtt mapping needs to be mappable (and isn't just
877 * mappable by accident). Track pin and fault separate for a more
878 * accurate mappable working set.
879 */
880 unsigned int fault_mappable:1;
881 unsigned int pin_mappable:1;
882
883 /*
884 * Is the GPU currently using a fence to access this buffer,
885 */
886 unsigned int pending_fenced_gpu_access:1;
887 unsigned int fenced_gpu_access:1;
888
889 unsigned int cache_level:2;
890
891 unsigned int has_aliasing_ppgtt_mapping:1;
892 unsigned int has_global_gtt_mapping:1;
893
894 struct page **pages;
895
896 /**
897 * DMAR support
898 */
899 struct scatterlist *sg_list;
900 int num_sg;
901
902 /**
903 * Used for performing relocations during execbuffer insertion.
904 */
905 struct hlist_node exec_node;
906 unsigned long exec_handle;
907 struct drm_i915_gem_exec_object2 *exec_entry;
908
909 /**
910 * Current offset of the object in GTT space.
911 *
912 * This is the same as gtt_space->start
913 */
914 uint32_t gtt_offset;
915
916 /** Breadcrumb of last rendering to the buffer. */
917 uint32_t last_rendering_seqno;
918 struct intel_ring_buffer *ring;
919
920 /** Breadcrumb of last fenced GPU access to the buffer. */
921 uint32_t last_fenced_seqno;
922 struct intel_ring_buffer *last_fenced_ring;
923
924 /** Current tiling stride for the object, if it's tiled. */
925 uint32_t stride;
926
927 /** Record of address bit 17 of each page at last unbind. */
928 unsigned long *bit_17;
929
930
931 /**
932 * If present, while GEM_DOMAIN_CPU is in the read domain this array
933 * flags which individual pages are valid.
934 */
935 uint8_t *page_cpu_valid;
936
937 /** User space pin count and filp owning the pin */
938 uint32_t user_pin_count;
939 struct drm_file *pin_filp;
940
941 /** for phy allocated objects */
942 struct drm_i915_gem_phys_object *phys_obj;
943
944 /**
945 * Number of crtcs where this object is currently the fb, but
946 * will be page flipped away on the next vblank. When it
947 * reaches 0, dev_priv->pending_flip_queue will be woken up.
948 */
949 atomic_t pending_flip;
950};
951
952#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
953
954/**
955 * Request queue structure.
956 *
957 * The request queue allows us to note sequence numbers that have been emitted
958 * and may be associated with active buffers to be retired.
959 *
960 * By keeping this list, we can avoid having to do questionable
961 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
962 * an emission time with seqnos for tracking how far ahead of the GPU we are.
963 */
964struct drm_i915_gem_request {
965 /** On Which ring this request was generated */
966 struct intel_ring_buffer *ring;
967
968 /** GEM sequence number associated with this request. */
969 uint32_t seqno;
970
971 /** Postion in the ringbuffer of the end of the request */
972 u32 tail;
973
974 /** Time at which this request was emitted, in jiffies. */
975 unsigned long emitted_jiffies;
976
977 /** global list entry for this request */
978 struct list_head list;
979
980 struct drm_i915_file_private *file_priv;
981 /** file_priv list entry for this request */
982 struct list_head client_list;
983};
984
985struct drm_i915_file_private {
986 struct {
987 struct spinlock lock;
988 struct list_head request_list;
989 } mm;
990};
991
992#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
993
994#define IS_I830(dev) ((dev)->pci_device == 0x3577)
995#define IS_845G(dev) ((dev)->pci_device == 0x2562)
996#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
997#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
998#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
999#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1000#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1001#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1002#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1003#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1004#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1005#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1006#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1007#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1008#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1009#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1010#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1011#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1012#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1013#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1014
1015/*
1016 * The genX designation typically refers to the render engine, so render
1017 * capability related checks should use IS_GEN, while display and other checks
1018 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1019 * chips, etc.).
1020 */
1021#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1022#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1023#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1024#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1025#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1026#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1027
1028#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1029#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1030#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1031#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1032
1033#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6)
1034
1035#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1036#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1037
1038/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1039 * rows, which changed the alignment requirements and fence programming.
1040 */
1041#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1042 IS_I915GM(dev)))
1043#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1044#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1045#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1046#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1047#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1048#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1049/* dsparb controlled by hw only */
1050#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1051
1052#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1053#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1054#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1055
1056#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
1057#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1058
1059#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1060#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1061#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1062
1063#include "i915_trace.h"
1064
1065extern struct drm_ioctl_desc i915_ioctls[];
1066extern int i915_max_ioctl;
1067extern unsigned int i915_fbpercrtc __always_unused;
1068extern int i915_panel_ignore_lid __read_mostly;
1069extern unsigned int i915_powersave __read_mostly;
1070extern int i915_semaphores __read_mostly;
1071extern unsigned int i915_lvds_downclock __read_mostly;
1072extern int i915_lvds_channel_mode __read_mostly;
1073extern int i915_panel_use_ssc __read_mostly;
1074extern int i915_vbt_sdvo_panel_type __read_mostly;
1075extern int i915_enable_rc6 __read_mostly;
1076extern int i915_enable_fbc __read_mostly;
1077extern bool i915_enable_hangcheck __read_mostly;
1078extern bool i915_enable_ppgtt __read_mostly;
1079
1080extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1081extern int i915_resume(struct drm_device *dev);
1082extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1083extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1084
1085 /* i915_dma.c */
1086extern void i915_kernel_lost_context(struct drm_device * dev);
1087extern int i915_driver_load(struct drm_device *, unsigned long flags);
1088extern int i915_driver_unload(struct drm_device *);
1089extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1090extern void i915_driver_lastclose(struct drm_device * dev);
1091extern void i915_driver_preclose(struct drm_device *dev,
1092 struct drm_file *file_priv);
1093extern void i915_driver_postclose(struct drm_device *dev,
1094 struct drm_file *file_priv);
1095extern int i915_driver_device_is_agp(struct drm_device * dev);
1096extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1097 unsigned long arg);
1098extern int i915_emit_box(struct drm_device *dev,
1099 struct drm_clip_rect *box,
1100 int DR1, int DR4);
1101extern int i915_reset(struct drm_device *dev, u8 flags);
1102extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1103extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1104extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1105extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1106
1107
1108/* i915_irq.c */
1109void i915_hangcheck_elapsed(unsigned long data);
1110void i915_handle_error(struct drm_device *dev, bool wedged);
1111extern int i915_irq_emit(struct drm_device *dev, void *data,
1112 struct drm_file *file_priv);
1113extern int i915_irq_wait(struct drm_device *dev, void *data,
1114 struct drm_file *file_priv);
1115
1116extern void intel_irq_init(struct drm_device *dev);
1117
1118extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1119 struct drm_file *file_priv);
1120extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1121 struct drm_file *file_priv);
1122extern int i915_vblank_swap(struct drm_device *dev, void *data,
1123 struct drm_file *file_priv);
1124
1125void
1126i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1127
1128void
1129i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1130
1131void intel_enable_asle(struct drm_device *dev);
1132
1133#ifdef CONFIG_DEBUG_FS
1134extern void i915_destroy_error_state(struct drm_device *dev);
1135#else
1136#define i915_destroy_error_state(x)
1137#endif
1138
1139
1140/* i915_gem.c */
1141int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1142 struct drm_file *file_priv);
1143int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1144 struct drm_file *file_priv);
1145int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1146 struct drm_file *file_priv);
1147int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1148 struct drm_file *file_priv);
1149int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1150 struct drm_file *file_priv);
1151int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1152 struct drm_file *file_priv);
1153int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1154 struct drm_file *file_priv);
1155int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1156 struct drm_file *file_priv);
1157int i915_gem_execbuffer(struct drm_device *dev, void *data,
1158 struct drm_file *file_priv);
1159int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1160 struct drm_file *file_priv);
1161int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1162 struct drm_file *file_priv);
1163int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1164 struct drm_file *file_priv);
1165int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1166 struct drm_file *file_priv);
1167int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1168 struct drm_file *file_priv);
1169int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1170 struct drm_file *file_priv);
1171int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1172 struct drm_file *file_priv);
1173int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1174 struct drm_file *file_priv);
1175int i915_gem_set_tiling(struct drm_device *dev, void *data,
1176 struct drm_file *file_priv);
1177int i915_gem_get_tiling(struct drm_device *dev, void *data,
1178 struct drm_file *file_priv);
1179int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1180 struct drm_file *file_priv);
1181void i915_gem_load(struct drm_device *dev);
1182int i915_gem_init_object(struct drm_gem_object *obj);
1183int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring,
1184 uint32_t invalidate_domains,
1185 uint32_t flush_domains);
1186struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1187 size_t size);
1188void i915_gem_free_object(struct drm_gem_object *obj);
1189int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1190 uint32_t alignment,
1191 bool map_and_fenceable);
1192void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1193int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1194void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1195void i915_gem_lastclose(struct drm_device *dev);
1196
1197int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1198int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj);
1199void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1200 struct intel_ring_buffer *ring,
1201 u32 seqno);
1202
1203int i915_gem_dumb_create(struct drm_file *file_priv,
1204 struct drm_device *dev,
1205 struct drm_mode_create_dumb *args);
1206int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1207 uint32_t handle, uint64_t *offset);
1208int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1209 uint32_t handle);
1210/**
1211 * Returns true if seq1 is later than seq2.
1212 */
1213static inline bool
1214i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1215{
1216 return (int32_t)(seq1 - seq2) >= 0;
1217}
1218
1219u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring);
1220
1221int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
1222 struct intel_ring_buffer *pipelined);
1223int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1224
1225static inline void
1226i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1227{
1228 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1229 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1230 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1231 }
1232}
1233
1234static inline void
1235i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1236{
1237 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1238 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1239 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1240 }
1241}
1242
1243void i915_gem_retire_requests(struct drm_device *dev);
1244void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1245
1246void i915_gem_reset(struct drm_device *dev);
1247void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1248int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1249 uint32_t read_domains,
1250 uint32_t write_domain);
1251int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1252int __must_check i915_gem_init_hw(struct drm_device *dev);
1253void i915_gem_init_swizzling(struct drm_device *dev);
1254void i915_gem_init_ppgtt(struct drm_device *dev);
1255void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1256int __must_check i915_gpu_idle(struct drm_device *dev, bool do_retire);
1257int __must_check i915_gem_idle(struct drm_device *dev);
1258int __must_check i915_add_request(struct intel_ring_buffer *ring,
1259 struct drm_file *file,
1260 struct drm_i915_gem_request *request);
1261int __must_check i915_wait_request(struct intel_ring_buffer *ring,
1262 uint32_t seqno,
1263 bool do_retire);
1264int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1265int __must_check
1266i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1267 bool write);
1268int __must_check
1269i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1270 u32 alignment,
1271 struct intel_ring_buffer *pipelined);
1272int i915_gem_attach_phys_object(struct drm_device *dev,
1273 struct drm_i915_gem_object *obj,
1274 int id,
1275 int align);
1276void i915_gem_detach_phys_object(struct drm_device *dev,
1277 struct drm_i915_gem_object *obj);
1278void i915_gem_free_all_phys_object(struct drm_device *dev);
1279void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1280
1281uint32_t
1282i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1283 uint32_t size,
1284 int tiling_mode);
1285
1286int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1287 enum i915_cache_level cache_level);
1288
1289/* i915_gem_gtt.c */
1290int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
1291void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1292void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1293 struct drm_i915_gem_object *obj,
1294 enum i915_cache_level cache_level);
1295void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1296 struct drm_i915_gem_object *obj);
1297
1298void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1299int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1300void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1301 enum i915_cache_level cache_level);
1302void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1303void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1304void i915_gem_init_global_gtt(struct drm_device *dev,
1305 unsigned long start,
1306 unsigned long mappable_end,
1307 unsigned long end);
1308
1309/* i915_gem_evict.c */
1310int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1311 unsigned alignment, bool mappable);
1312int __must_check i915_gem_evict_everything(struct drm_device *dev,
1313 bool purgeable_only);
1314int __must_check i915_gem_evict_inactive(struct drm_device *dev,
1315 bool purgeable_only);
1316
1317/* i915_gem_tiling.c */
1318void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1319void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1320void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1321
1322/* i915_gem_debug.c */
1323void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1324 const char *where, uint32_t mark);
1325#if WATCH_LISTS
1326int i915_verify_lists(struct drm_device *dev);
1327#else
1328#define i915_verify_lists(dev) 0
1329#endif
1330void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1331 int handle);
1332void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1333 const char *where, uint32_t mark);
1334
1335/* i915_debugfs.c */
1336int i915_debugfs_init(struct drm_minor *minor);
1337void i915_debugfs_cleanup(struct drm_minor *minor);
1338
1339/* i915_suspend.c */
1340extern int i915_save_state(struct drm_device *dev);
1341extern int i915_restore_state(struct drm_device *dev);
1342
1343/* i915_suspend.c */
1344extern int i915_save_state(struct drm_device *dev);
1345extern int i915_restore_state(struct drm_device *dev);
1346
1347/* intel_i2c.c */
1348extern int intel_setup_gmbus(struct drm_device *dev);
1349extern void intel_teardown_gmbus(struct drm_device *dev);
1350extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1351extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1352extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1353{
1354 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1355}
1356extern void intel_i2c_reset(struct drm_device *dev);
1357
1358/* intel_opregion.c */
1359extern int intel_opregion_setup(struct drm_device *dev);
1360#ifdef CONFIG_ACPI
1361extern void intel_opregion_init(struct drm_device *dev);
1362extern void intel_opregion_fini(struct drm_device *dev);
1363extern void intel_opregion_asle_intr(struct drm_device *dev);
1364extern void intel_opregion_gse_intr(struct drm_device *dev);
1365extern void intel_opregion_enable_asle(struct drm_device *dev);
1366#else
1367static inline void intel_opregion_init(struct drm_device *dev) { return; }
1368static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1369static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1370static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1371static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1372#endif
1373
1374/* intel_acpi.c */
1375#ifdef CONFIG_ACPI
1376extern void intel_register_dsm_handler(void);
1377extern void intel_unregister_dsm_handler(void);
1378#else
1379static inline void intel_register_dsm_handler(void) { return; }
1380static inline void intel_unregister_dsm_handler(void) { return; }
1381#endif /* CONFIG_ACPI */
1382
1383/* modesetting */
1384extern void intel_modeset_init(struct drm_device *dev);
1385extern void intel_modeset_gem_init(struct drm_device *dev);
1386extern void intel_modeset_cleanup(struct drm_device *dev);
1387extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1388extern bool intel_fbc_enabled(struct drm_device *dev);
1389extern void intel_disable_fbc(struct drm_device *dev);
1390extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1391extern void ironlake_init_pch_refclk(struct drm_device *dev);
1392extern void ironlake_enable_rc6(struct drm_device *dev);
1393extern void gen6_set_rps(struct drm_device *dev, u8 val);
1394extern void intel_detect_pch(struct drm_device *dev);
1395extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1396
1397extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1398extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv);
1399extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1400extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv);
1401
1402/* overlay */
1403#ifdef CONFIG_DEBUG_FS
1404extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1405extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1406
1407extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1408extern void intel_display_print_error_state(struct seq_file *m,
1409 struct drm_device *dev,
1410 struct intel_display_error_state *error);
1411#endif
1412
1413#define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1414
1415#define BEGIN_LP_RING(n) \
1416 intel_ring_begin(LP_RING(dev_priv), (n))
1417
1418#define OUT_RING(x) \
1419 intel_ring_emit(LP_RING(dev_priv), x)
1420
1421#define ADVANCE_LP_RING() \
1422 intel_ring_advance(LP_RING(dev_priv))
1423
1424/**
1425 * Lock test for when it's just for synchronization of ring access.
1426 *
1427 * In that case, we don't need to do it when GEM is initialized as nobody else
1428 * has access to the ring.
1429 */
1430#define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
1431 if (LP_RING(dev->dev_private)->obj == NULL) \
1432 LOCK_TEST_WITH_RETURN(dev, file); \
1433} while (0)
1434
1435/* On SNB platform, before reading ring registers forcewake bit
1436 * must be set to prevent GT core from power down and stale values being
1437 * returned.
1438 */
1439void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1440void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1441int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1442
1443#define __i915_read(x, y) \
1444 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1445
1446__i915_read(8, b)
1447__i915_read(16, w)
1448__i915_read(32, l)
1449__i915_read(64, q)
1450#undef __i915_read
1451
1452#define __i915_write(x, y) \
1453 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1454
1455__i915_write(8, b)
1456__i915_write(16, w)
1457__i915_write(32, l)
1458__i915_write(64, q)
1459#undef __i915_write
1460
1461#define I915_READ8(reg) i915_read8(dev_priv, (reg))
1462#define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1463
1464#define I915_READ16(reg) i915_read16(dev_priv, (reg))
1465#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1466#define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1467#define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1468
1469#define I915_READ(reg) i915_read32(dev_priv, (reg))
1470#define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1471#define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1472#define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1473
1474#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1475#define I915_READ64(reg) i915_read64(dev_priv, (reg))
1476
1477#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1478#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1479
1480
1481#endif
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