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drm/i915: Avoid clearing preallocated regions from the GTT
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_drv.h
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1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include "i915_reg.h"
34#include "intel_bios.h"
35#include "intel_ringbuffer.h"
36#include <linux/io-mapping.h>
37#include <linux/i2c.h>
38#include <linux/i2c-algo-bit.h>
39#include <drm/intel-gtt.h>
40#include <linux/backlight.h>
41#include <linux/intel-iommu.h>
42#include <linux/kref.h>
43
44/* General customization:
45 */
46
47#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
48
49#define DRIVER_NAME "i915"
50#define DRIVER_DESC "Intel Graphics"
51#define DRIVER_DATE "20080730"
52
53enum pipe {
54 PIPE_A = 0,
55 PIPE_B,
56 PIPE_C,
57 I915_MAX_PIPES
58};
59#define pipe_name(p) ((p) + 'A')
60
61enum transcoder {
62 TRANSCODER_A = 0,
63 TRANSCODER_B,
64 TRANSCODER_C,
65 TRANSCODER_EDP = 0xF,
66};
67#define transcoder_name(t) ((t) + 'A')
68
69enum plane {
70 PLANE_A = 0,
71 PLANE_B,
72 PLANE_C,
73};
74#define plane_name(p) ((p) + 'A')
75
76enum port {
77 PORT_A = 0,
78 PORT_B,
79 PORT_C,
80 PORT_D,
81 PORT_E,
82 I915_MAX_PORTS
83};
84#define port_name(p) ((p) + 'A')
85
86#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
87
88#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
89
90#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
91 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
92 if ((intel_encoder)->base.crtc == (__crtc))
93
94struct intel_pch_pll {
95 int refcount; /* count of number of CRTCs sharing this PLL */
96 int active; /* count of number of active CRTCs (i.e. DPMS on) */
97 bool on; /* is the PLL actually active? Disabled during modeset */
98 int pll_reg;
99 int fp0_reg;
100 int fp1_reg;
101};
102#define I915_NUM_PLLS 2
103
104struct intel_ddi_plls {
105 int spll_refcount;
106 int wrpll1_refcount;
107 int wrpll2_refcount;
108};
109
110/* Interface history:
111 *
112 * 1.1: Original.
113 * 1.2: Add Power Management
114 * 1.3: Add vblank support
115 * 1.4: Fix cmdbuffer path, add heap destroy
116 * 1.5: Add vblank pipe configuration
117 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
118 * - Support vertical blank on secondary display pipe
119 */
120#define DRIVER_MAJOR 1
121#define DRIVER_MINOR 6
122#define DRIVER_PATCHLEVEL 0
123
124#define WATCH_COHERENCY 0
125#define WATCH_LISTS 0
126#define WATCH_GTT 0
127
128#define I915_GEM_PHYS_CURSOR_0 1
129#define I915_GEM_PHYS_CURSOR_1 2
130#define I915_GEM_PHYS_OVERLAY_REGS 3
131#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
132
133struct drm_i915_gem_phys_object {
134 int id;
135 struct page **page_list;
136 drm_dma_handle_t *handle;
137 struct drm_i915_gem_object *cur_obj;
138};
139
140struct opregion_header;
141struct opregion_acpi;
142struct opregion_swsci;
143struct opregion_asle;
144struct drm_i915_private;
145
146struct intel_opregion {
147 struct opregion_header __iomem *header;
148 struct opregion_acpi __iomem *acpi;
149 struct opregion_swsci __iomem *swsci;
150 struct opregion_asle __iomem *asle;
151 void __iomem *vbt;
152 u32 __iomem *lid_state;
153};
154#define OPREGION_SIZE (8*1024)
155
156struct intel_overlay;
157struct intel_overlay_error_state;
158
159struct drm_i915_master_private {
160 drm_local_map_t *sarea;
161 struct _drm_i915_sarea *sarea_priv;
162};
163#define I915_FENCE_REG_NONE -1
164#define I915_MAX_NUM_FENCES 16
165/* 16 fences + sign bit for FENCE_REG_NONE */
166#define I915_MAX_NUM_FENCE_BITS 5
167
168struct drm_i915_fence_reg {
169 struct list_head lru_list;
170 struct drm_i915_gem_object *obj;
171 int pin_count;
172};
173
174struct sdvo_device_mapping {
175 u8 initialized;
176 u8 dvo_port;
177 u8 slave_addr;
178 u8 dvo_wiring;
179 u8 i2c_pin;
180 u8 ddc_pin;
181};
182
183struct intel_display_error_state;
184
185struct drm_i915_error_state {
186 struct kref ref;
187 u32 eir;
188 u32 pgtbl_er;
189 u32 ier;
190 u32 ccid;
191 bool waiting[I915_NUM_RINGS];
192 u32 pipestat[I915_MAX_PIPES];
193 u32 tail[I915_NUM_RINGS];
194 u32 head[I915_NUM_RINGS];
195 u32 ipeir[I915_NUM_RINGS];
196 u32 ipehr[I915_NUM_RINGS];
197 u32 instdone[I915_NUM_RINGS];
198 u32 acthd[I915_NUM_RINGS];
199 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
200 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
201 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
202 /* our own tracking of ring head and tail */
203 u32 cpu_ring_head[I915_NUM_RINGS];
204 u32 cpu_ring_tail[I915_NUM_RINGS];
205 u32 error; /* gen6+ */
206 u32 err_int; /* gen7 */
207 u32 instpm[I915_NUM_RINGS];
208 u32 instps[I915_NUM_RINGS];
209 u32 extra_instdone[I915_NUM_INSTDONE_REG];
210 u32 seqno[I915_NUM_RINGS];
211 u64 bbaddr;
212 u32 fault_reg[I915_NUM_RINGS];
213 u32 done_reg;
214 u32 faddr[I915_NUM_RINGS];
215 u64 fence[I915_MAX_NUM_FENCES];
216 struct timeval time;
217 struct drm_i915_error_ring {
218 struct drm_i915_error_object {
219 int page_count;
220 u32 gtt_offset;
221 u32 *pages[0];
222 } *ringbuffer, *batchbuffer;
223 struct drm_i915_error_request {
224 long jiffies;
225 u32 seqno;
226 u32 tail;
227 } *requests;
228 int num_requests;
229 } ring[I915_NUM_RINGS];
230 struct drm_i915_error_buffer {
231 u32 size;
232 u32 name;
233 u32 rseqno, wseqno;
234 u32 gtt_offset;
235 u32 read_domains;
236 u32 write_domain;
237 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
238 s32 pinned:2;
239 u32 tiling:2;
240 u32 dirty:1;
241 u32 purgeable:1;
242 s32 ring:4;
243 u32 cache_level:2;
244 } *active_bo, *pinned_bo;
245 u32 active_bo_count, pinned_bo_count;
246 struct intel_overlay_error_state *overlay;
247 struct intel_display_error_state *display;
248};
249
250struct drm_i915_display_funcs {
251 bool (*fbc_enabled)(struct drm_device *dev);
252 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
253 void (*disable_fbc)(struct drm_device *dev);
254 int (*get_display_clock_speed)(struct drm_device *dev);
255 int (*get_fifo_size)(struct drm_device *dev, int plane);
256 void (*update_wm)(struct drm_device *dev);
257 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
258 uint32_t sprite_width, int pixel_size);
259 void (*update_linetime_wm)(struct drm_device *dev, int pipe,
260 struct drm_display_mode *mode);
261 void (*modeset_global_resources)(struct drm_device *dev);
262 int (*crtc_mode_set)(struct drm_crtc *crtc,
263 struct drm_display_mode *mode,
264 struct drm_display_mode *adjusted_mode,
265 int x, int y,
266 struct drm_framebuffer *old_fb);
267 void (*crtc_enable)(struct drm_crtc *crtc);
268 void (*crtc_disable)(struct drm_crtc *crtc);
269 void (*off)(struct drm_crtc *crtc);
270 void (*write_eld)(struct drm_connector *connector,
271 struct drm_crtc *crtc);
272 void (*fdi_link_train)(struct drm_crtc *crtc);
273 void (*init_clock_gating)(struct drm_device *dev);
274 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
275 struct drm_framebuffer *fb,
276 struct drm_i915_gem_object *obj);
277 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
278 int x, int y);
279 /* clock updates for mode set */
280 /* cursor updates */
281 /* render clock increase/decrease */
282 /* display clock increase/decrease */
283 /* pll clock increase/decrease */
284};
285
286struct drm_i915_gt_funcs {
287 void (*force_wake_get)(struct drm_i915_private *dev_priv);
288 void (*force_wake_put)(struct drm_i915_private *dev_priv);
289};
290
291#define DEV_INFO_FLAGS \
292 DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \
293 DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \
294 DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \
295 DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \
296 DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \
297 DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \
298 DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \
299 DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \
300 DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \
301 DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \
302 DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \
303 DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \
304 DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \
305 DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \
306 DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \
307 DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \
308 DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \
309 DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \
310 DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \
311 DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \
312 DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \
313 DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \
314 DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \
315 DEV_INFO_FLAG(has_llc)
316
317struct intel_device_info {
318 u8 gen;
319 u8 is_mobile:1;
320 u8 is_i85x:1;
321 u8 is_i915g:1;
322 u8 is_i945gm:1;
323 u8 is_g33:1;
324 u8 need_gfx_hws:1;
325 u8 is_g4x:1;
326 u8 is_pineview:1;
327 u8 is_broadwater:1;
328 u8 is_crestline:1;
329 u8 is_ivybridge:1;
330 u8 is_valleyview:1;
331 u8 has_force_wake:1;
332 u8 is_haswell:1;
333 u8 has_fbc:1;
334 u8 has_pipe_cxsr:1;
335 u8 has_hotplug:1;
336 u8 cursor_needs_physical:1;
337 u8 has_overlay:1;
338 u8 overlay_needs_physical:1;
339 u8 supports_tv:1;
340 u8 has_bsd_ring:1;
341 u8 has_blt_ring:1;
342 u8 has_llc:1;
343};
344
345#define I915_PPGTT_PD_ENTRIES 512
346#define I915_PPGTT_PT_ENTRIES 1024
347struct i915_hw_ppgtt {
348 struct drm_device *dev;
349 unsigned num_pd_entries;
350 struct page **pt_pages;
351 uint32_t pd_offset;
352 dma_addr_t *pt_dma_addr;
353 dma_addr_t scratch_page_dma_addr;
354};
355
356
357/* This must match up with the value previously used for execbuf2.rsvd1. */
358#define DEFAULT_CONTEXT_ID 0
359struct i915_hw_context {
360 int id;
361 bool is_initialized;
362 struct drm_i915_file_private *file_priv;
363 struct intel_ring_buffer *ring;
364 struct drm_i915_gem_object *obj;
365};
366
367enum no_fbc_reason {
368 FBC_NO_OUTPUT, /* no outputs enabled to compress */
369 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
370 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
371 FBC_MODE_TOO_LARGE, /* mode too large for compression */
372 FBC_BAD_PLANE, /* fbc not supported on plane */
373 FBC_NOT_TILED, /* buffer not tiled */
374 FBC_MULTIPLE_PIPES, /* more than one pipe active */
375 FBC_MODULE_PARAM,
376};
377
378enum intel_pch {
379 PCH_NONE = 0, /* No PCH present */
380 PCH_IBX, /* Ibexpeak PCH */
381 PCH_CPT, /* Cougarpoint PCH */
382 PCH_LPT, /* Lynxpoint PCH */
383};
384
385#define QUIRK_PIPEA_FORCE (1<<0)
386#define QUIRK_LVDS_SSC_DISABLE (1<<1)
387#define QUIRK_INVERT_BRIGHTNESS (1<<2)
388
389struct intel_fbdev;
390struct intel_fbc_work;
391
392struct intel_gmbus {
393 struct i2c_adapter adapter;
394 u32 force_bit;
395 u32 reg0;
396 u32 gpio_reg;
397 struct i2c_algo_bit_data bit_algo;
398 struct drm_i915_private *dev_priv;
399};
400
401struct i915_suspend_saved_registers {
402 u8 saveLBB;
403 u32 saveDSPACNTR;
404 u32 saveDSPBCNTR;
405 u32 saveDSPARB;
406 u32 savePIPEACONF;
407 u32 savePIPEBCONF;
408 u32 savePIPEASRC;
409 u32 savePIPEBSRC;
410 u32 saveFPA0;
411 u32 saveFPA1;
412 u32 saveDPLL_A;
413 u32 saveDPLL_A_MD;
414 u32 saveHTOTAL_A;
415 u32 saveHBLANK_A;
416 u32 saveHSYNC_A;
417 u32 saveVTOTAL_A;
418 u32 saveVBLANK_A;
419 u32 saveVSYNC_A;
420 u32 saveBCLRPAT_A;
421 u32 saveTRANSACONF;
422 u32 saveTRANS_HTOTAL_A;
423 u32 saveTRANS_HBLANK_A;
424 u32 saveTRANS_HSYNC_A;
425 u32 saveTRANS_VTOTAL_A;
426 u32 saveTRANS_VBLANK_A;
427 u32 saveTRANS_VSYNC_A;
428 u32 savePIPEASTAT;
429 u32 saveDSPASTRIDE;
430 u32 saveDSPASIZE;
431 u32 saveDSPAPOS;
432 u32 saveDSPAADDR;
433 u32 saveDSPASURF;
434 u32 saveDSPATILEOFF;
435 u32 savePFIT_PGM_RATIOS;
436 u32 saveBLC_HIST_CTL;
437 u32 saveBLC_PWM_CTL;
438 u32 saveBLC_PWM_CTL2;
439 u32 saveBLC_CPU_PWM_CTL;
440 u32 saveBLC_CPU_PWM_CTL2;
441 u32 saveFPB0;
442 u32 saveFPB1;
443 u32 saveDPLL_B;
444 u32 saveDPLL_B_MD;
445 u32 saveHTOTAL_B;
446 u32 saveHBLANK_B;
447 u32 saveHSYNC_B;
448 u32 saveVTOTAL_B;
449 u32 saveVBLANK_B;
450 u32 saveVSYNC_B;
451 u32 saveBCLRPAT_B;
452 u32 saveTRANSBCONF;
453 u32 saveTRANS_HTOTAL_B;
454 u32 saveTRANS_HBLANK_B;
455 u32 saveTRANS_HSYNC_B;
456 u32 saveTRANS_VTOTAL_B;
457 u32 saveTRANS_VBLANK_B;
458 u32 saveTRANS_VSYNC_B;
459 u32 savePIPEBSTAT;
460 u32 saveDSPBSTRIDE;
461 u32 saveDSPBSIZE;
462 u32 saveDSPBPOS;
463 u32 saveDSPBADDR;
464 u32 saveDSPBSURF;
465 u32 saveDSPBTILEOFF;
466 u32 saveVGA0;
467 u32 saveVGA1;
468 u32 saveVGA_PD;
469 u32 saveVGACNTRL;
470 u32 saveADPA;
471 u32 saveLVDS;
472 u32 savePP_ON_DELAYS;
473 u32 savePP_OFF_DELAYS;
474 u32 saveDVOA;
475 u32 saveDVOB;
476 u32 saveDVOC;
477 u32 savePP_ON;
478 u32 savePP_OFF;
479 u32 savePP_CONTROL;
480 u32 savePP_DIVISOR;
481 u32 savePFIT_CONTROL;
482 u32 save_palette_a[256];
483 u32 save_palette_b[256];
484 u32 saveDPFC_CB_BASE;
485 u32 saveFBC_CFB_BASE;
486 u32 saveFBC_LL_BASE;
487 u32 saveFBC_CONTROL;
488 u32 saveFBC_CONTROL2;
489 u32 saveIER;
490 u32 saveIIR;
491 u32 saveIMR;
492 u32 saveDEIER;
493 u32 saveDEIMR;
494 u32 saveGTIER;
495 u32 saveGTIMR;
496 u32 saveFDI_RXA_IMR;
497 u32 saveFDI_RXB_IMR;
498 u32 saveCACHE_MODE_0;
499 u32 saveMI_ARB_STATE;
500 u32 saveSWF0[16];
501 u32 saveSWF1[16];
502 u32 saveSWF2[3];
503 u8 saveMSR;
504 u8 saveSR[8];
505 u8 saveGR[25];
506 u8 saveAR_INDEX;
507 u8 saveAR[21];
508 u8 saveDACMASK;
509 u8 saveCR[37];
510 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
511 u32 saveCURACNTR;
512 u32 saveCURAPOS;
513 u32 saveCURABASE;
514 u32 saveCURBCNTR;
515 u32 saveCURBPOS;
516 u32 saveCURBBASE;
517 u32 saveCURSIZE;
518 u32 saveDP_B;
519 u32 saveDP_C;
520 u32 saveDP_D;
521 u32 savePIPEA_GMCH_DATA_M;
522 u32 savePIPEB_GMCH_DATA_M;
523 u32 savePIPEA_GMCH_DATA_N;
524 u32 savePIPEB_GMCH_DATA_N;
525 u32 savePIPEA_DP_LINK_M;
526 u32 savePIPEB_DP_LINK_M;
527 u32 savePIPEA_DP_LINK_N;
528 u32 savePIPEB_DP_LINK_N;
529 u32 saveFDI_RXA_CTL;
530 u32 saveFDI_TXA_CTL;
531 u32 saveFDI_RXB_CTL;
532 u32 saveFDI_TXB_CTL;
533 u32 savePFA_CTL_1;
534 u32 savePFB_CTL_1;
535 u32 savePFA_WIN_SZ;
536 u32 savePFB_WIN_SZ;
537 u32 savePFA_WIN_POS;
538 u32 savePFB_WIN_POS;
539 u32 savePCH_DREF_CONTROL;
540 u32 saveDISP_ARB_CTL;
541 u32 savePIPEA_DATA_M1;
542 u32 savePIPEA_DATA_N1;
543 u32 savePIPEA_LINK_M1;
544 u32 savePIPEA_LINK_N1;
545 u32 savePIPEB_DATA_M1;
546 u32 savePIPEB_DATA_N1;
547 u32 savePIPEB_LINK_M1;
548 u32 savePIPEB_LINK_N1;
549 u32 saveMCHBAR_RENDER_STANDBY;
550 u32 savePCH_PORT_HOTPLUG;
551};
552
553struct intel_gen6_power_mgmt {
554 struct work_struct work;
555 u32 pm_iir;
556 /* lock - irqsave spinlock that protectects the work_struct and
557 * pm_iir. */
558 spinlock_t lock;
559
560 /* The below variables an all the rps hw state are protected by
561 * dev->struct mutext. */
562 u8 cur_delay;
563 u8 min_delay;
564 u8 max_delay;
565
566 struct delayed_work delayed_resume_work;
567
568 /*
569 * Protects RPS/RC6 register access and PCU communication.
570 * Must be taken after struct_mutex if nested.
571 */
572 struct mutex hw_lock;
573};
574
575struct intel_ilk_power_mgmt {
576 u8 cur_delay;
577 u8 min_delay;
578 u8 max_delay;
579 u8 fmax;
580 u8 fstart;
581
582 u64 last_count1;
583 unsigned long last_time1;
584 unsigned long chipset_power;
585 u64 last_count2;
586 struct timespec last_time2;
587 unsigned long gfx_power;
588 u8 corr;
589
590 int c_m;
591 int r_t;
592
593 struct drm_i915_gem_object *pwrctx;
594 struct drm_i915_gem_object *renderctx;
595};
596
597struct i915_dri1_state {
598 unsigned allow_batchbuffer : 1;
599 u32 __iomem *gfx_hws_cpu_addr;
600
601 unsigned int cpp;
602 int back_offset;
603 int front_offset;
604 int current_page;
605 int page_flipping;
606
607 uint32_t counter;
608};
609
610struct intel_l3_parity {
611 u32 *remap_info;
612 struct work_struct error_work;
613};
614
615typedef struct drm_i915_private {
616 struct drm_device *dev;
617
618 const struct intel_device_info *info;
619
620 int relative_constants_mode;
621
622 void __iomem *regs;
623
624 struct drm_i915_gt_funcs gt;
625 /** gt_fifo_count and the subsequent register write are synchronized
626 * with dev->struct_mutex. */
627 unsigned gt_fifo_count;
628 /** forcewake_count is protected by gt_lock */
629 unsigned forcewake_count;
630 /** gt_lock is also taken in irq contexts. */
631 spinlock_t gt_lock;
632
633 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
634
635 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
636 * controller on different i2c buses. */
637 struct mutex gmbus_mutex;
638
639 /**
640 * Base address of the gmbus and gpio block.
641 */
642 uint32_t gpio_mmio_base;
643
644 struct pci_dev *bridge_dev;
645 struct intel_ring_buffer ring[I915_NUM_RINGS];
646 uint32_t next_seqno;
647
648 drm_dma_handle_t *status_page_dmah;
649 struct resource mch_res;
650
651 atomic_t irq_received;
652
653 /* protects the irq masks */
654 spinlock_t irq_lock;
655
656 /* DPIO indirect register protection */
657 spinlock_t dpio_lock;
658
659 /** Cached value of IMR to avoid reads in updating the bitfield */
660 u32 pipestat[2];
661 u32 irq_mask;
662 u32 gt_irq_mask;
663 u32 pch_irq_mask;
664
665 u32 hotplug_supported_mask;
666 struct work_struct hotplug_work;
667
668 int num_pipe;
669 int num_pch_pll;
670
671 /* For hangcheck timer */
672#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
673#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
674 struct timer_list hangcheck_timer;
675 int hangcheck_count;
676 uint32_t last_acthd[I915_NUM_RINGS];
677 uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
678
679 unsigned int stop_rings;
680
681 unsigned long cfb_size;
682 unsigned int cfb_fb;
683 enum plane cfb_plane;
684 int cfb_y;
685 struct intel_fbc_work *fbc_work;
686
687 struct intel_opregion opregion;
688
689 /* overlay */
690 struct intel_overlay *overlay;
691 bool sprite_scaling_enabled;
692
693 /* LVDS info */
694 int backlight_level; /* restore backlight to this value */
695 bool backlight_enabled;
696 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
697 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
698
699 /* Feature bits from the VBIOS */
700 unsigned int int_tv_support:1;
701 unsigned int lvds_dither:1;
702 unsigned int lvds_vbt:1;
703 unsigned int int_crt_support:1;
704 unsigned int lvds_use_ssc:1;
705 unsigned int display_clock_mode:1;
706 int lvds_ssc_freq;
707 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
708 struct {
709 int rate;
710 int lanes;
711 int preemphasis;
712 int vswing;
713
714 bool initialized;
715 bool support;
716 int bpp;
717 struct edp_power_seq pps;
718 } edp;
719 bool no_aux_handshake;
720
721 int crt_ddc_pin;
722 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
723 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
724 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
725
726 unsigned int fsb_freq, mem_freq, is_ddr3;
727
728 spinlock_t error_lock;
729 /* Protected by dev->error_lock. */
730 struct drm_i915_error_state *first_error;
731 struct work_struct error_work;
732 struct completion error_completion;
733 struct workqueue_struct *wq;
734
735 /* Display functions */
736 struct drm_i915_display_funcs display;
737
738 /* PCH chipset type */
739 enum intel_pch pch_type;
740 unsigned short pch_id;
741
742 unsigned long quirks;
743
744 /* Register state */
745 bool modeset_on_lid;
746
747 struct {
748 /** Bridge to intel-gtt-ko */
749 struct intel_gtt *gtt;
750 /** Memory allocator for GTT stolen memory */
751 struct drm_mm stolen;
752 /** Memory allocator for GTT */
753 struct drm_mm gtt_space;
754 /** List of all objects in gtt_space. Used to restore gtt
755 * mappings on resume */
756 struct list_head bound_list;
757 /**
758 * List of objects which are not bound to the GTT (thus
759 * are idle and not used by the GPU) but still have
760 * (presumably uncached) pages still attached.
761 */
762 struct list_head unbound_list;
763
764 /** Usable portion of the GTT for GEM */
765 unsigned long gtt_start;
766 unsigned long gtt_mappable_end;
767 unsigned long gtt_end;
768 unsigned long stolen_base; /* limited to low memory (32-bit) */
769
770 struct io_mapping *gtt_mapping;
771 phys_addr_t gtt_base_addr;
772 int gtt_mtrr;
773
774 /** PPGTT used for aliasing the PPGTT with the GTT */
775 struct i915_hw_ppgtt *aliasing_ppgtt;
776
777 struct shrinker inactive_shrinker;
778
779 /**
780 * List of objects currently involved in rendering.
781 *
782 * Includes buffers having the contents of their GPU caches
783 * flushed, not necessarily primitives. last_rendering_seqno
784 * represents when the rendering involved will be completed.
785 *
786 * A reference is held on the buffer while on this list.
787 */
788 struct list_head active_list;
789
790 /**
791 * LRU list of objects which are not in the ringbuffer and
792 * are ready to unbind, but are still in the GTT.
793 *
794 * last_rendering_seqno is 0 while an object is in this list.
795 *
796 * A reference is not held on the buffer while on this list,
797 * as merely being GTT-bound shouldn't prevent its being
798 * freed, and we'll pull it off the list in the free path.
799 */
800 struct list_head inactive_list;
801
802 /** LRU list of objects with fence regs on them. */
803 struct list_head fence_list;
804
805 /**
806 * We leave the user IRQ off as much as possible,
807 * but this means that requests will finish and never
808 * be retired once the system goes idle. Set a timer to
809 * fire periodically while the ring is running. When it
810 * fires, go retire requests.
811 */
812 struct delayed_work retire_work;
813
814 /**
815 * Are we in a non-interruptible section of code like
816 * modesetting?
817 */
818 bool interruptible;
819
820 /**
821 * Flag if the X Server, and thus DRM, is not currently in
822 * control of the device.
823 *
824 * This is set between LeaveVT and EnterVT. It needs to be
825 * replaced with a semaphore. It also needs to be
826 * transitioned away from for kernel modesetting.
827 */
828 int suspended;
829
830 /**
831 * Flag if the hardware appears to be wedged.
832 *
833 * This is set when attempts to idle the device timeout.
834 * It prevents command submission from occurring and makes
835 * every pending request fail
836 */
837 atomic_t wedged;
838
839 /** Bit 6 swizzling required for X tiling */
840 uint32_t bit_6_swizzle_x;
841 /** Bit 6 swizzling required for Y tiling */
842 uint32_t bit_6_swizzle_y;
843
844 /* storage for physical objects */
845 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
846
847 /* accounting, useful for userland debugging */
848 size_t gtt_total;
849 size_t mappable_gtt_total;
850 size_t object_memory;
851 u32 object_count;
852 } mm;
853
854 /* Kernel Modesetting */
855
856 struct sdvo_device_mapping sdvo_mappings[2];
857 /* indicate whether the LVDS_BORDER should be enabled or not */
858 unsigned int lvds_border_bits;
859 /* Panel fitter placement and size for Ironlake+ */
860 u32 pch_pf_pos, pch_pf_size;
861
862 struct drm_crtc *plane_to_crtc_mapping[3];
863 struct drm_crtc *pipe_to_crtc_mapping[3];
864 wait_queue_head_t pending_flip_queue;
865
866 struct intel_pch_pll pch_plls[I915_NUM_PLLS];
867 struct intel_ddi_plls ddi_plls;
868
869 /* Reclocking support */
870 bool render_reclock_avail;
871 bool lvds_downclock_avail;
872 /* indicates the reduced downclock for LVDS*/
873 int lvds_downclock;
874 u16 orig_clock;
875 int child_dev_num;
876 struct child_device_config *child_dev;
877
878 bool mchbar_need_disable;
879
880 struct intel_l3_parity l3_parity;
881
882 /* gen6+ rps state */
883 struct intel_gen6_power_mgmt rps;
884
885 /* ilk-only ips/rps state. Everything in here is protected by the global
886 * mchdev_lock in intel_pm.c */
887 struct intel_ilk_power_mgmt ips;
888
889 enum no_fbc_reason no_fbc_reason;
890
891 struct drm_mm_node *compressed_fb;
892 struct drm_mm_node *compressed_llb;
893
894 unsigned long last_gpu_reset;
895
896 /* list of fbdev register on this device */
897 struct intel_fbdev *fbdev;
898
899 /*
900 * The console may be contended at resume, but we don't
901 * want it to block on it.
902 */
903 struct work_struct console_resume_work;
904
905 struct backlight_device *backlight;
906
907 struct drm_property *broadcast_rgb_property;
908 struct drm_property *force_audio_property;
909
910 bool hw_contexts_disabled;
911 uint32_t hw_context_size;
912
913 struct i915_suspend_saved_registers regfile;
914
915 /* Old dri1 support infrastructure, beware the dragons ya fools entering
916 * here! */
917 struct i915_dri1_state dri1;
918} drm_i915_private_t;
919
920/* Iterate over initialised rings */
921#define for_each_ring(ring__, dev_priv__, i__) \
922 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
923 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
924
925enum hdmi_force_audio {
926 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
927 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
928 HDMI_AUDIO_AUTO, /* trust EDID */
929 HDMI_AUDIO_ON, /* force turn on HDMI audio */
930};
931
932enum i915_cache_level {
933 I915_CACHE_NONE = 0,
934 I915_CACHE_LLC,
935 I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
936};
937
938#define I915_GTT_RESERVED ((struct drm_mm_node *)0x1)
939
940struct drm_i915_gem_object_ops {
941 /* Interface between the GEM object and its backing storage.
942 * get_pages() is called once prior to the use of the associated set
943 * of pages before to binding them into the GTT, and put_pages() is
944 * called after we no longer need them. As we expect there to be
945 * associated cost with migrating pages between the backing storage
946 * and making them available for the GPU (e.g. clflush), we may hold
947 * onto the pages after they are no longer referenced by the GPU
948 * in case they may be used again shortly (for example migrating the
949 * pages to a different memory domain within the GTT). put_pages()
950 * will therefore most likely be called when the object itself is
951 * being released or under memory pressure (where we attempt to
952 * reap pages for the shrinker).
953 */
954 int (*get_pages)(struct drm_i915_gem_object *);
955 void (*put_pages)(struct drm_i915_gem_object *);
956};
957
958struct drm_i915_gem_object {
959 struct drm_gem_object base;
960
961 const struct drm_i915_gem_object_ops *ops;
962
963 /** Current space allocated to this object in the GTT, if any. */
964 struct drm_mm_node *gtt_space;
965 struct list_head gtt_list;
966
967 /** This object's place on the active/inactive lists */
968 struct list_head ring_list;
969 struct list_head mm_list;
970 /** This object's place in the batchbuffer or on the eviction list */
971 struct list_head exec_list;
972
973 /**
974 * This is set if the object is on the active lists (has pending
975 * rendering and so a non-zero seqno), and is not set if it i s on
976 * inactive (ready to be unbound) list.
977 */
978 unsigned int active:1;
979
980 /**
981 * This is set if the object has been written to since last bound
982 * to the GTT
983 */
984 unsigned int dirty:1;
985
986 /**
987 * Fence register bits (if any) for this object. Will be set
988 * as needed when mapped into the GTT.
989 * Protected by dev->struct_mutex.
990 */
991 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
992
993 /**
994 * Advice: are the backing pages purgeable?
995 */
996 unsigned int madv:2;
997
998 /**
999 * Current tiling mode for the object.
1000 */
1001 unsigned int tiling_mode:2;
1002 /**
1003 * Whether the tiling parameters for the currently associated fence
1004 * register have changed. Note that for the purposes of tracking
1005 * tiling changes we also treat the unfenced register, the register
1006 * slot that the object occupies whilst it executes a fenced
1007 * command (such as BLT on gen2/3), as a "fence".
1008 */
1009 unsigned int fence_dirty:1;
1010
1011 /** How many users have pinned this object in GTT space. The following
1012 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1013 * (via user_pin_count), execbuffer (objects are not allowed multiple
1014 * times for the same batchbuffer), and the framebuffer code. When
1015 * switching/pageflipping, the framebuffer code has at most two buffers
1016 * pinned per crtc.
1017 *
1018 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1019 * bits with absolutely no headroom. So use 4 bits. */
1020 unsigned int pin_count:4;
1021#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1022
1023 /**
1024 * Is the object at the current location in the gtt mappable and
1025 * fenceable? Used to avoid costly recalculations.
1026 */
1027 unsigned int map_and_fenceable:1;
1028
1029 /**
1030 * Whether the current gtt mapping needs to be mappable (and isn't just
1031 * mappable by accident). Track pin and fault separate for a more
1032 * accurate mappable working set.
1033 */
1034 unsigned int fault_mappable:1;
1035 unsigned int pin_mappable:1;
1036
1037 /*
1038 * Is the GPU currently using a fence to access this buffer,
1039 */
1040 unsigned int pending_fenced_gpu_access:1;
1041 unsigned int fenced_gpu_access:1;
1042
1043 unsigned int cache_level:2;
1044
1045 unsigned int has_aliasing_ppgtt_mapping:1;
1046 unsigned int has_global_gtt_mapping:1;
1047 unsigned int has_dma_mapping:1;
1048
1049 struct sg_table *pages;
1050 int pages_pin_count;
1051
1052 /* prime dma-buf support */
1053 void *dma_buf_vmapping;
1054 int vmapping_count;
1055
1056 /**
1057 * Used for performing relocations during execbuffer insertion.
1058 */
1059 struct hlist_node exec_node;
1060 unsigned long exec_handle;
1061 struct drm_i915_gem_exec_object2 *exec_entry;
1062
1063 /**
1064 * Current offset of the object in GTT space.
1065 *
1066 * This is the same as gtt_space->start
1067 */
1068 uint32_t gtt_offset;
1069
1070 struct intel_ring_buffer *ring;
1071
1072 /** Breadcrumb of last rendering to the buffer. */
1073 uint32_t last_read_seqno;
1074 uint32_t last_write_seqno;
1075 /** Breadcrumb of last fenced GPU access to the buffer. */
1076 uint32_t last_fenced_seqno;
1077
1078 /** Current tiling stride for the object, if it's tiled. */
1079 uint32_t stride;
1080
1081 /** Record of address bit 17 of each page at last unbind. */
1082 unsigned long *bit_17;
1083
1084 /** User space pin count and filp owning the pin */
1085 uint32_t user_pin_count;
1086 struct drm_file *pin_filp;
1087
1088 /** for phy allocated objects */
1089 struct drm_i915_gem_phys_object *phys_obj;
1090
1091 /**
1092 * Number of crtcs where this object is currently the fb, but
1093 * will be page flipped away on the next vblank. When it
1094 * reaches 0, dev_priv->pending_flip_queue will be woken up.
1095 */
1096 atomic_t pending_flip;
1097};
1098
1099#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1100
1101/**
1102 * Request queue structure.
1103 *
1104 * The request queue allows us to note sequence numbers that have been emitted
1105 * and may be associated with active buffers to be retired.
1106 *
1107 * By keeping this list, we can avoid having to do questionable
1108 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1109 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1110 */
1111struct drm_i915_gem_request {
1112 /** On Which ring this request was generated */
1113 struct intel_ring_buffer *ring;
1114
1115 /** GEM sequence number associated with this request. */
1116 uint32_t seqno;
1117
1118 /** Postion in the ringbuffer of the end of the request */
1119 u32 tail;
1120
1121 /** Time at which this request was emitted, in jiffies. */
1122 unsigned long emitted_jiffies;
1123
1124 /** global list entry for this request */
1125 struct list_head list;
1126
1127 struct drm_i915_file_private *file_priv;
1128 /** file_priv list entry for this request */
1129 struct list_head client_list;
1130};
1131
1132struct drm_i915_file_private {
1133 struct {
1134 spinlock_t lock;
1135 struct list_head request_list;
1136 } mm;
1137 struct idr context_idr;
1138};
1139
1140#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1141
1142#define IS_I830(dev) ((dev)->pci_device == 0x3577)
1143#define IS_845G(dev) ((dev)->pci_device == 0x2562)
1144#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1145#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1146#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1147#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1148#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1149#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1150#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1151#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1152#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1153#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1154#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1155#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1156#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1157#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1158#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1159#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1160#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1161#define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1162 (dev)->pci_device == 0x0152 || \
1163 (dev)->pci_device == 0x015a)
1164#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1165#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1166#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1167#define IS_ULT(dev) (IS_HASWELL(dev) && \
1168 ((dev)->pci_device & 0xFF00) == 0x0A00)
1169
1170/*
1171 * The genX designation typically refers to the render engine, so render
1172 * capability related checks should use IS_GEN, while display and other checks
1173 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1174 * chips, etc.).
1175 */
1176#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1177#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1178#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1179#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1180#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1181#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1182
1183#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1184#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1185#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1186#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1187
1188#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1189#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1190
1191#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1192#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1193
1194/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1195 * rows, which changed the alignment requirements and fence programming.
1196 */
1197#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1198 IS_I915GM(dev)))
1199#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1200#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1201#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1202#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1203#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1204#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1205/* dsparb controlled by hw only */
1206#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1207
1208#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1209#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1210#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1211
1212#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1213
1214#define HAS_DDI(dev) (IS_HASWELL(dev))
1215
1216#define INTEL_PCH_DEVICE_ID_MASK 0xff00
1217#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1218#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1219#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1220#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1221#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1222
1223#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1224#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1225#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1226#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1227#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1228
1229#define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1230
1231#define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1232
1233#define GT_FREQUENCY_MULTIPLIER 50
1234
1235#include "i915_trace.h"
1236
1237/**
1238 * RC6 is a special power stage which allows the GPU to enter an very
1239 * low-voltage mode when idle, using down to 0V while at this stage. This
1240 * stage is entered automatically when the GPU is idle when RC6 support is
1241 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1242 *
1243 * There are different RC6 modes available in Intel GPU, which differentiate
1244 * among each other with the latency required to enter and leave RC6 and
1245 * voltage consumed by the GPU in different states.
1246 *
1247 * The combination of the following flags define which states GPU is allowed
1248 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1249 * RC6pp is deepest RC6. Their support by hardware varies according to the
1250 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1251 * which brings the most power savings; deeper states save more power, but
1252 * require higher latency to switch to and wake up.
1253 */
1254#define INTEL_RC6_ENABLE (1<<0)
1255#define INTEL_RC6p_ENABLE (1<<1)
1256#define INTEL_RC6pp_ENABLE (1<<2)
1257
1258extern struct drm_ioctl_desc i915_ioctls[];
1259extern int i915_max_ioctl;
1260extern unsigned int i915_fbpercrtc __always_unused;
1261extern int i915_panel_ignore_lid __read_mostly;
1262extern unsigned int i915_powersave __read_mostly;
1263extern int i915_semaphores __read_mostly;
1264extern unsigned int i915_lvds_downclock __read_mostly;
1265extern int i915_lvds_channel_mode __read_mostly;
1266extern int i915_panel_use_ssc __read_mostly;
1267extern int i915_vbt_sdvo_panel_type __read_mostly;
1268extern int i915_enable_rc6 __read_mostly;
1269extern int i915_enable_fbc __read_mostly;
1270extern bool i915_enable_hangcheck __read_mostly;
1271extern int i915_enable_ppgtt __read_mostly;
1272extern unsigned int i915_preliminary_hw_support __read_mostly;
1273
1274extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1275extern int i915_resume(struct drm_device *dev);
1276extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1277extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1278
1279 /* i915_dma.c */
1280void i915_update_dri1_breadcrumb(struct drm_device *dev);
1281extern void i915_kernel_lost_context(struct drm_device * dev);
1282extern int i915_driver_load(struct drm_device *, unsigned long flags);
1283extern int i915_driver_unload(struct drm_device *);
1284extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1285extern void i915_driver_lastclose(struct drm_device * dev);
1286extern void i915_driver_preclose(struct drm_device *dev,
1287 struct drm_file *file_priv);
1288extern void i915_driver_postclose(struct drm_device *dev,
1289 struct drm_file *file_priv);
1290extern int i915_driver_device_is_agp(struct drm_device * dev);
1291#ifdef CONFIG_COMPAT
1292extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1293 unsigned long arg);
1294#endif
1295extern int i915_emit_box(struct drm_device *dev,
1296 struct drm_clip_rect *box,
1297 int DR1, int DR4);
1298extern int intel_gpu_reset(struct drm_device *dev);
1299extern int i915_reset(struct drm_device *dev);
1300extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1301extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1302extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1303extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1304
1305extern void intel_console_resume(struct work_struct *work);
1306
1307/* i915_irq.c */
1308void i915_hangcheck_elapsed(unsigned long data);
1309void i915_handle_error(struct drm_device *dev, bool wedged);
1310
1311extern void intel_irq_init(struct drm_device *dev);
1312extern void intel_gt_init(struct drm_device *dev);
1313extern void intel_gt_reset(struct drm_device *dev);
1314
1315void i915_error_state_free(struct kref *error_ref);
1316
1317void
1318i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1319
1320void
1321i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1322
1323void intel_enable_asle(struct drm_device *dev);
1324
1325#ifdef CONFIG_DEBUG_FS
1326extern void i915_destroy_error_state(struct drm_device *dev);
1327#else
1328#define i915_destroy_error_state(x)
1329#endif
1330
1331
1332/* i915_gem.c */
1333int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1334 struct drm_file *file_priv);
1335int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1336 struct drm_file *file_priv);
1337int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1338 struct drm_file *file_priv);
1339int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1340 struct drm_file *file_priv);
1341int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1342 struct drm_file *file_priv);
1343int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1344 struct drm_file *file_priv);
1345int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1346 struct drm_file *file_priv);
1347int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1348 struct drm_file *file_priv);
1349int i915_gem_execbuffer(struct drm_device *dev, void *data,
1350 struct drm_file *file_priv);
1351int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1352 struct drm_file *file_priv);
1353int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1354 struct drm_file *file_priv);
1355int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1356 struct drm_file *file_priv);
1357int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1358 struct drm_file *file_priv);
1359int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1360 struct drm_file *file);
1361int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1362 struct drm_file *file);
1363int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1364 struct drm_file *file_priv);
1365int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1366 struct drm_file *file_priv);
1367int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1368 struct drm_file *file_priv);
1369int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1370 struct drm_file *file_priv);
1371int i915_gem_set_tiling(struct drm_device *dev, void *data,
1372 struct drm_file *file_priv);
1373int i915_gem_get_tiling(struct drm_device *dev, void *data,
1374 struct drm_file *file_priv);
1375int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1376 struct drm_file *file_priv);
1377int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1378 struct drm_file *file_priv);
1379void i915_gem_load(struct drm_device *dev);
1380int i915_gem_init_object(struct drm_gem_object *obj);
1381void i915_gem_object_init(struct drm_i915_gem_object *obj,
1382 const struct drm_i915_gem_object_ops *ops);
1383struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1384 size_t size);
1385void i915_gem_free_object(struct drm_gem_object *obj);
1386int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1387 uint32_t alignment,
1388 bool map_and_fenceable,
1389 bool nonblocking);
1390void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1391int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1392void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1393void i915_gem_lastclose(struct drm_device *dev);
1394
1395int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
1396static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
1397{
1398 struct scatterlist *sg = obj->pages->sgl;
1399 int nents = obj->pages->nents;
1400 while (nents > SG_MAX_SINGLE_ALLOC) {
1401 if (n < SG_MAX_SINGLE_ALLOC - 1)
1402 break;
1403
1404 sg = sg_chain_ptr(sg + SG_MAX_SINGLE_ALLOC - 1);
1405 n -= SG_MAX_SINGLE_ALLOC - 1;
1406 nents -= SG_MAX_SINGLE_ALLOC - 1;
1407 }
1408 return sg_page(sg+n);
1409}
1410static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
1411{
1412 BUG_ON(obj->pages == NULL);
1413 obj->pages_pin_count++;
1414}
1415static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
1416{
1417 BUG_ON(obj->pages_pin_count == 0);
1418 obj->pages_pin_count--;
1419}
1420
1421int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1422int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1423 struct intel_ring_buffer *to);
1424void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1425 struct intel_ring_buffer *ring);
1426
1427int i915_gem_dumb_create(struct drm_file *file_priv,
1428 struct drm_device *dev,
1429 struct drm_mode_create_dumb *args);
1430int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1431 uint32_t handle, uint64_t *offset);
1432int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1433 uint32_t handle);
1434/**
1435 * Returns true if seq1 is later than seq2.
1436 */
1437static inline bool
1438i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1439{
1440 return (int32_t)(seq1 - seq2) >= 0;
1441}
1442
1443extern int i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
1444
1445int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1446int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1447
1448static inline bool
1449i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1450{
1451 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1452 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1453 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1454 return true;
1455 } else
1456 return false;
1457}
1458
1459static inline void
1460i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1461{
1462 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1463 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1464 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1465 }
1466}
1467
1468void i915_gem_retire_requests(struct drm_device *dev);
1469void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1470int __must_check i915_gem_check_wedge(struct drm_i915_private *dev_priv,
1471 bool interruptible);
1472
1473void i915_gem_reset(struct drm_device *dev);
1474void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1475int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1476 uint32_t read_domains,
1477 uint32_t write_domain);
1478int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1479int __must_check i915_gem_init(struct drm_device *dev);
1480int __must_check i915_gem_init_hw(struct drm_device *dev);
1481void i915_gem_l3_remap(struct drm_device *dev);
1482void i915_gem_init_swizzling(struct drm_device *dev);
1483void i915_gem_init_ppgtt(struct drm_device *dev);
1484void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1485int __must_check i915_gpu_idle(struct drm_device *dev);
1486int __must_check i915_gem_idle(struct drm_device *dev);
1487int i915_add_request(struct intel_ring_buffer *ring,
1488 struct drm_file *file,
1489 u32 *seqno);
1490int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1491 uint32_t seqno);
1492int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1493int __must_check
1494i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1495 bool write);
1496int __must_check
1497i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1498int __must_check
1499i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1500 u32 alignment,
1501 struct intel_ring_buffer *pipelined);
1502int i915_gem_attach_phys_object(struct drm_device *dev,
1503 struct drm_i915_gem_object *obj,
1504 int id,
1505 int align);
1506void i915_gem_detach_phys_object(struct drm_device *dev,
1507 struct drm_i915_gem_object *obj);
1508void i915_gem_free_all_phys_object(struct drm_device *dev);
1509void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1510
1511uint32_t
1512i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1513 uint32_t size,
1514 int tiling_mode);
1515
1516int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1517 enum i915_cache_level cache_level);
1518
1519struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1520 struct dma_buf *dma_buf);
1521
1522struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1523 struct drm_gem_object *gem_obj, int flags);
1524
1525/* i915_gem_context.c */
1526void i915_gem_context_init(struct drm_device *dev);
1527void i915_gem_context_fini(struct drm_device *dev);
1528void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
1529int i915_switch_context(struct intel_ring_buffer *ring,
1530 struct drm_file *file, int to_id);
1531int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1532 struct drm_file *file);
1533int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1534 struct drm_file *file);
1535
1536/* i915_gem_gtt.c */
1537int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
1538void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1539void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1540 struct drm_i915_gem_object *obj,
1541 enum i915_cache_level cache_level);
1542void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1543 struct drm_i915_gem_object *obj);
1544
1545void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1546int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1547void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1548 enum i915_cache_level cache_level);
1549void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1550void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1551void i915_gem_init_global_gtt(struct drm_device *dev,
1552 unsigned long start,
1553 unsigned long mappable_end,
1554 unsigned long end);
1555int i915_gem_gtt_init(struct drm_device *dev);
1556void i915_gem_gtt_fini(struct drm_device *dev);
1557static inline void i915_gem_chipset_flush(struct drm_device *dev)
1558{
1559 if (INTEL_INFO(dev)->gen < 6)
1560 intel_gtt_chipset_flush();
1561}
1562
1563
1564/* i915_gem_evict.c */
1565int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1566 unsigned alignment,
1567 unsigned cache_level,
1568 bool mappable,
1569 bool nonblock);
1570int i915_gem_evict_everything(struct drm_device *dev);
1571
1572/* i915_gem_stolen.c */
1573int i915_gem_init_stolen(struct drm_device *dev);
1574void i915_gem_cleanup_stolen(struct drm_device *dev);
1575
1576/* i915_gem_tiling.c */
1577void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1578void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1579void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1580
1581/* i915_gem_debug.c */
1582void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1583 const char *where, uint32_t mark);
1584#if WATCH_LISTS
1585int i915_verify_lists(struct drm_device *dev);
1586#else
1587#define i915_verify_lists(dev) 0
1588#endif
1589void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1590 int handle);
1591void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1592 const char *where, uint32_t mark);
1593
1594/* i915_debugfs.c */
1595int i915_debugfs_init(struct drm_minor *minor);
1596void i915_debugfs_cleanup(struct drm_minor *minor);
1597
1598/* i915_suspend.c */
1599extern int i915_save_state(struct drm_device *dev);
1600extern int i915_restore_state(struct drm_device *dev);
1601
1602/* i915_suspend.c */
1603extern int i915_save_state(struct drm_device *dev);
1604extern int i915_restore_state(struct drm_device *dev);
1605
1606/* i915_sysfs.c */
1607void i915_setup_sysfs(struct drm_device *dev_priv);
1608void i915_teardown_sysfs(struct drm_device *dev_priv);
1609
1610/* intel_i2c.c */
1611extern int intel_setup_gmbus(struct drm_device *dev);
1612extern void intel_teardown_gmbus(struct drm_device *dev);
1613extern inline bool intel_gmbus_is_port_valid(unsigned port)
1614{
1615 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1616}
1617
1618extern struct i2c_adapter *intel_gmbus_get_adapter(
1619 struct drm_i915_private *dev_priv, unsigned port);
1620extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1621extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1622extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1623{
1624 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1625}
1626extern void intel_i2c_reset(struct drm_device *dev);
1627
1628/* intel_opregion.c */
1629extern int intel_opregion_setup(struct drm_device *dev);
1630#ifdef CONFIG_ACPI
1631extern void intel_opregion_init(struct drm_device *dev);
1632extern void intel_opregion_fini(struct drm_device *dev);
1633extern void intel_opregion_asle_intr(struct drm_device *dev);
1634extern void intel_opregion_gse_intr(struct drm_device *dev);
1635extern void intel_opregion_enable_asle(struct drm_device *dev);
1636#else
1637static inline void intel_opregion_init(struct drm_device *dev) { return; }
1638static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1639static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1640static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1641static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1642#endif
1643
1644/* intel_acpi.c */
1645#ifdef CONFIG_ACPI
1646extern void intel_register_dsm_handler(void);
1647extern void intel_unregister_dsm_handler(void);
1648#else
1649static inline void intel_register_dsm_handler(void) { return; }
1650static inline void intel_unregister_dsm_handler(void) { return; }
1651#endif /* CONFIG_ACPI */
1652
1653/* modesetting */
1654extern void intel_modeset_init_hw(struct drm_device *dev);
1655extern void intel_modeset_init(struct drm_device *dev);
1656extern void intel_modeset_gem_init(struct drm_device *dev);
1657extern void intel_modeset_cleanup(struct drm_device *dev);
1658extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1659extern void intel_modeset_setup_hw_state(struct drm_device *dev,
1660 bool force_restore);
1661extern bool intel_fbc_enabled(struct drm_device *dev);
1662extern void intel_disable_fbc(struct drm_device *dev);
1663extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1664extern void ironlake_init_pch_refclk(struct drm_device *dev);
1665extern void gen6_set_rps(struct drm_device *dev, u8 val);
1666extern void intel_detect_pch(struct drm_device *dev);
1667extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1668extern int intel_enable_rc6(const struct drm_device *dev);
1669
1670extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1671int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1672 struct drm_file *file);
1673
1674/* overlay */
1675#ifdef CONFIG_DEBUG_FS
1676extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1677extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1678
1679extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1680extern void intel_display_print_error_state(struct seq_file *m,
1681 struct drm_device *dev,
1682 struct intel_display_error_state *error);
1683#endif
1684
1685/* On SNB platform, before reading ring registers forcewake bit
1686 * must be set to prevent GT core from power down and stale values being
1687 * returned.
1688 */
1689void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1690void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1691int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1692
1693int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
1694int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
1695
1696#define __i915_read(x, y) \
1697 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1698
1699__i915_read(8, b)
1700__i915_read(16, w)
1701__i915_read(32, l)
1702__i915_read(64, q)
1703#undef __i915_read
1704
1705#define __i915_write(x, y) \
1706 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1707
1708__i915_write(8, b)
1709__i915_write(16, w)
1710__i915_write(32, l)
1711__i915_write(64, q)
1712#undef __i915_write
1713
1714#define I915_READ8(reg) i915_read8(dev_priv, (reg))
1715#define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1716
1717#define I915_READ16(reg) i915_read16(dev_priv, (reg))
1718#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1719#define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1720#define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1721
1722#define I915_READ(reg) i915_read32(dev_priv, (reg))
1723#define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1724#define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1725#define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1726
1727#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1728#define I915_READ64(reg) i915_read64(dev_priv, (reg))
1729
1730#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1731#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1732
1733
1734#endif
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