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1 | /* | |
2 | * Copyright © 2008-2015 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <drm/drmP.h> | |
29 | #include <drm/drm_vma_manager.h> | |
30 | #include <drm/i915_drm.h> | |
31 | #include "i915_drv.h" | |
32 | #include "i915_vgpu.h" | |
33 | #include "i915_trace.h" | |
34 | #include "intel_drv.h" | |
35 | #include <linux/shmem_fs.h> | |
36 | #include <linux/slab.h> | |
37 | #include <linux/swap.h> | |
38 | #include <linux/pci.h> | |
39 | #include <linux/dma-buf.h> | |
40 | ||
41 | #define RQ_BUG_ON(expr) | |
42 | ||
43 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); | |
44 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
45 | static void | |
46 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj); | |
47 | static void | |
48 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring); | |
49 | ||
50 | static bool cpu_cache_is_coherent(struct drm_device *dev, | |
51 | enum i915_cache_level level) | |
52 | { | |
53 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
54 | } | |
55 | ||
56 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) | |
57 | { | |
58 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
59 | return true; | |
60 | ||
61 | return obj->pin_display; | |
62 | } | |
63 | ||
64 | /* some bookkeeping */ | |
65 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
66 | size_t size) | |
67 | { | |
68 | spin_lock(&dev_priv->mm.object_stat_lock); | |
69 | dev_priv->mm.object_count++; | |
70 | dev_priv->mm.object_memory += size; | |
71 | spin_unlock(&dev_priv->mm.object_stat_lock); | |
72 | } | |
73 | ||
74 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
75 | size_t size) | |
76 | { | |
77 | spin_lock(&dev_priv->mm.object_stat_lock); | |
78 | dev_priv->mm.object_count--; | |
79 | dev_priv->mm.object_memory -= size; | |
80 | spin_unlock(&dev_priv->mm.object_stat_lock); | |
81 | } | |
82 | ||
83 | static int | |
84 | i915_gem_wait_for_error(struct i915_gpu_error *error) | |
85 | { | |
86 | int ret; | |
87 | ||
88 | #define EXIT_COND (!i915_reset_in_progress(error) || \ | |
89 | i915_terminally_wedged(error)) | |
90 | if (EXIT_COND) | |
91 | return 0; | |
92 | ||
93 | /* | |
94 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
95 | * userspace. If it takes that long something really bad is going on and | |
96 | * we should simply try to bail out and fail as gracefully as possible. | |
97 | */ | |
98 | ret = wait_event_interruptible_timeout(error->reset_queue, | |
99 | EXIT_COND, | |
100 | 10*HZ); | |
101 | if (ret == 0) { | |
102 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
103 | return -EIO; | |
104 | } else if (ret < 0) { | |
105 | return ret; | |
106 | } | |
107 | #undef EXIT_COND | |
108 | ||
109 | return 0; | |
110 | } | |
111 | ||
112 | int i915_mutex_lock_interruptible(struct drm_device *dev) | |
113 | { | |
114 | struct drm_i915_private *dev_priv = dev->dev_private; | |
115 | int ret; | |
116 | ||
117 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); | |
118 | if (ret) | |
119 | return ret; | |
120 | ||
121 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
122 | if (ret) | |
123 | return ret; | |
124 | ||
125 | WARN_ON(i915_verify_lists(dev)); | |
126 | return 0; | |
127 | } | |
128 | ||
129 | int | |
130 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
131 | struct drm_file *file) | |
132 | { | |
133 | struct drm_i915_private *dev_priv = dev->dev_private; | |
134 | struct drm_i915_gem_get_aperture *args = data; | |
135 | struct i915_gtt *ggtt = &dev_priv->gtt; | |
136 | struct i915_vma *vma; | |
137 | size_t pinned; | |
138 | ||
139 | pinned = 0; | |
140 | mutex_lock(&dev->struct_mutex); | |
141 | list_for_each_entry(vma, &ggtt->base.active_list, mm_list) | |
142 | if (vma->pin_count) | |
143 | pinned += vma->node.size; | |
144 | list_for_each_entry(vma, &ggtt->base.inactive_list, mm_list) | |
145 | if (vma->pin_count) | |
146 | pinned += vma->node.size; | |
147 | mutex_unlock(&dev->struct_mutex); | |
148 | ||
149 | args->aper_size = dev_priv->gtt.base.total; | |
150 | args->aper_available_size = args->aper_size - pinned; | |
151 | ||
152 | return 0; | |
153 | } | |
154 | ||
155 | static int | |
156 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) | |
157 | { | |
158 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; | |
159 | char *vaddr = obj->phys_handle->vaddr; | |
160 | struct sg_table *st; | |
161 | struct scatterlist *sg; | |
162 | int i; | |
163 | ||
164 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) | |
165 | return -EINVAL; | |
166 | ||
167 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
168 | struct page *page; | |
169 | char *src; | |
170 | ||
171 | page = shmem_read_mapping_page(mapping, i); | |
172 | if (IS_ERR(page)) | |
173 | return PTR_ERR(page); | |
174 | ||
175 | src = kmap_atomic(page); | |
176 | memcpy(vaddr, src, PAGE_SIZE); | |
177 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
178 | kunmap_atomic(src); | |
179 | ||
180 | page_cache_release(page); | |
181 | vaddr += PAGE_SIZE; | |
182 | } | |
183 | ||
184 | i915_gem_chipset_flush(obj->base.dev); | |
185 | ||
186 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
187 | if (st == NULL) | |
188 | return -ENOMEM; | |
189 | ||
190 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
191 | kfree(st); | |
192 | return -ENOMEM; | |
193 | } | |
194 | ||
195 | sg = st->sgl; | |
196 | sg->offset = 0; | |
197 | sg->length = obj->base.size; | |
198 | ||
199 | sg_dma_address(sg) = obj->phys_handle->busaddr; | |
200 | sg_dma_len(sg) = obj->base.size; | |
201 | ||
202 | obj->pages = st; | |
203 | return 0; | |
204 | } | |
205 | ||
206 | static void | |
207 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) | |
208 | { | |
209 | int ret; | |
210 | ||
211 | BUG_ON(obj->madv == __I915_MADV_PURGED); | |
212 | ||
213 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
214 | if (ret) { | |
215 | /* In the event of a disaster, abandon all caches and | |
216 | * hope for the best. | |
217 | */ | |
218 | WARN_ON(ret != -EIO); | |
219 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
220 | } | |
221 | ||
222 | if (obj->madv == I915_MADV_DONTNEED) | |
223 | obj->dirty = 0; | |
224 | ||
225 | if (obj->dirty) { | |
226 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; | |
227 | char *vaddr = obj->phys_handle->vaddr; | |
228 | int i; | |
229 | ||
230 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
231 | struct page *page; | |
232 | char *dst; | |
233 | ||
234 | page = shmem_read_mapping_page(mapping, i); | |
235 | if (IS_ERR(page)) | |
236 | continue; | |
237 | ||
238 | dst = kmap_atomic(page); | |
239 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
240 | memcpy(dst, vaddr, PAGE_SIZE); | |
241 | kunmap_atomic(dst); | |
242 | ||
243 | set_page_dirty(page); | |
244 | if (obj->madv == I915_MADV_WILLNEED) | |
245 | mark_page_accessed(page); | |
246 | page_cache_release(page); | |
247 | vaddr += PAGE_SIZE; | |
248 | } | |
249 | obj->dirty = 0; | |
250 | } | |
251 | ||
252 | sg_free_table(obj->pages); | |
253 | kfree(obj->pages); | |
254 | } | |
255 | ||
256 | static void | |
257 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
258 | { | |
259 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
260 | } | |
261 | ||
262 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
263 | .get_pages = i915_gem_object_get_pages_phys, | |
264 | .put_pages = i915_gem_object_put_pages_phys, | |
265 | .release = i915_gem_object_release_phys, | |
266 | }; | |
267 | ||
268 | static int | |
269 | drop_pages(struct drm_i915_gem_object *obj) | |
270 | { | |
271 | struct i915_vma *vma, *next; | |
272 | int ret; | |
273 | ||
274 | drm_gem_object_reference(&obj->base); | |
275 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) | |
276 | if (i915_vma_unbind(vma)) | |
277 | break; | |
278 | ||
279 | ret = i915_gem_object_put_pages(obj); | |
280 | drm_gem_object_unreference(&obj->base); | |
281 | ||
282 | return ret; | |
283 | } | |
284 | ||
285 | int | |
286 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
287 | int align) | |
288 | { | |
289 | drm_dma_handle_t *phys; | |
290 | int ret; | |
291 | ||
292 | if (obj->phys_handle) { | |
293 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
294 | return -EBUSY; | |
295 | ||
296 | return 0; | |
297 | } | |
298 | ||
299 | if (obj->madv != I915_MADV_WILLNEED) | |
300 | return -EFAULT; | |
301 | ||
302 | if (obj->base.filp == NULL) | |
303 | return -EINVAL; | |
304 | ||
305 | ret = drop_pages(obj); | |
306 | if (ret) | |
307 | return ret; | |
308 | ||
309 | /* create a new object */ | |
310 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
311 | if (!phys) | |
312 | return -ENOMEM; | |
313 | ||
314 | obj->phys_handle = phys; | |
315 | obj->ops = &i915_gem_phys_ops; | |
316 | ||
317 | return i915_gem_object_get_pages(obj); | |
318 | } | |
319 | ||
320 | static int | |
321 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
322 | struct drm_i915_gem_pwrite *args, | |
323 | struct drm_file *file_priv) | |
324 | { | |
325 | struct drm_device *dev = obj->base.dev; | |
326 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
327 | char __user *user_data = to_user_ptr(args->data_ptr); | |
328 | int ret = 0; | |
329 | ||
330 | /* We manually control the domain here and pretend that it | |
331 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
332 | */ | |
333 | ret = i915_gem_object_wait_rendering(obj, false); | |
334 | if (ret) | |
335 | return ret; | |
336 | ||
337 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); | |
338 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { | |
339 | unsigned long unwritten; | |
340 | ||
341 | /* The physical object once assigned is fixed for the lifetime | |
342 | * of the obj, so we can safely drop the lock and continue | |
343 | * to access vaddr. | |
344 | */ | |
345 | mutex_unlock(&dev->struct_mutex); | |
346 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
347 | mutex_lock(&dev->struct_mutex); | |
348 | if (unwritten) { | |
349 | ret = -EFAULT; | |
350 | goto out; | |
351 | } | |
352 | } | |
353 | ||
354 | drm_clflush_virt_range(vaddr, args->size); | |
355 | i915_gem_chipset_flush(dev); | |
356 | ||
357 | out: | |
358 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); | |
359 | return ret; | |
360 | } | |
361 | ||
362 | void *i915_gem_object_alloc(struct drm_device *dev) | |
363 | { | |
364 | struct drm_i915_private *dev_priv = dev->dev_private; | |
365 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); | |
366 | } | |
367 | ||
368 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
369 | { | |
370 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
371 | kmem_cache_free(dev_priv->objects, obj); | |
372 | } | |
373 | ||
374 | static int | |
375 | i915_gem_create(struct drm_file *file, | |
376 | struct drm_device *dev, | |
377 | uint64_t size, | |
378 | uint32_t *handle_p) | |
379 | { | |
380 | struct drm_i915_gem_object *obj; | |
381 | int ret; | |
382 | u32 handle; | |
383 | ||
384 | size = roundup(size, PAGE_SIZE); | |
385 | if (size == 0) | |
386 | return -EINVAL; | |
387 | ||
388 | /* Allocate the new object */ | |
389 | obj = i915_gem_alloc_object(dev, size); | |
390 | if (obj == NULL) | |
391 | return -ENOMEM; | |
392 | ||
393 | ret = drm_gem_handle_create(file, &obj->base, &handle); | |
394 | /* drop reference from allocate - handle holds it now */ | |
395 | drm_gem_object_unreference_unlocked(&obj->base); | |
396 | if (ret) | |
397 | return ret; | |
398 | ||
399 | *handle_p = handle; | |
400 | return 0; | |
401 | } | |
402 | ||
403 | int | |
404 | i915_gem_dumb_create(struct drm_file *file, | |
405 | struct drm_device *dev, | |
406 | struct drm_mode_create_dumb *args) | |
407 | { | |
408 | /* have to work out size/pitch and return them */ | |
409 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); | |
410 | args->size = args->pitch * args->height; | |
411 | return i915_gem_create(file, dev, | |
412 | args->size, &args->handle); | |
413 | } | |
414 | ||
415 | /** | |
416 | * Creates a new mm object and returns a handle to it. | |
417 | */ | |
418 | int | |
419 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
420 | struct drm_file *file) | |
421 | { | |
422 | struct drm_i915_gem_create *args = data; | |
423 | ||
424 | return i915_gem_create(file, dev, | |
425 | args->size, &args->handle); | |
426 | } | |
427 | ||
428 | static inline int | |
429 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
430 | const char *gpu_vaddr, int gpu_offset, | |
431 | int length) | |
432 | { | |
433 | int ret, cpu_offset = 0; | |
434 | ||
435 | while (length > 0) { | |
436 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
437 | int this_length = min(cacheline_end - gpu_offset, length); | |
438 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
439 | ||
440 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
441 | gpu_vaddr + swizzled_gpu_offset, | |
442 | this_length); | |
443 | if (ret) | |
444 | return ret + length; | |
445 | ||
446 | cpu_offset += this_length; | |
447 | gpu_offset += this_length; | |
448 | length -= this_length; | |
449 | } | |
450 | ||
451 | return 0; | |
452 | } | |
453 | ||
454 | static inline int | |
455 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, | |
456 | const char __user *cpu_vaddr, | |
457 | int length) | |
458 | { | |
459 | int ret, cpu_offset = 0; | |
460 | ||
461 | while (length > 0) { | |
462 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
463 | int this_length = min(cacheline_end - gpu_offset, length); | |
464 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
465 | ||
466 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
467 | cpu_vaddr + cpu_offset, | |
468 | this_length); | |
469 | if (ret) | |
470 | return ret + length; | |
471 | ||
472 | cpu_offset += this_length; | |
473 | gpu_offset += this_length; | |
474 | length -= this_length; | |
475 | } | |
476 | ||
477 | return 0; | |
478 | } | |
479 | ||
480 | /* | |
481 | * Pins the specified object's pages and synchronizes the object with | |
482 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
483 | * flush the object from the CPU cache. | |
484 | */ | |
485 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
486 | int *needs_clflush) | |
487 | { | |
488 | int ret; | |
489 | ||
490 | *needs_clflush = 0; | |
491 | ||
492 | if (!obj->base.filp) | |
493 | return -EINVAL; | |
494 | ||
495 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { | |
496 | /* If we're not in the cpu read domain, set ourself into the gtt | |
497 | * read domain and manually flush cachelines (if required). This | |
498 | * optimizes for the case when the gpu will dirty the data | |
499 | * anyway again before the next pread happens. */ | |
500 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, | |
501 | obj->cache_level); | |
502 | ret = i915_gem_object_wait_rendering(obj, true); | |
503 | if (ret) | |
504 | return ret; | |
505 | } | |
506 | ||
507 | ret = i915_gem_object_get_pages(obj); | |
508 | if (ret) | |
509 | return ret; | |
510 | ||
511 | i915_gem_object_pin_pages(obj); | |
512 | ||
513 | return ret; | |
514 | } | |
515 | ||
516 | /* Per-page copy function for the shmem pread fastpath. | |
517 | * Flushes invalid cachelines before reading the target if | |
518 | * needs_clflush is set. */ | |
519 | static int | |
520 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, | |
521 | char __user *user_data, | |
522 | bool page_do_bit17_swizzling, bool needs_clflush) | |
523 | { | |
524 | char *vaddr; | |
525 | int ret; | |
526 | ||
527 | if (unlikely(page_do_bit17_swizzling)) | |
528 | return -EINVAL; | |
529 | ||
530 | vaddr = kmap_atomic(page); | |
531 | if (needs_clflush) | |
532 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
533 | page_length); | |
534 | ret = __copy_to_user_inatomic(user_data, | |
535 | vaddr + shmem_page_offset, | |
536 | page_length); | |
537 | kunmap_atomic(vaddr); | |
538 | ||
539 | return ret ? -EFAULT : 0; | |
540 | } | |
541 | ||
542 | static void | |
543 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
544 | bool swizzled) | |
545 | { | |
546 | if (unlikely(swizzled)) { | |
547 | unsigned long start = (unsigned long) addr; | |
548 | unsigned long end = (unsigned long) addr + length; | |
549 | ||
550 | /* For swizzling simply ensure that we always flush both | |
551 | * channels. Lame, but simple and it works. Swizzled | |
552 | * pwrite/pread is far from a hotpath - current userspace | |
553 | * doesn't use it at all. */ | |
554 | start = round_down(start, 128); | |
555 | end = round_up(end, 128); | |
556 | ||
557 | drm_clflush_virt_range((void *)start, end - start); | |
558 | } else { | |
559 | drm_clflush_virt_range(addr, length); | |
560 | } | |
561 | ||
562 | } | |
563 | ||
564 | /* Only difference to the fast-path function is that this can handle bit17 | |
565 | * and uses non-atomic copy and kmap functions. */ | |
566 | static int | |
567 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
568 | char __user *user_data, | |
569 | bool page_do_bit17_swizzling, bool needs_clflush) | |
570 | { | |
571 | char *vaddr; | |
572 | int ret; | |
573 | ||
574 | vaddr = kmap(page); | |
575 | if (needs_clflush) | |
576 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, | |
577 | page_length, | |
578 | page_do_bit17_swizzling); | |
579 | ||
580 | if (page_do_bit17_swizzling) | |
581 | ret = __copy_to_user_swizzled(user_data, | |
582 | vaddr, shmem_page_offset, | |
583 | page_length); | |
584 | else | |
585 | ret = __copy_to_user(user_data, | |
586 | vaddr + shmem_page_offset, | |
587 | page_length); | |
588 | kunmap(page); | |
589 | ||
590 | return ret ? - EFAULT : 0; | |
591 | } | |
592 | ||
593 | static int | |
594 | i915_gem_shmem_pread(struct drm_device *dev, | |
595 | struct drm_i915_gem_object *obj, | |
596 | struct drm_i915_gem_pread *args, | |
597 | struct drm_file *file) | |
598 | { | |
599 | char __user *user_data; | |
600 | ssize_t remain; | |
601 | loff_t offset; | |
602 | int shmem_page_offset, page_length, ret = 0; | |
603 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; | |
604 | int prefaulted = 0; | |
605 | int needs_clflush = 0; | |
606 | struct sg_page_iter sg_iter; | |
607 | ||
608 | user_data = to_user_ptr(args->data_ptr); | |
609 | remain = args->size; | |
610 | ||
611 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); | |
612 | ||
613 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); | |
614 | if (ret) | |
615 | return ret; | |
616 | ||
617 | offset = args->offset; | |
618 | ||
619 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, | |
620 | offset >> PAGE_SHIFT) { | |
621 | struct page *page = sg_page_iter_page(&sg_iter); | |
622 | ||
623 | if (remain <= 0) | |
624 | break; | |
625 | ||
626 | /* Operation in this page | |
627 | * | |
628 | * shmem_page_offset = offset within page in shmem file | |
629 | * page_length = bytes to copy for this page | |
630 | */ | |
631 | shmem_page_offset = offset_in_page(offset); | |
632 | page_length = remain; | |
633 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
634 | page_length = PAGE_SIZE - shmem_page_offset; | |
635 | ||
636 | page_do_bit17_swizzling = obj_do_bit17_swizzling && | |
637 | (page_to_phys(page) & (1 << 17)) != 0; | |
638 | ||
639 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, | |
640 | user_data, page_do_bit17_swizzling, | |
641 | needs_clflush); | |
642 | if (ret == 0) | |
643 | goto next_page; | |
644 | ||
645 | mutex_unlock(&dev->struct_mutex); | |
646 | ||
647 | if (likely(!i915.prefault_disable) && !prefaulted) { | |
648 | ret = fault_in_multipages_writeable(user_data, remain); | |
649 | /* Userspace is tricking us, but we've already clobbered | |
650 | * its pages with the prefault and promised to write the | |
651 | * data up to the first fault. Hence ignore any errors | |
652 | * and just continue. */ | |
653 | (void)ret; | |
654 | prefaulted = 1; | |
655 | } | |
656 | ||
657 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, | |
658 | user_data, page_do_bit17_swizzling, | |
659 | needs_clflush); | |
660 | ||
661 | mutex_lock(&dev->struct_mutex); | |
662 | ||
663 | if (ret) | |
664 | goto out; | |
665 | ||
666 | next_page: | |
667 | remain -= page_length; | |
668 | user_data += page_length; | |
669 | offset += page_length; | |
670 | } | |
671 | ||
672 | out: | |
673 | i915_gem_object_unpin_pages(obj); | |
674 | ||
675 | return ret; | |
676 | } | |
677 | ||
678 | /** | |
679 | * Reads data from the object referenced by handle. | |
680 | * | |
681 | * On error, the contents of *data are undefined. | |
682 | */ | |
683 | int | |
684 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
685 | struct drm_file *file) | |
686 | { | |
687 | struct drm_i915_gem_pread *args = data; | |
688 | struct drm_i915_gem_object *obj; | |
689 | int ret = 0; | |
690 | ||
691 | if (args->size == 0) | |
692 | return 0; | |
693 | ||
694 | if (!access_ok(VERIFY_WRITE, | |
695 | to_user_ptr(args->data_ptr), | |
696 | args->size)) | |
697 | return -EFAULT; | |
698 | ||
699 | ret = i915_mutex_lock_interruptible(dev); | |
700 | if (ret) | |
701 | return ret; | |
702 | ||
703 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
704 | if (&obj->base == NULL) { | |
705 | ret = -ENOENT; | |
706 | goto unlock; | |
707 | } | |
708 | ||
709 | /* Bounds check source. */ | |
710 | if (args->offset > obj->base.size || | |
711 | args->size > obj->base.size - args->offset) { | |
712 | ret = -EINVAL; | |
713 | goto out; | |
714 | } | |
715 | ||
716 | /* prime objects have no backing filp to GEM pread/pwrite | |
717 | * pages from. | |
718 | */ | |
719 | if (!obj->base.filp) { | |
720 | ret = -EINVAL; | |
721 | goto out; | |
722 | } | |
723 | ||
724 | trace_i915_gem_object_pread(obj, args->offset, args->size); | |
725 | ||
726 | ret = i915_gem_shmem_pread(dev, obj, args, file); | |
727 | ||
728 | out: | |
729 | drm_gem_object_unreference(&obj->base); | |
730 | unlock: | |
731 | mutex_unlock(&dev->struct_mutex); | |
732 | return ret; | |
733 | } | |
734 | ||
735 | /* This is the fast write path which cannot handle | |
736 | * page faults in the source data | |
737 | */ | |
738 | ||
739 | static inline int | |
740 | fast_user_write(struct io_mapping *mapping, | |
741 | loff_t page_base, int page_offset, | |
742 | char __user *user_data, | |
743 | int length) | |
744 | { | |
745 | void __iomem *vaddr_atomic; | |
746 | void *vaddr; | |
747 | unsigned long unwritten; | |
748 | ||
749 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); | |
750 | /* We can use the cpu mem copy function because this is X86. */ | |
751 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
752 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
753 | user_data, length); | |
754 | io_mapping_unmap_atomic(vaddr_atomic); | |
755 | return unwritten; | |
756 | } | |
757 | ||
758 | /** | |
759 | * This is the fast pwrite path, where we copy the data directly from the | |
760 | * user into the GTT, uncached. | |
761 | */ | |
762 | static int | |
763 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, | |
764 | struct drm_i915_gem_object *obj, | |
765 | struct drm_i915_gem_pwrite *args, | |
766 | struct drm_file *file) | |
767 | { | |
768 | struct drm_i915_private *dev_priv = dev->dev_private; | |
769 | ssize_t remain; | |
770 | loff_t offset, page_base; | |
771 | char __user *user_data; | |
772 | int page_offset, page_length, ret; | |
773 | ||
774 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); | |
775 | if (ret) | |
776 | goto out; | |
777 | ||
778 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
779 | if (ret) | |
780 | goto out_unpin; | |
781 | ||
782 | ret = i915_gem_object_put_fence(obj); | |
783 | if (ret) | |
784 | goto out_unpin; | |
785 | ||
786 | user_data = to_user_ptr(args->data_ptr); | |
787 | remain = args->size; | |
788 | ||
789 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; | |
790 | ||
791 | intel_fb_obj_invalidate(obj, ORIGIN_GTT); | |
792 | ||
793 | while (remain > 0) { | |
794 | /* Operation in this page | |
795 | * | |
796 | * page_base = page offset within aperture | |
797 | * page_offset = offset within page | |
798 | * page_length = bytes to copy for this page | |
799 | */ | |
800 | page_base = offset & PAGE_MASK; | |
801 | page_offset = offset_in_page(offset); | |
802 | page_length = remain; | |
803 | if ((page_offset + remain) > PAGE_SIZE) | |
804 | page_length = PAGE_SIZE - page_offset; | |
805 | ||
806 | /* If we get a fault while copying data, then (presumably) our | |
807 | * source page isn't available. Return the error and we'll | |
808 | * retry in the slow path. | |
809 | */ | |
810 | if (fast_user_write(dev_priv->gtt.mappable, page_base, | |
811 | page_offset, user_data, page_length)) { | |
812 | ret = -EFAULT; | |
813 | goto out_flush; | |
814 | } | |
815 | ||
816 | remain -= page_length; | |
817 | user_data += page_length; | |
818 | offset += page_length; | |
819 | } | |
820 | ||
821 | out_flush: | |
822 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); | |
823 | out_unpin: | |
824 | i915_gem_object_ggtt_unpin(obj); | |
825 | out: | |
826 | return ret; | |
827 | } | |
828 | ||
829 | /* Per-page copy function for the shmem pwrite fastpath. | |
830 | * Flushes invalid cachelines before writing to the target if | |
831 | * needs_clflush_before is set and flushes out any written cachelines after | |
832 | * writing if needs_clflush is set. */ | |
833 | static int | |
834 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, | |
835 | char __user *user_data, | |
836 | bool page_do_bit17_swizzling, | |
837 | bool needs_clflush_before, | |
838 | bool needs_clflush_after) | |
839 | { | |
840 | char *vaddr; | |
841 | int ret; | |
842 | ||
843 | if (unlikely(page_do_bit17_swizzling)) | |
844 | return -EINVAL; | |
845 | ||
846 | vaddr = kmap_atomic(page); | |
847 | if (needs_clflush_before) | |
848 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
849 | page_length); | |
850 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, | |
851 | user_data, page_length); | |
852 | if (needs_clflush_after) | |
853 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
854 | page_length); | |
855 | kunmap_atomic(vaddr); | |
856 | ||
857 | return ret ? -EFAULT : 0; | |
858 | } | |
859 | ||
860 | /* Only difference to the fast-path function is that this can handle bit17 | |
861 | * and uses non-atomic copy and kmap functions. */ | |
862 | static int | |
863 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, | |
864 | char __user *user_data, | |
865 | bool page_do_bit17_swizzling, | |
866 | bool needs_clflush_before, | |
867 | bool needs_clflush_after) | |
868 | { | |
869 | char *vaddr; | |
870 | int ret; | |
871 | ||
872 | vaddr = kmap(page); | |
873 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) | |
874 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, | |
875 | page_length, | |
876 | page_do_bit17_swizzling); | |
877 | if (page_do_bit17_swizzling) | |
878 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
879 | user_data, | |
880 | page_length); | |
881 | else | |
882 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
883 | user_data, | |
884 | page_length); | |
885 | if (needs_clflush_after) | |
886 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, | |
887 | page_length, | |
888 | page_do_bit17_swizzling); | |
889 | kunmap(page); | |
890 | ||
891 | return ret ? -EFAULT : 0; | |
892 | } | |
893 | ||
894 | static int | |
895 | i915_gem_shmem_pwrite(struct drm_device *dev, | |
896 | struct drm_i915_gem_object *obj, | |
897 | struct drm_i915_gem_pwrite *args, | |
898 | struct drm_file *file) | |
899 | { | |
900 | ssize_t remain; | |
901 | loff_t offset; | |
902 | char __user *user_data; | |
903 | int shmem_page_offset, page_length, ret = 0; | |
904 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; | |
905 | int hit_slowpath = 0; | |
906 | int needs_clflush_after = 0; | |
907 | int needs_clflush_before = 0; | |
908 | struct sg_page_iter sg_iter; | |
909 | ||
910 | user_data = to_user_ptr(args->data_ptr); | |
911 | remain = args->size; | |
912 | ||
913 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); | |
914 | ||
915 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
916 | /* If we're not in the cpu write domain, set ourself into the gtt | |
917 | * write domain and manually flush cachelines (if required). This | |
918 | * optimizes for the case when the gpu will use the data | |
919 | * right away and we therefore have to clflush anyway. */ | |
920 | needs_clflush_after = cpu_write_needs_clflush(obj); | |
921 | ret = i915_gem_object_wait_rendering(obj, false); | |
922 | if (ret) | |
923 | return ret; | |
924 | } | |
925 | /* Same trick applies to invalidate partially written cachelines read | |
926 | * before writing. */ | |
927 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
928 | needs_clflush_before = | |
929 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
930 | ||
931 | ret = i915_gem_object_get_pages(obj); | |
932 | if (ret) | |
933 | return ret; | |
934 | ||
935 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); | |
936 | ||
937 | i915_gem_object_pin_pages(obj); | |
938 | ||
939 | offset = args->offset; | |
940 | obj->dirty = 1; | |
941 | ||
942 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, | |
943 | offset >> PAGE_SHIFT) { | |
944 | struct page *page = sg_page_iter_page(&sg_iter); | |
945 | int partial_cacheline_write; | |
946 | ||
947 | if (remain <= 0) | |
948 | break; | |
949 | ||
950 | /* Operation in this page | |
951 | * | |
952 | * shmem_page_offset = offset within page in shmem file | |
953 | * page_length = bytes to copy for this page | |
954 | */ | |
955 | shmem_page_offset = offset_in_page(offset); | |
956 | ||
957 | page_length = remain; | |
958 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
959 | page_length = PAGE_SIZE - shmem_page_offset; | |
960 | ||
961 | /* If we don't overwrite a cacheline completely we need to be | |
962 | * careful to have up-to-date data by first clflushing. Don't | |
963 | * overcomplicate things and flush the entire patch. */ | |
964 | partial_cacheline_write = needs_clflush_before && | |
965 | ((shmem_page_offset | page_length) | |
966 | & (boot_cpu_data.x86_clflush_size - 1)); | |
967 | ||
968 | page_do_bit17_swizzling = obj_do_bit17_swizzling && | |
969 | (page_to_phys(page) & (1 << 17)) != 0; | |
970 | ||
971 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, | |
972 | user_data, page_do_bit17_swizzling, | |
973 | partial_cacheline_write, | |
974 | needs_clflush_after); | |
975 | if (ret == 0) | |
976 | goto next_page; | |
977 | ||
978 | hit_slowpath = 1; | |
979 | mutex_unlock(&dev->struct_mutex); | |
980 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, | |
981 | user_data, page_do_bit17_swizzling, | |
982 | partial_cacheline_write, | |
983 | needs_clflush_after); | |
984 | ||
985 | mutex_lock(&dev->struct_mutex); | |
986 | ||
987 | if (ret) | |
988 | goto out; | |
989 | ||
990 | next_page: | |
991 | remain -= page_length; | |
992 | user_data += page_length; | |
993 | offset += page_length; | |
994 | } | |
995 | ||
996 | out: | |
997 | i915_gem_object_unpin_pages(obj); | |
998 | ||
999 | if (hit_slowpath) { | |
1000 | /* | |
1001 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
1002 | * cachelines in-line while writing and the object moved | |
1003 | * out of the cpu write domain while we've dropped the lock. | |
1004 | */ | |
1005 | if (!needs_clflush_after && | |
1006 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
1007 | if (i915_gem_clflush_object(obj, obj->pin_display)) | |
1008 | i915_gem_chipset_flush(dev); | |
1009 | } | |
1010 | } | |
1011 | ||
1012 | if (needs_clflush_after) | |
1013 | i915_gem_chipset_flush(dev); | |
1014 | ||
1015 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); | |
1016 | return ret; | |
1017 | } | |
1018 | ||
1019 | /** | |
1020 | * Writes data to the object referenced by handle. | |
1021 | * | |
1022 | * On error, the contents of the buffer that were to be modified are undefined. | |
1023 | */ | |
1024 | int | |
1025 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1026 | struct drm_file *file) | |
1027 | { | |
1028 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1029 | struct drm_i915_gem_pwrite *args = data; | |
1030 | struct drm_i915_gem_object *obj; | |
1031 | int ret; | |
1032 | ||
1033 | if (args->size == 0) | |
1034 | return 0; | |
1035 | ||
1036 | if (!access_ok(VERIFY_READ, | |
1037 | to_user_ptr(args->data_ptr), | |
1038 | args->size)) | |
1039 | return -EFAULT; | |
1040 | ||
1041 | if (likely(!i915.prefault_disable)) { | |
1042 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), | |
1043 | args->size); | |
1044 | if (ret) | |
1045 | return -EFAULT; | |
1046 | } | |
1047 | ||
1048 | intel_runtime_pm_get(dev_priv); | |
1049 | ||
1050 | ret = i915_mutex_lock_interruptible(dev); | |
1051 | if (ret) | |
1052 | goto put_rpm; | |
1053 | ||
1054 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
1055 | if (&obj->base == NULL) { | |
1056 | ret = -ENOENT; | |
1057 | goto unlock; | |
1058 | } | |
1059 | ||
1060 | /* Bounds check destination. */ | |
1061 | if (args->offset > obj->base.size || | |
1062 | args->size > obj->base.size - args->offset) { | |
1063 | ret = -EINVAL; | |
1064 | goto out; | |
1065 | } | |
1066 | ||
1067 | /* prime objects have no backing filp to GEM pread/pwrite | |
1068 | * pages from. | |
1069 | */ | |
1070 | if (!obj->base.filp) { | |
1071 | ret = -EINVAL; | |
1072 | goto out; | |
1073 | } | |
1074 | ||
1075 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); | |
1076 | ||
1077 | ret = -EFAULT; | |
1078 | /* We can only do the GTT pwrite on untiled buffers, as otherwise | |
1079 | * it would end up going through the fenced access, and we'll get | |
1080 | * different detiling behavior between reading and writing. | |
1081 | * pread/pwrite currently are reading and writing from the CPU | |
1082 | * perspective, requiring manual detiling by the client. | |
1083 | */ | |
1084 | if (obj->tiling_mode == I915_TILING_NONE && | |
1085 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
1086 | cpu_write_needs_clflush(obj)) { | |
1087 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); | |
1088 | /* Note that the gtt paths might fail with non-page-backed user | |
1089 | * pointers (e.g. gtt mappings when moving data between | |
1090 | * textures). Fallback to the shmem path in that case. */ | |
1091 | } | |
1092 | ||
1093 | if (ret == -EFAULT || ret == -ENOSPC) { | |
1094 | if (obj->phys_handle) | |
1095 | ret = i915_gem_phys_pwrite(obj, args, file); | |
1096 | else | |
1097 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); | |
1098 | } | |
1099 | ||
1100 | out: | |
1101 | drm_gem_object_unreference(&obj->base); | |
1102 | unlock: | |
1103 | mutex_unlock(&dev->struct_mutex); | |
1104 | put_rpm: | |
1105 | intel_runtime_pm_put(dev_priv); | |
1106 | ||
1107 | return ret; | |
1108 | } | |
1109 | ||
1110 | int | |
1111 | i915_gem_check_wedge(struct i915_gpu_error *error, | |
1112 | bool interruptible) | |
1113 | { | |
1114 | if (i915_reset_in_progress(error)) { | |
1115 | /* Non-interruptible callers can't handle -EAGAIN, hence return | |
1116 | * -EIO unconditionally for these. */ | |
1117 | if (!interruptible) | |
1118 | return -EIO; | |
1119 | ||
1120 | /* Recovery complete, but the reset failed ... */ | |
1121 | if (i915_terminally_wedged(error)) | |
1122 | return -EIO; | |
1123 | ||
1124 | /* | |
1125 | * Check if GPU Reset is in progress - we need intel_ring_begin | |
1126 | * to work properly to reinit the hw state while the gpu is | |
1127 | * still marked as reset-in-progress. Handle this with a flag. | |
1128 | */ | |
1129 | if (!error->reload_in_reset) | |
1130 | return -EAGAIN; | |
1131 | } | |
1132 | ||
1133 | return 0; | |
1134 | } | |
1135 | ||
1136 | static void fake_irq(unsigned long data) | |
1137 | { | |
1138 | wake_up_process((struct task_struct *)data); | |
1139 | } | |
1140 | ||
1141 | static bool missed_irq(struct drm_i915_private *dev_priv, | |
1142 | struct intel_engine_cs *ring) | |
1143 | { | |
1144 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); | |
1145 | } | |
1146 | ||
1147 | static int __i915_spin_request(struct drm_i915_gem_request *req) | |
1148 | { | |
1149 | unsigned long timeout; | |
1150 | ||
1151 | if (i915_gem_request_get_ring(req)->irq_refcount) | |
1152 | return -EBUSY; | |
1153 | ||
1154 | timeout = jiffies + 1; | |
1155 | while (!need_resched()) { | |
1156 | if (i915_gem_request_completed(req, true)) | |
1157 | return 0; | |
1158 | ||
1159 | if (time_after_eq(jiffies, timeout)) | |
1160 | break; | |
1161 | ||
1162 | cpu_relax_lowlatency(); | |
1163 | } | |
1164 | if (i915_gem_request_completed(req, false)) | |
1165 | return 0; | |
1166 | ||
1167 | return -EAGAIN; | |
1168 | } | |
1169 | ||
1170 | /** | |
1171 | * __i915_wait_request - wait until execution of request has finished | |
1172 | * @req: duh! | |
1173 | * @reset_counter: reset sequence associated with the given request | |
1174 | * @interruptible: do an interruptible wait (normally yes) | |
1175 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
1176 | * | |
1177 | * Note: It is of utmost importance that the passed in seqno and reset_counter | |
1178 | * values have been read by the caller in an smp safe manner. Where read-side | |
1179 | * locks are involved, it is sufficient to read the reset_counter before | |
1180 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
1181 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
1182 | * inserted. | |
1183 | * | |
1184 | * Returns 0 if the request was found within the alloted time. Else returns the | |
1185 | * errno with remaining time filled in timeout argument. | |
1186 | */ | |
1187 | int __i915_wait_request(struct drm_i915_gem_request *req, | |
1188 | unsigned reset_counter, | |
1189 | bool interruptible, | |
1190 | s64 *timeout, | |
1191 | struct intel_rps_client *rps) | |
1192 | { | |
1193 | struct intel_engine_cs *ring = i915_gem_request_get_ring(req); | |
1194 | struct drm_device *dev = ring->dev; | |
1195 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1196 | const bool irq_test_in_progress = | |
1197 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); | |
1198 | DEFINE_WAIT(wait); | |
1199 | unsigned long timeout_expire; | |
1200 | s64 before, now; | |
1201 | int ret; | |
1202 | ||
1203 | WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled"); | |
1204 | ||
1205 | if (list_empty(&req->list)) | |
1206 | return 0; | |
1207 | ||
1208 | if (i915_gem_request_completed(req, true)) | |
1209 | return 0; | |
1210 | ||
1211 | timeout_expire = timeout ? | |
1212 | jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0; | |
1213 | ||
1214 | if (INTEL_INFO(dev_priv)->gen >= 6) | |
1215 | gen6_rps_boost(dev_priv, rps, req->emitted_jiffies); | |
1216 | ||
1217 | /* Record current time in case interrupted by signal, or wedged */ | |
1218 | trace_i915_gem_request_wait_begin(req); | |
1219 | before = ktime_get_raw_ns(); | |
1220 | ||
1221 | /* Optimistic spin for the next jiffie before touching IRQs */ | |
1222 | ret = __i915_spin_request(req); | |
1223 | if (ret == 0) | |
1224 | goto out; | |
1225 | ||
1226 | if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) { | |
1227 | ret = -ENODEV; | |
1228 | goto out; | |
1229 | } | |
1230 | ||
1231 | for (;;) { | |
1232 | struct timer_list timer; | |
1233 | ||
1234 | prepare_to_wait(&ring->irq_queue, &wait, | |
1235 | interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); | |
1236 | ||
1237 | /* We need to check whether any gpu reset happened in between | |
1238 | * the caller grabbing the seqno and now ... */ | |
1239 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { | |
1240 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu | |
1241 | * is truely gone. */ | |
1242 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); | |
1243 | if (ret == 0) | |
1244 | ret = -EAGAIN; | |
1245 | break; | |
1246 | } | |
1247 | ||
1248 | if (i915_gem_request_completed(req, false)) { | |
1249 | ret = 0; | |
1250 | break; | |
1251 | } | |
1252 | ||
1253 | if (interruptible && signal_pending(current)) { | |
1254 | ret = -ERESTARTSYS; | |
1255 | break; | |
1256 | } | |
1257 | ||
1258 | if (timeout && time_after_eq(jiffies, timeout_expire)) { | |
1259 | ret = -ETIME; | |
1260 | break; | |
1261 | } | |
1262 | ||
1263 | timer.function = NULL; | |
1264 | if (timeout || missed_irq(dev_priv, ring)) { | |
1265 | unsigned long expire; | |
1266 | ||
1267 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); | |
1268 | expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire; | |
1269 | mod_timer(&timer, expire); | |
1270 | } | |
1271 | ||
1272 | io_schedule(); | |
1273 | ||
1274 | if (timer.function) { | |
1275 | del_singleshot_timer_sync(&timer); | |
1276 | destroy_timer_on_stack(&timer); | |
1277 | } | |
1278 | } | |
1279 | if (!irq_test_in_progress) | |
1280 | ring->irq_put(ring); | |
1281 | ||
1282 | finish_wait(&ring->irq_queue, &wait); | |
1283 | ||
1284 | out: | |
1285 | now = ktime_get_raw_ns(); | |
1286 | trace_i915_gem_request_wait_end(req); | |
1287 | ||
1288 | if (timeout) { | |
1289 | s64 tres = *timeout - (now - before); | |
1290 | ||
1291 | *timeout = tres < 0 ? 0 : tres; | |
1292 | ||
1293 | /* | |
1294 | * Apparently ktime isn't accurate enough and occasionally has a | |
1295 | * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch | |
1296 | * things up to make the test happy. We allow up to 1 jiffy. | |
1297 | * | |
1298 | * This is a regrssion from the timespec->ktime conversion. | |
1299 | */ | |
1300 | if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000) | |
1301 | *timeout = 0; | |
1302 | } | |
1303 | ||
1304 | return ret; | |
1305 | } | |
1306 | ||
1307 | int i915_gem_request_add_to_client(struct drm_i915_gem_request *req, | |
1308 | struct drm_file *file) | |
1309 | { | |
1310 | struct drm_i915_private *dev_private; | |
1311 | struct drm_i915_file_private *file_priv; | |
1312 | ||
1313 | WARN_ON(!req || !file || req->file_priv); | |
1314 | ||
1315 | if (!req || !file) | |
1316 | return -EINVAL; | |
1317 | ||
1318 | if (req->file_priv) | |
1319 | return -EINVAL; | |
1320 | ||
1321 | dev_private = req->ring->dev->dev_private; | |
1322 | file_priv = file->driver_priv; | |
1323 | ||
1324 | spin_lock(&file_priv->mm.lock); | |
1325 | req->file_priv = file_priv; | |
1326 | list_add_tail(&req->client_list, &file_priv->mm.request_list); | |
1327 | spin_unlock(&file_priv->mm.lock); | |
1328 | ||
1329 | req->pid = get_pid(task_pid(current)); | |
1330 | ||
1331 | return 0; | |
1332 | } | |
1333 | ||
1334 | static inline void | |
1335 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
1336 | { | |
1337 | struct drm_i915_file_private *file_priv = request->file_priv; | |
1338 | ||
1339 | if (!file_priv) | |
1340 | return; | |
1341 | ||
1342 | spin_lock(&file_priv->mm.lock); | |
1343 | list_del(&request->client_list); | |
1344 | request->file_priv = NULL; | |
1345 | spin_unlock(&file_priv->mm.lock); | |
1346 | ||
1347 | put_pid(request->pid); | |
1348 | request->pid = NULL; | |
1349 | } | |
1350 | ||
1351 | static void i915_gem_request_retire(struct drm_i915_gem_request *request) | |
1352 | { | |
1353 | trace_i915_gem_request_retire(request); | |
1354 | ||
1355 | /* We know the GPU must have read the request to have | |
1356 | * sent us the seqno + interrupt, so use the position | |
1357 | * of tail of the request to update the last known position | |
1358 | * of the GPU head. | |
1359 | * | |
1360 | * Note this requires that we are always called in request | |
1361 | * completion order. | |
1362 | */ | |
1363 | request->ringbuf->last_retired_head = request->postfix; | |
1364 | ||
1365 | list_del_init(&request->list); | |
1366 | i915_gem_request_remove_from_client(request); | |
1367 | ||
1368 | i915_gem_request_unreference(request); | |
1369 | } | |
1370 | ||
1371 | static void | |
1372 | __i915_gem_request_retire__upto(struct drm_i915_gem_request *req) | |
1373 | { | |
1374 | struct intel_engine_cs *engine = req->ring; | |
1375 | struct drm_i915_gem_request *tmp; | |
1376 | ||
1377 | lockdep_assert_held(&engine->dev->struct_mutex); | |
1378 | ||
1379 | if (list_empty(&req->list)) | |
1380 | return; | |
1381 | ||
1382 | do { | |
1383 | tmp = list_first_entry(&engine->request_list, | |
1384 | typeof(*tmp), list); | |
1385 | ||
1386 | i915_gem_request_retire(tmp); | |
1387 | } while (tmp != req); | |
1388 | ||
1389 | WARN_ON(i915_verify_lists(engine->dev)); | |
1390 | } | |
1391 | ||
1392 | /** | |
1393 | * Waits for a request to be signaled, and cleans up the | |
1394 | * request and object lists appropriately for that event. | |
1395 | */ | |
1396 | int | |
1397 | i915_wait_request(struct drm_i915_gem_request *req) | |
1398 | { | |
1399 | struct drm_device *dev; | |
1400 | struct drm_i915_private *dev_priv; | |
1401 | bool interruptible; | |
1402 | int ret; | |
1403 | ||
1404 | BUG_ON(req == NULL); | |
1405 | ||
1406 | dev = req->ring->dev; | |
1407 | dev_priv = dev->dev_private; | |
1408 | interruptible = dev_priv->mm.interruptible; | |
1409 | ||
1410 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1411 | ||
1412 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); | |
1413 | if (ret) | |
1414 | return ret; | |
1415 | ||
1416 | ret = __i915_wait_request(req, | |
1417 | atomic_read(&dev_priv->gpu_error.reset_counter), | |
1418 | interruptible, NULL, NULL); | |
1419 | if (ret) | |
1420 | return ret; | |
1421 | ||
1422 | __i915_gem_request_retire__upto(req); | |
1423 | return 0; | |
1424 | } | |
1425 | ||
1426 | /** | |
1427 | * Ensures that all rendering to the object has completed and the object is | |
1428 | * safe to unbind from the GTT or access from the CPU. | |
1429 | */ | |
1430 | int | |
1431 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1432 | bool readonly) | |
1433 | { | |
1434 | int ret, i; | |
1435 | ||
1436 | if (!obj->active) | |
1437 | return 0; | |
1438 | ||
1439 | if (readonly) { | |
1440 | if (obj->last_write_req != NULL) { | |
1441 | ret = i915_wait_request(obj->last_write_req); | |
1442 | if (ret) | |
1443 | return ret; | |
1444 | ||
1445 | i = obj->last_write_req->ring->id; | |
1446 | if (obj->last_read_req[i] == obj->last_write_req) | |
1447 | i915_gem_object_retire__read(obj, i); | |
1448 | else | |
1449 | i915_gem_object_retire__write(obj); | |
1450 | } | |
1451 | } else { | |
1452 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
1453 | if (obj->last_read_req[i] == NULL) | |
1454 | continue; | |
1455 | ||
1456 | ret = i915_wait_request(obj->last_read_req[i]); | |
1457 | if (ret) | |
1458 | return ret; | |
1459 | ||
1460 | i915_gem_object_retire__read(obj, i); | |
1461 | } | |
1462 | RQ_BUG_ON(obj->active); | |
1463 | } | |
1464 | ||
1465 | return 0; | |
1466 | } | |
1467 | ||
1468 | static void | |
1469 | i915_gem_object_retire_request(struct drm_i915_gem_object *obj, | |
1470 | struct drm_i915_gem_request *req) | |
1471 | { | |
1472 | int ring = req->ring->id; | |
1473 | ||
1474 | if (obj->last_read_req[ring] == req) | |
1475 | i915_gem_object_retire__read(obj, ring); | |
1476 | else if (obj->last_write_req == req) | |
1477 | i915_gem_object_retire__write(obj); | |
1478 | ||
1479 | __i915_gem_request_retire__upto(req); | |
1480 | } | |
1481 | ||
1482 | /* A nonblocking variant of the above wait. This is a highly dangerous routine | |
1483 | * as the object state may change during this call. | |
1484 | */ | |
1485 | static __must_check int | |
1486 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
1487 | struct intel_rps_client *rps, | |
1488 | bool readonly) | |
1489 | { | |
1490 | struct drm_device *dev = obj->base.dev; | |
1491 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1492 | struct drm_i915_gem_request *requests[I915_NUM_RINGS]; | |
1493 | unsigned reset_counter; | |
1494 | int ret, i, n = 0; | |
1495 | ||
1496 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1497 | BUG_ON(!dev_priv->mm.interruptible); | |
1498 | ||
1499 | if (!obj->active) | |
1500 | return 0; | |
1501 | ||
1502 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); | |
1503 | if (ret) | |
1504 | return ret; | |
1505 | ||
1506 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); | |
1507 | ||
1508 | if (readonly) { | |
1509 | struct drm_i915_gem_request *req; | |
1510 | ||
1511 | req = obj->last_write_req; | |
1512 | if (req == NULL) | |
1513 | return 0; | |
1514 | ||
1515 | requests[n++] = i915_gem_request_reference(req); | |
1516 | } else { | |
1517 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
1518 | struct drm_i915_gem_request *req; | |
1519 | ||
1520 | req = obj->last_read_req[i]; | |
1521 | if (req == NULL) | |
1522 | continue; | |
1523 | ||
1524 | requests[n++] = i915_gem_request_reference(req); | |
1525 | } | |
1526 | } | |
1527 | ||
1528 | mutex_unlock(&dev->struct_mutex); | |
1529 | for (i = 0; ret == 0 && i < n; i++) | |
1530 | ret = __i915_wait_request(requests[i], reset_counter, true, | |
1531 | NULL, rps); | |
1532 | mutex_lock(&dev->struct_mutex); | |
1533 | ||
1534 | for (i = 0; i < n; i++) { | |
1535 | if (ret == 0) | |
1536 | i915_gem_object_retire_request(obj, requests[i]); | |
1537 | i915_gem_request_unreference(requests[i]); | |
1538 | } | |
1539 | ||
1540 | return ret; | |
1541 | } | |
1542 | ||
1543 | static struct intel_rps_client *to_rps_client(struct drm_file *file) | |
1544 | { | |
1545 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
1546 | return &fpriv->rps; | |
1547 | } | |
1548 | ||
1549 | /** | |
1550 | * Called when user space prepares to use an object with the CPU, either | |
1551 | * through the mmap ioctl's mapping or a GTT mapping. | |
1552 | */ | |
1553 | int | |
1554 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
1555 | struct drm_file *file) | |
1556 | { | |
1557 | struct drm_i915_gem_set_domain *args = data; | |
1558 | struct drm_i915_gem_object *obj; | |
1559 | uint32_t read_domains = args->read_domains; | |
1560 | uint32_t write_domain = args->write_domain; | |
1561 | int ret; | |
1562 | ||
1563 | /* Only handle setting domains to types used by the CPU. */ | |
1564 | if (write_domain & I915_GEM_GPU_DOMAINS) | |
1565 | return -EINVAL; | |
1566 | ||
1567 | if (read_domains & I915_GEM_GPU_DOMAINS) | |
1568 | return -EINVAL; | |
1569 | ||
1570 | /* Having something in the write domain implies it's in the read | |
1571 | * domain, and only that read domain. Enforce that in the request. | |
1572 | */ | |
1573 | if (write_domain != 0 && read_domains != write_domain) | |
1574 | return -EINVAL; | |
1575 | ||
1576 | ret = i915_mutex_lock_interruptible(dev); | |
1577 | if (ret) | |
1578 | return ret; | |
1579 | ||
1580 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
1581 | if (&obj->base == NULL) { | |
1582 | ret = -ENOENT; | |
1583 | goto unlock; | |
1584 | } | |
1585 | ||
1586 | /* Try to flush the object off the GPU without holding the lock. | |
1587 | * We will repeat the flush holding the lock in the normal manner | |
1588 | * to catch cases where we are gazumped. | |
1589 | */ | |
1590 | ret = i915_gem_object_wait_rendering__nonblocking(obj, | |
1591 | to_rps_client(file), | |
1592 | !write_domain); | |
1593 | if (ret) | |
1594 | goto unref; | |
1595 | ||
1596 | if (read_domains & I915_GEM_DOMAIN_GTT) | |
1597 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
1598 | else | |
1599 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); | |
1600 | ||
1601 | if (write_domain != 0) | |
1602 | intel_fb_obj_invalidate(obj, | |
1603 | write_domain == I915_GEM_DOMAIN_GTT ? | |
1604 | ORIGIN_GTT : ORIGIN_CPU); | |
1605 | ||
1606 | unref: | |
1607 | drm_gem_object_unreference(&obj->base); | |
1608 | unlock: | |
1609 | mutex_unlock(&dev->struct_mutex); | |
1610 | return ret; | |
1611 | } | |
1612 | ||
1613 | /** | |
1614 | * Called when user space has done writes to this buffer | |
1615 | */ | |
1616 | int | |
1617 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1618 | struct drm_file *file) | |
1619 | { | |
1620 | struct drm_i915_gem_sw_finish *args = data; | |
1621 | struct drm_i915_gem_object *obj; | |
1622 | int ret = 0; | |
1623 | ||
1624 | ret = i915_mutex_lock_interruptible(dev); | |
1625 | if (ret) | |
1626 | return ret; | |
1627 | ||
1628 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
1629 | if (&obj->base == NULL) { | |
1630 | ret = -ENOENT; | |
1631 | goto unlock; | |
1632 | } | |
1633 | ||
1634 | /* Pinned buffers may be scanout, so flush the cache */ | |
1635 | if (obj->pin_display) | |
1636 | i915_gem_object_flush_cpu_write_domain(obj); | |
1637 | ||
1638 | drm_gem_object_unreference(&obj->base); | |
1639 | unlock: | |
1640 | mutex_unlock(&dev->struct_mutex); | |
1641 | return ret; | |
1642 | } | |
1643 | ||
1644 | /** | |
1645 | * Maps the contents of an object, returning the address it is mapped | |
1646 | * into. | |
1647 | * | |
1648 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1649 | * imply a ref on the object itself. | |
1650 | * | |
1651 | * IMPORTANT: | |
1652 | * | |
1653 | * DRM driver writers who look a this function as an example for how to do GEM | |
1654 | * mmap support, please don't implement mmap support like here. The modern way | |
1655 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1656 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1657 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1658 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1659 | * does cpu mmaps this way because we didn't know better. | |
1660 | */ | |
1661 | int | |
1662 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1663 | struct drm_file *file) | |
1664 | { | |
1665 | struct drm_i915_gem_mmap *args = data; | |
1666 | struct drm_gem_object *obj; | |
1667 | unsigned long addr; | |
1668 | ||
1669 | if (args->flags & ~(I915_MMAP_WC)) | |
1670 | return -EINVAL; | |
1671 | ||
1672 | if (args->flags & I915_MMAP_WC && !cpu_has_pat) | |
1673 | return -ENODEV; | |
1674 | ||
1675 | obj = drm_gem_object_lookup(dev, file, args->handle); | |
1676 | if (obj == NULL) | |
1677 | return -ENOENT; | |
1678 | ||
1679 | /* prime objects have no backing filp to GEM mmap | |
1680 | * pages from. | |
1681 | */ | |
1682 | if (!obj->filp) { | |
1683 | drm_gem_object_unreference_unlocked(obj); | |
1684 | return -EINVAL; | |
1685 | } | |
1686 | ||
1687 | addr = vm_mmap(obj->filp, 0, args->size, | |
1688 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1689 | args->offset); | |
1690 | if (args->flags & I915_MMAP_WC) { | |
1691 | struct mm_struct *mm = current->mm; | |
1692 | struct vm_area_struct *vma; | |
1693 | ||
1694 | down_write(&mm->mmap_sem); | |
1695 | vma = find_vma(mm, addr); | |
1696 | if (vma) | |
1697 | vma->vm_page_prot = | |
1698 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1699 | else | |
1700 | addr = -ENOMEM; | |
1701 | up_write(&mm->mmap_sem); | |
1702 | } | |
1703 | drm_gem_object_unreference_unlocked(obj); | |
1704 | if (IS_ERR((void *)addr)) | |
1705 | return addr; | |
1706 | ||
1707 | args->addr_ptr = (uint64_t) addr; | |
1708 | ||
1709 | return 0; | |
1710 | } | |
1711 | ||
1712 | /** | |
1713 | * i915_gem_fault - fault a page into the GTT | |
1714 | * vma: VMA in question | |
1715 | * vmf: fault info | |
1716 | * | |
1717 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1718 | * from userspace. The fault handler takes care of binding the object to | |
1719 | * the GTT (if needed), allocating and programming a fence register (again, | |
1720 | * only if needed based on whether the old reg is still valid or the object | |
1721 | * is tiled) and inserting a new PTE into the faulting process. | |
1722 | * | |
1723 | * Note that the faulting process may involve evicting existing objects | |
1724 | * from the GTT and/or fence registers to make room. So performance may | |
1725 | * suffer if the GTT working set is large or there are few fence registers | |
1726 | * left. | |
1727 | */ | |
1728 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1729 | { | |
1730 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); | |
1731 | struct drm_device *dev = obj->base.dev; | |
1732 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1733 | struct i915_ggtt_view view = i915_ggtt_view_normal; | |
1734 | pgoff_t page_offset; | |
1735 | unsigned long pfn; | |
1736 | int ret = 0; | |
1737 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); | |
1738 | ||
1739 | intel_runtime_pm_get(dev_priv); | |
1740 | ||
1741 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1742 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1743 | PAGE_SHIFT; | |
1744 | ||
1745 | ret = i915_mutex_lock_interruptible(dev); | |
1746 | if (ret) | |
1747 | goto out; | |
1748 | ||
1749 | trace_i915_gem_object_fault(obj, page_offset, true, write); | |
1750 | ||
1751 | /* Try to flush the object off the GPU first without holding the lock. | |
1752 | * Upon reacquiring the lock, we will perform our sanity checks and then | |
1753 | * repeat the flush holding the lock in the normal manner to catch cases | |
1754 | * where we are gazumped. | |
1755 | */ | |
1756 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); | |
1757 | if (ret) | |
1758 | goto unlock; | |
1759 | ||
1760 | /* Access to snoopable pages through the GTT is incoherent. */ | |
1761 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
1762 | ret = -EFAULT; | |
1763 | goto unlock; | |
1764 | } | |
1765 | ||
1766 | /* Use a partial view if the object is bigger than the aperture. */ | |
1767 | if (obj->base.size >= dev_priv->gtt.mappable_end && | |
1768 | obj->tiling_mode == I915_TILING_NONE) { | |
1769 | static const unsigned int chunk_size = 256; // 1 MiB | |
1770 | ||
1771 | memset(&view, 0, sizeof(view)); | |
1772 | view.type = I915_GGTT_VIEW_PARTIAL; | |
1773 | view.params.partial.offset = rounddown(page_offset, chunk_size); | |
1774 | view.params.partial.size = | |
1775 | min_t(unsigned int, | |
1776 | chunk_size, | |
1777 | (vma->vm_end - vma->vm_start)/PAGE_SIZE - | |
1778 | view.params.partial.offset); | |
1779 | } | |
1780 | ||
1781 | /* Now pin it into the GTT if needed */ | |
1782 | ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE); | |
1783 | if (ret) | |
1784 | goto unlock; | |
1785 | ||
1786 | ret = i915_gem_object_set_to_gtt_domain(obj, write); | |
1787 | if (ret) | |
1788 | goto unpin; | |
1789 | ||
1790 | ret = i915_gem_object_get_fence(obj); | |
1791 | if (ret) | |
1792 | goto unpin; | |
1793 | ||
1794 | /* Finally, remap it using the new GTT offset */ | |
1795 | pfn = dev_priv->gtt.mappable_base + | |
1796 | i915_gem_obj_ggtt_offset_view(obj, &view); | |
1797 | pfn >>= PAGE_SHIFT; | |
1798 | ||
1799 | if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) { | |
1800 | /* Overriding existing pages in partial view does not cause | |
1801 | * us any trouble as TLBs are still valid because the fault | |
1802 | * is due to userspace losing part of the mapping or never | |
1803 | * having accessed it before (at this partials' range). | |
1804 | */ | |
1805 | unsigned long base = vma->vm_start + | |
1806 | (view.params.partial.offset << PAGE_SHIFT); | |
1807 | unsigned int i; | |
1808 | ||
1809 | for (i = 0; i < view.params.partial.size; i++) { | |
1810 | ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i); | |
1811 | if (ret) | |
1812 | break; | |
1813 | } | |
1814 | ||
1815 | obj->fault_mappable = true; | |
1816 | } else { | |
1817 | if (!obj->fault_mappable) { | |
1818 | unsigned long size = min_t(unsigned long, | |
1819 | vma->vm_end - vma->vm_start, | |
1820 | obj->base.size); | |
1821 | int i; | |
1822 | ||
1823 | for (i = 0; i < size >> PAGE_SHIFT; i++) { | |
1824 | ret = vm_insert_pfn(vma, | |
1825 | (unsigned long)vma->vm_start + i * PAGE_SIZE, | |
1826 | pfn + i); | |
1827 | if (ret) | |
1828 | break; | |
1829 | } | |
1830 | ||
1831 | obj->fault_mappable = true; | |
1832 | } else | |
1833 | ret = vm_insert_pfn(vma, | |
1834 | (unsigned long)vmf->virtual_address, | |
1835 | pfn + page_offset); | |
1836 | } | |
1837 | unpin: | |
1838 | i915_gem_object_ggtt_unpin_view(obj, &view); | |
1839 | unlock: | |
1840 | mutex_unlock(&dev->struct_mutex); | |
1841 | out: | |
1842 | switch (ret) { | |
1843 | case -EIO: | |
1844 | /* | |
1845 | * We eat errors when the gpu is terminally wedged to avoid | |
1846 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1847 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1848 | * and so needs to be reported. | |
1849 | */ | |
1850 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
1851 | ret = VM_FAULT_SIGBUS; | |
1852 | break; | |
1853 | } | |
1854 | case -EAGAIN: | |
1855 | /* | |
1856 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1857 | * handler to reset everything when re-faulting in | |
1858 | * i915_mutex_lock_interruptible. | |
1859 | */ | |
1860 | case 0: | |
1861 | case -ERESTARTSYS: | |
1862 | case -EINTR: | |
1863 | case -EBUSY: | |
1864 | /* | |
1865 | * EBUSY is ok: this just means that another thread | |
1866 | * already did the job. | |
1867 | */ | |
1868 | ret = VM_FAULT_NOPAGE; | |
1869 | break; | |
1870 | case -ENOMEM: | |
1871 | ret = VM_FAULT_OOM; | |
1872 | break; | |
1873 | case -ENOSPC: | |
1874 | case -EFAULT: | |
1875 | ret = VM_FAULT_SIGBUS; | |
1876 | break; | |
1877 | default: | |
1878 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); | |
1879 | ret = VM_FAULT_SIGBUS; | |
1880 | break; | |
1881 | } | |
1882 | ||
1883 | intel_runtime_pm_put(dev_priv); | |
1884 | return ret; | |
1885 | } | |
1886 | ||
1887 | /** | |
1888 | * i915_gem_release_mmap - remove physical page mappings | |
1889 | * @obj: obj in question | |
1890 | * | |
1891 | * Preserve the reservation of the mmapping with the DRM core code, but | |
1892 | * relinquish ownership of the pages back to the system. | |
1893 | * | |
1894 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1895 | * object through the GTT and then lose the fence register due to | |
1896 | * resource pressure. Similarly if the object has been moved out of the | |
1897 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1898 | * mapping will then trigger a page fault on the next user access, allowing | |
1899 | * fixup by i915_gem_fault(). | |
1900 | */ | |
1901 | void | |
1902 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) | |
1903 | { | |
1904 | if (!obj->fault_mappable) | |
1905 | return; | |
1906 | ||
1907 | drm_vma_node_unmap(&obj->base.vma_node, | |
1908 | obj->base.dev->anon_inode->i_mapping); | |
1909 | obj->fault_mappable = false; | |
1910 | } | |
1911 | ||
1912 | void | |
1913 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) | |
1914 | { | |
1915 | struct drm_i915_gem_object *obj; | |
1916 | ||
1917 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) | |
1918 | i915_gem_release_mmap(obj); | |
1919 | } | |
1920 | ||
1921 | uint32_t | |
1922 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) | |
1923 | { | |
1924 | uint32_t gtt_size; | |
1925 | ||
1926 | if (INTEL_INFO(dev)->gen >= 4 || | |
1927 | tiling_mode == I915_TILING_NONE) | |
1928 | return size; | |
1929 | ||
1930 | /* Previous chips need a power-of-two fence region when tiling */ | |
1931 | if (INTEL_INFO(dev)->gen == 3) | |
1932 | gtt_size = 1024*1024; | |
1933 | else | |
1934 | gtt_size = 512*1024; | |
1935 | ||
1936 | while (gtt_size < size) | |
1937 | gtt_size <<= 1; | |
1938 | ||
1939 | return gtt_size; | |
1940 | } | |
1941 | ||
1942 | /** | |
1943 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1944 | * @obj: object to check | |
1945 | * | |
1946 | * Return the required GTT alignment for an object, taking into account | |
1947 | * potential fence register mapping. | |
1948 | */ | |
1949 | uint32_t | |
1950 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1951 | int tiling_mode, bool fenced) | |
1952 | { | |
1953 | /* | |
1954 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1955 | * if a fence register is needed for the object. | |
1956 | */ | |
1957 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || | |
1958 | tiling_mode == I915_TILING_NONE) | |
1959 | return 4096; | |
1960 | ||
1961 | /* | |
1962 | * Previous chips need to be aligned to the size of the smallest | |
1963 | * fence register that can contain the object. | |
1964 | */ | |
1965 | return i915_gem_get_gtt_size(dev, size, tiling_mode); | |
1966 | } | |
1967 | ||
1968 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) | |
1969 | { | |
1970 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1971 | int ret; | |
1972 | ||
1973 | if (drm_vma_node_has_offset(&obj->base.vma_node)) | |
1974 | return 0; | |
1975 | ||
1976 | dev_priv->mm.shrinker_no_lock_stealing = true; | |
1977 | ||
1978 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1979 | if (ret != -ENOSPC) | |
1980 | goto out; | |
1981 | ||
1982 | /* Badly fragmented mmap space? The only way we can recover | |
1983 | * space is by destroying unwanted objects. We can't randomly release | |
1984 | * mmap_offsets as userspace expects them to be persistent for the | |
1985 | * lifetime of the objects. The closest we can is to release the | |
1986 | * offsets on purgeable objects by truncating it and marking it purged, | |
1987 | * which prevents userspace from ever using that object again. | |
1988 | */ | |
1989 | i915_gem_shrink(dev_priv, | |
1990 | obj->base.size >> PAGE_SHIFT, | |
1991 | I915_SHRINK_BOUND | | |
1992 | I915_SHRINK_UNBOUND | | |
1993 | I915_SHRINK_PURGEABLE); | |
1994 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1995 | if (ret != -ENOSPC) | |
1996 | goto out; | |
1997 | ||
1998 | i915_gem_shrink_all(dev_priv); | |
1999 | ret = drm_gem_create_mmap_offset(&obj->base); | |
2000 | out: | |
2001 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
2002 | ||
2003 | return ret; | |
2004 | } | |
2005 | ||
2006 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
2007 | { | |
2008 | drm_gem_free_mmap_offset(&obj->base); | |
2009 | } | |
2010 | ||
2011 | int | |
2012 | i915_gem_mmap_gtt(struct drm_file *file, | |
2013 | struct drm_device *dev, | |
2014 | uint32_t handle, | |
2015 | uint64_t *offset) | |
2016 | { | |
2017 | struct drm_i915_gem_object *obj; | |
2018 | int ret; | |
2019 | ||
2020 | ret = i915_mutex_lock_interruptible(dev); | |
2021 | if (ret) | |
2022 | return ret; | |
2023 | ||
2024 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); | |
2025 | if (&obj->base == NULL) { | |
2026 | ret = -ENOENT; | |
2027 | goto unlock; | |
2028 | } | |
2029 | ||
2030 | if (obj->madv != I915_MADV_WILLNEED) { | |
2031 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); | |
2032 | ret = -EFAULT; | |
2033 | goto out; | |
2034 | } | |
2035 | ||
2036 | ret = i915_gem_object_create_mmap_offset(obj); | |
2037 | if (ret) | |
2038 | goto out; | |
2039 | ||
2040 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); | |
2041 | ||
2042 | out: | |
2043 | drm_gem_object_unreference(&obj->base); | |
2044 | unlock: | |
2045 | mutex_unlock(&dev->struct_mutex); | |
2046 | return ret; | |
2047 | } | |
2048 | ||
2049 | /** | |
2050 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
2051 | * @dev: DRM device | |
2052 | * @data: GTT mapping ioctl data | |
2053 | * @file: GEM object info | |
2054 | * | |
2055 | * Simply returns the fake offset to userspace so it can mmap it. | |
2056 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
2057 | * up so we can get faults in the handler above. | |
2058 | * | |
2059 | * The fault handler will take care of binding the object into the GTT | |
2060 | * (since it may have been evicted to make room for something), allocating | |
2061 | * a fence register, and mapping the appropriate aperture address into | |
2062 | * userspace. | |
2063 | */ | |
2064 | int | |
2065 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
2066 | struct drm_file *file) | |
2067 | { | |
2068 | struct drm_i915_gem_mmap_gtt *args = data; | |
2069 | ||
2070 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); | |
2071 | } | |
2072 | ||
2073 | /* Immediately discard the backing storage */ | |
2074 | static void | |
2075 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
2076 | { | |
2077 | i915_gem_object_free_mmap_offset(obj); | |
2078 | ||
2079 | if (obj->base.filp == NULL) | |
2080 | return; | |
2081 | ||
2082 | /* Our goal here is to return as much of the memory as | |
2083 | * is possible back to the system as we are called from OOM. | |
2084 | * To do this we must instruct the shmfs to drop all of its | |
2085 | * backing pages, *now*. | |
2086 | */ | |
2087 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); | |
2088 | obj->madv = __I915_MADV_PURGED; | |
2089 | } | |
2090 | ||
2091 | /* Try to discard unwanted pages */ | |
2092 | static void | |
2093 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) | |
2094 | { | |
2095 | struct address_space *mapping; | |
2096 | ||
2097 | switch (obj->madv) { | |
2098 | case I915_MADV_DONTNEED: | |
2099 | i915_gem_object_truncate(obj); | |
2100 | case __I915_MADV_PURGED: | |
2101 | return; | |
2102 | } | |
2103 | ||
2104 | if (obj->base.filp == NULL) | |
2105 | return; | |
2106 | ||
2107 | mapping = file_inode(obj->base.filp)->i_mapping, | |
2108 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); | |
2109 | } | |
2110 | ||
2111 | static void | |
2112 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) | |
2113 | { | |
2114 | struct sg_page_iter sg_iter; | |
2115 | int ret; | |
2116 | ||
2117 | BUG_ON(obj->madv == __I915_MADV_PURGED); | |
2118 | ||
2119 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
2120 | if (ret) { | |
2121 | /* In the event of a disaster, abandon all caches and | |
2122 | * hope for the best. | |
2123 | */ | |
2124 | WARN_ON(ret != -EIO); | |
2125 | i915_gem_clflush_object(obj, true); | |
2126 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
2127 | } | |
2128 | ||
2129 | i915_gem_gtt_finish_object(obj); | |
2130 | ||
2131 | if (i915_gem_object_needs_bit17_swizzle(obj)) | |
2132 | i915_gem_object_save_bit_17_swizzle(obj); | |
2133 | ||
2134 | if (obj->madv == I915_MADV_DONTNEED) | |
2135 | obj->dirty = 0; | |
2136 | ||
2137 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { | |
2138 | struct page *page = sg_page_iter_page(&sg_iter); | |
2139 | ||
2140 | if (obj->dirty) | |
2141 | set_page_dirty(page); | |
2142 | ||
2143 | if (obj->madv == I915_MADV_WILLNEED) | |
2144 | mark_page_accessed(page); | |
2145 | ||
2146 | page_cache_release(page); | |
2147 | } | |
2148 | obj->dirty = 0; | |
2149 | ||
2150 | sg_free_table(obj->pages); | |
2151 | kfree(obj->pages); | |
2152 | } | |
2153 | ||
2154 | int | |
2155 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) | |
2156 | { | |
2157 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2158 | ||
2159 | if (obj->pages == NULL) | |
2160 | return 0; | |
2161 | ||
2162 | if (obj->pages_pin_count) | |
2163 | return -EBUSY; | |
2164 | ||
2165 | BUG_ON(i915_gem_obj_bound_any(obj)); | |
2166 | ||
2167 | /* ->put_pages might need to allocate memory for the bit17 swizzle | |
2168 | * array, hence protect them from being reaped by removing them from gtt | |
2169 | * lists early. */ | |
2170 | list_del(&obj->global_list); | |
2171 | ||
2172 | ops->put_pages(obj); | |
2173 | obj->pages = NULL; | |
2174 | ||
2175 | i915_gem_object_invalidate(obj); | |
2176 | ||
2177 | return 0; | |
2178 | } | |
2179 | ||
2180 | static int | |
2181 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) | |
2182 | { | |
2183 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2184 | int page_count, i; | |
2185 | struct address_space *mapping; | |
2186 | struct sg_table *st; | |
2187 | struct scatterlist *sg; | |
2188 | struct sg_page_iter sg_iter; | |
2189 | struct page *page; | |
2190 | unsigned long last_pfn = 0; /* suppress gcc warning */ | |
2191 | int ret; | |
2192 | gfp_t gfp; | |
2193 | ||
2194 | /* Assert that the object is not currently in any GPU domain. As it | |
2195 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2196 | * a GPU cache | |
2197 | */ | |
2198 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
2199 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
2200 | ||
2201 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
2202 | if (st == NULL) | |
2203 | return -ENOMEM; | |
2204 | ||
2205 | page_count = obj->base.size / PAGE_SIZE; | |
2206 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { | |
2207 | kfree(st); | |
2208 | return -ENOMEM; | |
2209 | } | |
2210 | ||
2211 | /* Get the list of pages out of our struct file. They'll be pinned | |
2212 | * at this point until we release them. | |
2213 | * | |
2214 | * Fail silently without starting the shrinker | |
2215 | */ | |
2216 | mapping = file_inode(obj->base.filp)->i_mapping; | |
2217 | gfp = mapping_gfp_mask(mapping); | |
2218 | gfp |= __GFP_NORETRY | __GFP_NOWARN; | |
2219 | gfp &= ~(__GFP_IO | __GFP_WAIT); | |
2220 | sg = st->sgl; | |
2221 | st->nents = 0; | |
2222 | for (i = 0; i < page_count; i++) { | |
2223 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
2224 | if (IS_ERR(page)) { | |
2225 | i915_gem_shrink(dev_priv, | |
2226 | page_count, | |
2227 | I915_SHRINK_BOUND | | |
2228 | I915_SHRINK_UNBOUND | | |
2229 | I915_SHRINK_PURGEABLE); | |
2230 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
2231 | } | |
2232 | if (IS_ERR(page)) { | |
2233 | /* We've tried hard to allocate the memory by reaping | |
2234 | * our own buffer, now let the real VM do its job and | |
2235 | * go down in flames if truly OOM. | |
2236 | */ | |
2237 | i915_gem_shrink_all(dev_priv); | |
2238 | page = shmem_read_mapping_page(mapping, i); | |
2239 | if (IS_ERR(page)) { | |
2240 | ret = PTR_ERR(page); | |
2241 | goto err_pages; | |
2242 | } | |
2243 | } | |
2244 | #ifdef CONFIG_SWIOTLB | |
2245 | if (swiotlb_nr_tbl()) { | |
2246 | st->nents++; | |
2247 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2248 | sg = sg_next(sg); | |
2249 | continue; | |
2250 | } | |
2251 | #endif | |
2252 | if (!i || page_to_pfn(page) != last_pfn + 1) { | |
2253 | if (i) | |
2254 | sg = sg_next(sg); | |
2255 | st->nents++; | |
2256 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2257 | } else { | |
2258 | sg->length += PAGE_SIZE; | |
2259 | } | |
2260 | last_pfn = page_to_pfn(page); | |
2261 | ||
2262 | /* Check that the i965g/gm workaround works. */ | |
2263 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
2264 | } | |
2265 | #ifdef CONFIG_SWIOTLB | |
2266 | if (!swiotlb_nr_tbl()) | |
2267 | #endif | |
2268 | sg_mark_end(sg); | |
2269 | obj->pages = st; | |
2270 | ||
2271 | ret = i915_gem_gtt_prepare_object(obj); | |
2272 | if (ret) | |
2273 | goto err_pages; | |
2274 | ||
2275 | if (i915_gem_object_needs_bit17_swizzle(obj)) | |
2276 | i915_gem_object_do_bit_17_swizzle(obj); | |
2277 | ||
2278 | if (obj->tiling_mode != I915_TILING_NONE && | |
2279 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2280 | i915_gem_object_pin_pages(obj); | |
2281 | ||
2282 | return 0; | |
2283 | ||
2284 | err_pages: | |
2285 | sg_mark_end(sg); | |
2286 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2287 | page_cache_release(sg_page_iter_page(&sg_iter)); | |
2288 | sg_free_table(st); | |
2289 | kfree(st); | |
2290 | ||
2291 | /* shmemfs first checks if there is enough memory to allocate the page | |
2292 | * and reports ENOSPC should there be insufficient, along with the usual | |
2293 | * ENOMEM for a genuine allocation failure. | |
2294 | * | |
2295 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2296 | * space and so want to translate the error from shmemfs back to our | |
2297 | * usual understanding of ENOMEM. | |
2298 | */ | |
2299 | if (ret == -ENOSPC) | |
2300 | ret = -ENOMEM; | |
2301 | ||
2302 | return ret; | |
2303 | } | |
2304 | ||
2305 | /* Ensure that the associated pages are gathered from the backing storage | |
2306 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
2307 | * multiple times before they are released by a single call to | |
2308 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
2309 | * either as a result of memory pressure (reaping pages under the shrinker) | |
2310 | * or as the object is itself released. | |
2311 | */ | |
2312 | int | |
2313 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2314 | { | |
2315 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2316 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2317 | int ret; | |
2318 | ||
2319 | if (obj->pages) | |
2320 | return 0; | |
2321 | ||
2322 | if (obj->madv != I915_MADV_WILLNEED) { | |
2323 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); | |
2324 | return -EFAULT; | |
2325 | } | |
2326 | ||
2327 | BUG_ON(obj->pages_pin_count); | |
2328 | ||
2329 | ret = ops->get_pages(obj); | |
2330 | if (ret) | |
2331 | return ret; | |
2332 | ||
2333 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); | |
2334 | ||
2335 | obj->get_page.sg = obj->pages->sgl; | |
2336 | obj->get_page.last = 0; | |
2337 | ||
2338 | return 0; | |
2339 | } | |
2340 | ||
2341 | void i915_vma_move_to_active(struct i915_vma *vma, | |
2342 | struct drm_i915_gem_request *req) | |
2343 | { | |
2344 | struct drm_i915_gem_object *obj = vma->obj; | |
2345 | struct intel_engine_cs *ring; | |
2346 | ||
2347 | ring = i915_gem_request_get_ring(req); | |
2348 | ||
2349 | /* Add a reference if we're newly entering the active list. */ | |
2350 | if (obj->active == 0) | |
2351 | drm_gem_object_reference(&obj->base); | |
2352 | obj->active |= intel_ring_flag(ring); | |
2353 | ||
2354 | list_move_tail(&obj->ring_list[ring->id], &ring->active_list); | |
2355 | i915_gem_request_assign(&obj->last_read_req[ring->id], req); | |
2356 | ||
2357 | list_move_tail(&vma->mm_list, &vma->vm->active_list); | |
2358 | } | |
2359 | ||
2360 | static void | |
2361 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj) | |
2362 | { | |
2363 | RQ_BUG_ON(obj->last_write_req == NULL); | |
2364 | RQ_BUG_ON(!(obj->active & intel_ring_flag(obj->last_write_req->ring))); | |
2365 | ||
2366 | i915_gem_request_assign(&obj->last_write_req, NULL); | |
2367 | intel_fb_obj_flush(obj, true, ORIGIN_CS); | |
2368 | } | |
2369 | ||
2370 | static void | |
2371 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring) | |
2372 | { | |
2373 | struct i915_vma *vma; | |
2374 | ||
2375 | RQ_BUG_ON(obj->last_read_req[ring] == NULL); | |
2376 | RQ_BUG_ON(!(obj->active & (1 << ring))); | |
2377 | ||
2378 | list_del_init(&obj->ring_list[ring]); | |
2379 | i915_gem_request_assign(&obj->last_read_req[ring], NULL); | |
2380 | ||
2381 | if (obj->last_write_req && obj->last_write_req->ring->id == ring) | |
2382 | i915_gem_object_retire__write(obj); | |
2383 | ||
2384 | obj->active &= ~(1 << ring); | |
2385 | if (obj->active) | |
2386 | return; | |
2387 | ||
2388 | /* Bump our place on the bound list to keep it roughly in LRU order | |
2389 | * so that we don't steal from recently used but inactive objects | |
2390 | * (unless we are forced to ofc!) | |
2391 | */ | |
2392 | list_move_tail(&obj->global_list, | |
2393 | &to_i915(obj->base.dev)->mm.bound_list); | |
2394 | ||
2395 | list_for_each_entry(vma, &obj->vma_list, vma_link) { | |
2396 | if (!list_empty(&vma->mm_list)) | |
2397 | list_move_tail(&vma->mm_list, &vma->vm->inactive_list); | |
2398 | } | |
2399 | ||
2400 | i915_gem_request_assign(&obj->last_fenced_req, NULL); | |
2401 | drm_gem_object_unreference(&obj->base); | |
2402 | } | |
2403 | ||
2404 | static int | |
2405 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) | |
2406 | { | |
2407 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2408 | struct intel_engine_cs *ring; | |
2409 | int ret, i, j; | |
2410 | ||
2411 | /* Carefully retire all requests without writing to the rings */ | |
2412 | for_each_ring(ring, dev_priv, i) { | |
2413 | ret = intel_ring_idle(ring); | |
2414 | if (ret) | |
2415 | return ret; | |
2416 | } | |
2417 | i915_gem_retire_requests(dev); | |
2418 | ||
2419 | /* Finally reset hw state */ | |
2420 | for_each_ring(ring, dev_priv, i) { | |
2421 | intel_ring_init_seqno(ring, seqno); | |
2422 | ||
2423 | for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++) | |
2424 | ring->semaphore.sync_seqno[j] = 0; | |
2425 | } | |
2426 | ||
2427 | return 0; | |
2428 | } | |
2429 | ||
2430 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) | |
2431 | { | |
2432 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2433 | int ret; | |
2434 | ||
2435 | if (seqno == 0) | |
2436 | return -EINVAL; | |
2437 | ||
2438 | /* HWS page needs to be set less than what we | |
2439 | * will inject to ring | |
2440 | */ | |
2441 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
2442 | if (ret) | |
2443 | return ret; | |
2444 | ||
2445 | /* Carefully set the last_seqno value so that wrap | |
2446 | * detection still works | |
2447 | */ | |
2448 | dev_priv->next_seqno = seqno; | |
2449 | dev_priv->last_seqno = seqno - 1; | |
2450 | if (dev_priv->last_seqno == 0) | |
2451 | dev_priv->last_seqno--; | |
2452 | ||
2453 | return 0; | |
2454 | } | |
2455 | ||
2456 | int | |
2457 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
2458 | { | |
2459 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2460 | ||
2461 | /* reserve 0 for non-seqno */ | |
2462 | if (dev_priv->next_seqno == 0) { | |
2463 | int ret = i915_gem_init_seqno(dev, 0); | |
2464 | if (ret) | |
2465 | return ret; | |
2466 | ||
2467 | dev_priv->next_seqno = 1; | |
2468 | } | |
2469 | ||
2470 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; | |
2471 | return 0; | |
2472 | } | |
2473 | ||
2474 | /* | |
2475 | * NB: This function is not allowed to fail. Doing so would mean the the | |
2476 | * request is not being tracked for completion but the work itself is | |
2477 | * going to happen on the hardware. This would be a Bad Thing(tm). | |
2478 | */ | |
2479 | void __i915_add_request(struct drm_i915_gem_request *request, | |
2480 | struct drm_i915_gem_object *obj, | |
2481 | bool flush_caches) | |
2482 | { | |
2483 | struct intel_engine_cs *ring; | |
2484 | struct drm_i915_private *dev_priv; | |
2485 | struct intel_ringbuffer *ringbuf; | |
2486 | u32 request_start; | |
2487 | int ret; | |
2488 | ||
2489 | if (WARN_ON(request == NULL)) | |
2490 | return; | |
2491 | ||
2492 | ring = request->ring; | |
2493 | dev_priv = ring->dev->dev_private; | |
2494 | ringbuf = request->ringbuf; | |
2495 | ||
2496 | /* | |
2497 | * To ensure that this call will not fail, space for its emissions | |
2498 | * should already have been reserved in the ring buffer. Let the ring | |
2499 | * know that it is time to use that space up. | |
2500 | */ | |
2501 | intel_ring_reserved_space_use(ringbuf); | |
2502 | ||
2503 | request_start = intel_ring_get_tail(ringbuf); | |
2504 | /* | |
2505 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2506 | * after having emitted the batchbuffer command. Hence we need to fix | |
2507 | * things up similar to emitting the lazy request. The difference here | |
2508 | * is that the flush _must_ happen before the next request, no matter | |
2509 | * what. | |
2510 | */ | |
2511 | if (flush_caches) { | |
2512 | if (i915.enable_execlists) | |
2513 | ret = logical_ring_flush_all_caches(request); | |
2514 | else | |
2515 | ret = intel_ring_flush_all_caches(request); | |
2516 | /* Not allowed to fail! */ | |
2517 | WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret); | |
2518 | } | |
2519 | ||
2520 | /* Record the position of the start of the request so that | |
2521 | * should we detect the updated seqno part-way through the | |
2522 | * GPU processing the request, we never over-estimate the | |
2523 | * position of the head. | |
2524 | */ | |
2525 | request->postfix = intel_ring_get_tail(ringbuf); | |
2526 | ||
2527 | if (i915.enable_execlists) | |
2528 | ret = ring->emit_request(request); | |
2529 | else { | |
2530 | ret = ring->add_request(request); | |
2531 | ||
2532 | request->tail = intel_ring_get_tail(ringbuf); | |
2533 | } | |
2534 | /* Not allowed to fail! */ | |
2535 | WARN(ret, "emit|add_request failed: %d!\n", ret); | |
2536 | ||
2537 | request->head = request_start; | |
2538 | ||
2539 | /* Whilst this request exists, batch_obj will be on the | |
2540 | * active_list, and so will hold the active reference. Only when this | |
2541 | * request is retired will the the batch_obj be moved onto the | |
2542 | * inactive_list and lose its active reference. Hence we do not need | |
2543 | * to explicitly hold another reference here. | |
2544 | */ | |
2545 | request->batch_obj = obj; | |
2546 | ||
2547 | request->emitted_jiffies = jiffies; | |
2548 | ring->last_submitted_seqno = request->seqno; | |
2549 | list_add_tail(&request->list, &ring->request_list); | |
2550 | ||
2551 | trace_i915_gem_request_add(request); | |
2552 | ||
2553 | i915_queue_hangcheck(ring->dev); | |
2554 | ||
2555 | queue_delayed_work(dev_priv->wq, | |
2556 | &dev_priv->mm.retire_work, | |
2557 | round_jiffies_up_relative(HZ)); | |
2558 | intel_mark_busy(dev_priv->dev); | |
2559 | ||
2560 | /* Sanity check that the reserved size was large enough. */ | |
2561 | intel_ring_reserved_space_end(ringbuf); | |
2562 | } | |
2563 | ||
2564 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, | |
2565 | const struct intel_context *ctx) | |
2566 | { | |
2567 | unsigned long elapsed; | |
2568 | ||
2569 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; | |
2570 | ||
2571 | if (ctx->hang_stats.banned) | |
2572 | return true; | |
2573 | ||
2574 | if (ctx->hang_stats.ban_period_seconds && | |
2575 | elapsed <= ctx->hang_stats.ban_period_seconds) { | |
2576 | if (!i915_gem_context_is_default(ctx)) { | |
2577 | DRM_DEBUG("context hanging too fast, banning!\n"); | |
2578 | return true; | |
2579 | } else if (i915_stop_ring_allow_ban(dev_priv)) { | |
2580 | if (i915_stop_ring_allow_warn(dev_priv)) | |
2581 | DRM_ERROR("gpu hanging too fast, banning!\n"); | |
2582 | return true; | |
2583 | } | |
2584 | } | |
2585 | ||
2586 | return false; | |
2587 | } | |
2588 | ||
2589 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, | |
2590 | struct intel_context *ctx, | |
2591 | const bool guilty) | |
2592 | { | |
2593 | struct i915_ctx_hang_stats *hs; | |
2594 | ||
2595 | if (WARN_ON(!ctx)) | |
2596 | return; | |
2597 | ||
2598 | hs = &ctx->hang_stats; | |
2599 | ||
2600 | if (guilty) { | |
2601 | hs->banned = i915_context_is_banned(dev_priv, ctx); | |
2602 | hs->batch_active++; | |
2603 | hs->guilty_ts = get_seconds(); | |
2604 | } else { | |
2605 | hs->batch_pending++; | |
2606 | } | |
2607 | } | |
2608 | ||
2609 | void i915_gem_request_free(struct kref *req_ref) | |
2610 | { | |
2611 | struct drm_i915_gem_request *req = container_of(req_ref, | |
2612 | typeof(*req), ref); | |
2613 | struct intel_context *ctx = req->ctx; | |
2614 | ||
2615 | if (req->file_priv) | |
2616 | i915_gem_request_remove_from_client(req); | |
2617 | ||
2618 | if (ctx) { | |
2619 | if (i915.enable_execlists) { | |
2620 | if (ctx != req->ring->default_context) | |
2621 | intel_lr_context_unpin(req); | |
2622 | } | |
2623 | ||
2624 | i915_gem_context_unreference(ctx); | |
2625 | } | |
2626 | ||
2627 | kmem_cache_free(req->i915->requests, req); | |
2628 | } | |
2629 | ||
2630 | int i915_gem_request_alloc(struct intel_engine_cs *ring, | |
2631 | struct intel_context *ctx, | |
2632 | struct drm_i915_gem_request **req_out) | |
2633 | { | |
2634 | struct drm_i915_private *dev_priv = to_i915(ring->dev); | |
2635 | struct drm_i915_gem_request *req; | |
2636 | int ret; | |
2637 | ||
2638 | if (!req_out) | |
2639 | return -EINVAL; | |
2640 | ||
2641 | *req_out = NULL; | |
2642 | ||
2643 | req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL); | |
2644 | if (req == NULL) | |
2645 | return -ENOMEM; | |
2646 | ||
2647 | ret = i915_gem_get_seqno(ring->dev, &req->seqno); | |
2648 | if (ret) | |
2649 | goto err; | |
2650 | ||
2651 | kref_init(&req->ref); | |
2652 | req->i915 = dev_priv; | |
2653 | req->ring = ring; | |
2654 | req->ctx = ctx; | |
2655 | i915_gem_context_reference(req->ctx); | |
2656 | ||
2657 | if (i915.enable_execlists) | |
2658 | ret = intel_logical_ring_alloc_request_extras(req); | |
2659 | else | |
2660 | ret = intel_ring_alloc_request_extras(req); | |
2661 | if (ret) { | |
2662 | i915_gem_context_unreference(req->ctx); | |
2663 | goto err; | |
2664 | } | |
2665 | ||
2666 | /* | |
2667 | * Reserve space in the ring buffer for all the commands required to | |
2668 | * eventually emit this request. This is to guarantee that the | |
2669 | * i915_add_request() call can't fail. Note that the reserve may need | |
2670 | * to be redone if the request is not actually submitted straight | |
2671 | * away, e.g. because a GPU scheduler has deferred it. | |
2672 | */ | |
2673 | if (i915.enable_execlists) | |
2674 | ret = intel_logical_ring_reserve_space(req); | |
2675 | else | |
2676 | ret = intel_ring_reserve_space(req); | |
2677 | if (ret) { | |
2678 | /* | |
2679 | * At this point, the request is fully allocated even if not | |
2680 | * fully prepared. Thus it can be cleaned up using the proper | |
2681 | * free code. | |
2682 | */ | |
2683 | i915_gem_request_cancel(req); | |
2684 | return ret; | |
2685 | } | |
2686 | ||
2687 | *req_out = req; | |
2688 | return 0; | |
2689 | ||
2690 | err: | |
2691 | kmem_cache_free(dev_priv->requests, req); | |
2692 | return ret; | |
2693 | } | |
2694 | ||
2695 | void i915_gem_request_cancel(struct drm_i915_gem_request *req) | |
2696 | { | |
2697 | intel_ring_reserved_space_cancel(req->ringbuf); | |
2698 | ||
2699 | i915_gem_request_unreference(req); | |
2700 | } | |
2701 | ||
2702 | struct drm_i915_gem_request * | |
2703 | i915_gem_find_active_request(struct intel_engine_cs *ring) | |
2704 | { | |
2705 | struct drm_i915_gem_request *request; | |
2706 | ||
2707 | list_for_each_entry(request, &ring->request_list, list) { | |
2708 | if (i915_gem_request_completed(request, false)) | |
2709 | continue; | |
2710 | ||
2711 | return request; | |
2712 | } | |
2713 | ||
2714 | return NULL; | |
2715 | } | |
2716 | ||
2717 | static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, | |
2718 | struct intel_engine_cs *ring) | |
2719 | { | |
2720 | struct drm_i915_gem_request *request; | |
2721 | bool ring_hung; | |
2722 | ||
2723 | request = i915_gem_find_active_request(ring); | |
2724 | ||
2725 | if (request == NULL) | |
2726 | return; | |
2727 | ||
2728 | ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; | |
2729 | ||
2730 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); | |
2731 | ||
2732 | list_for_each_entry_continue(request, &ring->request_list, list) | |
2733 | i915_set_reset_status(dev_priv, request->ctx, false); | |
2734 | } | |
2735 | ||
2736 | static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, | |
2737 | struct intel_engine_cs *ring) | |
2738 | { | |
2739 | while (!list_empty(&ring->active_list)) { | |
2740 | struct drm_i915_gem_object *obj; | |
2741 | ||
2742 | obj = list_first_entry(&ring->active_list, | |
2743 | struct drm_i915_gem_object, | |
2744 | ring_list[ring->id]); | |
2745 | ||
2746 | i915_gem_object_retire__read(obj, ring->id); | |
2747 | } | |
2748 | ||
2749 | /* | |
2750 | * Clear the execlists queue up before freeing the requests, as those | |
2751 | * are the ones that keep the context and ringbuffer backing objects | |
2752 | * pinned in place. | |
2753 | */ | |
2754 | while (!list_empty(&ring->execlist_queue)) { | |
2755 | struct drm_i915_gem_request *submit_req; | |
2756 | ||
2757 | submit_req = list_first_entry(&ring->execlist_queue, | |
2758 | struct drm_i915_gem_request, | |
2759 | execlist_link); | |
2760 | list_del(&submit_req->execlist_link); | |
2761 | ||
2762 | if (submit_req->ctx != ring->default_context) | |
2763 | intel_lr_context_unpin(submit_req); | |
2764 | ||
2765 | i915_gem_request_unreference(submit_req); | |
2766 | } | |
2767 | ||
2768 | /* | |
2769 | * We must free the requests after all the corresponding objects have | |
2770 | * been moved off active lists. Which is the same order as the normal | |
2771 | * retire_requests function does. This is important if object hold | |
2772 | * implicit references on things like e.g. ppgtt address spaces through | |
2773 | * the request. | |
2774 | */ | |
2775 | while (!list_empty(&ring->request_list)) { | |
2776 | struct drm_i915_gem_request *request; | |
2777 | ||
2778 | request = list_first_entry(&ring->request_list, | |
2779 | struct drm_i915_gem_request, | |
2780 | list); | |
2781 | ||
2782 | i915_gem_request_retire(request); | |
2783 | } | |
2784 | } | |
2785 | ||
2786 | void i915_gem_reset(struct drm_device *dev) | |
2787 | { | |
2788 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2789 | struct intel_engine_cs *ring; | |
2790 | int i; | |
2791 | ||
2792 | /* | |
2793 | * Before we free the objects from the requests, we need to inspect | |
2794 | * them for finding the guilty party. As the requests only borrow | |
2795 | * their reference to the objects, the inspection must be done first. | |
2796 | */ | |
2797 | for_each_ring(ring, dev_priv, i) | |
2798 | i915_gem_reset_ring_status(dev_priv, ring); | |
2799 | ||
2800 | for_each_ring(ring, dev_priv, i) | |
2801 | i915_gem_reset_ring_cleanup(dev_priv, ring); | |
2802 | ||
2803 | i915_gem_context_reset(dev); | |
2804 | ||
2805 | i915_gem_restore_fences(dev); | |
2806 | ||
2807 | WARN_ON(i915_verify_lists(dev)); | |
2808 | } | |
2809 | ||
2810 | /** | |
2811 | * This function clears the request list as sequence numbers are passed. | |
2812 | */ | |
2813 | void | |
2814 | i915_gem_retire_requests_ring(struct intel_engine_cs *ring) | |
2815 | { | |
2816 | WARN_ON(i915_verify_lists(ring->dev)); | |
2817 | ||
2818 | /* Retire requests first as we use it above for the early return. | |
2819 | * If we retire requests last, we may use a later seqno and so clear | |
2820 | * the requests lists without clearing the active list, leading to | |
2821 | * confusion. | |
2822 | */ | |
2823 | while (!list_empty(&ring->request_list)) { | |
2824 | struct drm_i915_gem_request *request; | |
2825 | ||
2826 | request = list_first_entry(&ring->request_list, | |
2827 | struct drm_i915_gem_request, | |
2828 | list); | |
2829 | ||
2830 | if (!i915_gem_request_completed(request, true)) | |
2831 | break; | |
2832 | ||
2833 | i915_gem_request_retire(request); | |
2834 | } | |
2835 | ||
2836 | /* Move any buffers on the active list that are no longer referenced | |
2837 | * by the ringbuffer to the flushing/inactive lists as appropriate, | |
2838 | * before we free the context associated with the requests. | |
2839 | */ | |
2840 | while (!list_empty(&ring->active_list)) { | |
2841 | struct drm_i915_gem_object *obj; | |
2842 | ||
2843 | obj = list_first_entry(&ring->active_list, | |
2844 | struct drm_i915_gem_object, | |
2845 | ring_list[ring->id]); | |
2846 | ||
2847 | if (!list_empty(&obj->last_read_req[ring->id]->list)) | |
2848 | break; | |
2849 | ||
2850 | i915_gem_object_retire__read(obj, ring->id); | |
2851 | } | |
2852 | ||
2853 | if (unlikely(ring->trace_irq_req && | |
2854 | i915_gem_request_completed(ring->trace_irq_req, true))) { | |
2855 | ring->irq_put(ring); | |
2856 | i915_gem_request_assign(&ring->trace_irq_req, NULL); | |
2857 | } | |
2858 | ||
2859 | WARN_ON(i915_verify_lists(ring->dev)); | |
2860 | } | |
2861 | ||
2862 | bool | |
2863 | i915_gem_retire_requests(struct drm_device *dev) | |
2864 | { | |
2865 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2866 | struct intel_engine_cs *ring; | |
2867 | bool idle = true; | |
2868 | int i; | |
2869 | ||
2870 | for_each_ring(ring, dev_priv, i) { | |
2871 | i915_gem_retire_requests_ring(ring); | |
2872 | idle &= list_empty(&ring->request_list); | |
2873 | if (i915.enable_execlists) { | |
2874 | unsigned long flags; | |
2875 | ||
2876 | spin_lock_irqsave(&ring->execlist_lock, flags); | |
2877 | idle &= list_empty(&ring->execlist_queue); | |
2878 | spin_unlock_irqrestore(&ring->execlist_lock, flags); | |
2879 | ||
2880 | intel_execlists_retire_requests(ring); | |
2881 | } | |
2882 | } | |
2883 | ||
2884 | if (idle) | |
2885 | mod_delayed_work(dev_priv->wq, | |
2886 | &dev_priv->mm.idle_work, | |
2887 | msecs_to_jiffies(100)); | |
2888 | ||
2889 | return idle; | |
2890 | } | |
2891 | ||
2892 | static void | |
2893 | i915_gem_retire_work_handler(struct work_struct *work) | |
2894 | { | |
2895 | struct drm_i915_private *dev_priv = | |
2896 | container_of(work, typeof(*dev_priv), mm.retire_work.work); | |
2897 | struct drm_device *dev = dev_priv->dev; | |
2898 | bool idle; | |
2899 | ||
2900 | /* Come back later if the device is busy... */ | |
2901 | idle = false; | |
2902 | if (mutex_trylock(&dev->struct_mutex)) { | |
2903 | idle = i915_gem_retire_requests(dev); | |
2904 | mutex_unlock(&dev->struct_mutex); | |
2905 | } | |
2906 | if (!idle) | |
2907 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, | |
2908 | round_jiffies_up_relative(HZ)); | |
2909 | } | |
2910 | ||
2911 | static void | |
2912 | i915_gem_idle_work_handler(struct work_struct *work) | |
2913 | { | |
2914 | struct drm_i915_private *dev_priv = | |
2915 | container_of(work, typeof(*dev_priv), mm.idle_work.work); | |
2916 | struct drm_device *dev = dev_priv->dev; | |
2917 | struct intel_engine_cs *ring; | |
2918 | int i; | |
2919 | ||
2920 | for_each_ring(ring, dev_priv, i) | |
2921 | if (!list_empty(&ring->request_list)) | |
2922 | return; | |
2923 | ||
2924 | intel_mark_idle(dev); | |
2925 | ||
2926 | if (mutex_trylock(&dev->struct_mutex)) { | |
2927 | struct intel_engine_cs *ring; | |
2928 | int i; | |
2929 | ||
2930 | for_each_ring(ring, dev_priv, i) | |
2931 | i915_gem_batch_pool_fini(&ring->batch_pool); | |
2932 | ||
2933 | mutex_unlock(&dev->struct_mutex); | |
2934 | } | |
2935 | } | |
2936 | ||
2937 | /** | |
2938 | * Ensures that an object will eventually get non-busy by flushing any required | |
2939 | * write domains, emitting any outstanding lazy request and retiring and | |
2940 | * completed requests. | |
2941 | */ | |
2942 | static int | |
2943 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2944 | { | |
2945 | int i; | |
2946 | ||
2947 | if (!obj->active) | |
2948 | return 0; | |
2949 | ||
2950 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
2951 | struct drm_i915_gem_request *req; | |
2952 | ||
2953 | req = obj->last_read_req[i]; | |
2954 | if (req == NULL) | |
2955 | continue; | |
2956 | ||
2957 | if (list_empty(&req->list)) | |
2958 | goto retire; | |
2959 | ||
2960 | if (i915_gem_request_completed(req, true)) { | |
2961 | __i915_gem_request_retire__upto(req); | |
2962 | retire: | |
2963 | i915_gem_object_retire__read(obj, i); | |
2964 | } | |
2965 | } | |
2966 | ||
2967 | return 0; | |
2968 | } | |
2969 | ||
2970 | /** | |
2971 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2972 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2973 | * | |
2974 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2975 | * the timeout parameter. | |
2976 | * -ETIME: object is still busy after timeout | |
2977 | * -ERESTARTSYS: signal interrupted the wait | |
2978 | * -ENONENT: object doesn't exist | |
2979 | * Also possible, but rare: | |
2980 | * -EAGAIN: GPU wedged | |
2981 | * -ENOMEM: damn | |
2982 | * -ENODEV: Internal IRQ fail | |
2983 | * -E?: The add request failed | |
2984 | * | |
2985 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2986 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2987 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2988 | * without holding struct_mutex the object may become re-busied before this | |
2989 | * function completes. A similar but shorter * race condition exists in the busy | |
2990 | * ioctl | |
2991 | */ | |
2992 | int | |
2993 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2994 | { | |
2995 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2996 | struct drm_i915_gem_wait *args = data; | |
2997 | struct drm_i915_gem_object *obj; | |
2998 | struct drm_i915_gem_request *req[I915_NUM_RINGS]; | |
2999 | unsigned reset_counter; | |
3000 | int i, n = 0; | |
3001 | int ret; | |
3002 | ||
3003 | if (args->flags != 0) | |
3004 | return -EINVAL; | |
3005 | ||
3006 | ret = i915_mutex_lock_interruptible(dev); | |
3007 | if (ret) | |
3008 | return ret; | |
3009 | ||
3010 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
3011 | if (&obj->base == NULL) { | |
3012 | mutex_unlock(&dev->struct_mutex); | |
3013 | return -ENOENT; | |
3014 | } | |
3015 | ||
3016 | /* Need to make sure the object gets inactive eventually. */ | |
3017 | ret = i915_gem_object_flush_active(obj); | |
3018 | if (ret) | |
3019 | goto out; | |
3020 | ||
3021 | if (!obj->active) | |
3022 | goto out; | |
3023 | ||
3024 | /* Do this after OLR check to make sure we make forward progress polling | |
3025 | * on this IOCTL with a timeout == 0 (like busy ioctl) | |
3026 | */ | |
3027 | if (args->timeout_ns == 0) { | |
3028 | ret = -ETIME; | |
3029 | goto out; | |
3030 | } | |
3031 | ||
3032 | drm_gem_object_unreference(&obj->base); | |
3033 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); | |
3034 | ||
3035 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
3036 | if (obj->last_read_req[i] == NULL) | |
3037 | continue; | |
3038 | ||
3039 | req[n++] = i915_gem_request_reference(obj->last_read_req[i]); | |
3040 | } | |
3041 | ||
3042 | mutex_unlock(&dev->struct_mutex); | |
3043 | ||
3044 | for (i = 0; i < n; i++) { | |
3045 | if (ret == 0) | |
3046 | ret = __i915_wait_request(req[i], reset_counter, true, | |
3047 | args->timeout_ns > 0 ? &args->timeout_ns : NULL, | |
3048 | file->driver_priv); | |
3049 | i915_gem_request_unreference__unlocked(req[i]); | |
3050 | } | |
3051 | return ret; | |
3052 | ||
3053 | out: | |
3054 | drm_gem_object_unreference(&obj->base); | |
3055 | mutex_unlock(&dev->struct_mutex); | |
3056 | return ret; | |
3057 | } | |
3058 | ||
3059 | static int | |
3060 | __i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
3061 | struct intel_engine_cs *to, | |
3062 | struct drm_i915_gem_request *from_req, | |
3063 | struct drm_i915_gem_request **to_req) | |
3064 | { | |
3065 | struct intel_engine_cs *from; | |
3066 | int ret; | |
3067 | ||
3068 | from = i915_gem_request_get_ring(from_req); | |
3069 | if (to == from) | |
3070 | return 0; | |
3071 | ||
3072 | if (i915_gem_request_completed(from_req, true)) | |
3073 | return 0; | |
3074 | ||
3075 | if (!i915_semaphore_is_enabled(obj->base.dev)) { | |
3076 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
3077 | ret = __i915_wait_request(from_req, | |
3078 | atomic_read(&i915->gpu_error.reset_counter), | |
3079 | i915->mm.interruptible, | |
3080 | NULL, | |
3081 | &i915->rps.semaphores); | |
3082 | if (ret) | |
3083 | return ret; | |
3084 | ||
3085 | i915_gem_object_retire_request(obj, from_req); | |
3086 | } else { | |
3087 | int idx = intel_ring_sync_index(from, to); | |
3088 | u32 seqno = i915_gem_request_get_seqno(from_req); | |
3089 | ||
3090 | WARN_ON(!to_req); | |
3091 | ||
3092 | if (seqno <= from->semaphore.sync_seqno[idx]) | |
3093 | return 0; | |
3094 | ||
3095 | if (*to_req == NULL) { | |
3096 | ret = i915_gem_request_alloc(to, to->default_context, to_req); | |
3097 | if (ret) | |
3098 | return ret; | |
3099 | } | |
3100 | ||
3101 | trace_i915_gem_ring_sync_to(*to_req, from, from_req); | |
3102 | ret = to->semaphore.sync_to(*to_req, from, seqno); | |
3103 | if (ret) | |
3104 | return ret; | |
3105 | ||
3106 | /* We use last_read_req because sync_to() | |
3107 | * might have just caused seqno wrap under | |
3108 | * the radar. | |
3109 | */ | |
3110 | from->semaphore.sync_seqno[idx] = | |
3111 | i915_gem_request_get_seqno(obj->last_read_req[from->id]); | |
3112 | } | |
3113 | ||
3114 | return 0; | |
3115 | } | |
3116 | ||
3117 | /** | |
3118 | * i915_gem_object_sync - sync an object to a ring. | |
3119 | * | |
3120 | * @obj: object which may be in use on another ring. | |
3121 | * @to: ring we wish to use the object on. May be NULL. | |
3122 | * @to_req: request we wish to use the object for. See below. | |
3123 | * This will be allocated and returned if a request is | |
3124 | * required but not passed in. | |
3125 | * | |
3126 | * This code is meant to abstract object synchronization with the GPU. | |
3127 | * Calling with NULL implies synchronizing the object with the CPU | |
3128 | * rather than a particular GPU ring. Conceptually we serialise writes | |
3129 | * between engines inside the GPU. We only allow one engine to write | |
3130 | * into a buffer at any time, but multiple readers. To ensure each has | |
3131 | * a coherent view of memory, we must: | |
3132 | * | |
3133 | * - If there is an outstanding write request to the object, the new | |
3134 | * request must wait for it to complete (either CPU or in hw, requests | |
3135 | * on the same ring will be naturally ordered). | |
3136 | * | |
3137 | * - If we are a write request (pending_write_domain is set), the new | |
3138 | * request must wait for outstanding read requests to complete. | |
3139 | * | |
3140 | * For CPU synchronisation (NULL to) no request is required. For syncing with | |
3141 | * rings to_req must be non-NULL. However, a request does not have to be | |
3142 | * pre-allocated. If *to_req is NULL and sync commands will be emitted then a | |
3143 | * request will be allocated automatically and returned through *to_req. Note | |
3144 | * that it is not guaranteed that commands will be emitted (because the system | |
3145 | * might already be idle). Hence there is no need to create a request that | |
3146 | * might never have any work submitted. Note further that if a request is | |
3147 | * returned in *to_req, it is the responsibility of the caller to submit | |
3148 | * that request (after potentially adding more work to it). | |
3149 | * | |
3150 | * Returns 0 if successful, else propagates up the lower layer error. | |
3151 | */ | |
3152 | int | |
3153 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
3154 | struct intel_engine_cs *to, | |
3155 | struct drm_i915_gem_request **to_req) | |
3156 | { | |
3157 | const bool readonly = obj->base.pending_write_domain == 0; | |
3158 | struct drm_i915_gem_request *req[I915_NUM_RINGS]; | |
3159 | int ret, i, n; | |
3160 | ||
3161 | if (!obj->active) | |
3162 | return 0; | |
3163 | ||
3164 | if (to == NULL) | |
3165 | return i915_gem_object_wait_rendering(obj, readonly); | |
3166 | ||
3167 | n = 0; | |
3168 | if (readonly) { | |
3169 | if (obj->last_write_req) | |
3170 | req[n++] = obj->last_write_req; | |
3171 | } else { | |
3172 | for (i = 0; i < I915_NUM_RINGS; i++) | |
3173 | if (obj->last_read_req[i]) | |
3174 | req[n++] = obj->last_read_req[i]; | |
3175 | } | |
3176 | for (i = 0; i < n; i++) { | |
3177 | ret = __i915_gem_object_sync(obj, to, req[i], to_req); | |
3178 | if (ret) | |
3179 | return ret; | |
3180 | } | |
3181 | ||
3182 | return 0; | |
3183 | } | |
3184 | ||
3185 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) | |
3186 | { | |
3187 | u32 old_write_domain, old_read_domains; | |
3188 | ||
3189 | /* Force a pagefault for domain tracking on next user access */ | |
3190 | i915_gem_release_mmap(obj); | |
3191 | ||
3192 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3193 | return; | |
3194 | ||
3195 | /* Wait for any direct GTT access to complete */ | |
3196 | mb(); | |
3197 | ||
3198 | old_read_domains = obj->base.read_domains; | |
3199 | old_write_domain = obj->base.write_domain; | |
3200 | ||
3201 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
3202 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
3203 | ||
3204 | trace_i915_gem_object_change_domain(obj, | |
3205 | old_read_domains, | |
3206 | old_write_domain); | |
3207 | } | |
3208 | ||
3209 | int i915_vma_unbind(struct i915_vma *vma) | |
3210 | { | |
3211 | struct drm_i915_gem_object *obj = vma->obj; | |
3212 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
3213 | int ret; | |
3214 | ||
3215 | if (list_empty(&vma->vma_link)) | |
3216 | return 0; | |
3217 | ||
3218 | if (!drm_mm_node_allocated(&vma->node)) { | |
3219 | i915_gem_vma_destroy(vma); | |
3220 | return 0; | |
3221 | } | |
3222 | ||
3223 | if (vma->pin_count) | |
3224 | return -EBUSY; | |
3225 | ||
3226 | BUG_ON(obj->pages == NULL); | |
3227 | ||
3228 | ret = i915_gem_object_wait_rendering(obj, false); | |
3229 | if (ret) | |
3230 | return ret; | |
3231 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
3232 | * should be safe and we need to cleanup or else we might | |
3233 | * cause memory corruption through use-after-free. | |
3234 | */ | |
3235 | ||
3236 | if (i915_is_ggtt(vma->vm) && | |
3237 | vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { | |
3238 | i915_gem_object_finish_gtt(obj); | |
3239 | ||
3240 | /* release the fence reg _after_ flushing */ | |
3241 | ret = i915_gem_object_put_fence(obj); | |
3242 | if (ret) | |
3243 | return ret; | |
3244 | } | |
3245 | ||
3246 | trace_i915_vma_unbind(vma); | |
3247 | ||
3248 | vma->vm->unbind_vma(vma); | |
3249 | vma->bound = 0; | |
3250 | ||
3251 | list_del_init(&vma->mm_list); | |
3252 | if (i915_is_ggtt(vma->vm)) { | |
3253 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { | |
3254 | obj->map_and_fenceable = false; | |
3255 | } else if (vma->ggtt_view.pages) { | |
3256 | sg_free_table(vma->ggtt_view.pages); | |
3257 | kfree(vma->ggtt_view.pages); | |
3258 | } | |
3259 | vma->ggtt_view.pages = NULL; | |
3260 | } | |
3261 | ||
3262 | drm_mm_remove_node(&vma->node); | |
3263 | i915_gem_vma_destroy(vma); | |
3264 | ||
3265 | /* Since the unbound list is global, only move to that list if | |
3266 | * no more VMAs exist. */ | |
3267 | if (list_empty(&obj->vma_list)) | |
3268 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); | |
3269 | ||
3270 | /* And finally now the object is completely decoupled from this vma, | |
3271 | * we can drop its hold on the backing storage and allow it to be | |
3272 | * reaped by the shrinker. | |
3273 | */ | |
3274 | i915_gem_object_unpin_pages(obj); | |
3275 | ||
3276 | return 0; | |
3277 | } | |
3278 | ||
3279 | int i915_gpu_idle(struct drm_device *dev) | |
3280 | { | |
3281 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3282 | struct intel_engine_cs *ring; | |
3283 | int ret, i; | |
3284 | ||
3285 | /* Flush everything onto the inactive list. */ | |
3286 | for_each_ring(ring, dev_priv, i) { | |
3287 | if (!i915.enable_execlists) { | |
3288 | struct drm_i915_gem_request *req; | |
3289 | ||
3290 | ret = i915_gem_request_alloc(ring, ring->default_context, &req); | |
3291 | if (ret) | |
3292 | return ret; | |
3293 | ||
3294 | ret = i915_switch_context(req); | |
3295 | if (ret) { | |
3296 | i915_gem_request_cancel(req); | |
3297 | return ret; | |
3298 | } | |
3299 | ||
3300 | i915_add_request_no_flush(req); | |
3301 | } | |
3302 | ||
3303 | ret = intel_ring_idle(ring); | |
3304 | if (ret) | |
3305 | return ret; | |
3306 | } | |
3307 | ||
3308 | WARN_ON(i915_verify_lists(dev)); | |
3309 | return 0; | |
3310 | } | |
3311 | ||
3312 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, | |
3313 | unsigned long cache_level) | |
3314 | { | |
3315 | struct drm_mm_node *gtt_space = &vma->node; | |
3316 | struct drm_mm_node *other; | |
3317 | ||
3318 | /* | |
3319 | * On some machines we have to be careful when putting differing types | |
3320 | * of snoopable memory together to avoid the prefetcher crossing memory | |
3321 | * domains and dying. During vm initialisation, we decide whether or not | |
3322 | * these constraints apply and set the drm_mm.color_adjust | |
3323 | * appropriately. | |
3324 | */ | |
3325 | if (vma->vm->mm.color_adjust == NULL) | |
3326 | return true; | |
3327 | ||
3328 | if (!drm_mm_node_allocated(gtt_space)) | |
3329 | return true; | |
3330 | ||
3331 | if (list_empty(>t_space->node_list)) | |
3332 | return true; | |
3333 | ||
3334 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3335 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3336 | return false; | |
3337 | ||
3338 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3339 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3340 | return false; | |
3341 | ||
3342 | return true; | |
3343 | } | |
3344 | ||
3345 | /** | |
3346 | * Finds free space in the GTT aperture and binds the object or a view of it | |
3347 | * there. | |
3348 | */ | |
3349 | static struct i915_vma * | |
3350 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, | |
3351 | struct i915_address_space *vm, | |
3352 | const struct i915_ggtt_view *ggtt_view, | |
3353 | unsigned alignment, | |
3354 | uint64_t flags) | |
3355 | { | |
3356 | struct drm_device *dev = obj->base.dev; | |
3357 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3358 | u32 size, fence_size, fence_alignment, unfenced_alignment; | |
3359 | u64 start = | |
3360 | flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; | |
3361 | u64 end = | |
3362 | flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total; | |
3363 | struct i915_vma *vma; | |
3364 | int ret; | |
3365 | ||
3366 | if (i915_is_ggtt(vm)) { | |
3367 | u32 view_size; | |
3368 | ||
3369 | if (WARN_ON(!ggtt_view)) | |
3370 | return ERR_PTR(-EINVAL); | |
3371 | ||
3372 | view_size = i915_ggtt_view_size(obj, ggtt_view); | |
3373 | ||
3374 | fence_size = i915_gem_get_gtt_size(dev, | |
3375 | view_size, | |
3376 | obj->tiling_mode); | |
3377 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3378 | view_size, | |
3379 | obj->tiling_mode, | |
3380 | true); | |
3381 | unfenced_alignment = i915_gem_get_gtt_alignment(dev, | |
3382 | view_size, | |
3383 | obj->tiling_mode, | |
3384 | false); | |
3385 | size = flags & PIN_MAPPABLE ? fence_size : view_size; | |
3386 | } else { | |
3387 | fence_size = i915_gem_get_gtt_size(dev, | |
3388 | obj->base.size, | |
3389 | obj->tiling_mode); | |
3390 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3391 | obj->base.size, | |
3392 | obj->tiling_mode, | |
3393 | true); | |
3394 | unfenced_alignment = | |
3395 | i915_gem_get_gtt_alignment(dev, | |
3396 | obj->base.size, | |
3397 | obj->tiling_mode, | |
3398 | false); | |
3399 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; | |
3400 | } | |
3401 | ||
3402 | if (alignment == 0) | |
3403 | alignment = flags & PIN_MAPPABLE ? fence_alignment : | |
3404 | unfenced_alignment; | |
3405 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { | |
3406 | DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n", | |
3407 | ggtt_view ? ggtt_view->type : 0, | |
3408 | alignment); | |
3409 | return ERR_PTR(-EINVAL); | |
3410 | } | |
3411 | ||
3412 | /* If binding the object/GGTT view requires more space than the entire | |
3413 | * aperture has, reject it early before evicting everything in a vain | |
3414 | * attempt to find space. | |
3415 | */ | |
3416 | if (size > end) { | |
3417 | DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%u > %s aperture=%llu\n", | |
3418 | ggtt_view ? ggtt_view->type : 0, | |
3419 | size, | |
3420 | flags & PIN_MAPPABLE ? "mappable" : "total", | |
3421 | end); | |
3422 | return ERR_PTR(-E2BIG); | |
3423 | } | |
3424 | ||
3425 | ret = i915_gem_object_get_pages(obj); | |
3426 | if (ret) | |
3427 | return ERR_PTR(ret); | |
3428 | ||
3429 | i915_gem_object_pin_pages(obj); | |
3430 | ||
3431 | vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) : | |
3432 | i915_gem_obj_lookup_or_create_vma(obj, vm); | |
3433 | ||
3434 | if (IS_ERR(vma)) | |
3435 | goto err_unpin; | |
3436 | ||
3437 | search_free: | |
3438 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, | |
3439 | size, alignment, | |
3440 | obj->cache_level, | |
3441 | start, end, | |
3442 | DRM_MM_SEARCH_DEFAULT, | |
3443 | DRM_MM_CREATE_DEFAULT); | |
3444 | if (ret) { | |
3445 | ret = i915_gem_evict_something(dev, vm, size, alignment, | |
3446 | obj->cache_level, | |
3447 | start, end, | |
3448 | flags); | |
3449 | if (ret == 0) | |
3450 | goto search_free; | |
3451 | ||
3452 | goto err_free_vma; | |
3453 | } | |
3454 | if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) { | |
3455 | ret = -EINVAL; | |
3456 | goto err_remove_node; | |
3457 | } | |
3458 | ||
3459 | trace_i915_vma_bind(vma, flags); | |
3460 | ret = i915_vma_bind(vma, obj->cache_level, flags); | |
3461 | if (ret) | |
3462 | goto err_remove_node; | |
3463 | ||
3464 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); | |
3465 | list_add_tail(&vma->mm_list, &vm->inactive_list); | |
3466 | ||
3467 | return vma; | |
3468 | ||
3469 | err_remove_node: | |
3470 | drm_mm_remove_node(&vma->node); | |
3471 | err_free_vma: | |
3472 | i915_gem_vma_destroy(vma); | |
3473 | vma = ERR_PTR(ret); | |
3474 | err_unpin: | |
3475 | i915_gem_object_unpin_pages(obj); | |
3476 | return vma; | |
3477 | } | |
3478 | ||
3479 | bool | |
3480 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, | |
3481 | bool force) | |
3482 | { | |
3483 | /* If we don't have a page list set up, then we're not pinned | |
3484 | * to GPU, and we can ignore the cache flush because it'll happen | |
3485 | * again at bind time. | |
3486 | */ | |
3487 | if (obj->pages == NULL) | |
3488 | return false; | |
3489 | ||
3490 | /* | |
3491 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3492 | * marked as wc by the system, or the system is cache-coherent. | |
3493 | */ | |
3494 | if (obj->stolen || obj->phys_handle) | |
3495 | return false; | |
3496 | ||
3497 | /* If the GPU is snooping the contents of the CPU cache, | |
3498 | * we do not need to manually clear the CPU cache lines. However, | |
3499 | * the caches are only snooped when the render cache is | |
3500 | * flushed/invalidated. As we always have to emit invalidations | |
3501 | * and flushes when moving into and out of the RENDER domain, correct | |
3502 | * snooping behaviour occurs naturally as the result of our domain | |
3503 | * tracking. | |
3504 | */ | |
3505 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { | |
3506 | obj->cache_dirty = true; | |
3507 | return false; | |
3508 | } | |
3509 | ||
3510 | trace_i915_gem_object_clflush(obj); | |
3511 | drm_clflush_sg(obj->pages); | |
3512 | obj->cache_dirty = false; | |
3513 | ||
3514 | return true; | |
3515 | } | |
3516 | ||
3517 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3518 | static void | |
3519 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) | |
3520 | { | |
3521 | uint32_t old_write_domain; | |
3522 | ||
3523 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) | |
3524 | return; | |
3525 | ||
3526 | /* No actual flushing is required for the GTT write domain. Writes | |
3527 | * to it immediately go to main memory as far as we know, so there's | |
3528 | * no chipset flush. It also doesn't land in render cache. | |
3529 | * | |
3530 | * However, we do have to enforce the order so that all writes through | |
3531 | * the GTT land before any writes to the device, such as updates to | |
3532 | * the GATT itself. | |
3533 | */ | |
3534 | wmb(); | |
3535 | ||
3536 | old_write_domain = obj->base.write_domain; | |
3537 | obj->base.write_domain = 0; | |
3538 | ||
3539 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); | |
3540 | ||
3541 | trace_i915_gem_object_change_domain(obj, | |
3542 | obj->base.read_domains, | |
3543 | old_write_domain); | |
3544 | } | |
3545 | ||
3546 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3547 | static void | |
3548 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) | |
3549 | { | |
3550 | uint32_t old_write_domain; | |
3551 | ||
3552 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) | |
3553 | return; | |
3554 | ||
3555 | if (i915_gem_clflush_object(obj, obj->pin_display)) | |
3556 | i915_gem_chipset_flush(obj->base.dev); | |
3557 | ||
3558 | old_write_domain = obj->base.write_domain; | |
3559 | obj->base.write_domain = 0; | |
3560 | ||
3561 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); | |
3562 | ||
3563 | trace_i915_gem_object_change_domain(obj, | |
3564 | obj->base.read_domains, | |
3565 | old_write_domain); | |
3566 | } | |
3567 | ||
3568 | /** | |
3569 | * Moves a single object to the GTT read, and possibly write domain. | |
3570 | * | |
3571 | * This function returns when the move is complete, including waiting on | |
3572 | * flushes to occur. | |
3573 | */ | |
3574 | int | |
3575 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) | |
3576 | { | |
3577 | uint32_t old_write_domain, old_read_domains; | |
3578 | struct i915_vma *vma; | |
3579 | int ret; | |
3580 | ||
3581 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) | |
3582 | return 0; | |
3583 | ||
3584 | ret = i915_gem_object_wait_rendering(obj, !write); | |
3585 | if (ret) | |
3586 | return ret; | |
3587 | ||
3588 | /* Flush and acquire obj->pages so that we are coherent through | |
3589 | * direct access in memory with previous cached writes through | |
3590 | * shmemfs and that our cache domain tracking remains valid. | |
3591 | * For example, if the obj->filp was moved to swap without us | |
3592 | * being notified and releasing the pages, we would mistakenly | |
3593 | * continue to assume that the obj remained out of the CPU cached | |
3594 | * domain. | |
3595 | */ | |
3596 | ret = i915_gem_object_get_pages(obj); | |
3597 | if (ret) | |
3598 | return ret; | |
3599 | ||
3600 | i915_gem_object_flush_cpu_write_domain(obj); | |
3601 | ||
3602 | /* Serialise direct access to this object with the barriers for | |
3603 | * coherent writes from the GPU, by effectively invalidating the | |
3604 | * GTT domain upon first access. | |
3605 | */ | |
3606 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3607 | mb(); | |
3608 | ||
3609 | old_write_domain = obj->base.write_domain; | |
3610 | old_read_domains = obj->base.read_domains; | |
3611 | ||
3612 | /* It should now be out of any other write domains, and we can update | |
3613 | * the domain values for our changes. | |
3614 | */ | |
3615 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
3616 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
3617 | if (write) { | |
3618 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; | |
3619 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3620 | obj->dirty = 1; | |
3621 | } | |
3622 | ||
3623 | trace_i915_gem_object_change_domain(obj, | |
3624 | old_read_domains, | |
3625 | old_write_domain); | |
3626 | ||
3627 | /* And bump the LRU for this access */ | |
3628 | vma = i915_gem_obj_to_ggtt(obj); | |
3629 | if (vma && drm_mm_node_allocated(&vma->node) && !obj->active) | |
3630 | list_move_tail(&vma->mm_list, | |
3631 | &to_i915(obj->base.dev)->gtt.base.inactive_list); | |
3632 | ||
3633 | return 0; | |
3634 | } | |
3635 | ||
3636 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, | |
3637 | enum i915_cache_level cache_level) | |
3638 | { | |
3639 | struct drm_device *dev = obj->base.dev; | |
3640 | struct i915_vma *vma, *next; | |
3641 | int ret; | |
3642 | ||
3643 | if (obj->cache_level == cache_level) | |
3644 | return 0; | |
3645 | ||
3646 | if (i915_gem_obj_is_pinned(obj)) { | |
3647 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3648 | return -EBUSY; | |
3649 | } | |
3650 | ||
3651 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { | |
3652 | if (!i915_gem_valid_gtt_space(vma, cache_level)) { | |
3653 | ret = i915_vma_unbind(vma); | |
3654 | if (ret) | |
3655 | return ret; | |
3656 | } | |
3657 | } | |
3658 | ||
3659 | if (i915_gem_obj_bound_any(obj)) { | |
3660 | ret = i915_gem_object_wait_rendering(obj, false); | |
3661 | if (ret) | |
3662 | return ret; | |
3663 | ||
3664 | i915_gem_object_finish_gtt(obj); | |
3665 | ||
3666 | /* Before SandyBridge, you could not use tiling or fence | |
3667 | * registers with snooped memory, so relinquish any fences | |
3668 | * currently pointing to our region in the aperture. | |
3669 | */ | |
3670 | if (INTEL_INFO(dev)->gen < 6) { | |
3671 | ret = i915_gem_object_put_fence(obj); | |
3672 | if (ret) | |
3673 | return ret; | |
3674 | } | |
3675 | ||
3676 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
3677 | if (drm_mm_node_allocated(&vma->node)) { | |
3678 | ret = i915_vma_bind(vma, cache_level, | |
3679 | PIN_UPDATE); | |
3680 | if (ret) | |
3681 | return ret; | |
3682 | } | |
3683 | } | |
3684 | ||
3685 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
3686 | vma->node.color = cache_level; | |
3687 | obj->cache_level = cache_level; | |
3688 | ||
3689 | if (obj->cache_dirty && | |
3690 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
3691 | cpu_write_needs_clflush(obj)) { | |
3692 | if (i915_gem_clflush_object(obj, true)) | |
3693 | i915_gem_chipset_flush(obj->base.dev); | |
3694 | } | |
3695 | ||
3696 | return 0; | |
3697 | } | |
3698 | ||
3699 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, | |
3700 | struct drm_file *file) | |
3701 | { | |
3702 | struct drm_i915_gem_caching *args = data; | |
3703 | struct drm_i915_gem_object *obj; | |
3704 | ||
3705 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3706 | if (&obj->base == NULL) | |
3707 | return -ENOENT; | |
3708 | ||
3709 | switch (obj->cache_level) { | |
3710 | case I915_CACHE_LLC: | |
3711 | case I915_CACHE_L3_LLC: | |
3712 | args->caching = I915_CACHING_CACHED; | |
3713 | break; | |
3714 | ||
3715 | case I915_CACHE_WT: | |
3716 | args->caching = I915_CACHING_DISPLAY; | |
3717 | break; | |
3718 | ||
3719 | default: | |
3720 | args->caching = I915_CACHING_NONE; | |
3721 | break; | |
3722 | } | |
3723 | ||
3724 | drm_gem_object_unreference_unlocked(&obj->base); | |
3725 | return 0; | |
3726 | } | |
3727 | ||
3728 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
3729 | struct drm_file *file) | |
3730 | { | |
3731 | struct drm_i915_gem_caching *args = data; | |
3732 | struct drm_i915_gem_object *obj; | |
3733 | enum i915_cache_level level; | |
3734 | int ret; | |
3735 | ||
3736 | switch (args->caching) { | |
3737 | case I915_CACHING_NONE: | |
3738 | level = I915_CACHE_NONE; | |
3739 | break; | |
3740 | case I915_CACHING_CACHED: | |
3741 | level = I915_CACHE_LLC; | |
3742 | break; | |
3743 | case I915_CACHING_DISPLAY: | |
3744 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3745 | break; | |
3746 | default: | |
3747 | return -EINVAL; | |
3748 | } | |
3749 | ||
3750 | ret = i915_mutex_lock_interruptible(dev); | |
3751 | if (ret) | |
3752 | return ret; | |
3753 | ||
3754 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3755 | if (&obj->base == NULL) { | |
3756 | ret = -ENOENT; | |
3757 | goto unlock; | |
3758 | } | |
3759 | ||
3760 | ret = i915_gem_object_set_cache_level(obj, level); | |
3761 | ||
3762 | drm_gem_object_unreference(&obj->base); | |
3763 | unlock: | |
3764 | mutex_unlock(&dev->struct_mutex); | |
3765 | return ret; | |
3766 | } | |
3767 | ||
3768 | /* | |
3769 | * Prepare buffer for display plane (scanout, cursors, etc). | |
3770 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3771 | * any flushes to be pipelined (for pageflips). | |
3772 | */ | |
3773 | int | |
3774 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, | |
3775 | u32 alignment, | |
3776 | struct intel_engine_cs *pipelined, | |
3777 | struct drm_i915_gem_request **pipelined_request, | |
3778 | const struct i915_ggtt_view *view) | |
3779 | { | |
3780 | u32 old_read_domains, old_write_domain; | |
3781 | int ret; | |
3782 | ||
3783 | ret = i915_gem_object_sync(obj, pipelined, pipelined_request); | |
3784 | if (ret) | |
3785 | return ret; | |
3786 | ||
3787 | /* Mark the pin_display early so that we account for the | |
3788 | * display coherency whilst setting up the cache domains. | |
3789 | */ | |
3790 | obj->pin_display++; | |
3791 | ||
3792 | /* The display engine is not coherent with the LLC cache on gen6. As | |
3793 | * a result, we make sure that the pinning that is about to occur is | |
3794 | * done with uncached PTEs. This is lowest common denominator for all | |
3795 | * chipsets. | |
3796 | * | |
3797 | * However for gen6+, we could do better by using the GFDT bit instead | |
3798 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3799 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3800 | */ | |
3801 | ret = i915_gem_object_set_cache_level(obj, | |
3802 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
3803 | if (ret) | |
3804 | goto err_unpin_display; | |
3805 | ||
3806 | /* As the user may map the buffer once pinned in the display plane | |
3807 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3808 | * always use map_and_fenceable for all scanout buffers. | |
3809 | */ | |
3810 | ret = i915_gem_object_ggtt_pin(obj, view, alignment, | |
3811 | view->type == I915_GGTT_VIEW_NORMAL ? | |
3812 | PIN_MAPPABLE : 0); | |
3813 | if (ret) | |
3814 | goto err_unpin_display; | |
3815 | ||
3816 | i915_gem_object_flush_cpu_write_domain(obj); | |
3817 | ||
3818 | old_write_domain = obj->base.write_domain; | |
3819 | old_read_domains = obj->base.read_domains; | |
3820 | ||
3821 | /* It should now be out of any other write domains, and we can update | |
3822 | * the domain values for our changes. | |
3823 | */ | |
3824 | obj->base.write_domain = 0; | |
3825 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
3826 | ||
3827 | trace_i915_gem_object_change_domain(obj, | |
3828 | old_read_domains, | |
3829 | old_write_domain); | |
3830 | ||
3831 | return 0; | |
3832 | ||
3833 | err_unpin_display: | |
3834 | obj->pin_display--; | |
3835 | return ret; | |
3836 | } | |
3837 | ||
3838 | void | |
3839 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, | |
3840 | const struct i915_ggtt_view *view) | |
3841 | { | |
3842 | if (WARN_ON(obj->pin_display == 0)) | |
3843 | return; | |
3844 | ||
3845 | i915_gem_object_ggtt_unpin_view(obj, view); | |
3846 | ||
3847 | obj->pin_display--; | |
3848 | } | |
3849 | ||
3850 | /** | |
3851 | * Moves a single object to the CPU read, and possibly write domain. | |
3852 | * | |
3853 | * This function returns when the move is complete, including waiting on | |
3854 | * flushes to occur. | |
3855 | */ | |
3856 | int | |
3857 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) | |
3858 | { | |
3859 | uint32_t old_write_domain, old_read_domains; | |
3860 | int ret; | |
3861 | ||
3862 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) | |
3863 | return 0; | |
3864 | ||
3865 | ret = i915_gem_object_wait_rendering(obj, !write); | |
3866 | if (ret) | |
3867 | return ret; | |
3868 | ||
3869 | i915_gem_object_flush_gtt_write_domain(obj); | |
3870 | ||
3871 | old_write_domain = obj->base.write_domain; | |
3872 | old_read_domains = obj->base.read_domains; | |
3873 | ||
3874 | /* Flush the CPU cache if it's still invalid. */ | |
3875 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { | |
3876 | i915_gem_clflush_object(obj, false); | |
3877 | ||
3878 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; | |
3879 | } | |
3880 | ||
3881 | /* It should now be out of any other write domains, and we can update | |
3882 | * the domain values for our changes. | |
3883 | */ | |
3884 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); | |
3885 | ||
3886 | /* If we're writing through the CPU, then the GPU read domains will | |
3887 | * need to be invalidated at next use. | |
3888 | */ | |
3889 | if (write) { | |
3890 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3891 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3892 | } | |
3893 | ||
3894 | trace_i915_gem_object_change_domain(obj, | |
3895 | old_read_domains, | |
3896 | old_write_domain); | |
3897 | ||
3898 | return 0; | |
3899 | } | |
3900 | ||
3901 | /* Throttle our rendering by waiting until the ring has completed our requests | |
3902 | * emitted over 20 msec ago. | |
3903 | * | |
3904 | * Note that if we were to use the current jiffies each time around the loop, | |
3905 | * we wouldn't escape the function with any frames outstanding if the time to | |
3906 | * render a frame was over 20ms. | |
3907 | * | |
3908 | * This should get us reasonable parallelism between CPU and GPU but also | |
3909 | * relatively low latency when blocking on a particular request to finish. | |
3910 | */ | |
3911 | static int | |
3912 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) | |
3913 | { | |
3914 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3915 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
3916 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; | |
3917 | struct drm_i915_gem_request *request, *target = NULL; | |
3918 | unsigned reset_counter; | |
3919 | int ret; | |
3920 | ||
3921 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); | |
3922 | if (ret) | |
3923 | return ret; | |
3924 | ||
3925 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
3926 | if (ret) | |
3927 | return ret; | |
3928 | ||
3929 | spin_lock(&file_priv->mm.lock); | |
3930 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { | |
3931 | if (time_after_eq(request->emitted_jiffies, recent_enough)) | |
3932 | break; | |
3933 | ||
3934 | /* | |
3935 | * Note that the request might not have been submitted yet. | |
3936 | * In which case emitted_jiffies will be zero. | |
3937 | */ | |
3938 | if (!request->emitted_jiffies) | |
3939 | continue; | |
3940 | ||
3941 | target = request; | |
3942 | } | |
3943 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); | |
3944 | if (target) | |
3945 | i915_gem_request_reference(target); | |
3946 | spin_unlock(&file_priv->mm.lock); | |
3947 | ||
3948 | if (target == NULL) | |
3949 | return 0; | |
3950 | ||
3951 | ret = __i915_wait_request(target, reset_counter, true, NULL, NULL); | |
3952 | if (ret == 0) | |
3953 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
3954 | ||
3955 | i915_gem_request_unreference__unlocked(target); | |
3956 | ||
3957 | return ret; | |
3958 | } | |
3959 | ||
3960 | static bool | |
3961 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) | |
3962 | { | |
3963 | struct drm_i915_gem_object *obj = vma->obj; | |
3964 | ||
3965 | if (alignment && | |
3966 | vma->node.start & (alignment - 1)) | |
3967 | return true; | |
3968 | ||
3969 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) | |
3970 | return true; | |
3971 | ||
3972 | if (flags & PIN_OFFSET_BIAS && | |
3973 | vma->node.start < (flags & PIN_OFFSET_MASK)) | |
3974 | return true; | |
3975 | ||
3976 | return false; | |
3977 | } | |
3978 | ||
3979 | static int | |
3980 | i915_gem_object_do_pin(struct drm_i915_gem_object *obj, | |
3981 | struct i915_address_space *vm, | |
3982 | const struct i915_ggtt_view *ggtt_view, | |
3983 | uint32_t alignment, | |
3984 | uint64_t flags) | |
3985 | { | |
3986 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
3987 | struct i915_vma *vma; | |
3988 | unsigned bound; | |
3989 | int ret; | |
3990 | ||
3991 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) | |
3992 | return -ENODEV; | |
3993 | ||
3994 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) | |
3995 | return -EINVAL; | |
3996 | ||
3997 | if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)) | |
3998 | return -EINVAL; | |
3999 | ||
4000 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) | |
4001 | return -EINVAL; | |
4002 | ||
4003 | vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) : | |
4004 | i915_gem_obj_to_vma(obj, vm); | |
4005 | ||
4006 | if (IS_ERR(vma)) | |
4007 | return PTR_ERR(vma); | |
4008 | ||
4009 | if (vma) { | |
4010 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) | |
4011 | return -EBUSY; | |
4012 | ||
4013 | if (i915_vma_misplaced(vma, alignment, flags)) { | |
4014 | unsigned long offset; | |
4015 | offset = ggtt_view ? i915_gem_obj_ggtt_offset_view(obj, ggtt_view) : | |
4016 | i915_gem_obj_offset(obj, vm); | |
4017 | WARN(vma->pin_count, | |
4018 | "bo is already pinned in %s with incorrect alignment:" | |
4019 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," | |
4020 | " obj->map_and_fenceable=%d\n", | |
4021 | ggtt_view ? "ggtt" : "ppgtt", | |
4022 | offset, | |
4023 | alignment, | |
4024 | !!(flags & PIN_MAPPABLE), | |
4025 | obj->map_and_fenceable); | |
4026 | ret = i915_vma_unbind(vma); | |
4027 | if (ret) | |
4028 | return ret; | |
4029 | ||
4030 | vma = NULL; | |
4031 | } | |
4032 | } | |
4033 | ||
4034 | bound = vma ? vma->bound : 0; | |
4035 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { | |
4036 | vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment, | |
4037 | flags); | |
4038 | if (IS_ERR(vma)) | |
4039 | return PTR_ERR(vma); | |
4040 | } else { | |
4041 | ret = i915_vma_bind(vma, obj->cache_level, flags); | |
4042 | if (ret) | |
4043 | return ret; | |
4044 | } | |
4045 | ||
4046 | if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL && | |
4047 | (bound ^ vma->bound) & GLOBAL_BIND) { | |
4048 | bool mappable, fenceable; | |
4049 | u32 fence_size, fence_alignment; | |
4050 | ||
4051 | fence_size = i915_gem_get_gtt_size(obj->base.dev, | |
4052 | obj->base.size, | |
4053 | obj->tiling_mode); | |
4054 | fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, | |
4055 | obj->base.size, | |
4056 | obj->tiling_mode, | |
4057 | true); | |
4058 | ||
4059 | fenceable = (vma->node.size == fence_size && | |
4060 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4061 | ||
4062 | mappable = (vma->node.start + fence_size <= | |
4063 | dev_priv->gtt.mappable_end); | |
4064 | ||
4065 | obj->map_and_fenceable = mappable && fenceable; | |
4066 | ||
4067 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); | |
4068 | } | |
4069 | ||
4070 | vma->pin_count++; | |
4071 | return 0; | |
4072 | } | |
4073 | ||
4074 | int | |
4075 | i915_gem_object_pin(struct drm_i915_gem_object *obj, | |
4076 | struct i915_address_space *vm, | |
4077 | uint32_t alignment, | |
4078 | uint64_t flags) | |
4079 | { | |
4080 | return i915_gem_object_do_pin(obj, vm, | |
4081 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL, | |
4082 | alignment, flags); | |
4083 | } | |
4084 | ||
4085 | int | |
4086 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, | |
4087 | const struct i915_ggtt_view *view, | |
4088 | uint32_t alignment, | |
4089 | uint64_t flags) | |
4090 | { | |
4091 | if (WARN_ONCE(!view, "no view specified")) | |
4092 | return -EINVAL; | |
4093 | ||
4094 | return i915_gem_object_do_pin(obj, i915_obj_to_ggtt(obj), view, | |
4095 | alignment, flags | PIN_GLOBAL); | |
4096 | } | |
4097 | ||
4098 | void | |
4099 | i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, | |
4100 | const struct i915_ggtt_view *view) | |
4101 | { | |
4102 | struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view); | |
4103 | ||
4104 | BUG_ON(!vma); | |
4105 | WARN_ON(vma->pin_count == 0); | |
4106 | WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view)); | |
4107 | ||
4108 | --vma->pin_count; | |
4109 | } | |
4110 | ||
4111 | int | |
4112 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
4113 | struct drm_file *file) | |
4114 | { | |
4115 | struct drm_i915_gem_busy *args = data; | |
4116 | struct drm_i915_gem_object *obj; | |
4117 | int ret; | |
4118 | ||
4119 | ret = i915_mutex_lock_interruptible(dev); | |
4120 | if (ret) | |
4121 | return ret; | |
4122 | ||
4123 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
4124 | if (&obj->base == NULL) { | |
4125 | ret = -ENOENT; | |
4126 | goto unlock; | |
4127 | } | |
4128 | ||
4129 | /* Count all active objects as busy, even if they are currently not used | |
4130 | * by the gpu. Users of this interface expect objects to eventually | |
4131 | * become non-busy without any further actions, therefore emit any | |
4132 | * necessary flushes here. | |
4133 | */ | |
4134 | ret = i915_gem_object_flush_active(obj); | |
4135 | if (ret) | |
4136 | goto unref; | |
4137 | ||
4138 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
4139 | args->busy = obj->active << 16; | |
4140 | if (obj->last_write_req) | |
4141 | args->busy |= obj->last_write_req->ring->id; | |
4142 | ||
4143 | unref: | |
4144 | drm_gem_object_unreference(&obj->base); | |
4145 | unlock: | |
4146 | mutex_unlock(&dev->struct_mutex); | |
4147 | return ret; | |
4148 | } | |
4149 | ||
4150 | int | |
4151 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4152 | struct drm_file *file_priv) | |
4153 | { | |
4154 | return i915_gem_ring_throttle(dev, file_priv); | |
4155 | } | |
4156 | ||
4157 | int | |
4158 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4159 | struct drm_file *file_priv) | |
4160 | { | |
4161 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4162 | struct drm_i915_gem_madvise *args = data; | |
4163 | struct drm_i915_gem_object *obj; | |
4164 | int ret; | |
4165 | ||
4166 | switch (args->madv) { | |
4167 | case I915_MADV_DONTNEED: | |
4168 | case I915_MADV_WILLNEED: | |
4169 | break; | |
4170 | default: | |
4171 | return -EINVAL; | |
4172 | } | |
4173 | ||
4174 | ret = i915_mutex_lock_interruptible(dev); | |
4175 | if (ret) | |
4176 | return ret; | |
4177 | ||
4178 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); | |
4179 | if (&obj->base == NULL) { | |
4180 | ret = -ENOENT; | |
4181 | goto unlock; | |
4182 | } | |
4183 | ||
4184 | if (i915_gem_obj_is_pinned(obj)) { | |
4185 | ret = -EINVAL; | |
4186 | goto out; | |
4187 | } | |
4188 | ||
4189 | if (obj->pages && | |
4190 | obj->tiling_mode != I915_TILING_NONE && | |
4191 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { | |
4192 | if (obj->madv == I915_MADV_WILLNEED) | |
4193 | i915_gem_object_unpin_pages(obj); | |
4194 | if (args->madv == I915_MADV_WILLNEED) | |
4195 | i915_gem_object_pin_pages(obj); | |
4196 | } | |
4197 | ||
4198 | if (obj->madv != __I915_MADV_PURGED) | |
4199 | obj->madv = args->madv; | |
4200 | ||
4201 | /* if the object is no longer attached, discard its backing storage */ | |
4202 | if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL) | |
4203 | i915_gem_object_truncate(obj); | |
4204 | ||
4205 | args->retained = obj->madv != __I915_MADV_PURGED; | |
4206 | ||
4207 | out: | |
4208 | drm_gem_object_unreference(&obj->base); | |
4209 | unlock: | |
4210 | mutex_unlock(&dev->struct_mutex); | |
4211 | return ret; | |
4212 | } | |
4213 | ||
4214 | void i915_gem_object_init(struct drm_i915_gem_object *obj, | |
4215 | const struct drm_i915_gem_object_ops *ops) | |
4216 | { | |
4217 | int i; | |
4218 | ||
4219 | INIT_LIST_HEAD(&obj->global_list); | |
4220 | for (i = 0; i < I915_NUM_RINGS; i++) | |
4221 | INIT_LIST_HEAD(&obj->ring_list[i]); | |
4222 | INIT_LIST_HEAD(&obj->obj_exec_link); | |
4223 | INIT_LIST_HEAD(&obj->vma_list); | |
4224 | INIT_LIST_HEAD(&obj->batch_pool_link); | |
4225 | ||
4226 | obj->ops = ops; | |
4227 | ||
4228 | obj->fence_reg = I915_FENCE_REG_NONE; | |
4229 | obj->madv = I915_MADV_WILLNEED; | |
4230 | ||
4231 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
4232 | } | |
4233 | ||
4234 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { | |
4235 | .get_pages = i915_gem_object_get_pages_gtt, | |
4236 | .put_pages = i915_gem_object_put_pages_gtt, | |
4237 | }; | |
4238 | ||
4239 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, | |
4240 | size_t size) | |
4241 | { | |
4242 | struct drm_i915_gem_object *obj; | |
4243 | struct address_space *mapping; | |
4244 | gfp_t mask; | |
4245 | ||
4246 | obj = i915_gem_object_alloc(dev); | |
4247 | if (obj == NULL) | |
4248 | return NULL; | |
4249 | ||
4250 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { | |
4251 | i915_gem_object_free(obj); | |
4252 | return NULL; | |
4253 | } | |
4254 | ||
4255 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; | |
4256 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4257 | /* 965gm cannot relocate objects above 4GiB. */ | |
4258 | mask &= ~__GFP_HIGHMEM; | |
4259 | mask |= __GFP_DMA32; | |
4260 | } | |
4261 | ||
4262 | mapping = file_inode(obj->base.filp)->i_mapping; | |
4263 | mapping_set_gfp_mask(mapping, mask); | |
4264 | ||
4265 | i915_gem_object_init(obj, &i915_gem_object_ops); | |
4266 | ||
4267 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
4268 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
4269 | ||
4270 | if (HAS_LLC(dev)) { | |
4271 | /* On some devices, we can have the GPU use the LLC (the CPU | |
4272 | * cache) for about a 10% performance improvement | |
4273 | * compared to uncached. Graphics requests other than | |
4274 | * display scanout are coherent with the CPU in | |
4275 | * accessing this cache. This means in this mode we | |
4276 | * don't need to clflush on the CPU side, and on the | |
4277 | * GPU side we only need to flush internal caches to | |
4278 | * get data visible to the CPU. | |
4279 | * | |
4280 | * However, we maintain the display planes as UC, and so | |
4281 | * need to rebind when first used as such. | |
4282 | */ | |
4283 | obj->cache_level = I915_CACHE_LLC; | |
4284 | } else | |
4285 | obj->cache_level = I915_CACHE_NONE; | |
4286 | ||
4287 | trace_i915_gem_object_create(obj); | |
4288 | ||
4289 | return obj; | |
4290 | } | |
4291 | ||
4292 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) | |
4293 | { | |
4294 | /* If we are the last user of the backing storage (be it shmemfs | |
4295 | * pages or stolen etc), we know that the pages are going to be | |
4296 | * immediately released. In this case, we can then skip copying | |
4297 | * back the contents from the GPU. | |
4298 | */ | |
4299 | ||
4300 | if (obj->madv != I915_MADV_WILLNEED) | |
4301 | return false; | |
4302 | ||
4303 | if (obj->base.filp == NULL) | |
4304 | return true; | |
4305 | ||
4306 | /* At first glance, this looks racy, but then again so would be | |
4307 | * userspace racing mmap against close. However, the first external | |
4308 | * reference to the filp can only be obtained through the | |
4309 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4310 | * acquiring such a reference whilst we are in the middle of | |
4311 | * freeing the object. | |
4312 | */ | |
4313 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4314 | } | |
4315 | ||
4316 | void i915_gem_free_object(struct drm_gem_object *gem_obj) | |
4317 | { | |
4318 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); | |
4319 | struct drm_device *dev = obj->base.dev; | |
4320 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4321 | struct i915_vma *vma, *next; | |
4322 | ||
4323 | intel_runtime_pm_get(dev_priv); | |
4324 | ||
4325 | trace_i915_gem_object_destroy(obj); | |
4326 | ||
4327 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { | |
4328 | int ret; | |
4329 | ||
4330 | vma->pin_count = 0; | |
4331 | ret = i915_vma_unbind(vma); | |
4332 | if (WARN_ON(ret == -ERESTARTSYS)) { | |
4333 | bool was_interruptible; | |
4334 | ||
4335 | was_interruptible = dev_priv->mm.interruptible; | |
4336 | dev_priv->mm.interruptible = false; | |
4337 | ||
4338 | WARN_ON(i915_vma_unbind(vma)); | |
4339 | ||
4340 | dev_priv->mm.interruptible = was_interruptible; | |
4341 | } | |
4342 | } | |
4343 | ||
4344 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up | |
4345 | * before progressing. */ | |
4346 | if (obj->stolen) | |
4347 | i915_gem_object_unpin_pages(obj); | |
4348 | ||
4349 | WARN_ON(obj->frontbuffer_bits); | |
4350 | ||
4351 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && | |
4352 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && | |
4353 | obj->tiling_mode != I915_TILING_NONE) | |
4354 | i915_gem_object_unpin_pages(obj); | |
4355 | ||
4356 | if (WARN_ON(obj->pages_pin_count)) | |
4357 | obj->pages_pin_count = 0; | |
4358 | if (discard_backing_storage(obj)) | |
4359 | obj->madv = I915_MADV_DONTNEED; | |
4360 | i915_gem_object_put_pages(obj); | |
4361 | i915_gem_object_free_mmap_offset(obj); | |
4362 | ||
4363 | BUG_ON(obj->pages); | |
4364 | ||
4365 | if (obj->base.import_attach) | |
4366 | drm_prime_gem_destroy(&obj->base, NULL); | |
4367 | ||
4368 | if (obj->ops->release) | |
4369 | obj->ops->release(obj); | |
4370 | ||
4371 | drm_gem_object_release(&obj->base); | |
4372 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
4373 | ||
4374 | kfree(obj->bit_17); | |
4375 | i915_gem_object_free(obj); | |
4376 | ||
4377 | intel_runtime_pm_put(dev_priv); | |
4378 | } | |
4379 | ||
4380 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, | |
4381 | struct i915_address_space *vm) | |
4382 | { | |
4383 | struct i915_vma *vma; | |
4384 | list_for_each_entry(vma, &obj->vma_list, vma_link) { | |
4385 | if (i915_is_ggtt(vma->vm) && | |
4386 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) | |
4387 | continue; | |
4388 | if (vma->vm == vm) | |
4389 | return vma; | |
4390 | } | |
4391 | return NULL; | |
4392 | } | |
4393 | ||
4394 | struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, | |
4395 | const struct i915_ggtt_view *view) | |
4396 | { | |
4397 | struct i915_address_space *ggtt = i915_obj_to_ggtt(obj); | |
4398 | struct i915_vma *vma; | |
4399 | ||
4400 | if (WARN_ONCE(!view, "no view specified")) | |
4401 | return ERR_PTR(-EINVAL); | |
4402 | ||
4403 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
4404 | if (vma->vm == ggtt && | |
4405 | i915_ggtt_view_equal(&vma->ggtt_view, view)) | |
4406 | return vma; | |
4407 | return NULL; | |
4408 | } | |
4409 | ||
4410 | void i915_gem_vma_destroy(struct i915_vma *vma) | |
4411 | { | |
4412 | struct i915_address_space *vm = NULL; | |
4413 | WARN_ON(vma->node.allocated); | |
4414 | ||
4415 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4416 | if (!list_empty(&vma->exec_list)) | |
4417 | return; | |
4418 | ||
4419 | vm = vma->vm; | |
4420 | ||
4421 | if (!i915_is_ggtt(vm)) | |
4422 | i915_ppgtt_put(i915_vm_to_ppgtt(vm)); | |
4423 | ||
4424 | list_del(&vma->vma_link); | |
4425 | ||
4426 | kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma); | |
4427 | } | |
4428 | ||
4429 | static void | |
4430 | i915_gem_stop_ringbuffers(struct drm_device *dev) | |
4431 | { | |
4432 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4433 | struct intel_engine_cs *ring; | |
4434 | int i; | |
4435 | ||
4436 | for_each_ring(ring, dev_priv, i) | |
4437 | dev_priv->gt.stop_ring(ring); | |
4438 | } | |
4439 | ||
4440 | int | |
4441 | i915_gem_suspend(struct drm_device *dev) | |
4442 | { | |
4443 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4444 | int ret = 0; | |
4445 | ||
4446 | mutex_lock(&dev->struct_mutex); | |
4447 | ret = i915_gpu_idle(dev); | |
4448 | if (ret) | |
4449 | goto err; | |
4450 | ||
4451 | i915_gem_retire_requests(dev); | |
4452 | ||
4453 | i915_gem_stop_ringbuffers(dev); | |
4454 | mutex_unlock(&dev->struct_mutex); | |
4455 | ||
4456 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); | |
4457 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
4458 | flush_delayed_work(&dev_priv->mm.idle_work); | |
4459 | ||
4460 | /* Assert that we sucessfully flushed all the work and | |
4461 | * reset the GPU back to its idle, low power state. | |
4462 | */ | |
4463 | WARN_ON(dev_priv->mm.busy); | |
4464 | ||
4465 | return 0; | |
4466 | ||
4467 | err: | |
4468 | mutex_unlock(&dev->struct_mutex); | |
4469 | return ret; | |
4470 | } | |
4471 | ||
4472 | int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice) | |
4473 | { | |
4474 | struct intel_engine_cs *ring = req->ring; | |
4475 | struct drm_device *dev = ring->dev; | |
4476 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4477 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); | |
4478 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; | |
4479 | int i, ret; | |
4480 | ||
4481 | if (!HAS_L3_DPF(dev) || !remap_info) | |
4482 | return 0; | |
4483 | ||
4484 | ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3); | |
4485 | if (ret) | |
4486 | return ret; | |
4487 | ||
4488 | /* | |
4489 | * Note: We do not worry about the concurrent register cacheline hang | |
4490 | * here because no other code should access these registers other than | |
4491 | * at initialization time. | |
4492 | */ | |
4493 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { | |
4494 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
4495 | intel_ring_emit(ring, reg_base + i); | |
4496 | intel_ring_emit(ring, remap_info[i/4]); | |
4497 | } | |
4498 | ||
4499 | intel_ring_advance(ring); | |
4500 | ||
4501 | return ret; | |
4502 | } | |
4503 | ||
4504 | void i915_gem_init_swizzling(struct drm_device *dev) | |
4505 | { | |
4506 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4507 | ||
4508 | if (INTEL_INFO(dev)->gen < 5 || | |
4509 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) | |
4510 | return; | |
4511 | ||
4512 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4513 | DISP_TILE_SURFACE_SWIZZLING); | |
4514 | ||
4515 | if (IS_GEN5(dev)) | |
4516 | return; | |
4517 | ||
4518 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); | |
4519 | if (IS_GEN6(dev)) | |
4520 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); | |
4521 | else if (IS_GEN7(dev)) | |
4522 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); | |
4523 | else if (IS_GEN8(dev)) | |
4524 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
4525 | else | |
4526 | BUG(); | |
4527 | } | |
4528 | ||
4529 | static bool | |
4530 | intel_enable_blt(struct drm_device *dev) | |
4531 | { | |
4532 | if (!HAS_BLT(dev)) | |
4533 | return false; | |
4534 | ||
4535 | /* The blitter was dysfunctional on early prototypes */ | |
4536 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
4537 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
4538 | " graphics performance will be degraded.\n"); | |
4539 | return false; | |
4540 | } | |
4541 | ||
4542 | return true; | |
4543 | } | |
4544 | ||
4545 | static void init_unused_ring(struct drm_device *dev, u32 base) | |
4546 | { | |
4547 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4548 | ||
4549 | I915_WRITE(RING_CTL(base), 0); | |
4550 | I915_WRITE(RING_HEAD(base), 0); | |
4551 | I915_WRITE(RING_TAIL(base), 0); | |
4552 | I915_WRITE(RING_START(base), 0); | |
4553 | } | |
4554 | ||
4555 | static void init_unused_rings(struct drm_device *dev) | |
4556 | { | |
4557 | if (IS_I830(dev)) { | |
4558 | init_unused_ring(dev, PRB1_BASE); | |
4559 | init_unused_ring(dev, SRB0_BASE); | |
4560 | init_unused_ring(dev, SRB1_BASE); | |
4561 | init_unused_ring(dev, SRB2_BASE); | |
4562 | init_unused_ring(dev, SRB3_BASE); | |
4563 | } else if (IS_GEN2(dev)) { | |
4564 | init_unused_ring(dev, SRB0_BASE); | |
4565 | init_unused_ring(dev, SRB1_BASE); | |
4566 | } else if (IS_GEN3(dev)) { | |
4567 | init_unused_ring(dev, PRB1_BASE); | |
4568 | init_unused_ring(dev, PRB2_BASE); | |
4569 | } | |
4570 | } | |
4571 | ||
4572 | int i915_gem_init_rings(struct drm_device *dev) | |
4573 | { | |
4574 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4575 | int ret; | |
4576 | ||
4577 | ret = intel_init_render_ring_buffer(dev); | |
4578 | if (ret) | |
4579 | return ret; | |
4580 | ||
4581 | if (HAS_BSD(dev)) { | |
4582 | ret = intel_init_bsd_ring_buffer(dev); | |
4583 | if (ret) | |
4584 | goto cleanup_render_ring; | |
4585 | } | |
4586 | ||
4587 | if (intel_enable_blt(dev)) { | |
4588 | ret = intel_init_blt_ring_buffer(dev); | |
4589 | if (ret) | |
4590 | goto cleanup_bsd_ring; | |
4591 | } | |
4592 | ||
4593 | if (HAS_VEBOX(dev)) { | |
4594 | ret = intel_init_vebox_ring_buffer(dev); | |
4595 | if (ret) | |
4596 | goto cleanup_blt_ring; | |
4597 | } | |
4598 | ||
4599 | if (HAS_BSD2(dev)) { | |
4600 | ret = intel_init_bsd2_ring_buffer(dev); | |
4601 | if (ret) | |
4602 | goto cleanup_vebox_ring; | |
4603 | } | |
4604 | ||
4605 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); | |
4606 | if (ret) | |
4607 | goto cleanup_bsd2_ring; | |
4608 | ||
4609 | return 0; | |
4610 | ||
4611 | cleanup_bsd2_ring: | |
4612 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]); | |
4613 | cleanup_vebox_ring: | |
4614 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); | |
4615 | cleanup_blt_ring: | |
4616 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
4617 | cleanup_bsd_ring: | |
4618 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
4619 | cleanup_render_ring: | |
4620 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
4621 | ||
4622 | return ret; | |
4623 | } | |
4624 | ||
4625 | int | |
4626 | i915_gem_init_hw(struct drm_device *dev) | |
4627 | { | |
4628 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4629 | struct intel_engine_cs *ring; | |
4630 | int ret, i, j; | |
4631 | ||
4632 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4633 | return -EIO; | |
4634 | ||
4635 | /* Double layer security blanket, see i915_gem_init() */ | |
4636 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4637 | ||
4638 | if (dev_priv->ellc_size) | |
4639 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); | |
4640 | ||
4641 | if (IS_HASWELL(dev)) | |
4642 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4643 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
4644 | ||
4645 | if (HAS_PCH_NOP(dev)) { | |
4646 | if (IS_IVYBRIDGE(dev)) { | |
4647 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4648 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4649 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4650 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4651 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4652 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4653 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4654 | } | |
4655 | } | |
4656 | ||
4657 | i915_gem_init_swizzling(dev); | |
4658 | ||
4659 | /* | |
4660 | * At least 830 can leave some of the unused rings | |
4661 | * "active" (ie. head != tail) after resume which | |
4662 | * will prevent c3 entry. Makes sure all unused rings | |
4663 | * are totally idle. | |
4664 | */ | |
4665 | init_unused_rings(dev); | |
4666 | ||
4667 | BUG_ON(!dev_priv->ring[RCS].default_context); | |
4668 | ||
4669 | ret = i915_ppgtt_init_hw(dev); | |
4670 | if (ret) { | |
4671 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); | |
4672 | goto out; | |
4673 | } | |
4674 | ||
4675 | /* Need to do basic initialisation of all rings first: */ | |
4676 | for_each_ring(ring, dev_priv, i) { | |
4677 | ret = ring->init_hw(ring); | |
4678 | if (ret) | |
4679 | goto out; | |
4680 | } | |
4681 | ||
4682 | /* Now it is safe to go back round and do everything else: */ | |
4683 | for_each_ring(ring, dev_priv, i) { | |
4684 | struct drm_i915_gem_request *req; | |
4685 | ||
4686 | WARN_ON(!ring->default_context); | |
4687 | ||
4688 | ret = i915_gem_request_alloc(ring, ring->default_context, &req); | |
4689 | if (ret) { | |
4690 | i915_gem_cleanup_ringbuffer(dev); | |
4691 | goto out; | |
4692 | } | |
4693 | ||
4694 | if (ring->id == RCS) { | |
4695 | for (j = 0; j < NUM_L3_SLICES(dev); j++) | |
4696 | i915_gem_l3_remap(req, j); | |
4697 | } | |
4698 | ||
4699 | ret = i915_ppgtt_init_ring(req); | |
4700 | if (ret && ret != -EIO) { | |
4701 | DRM_ERROR("PPGTT enable ring #%d failed %d\n", i, ret); | |
4702 | i915_gem_request_cancel(req); | |
4703 | i915_gem_cleanup_ringbuffer(dev); | |
4704 | goto out; | |
4705 | } | |
4706 | ||
4707 | ret = i915_gem_context_enable(req); | |
4708 | if (ret && ret != -EIO) { | |
4709 | DRM_ERROR("Context enable ring #%d failed %d\n", i, ret); | |
4710 | i915_gem_request_cancel(req); | |
4711 | i915_gem_cleanup_ringbuffer(dev); | |
4712 | goto out; | |
4713 | } | |
4714 | ||
4715 | i915_add_request_no_flush(req); | |
4716 | } | |
4717 | ||
4718 | out: | |
4719 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
4720 | return ret; | |
4721 | } | |
4722 | ||
4723 | int i915_gem_init(struct drm_device *dev) | |
4724 | { | |
4725 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4726 | int ret; | |
4727 | ||
4728 | i915.enable_execlists = intel_sanitize_enable_execlists(dev, | |
4729 | i915.enable_execlists); | |
4730 | ||
4731 | mutex_lock(&dev->struct_mutex); | |
4732 | ||
4733 | if (IS_VALLEYVIEW(dev)) { | |
4734 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
4735 | I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ); | |
4736 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & | |
4737 | VLV_GTLC_ALLOWWAKEACK), 10)) | |
4738 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); | |
4739 | } | |
4740 | ||
4741 | if (!i915.enable_execlists) { | |
4742 | dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission; | |
4743 | dev_priv->gt.init_rings = i915_gem_init_rings; | |
4744 | dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer; | |
4745 | dev_priv->gt.stop_ring = intel_stop_ring_buffer; | |
4746 | } else { | |
4747 | dev_priv->gt.execbuf_submit = intel_execlists_submission; | |
4748 | dev_priv->gt.init_rings = intel_logical_rings_init; | |
4749 | dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup; | |
4750 | dev_priv->gt.stop_ring = intel_logical_ring_stop; | |
4751 | } | |
4752 | ||
4753 | /* This is just a security blanket to placate dragons. | |
4754 | * On some systems, we very sporadically observe that the first TLBs | |
4755 | * used by the CS may be stale, despite us poking the TLB reset. If | |
4756 | * we hold the forcewake during initialisation these problems | |
4757 | * just magically go away. | |
4758 | */ | |
4759 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4760 | ||
4761 | ret = i915_gem_init_userptr(dev); | |
4762 | if (ret) | |
4763 | goto out_unlock; | |
4764 | ||
4765 | i915_gem_init_global_gtt(dev); | |
4766 | ||
4767 | ret = i915_gem_context_init(dev); | |
4768 | if (ret) | |
4769 | goto out_unlock; | |
4770 | ||
4771 | ret = dev_priv->gt.init_rings(dev); | |
4772 | if (ret) | |
4773 | goto out_unlock; | |
4774 | ||
4775 | ret = i915_gem_init_hw(dev); | |
4776 | if (ret == -EIO) { | |
4777 | /* Allow ring initialisation to fail by marking the GPU as | |
4778 | * wedged. But we only want to do this where the GPU is angry, | |
4779 | * for all other failure, such as an allocation failure, bail. | |
4780 | */ | |
4781 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
4782 | atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter); | |
4783 | ret = 0; | |
4784 | } | |
4785 | ||
4786 | out_unlock: | |
4787 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
4788 | mutex_unlock(&dev->struct_mutex); | |
4789 | ||
4790 | return ret; | |
4791 | } | |
4792 | ||
4793 | void | |
4794 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4795 | { | |
4796 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4797 | struct intel_engine_cs *ring; | |
4798 | int i; | |
4799 | ||
4800 | for_each_ring(ring, dev_priv, i) | |
4801 | dev_priv->gt.cleanup_ring(ring); | |
4802 | ||
4803 | if (i915.enable_execlists) | |
4804 | /* | |
4805 | * Neither the BIOS, ourselves or any other kernel | |
4806 | * expects the system to be in execlists mode on startup, | |
4807 | * so we need to reset the GPU back to legacy mode. | |
4808 | */ | |
4809 | intel_gpu_reset(dev); | |
4810 | } | |
4811 | ||
4812 | static void | |
4813 | init_ring_lists(struct intel_engine_cs *ring) | |
4814 | { | |
4815 | INIT_LIST_HEAD(&ring->active_list); | |
4816 | INIT_LIST_HEAD(&ring->request_list); | |
4817 | } | |
4818 | ||
4819 | void i915_init_vm(struct drm_i915_private *dev_priv, | |
4820 | struct i915_address_space *vm) | |
4821 | { | |
4822 | if (!i915_is_ggtt(vm)) | |
4823 | drm_mm_init(&vm->mm, vm->start, vm->total); | |
4824 | vm->dev = dev_priv->dev; | |
4825 | INIT_LIST_HEAD(&vm->active_list); | |
4826 | INIT_LIST_HEAD(&vm->inactive_list); | |
4827 | INIT_LIST_HEAD(&vm->global_link); | |
4828 | list_add_tail(&vm->global_link, &dev_priv->vm_list); | |
4829 | } | |
4830 | ||
4831 | void | |
4832 | i915_gem_load(struct drm_device *dev) | |
4833 | { | |
4834 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4835 | int i; | |
4836 | ||
4837 | dev_priv->objects = | |
4838 | kmem_cache_create("i915_gem_object", | |
4839 | sizeof(struct drm_i915_gem_object), 0, | |
4840 | SLAB_HWCACHE_ALIGN, | |
4841 | NULL); | |
4842 | dev_priv->vmas = | |
4843 | kmem_cache_create("i915_gem_vma", | |
4844 | sizeof(struct i915_vma), 0, | |
4845 | SLAB_HWCACHE_ALIGN, | |
4846 | NULL); | |
4847 | dev_priv->requests = | |
4848 | kmem_cache_create("i915_gem_request", | |
4849 | sizeof(struct drm_i915_gem_request), 0, | |
4850 | SLAB_HWCACHE_ALIGN, | |
4851 | NULL); | |
4852 | ||
4853 | INIT_LIST_HEAD(&dev_priv->vm_list); | |
4854 | i915_init_vm(dev_priv, &dev_priv->gtt.base); | |
4855 | ||
4856 | INIT_LIST_HEAD(&dev_priv->context_list); | |
4857 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); | |
4858 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
4859 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); | |
4860 | for (i = 0; i < I915_NUM_RINGS; i++) | |
4861 | init_ring_lists(&dev_priv->ring[i]); | |
4862 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) | |
4863 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
4864 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, | |
4865 | i915_gem_retire_work_handler); | |
4866 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, | |
4867 | i915_gem_idle_work_handler); | |
4868 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); | |
4869 | ||
4870 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; | |
4871 | ||
4872 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) | |
4873 | dev_priv->num_fence_regs = 32; | |
4874 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
4875 | dev_priv->num_fence_regs = 16; | |
4876 | else | |
4877 | dev_priv->num_fence_regs = 8; | |
4878 | ||
4879 | if (intel_vgpu_active(dev)) | |
4880 | dev_priv->num_fence_regs = | |
4881 | I915_READ(vgtif_reg(avail_rs.fence_num)); | |
4882 | ||
4883 | /* Initialize fence registers to zero */ | |
4884 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); | |
4885 | i915_gem_restore_fences(dev); | |
4886 | ||
4887 | i915_gem_detect_bit_6_swizzle(dev); | |
4888 | init_waitqueue_head(&dev_priv->pending_flip_queue); | |
4889 | ||
4890 | dev_priv->mm.interruptible = true; | |
4891 | ||
4892 | i915_gem_shrinker_init(dev_priv); | |
4893 | ||
4894 | mutex_init(&dev_priv->fb_tracking.lock); | |
4895 | } | |
4896 | ||
4897 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) | |
4898 | { | |
4899 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
4900 | ||
4901 | /* Clean up our request list when the client is going away, so that | |
4902 | * later retire_requests won't dereference our soon-to-be-gone | |
4903 | * file_priv. | |
4904 | */ | |
4905 | spin_lock(&file_priv->mm.lock); | |
4906 | while (!list_empty(&file_priv->mm.request_list)) { | |
4907 | struct drm_i915_gem_request *request; | |
4908 | ||
4909 | request = list_first_entry(&file_priv->mm.request_list, | |
4910 | struct drm_i915_gem_request, | |
4911 | client_list); | |
4912 | list_del(&request->client_list); | |
4913 | request->file_priv = NULL; | |
4914 | } | |
4915 | spin_unlock(&file_priv->mm.lock); | |
4916 | ||
4917 | if (!list_empty(&file_priv->rps.link)) { | |
4918 | spin_lock(&to_i915(dev)->rps.client_lock); | |
4919 | list_del(&file_priv->rps.link); | |
4920 | spin_unlock(&to_i915(dev)->rps.client_lock); | |
4921 | } | |
4922 | } | |
4923 | ||
4924 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
4925 | { | |
4926 | struct drm_i915_file_private *file_priv; | |
4927 | int ret; | |
4928 | ||
4929 | DRM_DEBUG_DRIVER("\n"); | |
4930 | ||
4931 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
4932 | if (!file_priv) | |
4933 | return -ENOMEM; | |
4934 | ||
4935 | file->driver_priv = file_priv; | |
4936 | file_priv->dev_priv = dev->dev_private; | |
4937 | file_priv->file = file; | |
4938 | INIT_LIST_HEAD(&file_priv->rps.link); | |
4939 | ||
4940 | spin_lock_init(&file_priv->mm.lock); | |
4941 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
4942 | ||
4943 | ret = i915_gem_context_open(dev, file); | |
4944 | if (ret) | |
4945 | kfree(file_priv); | |
4946 | ||
4947 | return ret; | |
4948 | } | |
4949 | ||
4950 | /** | |
4951 | * i915_gem_track_fb - update frontbuffer tracking | |
4952 | * old: current GEM buffer for the frontbuffer slots | |
4953 | * new: new GEM buffer for the frontbuffer slots | |
4954 | * frontbuffer_bits: bitmask of frontbuffer slots | |
4955 | * | |
4956 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
4957 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
4958 | */ | |
4959 | void i915_gem_track_fb(struct drm_i915_gem_object *old, | |
4960 | struct drm_i915_gem_object *new, | |
4961 | unsigned frontbuffer_bits) | |
4962 | { | |
4963 | if (old) { | |
4964 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); | |
4965 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); | |
4966 | old->frontbuffer_bits &= ~frontbuffer_bits; | |
4967 | } | |
4968 | ||
4969 | if (new) { | |
4970 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); | |
4971 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); | |
4972 | new->frontbuffer_bits |= frontbuffer_bits; | |
4973 | } | |
4974 | } | |
4975 | ||
4976 | /* All the new VM stuff */ | |
4977 | unsigned long | |
4978 | i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
4979 | struct i915_address_space *vm) | |
4980 | { | |
4981 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
4982 | struct i915_vma *vma; | |
4983 | ||
4984 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); | |
4985 | ||
4986 | list_for_each_entry(vma, &o->vma_list, vma_link) { | |
4987 | if (i915_is_ggtt(vma->vm) && | |
4988 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) | |
4989 | continue; | |
4990 | if (vma->vm == vm) | |
4991 | return vma->node.start; | |
4992 | } | |
4993 | ||
4994 | WARN(1, "%s vma for this object not found.\n", | |
4995 | i915_is_ggtt(vm) ? "global" : "ppgtt"); | |
4996 | return -1; | |
4997 | } | |
4998 | ||
4999 | unsigned long | |
5000 | i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, | |
5001 | const struct i915_ggtt_view *view) | |
5002 | { | |
5003 | struct i915_address_space *ggtt = i915_obj_to_ggtt(o); | |
5004 | struct i915_vma *vma; | |
5005 | ||
5006 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
5007 | if (vma->vm == ggtt && | |
5008 | i915_ggtt_view_equal(&vma->ggtt_view, view)) | |
5009 | return vma->node.start; | |
5010 | ||
5011 | WARN(1, "global vma for this object not found. (view=%u)\n", view->type); | |
5012 | return -1; | |
5013 | } | |
5014 | ||
5015 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
5016 | struct i915_address_space *vm) | |
5017 | { | |
5018 | struct i915_vma *vma; | |
5019 | ||
5020 | list_for_each_entry(vma, &o->vma_list, vma_link) { | |
5021 | if (i915_is_ggtt(vma->vm) && | |
5022 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) | |
5023 | continue; | |
5024 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) | |
5025 | return true; | |
5026 | } | |
5027 | ||
5028 | return false; | |
5029 | } | |
5030 | ||
5031 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, | |
5032 | const struct i915_ggtt_view *view) | |
5033 | { | |
5034 | struct i915_address_space *ggtt = i915_obj_to_ggtt(o); | |
5035 | struct i915_vma *vma; | |
5036 | ||
5037 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
5038 | if (vma->vm == ggtt && | |
5039 | i915_ggtt_view_equal(&vma->ggtt_view, view) && | |
5040 | drm_mm_node_allocated(&vma->node)) | |
5041 | return true; | |
5042 | ||
5043 | return false; | |
5044 | } | |
5045 | ||
5046 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
5047 | { | |
5048 | struct i915_vma *vma; | |
5049 | ||
5050 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
5051 | if (drm_mm_node_allocated(&vma->node)) | |
5052 | return true; | |
5053 | ||
5054 | return false; | |
5055 | } | |
5056 | ||
5057 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
5058 | struct i915_address_space *vm) | |
5059 | { | |
5060 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5061 | struct i915_vma *vma; | |
5062 | ||
5063 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); | |
5064 | ||
5065 | BUG_ON(list_empty(&o->vma_list)); | |
5066 | ||
5067 | list_for_each_entry(vma, &o->vma_list, vma_link) { | |
5068 | if (i915_is_ggtt(vma->vm) && | |
5069 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) | |
5070 | continue; | |
5071 | if (vma->vm == vm) | |
5072 | return vma->node.size; | |
5073 | } | |
5074 | return 0; | |
5075 | } | |
5076 | ||
5077 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) | |
5078 | { | |
5079 | struct i915_vma *vma; | |
5080 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
5081 | if (vma->pin_count > 0) | |
5082 | return true; | |
5083 | ||
5084 | return false; | |
5085 | } | |
5086 | ||
5087 | /* Allocate a new GEM object and fill it with the supplied data */ | |
5088 | struct drm_i915_gem_object * | |
5089 | i915_gem_object_create_from_data(struct drm_device *dev, | |
5090 | const void *data, size_t size) | |
5091 | { | |
5092 | struct drm_i915_gem_object *obj; | |
5093 | struct sg_table *sg; | |
5094 | size_t bytes; | |
5095 | int ret; | |
5096 | ||
5097 | obj = i915_gem_alloc_object(dev, round_up(size, PAGE_SIZE)); | |
5098 | if (IS_ERR_OR_NULL(obj)) | |
5099 | return obj; | |
5100 | ||
5101 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
5102 | if (ret) | |
5103 | goto fail; | |
5104 | ||
5105 | ret = i915_gem_object_get_pages(obj); | |
5106 | if (ret) | |
5107 | goto fail; | |
5108 | ||
5109 | i915_gem_object_pin_pages(obj); | |
5110 | sg = obj->pages; | |
5111 | bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size); | |
5112 | i915_gem_object_unpin_pages(obj); | |
5113 | ||
5114 | if (WARN_ON(bytes != size)) { | |
5115 | DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size); | |
5116 | ret = -EFAULT; | |
5117 | goto fail; | |
5118 | } | |
5119 | ||
5120 | return obj; | |
5121 | ||
5122 | fail: | |
5123 | drm_gem_object_unreference(&obj->base); | |
5124 | return ERR_PTR(ret); | |
5125 | } |