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1 | /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. | |
2 | * All Rights Reserved. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the | |
6 | * "Software"), to deal in the Software without restriction, including | |
7 | * without limitation the rights to use, copy, modify, merge, publish, | |
8 | * distribute, sub license, and/or sell copies of the Software, and to | |
9 | * permit persons to whom the Software is furnished to do so, subject to | |
10 | * the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the | |
13 | * next paragraph) shall be included in all copies or substantial portions | |
14 | * of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
19 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
20 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
21 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
22 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #ifndef _I915_REG_H_ | |
26 | #define _I915_REG_H_ | |
27 | ||
28 | #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) | |
29 | #define _PLANE(plane, a, b) _PIPE(plane, a, b) | |
30 | #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a))) | |
31 | #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) | |
32 | #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \ | |
33 | (pipe) == PIPE_B ? (b) : (c)) | |
34 | #define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \ | |
35 | (port) == PORT_B ? (b) : (c)) | |
36 | ||
37 | #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a)) | |
38 | #define _MASKED_BIT_DISABLE(a) ((a) << 16) | |
39 | ||
40 | /* PCI config space */ | |
41 | ||
42 | #define HPLLCC 0xc0 /* 855 only */ | |
43 | #define GC_CLOCK_CONTROL_MASK (0xf << 0) | |
44 | #define GC_CLOCK_133_200 (0 << 0) | |
45 | #define GC_CLOCK_100_200 (1 << 0) | |
46 | #define GC_CLOCK_100_133 (2 << 0) | |
47 | #define GC_CLOCK_166_250 (3 << 0) | |
48 | #define GCFGC2 0xda | |
49 | #define GCFGC 0xf0 /* 915+ only */ | |
50 | #define GC_LOW_FREQUENCY_ENABLE (1 << 7) | |
51 | #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) | |
52 | #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) | |
53 | #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) | |
54 | #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) | |
55 | #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) | |
56 | #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) | |
57 | #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) | |
58 | #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) | |
59 | #define GC_DISPLAY_CLOCK_MASK (7 << 4) | |
60 | #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) | |
61 | #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) | |
62 | #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) | |
63 | #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) | |
64 | #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) | |
65 | #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) | |
66 | #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) | |
67 | #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) | |
68 | #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) | |
69 | #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) | |
70 | #define I945_GC_RENDER_CLOCK_MASK (7 << 0) | |
71 | #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) | |
72 | #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) | |
73 | #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) | |
74 | #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) | |
75 | #define I915_GC_RENDER_CLOCK_MASK (7 << 0) | |
76 | #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) | |
77 | #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) | |
78 | #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) | |
79 | #define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */ | |
80 | ||
81 | ||
82 | /* Graphics reset regs */ | |
83 | #define I915_GDRST 0xc0 /* PCI config register */ | |
84 | #define GRDOM_FULL (0<<2) | |
85 | #define GRDOM_RENDER (1<<2) | |
86 | #define GRDOM_MEDIA (3<<2) | |
87 | #define GRDOM_MASK (3<<2) | |
88 | #define GRDOM_RESET_STATUS (1<<1) | |
89 | #define GRDOM_RESET_ENABLE (1<<0) | |
90 | ||
91 | #define ILK_GDSR 0x2ca4 /* MCHBAR offset */ | |
92 | #define ILK_GRDOM_FULL (0<<1) | |
93 | #define ILK_GRDOM_RENDER (1<<1) | |
94 | #define ILK_GRDOM_MEDIA (3<<1) | |
95 | #define ILK_GRDOM_MASK (3<<1) | |
96 | #define ILK_GRDOM_RESET_ENABLE (1<<0) | |
97 | ||
98 | #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ | |
99 | #define GEN6_MBC_SNPCR_SHIFT 21 | |
100 | #define GEN6_MBC_SNPCR_MASK (3<<21) | |
101 | #define GEN6_MBC_SNPCR_MAX (0<<21) | |
102 | #define GEN6_MBC_SNPCR_MED (1<<21) | |
103 | #define GEN6_MBC_SNPCR_LOW (2<<21) | |
104 | #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ | |
105 | ||
106 | #define VLV_G3DCTL 0x9024 | |
107 | #define VLV_GSCKGCTL 0x9028 | |
108 | ||
109 | #define GEN6_MBCTL 0x0907c | |
110 | #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) | |
111 | #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) | |
112 | #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) | |
113 | #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) | |
114 | #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) | |
115 | ||
116 | #define GEN6_GDRST 0x941c | |
117 | #define GEN6_GRDOM_FULL (1 << 0) | |
118 | #define GEN6_GRDOM_RENDER (1 << 1) | |
119 | #define GEN6_GRDOM_MEDIA (1 << 2) | |
120 | #define GEN6_GRDOM_BLT (1 << 3) | |
121 | ||
122 | #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228) | |
123 | #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518) | |
124 | #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220) | |
125 | #define PP_DIR_DCLV_2G 0xffffffff | |
126 | ||
127 | #define GEN8_RING_PDP_UDW(ring, n) ((ring)->mmio_base+0x270 + ((n) * 8 + 4)) | |
128 | #define GEN8_RING_PDP_LDW(ring, n) ((ring)->mmio_base+0x270 + (n) * 8) | |
129 | ||
130 | #define GAM_ECOCHK 0x4090 | |
131 | #define ECOCHK_SNB_BIT (1<<10) | |
132 | #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6) | |
133 | #define ECOCHK_PPGTT_CACHE64B (0x3<<3) | |
134 | #define ECOCHK_PPGTT_CACHE4B (0x0<<3) | |
135 | #define ECOCHK_PPGTT_GFDT_IVB (0x1<<4) | |
136 | #define ECOCHK_PPGTT_LLC_IVB (0x1<<3) | |
137 | #define ECOCHK_PPGTT_UC_HSW (0x1<<3) | |
138 | #define ECOCHK_PPGTT_WT_HSW (0x2<<3) | |
139 | #define ECOCHK_PPGTT_WB_HSW (0x3<<3) | |
140 | ||
141 | #define GAC_ECO_BITS 0x14090 | |
142 | #define ECOBITS_SNB_BIT (1<<13) | |
143 | #define ECOBITS_PPGTT_CACHE64B (3<<8) | |
144 | #define ECOBITS_PPGTT_CACHE4B (0<<8) | |
145 | ||
146 | #define GAB_CTL 0x24000 | |
147 | #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8) | |
148 | ||
149 | #define GEN7_BIOS_RESERVED 0x1082C0 | |
150 | #define GEN7_BIOS_RESERVED_1M (0 << 5) | |
151 | #define GEN7_BIOS_RESERVED_256K (1 << 5) | |
152 | #define GEN8_BIOS_RESERVED_SHIFT 7 | |
153 | #define GEN7_BIOS_RESERVED_MASK 0x1 | |
154 | #define GEN8_BIOS_RESERVED_MASK 0x3 | |
155 | ||
156 | ||
157 | /* VGA stuff */ | |
158 | ||
159 | #define VGA_ST01_MDA 0x3ba | |
160 | #define VGA_ST01_CGA 0x3da | |
161 | ||
162 | #define VGA_MSR_WRITE 0x3c2 | |
163 | #define VGA_MSR_READ 0x3cc | |
164 | #define VGA_MSR_MEM_EN (1<<1) | |
165 | #define VGA_MSR_CGA_MODE (1<<0) | |
166 | ||
167 | #define VGA_SR_INDEX 0x3c4 | |
168 | #define SR01 1 | |
169 | #define VGA_SR_DATA 0x3c5 | |
170 | ||
171 | #define VGA_AR_INDEX 0x3c0 | |
172 | #define VGA_AR_VID_EN (1<<5) | |
173 | #define VGA_AR_DATA_WRITE 0x3c0 | |
174 | #define VGA_AR_DATA_READ 0x3c1 | |
175 | ||
176 | #define VGA_GR_INDEX 0x3ce | |
177 | #define VGA_GR_DATA 0x3cf | |
178 | /* GR05 */ | |
179 | #define VGA_GR_MEM_READ_MODE_SHIFT 3 | |
180 | #define VGA_GR_MEM_READ_MODE_PLANE 1 | |
181 | /* GR06 */ | |
182 | #define VGA_GR_MEM_MODE_MASK 0xc | |
183 | #define VGA_GR_MEM_MODE_SHIFT 2 | |
184 | #define VGA_GR_MEM_A0000_AFFFF 0 | |
185 | #define VGA_GR_MEM_A0000_BFFFF 1 | |
186 | #define VGA_GR_MEM_B0000_B7FFF 2 | |
187 | #define VGA_GR_MEM_B0000_BFFFF 3 | |
188 | ||
189 | #define VGA_DACMASK 0x3c6 | |
190 | #define VGA_DACRX 0x3c7 | |
191 | #define VGA_DACWX 0x3c8 | |
192 | #define VGA_DACDATA 0x3c9 | |
193 | ||
194 | #define VGA_CR_INDEX_MDA 0x3b4 | |
195 | #define VGA_CR_DATA_MDA 0x3b5 | |
196 | #define VGA_CR_INDEX_CGA 0x3d4 | |
197 | #define VGA_CR_DATA_CGA 0x3d5 | |
198 | ||
199 | /* | |
200 | * Instruction field definitions used by the command parser | |
201 | */ | |
202 | #define INSTR_CLIENT_SHIFT 29 | |
203 | #define INSTR_CLIENT_MASK 0xE0000000 | |
204 | #define INSTR_MI_CLIENT 0x0 | |
205 | #define INSTR_BC_CLIENT 0x2 | |
206 | #define INSTR_RC_CLIENT 0x3 | |
207 | #define INSTR_SUBCLIENT_SHIFT 27 | |
208 | #define INSTR_SUBCLIENT_MASK 0x18000000 | |
209 | #define INSTR_MEDIA_SUBCLIENT 0x2 | |
210 | ||
211 | /* | |
212 | * Memory interface instructions used by the kernel | |
213 | */ | |
214 | #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) | |
215 | /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */ | |
216 | #define MI_GLOBAL_GTT (1<<22) | |
217 | ||
218 | #define MI_NOOP MI_INSTR(0, 0) | |
219 | #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) | |
220 | #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) | |
221 | #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) | |
222 | #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) | |
223 | #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) | |
224 | #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) | |
225 | #define MI_FLUSH MI_INSTR(0x04, 0) | |
226 | #define MI_READ_FLUSH (1 << 0) | |
227 | #define MI_EXE_FLUSH (1 << 1) | |
228 | #define MI_NO_WRITE_FLUSH (1 << 2) | |
229 | #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ | |
230 | #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ | |
231 | #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ | |
232 | #define MI_REPORT_HEAD MI_INSTR(0x07, 0) | |
233 | #define MI_ARB_ON_OFF MI_INSTR(0x08, 0) | |
234 | #define MI_ARB_ENABLE (1<<0) | |
235 | #define MI_ARB_DISABLE (0<<0) | |
236 | #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) | |
237 | #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) | |
238 | #define MI_SUSPEND_FLUSH_EN (1<<0) | |
239 | #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) | |
240 | #define MI_OVERLAY_CONTINUE (0x0<<21) | |
241 | #define MI_OVERLAY_ON (0x1<<21) | |
242 | #define MI_OVERLAY_OFF (0x2<<21) | |
243 | #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) | |
244 | #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) | |
245 | #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) | |
246 | #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) | |
247 | /* IVB has funny definitions for which plane to flip. */ | |
248 | #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19) | |
249 | #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19) | |
250 | #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19) | |
251 | #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) | |
252 | #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) | |
253 | #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) | |
254 | /* SKL ones */ | |
255 | #define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8) | |
256 | #define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8) | |
257 | #define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8) | |
258 | #define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8) | |
259 | #define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8) | |
260 | #define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8) | |
261 | #define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8) | |
262 | #define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8) | |
263 | #define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8) | |
264 | #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */ | |
265 | #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) | |
266 | #define MI_SEMAPHORE_UPDATE (1<<21) | |
267 | #define MI_SEMAPHORE_COMPARE (1<<20) | |
268 | #define MI_SEMAPHORE_REGISTER (1<<18) | |
269 | #define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */ | |
270 | #define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */ | |
271 | #define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */ | |
272 | #define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */ | |
273 | #define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */ | |
274 | #define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */ | |
275 | #define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */ | |
276 | #define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */ | |
277 | #define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */ | |
278 | #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */ | |
279 | #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */ | |
280 | #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */ | |
281 | #define MI_SEMAPHORE_SYNC_INVALID (3<<16) | |
282 | #define MI_SEMAPHORE_SYNC_MASK (3<<16) | |
283 | #define MI_SET_CONTEXT MI_INSTR(0x18, 0) | |
284 | #define MI_MM_SPACE_GTT (1<<8) | |
285 | #define MI_MM_SPACE_PHYSICAL (0<<8) | |
286 | #define MI_SAVE_EXT_STATE_EN (1<<3) | |
287 | #define MI_RESTORE_EXT_STATE_EN (1<<2) | |
288 | #define MI_FORCE_RESTORE (1<<1) | |
289 | #define MI_RESTORE_INHIBIT (1<<0) | |
290 | #define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */ | |
291 | #define MI_SEMAPHORE_TARGET(engine) ((engine)<<15) | |
292 | #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */ | |
293 | #define MI_SEMAPHORE_POLL (1<<15) | |
294 | #define MI_SEMAPHORE_SAD_GTE_SDD (1<<12) | |
295 | #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) | |
296 | #define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2) | |
297 | #define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */ | |
298 | #define MI_USE_GGTT (1 << 22) /* g4x+ */ | |
299 | #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) | |
300 | #define MI_STORE_DWORD_INDEX_SHIFT 2 | |
301 | /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: | |
302 | * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw | |
303 | * simply ignores the register load under certain conditions. | |
304 | * - One can actually load arbitrary many arbitrary registers: Simply issue x | |
305 | * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! | |
306 | */ | |
307 | #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) | |
308 | #define MI_LRI_FORCE_POSTED (1<<12) | |
309 | #define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1) | |
310 | #define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1) | |
311 | #define MI_SRM_LRM_GLOBAL_GTT (1<<22) | |
312 | #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ | |
313 | #define MI_FLUSH_DW_STORE_INDEX (1<<21) | |
314 | #define MI_INVALIDATE_TLB (1<<18) | |
315 | #define MI_FLUSH_DW_OP_STOREDW (1<<14) | |
316 | #define MI_FLUSH_DW_OP_MASK (3<<14) | |
317 | #define MI_FLUSH_DW_NOTIFY (1<<8) | |
318 | #define MI_INVALIDATE_BSD (1<<7) | |
319 | #define MI_FLUSH_DW_USE_GTT (1<<2) | |
320 | #define MI_FLUSH_DW_USE_PPGTT (0<<2) | |
321 | #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) | |
322 | #define MI_BATCH_NON_SECURE (1) | |
323 | /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */ | |
324 | #define MI_BATCH_NON_SECURE_I965 (1<<8) | |
325 | #define MI_BATCH_PPGTT_HSW (1<<8) | |
326 | #define MI_BATCH_NON_SECURE_HSW (1<<13) | |
327 | #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) | |
328 | #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ | |
329 | #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1) | |
330 | ||
331 | #define MI_PREDICATE_SRC0 (0x2400) | |
332 | #define MI_PREDICATE_SRC1 (0x2408) | |
333 | ||
334 | #define MI_PREDICATE_RESULT_2 (0x2214) | |
335 | #define LOWER_SLICE_ENABLED (1<<0) | |
336 | #define LOWER_SLICE_DISABLED (0<<0) | |
337 | ||
338 | /* | |
339 | * 3D instructions used by the kernel | |
340 | */ | |
341 | #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) | |
342 | ||
343 | #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) | |
344 | #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) | |
345 | #define SC_UPDATE_SCISSOR (0x1<<1) | |
346 | #define SC_ENABLE_MASK (0x1<<0) | |
347 | #define SC_ENABLE (0x1<<0) | |
348 | #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) | |
349 | #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) | |
350 | #define SCI_YMIN_MASK (0xffff<<16) | |
351 | #define SCI_XMIN_MASK (0xffff<<0) | |
352 | #define SCI_YMAX_MASK (0xffff<<16) | |
353 | #define SCI_XMAX_MASK (0xffff<<0) | |
354 | #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) | |
355 | #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) | |
356 | #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) | |
357 | #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) | |
358 | #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) | |
359 | #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) | |
360 | #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) | |
361 | #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) | |
362 | #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) | |
363 | ||
364 | #define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2)) | |
365 | #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) | |
366 | #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) | |
367 | #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) | |
368 | #define BLT_WRITE_A (2<<20) | |
369 | #define BLT_WRITE_RGB (1<<20) | |
370 | #define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A) | |
371 | #define BLT_DEPTH_8 (0<<24) | |
372 | #define BLT_DEPTH_16_565 (1<<24) | |
373 | #define BLT_DEPTH_16_1555 (2<<24) | |
374 | #define BLT_DEPTH_32 (3<<24) | |
375 | #define BLT_ROP_SRC_COPY (0xcc<<16) | |
376 | #define BLT_ROP_COLOR_COPY (0xf0<<16) | |
377 | #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ | |
378 | #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ | |
379 | #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) | |
380 | #define ASYNC_FLIP (1<<22) | |
381 | #define DISPLAY_PLANE_A (0<<20) | |
382 | #define DISPLAY_PLANE_B (1<<20) | |
383 | #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) | |
384 | #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ | |
385 | #define PIPE_CONTROL_MMIO_WRITE (1<<23) | |
386 | #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21) | |
387 | #define PIPE_CONTROL_CS_STALL (1<<20) | |
388 | #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) | |
389 | #define PIPE_CONTROL_QW_WRITE (1<<14) | |
390 | #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14) | |
391 | #define PIPE_CONTROL_DEPTH_STALL (1<<13) | |
392 | #define PIPE_CONTROL_WRITE_FLUSH (1<<12) | |
393 | #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ | |
394 | #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ | |
395 | #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ | |
396 | #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) | |
397 | #define PIPE_CONTROL_NOTIFY (1<<8) | |
398 | #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */ | |
399 | #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) | |
400 | #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) | |
401 | #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) | |
402 | #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) | |
403 | #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) | |
404 | #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ | |
405 | ||
406 | /* | |
407 | * Commands used only by the command parser | |
408 | */ | |
409 | #define MI_SET_PREDICATE MI_INSTR(0x01, 0) | |
410 | #define MI_ARB_CHECK MI_INSTR(0x05, 0) | |
411 | #define MI_RS_CONTROL MI_INSTR(0x06, 0) | |
412 | #define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0) | |
413 | #define MI_PREDICATE MI_INSTR(0x0C, 0) | |
414 | #define MI_RS_CONTEXT MI_INSTR(0x0F, 0) | |
415 | #define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0) | |
416 | #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0) | |
417 | #define MI_URB_CLEAR MI_INSTR(0x19, 0) | |
418 | #define MI_UPDATE_GTT MI_INSTR(0x23, 0) | |
419 | #define MI_CLFLUSH MI_INSTR(0x27, 0) | |
420 | #define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0) | |
421 | #define MI_REPORT_PERF_COUNT_GGTT (1<<0) | |
422 | #define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0) | |
423 | #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0) | |
424 | #define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0) | |
425 | #define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0) | |
426 | #define MI_STORE_URB_MEM MI_INSTR(0x2D, 0) | |
427 | #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0) | |
428 | ||
429 | #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16)) | |
430 | #define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16)) | |
431 | #define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16)) | |
432 | #define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18) | |
433 | #define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16)) | |
434 | #define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16)) | |
435 | #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \ | |
436 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16)) | |
437 | #define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \ | |
438 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16)) | |
439 | #define GFX_OP_3DSTATE_SO_DECL_LIST \ | |
440 | ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16)) | |
441 | ||
442 | #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \ | |
443 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16)) | |
444 | #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \ | |
445 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16)) | |
446 | #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \ | |
447 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16)) | |
448 | #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \ | |
449 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16)) | |
450 | #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \ | |
451 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16)) | |
452 | ||
453 | #define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16)) | |
454 | ||
455 | #define COLOR_BLT ((0x2<<29)|(0x40<<22)) | |
456 | #define SRC_COPY_BLT ((0x2<<29)|(0x43<<22)) | |
457 | ||
458 | /* | |
459 | * Registers used only by the command parser | |
460 | */ | |
461 | #define BCS_SWCTRL 0x22200 | |
462 | ||
463 | #define HS_INVOCATION_COUNT 0x2300 | |
464 | #define DS_INVOCATION_COUNT 0x2308 | |
465 | #define IA_VERTICES_COUNT 0x2310 | |
466 | #define IA_PRIMITIVES_COUNT 0x2318 | |
467 | #define VS_INVOCATION_COUNT 0x2320 | |
468 | #define GS_INVOCATION_COUNT 0x2328 | |
469 | #define GS_PRIMITIVES_COUNT 0x2330 | |
470 | #define CL_INVOCATION_COUNT 0x2338 | |
471 | #define CL_PRIMITIVES_COUNT 0x2340 | |
472 | #define PS_INVOCATION_COUNT 0x2348 | |
473 | #define PS_DEPTH_COUNT 0x2350 | |
474 | ||
475 | /* There are the 4 64-bit counter registers, one for each stream output */ | |
476 | #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8) | |
477 | ||
478 | #define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8) | |
479 | ||
480 | #define GEN7_3DPRIM_END_OFFSET 0x2420 | |
481 | #define GEN7_3DPRIM_START_VERTEX 0x2430 | |
482 | #define GEN7_3DPRIM_VERTEX_COUNT 0x2434 | |
483 | #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438 | |
484 | #define GEN7_3DPRIM_START_INSTANCE 0x243C | |
485 | #define GEN7_3DPRIM_BASE_VERTEX 0x2440 | |
486 | ||
487 | #define OACONTROL 0x2360 | |
488 | ||
489 | #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 | |
490 | #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 | |
491 | #define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \ | |
492 | _GEN7_PIPEA_DE_LOAD_SL, \ | |
493 | _GEN7_PIPEB_DE_LOAD_SL) | |
494 | ||
495 | /* | |
496 | * Reset registers | |
497 | */ | |
498 | #define DEBUG_RESET_I830 0x6070 | |
499 | #define DEBUG_RESET_FULL (1<<7) | |
500 | #define DEBUG_RESET_RENDER (1<<8) | |
501 | #define DEBUG_RESET_DISPLAY (1<<9) | |
502 | ||
503 | /* | |
504 | * IOSF sideband | |
505 | */ | |
506 | #define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100) | |
507 | #define IOSF_DEVFN_SHIFT 24 | |
508 | #define IOSF_OPCODE_SHIFT 16 | |
509 | #define IOSF_PORT_SHIFT 8 | |
510 | #define IOSF_BYTE_ENABLES_SHIFT 4 | |
511 | #define IOSF_BAR_SHIFT 1 | |
512 | #define IOSF_SB_BUSY (1<<0) | |
513 | #define IOSF_PORT_BUNIT 0x3 | |
514 | #define IOSF_PORT_PUNIT 0x4 | |
515 | #define IOSF_PORT_NC 0x11 | |
516 | #define IOSF_PORT_DPIO 0x12 | |
517 | #define IOSF_PORT_DPIO_2 0x1a | |
518 | #define IOSF_PORT_GPIO_NC 0x13 | |
519 | #define IOSF_PORT_CCK 0x14 | |
520 | #define IOSF_PORT_CCU 0xA9 | |
521 | #define IOSF_PORT_GPS_CORE 0x48 | |
522 | #define IOSF_PORT_FLISDSI 0x1B | |
523 | #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104) | |
524 | #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108) | |
525 | ||
526 | /* See configdb bunit SB addr map */ | |
527 | #define BUNIT_REG_BISOC 0x11 | |
528 | ||
529 | #define PUNIT_REG_DSPFREQ 0x36 | |
530 | #define DSPFREQSTAT_SHIFT_CHV 24 | |
531 | #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV) | |
532 | #define DSPFREQGUAR_SHIFT_CHV 8 | |
533 | #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV) | |
534 | #define DSPFREQSTAT_SHIFT 30 | |
535 | #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) | |
536 | #define DSPFREQGUAR_SHIFT 14 | |
537 | #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) | |
538 | #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) | |
539 | #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) | |
540 | #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) | |
541 | #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) | |
542 | #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) | |
543 | #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe)) | |
544 | #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16)) | |
545 | #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe)) | |
546 | #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe)) | |
547 | #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe)) | |
548 | #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe)) | |
549 | #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe)) | |
550 | ||
551 | /* See the PUNIT HAS v0.8 for the below bits */ | |
552 | enum punit_power_well { | |
553 | PUNIT_POWER_WELL_RENDER = 0, | |
554 | PUNIT_POWER_WELL_MEDIA = 1, | |
555 | PUNIT_POWER_WELL_DISP2D = 3, | |
556 | PUNIT_POWER_WELL_DPIO_CMN_BC = 5, | |
557 | PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6, | |
558 | PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7, | |
559 | PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8, | |
560 | PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9, | |
561 | PUNIT_POWER_WELL_DPIO_RX0 = 10, | |
562 | PUNIT_POWER_WELL_DPIO_RX1 = 11, | |
563 | PUNIT_POWER_WELL_DPIO_CMN_D = 12, | |
564 | /* FIXME: guesswork below */ | |
565 | PUNIT_POWER_WELL_DPIO_TX_D_LANES_01 = 13, | |
566 | PUNIT_POWER_WELL_DPIO_TX_D_LANES_23 = 14, | |
567 | PUNIT_POWER_WELL_DPIO_RX2 = 15, | |
568 | ||
569 | PUNIT_POWER_WELL_NUM, | |
570 | }; | |
571 | ||
572 | #define PUNIT_REG_PWRGT_CTRL 0x60 | |
573 | #define PUNIT_REG_PWRGT_STATUS 0x61 | |
574 | #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2)) | |
575 | #define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2)) | |
576 | #define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2)) | |
577 | #define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2)) | |
578 | #define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2)) | |
579 | ||
580 | #define PUNIT_REG_GPU_LFM 0xd3 | |
581 | #define PUNIT_REG_GPU_FREQ_REQ 0xd4 | |
582 | #define PUNIT_REG_GPU_FREQ_STS 0xd8 | |
583 | #define GPLLENABLE (1<<4) | |
584 | #define GENFREQSTATUS (1<<0) | |
585 | #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc | |
586 | #define PUNIT_REG_CZ_TIMESTAMP 0xce | |
587 | ||
588 | #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ | |
589 | #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ | |
590 | ||
591 | #define PUNIT_GPU_STATUS_REG 0xdb | |
592 | #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16 | |
593 | #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff | |
594 | #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8 | |
595 | #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff | |
596 | ||
597 | #define PUNIT_GPU_DUTYCYCLE_REG 0xdf | |
598 | #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8 | |
599 | #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff | |
600 | ||
601 | #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c | |
602 | #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 | |
603 | #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 | |
604 | #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11 | |
605 | #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800 | |
606 | #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34 | |
607 | #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 | |
608 | #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 | |
609 | #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 | |
610 | #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 | |
611 | ||
612 | #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000 | |
613 | #define VLV_RP_UP_EI_THRESHOLD 90 | |
614 | #define VLV_RP_DOWN_EI_THRESHOLD 70 | |
615 | #define VLV_INT_COUNT_FOR_DOWN_EI 5 | |
616 | ||
617 | /* vlv2 north clock has */ | |
618 | #define CCK_FUSE_REG 0x8 | |
619 | #define CCK_FUSE_HPLL_FREQ_MASK 0x3 | |
620 | #define CCK_REG_DSI_PLL_FUSE 0x44 | |
621 | #define CCK_REG_DSI_PLL_CONTROL 0x48 | |
622 | #define DSI_PLL_VCO_EN (1 << 31) | |
623 | #define DSI_PLL_LDO_GATE (1 << 30) | |
624 | #define DSI_PLL_P1_POST_DIV_SHIFT 17 | |
625 | #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) | |
626 | #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) | |
627 | #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12) | |
628 | #define DSI_PLL_MUX_MASK (3 << 9) | |
629 | #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) | |
630 | #define DSI_PLL_MUX_DSI0_CCK (1 << 10) | |
631 | #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) | |
632 | #define DSI_PLL_MUX_DSI1_CCK (1 << 9) | |
633 | #define DSI_PLL_CLK_GATE_MASK (0xf << 5) | |
634 | #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8) | |
635 | #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7) | |
636 | #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6) | |
637 | #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5) | |
638 | #define DSI_PLL_LOCK (1 << 0) | |
639 | #define CCK_REG_DSI_PLL_DIVIDER 0x4c | |
640 | #define DSI_PLL_LFSR (1 << 31) | |
641 | #define DSI_PLL_FRACTION_EN (1 << 30) | |
642 | #define DSI_PLL_FRAC_COUNTER_SHIFT 27 | |
643 | #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) | |
644 | #define DSI_PLL_USYNC_CNT_SHIFT 18 | |
645 | #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) | |
646 | #define DSI_PLL_N1_DIV_SHIFT 16 | |
647 | #define DSI_PLL_N1_DIV_MASK (3 << 16) | |
648 | #define DSI_PLL_M1_DIV_SHIFT 0 | |
649 | #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) | |
650 | #define CCK_DISPLAY_CLOCK_CONTROL 0x6b | |
651 | #define DISPLAY_TRUNK_FORCE_ON (1 << 17) | |
652 | #define DISPLAY_TRUNK_FORCE_OFF (1 << 16) | |
653 | #define DISPLAY_FREQUENCY_STATUS (0x1f << 8) | |
654 | #define DISPLAY_FREQUENCY_STATUS_SHIFT 8 | |
655 | #define DISPLAY_FREQUENCY_VALUES (0x1f << 0) | |
656 | ||
657 | /** | |
658 | * DOC: DPIO | |
659 | * | |
660 | * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI | |
661 | * ports. DPIO is the name given to such a display PHY. These PHYs | |
662 | * don't follow the standard programming model using direct MMIO | |
663 | * registers, and instead their registers must be accessed trough IOSF | |
664 | * sideband. VLV has one such PHY for driving ports B and C, and CHV | |
665 | * adds another PHY for driving port D. Each PHY responds to specific | |
666 | * IOSF-SB port. | |
667 | * | |
668 | * Each display PHY is made up of one or two channels. Each channel | |
669 | * houses a common lane part which contains the PLL and other common | |
670 | * logic. CH0 common lane also contains the IOSF-SB logic for the | |
671 | * Common Register Interface (CRI) ie. the DPIO registers. CRI clock | |
672 | * must be running when any DPIO registers are accessed. | |
673 | * | |
674 | * In addition to having their own registers, the PHYs are also | |
675 | * controlled through some dedicated signals from the display | |
676 | * controller. These include PLL reference clock enable, PLL enable, | |
677 | * and CRI clock selection, for example. | |
678 | * | |
679 | * Eeach channel also has two splines (also called data lanes), and | |
680 | * each spline is made up of one Physical Access Coding Sub-Layer | |
681 | * (PCS) block and two TX lanes. So each channel has two PCS blocks | |
682 | * and four TX lanes. The TX lanes are used as DP lanes or TMDS | |
683 | * data/clock pairs depending on the output type. | |
684 | * | |
685 | * Additionally the PHY also contains an AUX lane with AUX blocks | |
686 | * for each channel. This is used for DP AUX communication, but | |
687 | * this fact isn't really relevant for the driver since AUX is | |
688 | * controlled from the display controller side. No DPIO registers | |
689 | * need to be accessed during AUX communication, | |
690 | * | |
691 | * Generally the common lane corresponds to the pipe and | |
692 | * the spline (PCS/TX) corresponds to the port. | |
693 | * | |
694 | * For dual channel PHY (VLV/CHV): | |
695 | * | |
696 | * pipe A == CMN/PLL/REF CH0 | |
697 | * | |
698 | * pipe B == CMN/PLL/REF CH1 | |
699 | * | |
700 | * port B == PCS/TX CH0 | |
701 | * | |
702 | * port C == PCS/TX CH1 | |
703 | * | |
704 | * This is especially important when we cross the streams | |
705 | * ie. drive port B with pipe B, or port C with pipe A. | |
706 | * | |
707 | * For single channel PHY (CHV): | |
708 | * | |
709 | * pipe C == CMN/PLL/REF CH0 | |
710 | * | |
711 | * port D == PCS/TX CH0 | |
712 | * | |
713 | * Note: digital port B is DDI0, digital port C is DDI1, | |
714 | * digital port D is DDI2 | |
715 | */ | |
716 | /* | |
717 | * Dual channel PHY (VLV/CHV) | |
718 | * --------------------------------- | |
719 | * | CH0 | CH1 | | |
720 | * | CMN/PLL/REF | CMN/PLL/REF | | |
721 | * |---------------|---------------| Display PHY | |
722 | * | PCS01 | PCS23 | PCS01 | PCS23 | | |
723 | * |-------|-------|-------|-------| | |
724 | * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| | |
725 | * --------------------------------- | |
726 | * | DDI0 | DDI1 | DP/HDMI ports | |
727 | * --------------------------------- | |
728 | * | |
729 | * Single channel PHY (CHV) | |
730 | * ----------------- | |
731 | * | CH0 | | |
732 | * | CMN/PLL/REF | | |
733 | * |---------------| Display PHY | |
734 | * | PCS01 | PCS23 | | |
735 | * |-------|-------| | |
736 | * |TX0|TX1|TX2|TX3| | |
737 | * ----------------- | |
738 | * | DDI2 | DP/HDMI port | |
739 | * ----------------- | |
740 | */ | |
741 | #define DPIO_DEVFN 0 | |
742 | ||
743 | #define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110) | |
744 | #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ | |
745 | #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */ | |
746 | #define DPIO_SFR_BYPASS (1<<1) | |
747 | #define DPIO_CMNRST (1<<0) | |
748 | ||
749 | #define DPIO_PHY(pipe) ((pipe) >> 1) | |
750 | #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy]) | |
751 | ||
752 | /* | |
753 | * Per pipe/PLL DPIO regs | |
754 | */ | |
755 | #define _VLV_PLL_DW3_CH0 0x800c | |
756 | #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ | |
757 | #define DPIO_POST_DIV_DAC 0 | |
758 | #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ | |
759 | #define DPIO_POST_DIV_LVDS1 2 | |
760 | #define DPIO_POST_DIV_LVDS2 3 | |
761 | #define DPIO_K_SHIFT (24) /* 4 bits */ | |
762 | #define DPIO_P1_SHIFT (21) /* 3 bits */ | |
763 | #define DPIO_P2_SHIFT (16) /* 5 bits */ | |
764 | #define DPIO_N_SHIFT (12) /* 4 bits */ | |
765 | #define DPIO_ENABLE_CALIBRATION (1<<11) | |
766 | #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ | |
767 | #define DPIO_M2DIV_MASK 0xff | |
768 | #define _VLV_PLL_DW3_CH1 0x802c | |
769 | #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) | |
770 | ||
771 | #define _VLV_PLL_DW5_CH0 0x8014 | |
772 | #define DPIO_REFSEL_OVERRIDE 27 | |
773 | #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ | |
774 | #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ | |
775 | #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ | |
776 | #define DPIO_PLL_REFCLK_SEL_MASK 3 | |
777 | #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ | |
778 | #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ | |
779 | #define _VLV_PLL_DW5_CH1 0x8034 | |
780 | #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) | |
781 | ||
782 | #define _VLV_PLL_DW7_CH0 0x801c | |
783 | #define _VLV_PLL_DW7_CH1 0x803c | |
784 | #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) | |
785 | ||
786 | #define _VLV_PLL_DW8_CH0 0x8040 | |
787 | #define _VLV_PLL_DW8_CH1 0x8060 | |
788 | #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) | |
789 | ||
790 | #define VLV_PLL_DW9_BCAST 0xc044 | |
791 | #define _VLV_PLL_DW9_CH0 0x8044 | |
792 | #define _VLV_PLL_DW9_CH1 0x8064 | |
793 | #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) | |
794 | ||
795 | #define _VLV_PLL_DW10_CH0 0x8048 | |
796 | #define _VLV_PLL_DW10_CH1 0x8068 | |
797 | #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) | |
798 | ||
799 | #define _VLV_PLL_DW11_CH0 0x804c | |
800 | #define _VLV_PLL_DW11_CH1 0x806c | |
801 | #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) | |
802 | ||
803 | /* Spec for ref block start counts at DW10 */ | |
804 | #define VLV_REF_DW13 0x80ac | |
805 | ||
806 | #define VLV_CMN_DW0 0x8100 | |
807 | ||
808 | /* | |
809 | * Per DDI channel DPIO regs | |
810 | */ | |
811 | ||
812 | #define _VLV_PCS_DW0_CH0 0x8200 | |
813 | #define _VLV_PCS_DW0_CH1 0x8400 | |
814 | #define DPIO_PCS_TX_LANE2_RESET (1<<16) | |
815 | #define DPIO_PCS_TX_LANE1_RESET (1<<7) | |
816 | #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4) | |
817 | #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1<<3) | |
818 | #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) | |
819 | ||
820 | #define _VLV_PCS01_DW0_CH0 0x200 | |
821 | #define _VLV_PCS23_DW0_CH0 0x400 | |
822 | #define _VLV_PCS01_DW0_CH1 0x2600 | |
823 | #define _VLV_PCS23_DW0_CH1 0x2800 | |
824 | #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) | |
825 | #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) | |
826 | ||
827 | #define _VLV_PCS_DW1_CH0 0x8204 | |
828 | #define _VLV_PCS_DW1_CH1 0x8404 | |
829 | #define CHV_PCS_REQ_SOFTRESET_EN (1<<23) | |
830 | #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22) | |
831 | #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21) | |
832 | #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) | |
833 | #define DPIO_PCS_CLK_SOFT_RESET (1<<5) | |
834 | #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) | |
835 | ||
836 | #define _VLV_PCS01_DW1_CH0 0x204 | |
837 | #define _VLV_PCS23_DW1_CH0 0x404 | |
838 | #define _VLV_PCS01_DW1_CH1 0x2604 | |
839 | #define _VLV_PCS23_DW1_CH1 0x2804 | |
840 | #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) | |
841 | #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) | |
842 | ||
843 | #define _VLV_PCS_DW8_CH0 0x8220 | |
844 | #define _VLV_PCS_DW8_CH1 0x8420 | |
845 | #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) | |
846 | #define CHV_PCS_USEDCLKCHANNEL (1 << 21) | |
847 | #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) | |
848 | ||
849 | #define _VLV_PCS01_DW8_CH0 0x0220 | |
850 | #define _VLV_PCS23_DW8_CH0 0x0420 | |
851 | #define _VLV_PCS01_DW8_CH1 0x2620 | |
852 | #define _VLV_PCS23_DW8_CH1 0x2820 | |
853 | #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) | |
854 | #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) | |
855 | ||
856 | #define _VLV_PCS_DW9_CH0 0x8224 | |
857 | #define _VLV_PCS_DW9_CH1 0x8424 | |
858 | #define DPIO_PCS_TX2MARGIN_MASK (0x7<<13) | |
859 | #define DPIO_PCS_TX2MARGIN_000 (0<<13) | |
860 | #define DPIO_PCS_TX2MARGIN_101 (1<<13) | |
861 | #define DPIO_PCS_TX1MARGIN_MASK (0x7<<10) | |
862 | #define DPIO_PCS_TX1MARGIN_000 (0<<10) | |
863 | #define DPIO_PCS_TX1MARGIN_101 (1<<10) | |
864 | #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) | |
865 | ||
866 | #define _VLV_PCS01_DW9_CH0 0x224 | |
867 | #define _VLV_PCS23_DW9_CH0 0x424 | |
868 | #define _VLV_PCS01_DW9_CH1 0x2624 | |
869 | #define _VLV_PCS23_DW9_CH1 0x2824 | |
870 | #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) | |
871 | #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) | |
872 | ||
873 | #define _CHV_PCS_DW10_CH0 0x8228 | |
874 | #define _CHV_PCS_DW10_CH1 0x8428 | |
875 | #define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30) | |
876 | #define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31) | |
877 | #define DPIO_PCS_TX2DEEMP_MASK (0xf<<24) | |
878 | #define DPIO_PCS_TX2DEEMP_9P5 (0<<24) | |
879 | #define DPIO_PCS_TX2DEEMP_6P0 (2<<24) | |
880 | #define DPIO_PCS_TX1DEEMP_MASK (0xf<<16) | |
881 | #define DPIO_PCS_TX1DEEMP_9P5 (0<<16) | |
882 | #define DPIO_PCS_TX1DEEMP_6P0 (2<<16) | |
883 | #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) | |
884 | ||
885 | #define _VLV_PCS01_DW10_CH0 0x0228 | |
886 | #define _VLV_PCS23_DW10_CH0 0x0428 | |
887 | #define _VLV_PCS01_DW10_CH1 0x2628 | |
888 | #define _VLV_PCS23_DW10_CH1 0x2828 | |
889 | #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) | |
890 | #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) | |
891 | ||
892 | #define _VLV_PCS_DW11_CH0 0x822c | |
893 | #define _VLV_PCS_DW11_CH1 0x842c | |
894 | #define DPIO_LANEDESKEW_STRAP_OVRD (1<<3) | |
895 | #define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1) | |
896 | #define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0) | |
897 | #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) | |
898 | ||
899 | #define _VLV_PCS01_DW11_CH0 0x022c | |
900 | #define _VLV_PCS23_DW11_CH0 0x042c | |
901 | #define _VLV_PCS01_DW11_CH1 0x262c | |
902 | #define _VLV_PCS23_DW11_CH1 0x282c | |
903 | #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) | |
904 | #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) | |
905 | ||
906 | #define _VLV_PCS_DW12_CH0 0x8230 | |
907 | #define _VLV_PCS_DW12_CH1 0x8430 | |
908 | #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) | |
909 | ||
910 | #define _VLV_PCS_DW14_CH0 0x8238 | |
911 | #define _VLV_PCS_DW14_CH1 0x8438 | |
912 | #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) | |
913 | ||
914 | #define _VLV_PCS_DW23_CH0 0x825c | |
915 | #define _VLV_PCS_DW23_CH1 0x845c | |
916 | #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) | |
917 | ||
918 | #define _VLV_TX_DW2_CH0 0x8288 | |
919 | #define _VLV_TX_DW2_CH1 0x8488 | |
920 | #define DPIO_SWING_MARGIN000_SHIFT 16 | |
921 | #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) | |
922 | #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 | |
923 | #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) | |
924 | ||
925 | #define _VLV_TX_DW3_CH0 0x828c | |
926 | #define _VLV_TX_DW3_CH1 0x848c | |
927 | /* The following bit for CHV phy */ | |
928 | #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27) | |
929 | #define DPIO_SWING_MARGIN101_SHIFT 16 | |
930 | #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) | |
931 | #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) | |
932 | ||
933 | #define _VLV_TX_DW4_CH0 0x8290 | |
934 | #define _VLV_TX_DW4_CH1 0x8490 | |
935 | #define DPIO_SWING_DEEMPH9P5_SHIFT 24 | |
936 | #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) | |
937 | #define DPIO_SWING_DEEMPH6P0_SHIFT 16 | |
938 | #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) | |
939 | #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) | |
940 | ||
941 | #define _VLV_TX3_DW4_CH0 0x690 | |
942 | #define _VLV_TX3_DW4_CH1 0x2a90 | |
943 | #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) | |
944 | ||
945 | #define _VLV_TX_DW5_CH0 0x8294 | |
946 | #define _VLV_TX_DW5_CH1 0x8494 | |
947 | #define DPIO_TX_OCALINIT_EN (1<<31) | |
948 | #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) | |
949 | ||
950 | #define _VLV_TX_DW11_CH0 0x82ac | |
951 | #define _VLV_TX_DW11_CH1 0x84ac | |
952 | #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) | |
953 | ||
954 | #define _VLV_TX_DW14_CH0 0x82b8 | |
955 | #define _VLV_TX_DW14_CH1 0x84b8 | |
956 | #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) | |
957 | ||
958 | /* CHV dpPhy registers */ | |
959 | #define _CHV_PLL_DW0_CH0 0x8000 | |
960 | #define _CHV_PLL_DW0_CH1 0x8180 | |
961 | #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) | |
962 | ||
963 | #define _CHV_PLL_DW1_CH0 0x8004 | |
964 | #define _CHV_PLL_DW1_CH1 0x8184 | |
965 | #define DPIO_CHV_N_DIV_SHIFT 8 | |
966 | #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) | |
967 | #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) | |
968 | ||
969 | #define _CHV_PLL_DW2_CH0 0x8008 | |
970 | #define _CHV_PLL_DW2_CH1 0x8188 | |
971 | #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) | |
972 | ||
973 | #define _CHV_PLL_DW3_CH0 0x800c | |
974 | #define _CHV_PLL_DW3_CH1 0x818c | |
975 | #define DPIO_CHV_FRAC_DIV_EN (1 << 16) | |
976 | #define DPIO_CHV_FIRST_MOD (0 << 8) | |
977 | #define DPIO_CHV_SECOND_MOD (1 << 8) | |
978 | #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 | |
979 | #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) | |
980 | ||
981 | #define _CHV_PLL_DW6_CH0 0x8018 | |
982 | #define _CHV_PLL_DW6_CH1 0x8198 | |
983 | #define DPIO_CHV_GAIN_CTRL_SHIFT 16 | |
984 | #define DPIO_CHV_INT_COEFF_SHIFT 8 | |
985 | #define DPIO_CHV_PROP_COEFF_SHIFT 0 | |
986 | #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) | |
987 | ||
988 | #define _CHV_CMN_DW5_CH0 0x8114 | |
989 | #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) | |
990 | #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) | |
991 | #define CHV_BUFRIGHTENA1_FORCE (3 << 20) | |
992 | #define CHV_BUFRIGHTENA1_MASK (3 << 20) | |
993 | #define CHV_BUFLEFTENA1_DISABLE (0 << 22) | |
994 | #define CHV_BUFLEFTENA1_NORMAL (1 << 22) | |
995 | #define CHV_BUFLEFTENA1_FORCE (3 << 22) | |
996 | #define CHV_BUFLEFTENA1_MASK (3 << 22) | |
997 | ||
998 | #define _CHV_CMN_DW13_CH0 0x8134 | |
999 | #define _CHV_CMN_DW0_CH1 0x8080 | |
1000 | #define DPIO_CHV_S1_DIV_SHIFT 21 | |
1001 | #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ | |
1002 | #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ | |
1003 | #define DPIO_CHV_K_DIV_SHIFT 4 | |
1004 | #define DPIO_PLL_FREQLOCK (1 << 1) | |
1005 | #define DPIO_PLL_LOCK (1 << 0) | |
1006 | #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) | |
1007 | ||
1008 | #define _CHV_CMN_DW14_CH0 0x8138 | |
1009 | #define _CHV_CMN_DW1_CH1 0x8084 | |
1010 | #define DPIO_AFC_RECAL (1 << 14) | |
1011 | #define DPIO_DCLKP_EN (1 << 13) | |
1012 | #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ | |
1013 | #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ | |
1014 | #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ | |
1015 | #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ | |
1016 | #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ | |
1017 | #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ | |
1018 | #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ | |
1019 | #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ | |
1020 | #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) | |
1021 | ||
1022 | #define _CHV_CMN_DW19_CH0 0x814c | |
1023 | #define _CHV_CMN_DW6_CH1 0x8098 | |
1024 | #define CHV_CMN_USEDCLKCHANNEL (1 << 13) | |
1025 | #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) | |
1026 | ||
1027 | #define CHV_CMN_DW30 0x8178 | |
1028 | #define DPIO_LRC_BYPASS (1 << 3) | |
1029 | ||
1030 | #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ | |
1031 | (lane) * 0x200 + (offset)) | |
1032 | ||
1033 | #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) | |
1034 | #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) | |
1035 | #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) | |
1036 | #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) | |
1037 | #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) | |
1038 | #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) | |
1039 | #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) | |
1040 | #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) | |
1041 | #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) | |
1042 | #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) | |
1043 | #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) | |
1044 | #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) | |
1045 | #define DPIO_FRC_LATENCY_SHFIT 8 | |
1046 | #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) | |
1047 | #define DPIO_UPAR_SHIFT 30 | |
1048 | /* | |
1049 | * Fence registers | |
1050 | */ | |
1051 | #define FENCE_REG_830_0 0x2000 | |
1052 | #define FENCE_REG_945_8 0x3000 | |
1053 | #define I830_FENCE_START_MASK 0x07f80000 | |
1054 | #define I830_FENCE_TILING_Y_SHIFT 12 | |
1055 | #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) | |
1056 | #define I830_FENCE_PITCH_SHIFT 4 | |
1057 | #define I830_FENCE_REG_VALID (1<<0) | |
1058 | #define I915_FENCE_MAX_PITCH_VAL 4 | |
1059 | #define I830_FENCE_MAX_PITCH_VAL 6 | |
1060 | #define I830_FENCE_MAX_SIZE_VAL (1<<8) | |
1061 | ||
1062 | #define I915_FENCE_START_MASK 0x0ff00000 | |
1063 | #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) | |
1064 | ||
1065 | #define FENCE_REG_965_0 0x03000 | |
1066 | #define I965_FENCE_PITCH_SHIFT 2 | |
1067 | #define I965_FENCE_TILING_Y_SHIFT 1 | |
1068 | #define I965_FENCE_REG_VALID (1<<0) | |
1069 | #define I965_FENCE_MAX_PITCH_VAL 0x0400 | |
1070 | ||
1071 | #define FENCE_REG_SANDYBRIDGE_0 0x100000 | |
1072 | #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 | |
1073 | #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 | |
1074 | ||
1075 | ||
1076 | /* control register for cpu gtt access */ | |
1077 | #define TILECTL 0x101000 | |
1078 | #define TILECTL_SWZCTL (1 << 0) | |
1079 | #define TILECTL_TLB_PREFETCH_DIS (1 << 2) | |
1080 | #define TILECTL_BACKSNOOP_DIS (1 << 3) | |
1081 | ||
1082 | /* | |
1083 | * Instruction and interrupt control regs | |
1084 | */ | |
1085 | #define PGTBL_CTL 0x02020 | |
1086 | #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ | |
1087 | #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ | |
1088 | #define PGTBL_ER 0x02024 | |
1089 | #define PRB0_BASE (0x2030-0x30) | |
1090 | #define PRB1_BASE (0x2040-0x30) /* 830,gen3 */ | |
1091 | #define PRB2_BASE (0x2050-0x30) /* gen3 */ | |
1092 | #define SRB0_BASE (0x2100-0x30) /* gen2 */ | |
1093 | #define SRB1_BASE (0x2110-0x30) /* gen2 */ | |
1094 | #define SRB2_BASE (0x2120-0x30) /* 830 */ | |
1095 | #define SRB3_BASE (0x2130-0x30) /* 830 */ | |
1096 | #define RENDER_RING_BASE 0x02000 | |
1097 | #define BSD_RING_BASE 0x04000 | |
1098 | #define GEN6_BSD_RING_BASE 0x12000 | |
1099 | #define GEN8_BSD2_RING_BASE 0x1c000 | |
1100 | #define VEBOX_RING_BASE 0x1a000 | |
1101 | #define BLT_RING_BASE 0x22000 | |
1102 | #define RING_TAIL(base) ((base)+0x30) | |
1103 | #define RING_HEAD(base) ((base)+0x34) | |
1104 | #define RING_START(base) ((base)+0x38) | |
1105 | #define RING_CTL(base) ((base)+0x3c) | |
1106 | #define RING_SYNC_0(base) ((base)+0x40) | |
1107 | #define RING_SYNC_1(base) ((base)+0x44) | |
1108 | #define RING_SYNC_2(base) ((base)+0x48) | |
1109 | #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) | |
1110 | #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) | |
1111 | #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE)) | |
1112 | #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) | |
1113 | #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) | |
1114 | #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE)) | |
1115 | #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) | |
1116 | #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) | |
1117 | #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE)) | |
1118 | #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE)) | |
1119 | #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) | |
1120 | #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE)) | |
1121 | #define GEN6_NOSYNC 0 | |
1122 | #define RING_MAX_IDLE(base) ((base)+0x54) | |
1123 | #define RING_HWS_PGA(base) ((base)+0x80) | |
1124 | #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) | |
1125 | ||
1126 | #define GEN7_WR_WATERMARK 0x4028 | |
1127 | #define GEN7_GFX_PRIO_CTRL 0x402C | |
1128 | #define ARB_MODE 0x4030 | |
1129 | #define ARB_MODE_SWIZZLE_SNB (1<<4) | |
1130 | #define ARB_MODE_SWIZZLE_IVB (1<<5) | |
1131 | #define GEN7_GFX_PEND_TLB0 0x4034 | |
1132 | #define GEN7_GFX_PEND_TLB1 0x4038 | |
1133 | /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ | |
1134 | #define GEN7_LRA_LIMITS_BASE 0x403C | |
1135 | #define GEN7_LRA_LIMITS_REG_NUM 13 | |
1136 | #define GEN7_MEDIA_MAX_REQ_COUNT 0x4070 | |
1137 | #define GEN7_GFX_MAX_REQ_COUNT 0x4074 | |
1138 | ||
1139 | #define GAMTARBMODE 0x04a08 | |
1140 | #define ARB_MODE_BWGTLB_DISABLE (1<<9) | |
1141 | #define ARB_MODE_SWIZZLE_BDW (1<<1) | |
1142 | #define RENDER_HWS_PGA_GEN7 (0x04080) | |
1143 | #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) | |
1144 | #define RING_FAULT_GTTSEL_MASK (1<<11) | |
1145 | #define RING_FAULT_SRCID(x) ((x >> 3) & 0xff) | |
1146 | #define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3) | |
1147 | #define RING_FAULT_VALID (1<<0) | |
1148 | #define DONE_REG 0x40b0 | |
1149 | #define GEN8_PRIVATE_PAT 0x40e0 | |
1150 | #define BSD_HWS_PGA_GEN7 (0x04180) | |
1151 | #define BLT_HWS_PGA_GEN7 (0x04280) | |
1152 | #define VEBOX_HWS_PGA_GEN7 (0x04380) | |
1153 | #define RING_ACTHD(base) ((base)+0x74) | |
1154 | #define RING_ACTHD_UDW(base) ((base)+0x5c) | |
1155 | #define RING_NOPID(base) ((base)+0x94) | |
1156 | #define RING_IMR(base) ((base)+0xa8) | |
1157 | #define RING_HWSTAM(base) ((base)+0x98) | |
1158 | #define RING_TIMESTAMP(base) ((base)+0x358) | |
1159 | #define TAIL_ADDR 0x001FFFF8 | |
1160 | #define HEAD_WRAP_COUNT 0xFFE00000 | |
1161 | #define HEAD_WRAP_ONE 0x00200000 | |
1162 | #define HEAD_ADDR 0x001FFFFC | |
1163 | #define RING_NR_PAGES 0x001FF000 | |
1164 | #define RING_REPORT_MASK 0x00000006 | |
1165 | #define RING_REPORT_64K 0x00000002 | |
1166 | #define RING_REPORT_128K 0x00000004 | |
1167 | #define RING_NO_REPORT 0x00000000 | |
1168 | #define RING_VALID_MASK 0x00000001 | |
1169 | #define RING_VALID 0x00000001 | |
1170 | #define RING_INVALID 0x00000000 | |
1171 | #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ | |
1172 | #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ | |
1173 | #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ | |
1174 | ||
1175 | #define GEN7_TLB_RD_ADDR 0x4700 | |
1176 | ||
1177 | #if 0 | |
1178 | #define PRB0_TAIL 0x02030 | |
1179 | #define PRB0_HEAD 0x02034 | |
1180 | #define PRB0_START 0x02038 | |
1181 | #define PRB0_CTL 0x0203c | |
1182 | #define PRB1_TAIL 0x02040 /* 915+ only */ | |
1183 | #define PRB1_HEAD 0x02044 /* 915+ only */ | |
1184 | #define PRB1_START 0x02048 /* 915+ only */ | |
1185 | #define PRB1_CTL 0x0204c /* 915+ only */ | |
1186 | #endif | |
1187 | #define IPEIR_I965 0x02064 | |
1188 | #define IPEHR_I965 0x02068 | |
1189 | #define INSTDONE_I965 0x0206c | |
1190 | #define GEN7_INSTDONE_1 0x0206c | |
1191 | #define GEN7_SC_INSTDONE 0x07100 | |
1192 | #define GEN7_SAMPLER_INSTDONE 0x0e160 | |
1193 | #define GEN7_ROW_INSTDONE 0x0e164 | |
1194 | #define I915_NUM_INSTDONE_REG 4 | |
1195 | #define RING_IPEIR(base) ((base)+0x64) | |
1196 | #define RING_IPEHR(base) ((base)+0x68) | |
1197 | #define RING_INSTDONE(base) ((base)+0x6c) | |
1198 | #define RING_INSTPS(base) ((base)+0x70) | |
1199 | #define RING_DMA_FADD(base) ((base)+0x78) | |
1200 | #define RING_DMA_FADD_UDW(base) ((base)+0x60) /* gen8+ */ | |
1201 | #define RING_INSTPM(base) ((base)+0xc0) | |
1202 | #define RING_MI_MODE(base) ((base)+0x9c) | |
1203 | #define INSTPS 0x02070 /* 965+ only */ | |
1204 | #define INSTDONE1 0x0207c /* 965+ only */ | |
1205 | #define ACTHD_I965 0x02074 | |
1206 | #define HWS_PGA 0x02080 | |
1207 | #define HWS_ADDRESS_MASK 0xfffff000 | |
1208 | #define HWS_START_ADDRESS_SHIFT 4 | |
1209 | #define PWRCTXA 0x2088 /* 965GM+ only */ | |
1210 | #define PWRCTX_EN (1<<0) | |
1211 | #define IPEIR 0x02088 | |
1212 | #define IPEHR 0x0208c | |
1213 | #define INSTDONE 0x02090 | |
1214 | #define NOPID 0x02094 | |
1215 | #define HWSTAM 0x02098 | |
1216 | #define DMA_FADD_I8XX 0x020d0 | |
1217 | #define RING_BBSTATE(base) ((base)+0x110) | |
1218 | #define RING_BBADDR(base) ((base)+0x140) | |
1219 | #define RING_BBADDR_UDW(base) ((base)+0x168) /* gen8+ */ | |
1220 | ||
1221 | #define ERROR_GEN6 0x040a0 | |
1222 | #define GEN7_ERR_INT 0x44040 | |
1223 | #define ERR_INT_POISON (1<<31) | |
1224 | #define ERR_INT_MMIO_UNCLAIMED (1<<13) | |
1225 | #define ERR_INT_PIPE_CRC_DONE_C (1<<8) | |
1226 | #define ERR_INT_FIFO_UNDERRUN_C (1<<6) | |
1227 | #define ERR_INT_PIPE_CRC_DONE_B (1<<5) | |
1228 | #define ERR_INT_FIFO_UNDERRUN_B (1<<3) | |
1229 | #define ERR_INT_PIPE_CRC_DONE_A (1<<2) | |
1230 | #define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3)) | |
1231 | #define ERR_INT_FIFO_UNDERRUN_A (1<<0) | |
1232 | #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3)) | |
1233 | ||
1234 | #define FPGA_DBG 0x42300 | |
1235 | #define FPGA_DBG_RM_NOCLAIM (1<<31) | |
1236 | ||
1237 | #define DERRMR 0x44050 | |
1238 | /* Note that HBLANK events are reserved on bdw+ */ | |
1239 | #define DERRMR_PIPEA_SCANLINE (1<<0) | |
1240 | #define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1) | |
1241 | #define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2) | |
1242 | #define DERRMR_PIPEA_VBLANK (1<<3) | |
1243 | #define DERRMR_PIPEA_HBLANK (1<<5) | |
1244 | #define DERRMR_PIPEB_SCANLINE (1<<8) | |
1245 | #define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9) | |
1246 | #define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10) | |
1247 | #define DERRMR_PIPEB_VBLANK (1<<11) | |
1248 | #define DERRMR_PIPEB_HBLANK (1<<13) | |
1249 | /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ | |
1250 | #define DERRMR_PIPEC_SCANLINE (1<<14) | |
1251 | #define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15) | |
1252 | #define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20) | |
1253 | #define DERRMR_PIPEC_VBLANK (1<<21) | |
1254 | #define DERRMR_PIPEC_HBLANK (1<<22) | |
1255 | ||
1256 | ||
1257 | /* GM45+ chicken bits -- debug workaround bits that may be required | |
1258 | * for various sorts of correct behavior. The top 16 bits of each are | |
1259 | * the enables for writing to the corresponding low bit. | |
1260 | */ | |
1261 | #define _3D_CHICKEN 0x02084 | |
1262 | #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) | |
1263 | #define _3D_CHICKEN2 0x0208c | |
1264 | /* Disables pipelining of read flushes past the SF-WIZ interface. | |
1265 | * Required on all Ironlake steppings according to the B-Spec, but the | |
1266 | * particular danger of not doing so is not specified. | |
1267 | */ | |
1268 | # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) | |
1269 | #define _3D_CHICKEN3 0x02090 | |
1270 | #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) | |
1271 | #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) | |
1272 | #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */ | |
1273 | #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */ | |
1274 | ||
1275 | #define MI_MODE 0x0209c | |
1276 | # define VS_TIMER_DISPATCH (1 << 6) | |
1277 | # define MI_FLUSH_ENABLE (1 << 12) | |
1278 | # define ASYNC_FLIP_PERF_DISABLE (1 << 14) | |
1279 | # define MODE_IDLE (1 << 9) | |
1280 | # define STOP_RING (1 << 8) | |
1281 | ||
1282 | #define GEN6_GT_MODE 0x20d0 | |
1283 | #define GEN7_GT_MODE 0x7008 | |
1284 | #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7)) | |
1285 | #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0) | |
1286 | #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1) | |
1287 | #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) | |
1288 | #define GEN6_WIZ_HASHING_MASK (GEN6_WIZ_HASHING(1, 1) << 16) | |
1289 | #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) | |
1290 | ||
1291 | #define GFX_MODE 0x02520 | |
1292 | #define GFX_MODE_GEN7 0x0229c | |
1293 | #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c) | |
1294 | #define GFX_RUN_LIST_ENABLE (1<<15) | |
1295 | #define GFX_TLB_INVALIDATE_EXPLICIT (1<<13) | |
1296 | #define GFX_SURFACE_FAULT_ENABLE (1<<12) | |
1297 | #define GFX_REPLAY_MODE (1<<11) | |
1298 | #define GFX_PSMI_GRANULARITY (1<<10) | |
1299 | #define GFX_PPGTT_ENABLE (1<<9) | |
1300 | ||
1301 | #define VLV_DISPLAY_BASE 0x180000 | |
1302 | #define VLV_MIPI_BASE VLV_DISPLAY_BASE | |
1303 | ||
1304 | #define VLV_GU_CTL0 (VLV_DISPLAY_BASE + 0x2030) | |
1305 | #define VLV_GU_CTL1 (VLV_DISPLAY_BASE + 0x2034) | |
1306 | #define SCPD0 0x0209c /* 915+ only */ | |
1307 | #define IER 0x020a0 | |
1308 | #define IIR 0x020a4 | |
1309 | #define IMR 0x020a8 | |
1310 | #define ISR 0x020ac | |
1311 | #define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060) | |
1312 | #define GINT_DIS (1<<22) | |
1313 | #define GCFG_DIS (1<<8) | |
1314 | #define VLV_GUNIT_CLOCK_GATE2 (VLV_DISPLAY_BASE + 0x2064) | |
1315 | #define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084) | |
1316 | #define VLV_IER (VLV_DISPLAY_BASE + 0x20a0) | |
1317 | #define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4) | |
1318 | #define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8) | |
1319 | #define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac) | |
1320 | #define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120) | |
1321 | #define VLV_PCBR_ADDR_SHIFT 12 | |
1322 | ||
1323 | #define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */ | |
1324 | #define EIR 0x020b0 | |
1325 | #define EMR 0x020b4 | |
1326 | #define ESR 0x020b8 | |
1327 | #define GM45_ERROR_PAGE_TABLE (1<<5) | |
1328 | #define GM45_ERROR_MEM_PRIV (1<<4) | |
1329 | #define I915_ERROR_PAGE_TABLE (1<<4) | |
1330 | #define GM45_ERROR_CP_PRIV (1<<3) | |
1331 | #define I915_ERROR_MEMORY_REFRESH (1<<1) | |
1332 | #define I915_ERROR_INSTRUCTION (1<<0) | |
1333 | #define INSTPM 0x020c0 | |
1334 | #define INSTPM_SELF_EN (1<<12) /* 915GM only */ | |
1335 | #define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts | |
1336 | will not assert AGPBUSY# and will only | |
1337 | be delivered when out of C3. */ | |
1338 | #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ | |
1339 | #define INSTPM_TLB_INVALIDATE (1<<9) | |
1340 | #define INSTPM_SYNC_FLUSH (1<<5) | |
1341 | #define ACTHD 0x020c8 | |
1342 | #define MEM_MODE 0x020cc | |
1343 | #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */ | |
1344 | #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */ | |
1345 | #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */ | |
1346 | #define FW_BLC 0x020d8 | |
1347 | #define FW_BLC2 0x020dc | |
1348 | #define FW_BLC_SELF 0x020e0 /* 915+ only */ | |
1349 | #define FW_BLC_SELF_EN_MASK (1<<31) | |
1350 | #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ | |
1351 | #define FW_BLC_SELF_EN (1<<15) /* 945 only */ | |
1352 | #define MM_BURST_LENGTH 0x00700000 | |
1353 | #define MM_FIFO_WATERMARK 0x0001F000 | |
1354 | #define LM_BURST_LENGTH 0x00000700 | |
1355 | #define LM_FIFO_WATERMARK 0x0000001F | |
1356 | #define MI_ARB_STATE 0x020e4 /* 915+ only */ | |
1357 | ||
1358 | /* Make render/texture TLB fetches lower priorty than associated data | |
1359 | * fetches. This is not turned on by default | |
1360 | */ | |
1361 | #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) | |
1362 | ||
1363 | /* Isoch request wait on GTT enable (Display A/B/C streams). | |
1364 | * Make isoch requests stall on the TLB update. May cause | |
1365 | * display underruns (test mode only) | |
1366 | */ | |
1367 | #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) | |
1368 | ||
1369 | /* Block grant count for isoch requests when block count is | |
1370 | * set to a finite value. | |
1371 | */ | |
1372 | #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) | |
1373 | #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ | |
1374 | #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ | |
1375 | #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ | |
1376 | #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ | |
1377 | ||
1378 | /* Enable render writes to complete in C2/C3/C4 power states. | |
1379 | * If this isn't enabled, render writes are prevented in low | |
1380 | * power states. That seems bad to me. | |
1381 | */ | |
1382 | #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) | |
1383 | ||
1384 | /* This acknowledges an async flip immediately instead | |
1385 | * of waiting for 2TLB fetches. | |
1386 | */ | |
1387 | #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) | |
1388 | ||
1389 | /* Enables non-sequential data reads through arbiter | |
1390 | */ | |
1391 | #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) | |
1392 | ||
1393 | /* Disable FSB snooping of cacheable write cycles from binner/render | |
1394 | * command stream | |
1395 | */ | |
1396 | #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) | |
1397 | ||
1398 | /* Arbiter time slice for non-isoch streams */ | |
1399 | #define MI_ARB_TIME_SLICE_MASK (7 << 5) | |
1400 | #define MI_ARB_TIME_SLICE_1 (0 << 5) | |
1401 | #define MI_ARB_TIME_SLICE_2 (1 << 5) | |
1402 | #define MI_ARB_TIME_SLICE_4 (2 << 5) | |
1403 | #define MI_ARB_TIME_SLICE_6 (3 << 5) | |
1404 | #define MI_ARB_TIME_SLICE_8 (4 << 5) | |
1405 | #define MI_ARB_TIME_SLICE_10 (5 << 5) | |
1406 | #define MI_ARB_TIME_SLICE_14 (6 << 5) | |
1407 | #define MI_ARB_TIME_SLICE_16 (7 << 5) | |
1408 | ||
1409 | /* Low priority grace period page size */ | |
1410 | #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ | |
1411 | #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) | |
1412 | ||
1413 | /* Disable display A/B trickle feed */ | |
1414 | #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) | |
1415 | ||
1416 | /* Set display plane priority */ | |
1417 | #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ | |
1418 | #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ | |
1419 | ||
1420 | #define MI_STATE 0x020e4 /* gen2 only */ | |
1421 | #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ | |
1422 | #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ | |
1423 | ||
1424 | #define CACHE_MODE_0 0x02120 /* 915+ only */ | |
1425 | #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8) | |
1426 | #define CM0_IZ_OPT_DISABLE (1<<6) | |
1427 | #define CM0_ZR_OPT_DISABLE (1<<5) | |
1428 | #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) | |
1429 | #define CM0_DEPTH_EVICT_DISABLE (1<<4) | |
1430 | #define CM0_COLOR_EVICT_DISABLE (1<<3) | |
1431 | #define CM0_DEPTH_WRITE_DISABLE (1<<1) | |
1432 | #define CM0_RC_OP_FLUSH_DISABLE (1<<0) | |
1433 | #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ | |
1434 | #define GFX_FLSH_CNTL_GEN6 0x101008 | |
1435 | #define GFX_FLSH_CNTL_EN (1<<0) | |
1436 | #define ECOSKPD 0x021d0 | |
1437 | #define ECO_GATING_CX_ONLY (1<<3) | |
1438 | #define ECO_FLIP_DONE (1<<0) | |
1439 | ||
1440 | #define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */ | |
1441 | #define RC_OP_FLUSH_ENABLE (1<<0) | |
1442 | #define HIZ_RAW_STALL_OPT_DISABLE (1<<2) | |
1443 | #define CACHE_MODE_1 0x7004 /* IVB+ */ | |
1444 | #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) | |
1445 | #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6) | |
1446 | ||
1447 | #define GEN6_BLITTER_ECOSKPD 0x221d0 | |
1448 | #define GEN6_BLITTER_LOCK_SHIFT 16 | |
1449 | #define GEN6_BLITTER_FBC_NOTIFY (1<<3) | |
1450 | ||
1451 | #define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050 | |
1452 | #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12) | |
1453 | #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) | |
1454 | ||
1455 | #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 | |
1456 | #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) | |
1457 | #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2) | |
1458 | #define GEN6_BSD_SLEEP_INDICATOR (1 << 3) | |
1459 | #define GEN6_BSD_GO_INDICATOR (1 << 4) | |
1460 | ||
1461 | /* On modern GEN architectures interrupt control consists of two sets | |
1462 | * of registers. The first set pertains to the ring generating the | |
1463 | * interrupt. The second control is for the functional block generating the | |
1464 | * interrupt. These are PM, GT, DE, etc. | |
1465 | * | |
1466 | * Luckily *knocks on wood* all the ring interrupt bits match up with the | |
1467 | * GT interrupt bits, so we don't need to duplicate the defines. | |
1468 | * | |
1469 | * These defines should cover us well from SNB->HSW with minor exceptions | |
1470 | * it can also work on ILK. | |
1471 | */ | |
1472 | #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) | |
1473 | #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) | |
1474 | #define GT_BLT_USER_INTERRUPT (1 << 22) | |
1475 | #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) | |
1476 | #define GT_BSD_USER_INTERRUPT (1 << 12) | |
1477 | #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ | |
1478 | #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) | |
1479 | #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ | |
1480 | #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) | |
1481 | #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3) | |
1482 | #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) | |
1483 | #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) | |
1484 | #define GT_RENDER_USER_INTERRUPT (1 << 0) | |
1485 | ||
1486 | #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ | |
1487 | #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ | |
1488 | ||
1489 | #define GT_PARITY_ERROR(dev) \ | |
1490 | (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ | |
1491 | (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) | |
1492 | ||
1493 | /* These are all the "old" interrupts */ | |
1494 | #define ILK_BSD_USER_INTERRUPT (1<<5) | |
1495 | ||
1496 | #define I915_PM_INTERRUPT (1<<31) | |
1497 | #define I915_ISP_INTERRUPT (1<<22) | |
1498 | #define I915_LPE_PIPE_B_INTERRUPT (1<<21) | |
1499 | #define I915_LPE_PIPE_A_INTERRUPT (1<<20) | |
1500 | #define I915_MIPIC_INTERRUPT (1<<19) | |
1501 | #define I915_MIPIA_INTERRUPT (1<<18) | |
1502 | #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) | |
1503 | #define I915_DISPLAY_PORT_INTERRUPT (1<<17) | |
1504 | #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16) | |
1505 | #define I915_MASTER_ERROR_INTERRUPT (1<<15) | |
1506 | #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) | |
1507 | #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14) | |
1508 | #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ | |
1509 | #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13) | |
1510 | #define I915_HWB_OOM_INTERRUPT (1<<13) | |
1511 | #define I915_LPE_PIPE_C_INTERRUPT (1<<12) | |
1512 | #define I915_SYNC_STATUS_INTERRUPT (1<<12) | |
1513 | #define I915_MISC_INTERRUPT (1<<11) | |
1514 | #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) | |
1515 | #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10) | |
1516 | #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) | |
1517 | #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9) | |
1518 | #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) | |
1519 | #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8) | |
1520 | #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) | |
1521 | #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) | |
1522 | #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) | |
1523 | #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) | |
1524 | #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) | |
1525 | #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3) | |
1526 | #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2) | |
1527 | #define I915_DEBUG_INTERRUPT (1<<2) | |
1528 | #define I915_WINVALID_INTERRUPT (1<<1) | |
1529 | #define I915_USER_INTERRUPT (1<<1) | |
1530 | #define I915_ASLE_INTERRUPT (1<<0) | |
1531 | #define I915_BSD_USER_INTERRUPT (1<<25) | |
1532 | ||
1533 | #define GEN6_BSD_RNCID 0x12198 | |
1534 | ||
1535 | #define GEN7_FF_THREAD_MODE 0x20a0 | |
1536 | #define GEN7_FF_SCHED_MASK 0x0077070 | |
1537 | #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) | |
1538 | #define GEN7_FF_TS_SCHED_HS1 (0x5<<16) | |
1539 | #define GEN7_FF_TS_SCHED_HS0 (0x3<<16) | |
1540 | #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) | |
1541 | #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */ | |
1542 | #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) | |
1543 | #define GEN7_FF_VS_SCHED_HS1 (0x5<<12) | |
1544 | #define GEN7_FF_VS_SCHED_HS0 (0x3<<12) | |
1545 | #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */ | |
1546 | #define GEN7_FF_VS_SCHED_HW (0x0<<12) | |
1547 | #define GEN7_FF_DS_SCHED_HS1 (0x5<<4) | |
1548 | #define GEN7_FF_DS_SCHED_HS0 (0x3<<4) | |
1549 | #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */ | |
1550 | #define GEN7_FF_DS_SCHED_HW (0x0<<4) | |
1551 | ||
1552 | /* | |
1553 | * Framebuffer compression (915+ only) | |
1554 | */ | |
1555 | ||
1556 | #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ | |
1557 | #define FBC_LL_BASE 0x03204 /* 4k page aligned */ | |
1558 | #define FBC_CONTROL 0x03208 | |
1559 | #define FBC_CTL_EN (1<<31) | |
1560 | #define FBC_CTL_PERIODIC (1<<30) | |
1561 | #define FBC_CTL_INTERVAL_SHIFT (16) | |
1562 | #define FBC_CTL_UNCOMPRESSIBLE (1<<14) | |
1563 | #define FBC_CTL_C3_IDLE (1<<13) | |
1564 | #define FBC_CTL_STRIDE_SHIFT (5) | |
1565 | #define FBC_CTL_FENCENO_SHIFT (0) | |
1566 | #define FBC_COMMAND 0x0320c | |
1567 | #define FBC_CMD_COMPRESS (1<<0) | |
1568 | #define FBC_STATUS 0x03210 | |
1569 | #define FBC_STAT_COMPRESSING (1<<31) | |
1570 | #define FBC_STAT_COMPRESSED (1<<30) | |
1571 | #define FBC_STAT_MODIFIED (1<<29) | |
1572 | #define FBC_STAT_CURRENT_LINE_SHIFT (0) | |
1573 | #define FBC_CONTROL2 0x03214 | |
1574 | #define FBC_CTL_FENCE_DBL (0<<4) | |
1575 | #define FBC_CTL_IDLE_IMM (0<<2) | |
1576 | #define FBC_CTL_IDLE_FULL (1<<2) | |
1577 | #define FBC_CTL_IDLE_LINE (2<<2) | |
1578 | #define FBC_CTL_IDLE_DEBUG (3<<2) | |
1579 | #define FBC_CTL_CPU_FENCE (1<<1) | |
1580 | #define FBC_CTL_PLANE(plane) ((plane)<<0) | |
1581 | #define FBC_FENCE_OFF 0x03218 /* BSpec typo has 321Bh */ | |
1582 | #define FBC_TAG 0x03300 | |
1583 | ||
1584 | #define FBC_LL_SIZE (1536) | |
1585 | ||
1586 | /* Framebuffer compression for GM45+ */ | |
1587 | #define DPFC_CB_BASE 0x3200 | |
1588 | #define DPFC_CONTROL 0x3208 | |
1589 | #define DPFC_CTL_EN (1<<31) | |
1590 | #define DPFC_CTL_PLANE(plane) ((plane)<<30) | |
1591 | #define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29) | |
1592 | #define DPFC_CTL_FENCE_EN (1<<29) | |
1593 | #define IVB_DPFC_CTL_FENCE_EN (1<<28) | |
1594 | #define DPFC_CTL_PERSISTENT_MODE (1<<25) | |
1595 | #define DPFC_SR_EN (1<<10) | |
1596 | #define DPFC_CTL_LIMIT_1X (0<<6) | |
1597 | #define DPFC_CTL_LIMIT_2X (1<<6) | |
1598 | #define DPFC_CTL_LIMIT_4X (2<<6) | |
1599 | #define DPFC_RECOMP_CTL 0x320c | |
1600 | #define DPFC_RECOMP_STALL_EN (1<<27) | |
1601 | #define DPFC_RECOMP_STALL_WM_SHIFT (16) | |
1602 | #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) | |
1603 | #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) | |
1604 | #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) | |
1605 | #define DPFC_STATUS 0x3210 | |
1606 | #define DPFC_INVAL_SEG_SHIFT (16) | |
1607 | #define DPFC_INVAL_SEG_MASK (0x07ff0000) | |
1608 | #define DPFC_COMP_SEG_SHIFT (0) | |
1609 | #define DPFC_COMP_SEG_MASK (0x000003ff) | |
1610 | #define DPFC_STATUS2 0x3214 | |
1611 | #define DPFC_FENCE_YOFF 0x3218 | |
1612 | #define DPFC_CHICKEN 0x3224 | |
1613 | #define DPFC_HT_MODIFY (1<<31) | |
1614 | ||
1615 | /* Framebuffer compression for Ironlake */ | |
1616 | #define ILK_DPFC_CB_BASE 0x43200 | |
1617 | #define ILK_DPFC_CONTROL 0x43208 | |
1618 | #define FBC_CTL_FALSE_COLOR (1<<10) | |
1619 | /* The bit 28-8 is reserved */ | |
1620 | #define DPFC_RESERVED (0x1FFFFF00) | |
1621 | #define ILK_DPFC_RECOMP_CTL 0x4320c | |
1622 | #define ILK_DPFC_STATUS 0x43210 | |
1623 | #define ILK_DPFC_FENCE_YOFF 0x43218 | |
1624 | #define ILK_DPFC_CHICKEN 0x43224 | |
1625 | #define ILK_FBC_RT_BASE 0x2128 | |
1626 | #define ILK_FBC_RT_VALID (1<<0) | |
1627 | #define SNB_FBC_FRONT_BUFFER (1<<1) | |
1628 | ||
1629 | #define ILK_DISPLAY_CHICKEN1 0x42000 | |
1630 | #define ILK_FBCQ_DIS (1<<22) | |
1631 | #define ILK_PABSTRETCH_DIS (1<<21) | |
1632 | ||
1633 | ||
1634 | /* | |
1635 | * Framebuffer compression for Sandybridge | |
1636 | * | |
1637 | * The following two registers are of type GTTMMADR | |
1638 | */ | |
1639 | #define SNB_DPFC_CTL_SA 0x100100 | |
1640 | #define SNB_CPU_FENCE_ENABLE (1<<29) | |
1641 | #define DPFC_CPU_FENCE_OFFSET 0x100104 | |
1642 | ||
1643 | /* Framebuffer compression for Ivybridge */ | |
1644 | #define IVB_FBC_RT_BASE 0x7020 | |
1645 | ||
1646 | #define IPS_CTL 0x43408 | |
1647 | #define IPS_ENABLE (1 << 31) | |
1648 | ||
1649 | #define MSG_FBC_REND_STATE 0x50380 | |
1650 | #define FBC_REND_NUKE (1<<2) | |
1651 | #define FBC_REND_CACHE_CLEAN (1<<1) | |
1652 | ||
1653 | /* | |
1654 | * GPIO regs | |
1655 | */ | |
1656 | #define GPIOA 0x5010 | |
1657 | #define GPIOB 0x5014 | |
1658 | #define GPIOC 0x5018 | |
1659 | #define GPIOD 0x501c | |
1660 | #define GPIOE 0x5020 | |
1661 | #define GPIOF 0x5024 | |
1662 | #define GPIOG 0x5028 | |
1663 | #define GPIOH 0x502c | |
1664 | # define GPIO_CLOCK_DIR_MASK (1 << 0) | |
1665 | # define GPIO_CLOCK_DIR_IN (0 << 1) | |
1666 | # define GPIO_CLOCK_DIR_OUT (1 << 1) | |
1667 | # define GPIO_CLOCK_VAL_MASK (1 << 2) | |
1668 | # define GPIO_CLOCK_VAL_OUT (1 << 3) | |
1669 | # define GPIO_CLOCK_VAL_IN (1 << 4) | |
1670 | # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) | |
1671 | # define GPIO_DATA_DIR_MASK (1 << 8) | |
1672 | # define GPIO_DATA_DIR_IN (0 << 9) | |
1673 | # define GPIO_DATA_DIR_OUT (1 << 9) | |
1674 | # define GPIO_DATA_VAL_MASK (1 << 10) | |
1675 | # define GPIO_DATA_VAL_OUT (1 << 11) | |
1676 | # define GPIO_DATA_VAL_IN (1 << 12) | |
1677 | # define GPIO_DATA_PULLUP_DISABLE (1 << 13) | |
1678 | ||
1679 | #define GMBUS0 0x5100 /* clock/port select */ | |
1680 | #define GMBUS_RATE_100KHZ (0<<8) | |
1681 | #define GMBUS_RATE_50KHZ (1<<8) | |
1682 | #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ | |
1683 | #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ | |
1684 | #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ | |
1685 | #define GMBUS_PORT_DISABLED 0 | |
1686 | #define GMBUS_PORT_SSC 1 | |
1687 | #define GMBUS_PORT_VGADDC 2 | |
1688 | #define GMBUS_PORT_PANEL 3 | |
1689 | #define GMBUS_PORT_DPD_CHV 3 /* HDMID_CHV */ | |
1690 | #define GMBUS_PORT_DPC 4 /* HDMIC */ | |
1691 | #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ | |
1692 | #define GMBUS_PORT_DPD 6 /* HDMID */ | |
1693 | #define GMBUS_PORT_RESERVED 7 /* 7 reserved */ | |
1694 | #define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) | |
1695 | #define GMBUS1 0x5104 /* command/status */ | |
1696 | #define GMBUS_SW_CLR_INT (1<<31) | |
1697 | #define GMBUS_SW_RDY (1<<30) | |
1698 | #define GMBUS_ENT (1<<29) /* enable timeout */ | |
1699 | #define GMBUS_CYCLE_NONE (0<<25) | |
1700 | #define GMBUS_CYCLE_WAIT (1<<25) | |
1701 | #define GMBUS_CYCLE_INDEX (2<<25) | |
1702 | #define GMBUS_CYCLE_STOP (4<<25) | |
1703 | #define GMBUS_BYTE_COUNT_SHIFT 16 | |
1704 | #define GMBUS_SLAVE_INDEX_SHIFT 8 | |
1705 | #define GMBUS_SLAVE_ADDR_SHIFT 1 | |
1706 | #define GMBUS_SLAVE_READ (1<<0) | |
1707 | #define GMBUS_SLAVE_WRITE (0<<0) | |
1708 | #define GMBUS2 0x5108 /* status */ | |
1709 | #define GMBUS_INUSE (1<<15) | |
1710 | #define GMBUS_HW_WAIT_PHASE (1<<14) | |
1711 | #define GMBUS_STALL_TIMEOUT (1<<13) | |
1712 | #define GMBUS_INT (1<<12) | |
1713 | #define GMBUS_HW_RDY (1<<11) | |
1714 | #define GMBUS_SATOER (1<<10) | |
1715 | #define GMBUS_ACTIVE (1<<9) | |
1716 | #define GMBUS3 0x510c /* data buffer bytes 3-0 */ | |
1717 | #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ | |
1718 | #define GMBUS_SLAVE_TIMEOUT_EN (1<<4) | |
1719 | #define GMBUS_NAK_EN (1<<3) | |
1720 | #define GMBUS_IDLE_EN (1<<2) | |
1721 | #define GMBUS_HW_WAIT_EN (1<<1) | |
1722 | #define GMBUS_HW_RDY_EN (1<<0) | |
1723 | #define GMBUS5 0x5120 /* byte index */ | |
1724 | #define GMBUS_2BYTE_INDEX_EN (1<<31) | |
1725 | ||
1726 | /* | |
1727 | * Clock control & power management | |
1728 | */ | |
1729 | #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014) | |
1730 | #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018) | |
1731 | #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030) | |
1732 | #define DPLL(pipe) _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) | |
1733 | ||
1734 | #define VGA0 0x6000 | |
1735 | #define VGA1 0x6004 | |
1736 | #define VGA_PD 0x6010 | |
1737 | #define VGA0_PD_P2_DIV_4 (1 << 7) | |
1738 | #define VGA0_PD_P1_DIV_2 (1 << 5) | |
1739 | #define VGA0_PD_P1_SHIFT 0 | |
1740 | #define VGA0_PD_P1_MASK (0x1f << 0) | |
1741 | #define VGA1_PD_P2_DIV_4 (1 << 15) | |
1742 | #define VGA1_PD_P1_DIV_2 (1 << 13) | |
1743 | #define VGA1_PD_P1_SHIFT 8 | |
1744 | #define VGA1_PD_P1_MASK (0x1f << 8) | |
1745 | #define DPLL_VCO_ENABLE (1 << 31) | |
1746 | #define DPLL_SDVO_HIGH_SPEED (1 << 30) | |
1747 | #define DPLL_DVO_2X_MODE (1 << 30) | |
1748 | #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) | |
1749 | #define DPLL_SYNCLOCK_ENABLE (1 << 29) | |
1750 | #define DPLL_REFA_CLK_ENABLE_VLV (1 << 29) | |
1751 | #define DPLL_VGA_MODE_DIS (1 << 28) | |
1752 | #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ | |
1753 | #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ | |
1754 | #define DPLL_MODE_MASK (3 << 26) | |
1755 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ | |
1756 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ | |
1757 | #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ | |
1758 | #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ | |
1759 | #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ | |
1760 | #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ | |
1761 | #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ | |
1762 | #define DPLL_LOCK_VLV (1<<15) | |
1763 | #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14) | |
1764 | #define DPLL_INTEGRATED_CLOCK_VLV (1<<13) | |
1765 | #define DPLL_SSC_REF_CLOCK_CHV (1<<13) | |
1766 | #define DPLL_PORTC_READY_MASK (0xf << 4) | |
1767 | #define DPLL_PORTB_READY_MASK (0xf) | |
1768 | ||
1769 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 | |
1770 | ||
1771 | /* Additional CHV pll/phy registers */ | |
1772 | #define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240) | |
1773 | #define DPLL_PORTD_READY_MASK (0xf) | |
1774 | #define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100) | |
1775 | #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) | |
1776 | #define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104) | |
1777 | #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30)) | |
1778 | ||
1779 | /* | |
1780 | * The i830 generation, in LVDS mode, defines P1 as the bit number set within | |
1781 | * this field (only one bit may be set). | |
1782 | */ | |
1783 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 | |
1784 | #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 | |
1785 | #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 | |
1786 | /* i830, required in DVO non-gang */ | |
1787 | #define PLL_P2_DIVIDE_BY_4 (1 << 23) | |
1788 | #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ | |
1789 | #define PLL_REF_INPUT_DREFCLK (0 << 13) | |
1790 | #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ | |
1791 | #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ | |
1792 | #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) | |
1793 | #define PLL_REF_INPUT_MASK (3 << 13) | |
1794 | #define PLL_LOAD_PULSE_PHASE_SHIFT 9 | |
1795 | /* Ironlake */ | |
1796 | # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 | |
1797 | # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) | |
1798 | # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) | |
1799 | # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 | |
1800 | # define DPLL_FPA1_P1_POST_DIV_MASK 0xff | |
1801 | ||
1802 | /* | |
1803 | * Parallel to Serial Load Pulse phase selection. | |
1804 | * Selects the phase for the 10X DPLL clock for the PCIe | |
1805 | * digital display port. The range is 4 to 13; 10 or more | |
1806 | * is just a flip delay. The default is 6 | |
1807 | */ | |
1808 | #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) | |
1809 | #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) | |
1810 | /* | |
1811 | * SDVO multiplier for 945G/GM. Not used on 965. | |
1812 | */ | |
1813 | #define SDVO_MULTIPLIER_MASK 0x000000ff | |
1814 | #define SDVO_MULTIPLIER_SHIFT_HIRES 4 | |
1815 | #define SDVO_MULTIPLIER_SHIFT_VGA 0 | |
1816 | ||
1817 | #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c) | |
1818 | #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020) | |
1819 | #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c) | |
1820 | #define DPLL_MD(pipe) _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) | |
1821 | ||
1822 | /* | |
1823 | * UDI pixel divider, controlling how many pixels are stuffed into a packet. | |
1824 | * | |
1825 | * Value is pixels minus 1. Must be set to 1 pixel for SDVO. | |
1826 | */ | |
1827 | #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 | |
1828 | #define DPLL_MD_UDI_DIVIDER_SHIFT 24 | |
1829 | /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ | |
1830 | #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 | |
1831 | #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 | |
1832 | /* | |
1833 | * SDVO/UDI pixel multiplier. | |
1834 | * | |
1835 | * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus | |
1836 | * clock rate is 10 times the DPLL clock. At low resolution/refresh rate | |
1837 | * modes, the bus rate would be below the limits, so SDVO allows for stuffing | |
1838 | * dummy bytes in the datastream at an increased clock rate, with both sides of | |
1839 | * the link knowing how many bytes are fill. | |
1840 | * | |
1841 | * So, for a mode with a dotclock of 65Mhz, we would want to double the clock | |
1842 | * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be | |
1843 | * set to 130Mhz, and the SDVO multiplier set to 2x in this register and | |
1844 | * through an SDVO command. | |
1845 | * | |
1846 | * This register field has values of multiplication factor minus 1, with | |
1847 | * a maximum multiplier of 5 for SDVO. | |
1848 | */ | |
1849 | #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 | |
1850 | #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 | |
1851 | /* | |
1852 | * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. | |
1853 | * This best be set to the default value (3) or the CRT won't work. No, | |
1854 | * I don't entirely understand what this does... | |
1855 | */ | |
1856 | #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f | |
1857 | #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 | |
1858 | ||
1859 | #define _FPA0 0x06040 | |
1860 | #define _FPA1 0x06044 | |
1861 | #define _FPB0 0x06048 | |
1862 | #define _FPB1 0x0604c | |
1863 | #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0) | |
1864 | #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1) | |
1865 | #define FP_N_DIV_MASK 0x003f0000 | |
1866 | #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 | |
1867 | #define FP_N_DIV_SHIFT 16 | |
1868 | #define FP_M1_DIV_MASK 0x00003f00 | |
1869 | #define FP_M1_DIV_SHIFT 8 | |
1870 | #define FP_M2_DIV_MASK 0x0000003f | |
1871 | #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff | |
1872 | #define FP_M2_DIV_SHIFT 0 | |
1873 | #define DPLL_TEST 0x606c | |
1874 | #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) | |
1875 | #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) | |
1876 | #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) | |
1877 | #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) | |
1878 | #define DPLLB_TEST_N_BYPASS (1 << 19) | |
1879 | #define DPLLB_TEST_M_BYPASS (1 << 18) | |
1880 | #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) | |
1881 | #define DPLLA_TEST_N_BYPASS (1 << 3) | |
1882 | #define DPLLA_TEST_M_BYPASS (1 << 2) | |
1883 | #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) | |
1884 | #define D_STATE 0x6104 | |
1885 | #define DSTATE_GFX_RESET_I830 (1<<6) | |
1886 | #define DSTATE_PLL_D3_OFF (1<<3) | |
1887 | #define DSTATE_GFX_CLOCK_GATING (1<<1) | |
1888 | #define DSTATE_DOT_CLOCK_GATING (1<<0) | |
1889 | #define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200) | |
1890 | # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ | |
1891 | # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ | |
1892 | # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ | |
1893 | # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ | |
1894 | # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ | |
1895 | # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ | |
1896 | # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ | |
1897 | # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ | |
1898 | # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ | |
1899 | # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ | |
1900 | # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ | |
1901 | # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ | |
1902 | # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ | |
1903 | # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ | |
1904 | # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ | |
1905 | # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ | |
1906 | # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ | |
1907 | # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ | |
1908 | # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ | |
1909 | # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) | |
1910 | # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) | |
1911 | # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) | |
1912 | # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) | |
1913 | # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ | |
1914 | # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ | |
1915 | # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ | |
1916 | # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) | |
1917 | # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) | |
1918 | /* | |
1919 | * This bit must be set on the 830 to prevent hangs when turning off the | |
1920 | * overlay scaler. | |
1921 | */ | |
1922 | # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) | |
1923 | # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) | |
1924 | # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) | |
1925 | # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ | |
1926 | # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ | |
1927 | ||
1928 | #define RENCLK_GATE_D1 0x6204 | |
1929 | # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ | |
1930 | # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ | |
1931 | # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) | |
1932 | # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) | |
1933 | # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) | |
1934 | # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) | |
1935 | # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) | |
1936 | # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) | |
1937 | # define MAG_CLOCK_GATE_DISABLE (1 << 5) | |
1938 | /* This bit must be unset on 855,865 */ | |
1939 | # define MECI_CLOCK_GATE_DISABLE (1 << 4) | |
1940 | # define DCMP_CLOCK_GATE_DISABLE (1 << 3) | |
1941 | # define MEC_CLOCK_GATE_DISABLE (1 << 2) | |
1942 | # define MECO_CLOCK_GATE_DISABLE (1 << 1) | |
1943 | /* This bit must be set on 855,865. */ | |
1944 | # define SV_CLOCK_GATE_DISABLE (1 << 0) | |
1945 | # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) | |
1946 | # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) | |
1947 | # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) | |
1948 | # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) | |
1949 | # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) | |
1950 | # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) | |
1951 | # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) | |
1952 | # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) | |
1953 | # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) | |
1954 | # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) | |
1955 | # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) | |
1956 | # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) | |
1957 | # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) | |
1958 | # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) | |
1959 | # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) | |
1960 | # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) | |
1961 | # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) | |
1962 | ||
1963 | # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) | |
1964 | /* This bit must always be set on 965G/965GM */ | |
1965 | # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) | |
1966 | # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) | |
1967 | # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) | |
1968 | # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) | |
1969 | # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) | |
1970 | # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) | |
1971 | /* This bit must always be set on 965G */ | |
1972 | # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) | |
1973 | # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) | |
1974 | # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) | |
1975 | # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) | |
1976 | # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) | |
1977 | # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) | |
1978 | # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) | |
1979 | # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) | |
1980 | # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) | |
1981 | # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) | |
1982 | # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) | |
1983 | # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) | |
1984 | # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) | |
1985 | # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) | |
1986 | # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) | |
1987 | # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) | |
1988 | # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) | |
1989 | # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) | |
1990 | # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) | |
1991 | ||
1992 | #define RENCLK_GATE_D2 0x6208 | |
1993 | #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) | |
1994 | #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) | |
1995 | #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) | |
1996 | ||
1997 | #define VDECCLK_GATE_D 0x620C /* g4x only */ | |
1998 | #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) | |
1999 | ||
2000 | #define RAMCLK_GATE_D 0x6210 /* CRL only */ | |
2001 | #define DEUC 0x6214 /* CRL only */ | |
2002 | ||
2003 | #define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500) | |
2004 | #define FW_CSPWRDWNEN (1<<15) | |
2005 | ||
2006 | #define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504) | |
2007 | ||
2008 | #define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508) | |
2009 | #define CDCLK_FREQ_SHIFT 4 | |
2010 | #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) | |
2011 | #define CZCLK_FREQ_MASK 0xf | |
2012 | #define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510) | |
2013 | ||
2014 | /* | |
2015 | * Palette regs | |
2016 | */ | |
2017 | #define PALETTE_A_OFFSET 0xa000 | |
2018 | #define PALETTE_B_OFFSET 0xa800 | |
2019 | #define CHV_PALETTE_C_OFFSET 0xc000 | |
2020 | #define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \ | |
2021 | dev_priv->info.display_mmio_offset) | |
2022 | ||
2023 | /* MCH MMIO space */ | |
2024 | ||
2025 | /* | |
2026 | * MCHBAR mirror. | |
2027 | * | |
2028 | * This mirrors the MCHBAR MMIO space whose location is determined by | |
2029 | * device 0 function 0's pci config register 0x44 or 0x48 and matches it in | |
2030 | * every way. It is not accessible from the CP register read instructions. | |
2031 | * | |
2032 | * Starting from Haswell, you can't write registers using the MCHBAR mirror, | |
2033 | * just read. | |
2034 | */ | |
2035 | #define MCHBAR_MIRROR_BASE 0x10000 | |
2036 | ||
2037 | #define MCHBAR_MIRROR_BASE_SNB 0x140000 | |
2038 | ||
2039 | /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ | |
2040 | #define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04) | |
2041 | ||
2042 | /* 915-945 and GM965 MCH register controlling DRAM channel access */ | |
2043 | #define DCC 0x10200 | |
2044 | #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) | |
2045 | #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) | |
2046 | #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) | |
2047 | #define DCC_ADDRESSING_MODE_MASK (3 << 0) | |
2048 | #define DCC_CHANNEL_XOR_DISABLE (1 << 10) | |
2049 | #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) | |
2050 | #define DCC2 0x10204 | |
2051 | #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20) | |
2052 | ||
2053 | /* Pineview MCH register contains DDR3 setting */ | |
2054 | #define CSHRDDR3CTL 0x101a8 | |
2055 | #define CSHRDDR3CTL_DDR3 (1 << 2) | |
2056 | ||
2057 | /* 965 MCH register controlling DRAM channel configuration */ | |
2058 | #define C0DRB3 0x10206 | |
2059 | #define C1DRB3 0x10606 | |
2060 | ||
2061 | /* snb MCH registers for reading the DRAM channel configuration */ | |
2062 | #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004) | |
2063 | #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008) | |
2064 | #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C) | |
2065 | #define MAD_DIMM_ECC_MASK (0x3 << 24) | |
2066 | #define MAD_DIMM_ECC_OFF (0x0 << 24) | |
2067 | #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) | |
2068 | #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) | |
2069 | #define MAD_DIMM_ECC_ON (0x3 << 24) | |
2070 | #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) | |
2071 | #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) | |
2072 | #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ | |
2073 | #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ | |
2074 | #define MAD_DIMM_B_DUAL_RANK (0x1 << 18) | |
2075 | #define MAD_DIMM_A_DUAL_RANK (0x1 << 17) | |
2076 | #define MAD_DIMM_A_SELECT (0x1 << 16) | |
2077 | /* DIMM sizes are in multiples of 256mb. */ | |
2078 | #define MAD_DIMM_B_SIZE_SHIFT 8 | |
2079 | #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) | |
2080 | #define MAD_DIMM_A_SIZE_SHIFT 0 | |
2081 | #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) | |
2082 | ||
2083 | /* snb MCH registers for priority tuning */ | |
2084 | #define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10) | |
2085 | #define MCH_SSKPD_WM0_MASK 0x3f | |
2086 | #define MCH_SSKPD_WM0_VAL 0xc | |
2087 | ||
2088 | #define MCH_SECP_NRG_STTS (MCHBAR_MIRROR_BASE_SNB + 0x592c) | |
2089 | ||
2090 | /* Clocking configuration register */ | |
2091 | #define CLKCFG 0x10c00 | |
2092 | #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ | |
2093 | #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ | |
2094 | #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ | |
2095 | #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ | |
2096 | #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ | |
2097 | #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ | |
2098 | /* Note, below two are guess */ | |
2099 | #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */ | |
2100 | #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */ | |
2101 | #define CLKCFG_FSB_MASK (7 << 0) | |
2102 | #define CLKCFG_MEM_533 (1 << 4) | |
2103 | #define CLKCFG_MEM_667 (2 << 4) | |
2104 | #define CLKCFG_MEM_800 (3 << 4) | |
2105 | #define CLKCFG_MEM_MASK (7 << 4) | |
2106 | ||
2107 | #define TSC1 0x11001 | |
2108 | #define TSE (1<<0) | |
2109 | #define TR1 0x11006 | |
2110 | #define TSFS 0x11020 | |
2111 | #define TSFS_SLOPE_MASK 0x0000ff00 | |
2112 | #define TSFS_SLOPE_SHIFT 8 | |
2113 | #define TSFS_INTR_MASK 0x000000ff | |
2114 | ||
2115 | #define CRSTANDVID 0x11100 | |
2116 | #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ | |
2117 | #define PXVFREQ_PX_MASK 0x7f000000 | |
2118 | #define PXVFREQ_PX_SHIFT 24 | |
2119 | #define VIDFREQ_BASE 0x11110 | |
2120 | #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */ | |
2121 | #define VIDFREQ2 0x11114 | |
2122 | #define VIDFREQ3 0x11118 | |
2123 | #define VIDFREQ4 0x1111c | |
2124 | #define VIDFREQ_P0_MASK 0x1f000000 | |
2125 | #define VIDFREQ_P0_SHIFT 24 | |
2126 | #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 | |
2127 | #define VIDFREQ_P0_CSCLK_SHIFT 20 | |
2128 | #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 | |
2129 | #define VIDFREQ_P0_CRCLK_SHIFT 16 | |
2130 | #define VIDFREQ_P1_MASK 0x00001f00 | |
2131 | #define VIDFREQ_P1_SHIFT 8 | |
2132 | #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 | |
2133 | #define VIDFREQ_P1_CSCLK_SHIFT 4 | |
2134 | #define VIDFREQ_P1_CRCLK_MASK 0x0000000f | |
2135 | #define INTTOEXT_BASE_ILK 0x11300 | |
2136 | #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */ | |
2137 | #define INTTOEXT_MAP3_SHIFT 24 | |
2138 | #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) | |
2139 | #define INTTOEXT_MAP2_SHIFT 16 | |
2140 | #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) | |
2141 | #define INTTOEXT_MAP1_SHIFT 8 | |
2142 | #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) | |
2143 | #define INTTOEXT_MAP0_SHIFT 0 | |
2144 | #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) | |
2145 | #define MEMSWCTL 0x11170 /* Ironlake only */ | |
2146 | #define MEMCTL_CMD_MASK 0xe000 | |
2147 | #define MEMCTL_CMD_SHIFT 13 | |
2148 | #define MEMCTL_CMD_RCLK_OFF 0 | |
2149 | #define MEMCTL_CMD_RCLK_ON 1 | |
2150 | #define MEMCTL_CMD_CHFREQ 2 | |
2151 | #define MEMCTL_CMD_CHVID 3 | |
2152 | #define MEMCTL_CMD_VMMOFF 4 | |
2153 | #define MEMCTL_CMD_VMMON 5 | |
2154 | #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears | |
2155 | when command complete */ | |
2156 | #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ | |
2157 | #define MEMCTL_FREQ_SHIFT 8 | |
2158 | #define MEMCTL_SFCAVM (1<<7) | |
2159 | #define MEMCTL_TGT_VID_MASK 0x007f | |
2160 | #define MEMIHYST 0x1117c | |
2161 | #define MEMINTREN 0x11180 /* 16 bits */ | |
2162 | #define MEMINT_RSEXIT_EN (1<<8) | |
2163 | #define MEMINT_CX_SUPR_EN (1<<7) | |
2164 | #define MEMINT_CONT_BUSY_EN (1<<6) | |
2165 | #define MEMINT_AVG_BUSY_EN (1<<5) | |
2166 | #define MEMINT_EVAL_CHG_EN (1<<4) | |
2167 | #define MEMINT_MON_IDLE_EN (1<<3) | |
2168 | #define MEMINT_UP_EVAL_EN (1<<2) | |
2169 | #define MEMINT_DOWN_EVAL_EN (1<<1) | |
2170 | #define MEMINT_SW_CMD_EN (1<<0) | |
2171 | #define MEMINTRSTR 0x11182 /* 16 bits */ | |
2172 | #define MEM_RSEXIT_MASK 0xc000 | |
2173 | #define MEM_RSEXIT_SHIFT 14 | |
2174 | #define MEM_CONT_BUSY_MASK 0x3000 | |
2175 | #define MEM_CONT_BUSY_SHIFT 12 | |
2176 | #define MEM_AVG_BUSY_MASK 0x0c00 | |
2177 | #define MEM_AVG_BUSY_SHIFT 10 | |
2178 | #define MEM_EVAL_CHG_MASK 0x0300 | |
2179 | #define MEM_EVAL_BUSY_SHIFT 8 | |
2180 | #define MEM_MON_IDLE_MASK 0x00c0 | |
2181 | #define MEM_MON_IDLE_SHIFT 6 | |
2182 | #define MEM_UP_EVAL_MASK 0x0030 | |
2183 | #define MEM_UP_EVAL_SHIFT 4 | |
2184 | #define MEM_DOWN_EVAL_MASK 0x000c | |
2185 | #define MEM_DOWN_EVAL_SHIFT 2 | |
2186 | #define MEM_SW_CMD_MASK 0x0003 | |
2187 | #define MEM_INT_STEER_GFX 0 | |
2188 | #define MEM_INT_STEER_CMR 1 | |
2189 | #define MEM_INT_STEER_SMI 2 | |
2190 | #define MEM_INT_STEER_SCI 3 | |
2191 | #define MEMINTRSTS 0x11184 | |
2192 | #define MEMINT_RSEXIT (1<<7) | |
2193 | #define MEMINT_CONT_BUSY (1<<6) | |
2194 | #define MEMINT_AVG_BUSY (1<<5) | |
2195 | #define MEMINT_EVAL_CHG (1<<4) | |
2196 | #define MEMINT_MON_IDLE (1<<3) | |
2197 | #define MEMINT_UP_EVAL (1<<2) | |
2198 | #define MEMINT_DOWN_EVAL (1<<1) | |
2199 | #define MEMINT_SW_CMD (1<<0) | |
2200 | #define MEMMODECTL 0x11190 | |
2201 | #define MEMMODE_BOOST_EN (1<<31) | |
2202 | #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ | |
2203 | #define MEMMODE_BOOST_FREQ_SHIFT 24 | |
2204 | #define MEMMODE_IDLE_MODE_MASK 0x00030000 | |
2205 | #define MEMMODE_IDLE_MODE_SHIFT 16 | |
2206 | #define MEMMODE_IDLE_MODE_EVAL 0 | |
2207 | #define MEMMODE_IDLE_MODE_CONT 1 | |
2208 | #define MEMMODE_HWIDLE_EN (1<<15) | |
2209 | #define MEMMODE_SWMODE_EN (1<<14) | |
2210 | #define MEMMODE_RCLK_GATE (1<<13) | |
2211 | #define MEMMODE_HW_UPDATE (1<<12) | |
2212 | #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ | |
2213 | #define MEMMODE_FSTART_SHIFT 8 | |
2214 | #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ | |
2215 | #define MEMMODE_FMAX_SHIFT 4 | |
2216 | #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ | |
2217 | #define RCBMAXAVG 0x1119c | |
2218 | #define MEMSWCTL2 0x1119e /* Cantiga only */ | |
2219 | #define SWMEMCMD_RENDER_OFF (0 << 13) | |
2220 | #define SWMEMCMD_RENDER_ON (1 << 13) | |
2221 | #define SWMEMCMD_SWFREQ (2 << 13) | |
2222 | #define SWMEMCMD_TARVID (3 << 13) | |
2223 | #define SWMEMCMD_VRM_OFF (4 << 13) | |
2224 | #define SWMEMCMD_VRM_ON (5 << 13) | |
2225 | #define CMDSTS (1<<12) | |
2226 | #define SFCAVM (1<<11) | |
2227 | #define SWFREQ_MASK 0x0380 /* P0-7 */ | |
2228 | #define SWFREQ_SHIFT 7 | |
2229 | #define TARVID_MASK 0x001f | |
2230 | #define MEMSTAT_CTG 0x111a0 | |
2231 | #define RCBMINAVG 0x111a0 | |
2232 | #define RCUPEI 0x111b0 | |
2233 | #define RCDNEI 0x111b4 | |
2234 | #define RSTDBYCTL 0x111b8 | |
2235 | #define RS1EN (1<<31) | |
2236 | #define RS2EN (1<<30) | |
2237 | #define RS3EN (1<<29) | |
2238 | #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ | |
2239 | #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ | |
2240 | #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ | |
2241 | #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ | |
2242 | #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ | |
2243 | #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ | |
2244 | #define RSX_STATUS_MASK (7<<20) | |
2245 | #define RSX_STATUS_ON (0<<20) | |
2246 | #define RSX_STATUS_RC1 (1<<20) | |
2247 | #define RSX_STATUS_RC1E (2<<20) | |
2248 | #define RSX_STATUS_RS1 (3<<20) | |
2249 | #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ | |
2250 | #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ | |
2251 | #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ | |
2252 | #define RSX_STATUS_RSVD2 (7<<20) | |
2253 | #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ | |
2254 | #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ | |
2255 | #define JRSC (1<<17) /* rsx coupled to cpu c-state */ | |
2256 | #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ | |
2257 | #define RS1CONTSAV_MASK (3<<14) | |
2258 | #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ | |
2259 | #define RS1CONTSAV_RSVD (1<<14) | |
2260 | #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ | |
2261 | #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ | |
2262 | #define NORMSLEXLAT_MASK (3<<12) | |
2263 | #define SLOW_RS123 (0<<12) | |
2264 | #define SLOW_RS23 (1<<12) | |
2265 | #define SLOW_RS3 (2<<12) | |
2266 | #define NORMAL_RS123 (3<<12) | |
2267 | #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ | |
2268 | #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ | |
2269 | #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ | |
2270 | #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ | |
2271 | #define RS_CSTATE_MASK (3<<4) | |
2272 | #define RS_CSTATE_C367_RS1 (0<<4) | |
2273 | #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) | |
2274 | #define RS_CSTATE_RSVD (2<<4) | |
2275 | #define RS_CSTATE_C367_RS2 (3<<4) | |
2276 | #define REDSAVES (1<<3) /* no context save if was idle during rs0 */ | |
2277 | #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ | |
2278 | #define VIDCTL 0x111c0 | |
2279 | #define VIDSTS 0x111c8 | |
2280 | #define VIDSTART 0x111cc /* 8 bits */ | |
2281 | #define MEMSTAT_ILK 0x111f8 | |
2282 | #define MEMSTAT_VID_MASK 0x7f00 | |
2283 | #define MEMSTAT_VID_SHIFT 8 | |
2284 | #define MEMSTAT_PSTATE_MASK 0x00f8 | |
2285 | #define MEMSTAT_PSTATE_SHIFT 3 | |
2286 | #define MEMSTAT_MON_ACTV (1<<2) | |
2287 | #define MEMSTAT_SRC_CTL_MASK 0x0003 | |
2288 | #define MEMSTAT_SRC_CTL_CORE 0 | |
2289 | #define MEMSTAT_SRC_CTL_TRB 1 | |
2290 | #define MEMSTAT_SRC_CTL_THM 2 | |
2291 | #define MEMSTAT_SRC_CTL_STDBY 3 | |
2292 | #define RCPREVBSYTUPAVG 0x113b8 | |
2293 | #define RCPREVBSYTDNAVG 0x113bc | |
2294 | #define PMMISC 0x11214 | |
2295 | #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ | |
2296 | #define SDEW 0x1124c | |
2297 | #define CSIEW0 0x11250 | |
2298 | #define CSIEW1 0x11254 | |
2299 | #define CSIEW2 0x11258 | |
2300 | #define PEW 0x1125c | |
2301 | #define DEW 0x11270 | |
2302 | #define MCHAFE 0x112c0 | |
2303 | #define CSIEC 0x112e0 | |
2304 | #define DMIEC 0x112e4 | |
2305 | #define DDREC 0x112e8 | |
2306 | #define PEG0EC 0x112ec | |
2307 | #define PEG1EC 0x112f0 | |
2308 | #define GFXEC 0x112f4 | |
2309 | #define RPPREVBSYTUPAVG 0x113b8 | |
2310 | #define RPPREVBSYTDNAVG 0x113bc | |
2311 | #define ECR 0x11600 | |
2312 | #define ECR_GPFE (1<<31) | |
2313 | #define ECR_IMONE (1<<30) | |
2314 | #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ | |
2315 | #define OGW0 0x11608 | |
2316 | #define OGW1 0x1160c | |
2317 | #define EG0 0x11610 | |
2318 | #define EG1 0x11614 | |
2319 | #define EG2 0x11618 | |
2320 | #define EG3 0x1161c | |
2321 | #define EG4 0x11620 | |
2322 | #define EG5 0x11624 | |
2323 | #define EG6 0x11628 | |
2324 | #define EG7 0x1162c | |
2325 | #define PXW 0x11664 | |
2326 | #define PXWL 0x11680 | |
2327 | #define LCFUSE02 0x116c0 | |
2328 | #define LCFUSE_HIV_MASK 0x000000ff | |
2329 | #define CSIPLL0 0x12c10 | |
2330 | #define DDRMPLL1 0X12c20 | |
2331 | #define PEG_BAND_GAP_DATA 0x14d68 | |
2332 | ||
2333 | #define GEN6_GT_THREAD_STATUS_REG 0x13805c | |
2334 | #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 | |
2335 | ||
2336 | #define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948) | |
2337 | #define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994) | |
2338 | #define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998) | |
2339 | ||
2340 | /* | |
2341 | * Logical Context regs | |
2342 | */ | |
2343 | #define CCID 0x2180 | |
2344 | #define CCID_EN (1<<0) | |
2345 | /* | |
2346 | * Notes on SNB/IVB/VLV context size: | |
2347 | * - Power context is saved elsewhere (LLC or stolen) | |
2348 | * - Ring/execlist context is saved on SNB, not on IVB | |
2349 | * - Extended context size already includes render context size | |
2350 | * - We always need to follow the extended context size. | |
2351 | * SNB BSpec has comments indicating that we should use the | |
2352 | * render context size instead if execlists are disabled, but | |
2353 | * based on empirical testing that's just nonsense. | |
2354 | * - Pipelined/VF state is saved on SNB/IVB respectively | |
2355 | * - GT1 size just indicates how much of render context | |
2356 | * doesn't need saving on GT1 | |
2357 | */ | |
2358 | #define CXT_SIZE 0x21a0 | |
2359 | #define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f) | |
2360 | #define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f) | |
2361 | #define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f) | |
2362 | #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f) | |
2363 | #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f) | |
2364 | #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \ | |
2365 | GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ | |
2366 | GEN6_CXT_PIPELINE_SIZE(cxt_reg)) | |
2367 | #define GEN7_CXT_SIZE 0x21a8 | |
2368 | #define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f) | |
2369 | #define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7) | |
2370 | #define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f) | |
2371 | #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f) | |
2372 | #define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7) | |
2373 | #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f) | |
2374 | #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ | |
2375 | GEN7_CXT_VFSTATE_SIZE(ctx_reg)) | |
2376 | /* Haswell does have the CXT_SIZE register however it does not appear to be | |
2377 | * valid. Now, docs explain in dwords what is in the context object. The full | |
2378 | * size is 70720 bytes, however, the power context and execlist context will | |
2379 | * never be saved (power context is stored elsewhere, and execlists don't work | |
2380 | * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages. | |
2381 | */ | |
2382 | #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) | |
2383 | /* Same as Haswell, but 72064 bytes now. */ | |
2384 | #define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE) | |
2385 | ||
2386 | #define CHV_CLK_CTL1 0x101100 | |
2387 | #define VLV_CLK_CTL2 0x101104 | |
2388 | #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 | |
2389 | ||
2390 | /* | |
2391 | * Overlay regs | |
2392 | */ | |
2393 | ||
2394 | #define OVADD 0x30000 | |
2395 | #define DOVSTA 0x30008 | |
2396 | #define OC_BUF (0x3<<20) | |
2397 | #define OGAMC5 0x30010 | |
2398 | #define OGAMC4 0x30014 | |
2399 | #define OGAMC3 0x30018 | |
2400 | #define OGAMC2 0x3001c | |
2401 | #define OGAMC1 0x30020 | |
2402 | #define OGAMC0 0x30024 | |
2403 | ||
2404 | /* | |
2405 | * Display engine regs | |
2406 | */ | |
2407 | ||
2408 | /* Pipe A CRC regs */ | |
2409 | #define _PIPE_CRC_CTL_A 0x60050 | |
2410 | #define PIPE_CRC_ENABLE (1 << 31) | |
2411 | /* ivb+ source selection */ | |
2412 | #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29) | |
2413 | #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29) | |
2414 | #define PIPE_CRC_SOURCE_PF_IVB (2 << 29) | |
2415 | /* ilk+ source selection */ | |
2416 | #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28) | |
2417 | #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28) | |
2418 | #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28) | |
2419 | /* embedded DP port on the north display block, reserved on ivb */ | |
2420 | #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28) | |
2421 | #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */ | |
2422 | /* vlv source selection */ | |
2423 | #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27) | |
2424 | #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27) | |
2425 | #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27) | |
2426 | /* with DP port the pipe source is invalid */ | |
2427 | #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27) | |
2428 | #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27) | |
2429 | #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27) | |
2430 | /* gen3+ source selection */ | |
2431 | #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28) | |
2432 | #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28) | |
2433 | #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28) | |
2434 | /* with DP/TV port the pipe source is invalid */ | |
2435 | #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28) | |
2436 | #define PIPE_CRC_SOURCE_TV_PRE (4 << 28) | |
2437 | #define PIPE_CRC_SOURCE_TV_POST (5 << 28) | |
2438 | #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28) | |
2439 | #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28) | |
2440 | /* gen2 doesn't have source selection bits */ | |
2441 | #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30) | |
2442 | ||
2443 | #define _PIPE_CRC_RES_1_A_IVB 0x60064 | |
2444 | #define _PIPE_CRC_RES_2_A_IVB 0x60068 | |
2445 | #define _PIPE_CRC_RES_3_A_IVB 0x6006c | |
2446 | #define _PIPE_CRC_RES_4_A_IVB 0x60070 | |
2447 | #define _PIPE_CRC_RES_5_A_IVB 0x60074 | |
2448 | ||
2449 | #define _PIPE_CRC_RES_RED_A 0x60060 | |
2450 | #define _PIPE_CRC_RES_GREEN_A 0x60064 | |
2451 | #define _PIPE_CRC_RES_BLUE_A 0x60068 | |
2452 | #define _PIPE_CRC_RES_RES1_A_I915 0x6006c | |
2453 | #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 | |
2454 | ||
2455 | /* Pipe B CRC regs */ | |
2456 | #define _PIPE_CRC_RES_1_B_IVB 0x61064 | |
2457 | #define _PIPE_CRC_RES_2_B_IVB 0x61068 | |
2458 | #define _PIPE_CRC_RES_3_B_IVB 0x6106c | |
2459 | #define _PIPE_CRC_RES_4_B_IVB 0x61070 | |
2460 | #define _PIPE_CRC_RES_5_B_IVB 0x61074 | |
2461 | ||
2462 | #define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A) | |
2463 | #define PIPE_CRC_RES_1_IVB(pipe) \ | |
2464 | _TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB) | |
2465 | #define PIPE_CRC_RES_2_IVB(pipe) \ | |
2466 | _TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB) | |
2467 | #define PIPE_CRC_RES_3_IVB(pipe) \ | |
2468 | _TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB) | |
2469 | #define PIPE_CRC_RES_4_IVB(pipe) \ | |
2470 | _TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB) | |
2471 | #define PIPE_CRC_RES_5_IVB(pipe) \ | |
2472 | _TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB) | |
2473 | ||
2474 | #define PIPE_CRC_RES_RED(pipe) \ | |
2475 | _TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A) | |
2476 | #define PIPE_CRC_RES_GREEN(pipe) \ | |
2477 | _TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A) | |
2478 | #define PIPE_CRC_RES_BLUE(pipe) \ | |
2479 | _TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A) | |
2480 | #define PIPE_CRC_RES_RES1_I915(pipe) \ | |
2481 | _TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915) | |
2482 | #define PIPE_CRC_RES_RES2_G4X(pipe) \ | |
2483 | _TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X) | |
2484 | ||
2485 | /* Pipe A timing regs */ | |
2486 | #define _HTOTAL_A 0x60000 | |
2487 | #define _HBLANK_A 0x60004 | |
2488 | #define _HSYNC_A 0x60008 | |
2489 | #define _VTOTAL_A 0x6000c | |
2490 | #define _VBLANK_A 0x60010 | |
2491 | #define _VSYNC_A 0x60014 | |
2492 | #define _PIPEASRC 0x6001c | |
2493 | #define _BCLRPAT_A 0x60020 | |
2494 | #define _VSYNCSHIFT_A 0x60028 | |
2495 | #define _PIPE_MULT_A 0x6002c | |
2496 | ||
2497 | /* Pipe B timing regs */ | |
2498 | #define _HTOTAL_B 0x61000 | |
2499 | #define _HBLANK_B 0x61004 | |
2500 | #define _HSYNC_B 0x61008 | |
2501 | #define _VTOTAL_B 0x6100c | |
2502 | #define _VBLANK_B 0x61010 | |
2503 | #define _VSYNC_B 0x61014 | |
2504 | #define _PIPEBSRC 0x6101c | |
2505 | #define _BCLRPAT_B 0x61020 | |
2506 | #define _VSYNCSHIFT_B 0x61028 | |
2507 | #define _PIPE_MULT_B 0x6102c | |
2508 | ||
2509 | #define TRANSCODER_A_OFFSET 0x60000 | |
2510 | #define TRANSCODER_B_OFFSET 0x61000 | |
2511 | #define TRANSCODER_C_OFFSET 0x62000 | |
2512 | #define CHV_TRANSCODER_C_OFFSET 0x63000 | |
2513 | #define TRANSCODER_EDP_OFFSET 0x6f000 | |
2514 | ||
2515 | #define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \ | |
2516 | dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \ | |
2517 | dev_priv->info.display_mmio_offset) | |
2518 | ||
2519 | #define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A) | |
2520 | #define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A) | |
2521 | #define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A) | |
2522 | #define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A) | |
2523 | #define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A) | |
2524 | #define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A) | |
2525 | #define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A) | |
2526 | #define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A) | |
2527 | #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC) | |
2528 | #define PIPE_MULT(trans) _TRANSCODER2(trans, _PIPE_MULT_A) | |
2529 | ||
2530 | /* VLV eDP PSR registers */ | |
2531 | #define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090) | |
2532 | #define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090) | |
2533 | #define VLV_EDP_PSR_ENABLE (1<<0) | |
2534 | #define VLV_EDP_PSR_RESET (1<<1) | |
2535 | #define VLV_EDP_PSR_MODE_MASK (7<<2) | |
2536 | #define VLV_EDP_PSR_MODE_HW_TIMER (1<<3) | |
2537 | #define VLV_EDP_PSR_MODE_SW_TIMER (1<<2) | |
2538 | #define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1<<7) | |
2539 | #define VLV_EDP_PSR_ACTIVE_ENTRY (1<<8) | |
2540 | #define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1<<9) | |
2541 | #define VLV_EDP_PSR_DBL_FRAME (1<<10) | |
2542 | #define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff<<16) | |
2543 | #define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16 | |
2544 | #define VLV_PSRCTL(pipe) _PIPE(pipe, _PSRCTLA, _PSRCTLB) | |
2545 | ||
2546 | #define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0) | |
2547 | #define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0) | |
2548 | #define VLV_EDP_PSR_SDP_FREQ_MASK (3<<30) | |
2549 | #define VLV_EDP_PSR_SDP_FREQ_ONCE (1<<31) | |
2550 | #define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1<<30) | |
2551 | #define VLV_VSCSDP(pipe) _PIPE(pipe, _VSCSDPA, _VSCSDPB) | |
2552 | ||
2553 | #define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094) | |
2554 | #define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094) | |
2555 | #define VLV_EDP_PSR_LAST_STATE_MASK (7<<3) | |
2556 | #define VLV_EDP_PSR_CURR_STATE_MASK 7 | |
2557 | #define VLV_EDP_PSR_DISABLED (0<<0) | |
2558 | #define VLV_EDP_PSR_INACTIVE (1<<0) | |
2559 | #define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2<<0) | |
2560 | #define VLV_EDP_PSR_ACTIVE_NORFB_UP (3<<0) | |
2561 | #define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4<<0) | |
2562 | #define VLV_EDP_PSR_EXIT (5<<0) | |
2563 | #define VLV_EDP_PSR_IN_TRANS (1<<7) | |
2564 | #define VLV_PSRSTAT(pipe) _PIPE(pipe, _PSRSTATA, _PSRSTATB) | |
2565 | ||
2566 | /* HSW+ eDP PSR registers */ | |
2567 | #define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800) | |
2568 | #define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0) | |
2569 | #define EDP_PSR_ENABLE (1<<31) | |
2570 | #define BDW_PSR_SINGLE_FRAME (1<<30) | |
2571 | #define EDP_PSR_LINK_DISABLE (0<<27) | |
2572 | #define EDP_PSR_LINK_STANDBY (1<<27) | |
2573 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25) | |
2574 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25) | |
2575 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25) | |
2576 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25) | |
2577 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25) | |
2578 | #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 | |
2579 | #define EDP_PSR_SKIP_AUX_EXIT (1<<12) | |
2580 | #define EDP_PSR_TP1_TP2_SEL (0<<11) | |
2581 | #define EDP_PSR_TP1_TP3_SEL (1<<11) | |
2582 | #define EDP_PSR_TP2_TP3_TIME_500us (0<<8) | |
2583 | #define EDP_PSR_TP2_TP3_TIME_100us (1<<8) | |
2584 | #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8) | |
2585 | #define EDP_PSR_TP2_TP3_TIME_0us (3<<8) | |
2586 | #define EDP_PSR_TP1_TIME_500us (0<<4) | |
2587 | #define EDP_PSR_TP1_TIME_100us (1<<4) | |
2588 | #define EDP_PSR_TP1_TIME_2500us (2<<4) | |
2589 | #define EDP_PSR_TP1_TIME_0us (3<<4) | |
2590 | #define EDP_PSR_IDLE_FRAME_SHIFT 0 | |
2591 | ||
2592 | #define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10) | |
2593 | #define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14) | |
2594 | #define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18) | |
2595 | #define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c) | |
2596 | #define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20) | |
2597 | #define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24) | |
2598 | ||
2599 | #define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) + 0x40) | |
2600 | #define EDP_PSR_STATUS_STATE_MASK (7<<29) | |
2601 | #define EDP_PSR_STATUS_STATE_IDLE (0<<29) | |
2602 | #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29) | |
2603 | #define EDP_PSR_STATUS_STATE_SRDENT (2<<29) | |
2604 | #define EDP_PSR_STATUS_STATE_BUFOFF (3<<29) | |
2605 | #define EDP_PSR_STATUS_STATE_BUFON (4<<29) | |
2606 | #define EDP_PSR_STATUS_STATE_AUXACK (5<<29) | |
2607 | #define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29) | |
2608 | #define EDP_PSR_STATUS_LINK_MASK (3<<26) | |
2609 | #define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26) | |
2610 | #define EDP_PSR_STATUS_LINK_FULL_ON (1<<26) | |
2611 | #define EDP_PSR_STATUS_LINK_STANDBY (2<<26) | |
2612 | #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 | |
2613 | #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f | |
2614 | #define EDP_PSR_STATUS_COUNT_SHIFT 16 | |
2615 | #define EDP_PSR_STATUS_COUNT_MASK 0xf | |
2616 | #define EDP_PSR_STATUS_AUX_ERROR (1<<15) | |
2617 | #define EDP_PSR_STATUS_AUX_SENDING (1<<12) | |
2618 | #define EDP_PSR_STATUS_SENDING_IDLE (1<<9) | |
2619 | #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8) | |
2620 | #define EDP_PSR_STATUS_SENDING_TP1 (1<<4) | |
2621 | #define EDP_PSR_STATUS_IDLE_MASK 0xf | |
2622 | ||
2623 | #define EDP_PSR_PERF_CNT(dev) (EDP_PSR_BASE(dev) + 0x44) | |
2624 | #define EDP_PSR_PERF_CNT_MASK 0xffffff | |
2625 | ||
2626 | #define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60) | |
2627 | #define EDP_PSR_DEBUG_MASK_LPSP (1<<27) | |
2628 | #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26) | |
2629 | #define EDP_PSR_DEBUG_MASK_HPD (1<<25) | |
2630 | ||
2631 | /* VGA port control */ | |
2632 | #define ADPA 0x61100 | |
2633 | #define PCH_ADPA 0xe1100 | |
2634 | #define VLV_ADPA (VLV_DISPLAY_BASE + ADPA) | |
2635 | ||
2636 | #define ADPA_DAC_ENABLE (1<<31) | |
2637 | #define ADPA_DAC_DISABLE 0 | |
2638 | #define ADPA_PIPE_SELECT_MASK (1<<30) | |
2639 | #define ADPA_PIPE_A_SELECT 0 | |
2640 | #define ADPA_PIPE_B_SELECT (1<<30) | |
2641 | #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) | |
2642 | /* CPT uses bits 29:30 for pch transcoder select */ | |
2643 | #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ | |
2644 | #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) | |
2645 | #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) | |
2646 | #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) | |
2647 | #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) | |
2648 | #define ADPA_CRT_HOTPLUG_ENABLE (1<<23) | |
2649 | #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) | |
2650 | #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) | |
2651 | #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) | |
2652 | #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) | |
2653 | #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) | |
2654 | #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) | |
2655 | #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) | |
2656 | #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) | |
2657 | #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) | |
2658 | #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) | |
2659 | #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) | |
2660 | #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) | |
2661 | #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) | |
2662 | #define ADPA_USE_VGA_HVPOLARITY (1<<15) | |
2663 | #define ADPA_SETS_HVPOLARITY 0 | |
2664 | #define ADPA_VSYNC_CNTL_DISABLE (1<<10) | |
2665 | #define ADPA_VSYNC_CNTL_ENABLE 0 | |
2666 | #define ADPA_HSYNC_CNTL_DISABLE (1<<11) | |
2667 | #define ADPA_HSYNC_CNTL_ENABLE 0 | |
2668 | #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) | |
2669 | #define ADPA_VSYNC_ACTIVE_LOW 0 | |
2670 | #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) | |
2671 | #define ADPA_HSYNC_ACTIVE_LOW 0 | |
2672 | #define ADPA_DPMS_MASK (~(3<<10)) | |
2673 | #define ADPA_DPMS_ON (0<<10) | |
2674 | #define ADPA_DPMS_SUSPEND (1<<10) | |
2675 | #define ADPA_DPMS_STANDBY (2<<10) | |
2676 | #define ADPA_DPMS_OFF (3<<10) | |
2677 | ||
2678 | ||
2679 | /* Hotplug control (945+ only) */ | |
2680 | #define PORT_HOTPLUG_EN (dev_priv->info.display_mmio_offset + 0x61110) | |
2681 | #define PORTB_HOTPLUG_INT_EN (1 << 29) | |
2682 | #define PORTC_HOTPLUG_INT_EN (1 << 28) | |
2683 | #define PORTD_HOTPLUG_INT_EN (1 << 27) | |
2684 | #define SDVOB_HOTPLUG_INT_EN (1 << 26) | |
2685 | #define SDVOC_HOTPLUG_INT_EN (1 << 25) | |
2686 | #define TV_HOTPLUG_INT_EN (1 << 18) | |
2687 | #define CRT_HOTPLUG_INT_EN (1 << 9) | |
2688 | #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ | |
2689 | PORTC_HOTPLUG_INT_EN | \ | |
2690 | PORTD_HOTPLUG_INT_EN | \ | |
2691 | SDVOC_HOTPLUG_INT_EN | \ | |
2692 | SDVOB_HOTPLUG_INT_EN | \ | |
2693 | CRT_HOTPLUG_INT_EN) | |
2694 | #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) | |
2695 | #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) | |
2696 | /* must use period 64 on GM45 according to docs */ | |
2697 | #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) | |
2698 | #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) | |
2699 | #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) | |
2700 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) | |
2701 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) | |
2702 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) | |
2703 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) | |
2704 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) | |
2705 | #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) | |
2706 | #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) | |
2707 | #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) | |
2708 | #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) | |
2709 | ||
2710 | #define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114) | |
2711 | /* | |
2712 | * HDMI/DP bits are gen4+ | |
2713 | * | |
2714 | * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. | |
2715 | * Please check the detailed lore in the commit message for for experimental | |
2716 | * evidence. | |
2717 | */ | |
2718 | #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 29) | |
2719 | #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) | |
2720 | #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 27) | |
2721 | /* VLV DP/HDMI bits again match Bspec */ | |
2722 | #define PORTD_HOTPLUG_LIVE_STATUS_VLV (1 << 27) | |
2723 | #define PORTC_HOTPLUG_LIVE_STATUS_VLV (1 << 28) | |
2724 | #define PORTB_HOTPLUG_LIVE_STATUS_VLV (1 << 29) | |
2725 | #define PORTD_HOTPLUG_INT_STATUS (3 << 21) | |
2726 | #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) | |
2727 | #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) | |
2728 | #define PORTC_HOTPLUG_INT_STATUS (3 << 19) | |
2729 | #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) | |
2730 | #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) | |
2731 | #define PORTB_HOTPLUG_INT_STATUS (3 << 17) | |
2732 | #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) | |
2733 | #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) | |
2734 | /* CRT/TV common between gen3+ */ | |
2735 | #define CRT_HOTPLUG_INT_STATUS (1 << 11) | |
2736 | #define TV_HOTPLUG_INT_STATUS (1 << 10) | |
2737 | #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) | |
2738 | #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) | |
2739 | #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) | |
2740 | #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) | |
2741 | #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) | |
2742 | #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) | |
2743 | #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) | |
2744 | #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) | |
2745 | ||
2746 | /* SDVO is different across gen3/4 */ | |
2747 | #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) | |
2748 | #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) | |
2749 | /* | |
2750 | * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, | |
2751 | * since reality corrobates that they're the same as on gen3. But keep these | |
2752 | * bits here (and the comment!) to help any other lost wanderers back onto the | |
2753 | * right tracks. | |
2754 | */ | |
2755 | #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) | |
2756 | #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) | |
2757 | #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) | |
2758 | #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) | |
2759 | #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ | |
2760 | SDVOB_HOTPLUG_INT_STATUS_G4X | \ | |
2761 | SDVOC_HOTPLUG_INT_STATUS_G4X | \ | |
2762 | PORTB_HOTPLUG_INT_STATUS | \ | |
2763 | PORTC_HOTPLUG_INT_STATUS | \ | |
2764 | PORTD_HOTPLUG_INT_STATUS) | |
2765 | ||
2766 | #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ | |
2767 | SDVOB_HOTPLUG_INT_STATUS_I915 | \ | |
2768 | SDVOC_HOTPLUG_INT_STATUS_I915 | \ | |
2769 | PORTB_HOTPLUG_INT_STATUS | \ | |
2770 | PORTC_HOTPLUG_INT_STATUS | \ | |
2771 | PORTD_HOTPLUG_INT_STATUS) | |
2772 | ||
2773 | /* SDVO and HDMI port control. | |
2774 | * The same register may be used for SDVO or HDMI */ | |
2775 | #define GEN3_SDVOB 0x61140 | |
2776 | #define GEN3_SDVOC 0x61160 | |
2777 | #define GEN4_HDMIB GEN3_SDVOB | |
2778 | #define GEN4_HDMIC GEN3_SDVOC | |
2779 | #define CHV_HDMID 0x6116C | |
2780 | #define PCH_SDVOB 0xe1140 | |
2781 | #define PCH_HDMIB PCH_SDVOB | |
2782 | #define PCH_HDMIC 0xe1150 | |
2783 | #define PCH_HDMID 0xe1160 | |
2784 | ||
2785 | #define PORT_DFT_I9XX 0x61150 | |
2786 | #define DC_BALANCE_RESET (1 << 25) | |
2787 | #define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154) | |
2788 | #define DC_BALANCE_RESET_VLV (1 << 31) | |
2789 | #define PIPE_SCRAMBLE_RESET_MASK (0x3 << 0) | |
2790 | #define PIPE_B_SCRAMBLE_RESET (1 << 1) | |
2791 | #define PIPE_A_SCRAMBLE_RESET (1 << 0) | |
2792 | ||
2793 | /* Gen 3 SDVO bits: */ | |
2794 | #define SDVO_ENABLE (1 << 31) | |
2795 | #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) | |
2796 | #define SDVO_PIPE_SEL_MASK (1 << 30) | |
2797 | #define SDVO_PIPE_B_SELECT (1 << 30) | |
2798 | #define SDVO_STALL_SELECT (1 << 29) | |
2799 | #define SDVO_INTERRUPT_ENABLE (1 << 26) | |
2800 | /* | |
2801 | * 915G/GM SDVO pixel multiplier. | |
2802 | * Programmed value is multiplier - 1, up to 5x. | |
2803 | * \sa DPLL_MD_UDI_MULTIPLIER_MASK | |
2804 | */ | |
2805 | #define SDVO_PORT_MULTIPLY_MASK (7 << 23) | |
2806 | #define SDVO_PORT_MULTIPLY_SHIFT 23 | |
2807 | #define SDVO_PHASE_SELECT_MASK (15 << 19) | |
2808 | #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) | |
2809 | #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) | |
2810 | #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ | |
2811 | #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ | |
2812 | #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ | |
2813 | #define SDVO_DETECTED (1 << 2) | |
2814 | /* Bits to be preserved when writing */ | |
2815 | #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ | |
2816 | SDVO_INTERRUPT_ENABLE) | |
2817 | #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) | |
2818 | ||
2819 | /* Gen 4 SDVO/HDMI bits: */ | |
2820 | #define SDVO_COLOR_FORMAT_8bpc (0 << 26) | |
2821 | #define SDVO_COLOR_FORMAT_MASK (7 << 26) | |
2822 | #define SDVO_ENCODING_SDVO (0 << 10) | |
2823 | #define SDVO_ENCODING_HDMI (2 << 10) | |
2824 | #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ | |
2825 | #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ | |
2826 | #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ | |
2827 | #define SDVO_AUDIO_ENABLE (1 << 6) | |
2828 | /* VSYNC/HSYNC bits new with 965, default is to be set */ | |
2829 | #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) | |
2830 | #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) | |
2831 | ||
2832 | /* Gen 5 (IBX) SDVO/HDMI bits: */ | |
2833 | #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ | |
2834 | #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ | |
2835 | ||
2836 | /* Gen 6 (CPT) SDVO/HDMI bits: */ | |
2837 | #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) | |
2838 | #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) | |
2839 | ||
2840 | /* CHV SDVO/HDMI bits: */ | |
2841 | #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) | |
2842 | #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) | |
2843 | ||
2844 | ||
2845 | /* DVO port control */ | |
2846 | #define DVOA 0x61120 | |
2847 | #define DVOB 0x61140 | |
2848 | #define DVOC 0x61160 | |
2849 | #define DVO_ENABLE (1 << 31) | |
2850 | #define DVO_PIPE_B_SELECT (1 << 30) | |
2851 | #define DVO_PIPE_STALL_UNUSED (0 << 28) | |
2852 | #define DVO_PIPE_STALL (1 << 28) | |
2853 | #define DVO_PIPE_STALL_TV (2 << 28) | |
2854 | #define DVO_PIPE_STALL_MASK (3 << 28) | |
2855 | #define DVO_USE_VGA_SYNC (1 << 15) | |
2856 | #define DVO_DATA_ORDER_I740 (0 << 14) | |
2857 | #define DVO_DATA_ORDER_FP (1 << 14) | |
2858 | #define DVO_VSYNC_DISABLE (1 << 11) | |
2859 | #define DVO_HSYNC_DISABLE (1 << 10) | |
2860 | #define DVO_VSYNC_TRISTATE (1 << 9) | |
2861 | #define DVO_HSYNC_TRISTATE (1 << 8) | |
2862 | #define DVO_BORDER_ENABLE (1 << 7) | |
2863 | #define DVO_DATA_ORDER_GBRG (1 << 6) | |
2864 | #define DVO_DATA_ORDER_RGGB (0 << 6) | |
2865 | #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) | |
2866 | #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) | |
2867 | #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) | |
2868 | #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) | |
2869 | #define DVO_BLANK_ACTIVE_HIGH (1 << 2) | |
2870 | #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ | |
2871 | #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ | |
2872 | #define DVO_PRESERVE_MASK (0x7<<24) | |
2873 | #define DVOA_SRCDIM 0x61124 | |
2874 | #define DVOB_SRCDIM 0x61144 | |
2875 | #define DVOC_SRCDIM 0x61164 | |
2876 | #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 | |
2877 | #define DVO_SRCDIM_VERTICAL_SHIFT 0 | |
2878 | ||
2879 | /* LVDS port control */ | |
2880 | #define LVDS 0x61180 | |
2881 | /* | |
2882 | * Enables the LVDS port. This bit must be set before DPLLs are enabled, as | |
2883 | * the DPLL semantics change when the LVDS is assigned to that pipe. | |
2884 | */ | |
2885 | #define LVDS_PORT_EN (1 << 31) | |
2886 | /* Selects pipe B for LVDS data. Must be set on pre-965. */ | |
2887 | #define LVDS_PIPEB_SELECT (1 << 30) | |
2888 | #define LVDS_PIPE_MASK (1 << 30) | |
2889 | #define LVDS_PIPE(pipe) ((pipe) << 30) | |
2890 | /* LVDS dithering flag on 965/g4x platform */ | |
2891 | #define LVDS_ENABLE_DITHER (1 << 25) | |
2892 | /* LVDS sync polarity flags. Set to invert (i.e. negative) */ | |
2893 | #define LVDS_VSYNC_POLARITY (1 << 21) | |
2894 | #define LVDS_HSYNC_POLARITY (1 << 20) | |
2895 | ||
2896 | /* Enable border for unscaled (or aspect-scaled) display */ | |
2897 | #define LVDS_BORDER_ENABLE (1 << 15) | |
2898 | /* | |
2899 | * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per | |
2900 | * pixel. | |
2901 | */ | |
2902 | #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) | |
2903 | #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) | |
2904 | #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) | |
2905 | /* | |
2906 | * Controls the A3 data pair, which contains the additional LSBs for 24 bit | |
2907 | * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be | |
2908 | * on. | |
2909 | */ | |
2910 | #define LVDS_A3_POWER_MASK (3 << 6) | |
2911 | #define LVDS_A3_POWER_DOWN (0 << 6) | |
2912 | #define LVDS_A3_POWER_UP (3 << 6) | |
2913 | /* | |
2914 | * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP | |
2915 | * is set. | |
2916 | */ | |
2917 | #define LVDS_CLKB_POWER_MASK (3 << 4) | |
2918 | #define LVDS_CLKB_POWER_DOWN (0 << 4) | |
2919 | #define LVDS_CLKB_POWER_UP (3 << 4) | |
2920 | /* | |
2921 | * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 | |
2922 | * setting for whether we are in dual-channel mode. The B3 pair will | |
2923 | * additionally only be powered up when LVDS_A3_POWER_UP is set. | |
2924 | */ | |
2925 | #define LVDS_B0B3_POWER_MASK (3 << 2) | |
2926 | #define LVDS_B0B3_POWER_DOWN (0 << 2) | |
2927 | #define LVDS_B0B3_POWER_UP (3 << 2) | |
2928 | ||
2929 | /* Video Data Island Packet control */ | |
2930 | #define VIDEO_DIP_DATA 0x61178 | |
2931 | /* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC | |
2932 | * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte | |
2933 | * of the infoframe structure specified by CEA-861. */ | |
2934 | #define VIDEO_DIP_DATA_SIZE 32 | |
2935 | #define VIDEO_DIP_VSC_DATA_SIZE 36 | |
2936 | #define VIDEO_DIP_CTL 0x61170 | |
2937 | /* Pre HSW: */ | |
2938 | #define VIDEO_DIP_ENABLE (1 << 31) | |
2939 | #define VIDEO_DIP_PORT(port) ((port) << 29) | |
2940 | #define VIDEO_DIP_PORT_MASK (3 << 29) | |
2941 | #define VIDEO_DIP_ENABLE_GCP (1 << 25) | |
2942 | #define VIDEO_DIP_ENABLE_AVI (1 << 21) | |
2943 | #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) | |
2944 | #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) | |
2945 | #define VIDEO_DIP_ENABLE_SPD (8 << 21) | |
2946 | #define VIDEO_DIP_SELECT_AVI (0 << 19) | |
2947 | #define VIDEO_DIP_SELECT_VENDOR (1 << 19) | |
2948 | #define VIDEO_DIP_SELECT_SPD (3 << 19) | |
2949 | #define VIDEO_DIP_SELECT_MASK (3 << 19) | |
2950 | #define VIDEO_DIP_FREQ_ONCE (0 << 16) | |
2951 | #define VIDEO_DIP_FREQ_VSYNC (1 << 16) | |
2952 | #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) | |
2953 | #define VIDEO_DIP_FREQ_MASK (3 << 16) | |
2954 | /* HSW and later: */ | |
2955 | #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) | |
2956 | #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) | |
2957 | #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) | |
2958 | #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) | |
2959 | #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) | |
2960 | #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) | |
2961 | ||
2962 | /* Panel power sequencing */ | |
2963 | #define PP_STATUS 0x61200 | |
2964 | #define PP_ON (1 << 31) | |
2965 | /* | |
2966 | * Indicates that all dependencies of the panel are on: | |
2967 | * | |
2968 | * - PLL enabled | |
2969 | * - pipe enabled | |
2970 | * - LVDS/DVOB/DVOC on | |
2971 | */ | |
2972 | #define PP_READY (1 << 30) | |
2973 | #define PP_SEQUENCE_NONE (0 << 28) | |
2974 | #define PP_SEQUENCE_POWER_UP (1 << 28) | |
2975 | #define PP_SEQUENCE_POWER_DOWN (2 << 28) | |
2976 | #define PP_SEQUENCE_MASK (3 << 28) | |
2977 | #define PP_SEQUENCE_SHIFT 28 | |
2978 | #define PP_CYCLE_DELAY_ACTIVE (1 << 27) | |
2979 | #define PP_SEQUENCE_STATE_MASK 0x0000000f | |
2980 | #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) | |
2981 | #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) | |
2982 | #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) | |
2983 | #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) | |
2984 | #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) | |
2985 | #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) | |
2986 | #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) | |
2987 | #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) | |
2988 | #define PP_SEQUENCE_STATE_RESET (0xf << 0) | |
2989 | #define PP_CONTROL 0x61204 | |
2990 | #define POWER_TARGET_ON (1 << 0) | |
2991 | #define PP_ON_DELAYS 0x61208 | |
2992 | #define PP_OFF_DELAYS 0x6120c | |
2993 | #define PP_DIVISOR 0x61210 | |
2994 | ||
2995 | /* Panel fitting */ | |
2996 | #define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230) | |
2997 | #define PFIT_ENABLE (1 << 31) | |
2998 | #define PFIT_PIPE_MASK (3 << 29) | |
2999 | #define PFIT_PIPE_SHIFT 29 | |
3000 | #define VERT_INTERP_DISABLE (0 << 10) | |
3001 | #define VERT_INTERP_BILINEAR (1 << 10) | |
3002 | #define VERT_INTERP_MASK (3 << 10) | |
3003 | #define VERT_AUTO_SCALE (1 << 9) | |
3004 | #define HORIZ_INTERP_DISABLE (0 << 6) | |
3005 | #define HORIZ_INTERP_BILINEAR (1 << 6) | |
3006 | #define HORIZ_INTERP_MASK (3 << 6) | |
3007 | #define HORIZ_AUTO_SCALE (1 << 5) | |
3008 | #define PANEL_8TO6_DITHER_ENABLE (1 << 3) | |
3009 | #define PFIT_FILTER_FUZZY (0 << 24) | |
3010 | #define PFIT_SCALING_AUTO (0 << 26) | |
3011 | #define PFIT_SCALING_PROGRAMMED (1 << 26) | |
3012 | #define PFIT_SCALING_PILLAR (2 << 26) | |
3013 | #define PFIT_SCALING_LETTER (3 << 26) | |
3014 | #define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234) | |
3015 | /* Pre-965 */ | |
3016 | #define PFIT_VERT_SCALE_SHIFT 20 | |
3017 | #define PFIT_VERT_SCALE_MASK 0xfff00000 | |
3018 | #define PFIT_HORIZ_SCALE_SHIFT 4 | |
3019 | #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 | |
3020 | /* 965+ */ | |
3021 | #define PFIT_VERT_SCALE_SHIFT_965 16 | |
3022 | #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 | |
3023 | #define PFIT_HORIZ_SCALE_SHIFT_965 0 | |
3024 | #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff | |
3025 | ||
3026 | #define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238) | |
3027 | ||
3028 | #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250) | |
3029 | #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350) | |
3030 | #define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ | |
3031 | _VLV_BLC_PWM_CTL2_B) | |
3032 | ||
3033 | #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254) | |
3034 | #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354) | |
3035 | #define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ | |
3036 | _VLV_BLC_PWM_CTL_B) | |
3037 | ||
3038 | #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260) | |
3039 | #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360) | |
3040 | #define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ | |
3041 | _VLV_BLC_HIST_CTL_B) | |
3042 | ||
3043 | /* Backlight control */ | |
3044 | #define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */ | |
3045 | #define BLM_PWM_ENABLE (1 << 31) | |
3046 | #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ | |
3047 | #define BLM_PIPE_SELECT (1 << 29) | |
3048 | #define BLM_PIPE_SELECT_IVB (3 << 29) | |
3049 | #define BLM_PIPE_A (0 << 29) | |
3050 | #define BLM_PIPE_B (1 << 29) | |
3051 | #define BLM_PIPE_C (2 << 29) /* ivb + */ | |
3052 | #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */ | |
3053 | #define BLM_TRANSCODER_B BLM_PIPE_B | |
3054 | #define BLM_TRANSCODER_C BLM_PIPE_C | |
3055 | #define BLM_TRANSCODER_EDP (3 << 29) | |
3056 | #define BLM_PIPE(pipe) ((pipe) << 29) | |
3057 | #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ | |
3058 | #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) | |
3059 | #define BLM_PHASE_IN_ENABLE (1 << 25) | |
3060 | #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) | |
3061 | #define BLM_PHASE_IN_TIME_BASE_SHIFT (16) | |
3062 | #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) | |
3063 | #define BLM_PHASE_IN_COUNT_SHIFT (8) | |
3064 | #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) | |
3065 | #define BLM_PHASE_IN_INCR_SHIFT (0) | |
3066 | #define BLM_PHASE_IN_INCR_MASK (0xff << 0) | |
3067 | #define BLC_PWM_CTL (dev_priv->info.display_mmio_offset + 0x61254) | |
3068 | /* | |
3069 | * This is the most significant 15 bits of the number of backlight cycles in a | |
3070 | * complete cycle of the modulated backlight control. | |
3071 | * | |
3072 | * The actual value is this field multiplied by two. | |
3073 | */ | |
3074 | #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) | |
3075 | #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) | |
3076 | #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ | |
3077 | /* | |
3078 | * This is the number of cycles out of the backlight modulation cycle for which | |
3079 | * the backlight is on. | |
3080 | * | |
3081 | * This field must be no greater than the number of cycles in the complete | |
3082 | * backlight modulation cycle. | |
3083 | */ | |
3084 | #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) | |
3085 | #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) | |
3086 | #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) | |
3087 | #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ | |
3088 | ||
3089 | #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260) | |
3090 | ||
3091 | /* New registers for PCH-split platforms. Safe where new bits show up, the | |
3092 | * register layout machtes with gen4 BLC_PWM_CTL[12]. */ | |
3093 | #define BLC_PWM_CPU_CTL2 0x48250 | |
3094 | #define BLC_PWM_CPU_CTL 0x48254 | |
3095 | ||
3096 | #define HSW_BLC_PWM2_CTL 0x48350 | |
3097 | ||
3098 | /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is | |
3099 | * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ | |
3100 | #define BLC_PWM_PCH_CTL1 0xc8250 | |
3101 | #define BLM_PCH_PWM_ENABLE (1 << 31) | |
3102 | #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) | |
3103 | #define BLM_PCH_POLARITY (1 << 29) | |
3104 | #define BLC_PWM_PCH_CTL2 0xc8254 | |
3105 | ||
3106 | #define UTIL_PIN_CTL 0x48400 | |
3107 | #define UTIL_PIN_ENABLE (1 << 31) | |
3108 | ||
3109 | #define PCH_GTC_CTL 0xe7000 | |
3110 | #define PCH_GTC_ENABLE (1 << 31) | |
3111 | ||
3112 | /* TV port control */ | |
3113 | #define TV_CTL 0x68000 | |
3114 | /* Enables the TV encoder */ | |
3115 | # define TV_ENC_ENABLE (1 << 31) | |
3116 | /* Sources the TV encoder input from pipe B instead of A. */ | |
3117 | # define TV_ENC_PIPEB_SELECT (1 << 30) | |
3118 | /* Outputs composite video (DAC A only) */ | |
3119 | # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) | |
3120 | /* Outputs SVideo video (DAC B/C) */ | |
3121 | # define TV_ENC_OUTPUT_SVIDEO (1 << 28) | |
3122 | /* Outputs Component video (DAC A/B/C) */ | |
3123 | # define TV_ENC_OUTPUT_COMPONENT (2 << 28) | |
3124 | /* Outputs Composite and SVideo (DAC A/B/C) */ | |
3125 | # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) | |
3126 | # define TV_TRILEVEL_SYNC (1 << 21) | |
3127 | /* Enables slow sync generation (945GM only) */ | |
3128 | # define TV_SLOW_SYNC (1 << 20) | |
3129 | /* Selects 4x oversampling for 480i and 576p */ | |
3130 | # define TV_OVERSAMPLE_4X (0 << 18) | |
3131 | /* Selects 2x oversampling for 720p and 1080i */ | |
3132 | # define TV_OVERSAMPLE_2X (1 << 18) | |
3133 | /* Selects no oversampling for 1080p */ | |
3134 | # define TV_OVERSAMPLE_NONE (2 << 18) | |
3135 | /* Selects 8x oversampling */ | |
3136 | # define TV_OVERSAMPLE_8X (3 << 18) | |
3137 | /* Selects progressive mode rather than interlaced */ | |
3138 | # define TV_PROGRESSIVE (1 << 17) | |
3139 | /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ | |
3140 | # define TV_PAL_BURST (1 << 16) | |
3141 | /* Field for setting delay of Y compared to C */ | |
3142 | # define TV_YC_SKEW_MASK (7 << 12) | |
3143 | /* Enables a fix for 480p/576p standard definition modes on the 915GM only */ | |
3144 | # define TV_ENC_SDP_FIX (1 << 11) | |
3145 | /* | |
3146 | * Enables a fix for the 915GM only. | |
3147 | * | |
3148 | * Not sure what it does. | |
3149 | */ | |
3150 | # define TV_ENC_C0_FIX (1 << 10) | |
3151 | /* Bits that must be preserved by software */ | |
3152 | # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) | |
3153 | # define TV_FUSE_STATE_MASK (3 << 4) | |
3154 | /* Read-only state that reports all features enabled */ | |
3155 | # define TV_FUSE_STATE_ENABLED (0 << 4) | |
3156 | /* Read-only state that reports that Macrovision is disabled in hardware*/ | |
3157 | # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) | |
3158 | /* Read-only state that reports that TV-out is disabled in hardware. */ | |
3159 | # define TV_FUSE_STATE_DISABLED (2 << 4) | |
3160 | /* Normal operation */ | |
3161 | # define TV_TEST_MODE_NORMAL (0 << 0) | |
3162 | /* Encoder test pattern 1 - combo pattern */ | |
3163 | # define TV_TEST_MODE_PATTERN_1 (1 << 0) | |
3164 | /* Encoder test pattern 2 - full screen vertical 75% color bars */ | |
3165 | # define TV_TEST_MODE_PATTERN_2 (2 << 0) | |
3166 | /* Encoder test pattern 3 - full screen horizontal 75% color bars */ | |
3167 | # define TV_TEST_MODE_PATTERN_3 (3 << 0) | |
3168 | /* Encoder test pattern 4 - random noise */ | |
3169 | # define TV_TEST_MODE_PATTERN_4 (4 << 0) | |
3170 | /* Encoder test pattern 5 - linear color ramps */ | |
3171 | # define TV_TEST_MODE_PATTERN_5 (5 << 0) | |
3172 | /* | |
3173 | * This test mode forces the DACs to 50% of full output. | |
3174 | * | |
3175 | * This is used for load detection in combination with TVDAC_SENSE_MASK | |
3176 | */ | |
3177 | # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) | |
3178 | # define TV_TEST_MODE_MASK (7 << 0) | |
3179 | ||
3180 | #define TV_DAC 0x68004 | |
3181 | # define TV_DAC_SAVE 0x00ffff00 | |
3182 | /* | |
3183 | * Reports that DAC state change logic has reported change (RO). | |
3184 | * | |
3185 | * This gets cleared when TV_DAC_STATE_EN is cleared | |
3186 | */ | |
3187 | # define TVDAC_STATE_CHG (1 << 31) | |
3188 | # define TVDAC_SENSE_MASK (7 << 28) | |
3189 | /* Reports that DAC A voltage is above the detect threshold */ | |
3190 | # define TVDAC_A_SENSE (1 << 30) | |
3191 | /* Reports that DAC B voltage is above the detect threshold */ | |
3192 | # define TVDAC_B_SENSE (1 << 29) | |
3193 | /* Reports that DAC C voltage is above the detect threshold */ | |
3194 | # define TVDAC_C_SENSE (1 << 28) | |
3195 | /* | |
3196 | * Enables DAC state detection logic, for load-based TV detection. | |
3197 | * | |
3198 | * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set | |
3199 | * to off, for load detection to work. | |
3200 | */ | |
3201 | # define TVDAC_STATE_CHG_EN (1 << 27) | |
3202 | /* Sets the DAC A sense value to high */ | |
3203 | # define TVDAC_A_SENSE_CTL (1 << 26) | |
3204 | /* Sets the DAC B sense value to high */ | |
3205 | # define TVDAC_B_SENSE_CTL (1 << 25) | |
3206 | /* Sets the DAC C sense value to high */ | |
3207 | # define TVDAC_C_SENSE_CTL (1 << 24) | |
3208 | /* Overrides the ENC_ENABLE and DAC voltage levels */ | |
3209 | # define DAC_CTL_OVERRIDE (1 << 7) | |
3210 | /* Sets the slew rate. Must be preserved in software */ | |
3211 | # define ENC_TVDAC_SLEW_FAST (1 << 6) | |
3212 | # define DAC_A_1_3_V (0 << 4) | |
3213 | # define DAC_A_1_1_V (1 << 4) | |
3214 | # define DAC_A_0_7_V (2 << 4) | |
3215 | # define DAC_A_MASK (3 << 4) | |
3216 | # define DAC_B_1_3_V (0 << 2) | |
3217 | # define DAC_B_1_1_V (1 << 2) | |
3218 | # define DAC_B_0_7_V (2 << 2) | |
3219 | # define DAC_B_MASK (3 << 2) | |
3220 | # define DAC_C_1_3_V (0 << 0) | |
3221 | # define DAC_C_1_1_V (1 << 0) | |
3222 | # define DAC_C_0_7_V (2 << 0) | |
3223 | # define DAC_C_MASK (3 << 0) | |
3224 | ||
3225 | /* | |
3226 | * CSC coefficients are stored in a floating point format with 9 bits of | |
3227 | * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, | |
3228 | * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with | |
3229 | * -1 (0x3) being the only legal negative value. | |
3230 | */ | |
3231 | #define TV_CSC_Y 0x68010 | |
3232 | # define TV_RY_MASK 0x07ff0000 | |
3233 | # define TV_RY_SHIFT 16 | |
3234 | # define TV_GY_MASK 0x00000fff | |
3235 | # define TV_GY_SHIFT 0 | |
3236 | ||
3237 | #define TV_CSC_Y2 0x68014 | |
3238 | # define TV_BY_MASK 0x07ff0000 | |
3239 | # define TV_BY_SHIFT 16 | |
3240 | /* | |
3241 | * Y attenuation for component video. | |
3242 | * | |
3243 | * Stored in 1.9 fixed point. | |
3244 | */ | |
3245 | # define TV_AY_MASK 0x000003ff | |
3246 | # define TV_AY_SHIFT 0 | |
3247 | ||
3248 | #define TV_CSC_U 0x68018 | |
3249 | # define TV_RU_MASK 0x07ff0000 | |
3250 | # define TV_RU_SHIFT 16 | |
3251 | # define TV_GU_MASK 0x000007ff | |
3252 | # define TV_GU_SHIFT 0 | |
3253 | ||
3254 | #define TV_CSC_U2 0x6801c | |
3255 | # define TV_BU_MASK 0x07ff0000 | |
3256 | # define TV_BU_SHIFT 16 | |
3257 | /* | |
3258 | * U attenuation for component video. | |
3259 | * | |
3260 | * Stored in 1.9 fixed point. | |
3261 | */ | |
3262 | # define TV_AU_MASK 0x000003ff | |
3263 | # define TV_AU_SHIFT 0 | |
3264 | ||
3265 | #define TV_CSC_V 0x68020 | |
3266 | # define TV_RV_MASK 0x0fff0000 | |
3267 | # define TV_RV_SHIFT 16 | |
3268 | # define TV_GV_MASK 0x000007ff | |
3269 | # define TV_GV_SHIFT 0 | |
3270 | ||
3271 | #define TV_CSC_V2 0x68024 | |
3272 | # define TV_BV_MASK 0x07ff0000 | |
3273 | # define TV_BV_SHIFT 16 | |
3274 | /* | |
3275 | * V attenuation for component video. | |
3276 | * | |
3277 | * Stored in 1.9 fixed point. | |
3278 | */ | |
3279 | # define TV_AV_MASK 0x000007ff | |
3280 | # define TV_AV_SHIFT 0 | |
3281 | ||
3282 | #define TV_CLR_KNOBS 0x68028 | |
3283 | /* 2s-complement brightness adjustment */ | |
3284 | # define TV_BRIGHTNESS_MASK 0xff000000 | |
3285 | # define TV_BRIGHTNESS_SHIFT 24 | |
3286 | /* Contrast adjustment, as a 2.6 unsigned floating point number */ | |
3287 | # define TV_CONTRAST_MASK 0x00ff0000 | |
3288 | # define TV_CONTRAST_SHIFT 16 | |
3289 | /* Saturation adjustment, as a 2.6 unsigned floating point number */ | |
3290 | # define TV_SATURATION_MASK 0x0000ff00 | |
3291 | # define TV_SATURATION_SHIFT 8 | |
3292 | /* Hue adjustment, as an integer phase angle in degrees */ | |
3293 | # define TV_HUE_MASK 0x000000ff | |
3294 | # define TV_HUE_SHIFT 0 | |
3295 | ||
3296 | #define TV_CLR_LEVEL 0x6802c | |
3297 | /* Controls the DAC level for black */ | |
3298 | # define TV_BLACK_LEVEL_MASK 0x01ff0000 | |
3299 | # define TV_BLACK_LEVEL_SHIFT 16 | |
3300 | /* Controls the DAC level for blanking */ | |
3301 | # define TV_BLANK_LEVEL_MASK 0x000001ff | |
3302 | # define TV_BLANK_LEVEL_SHIFT 0 | |
3303 | ||
3304 | #define TV_H_CTL_1 0x68030 | |
3305 | /* Number of pixels in the hsync. */ | |
3306 | # define TV_HSYNC_END_MASK 0x1fff0000 | |
3307 | # define TV_HSYNC_END_SHIFT 16 | |
3308 | /* Total number of pixels minus one in the line (display and blanking). */ | |
3309 | # define TV_HTOTAL_MASK 0x00001fff | |
3310 | # define TV_HTOTAL_SHIFT 0 | |
3311 | ||
3312 | #define TV_H_CTL_2 0x68034 | |
3313 | /* Enables the colorburst (needed for non-component color) */ | |
3314 | # define TV_BURST_ENA (1 << 31) | |
3315 | /* Offset of the colorburst from the start of hsync, in pixels minus one. */ | |
3316 | # define TV_HBURST_START_SHIFT 16 | |
3317 | # define TV_HBURST_START_MASK 0x1fff0000 | |
3318 | /* Length of the colorburst */ | |
3319 | # define TV_HBURST_LEN_SHIFT 0 | |
3320 | # define TV_HBURST_LEN_MASK 0x0001fff | |
3321 | ||
3322 | #define TV_H_CTL_3 0x68038 | |
3323 | /* End of hblank, measured in pixels minus one from start of hsync */ | |
3324 | # define TV_HBLANK_END_SHIFT 16 | |
3325 | # define TV_HBLANK_END_MASK 0x1fff0000 | |
3326 | /* Start of hblank, measured in pixels minus one from start of hsync */ | |
3327 | # define TV_HBLANK_START_SHIFT 0 | |
3328 | # define TV_HBLANK_START_MASK 0x0001fff | |
3329 | ||
3330 | #define TV_V_CTL_1 0x6803c | |
3331 | /* XXX */ | |
3332 | # define TV_NBR_END_SHIFT 16 | |
3333 | # define TV_NBR_END_MASK 0x07ff0000 | |
3334 | /* XXX */ | |
3335 | # define TV_VI_END_F1_SHIFT 8 | |
3336 | # define TV_VI_END_F1_MASK 0x00003f00 | |
3337 | /* XXX */ | |
3338 | # define TV_VI_END_F2_SHIFT 0 | |
3339 | # define TV_VI_END_F2_MASK 0x0000003f | |
3340 | ||
3341 | #define TV_V_CTL_2 0x68040 | |
3342 | /* Length of vsync, in half lines */ | |
3343 | # define TV_VSYNC_LEN_MASK 0x07ff0000 | |
3344 | # define TV_VSYNC_LEN_SHIFT 16 | |
3345 | /* Offset of the start of vsync in field 1, measured in one less than the | |
3346 | * number of half lines. | |
3347 | */ | |
3348 | # define TV_VSYNC_START_F1_MASK 0x00007f00 | |
3349 | # define TV_VSYNC_START_F1_SHIFT 8 | |
3350 | /* | |
3351 | * Offset of the start of vsync in field 2, measured in one less than the | |
3352 | * number of half lines. | |
3353 | */ | |
3354 | # define TV_VSYNC_START_F2_MASK 0x0000007f | |
3355 | # define TV_VSYNC_START_F2_SHIFT 0 | |
3356 | ||
3357 | #define TV_V_CTL_3 0x68044 | |
3358 | /* Enables generation of the equalization signal */ | |
3359 | # define TV_EQUAL_ENA (1 << 31) | |
3360 | /* Length of vsync, in half lines */ | |
3361 | # define TV_VEQ_LEN_MASK 0x007f0000 | |
3362 | # define TV_VEQ_LEN_SHIFT 16 | |
3363 | /* Offset of the start of equalization in field 1, measured in one less than | |
3364 | * the number of half lines. | |
3365 | */ | |
3366 | # define TV_VEQ_START_F1_MASK 0x0007f00 | |
3367 | # define TV_VEQ_START_F1_SHIFT 8 | |
3368 | /* | |
3369 | * Offset of the start of equalization in field 2, measured in one less than | |
3370 | * the number of half lines. | |
3371 | */ | |
3372 | # define TV_VEQ_START_F2_MASK 0x000007f | |
3373 | # define TV_VEQ_START_F2_SHIFT 0 | |
3374 | ||
3375 | #define TV_V_CTL_4 0x68048 | |
3376 | /* | |
3377 | * Offset to start of vertical colorburst, measured in one less than the | |
3378 | * number of lines from vertical start. | |
3379 | */ | |
3380 | # define TV_VBURST_START_F1_MASK 0x003f0000 | |
3381 | # define TV_VBURST_START_F1_SHIFT 16 | |
3382 | /* | |
3383 | * Offset to the end of vertical colorburst, measured in one less than the | |
3384 | * number of lines from the start of NBR. | |
3385 | */ | |
3386 | # define TV_VBURST_END_F1_MASK 0x000000ff | |
3387 | # define TV_VBURST_END_F1_SHIFT 0 | |
3388 | ||
3389 | #define TV_V_CTL_5 0x6804c | |
3390 | /* | |
3391 | * Offset to start of vertical colorburst, measured in one less than the | |
3392 | * number of lines from vertical start. | |
3393 | */ | |
3394 | # define TV_VBURST_START_F2_MASK 0x003f0000 | |
3395 | # define TV_VBURST_START_F2_SHIFT 16 | |
3396 | /* | |
3397 | * Offset to the end of vertical colorburst, measured in one less than the | |
3398 | * number of lines from the start of NBR. | |
3399 | */ | |
3400 | # define TV_VBURST_END_F2_MASK 0x000000ff | |
3401 | # define TV_VBURST_END_F2_SHIFT 0 | |
3402 | ||
3403 | #define TV_V_CTL_6 0x68050 | |
3404 | /* | |
3405 | * Offset to start of vertical colorburst, measured in one less than the | |
3406 | * number of lines from vertical start. | |
3407 | */ | |
3408 | # define TV_VBURST_START_F3_MASK 0x003f0000 | |
3409 | # define TV_VBURST_START_F3_SHIFT 16 | |
3410 | /* | |
3411 | * Offset to the end of vertical colorburst, measured in one less than the | |
3412 | * number of lines from the start of NBR. | |
3413 | */ | |
3414 | # define TV_VBURST_END_F3_MASK 0x000000ff | |
3415 | # define TV_VBURST_END_F3_SHIFT 0 | |
3416 | ||
3417 | #define TV_V_CTL_7 0x68054 | |
3418 | /* | |
3419 | * Offset to start of vertical colorburst, measured in one less than the | |
3420 | * number of lines from vertical start. | |
3421 | */ | |
3422 | # define TV_VBURST_START_F4_MASK 0x003f0000 | |
3423 | # define TV_VBURST_START_F4_SHIFT 16 | |
3424 | /* | |
3425 | * Offset to the end of vertical colorburst, measured in one less than the | |
3426 | * number of lines from the start of NBR. | |
3427 | */ | |
3428 | # define TV_VBURST_END_F4_MASK 0x000000ff | |
3429 | # define TV_VBURST_END_F4_SHIFT 0 | |
3430 | ||
3431 | #define TV_SC_CTL_1 0x68060 | |
3432 | /* Turns on the first subcarrier phase generation DDA */ | |
3433 | # define TV_SC_DDA1_EN (1 << 31) | |
3434 | /* Turns on the first subcarrier phase generation DDA */ | |
3435 | # define TV_SC_DDA2_EN (1 << 30) | |
3436 | /* Turns on the first subcarrier phase generation DDA */ | |
3437 | # define TV_SC_DDA3_EN (1 << 29) | |
3438 | /* Sets the subcarrier DDA to reset frequency every other field */ | |
3439 | # define TV_SC_RESET_EVERY_2 (0 << 24) | |
3440 | /* Sets the subcarrier DDA to reset frequency every fourth field */ | |
3441 | # define TV_SC_RESET_EVERY_4 (1 << 24) | |
3442 | /* Sets the subcarrier DDA to reset frequency every eighth field */ | |
3443 | # define TV_SC_RESET_EVERY_8 (2 << 24) | |
3444 | /* Sets the subcarrier DDA to never reset the frequency */ | |
3445 | # define TV_SC_RESET_NEVER (3 << 24) | |
3446 | /* Sets the peak amplitude of the colorburst.*/ | |
3447 | # define TV_BURST_LEVEL_MASK 0x00ff0000 | |
3448 | # define TV_BURST_LEVEL_SHIFT 16 | |
3449 | /* Sets the increment of the first subcarrier phase generation DDA */ | |
3450 | # define TV_SCDDA1_INC_MASK 0x00000fff | |
3451 | # define TV_SCDDA1_INC_SHIFT 0 | |
3452 | ||
3453 | #define TV_SC_CTL_2 0x68064 | |
3454 | /* Sets the rollover for the second subcarrier phase generation DDA */ | |
3455 | # define TV_SCDDA2_SIZE_MASK 0x7fff0000 | |
3456 | # define TV_SCDDA2_SIZE_SHIFT 16 | |
3457 | /* Sets the increent of the second subcarrier phase generation DDA */ | |
3458 | # define TV_SCDDA2_INC_MASK 0x00007fff | |
3459 | # define TV_SCDDA2_INC_SHIFT 0 | |
3460 | ||
3461 | #define TV_SC_CTL_3 0x68068 | |
3462 | /* Sets the rollover for the third subcarrier phase generation DDA */ | |
3463 | # define TV_SCDDA3_SIZE_MASK 0x7fff0000 | |
3464 | # define TV_SCDDA3_SIZE_SHIFT 16 | |
3465 | /* Sets the increent of the third subcarrier phase generation DDA */ | |
3466 | # define TV_SCDDA3_INC_MASK 0x00007fff | |
3467 | # define TV_SCDDA3_INC_SHIFT 0 | |
3468 | ||
3469 | #define TV_WIN_POS 0x68070 | |
3470 | /* X coordinate of the display from the start of horizontal active */ | |
3471 | # define TV_XPOS_MASK 0x1fff0000 | |
3472 | # define TV_XPOS_SHIFT 16 | |
3473 | /* Y coordinate of the display from the start of vertical active (NBR) */ | |
3474 | # define TV_YPOS_MASK 0x00000fff | |
3475 | # define TV_YPOS_SHIFT 0 | |
3476 | ||
3477 | #define TV_WIN_SIZE 0x68074 | |
3478 | /* Horizontal size of the display window, measured in pixels*/ | |
3479 | # define TV_XSIZE_MASK 0x1fff0000 | |
3480 | # define TV_XSIZE_SHIFT 16 | |
3481 | /* | |
3482 | * Vertical size of the display window, measured in pixels. | |
3483 | * | |
3484 | * Must be even for interlaced modes. | |
3485 | */ | |
3486 | # define TV_YSIZE_MASK 0x00000fff | |
3487 | # define TV_YSIZE_SHIFT 0 | |
3488 | ||
3489 | #define TV_FILTER_CTL_1 0x68080 | |
3490 | /* | |
3491 | * Enables automatic scaling calculation. | |
3492 | * | |
3493 | * If set, the rest of the registers are ignored, and the calculated values can | |
3494 | * be read back from the register. | |
3495 | */ | |
3496 | # define TV_AUTO_SCALE (1 << 31) | |
3497 | /* | |
3498 | * Disables the vertical filter. | |
3499 | * | |
3500 | * This is required on modes more than 1024 pixels wide */ | |
3501 | # define TV_V_FILTER_BYPASS (1 << 29) | |
3502 | /* Enables adaptive vertical filtering */ | |
3503 | # define TV_VADAPT (1 << 28) | |
3504 | # define TV_VADAPT_MODE_MASK (3 << 26) | |
3505 | /* Selects the least adaptive vertical filtering mode */ | |
3506 | # define TV_VADAPT_MODE_LEAST (0 << 26) | |
3507 | /* Selects the moderately adaptive vertical filtering mode */ | |
3508 | # define TV_VADAPT_MODE_MODERATE (1 << 26) | |
3509 | /* Selects the most adaptive vertical filtering mode */ | |
3510 | # define TV_VADAPT_MODE_MOST (3 << 26) | |
3511 | /* | |
3512 | * Sets the horizontal scaling factor. | |
3513 | * | |
3514 | * This should be the fractional part of the horizontal scaling factor divided | |
3515 | * by the oversampling rate. TV_HSCALE should be less than 1, and set to: | |
3516 | * | |
3517 | * (src width - 1) / ((oversample * dest width) - 1) | |
3518 | */ | |
3519 | # define TV_HSCALE_FRAC_MASK 0x00003fff | |
3520 | # define TV_HSCALE_FRAC_SHIFT 0 | |
3521 | ||
3522 | #define TV_FILTER_CTL_2 0x68084 | |
3523 | /* | |
3524 | * Sets the integer part of the 3.15 fixed-point vertical scaling factor. | |
3525 | * | |
3526 | * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) | |
3527 | */ | |
3528 | # define TV_VSCALE_INT_MASK 0x00038000 | |
3529 | # define TV_VSCALE_INT_SHIFT 15 | |
3530 | /* | |
3531 | * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. | |
3532 | * | |
3533 | * \sa TV_VSCALE_INT_MASK | |
3534 | */ | |
3535 | # define TV_VSCALE_FRAC_MASK 0x00007fff | |
3536 | # define TV_VSCALE_FRAC_SHIFT 0 | |
3537 | ||
3538 | #define TV_FILTER_CTL_3 0x68088 | |
3539 | /* | |
3540 | * Sets the integer part of the 3.15 fixed-point vertical scaling factor. | |
3541 | * | |
3542 | * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) | |
3543 | * | |
3544 | * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. | |
3545 | */ | |
3546 | # define TV_VSCALE_IP_INT_MASK 0x00038000 | |
3547 | # define TV_VSCALE_IP_INT_SHIFT 15 | |
3548 | /* | |
3549 | * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. | |
3550 | * | |
3551 | * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. | |
3552 | * | |
3553 | * \sa TV_VSCALE_IP_INT_MASK | |
3554 | */ | |
3555 | # define TV_VSCALE_IP_FRAC_MASK 0x00007fff | |
3556 | # define TV_VSCALE_IP_FRAC_SHIFT 0 | |
3557 | ||
3558 | #define TV_CC_CONTROL 0x68090 | |
3559 | # define TV_CC_ENABLE (1 << 31) | |
3560 | /* | |
3561 | * Specifies which field to send the CC data in. | |
3562 | * | |
3563 | * CC data is usually sent in field 0. | |
3564 | */ | |
3565 | # define TV_CC_FID_MASK (1 << 27) | |
3566 | # define TV_CC_FID_SHIFT 27 | |
3567 | /* Sets the horizontal position of the CC data. Usually 135. */ | |
3568 | # define TV_CC_HOFF_MASK 0x03ff0000 | |
3569 | # define TV_CC_HOFF_SHIFT 16 | |
3570 | /* Sets the vertical position of the CC data. Usually 21 */ | |
3571 | # define TV_CC_LINE_MASK 0x0000003f | |
3572 | # define TV_CC_LINE_SHIFT 0 | |
3573 | ||
3574 | #define TV_CC_DATA 0x68094 | |
3575 | # define TV_CC_RDY (1 << 31) | |
3576 | /* Second word of CC data to be transmitted. */ | |
3577 | # define TV_CC_DATA_2_MASK 0x007f0000 | |
3578 | # define TV_CC_DATA_2_SHIFT 16 | |
3579 | /* First word of CC data to be transmitted. */ | |
3580 | # define TV_CC_DATA_1_MASK 0x0000007f | |
3581 | # define TV_CC_DATA_1_SHIFT 0 | |
3582 | ||
3583 | #define TV_H_LUMA_0 0x68100 | |
3584 | #define TV_H_LUMA_59 0x681ec | |
3585 | #define TV_H_CHROMA_0 0x68200 | |
3586 | #define TV_H_CHROMA_59 0x682ec | |
3587 | #define TV_V_LUMA_0 0x68300 | |
3588 | #define TV_V_LUMA_42 0x683a8 | |
3589 | #define TV_V_CHROMA_0 0x68400 | |
3590 | #define TV_V_CHROMA_42 0x684a8 | |
3591 | ||
3592 | /* Display Port */ | |
3593 | #define DP_A 0x64000 /* eDP */ | |
3594 | #define DP_B 0x64100 | |
3595 | #define DP_C 0x64200 | |
3596 | #define DP_D 0x64300 | |
3597 | ||
3598 | #define DP_PORT_EN (1 << 31) | |
3599 | #define DP_PIPEB_SELECT (1 << 30) | |
3600 | #define DP_PIPE_MASK (1 << 30) | |
3601 | #define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16) | |
3602 | #define DP_PIPE_MASK_CHV (3 << 16) | |
3603 | ||
3604 | /* Link training mode - select a suitable mode for each stage */ | |
3605 | #define DP_LINK_TRAIN_PAT_1 (0 << 28) | |
3606 | #define DP_LINK_TRAIN_PAT_2 (1 << 28) | |
3607 | #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) | |
3608 | #define DP_LINK_TRAIN_OFF (3 << 28) | |
3609 | #define DP_LINK_TRAIN_MASK (3 << 28) | |
3610 | #define DP_LINK_TRAIN_SHIFT 28 | |
3611 | #define DP_LINK_TRAIN_PAT_3_CHV (1 << 14) | |
3612 | #define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14)) | |
3613 | ||
3614 | /* CPT Link training mode */ | |
3615 | #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) | |
3616 | #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) | |
3617 | #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) | |
3618 | #define DP_LINK_TRAIN_OFF_CPT (3 << 8) | |
3619 | #define DP_LINK_TRAIN_MASK_CPT (7 << 8) | |
3620 | #define DP_LINK_TRAIN_SHIFT_CPT 8 | |
3621 | ||
3622 | /* Signal voltages. These are mostly controlled by the other end */ | |
3623 | #define DP_VOLTAGE_0_4 (0 << 25) | |
3624 | #define DP_VOLTAGE_0_6 (1 << 25) | |
3625 | #define DP_VOLTAGE_0_8 (2 << 25) | |
3626 | #define DP_VOLTAGE_1_2 (3 << 25) | |
3627 | #define DP_VOLTAGE_MASK (7 << 25) | |
3628 | #define DP_VOLTAGE_SHIFT 25 | |
3629 | ||
3630 | /* Signal pre-emphasis levels, like voltages, the other end tells us what | |
3631 | * they want | |
3632 | */ | |
3633 | #define DP_PRE_EMPHASIS_0 (0 << 22) | |
3634 | #define DP_PRE_EMPHASIS_3_5 (1 << 22) | |
3635 | #define DP_PRE_EMPHASIS_6 (2 << 22) | |
3636 | #define DP_PRE_EMPHASIS_9_5 (3 << 22) | |
3637 | #define DP_PRE_EMPHASIS_MASK (7 << 22) | |
3638 | #define DP_PRE_EMPHASIS_SHIFT 22 | |
3639 | ||
3640 | /* How many wires to use. I guess 3 was too hard */ | |
3641 | #define DP_PORT_WIDTH(width) (((width) - 1) << 19) | |
3642 | #define DP_PORT_WIDTH_MASK (7 << 19) | |
3643 | ||
3644 | /* Mystic DPCD version 1.1 special mode */ | |
3645 | #define DP_ENHANCED_FRAMING (1 << 18) | |
3646 | ||
3647 | /* eDP */ | |
3648 | #define DP_PLL_FREQ_270MHZ (0 << 16) | |
3649 | #define DP_PLL_FREQ_160MHZ (1 << 16) | |
3650 | #define DP_PLL_FREQ_MASK (3 << 16) | |
3651 | ||
3652 | /* locked once port is enabled */ | |
3653 | #define DP_PORT_REVERSAL (1 << 15) | |
3654 | ||
3655 | /* eDP */ | |
3656 | #define DP_PLL_ENABLE (1 << 14) | |
3657 | ||
3658 | /* sends the clock on lane 15 of the PEG for debug */ | |
3659 | #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) | |
3660 | ||
3661 | #define DP_SCRAMBLING_DISABLE (1 << 12) | |
3662 | #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) | |
3663 | ||
3664 | /* limit RGB values to avoid confusing TVs */ | |
3665 | #define DP_COLOR_RANGE_16_235 (1 << 8) | |
3666 | ||
3667 | /* Turn on the audio link */ | |
3668 | #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) | |
3669 | ||
3670 | /* vs and hs sync polarity */ | |
3671 | #define DP_SYNC_VS_HIGH (1 << 4) | |
3672 | #define DP_SYNC_HS_HIGH (1 << 3) | |
3673 | ||
3674 | /* A fantasy */ | |
3675 | #define DP_DETECTED (1 << 2) | |
3676 | ||
3677 | /* The aux channel provides a way to talk to the | |
3678 | * signal sink for DDC etc. Max packet size supported | |
3679 | * is 20 bytes in each direction, hence the 5 fixed | |
3680 | * data registers | |
3681 | */ | |
3682 | #define DPA_AUX_CH_CTL 0x64010 | |
3683 | #define DPA_AUX_CH_DATA1 0x64014 | |
3684 | #define DPA_AUX_CH_DATA2 0x64018 | |
3685 | #define DPA_AUX_CH_DATA3 0x6401c | |
3686 | #define DPA_AUX_CH_DATA4 0x64020 | |
3687 | #define DPA_AUX_CH_DATA5 0x64024 | |
3688 | ||
3689 | #define DPB_AUX_CH_CTL 0x64110 | |
3690 | #define DPB_AUX_CH_DATA1 0x64114 | |
3691 | #define DPB_AUX_CH_DATA2 0x64118 | |
3692 | #define DPB_AUX_CH_DATA3 0x6411c | |
3693 | #define DPB_AUX_CH_DATA4 0x64120 | |
3694 | #define DPB_AUX_CH_DATA5 0x64124 | |
3695 | ||
3696 | #define DPC_AUX_CH_CTL 0x64210 | |
3697 | #define DPC_AUX_CH_DATA1 0x64214 | |
3698 | #define DPC_AUX_CH_DATA2 0x64218 | |
3699 | #define DPC_AUX_CH_DATA3 0x6421c | |
3700 | #define DPC_AUX_CH_DATA4 0x64220 | |
3701 | #define DPC_AUX_CH_DATA5 0x64224 | |
3702 | ||
3703 | #define DPD_AUX_CH_CTL 0x64310 | |
3704 | #define DPD_AUX_CH_DATA1 0x64314 | |
3705 | #define DPD_AUX_CH_DATA2 0x64318 | |
3706 | #define DPD_AUX_CH_DATA3 0x6431c | |
3707 | #define DPD_AUX_CH_DATA4 0x64320 | |
3708 | #define DPD_AUX_CH_DATA5 0x64324 | |
3709 | ||
3710 | #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) | |
3711 | #define DP_AUX_CH_CTL_DONE (1 << 30) | |
3712 | #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) | |
3713 | #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) | |
3714 | #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) | |
3715 | #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) | |
3716 | #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) | |
3717 | #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) | |
3718 | #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) | |
3719 | #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) | |
3720 | #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) | |
3721 | #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 | |
3722 | #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) | |
3723 | #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 | |
3724 | #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) | |
3725 | #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) | |
3726 | #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) | |
3727 | #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) | |
3728 | #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) | |
3729 | #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) | |
3730 | #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 | |
3731 | #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) | |
3732 | ||
3733 | /* | |
3734 | * Computing GMCH M and N values for the Display Port link | |
3735 | * | |
3736 | * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes | |
3737 | * | |
3738 | * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) | |
3739 | * | |
3740 | * The GMCH value is used internally | |
3741 | * | |
3742 | * bytes_per_pixel is the number of bytes coming out of the plane, | |
3743 | * which is after the LUTs, so we want the bytes for our color format. | |
3744 | * For our current usage, this is always 3, one byte for R, G and B. | |
3745 | */ | |
3746 | #define _PIPEA_DATA_M_G4X 0x70050 | |
3747 | #define _PIPEB_DATA_M_G4X 0x71050 | |
3748 | ||
3749 | /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ | |
3750 | #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ | |
3751 | #define TU_SIZE_SHIFT 25 | |
3752 | #define TU_SIZE_MASK (0x3f << 25) | |
3753 | ||
3754 | #define DATA_LINK_M_N_MASK (0xffffff) | |
3755 | #define DATA_LINK_N_MAX (0x800000) | |
3756 | ||
3757 | #define _PIPEA_DATA_N_G4X 0x70054 | |
3758 | #define _PIPEB_DATA_N_G4X 0x71054 | |
3759 | #define PIPE_GMCH_DATA_N_MASK (0xffffff) | |
3760 | ||
3761 | /* | |
3762 | * Computing Link M and N values for the Display Port link | |
3763 | * | |
3764 | * Link M / N = pixel_clock / ls_clk | |
3765 | * | |
3766 | * (the DP spec calls pixel_clock the 'strm_clk') | |
3767 | * | |
3768 | * The Link value is transmitted in the Main Stream | |
3769 | * Attributes and VB-ID. | |
3770 | */ | |
3771 | ||
3772 | #define _PIPEA_LINK_M_G4X 0x70060 | |
3773 | #define _PIPEB_LINK_M_G4X 0x71060 | |
3774 | #define PIPEA_DP_LINK_M_MASK (0xffffff) | |
3775 | ||
3776 | #define _PIPEA_LINK_N_G4X 0x70064 | |
3777 | #define _PIPEB_LINK_N_G4X 0x71064 | |
3778 | #define PIPEA_DP_LINK_N_MASK (0xffffff) | |
3779 | ||
3780 | #define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) | |
3781 | #define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) | |
3782 | #define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) | |
3783 | #define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) | |
3784 | ||
3785 | /* Display & cursor control */ | |
3786 | ||
3787 | /* Pipe A */ | |
3788 | #define _PIPEADSL 0x70000 | |
3789 | #define DSL_LINEMASK_GEN2 0x00000fff | |
3790 | #define DSL_LINEMASK_GEN3 0x00001fff | |
3791 | #define _PIPEACONF 0x70008 | |
3792 | #define PIPECONF_ENABLE (1<<31) | |
3793 | #define PIPECONF_DISABLE 0 | |
3794 | #define PIPECONF_DOUBLE_WIDE (1<<30) | |
3795 | #define I965_PIPECONF_ACTIVE (1<<30) | |
3796 | #define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */ | |
3797 | #define PIPECONF_FRAME_START_DELAY_MASK (3<<27) | |
3798 | #define PIPECONF_SINGLE_WIDE 0 | |
3799 | #define PIPECONF_PIPE_UNLOCKED 0 | |
3800 | #define PIPECONF_PIPE_LOCKED (1<<25) | |
3801 | #define PIPECONF_PALETTE 0 | |
3802 | #define PIPECONF_GAMMA (1<<24) | |
3803 | #define PIPECONF_FORCE_BORDER (1<<25) | |
3804 | #define PIPECONF_INTERLACE_MASK (7 << 21) | |
3805 | #define PIPECONF_INTERLACE_MASK_HSW (3 << 21) | |
3806 | /* Note that pre-gen3 does not support interlaced display directly. Panel | |
3807 | * fitting must be disabled on pre-ilk for interlaced. */ | |
3808 | #define PIPECONF_PROGRESSIVE (0 << 21) | |
3809 | #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ | |
3810 | #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ | |
3811 | #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) | |
3812 | #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ | |
3813 | /* Ironlake and later have a complete new set of values for interlaced. PFIT | |
3814 | * means panel fitter required, PF means progressive fetch, DBL means power | |
3815 | * saving pixel doubling. */ | |
3816 | #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) | |
3817 | #define PIPECONF_INTERLACED_ILK (3 << 21) | |
3818 | #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ | |
3819 | #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ | |
3820 | #define PIPECONF_INTERLACE_MODE_MASK (7 << 21) | |
3821 | #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20) | |
3822 | #define PIPECONF_CXSR_DOWNCLOCK (1<<16) | |
3823 | #define PIPECONF_COLOR_RANGE_SELECT (1 << 13) | |
3824 | #define PIPECONF_BPC_MASK (0x7 << 5) | |
3825 | #define PIPECONF_8BPC (0<<5) | |
3826 | #define PIPECONF_10BPC (1<<5) | |
3827 | #define PIPECONF_6BPC (2<<5) | |
3828 | #define PIPECONF_12BPC (3<<5) | |
3829 | #define PIPECONF_DITHER_EN (1<<4) | |
3830 | #define PIPECONF_DITHER_TYPE_MASK (0x0000000c) | |
3831 | #define PIPECONF_DITHER_TYPE_SP (0<<2) | |
3832 | #define PIPECONF_DITHER_TYPE_ST1 (1<<2) | |
3833 | #define PIPECONF_DITHER_TYPE_ST2 (2<<2) | |
3834 | #define PIPECONF_DITHER_TYPE_TEMP (3<<2) | |
3835 | #define _PIPEASTAT 0x70024 | |
3836 | #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) | |
3837 | #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30) | |
3838 | #define PIPE_CRC_ERROR_ENABLE (1UL<<29) | |
3839 | #define PIPE_CRC_DONE_ENABLE (1UL<<28) | |
3840 | #define PERF_COUNTER2_INTERRUPT_EN (1UL<<27) | |
3841 | #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) | |
3842 | #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26) | |
3843 | #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) | |
3844 | #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) | |
3845 | #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) | |
3846 | #define PIPE_DPST_EVENT_ENABLE (1UL<<23) | |
3847 | #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22) | |
3848 | #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) | |
3849 | #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) | |
3850 | #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) | |
3851 | #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19) | |
3852 | #define PERF_COUNTER_INTERRUPT_EN (1UL<<19) | |
3853 | #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ | |
3854 | #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ | |
3855 | #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17) | |
3856 | #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) | |
3857 | #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16) | |
3858 | #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) | |
3859 | #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15) | |
3860 | #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14) | |
3861 | #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) | |
3862 | #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) | |
3863 | #define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11) | |
3864 | #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) | |
3865 | #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10) | |
3866 | #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) | |
3867 | #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) | |
3868 | #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) | |
3869 | #define PIPE_DPST_EVENT_STATUS (1UL<<7) | |
3870 | #define PIPE_A_PSR_STATUS_VLV (1UL<<6) | |
3871 | #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) | |
3872 | #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) | |
3873 | #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) | |
3874 | #define PIPE_B_PSR_STATUS_VLV (1UL<<3) | |
3875 | #define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3) | |
3876 | #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ | |
3877 | #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ | |
3878 | #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1) | |
3879 | #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) | |
3880 | #define PIPE_HBLANK_INT_STATUS (1UL<<0) | |
3881 | #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) | |
3882 | ||
3883 | #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 | |
3884 | #define PIPESTAT_INT_STATUS_MASK 0x0000ffff | |
3885 | ||
3886 | #define PIPE_A_OFFSET 0x70000 | |
3887 | #define PIPE_B_OFFSET 0x71000 | |
3888 | #define PIPE_C_OFFSET 0x72000 | |
3889 | #define CHV_PIPE_C_OFFSET 0x74000 | |
3890 | /* | |
3891 | * There's actually no pipe EDP. Some pipe registers have | |
3892 | * simply shifted from the pipe to the transcoder, while | |
3893 | * keeping their original offset. Thus we need PIPE_EDP_OFFSET | |
3894 | * to access such registers in transcoder EDP. | |
3895 | */ | |
3896 | #define PIPE_EDP_OFFSET 0x7f000 | |
3897 | ||
3898 | #define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \ | |
3899 | dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \ | |
3900 | dev_priv->info.display_mmio_offset) | |
3901 | ||
3902 | #define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF) | |
3903 | #define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL) | |
3904 | #define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH) | |
3905 | #define PIPEFRAMEPIXEL(pipe) _PIPE2(pipe, _PIPEAFRAMEPIXEL) | |
3906 | #define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT) | |
3907 | ||
3908 | #define _PIPE_MISC_A 0x70030 | |
3909 | #define _PIPE_MISC_B 0x71030 | |
3910 | #define PIPEMISC_DITHER_BPC_MASK (7<<5) | |
3911 | #define PIPEMISC_DITHER_8_BPC (0<<5) | |
3912 | #define PIPEMISC_DITHER_10_BPC (1<<5) | |
3913 | #define PIPEMISC_DITHER_6_BPC (2<<5) | |
3914 | #define PIPEMISC_DITHER_12_BPC (3<<5) | |
3915 | #define PIPEMISC_DITHER_ENABLE (1<<4) | |
3916 | #define PIPEMISC_DITHER_TYPE_MASK (3<<2) | |
3917 | #define PIPEMISC_DITHER_TYPE_SP (0<<2) | |
3918 | #define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A) | |
3919 | ||
3920 | #define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028) | |
3921 | #define PIPEB_LINE_COMPARE_INT_EN (1<<29) | |
3922 | #define PIPEB_HLINE_INT_EN (1<<28) | |
3923 | #define PIPEB_VBLANK_INT_EN (1<<27) | |
3924 | #define SPRITED_FLIP_DONE_INT_EN (1<<26) | |
3925 | #define SPRITEC_FLIP_DONE_INT_EN (1<<25) | |
3926 | #define PLANEB_FLIP_DONE_INT_EN (1<<24) | |
3927 | #define PIPE_PSR_INT_EN (1<<22) | |
3928 | #define PIPEA_LINE_COMPARE_INT_EN (1<<21) | |
3929 | #define PIPEA_HLINE_INT_EN (1<<20) | |
3930 | #define PIPEA_VBLANK_INT_EN (1<<19) | |
3931 | #define SPRITEB_FLIP_DONE_INT_EN (1<<18) | |
3932 | #define SPRITEA_FLIP_DONE_INT_EN (1<<17) | |
3933 | #define PLANEA_FLIPDONE_INT_EN (1<<16) | |
3934 | #define PIPEC_LINE_COMPARE_INT_EN (1<<13) | |
3935 | #define PIPEC_HLINE_INT_EN (1<<12) | |
3936 | #define PIPEC_VBLANK_INT_EN (1<<11) | |
3937 | #define SPRITEF_FLIPDONE_INT_EN (1<<10) | |
3938 | #define SPRITEE_FLIPDONE_INT_EN (1<<9) | |
3939 | #define PLANEC_FLIPDONE_INT_EN (1<<8) | |
3940 | ||
3941 | #define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ | |
3942 | #define SPRITEF_INVALID_GTT_INT_EN (1<<27) | |
3943 | #define SPRITEE_INVALID_GTT_INT_EN (1<<26) | |
3944 | #define PLANEC_INVALID_GTT_INT_EN (1<<25) | |
3945 | #define CURSORC_INVALID_GTT_INT_EN (1<<24) | |
3946 | #define CURSORB_INVALID_GTT_INT_EN (1<<23) | |
3947 | #define CURSORA_INVALID_GTT_INT_EN (1<<22) | |
3948 | #define SPRITED_INVALID_GTT_INT_EN (1<<21) | |
3949 | #define SPRITEC_INVALID_GTT_INT_EN (1<<20) | |
3950 | #define PLANEB_INVALID_GTT_INT_EN (1<<19) | |
3951 | #define SPRITEB_INVALID_GTT_INT_EN (1<<18) | |
3952 | #define SPRITEA_INVALID_GTT_INT_EN (1<<17) | |
3953 | #define PLANEA_INVALID_GTT_INT_EN (1<<16) | |
3954 | #define DPINVGTT_EN_MASK 0xff0000 | |
3955 | #define DPINVGTT_EN_MASK_CHV 0xfff0000 | |
3956 | #define SPRITEF_INVALID_GTT_STATUS (1<<11) | |
3957 | #define SPRITEE_INVALID_GTT_STATUS (1<<10) | |
3958 | #define PLANEC_INVALID_GTT_STATUS (1<<9) | |
3959 | #define CURSORC_INVALID_GTT_STATUS (1<<8) | |
3960 | #define CURSORB_INVALID_GTT_STATUS (1<<7) | |
3961 | #define CURSORA_INVALID_GTT_STATUS (1<<6) | |
3962 | #define SPRITED_INVALID_GTT_STATUS (1<<5) | |
3963 | #define SPRITEC_INVALID_GTT_STATUS (1<<4) | |
3964 | #define PLANEB_INVALID_GTT_STATUS (1<<3) | |
3965 | #define SPRITEB_INVALID_GTT_STATUS (1<<2) | |
3966 | #define SPRITEA_INVALID_GTT_STATUS (1<<1) | |
3967 | #define PLANEA_INVALID_GTT_STATUS (1<<0) | |
3968 | #define DPINVGTT_STATUS_MASK 0xff | |
3969 | #define DPINVGTT_STATUS_MASK_CHV 0xfff | |
3970 | ||
3971 | #define DSPARB 0x70030 | |
3972 | #define DSPARB_CSTART_MASK (0x7f << 7) | |
3973 | #define DSPARB_CSTART_SHIFT 7 | |
3974 | #define DSPARB_BSTART_MASK (0x7f) | |
3975 | #define DSPARB_BSTART_SHIFT 0 | |
3976 | #define DSPARB_BEND_SHIFT 9 /* on 855 */ | |
3977 | #define DSPARB_AEND_SHIFT 0 | |
3978 | ||
3979 | /* pnv/gen4/g4x/vlv/chv */ | |
3980 | #define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034) | |
3981 | #define DSPFW_SR_SHIFT 23 | |
3982 | #define DSPFW_SR_MASK (0x1ff<<23) | |
3983 | #define DSPFW_CURSORB_SHIFT 16 | |
3984 | #define DSPFW_CURSORB_MASK (0x3f<<16) | |
3985 | #define DSPFW_PLANEB_SHIFT 8 | |
3986 | #define DSPFW_PLANEB_MASK (0x7f<<8) | |
3987 | #define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */ | |
3988 | #define DSPFW_PLANEA_SHIFT 0 | |
3989 | #define DSPFW_PLANEA_MASK (0x7f<<0) | |
3990 | #define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */ | |
3991 | #define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038) | |
3992 | #define DSPFW_FBC_SR_EN (1<<31) /* g4x */ | |
3993 | #define DSPFW_FBC_SR_SHIFT 28 | |
3994 | #define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */ | |
3995 | #define DSPFW_FBC_HPLL_SR_SHIFT 24 | |
3996 | #define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */ | |
3997 | #define DSPFW_SPRITEB_SHIFT (16) | |
3998 | #define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */ | |
3999 | #define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */ | |
4000 | #define DSPFW_CURSORA_SHIFT 8 | |
4001 | #define DSPFW_CURSORA_MASK (0x3f<<8) | |
4002 | #define DSPFW_PLANEC_SHIFT_OLD 0 | |
4003 | #define DSPFW_PLANEC_MASK_OLD (0x7f<<0) /* pre-gen4 sprite C */ | |
4004 | #define DSPFW_SPRITEA_SHIFT 0 | |
4005 | #define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */ | |
4006 | #define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */ | |
4007 | #define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c) | |
4008 | #define DSPFW_HPLL_SR_EN (1<<31) | |
4009 | #define PINEVIEW_SELF_REFRESH_EN (1<<30) | |
4010 | #define DSPFW_CURSOR_SR_SHIFT 24 | |
4011 | #define DSPFW_CURSOR_SR_MASK (0x3f<<24) | |
4012 | #define DSPFW_HPLL_CURSOR_SHIFT 16 | |
4013 | #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) | |
4014 | #define DSPFW_HPLL_SR_SHIFT 0 | |
4015 | #define DSPFW_HPLL_SR_MASK (0x1ff<<0) | |
4016 | ||
4017 | /* vlv/chv */ | |
4018 | #define DSPFW4 (VLV_DISPLAY_BASE + 0x70070) | |
4019 | #define DSPFW_SPRITEB_WM1_SHIFT 16 | |
4020 | #define DSPFW_SPRITEB_WM1_MASK (0xff<<16) | |
4021 | #define DSPFW_CURSORA_WM1_SHIFT 8 | |
4022 | #define DSPFW_CURSORA_WM1_MASK (0x3f<<8) | |
4023 | #define DSPFW_SPRITEA_WM1_SHIFT 0 | |
4024 | #define DSPFW_SPRITEA_WM1_MASK (0xff<<0) | |
4025 | #define DSPFW5 (VLV_DISPLAY_BASE + 0x70074) | |
4026 | #define DSPFW_PLANEB_WM1_SHIFT 24 | |
4027 | #define DSPFW_PLANEB_WM1_MASK (0xff<<24) | |
4028 | #define DSPFW_PLANEA_WM1_SHIFT 16 | |
4029 | #define DSPFW_PLANEA_WM1_MASK (0xff<<16) | |
4030 | #define DSPFW_CURSORB_WM1_SHIFT 8 | |
4031 | #define DSPFW_CURSORB_WM1_MASK (0x3f<<8) | |
4032 | #define DSPFW_CURSOR_SR_WM1_SHIFT 0 | |
4033 | #define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0) | |
4034 | #define DSPFW6 (VLV_DISPLAY_BASE + 0x70078) | |
4035 | #define DSPFW_SR_WM1_SHIFT 0 | |
4036 | #define DSPFW_SR_WM1_MASK (0x1ff<<0) | |
4037 | #define DSPFW7 (VLV_DISPLAY_BASE + 0x7007c) | |
4038 | #define DSPFW7_CHV (VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ | |
4039 | #define DSPFW_SPRITED_WM1_SHIFT 24 | |
4040 | #define DSPFW_SPRITED_WM1_MASK (0xff<<24) | |
4041 | #define DSPFW_SPRITED_SHIFT 16 | |
4042 | #define DSPFW_SPRITED_MASK (0xff<<16) | |
4043 | #define DSPFW_SPRITEC_WM1_SHIFT 8 | |
4044 | #define DSPFW_SPRITEC_WM1_MASK (0xff<<8) | |
4045 | #define DSPFW_SPRITEC_SHIFT 0 | |
4046 | #define DSPFW_SPRITEC_MASK (0xff<<0) | |
4047 | #define DSPFW8_CHV (VLV_DISPLAY_BASE + 0x700b8) | |
4048 | #define DSPFW_SPRITEF_WM1_SHIFT 24 | |
4049 | #define DSPFW_SPRITEF_WM1_MASK (0xff<<24) | |
4050 | #define DSPFW_SPRITEF_SHIFT 16 | |
4051 | #define DSPFW_SPRITEF_MASK (0xff<<16) | |
4052 | #define DSPFW_SPRITEE_WM1_SHIFT 8 | |
4053 | #define DSPFW_SPRITEE_WM1_MASK (0xff<<8) | |
4054 | #define DSPFW_SPRITEE_SHIFT 0 | |
4055 | #define DSPFW_SPRITEE_MASK (0xff<<0) | |
4056 | #define DSPFW9_CHV (VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ | |
4057 | #define DSPFW_PLANEC_WM1_SHIFT 24 | |
4058 | #define DSPFW_PLANEC_WM1_MASK (0xff<<24) | |
4059 | #define DSPFW_PLANEC_SHIFT 16 | |
4060 | #define DSPFW_PLANEC_MASK (0xff<<16) | |
4061 | #define DSPFW_CURSORC_WM1_SHIFT 8 | |
4062 | #define DSPFW_CURSORC_WM1_MASK (0x3f<<16) | |
4063 | #define DSPFW_CURSORC_SHIFT 0 | |
4064 | #define DSPFW_CURSORC_MASK (0x3f<<0) | |
4065 | ||
4066 | /* vlv/chv high order bits */ | |
4067 | #define DSPHOWM (VLV_DISPLAY_BASE + 0x70064) | |
4068 | #define DSPFW_SR_HI_SHIFT 24 | |
4069 | #define DSPFW_SR_HI_MASK (1<<24) | |
4070 | #define DSPFW_SPRITEF_HI_SHIFT 23 | |
4071 | #define DSPFW_SPRITEF_HI_MASK (1<<23) | |
4072 | #define DSPFW_SPRITEE_HI_SHIFT 22 | |
4073 | #define DSPFW_SPRITEE_HI_MASK (1<<22) | |
4074 | #define DSPFW_PLANEC_HI_SHIFT 21 | |
4075 | #define DSPFW_PLANEC_HI_MASK (1<<21) | |
4076 | #define DSPFW_SPRITED_HI_SHIFT 20 | |
4077 | #define DSPFW_SPRITED_HI_MASK (1<<20) | |
4078 | #define DSPFW_SPRITEC_HI_SHIFT 16 | |
4079 | #define DSPFW_SPRITEC_HI_MASK (1<<16) | |
4080 | #define DSPFW_PLANEB_HI_SHIFT 12 | |
4081 | #define DSPFW_PLANEB_HI_MASK (1<<12) | |
4082 | #define DSPFW_SPRITEB_HI_SHIFT 8 | |
4083 | #define DSPFW_SPRITEB_HI_MASK (1<<8) | |
4084 | #define DSPFW_SPRITEA_HI_SHIFT 4 | |
4085 | #define DSPFW_SPRITEA_HI_MASK (1<<4) | |
4086 | #define DSPFW_PLANEA_HI_SHIFT 0 | |
4087 | #define DSPFW_PLANEA_HI_MASK (1<<0) | |
4088 | #define DSPHOWM1 (VLV_DISPLAY_BASE + 0x70068) | |
4089 | #define DSPFW_SR_WM1_HI_SHIFT 24 | |
4090 | #define DSPFW_SR_WM1_HI_MASK (1<<24) | |
4091 | #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 | |
4092 | #define DSPFW_SPRITEF_WM1_HI_MASK (1<<23) | |
4093 | #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 | |
4094 | #define DSPFW_SPRITEE_WM1_HI_MASK (1<<22) | |
4095 | #define DSPFW_PLANEC_WM1_HI_SHIFT 21 | |
4096 | #define DSPFW_PLANEC_WM1_HI_MASK (1<<21) | |
4097 | #define DSPFW_SPRITED_WM1_HI_SHIFT 20 | |
4098 | #define DSPFW_SPRITED_WM1_HI_MASK (1<<20) | |
4099 | #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 | |
4100 | #define DSPFW_SPRITEC_WM1_HI_MASK (1<<16) | |
4101 | #define DSPFW_PLANEB_WM1_HI_SHIFT 12 | |
4102 | #define DSPFW_PLANEB_WM1_HI_MASK (1<<12) | |
4103 | #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 | |
4104 | #define DSPFW_SPRITEB_WM1_HI_MASK (1<<8) | |
4105 | #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 | |
4106 | #define DSPFW_SPRITEA_WM1_HI_MASK (1<<4) | |
4107 | #define DSPFW_PLANEA_WM1_HI_SHIFT 0 | |
4108 | #define DSPFW_PLANEA_WM1_HI_MASK (1<<0) | |
4109 | ||
4110 | /* drain latency register values*/ | |
4111 | #define DRAIN_LATENCY_PRECISION_16 16 | |
4112 | #define DRAIN_LATENCY_PRECISION_32 32 | |
4113 | #define DRAIN_LATENCY_PRECISION_64 64 | |
4114 | #define VLV_DDL(pipe) (VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) | |
4115 | #define DDL_CURSOR_PRECISION_HIGH (1<<31) | |
4116 | #define DDL_CURSOR_PRECISION_LOW (0<<31) | |
4117 | #define DDL_CURSOR_SHIFT 24 | |
4118 | #define DDL_SPRITE_PRECISION_HIGH(sprite) (1<<(15+8*(sprite))) | |
4119 | #define DDL_SPRITE_PRECISION_LOW(sprite) (0<<(15+8*(sprite))) | |
4120 | #define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite)) | |
4121 | #define DDL_PLANE_PRECISION_HIGH (1<<7) | |
4122 | #define DDL_PLANE_PRECISION_LOW (0<<7) | |
4123 | #define DDL_PLANE_SHIFT 0 | |
4124 | #define DRAIN_LATENCY_MASK 0x7f | |
4125 | ||
4126 | /* FIFO watermark sizes etc */ | |
4127 | #define G4X_FIFO_LINE_SIZE 64 | |
4128 | #define I915_FIFO_LINE_SIZE 64 | |
4129 | #define I830_FIFO_LINE_SIZE 32 | |
4130 | ||
4131 | #define VALLEYVIEW_FIFO_SIZE 255 | |
4132 | #define G4X_FIFO_SIZE 127 | |
4133 | #define I965_FIFO_SIZE 512 | |
4134 | #define I945_FIFO_SIZE 127 | |
4135 | #define I915_FIFO_SIZE 95 | |
4136 | #define I855GM_FIFO_SIZE 127 /* In cachelines */ | |
4137 | #define I830_FIFO_SIZE 95 | |
4138 | ||
4139 | #define VALLEYVIEW_MAX_WM 0xff | |
4140 | #define G4X_MAX_WM 0x3f | |
4141 | #define I915_MAX_WM 0x3f | |
4142 | ||
4143 | #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ | |
4144 | #define PINEVIEW_FIFO_LINE_SIZE 64 | |
4145 | #define PINEVIEW_MAX_WM 0x1ff | |
4146 | #define PINEVIEW_DFT_WM 0x3f | |
4147 | #define PINEVIEW_DFT_HPLLOFF_WM 0 | |
4148 | #define PINEVIEW_GUARD_WM 10 | |
4149 | #define PINEVIEW_CURSOR_FIFO 64 | |
4150 | #define PINEVIEW_CURSOR_MAX_WM 0x3f | |
4151 | #define PINEVIEW_CURSOR_DFT_WM 0 | |
4152 | #define PINEVIEW_CURSOR_GUARD_WM 5 | |
4153 | ||
4154 | #define VALLEYVIEW_CURSOR_MAX_WM 64 | |
4155 | #define I965_CURSOR_FIFO 64 | |
4156 | #define I965_CURSOR_MAX_WM 32 | |
4157 | #define I965_CURSOR_DFT_WM 8 | |
4158 | ||
4159 | /* Watermark register definitions for SKL */ | |
4160 | #define CUR_WM_A_0 0x70140 | |
4161 | #define CUR_WM_B_0 0x71140 | |
4162 | #define PLANE_WM_1_A_0 0x70240 | |
4163 | #define PLANE_WM_1_B_0 0x71240 | |
4164 | #define PLANE_WM_2_A_0 0x70340 | |
4165 | #define PLANE_WM_2_B_0 0x71340 | |
4166 | #define PLANE_WM_TRANS_1_A_0 0x70268 | |
4167 | #define PLANE_WM_TRANS_1_B_0 0x71268 | |
4168 | #define PLANE_WM_TRANS_2_A_0 0x70368 | |
4169 | #define PLANE_WM_TRANS_2_B_0 0x71368 | |
4170 | #define CUR_WM_TRANS_A_0 0x70168 | |
4171 | #define CUR_WM_TRANS_B_0 0x71168 | |
4172 | #define PLANE_WM_EN (1 << 31) | |
4173 | #define PLANE_WM_LINES_SHIFT 14 | |
4174 | #define PLANE_WM_LINES_MASK 0x1f | |
4175 | #define PLANE_WM_BLOCKS_MASK 0x3ff | |
4176 | ||
4177 | #define CUR_WM_0(pipe) _PIPE(pipe, CUR_WM_A_0, CUR_WM_B_0) | |
4178 | #define CUR_WM(pipe, level) (CUR_WM_0(pipe) + ((4) * (level))) | |
4179 | #define CUR_WM_TRANS(pipe) _PIPE(pipe, CUR_WM_TRANS_A_0, CUR_WM_TRANS_B_0) | |
4180 | ||
4181 | #define _PLANE_WM_1(pipe) _PIPE(pipe, PLANE_WM_1_A_0, PLANE_WM_1_B_0) | |
4182 | #define _PLANE_WM_2(pipe) _PIPE(pipe, PLANE_WM_2_A_0, PLANE_WM_2_B_0) | |
4183 | #define _PLANE_WM_BASE(pipe, plane) \ | |
4184 | _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) | |
4185 | #define PLANE_WM(pipe, plane, level) \ | |
4186 | (_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) | |
4187 | #define _PLANE_WM_TRANS_1(pipe) \ | |
4188 | _PIPE(pipe, PLANE_WM_TRANS_1_A_0, PLANE_WM_TRANS_1_B_0) | |
4189 | #define _PLANE_WM_TRANS_2(pipe) \ | |
4190 | _PIPE(pipe, PLANE_WM_TRANS_2_A_0, PLANE_WM_TRANS_2_B_0) | |
4191 | #define PLANE_WM_TRANS(pipe, plane) \ | |
4192 | _PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)) | |
4193 | ||
4194 | /* define the Watermark register on Ironlake */ | |
4195 | #define WM0_PIPEA_ILK 0x45100 | |
4196 | #define WM0_PIPE_PLANE_MASK (0xffff<<16) | |
4197 | #define WM0_PIPE_PLANE_SHIFT 16 | |
4198 | #define WM0_PIPE_SPRITE_MASK (0xff<<8) | |
4199 | #define WM0_PIPE_SPRITE_SHIFT 8 | |
4200 | #define WM0_PIPE_CURSOR_MASK (0xff) | |
4201 | ||
4202 | #define WM0_PIPEB_ILK 0x45104 | |
4203 | #define WM0_PIPEC_IVB 0x45200 | |
4204 | #define WM1_LP_ILK 0x45108 | |
4205 | #define WM1_LP_SR_EN (1<<31) | |
4206 | #define WM1_LP_LATENCY_SHIFT 24 | |
4207 | #define WM1_LP_LATENCY_MASK (0x7f<<24) | |
4208 | #define WM1_LP_FBC_MASK (0xf<<20) | |
4209 | #define WM1_LP_FBC_SHIFT 20 | |
4210 | #define WM1_LP_FBC_SHIFT_BDW 19 | |
4211 | #define WM1_LP_SR_MASK (0x7ff<<8) | |
4212 | #define WM1_LP_SR_SHIFT 8 | |
4213 | #define WM1_LP_CURSOR_MASK (0xff) | |
4214 | #define WM2_LP_ILK 0x4510c | |
4215 | #define WM2_LP_EN (1<<31) | |
4216 | #define WM3_LP_ILK 0x45110 | |
4217 | #define WM3_LP_EN (1<<31) | |
4218 | #define WM1S_LP_ILK 0x45120 | |
4219 | #define WM2S_LP_IVB 0x45124 | |
4220 | #define WM3S_LP_IVB 0x45128 | |
4221 | #define WM1S_LP_EN (1<<31) | |
4222 | ||
4223 | #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \ | |
4224 | (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \ | |
4225 | ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur)) | |
4226 | ||
4227 | /* Memory latency timer register */ | |
4228 | #define MLTR_ILK 0x11222 | |
4229 | #define MLTR_WM1_SHIFT 0 | |
4230 | #define MLTR_WM2_SHIFT 8 | |
4231 | /* the unit of memory self-refresh latency time is 0.5us */ | |
4232 | #define ILK_SRLT_MASK 0x3f | |
4233 | ||
4234 | ||
4235 | /* the address where we get all kinds of latency value */ | |
4236 | #define SSKPD 0x5d10 | |
4237 | #define SSKPD_WM_MASK 0x3f | |
4238 | #define SSKPD_WM0_SHIFT 0 | |
4239 | #define SSKPD_WM1_SHIFT 8 | |
4240 | #define SSKPD_WM2_SHIFT 16 | |
4241 | #define SSKPD_WM3_SHIFT 24 | |
4242 | ||
4243 | /* | |
4244 | * The two pipe frame counter registers are not synchronized, so | |
4245 | * reading a stable value is somewhat tricky. The following code | |
4246 | * should work: | |
4247 | * | |
4248 | * do { | |
4249 | * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> | |
4250 | * PIPE_FRAME_HIGH_SHIFT; | |
4251 | * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> | |
4252 | * PIPE_FRAME_LOW_SHIFT); | |
4253 | * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> | |
4254 | * PIPE_FRAME_HIGH_SHIFT); | |
4255 | * } while (high1 != high2); | |
4256 | * frame = (high1 << 8) | low1; | |
4257 | */ | |
4258 | #define _PIPEAFRAMEHIGH 0x70040 | |
4259 | #define PIPE_FRAME_HIGH_MASK 0x0000ffff | |
4260 | #define PIPE_FRAME_HIGH_SHIFT 0 | |
4261 | #define _PIPEAFRAMEPIXEL 0x70044 | |
4262 | #define PIPE_FRAME_LOW_MASK 0xff000000 | |
4263 | #define PIPE_FRAME_LOW_SHIFT 24 | |
4264 | #define PIPE_PIXEL_MASK 0x00ffffff | |
4265 | #define PIPE_PIXEL_SHIFT 0 | |
4266 | /* GM45+ just has to be different */ | |
4267 | #define _PIPEA_FRMCOUNT_GM45 0x70040 | |
4268 | #define _PIPEA_FLIPCOUNT_GM45 0x70044 | |
4269 | #define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45) | |
4270 | #define PIPE_FLIPCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_GM45) | |
4271 | ||
4272 | /* Cursor A & B regs */ | |
4273 | #define _CURACNTR 0x70080 | |
4274 | /* Old style CUR*CNTR flags (desktop 8xx) */ | |
4275 | #define CURSOR_ENABLE 0x80000000 | |
4276 | #define CURSOR_GAMMA_ENABLE 0x40000000 | |
4277 | #define CURSOR_STRIDE_SHIFT 28 | |
4278 | #define CURSOR_STRIDE(x) ((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */ | |
4279 | #define CURSOR_PIPE_CSC_ENABLE (1<<24) | |
4280 | #define CURSOR_FORMAT_SHIFT 24 | |
4281 | #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) | |
4282 | #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) | |
4283 | #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) | |
4284 | #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) | |
4285 | #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) | |
4286 | #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) | |
4287 | /* New style CUR*CNTR flags */ | |
4288 | #define CURSOR_MODE 0x27 | |
4289 | #define CURSOR_MODE_DISABLE 0x00 | |
4290 | #define CURSOR_MODE_128_32B_AX 0x02 | |
4291 | #define CURSOR_MODE_256_32B_AX 0x03 | |
4292 | #define CURSOR_MODE_64_32B_AX 0x07 | |
4293 | #define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX) | |
4294 | #define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX) | |
4295 | #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) | |
4296 | #define MCURSOR_PIPE_SELECT (1 << 28) | |
4297 | #define MCURSOR_PIPE_A 0x00 | |
4298 | #define MCURSOR_PIPE_B (1 << 28) | |
4299 | #define MCURSOR_GAMMA_ENABLE (1 << 26) | |
4300 | #define CURSOR_ROTATE_180 (1<<15) | |
4301 | #define CURSOR_TRICKLE_FEED_DISABLE (1 << 14) | |
4302 | #define _CURABASE 0x70084 | |
4303 | #define _CURAPOS 0x70088 | |
4304 | #define CURSOR_POS_MASK 0x007FF | |
4305 | #define CURSOR_POS_SIGN 0x8000 | |
4306 | #define CURSOR_X_SHIFT 0 | |
4307 | #define CURSOR_Y_SHIFT 16 | |
4308 | #define CURSIZE 0x700a0 | |
4309 | #define _CURBCNTR 0x700c0 | |
4310 | #define _CURBBASE 0x700c4 | |
4311 | #define _CURBPOS 0x700c8 | |
4312 | ||
4313 | #define _CURBCNTR_IVB 0x71080 | |
4314 | #define _CURBBASE_IVB 0x71084 | |
4315 | #define _CURBPOS_IVB 0x71088 | |
4316 | ||
4317 | #define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \ | |
4318 | dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \ | |
4319 | dev_priv->info.display_mmio_offset) | |
4320 | ||
4321 | #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR) | |
4322 | #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE) | |
4323 | #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS) | |
4324 | ||
4325 | #define CURSOR_A_OFFSET 0x70080 | |
4326 | #define CURSOR_B_OFFSET 0x700c0 | |
4327 | #define CHV_CURSOR_C_OFFSET 0x700e0 | |
4328 | #define IVB_CURSOR_B_OFFSET 0x71080 | |
4329 | #define IVB_CURSOR_C_OFFSET 0x72080 | |
4330 | ||
4331 | /* Display A control */ | |
4332 | #define _DSPACNTR 0x70180 | |
4333 | #define DISPLAY_PLANE_ENABLE (1<<31) | |
4334 | #define DISPLAY_PLANE_DISABLE 0 | |
4335 | #define DISPPLANE_GAMMA_ENABLE (1<<30) | |
4336 | #define DISPPLANE_GAMMA_DISABLE 0 | |
4337 | #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) | |
4338 | #define DISPPLANE_YUV422 (0x0<<26) | |
4339 | #define DISPPLANE_8BPP (0x2<<26) | |
4340 | #define DISPPLANE_BGRA555 (0x3<<26) | |
4341 | #define DISPPLANE_BGRX555 (0x4<<26) | |
4342 | #define DISPPLANE_BGRX565 (0x5<<26) | |
4343 | #define DISPPLANE_BGRX888 (0x6<<26) | |
4344 | #define DISPPLANE_BGRA888 (0x7<<26) | |
4345 | #define DISPPLANE_RGBX101010 (0x8<<26) | |
4346 | #define DISPPLANE_RGBA101010 (0x9<<26) | |
4347 | #define DISPPLANE_BGRX101010 (0xa<<26) | |
4348 | #define DISPPLANE_RGBX161616 (0xc<<26) | |
4349 | #define DISPPLANE_RGBX888 (0xe<<26) | |
4350 | #define DISPPLANE_RGBA888 (0xf<<26) | |
4351 | #define DISPPLANE_STEREO_ENABLE (1<<25) | |
4352 | #define DISPPLANE_STEREO_DISABLE 0 | |
4353 | #define DISPPLANE_PIPE_CSC_ENABLE (1<<24) | |
4354 | #define DISPPLANE_SEL_PIPE_SHIFT 24 | |
4355 | #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) | |
4356 | #define DISPPLANE_SEL_PIPE_A 0 | |
4357 | #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) | |
4358 | #define DISPPLANE_SRC_KEY_ENABLE (1<<22) | |
4359 | #define DISPPLANE_SRC_KEY_DISABLE 0 | |
4360 | #define DISPPLANE_LINE_DOUBLE (1<<20) | |
4361 | #define DISPPLANE_NO_LINE_DOUBLE 0 | |
4362 | #define DISPPLANE_STEREO_POLARITY_FIRST 0 | |
4363 | #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) | |
4364 | #define DISPPLANE_ALPHA_PREMULTIPLY (1<<16) /* CHV pipe B */ | |
4365 | #define DISPPLANE_ROTATE_180 (1<<15) | |
4366 | #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ | |
4367 | #define DISPPLANE_TILED (1<<10) | |
4368 | #define DISPPLANE_MIRROR (1<<8) /* CHV pipe B */ | |
4369 | #define _DSPAADDR 0x70184 | |
4370 | #define _DSPASTRIDE 0x70188 | |
4371 | #define _DSPAPOS 0x7018C /* reserved */ | |
4372 | #define _DSPASIZE 0x70190 | |
4373 | #define _DSPASURF 0x7019C /* 965+ only */ | |
4374 | #define _DSPATILEOFF 0x701A4 /* 965+ only */ | |
4375 | #define _DSPAOFFSET 0x701A4 /* HSW */ | |
4376 | #define _DSPASURFLIVE 0x701AC | |
4377 | ||
4378 | #define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR) | |
4379 | #define DSPADDR(plane) _PIPE2(plane, _DSPAADDR) | |
4380 | #define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE) | |
4381 | #define DSPPOS(plane) _PIPE2(plane, _DSPAPOS) | |
4382 | #define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE) | |
4383 | #define DSPSURF(plane) _PIPE2(plane, _DSPASURF) | |
4384 | #define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF) | |
4385 | #define DSPLINOFF(plane) DSPADDR(plane) | |
4386 | #define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET) | |
4387 | #define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE) | |
4388 | ||
4389 | /* CHV pipe B blender and primary plane */ | |
4390 | #define _CHV_BLEND_A 0x60a00 | |
4391 | #define CHV_BLEND_LEGACY (0<<30) | |
4392 | #define CHV_BLEND_ANDROID (1<<30) | |
4393 | #define CHV_BLEND_MPO (2<<30) | |
4394 | #define CHV_BLEND_MASK (3<<30) | |
4395 | #define _CHV_CANVAS_A 0x60a04 | |
4396 | #define _PRIMPOS_A 0x60a08 | |
4397 | #define _PRIMSIZE_A 0x60a0c | |
4398 | #define _PRIMCNSTALPHA_A 0x60a10 | |
4399 | #define PRIM_CONST_ALPHA_ENABLE (1<<31) | |
4400 | ||
4401 | #define CHV_BLEND(pipe) _TRANSCODER2(pipe, _CHV_BLEND_A) | |
4402 | #define CHV_CANVAS(pipe) _TRANSCODER2(pipe, _CHV_CANVAS_A) | |
4403 | #define PRIMPOS(plane) _TRANSCODER2(plane, _PRIMPOS_A) | |
4404 | #define PRIMSIZE(plane) _TRANSCODER2(plane, _PRIMSIZE_A) | |
4405 | #define PRIMCNSTALPHA(plane) _TRANSCODER2(plane, _PRIMCNSTALPHA_A) | |
4406 | ||
4407 | /* Display/Sprite base address macros */ | |
4408 | #define DISP_BASEADDR_MASK (0xfffff000) | |
4409 | #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) | |
4410 | #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) | |
4411 | ||
4412 | /* VBIOS flags */ | |
4413 | #define SWF00 (dev_priv->info.display_mmio_offset + 0x71410) | |
4414 | #define SWF01 (dev_priv->info.display_mmio_offset + 0x71414) | |
4415 | #define SWF02 (dev_priv->info.display_mmio_offset + 0x71418) | |
4416 | #define SWF03 (dev_priv->info.display_mmio_offset + 0x7141c) | |
4417 | #define SWF04 (dev_priv->info.display_mmio_offset + 0x71420) | |
4418 | #define SWF05 (dev_priv->info.display_mmio_offset + 0x71424) | |
4419 | #define SWF06 (dev_priv->info.display_mmio_offset + 0x71428) | |
4420 | #define SWF10 (dev_priv->info.display_mmio_offset + 0x70410) | |
4421 | #define SWF11 (dev_priv->info.display_mmio_offset + 0x70414) | |
4422 | #define SWF14 (dev_priv->info.display_mmio_offset + 0x71420) | |
4423 | #define SWF30 (dev_priv->info.display_mmio_offset + 0x72414) | |
4424 | #define SWF31 (dev_priv->info.display_mmio_offset + 0x72418) | |
4425 | #define SWF32 (dev_priv->info.display_mmio_offset + 0x7241c) | |
4426 | ||
4427 | /* Pipe B */ | |
4428 | #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000) | |
4429 | #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008) | |
4430 | #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024) | |
4431 | #define _PIPEBFRAMEHIGH 0x71040 | |
4432 | #define _PIPEBFRAMEPIXEL 0x71044 | |
4433 | #define _PIPEB_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71040) | |
4434 | #define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71044) | |
4435 | ||
4436 | ||
4437 | /* Display B control */ | |
4438 | #define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180) | |
4439 | #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) | |
4440 | #define DISPPLANE_ALPHA_TRANS_DISABLE 0 | |
4441 | #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 | |
4442 | #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) | |
4443 | #define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184) | |
4444 | #define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188) | |
4445 | #define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C) | |
4446 | #define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190) | |
4447 | #define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C) | |
4448 | #define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4) | |
4449 | #define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4) | |
4450 | #define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC) | |
4451 | ||
4452 | /* Sprite A control */ | |
4453 | #define _DVSACNTR 0x72180 | |
4454 | #define DVS_ENABLE (1<<31) | |
4455 | #define DVS_GAMMA_ENABLE (1<<30) | |
4456 | #define DVS_PIXFORMAT_MASK (3<<25) | |
4457 | #define DVS_FORMAT_YUV422 (0<<25) | |
4458 | #define DVS_FORMAT_RGBX101010 (1<<25) | |
4459 | #define DVS_FORMAT_RGBX888 (2<<25) | |
4460 | #define DVS_FORMAT_RGBX161616 (3<<25) | |
4461 | #define DVS_PIPE_CSC_ENABLE (1<<24) | |
4462 | #define DVS_SOURCE_KEY (1<<22) | |
4463 | #define DVS_RGB_ORDER_XBGR (1<<20) | |
4464 | #define DVS_YUV_BYTE_ORDER_MASK (3<<16) | |
4465 | #define DVS_YUV_ORDER_YUYV (0<<16) | |
4466 | #define DVS_YUV_ORDER_UYVY (1<<16) | |
4467 | #define DVS_YUV_ORDER_YVYU (2<<16) | |
4468 | #define DVS_YUV_ORDER_VYUY (3<<16) | |
4469 | #define DVS_ROTATE_180 (1<<15) | |
4470 | #define DVS_DEST_KEY (1<<2) | |
4471 | #define DVS_TRICKLE_FEED_DISABLE (1<<14) | |
4472 | #define DVS_TILED (1<<10) | |
4473 | #define _DVSALINOFF 0x72184 | |
4474 | #define _DVSASTRIDE 0x72188 | |
4475 | #define _DVSAPOS 0x7218c | |
4476 | #define _DVSASIZE 0x72190 | |
4477 | #define _DVSAKEYVAL 0x72194 | |
4478 | #define _DVSAKEYMSK 0x72198 | |
4479 | #define _DVSASURF 0x7219c | |
4480 | #define _DVSAKEYMAXVAL 0x721a0 | |
4481 | #define _DVSATILEOFF 0x721a4 | |
4482 | #define _DVSASURFLIVE 0x721ac | |
4483 | #define _DVSASCALE 0x72204 | |
4484 | #define DVS_SCALE_ENABLE (1<<31) | |
4485 | #define DVS_FILTER_MASK (3<<29) | |
4486 | #define DVS_FILTER_MEDIUM (0<<29) | |
4487 | #define DVS_FILTER_ENHANCING (1<<29) | |
4488 | #define DVS_FILTER_SOFTENING (2<<29) | |
4489 | #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ | |
4490 | #define DVS_VERTICAL_OFFSET_ENABLE (1<<27) | |
4491 | #define _DVSAGAMC 0x72300 | |
4492 | ||
4493 | #define _DVSBCNTR 0x73180 | |
4494 | #define _DVSBLINOFF 0x73184 | |
4495 | #define _DVSBSTRIDE 0x73188 | |
4496 | #define _DVSBPOS 0x7318c | |
4497 | #define _DVSBSIZE 0x73190 | |
4498 | #define _DVSBKEYVAL 0x73194 | |
4499 | #define _DVSBKEYMSK 0x73198 | |
4500 | #define _DVSBSURF 0x7319c | |
4501 | #define _DVSBKEYMAXVAL 0x731a0 | |
4502 | #define _DVSBTILEOFF 0x731a4 | |
4503 | #define _DVSBSURFLIVE 0x731ac | |
4504 | #define _DVSBSCALE 0x73204 | |
4505 | #define _DVSBGAMC 0x73300 | |
4506 | ||
4507 | #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR) | |
4508 | #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) | |
4509 | #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) | |
4510 | #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS) | |
4511 | #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF) | |
4512 | #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) | |
4513 | #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE) | |
4514 | #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE) | |
4515 | #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) | |
4516 | #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) | |
4517 | #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) | |
4518 | #define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) | |
4519 | ||
4520 | #define _SPRA_CTL 0x70280 | |
4521 | #define SPRITE_ENABLE (1<<31) | |
4522 | #define SPRITE_GAMMA_ENABLE (1<<30) | |
4523 | #define SPRITE_PIXFORMAT_MASK (7<<25) | |
4524 | #define SPRITE_FORMAT_YUV422 (0<<25) | |
4525 | #define SPRITE_FORMAT_RGBX101010 (1<<25) | |
4526 | #define SPRITE_FORMAT_RGBX888 (2<<25) | |
4527 | #define SPRITE_FORMAT_RGBX161616 (3<<25) | |
4528 | #define SPRITE_FORMAT_YUV444 (4<<25) | |
4529 | #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ | |
4530 | #define SPRITE_PIPE_CSC_ENABLE (1<<24) | |
4531 | #define SPRITE_SOURCE_KEY (1<<22) | |
4532 | #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ | |
4533 | #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) | |
4534 | #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ | |
4535 | #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) | |
4536 | #define SPRITE_YUV_ORDER_YUYV (0<<16) | |
4537 | #define SPRITE_YUV_ORDER_UYVY (1<<16) | |
4538 | #define SPRITE_YUV_ORDER_YVYU (2<<16) | |
4539 | #define SPRITE_YUV_ORDER_VYUY (3<<16) | |
4540 | #define SPRITE_ROTATE_180 (1<<15) | |
4541 | #define SPRITE_TRICKLE_FEED_DISABLE (1<<14) | |
4542 | #define SPRITE_INT_GAMMA_ENABLE (1<<13) | |
4543 | #define SPRITE_TILED (1<<10) | |
4544 | #define SPRITE_DEST_KEY (1<<2) | |
4545 | #define _SPRA_LINOFF 0x70284 | |
4546 | #define _SPRA_STRIDE 0x70288 | |
4547 | #define _SPRA_POS 0x7028c | |
4548 | #define _SPRA_SIZE 0x70290 | |
4549 | #define _SPRA_KEYVAL 0x70294 | |
4550 | #define _SPRA_KEYMSK 0x70298 | |
4551 | #define _SPRA_SURF 0x7029c | |
4552 | #define _SPRA_KEYMAX 0x702a0 | |
4553 | #define _SPRA_TILEOFF 0x702a4 | |
4554 | #define _SPRA_OFFSET 0x702a4 | |
4555 | #define _SPRA_SURFLIVE 0x702ac | |
4556 | #define _SPRA_SCALE 0x70304 | |
4557 | #define SPRITE_SCALE_ENABLE (1<<31) | |
4558 | #define SPRITE_FILTER_MASK (3<<29) | |
4559 | #define SPRITE_FILTER_MEDIUM (0<<29) | |
4560 | #define SPRITE_FILTER_ENHANCING (1<<29) | |
4561 | #define SPRITE_FILTER_SOFTENING (2<<29) | |
4562 | #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ | |
4563 | #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) | |
4564 | #define _SPRA_GAMC 0x70400 | |
4565 | ||
4566 | #define _SPRB_CTL 0x71280 | |
4567 | #define _SPRB_LINOFF 0x71284 | |
4568 | #define _SPRB_STRIDE 0x71288 | |
4569 | #define _SPRB_POS 0x7128c | |
4570 | #define _SPRB_SIZE 0x71290 | |
4571 | #define _SPRB_KEYVAL 0x71294 | |
4572 | #define _SPRB_KEYMSK 0x71298 | |
4573 | #define _SPRB_SURF 0x7129c | |
4574 | #define _SPRB_KEYMAX 0x712a0 | |
4575 | #define _SPRB_TILEOFF 0x712a4 | |
4576 | #define _SPRB_OFFSET 0x712a4 | |
4577 | #define _SPRB_SURFLIVE 0x712ac | |
4578 | #define _SPRB_SCALE 0x71304 | |
4579 | #define _SPRB_GAMC 0x71400 | |
4580 | ||
4581 | #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL) | |
4582 | #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) | |
4583 | #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) | |
4584 | #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS) | |
4585 | #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) | |
4586 | #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) | |
4587 | #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) | |
4588 | #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF) | |
4589 | #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) | |
4590 | #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) | |
4591 | #define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) | |
4592 | #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) | |
4593 | #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) | |
4594 | #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) | |
4595 | ||
4596 | #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) | |
4597 | #define SP_ENABLE (1<<31) | |
4598 | #define SP_GAMMA_ENABLE (1<<30) | |
4599 | #define SP_PIXFORMAT_MASK (0xf<<26) | |
4600 | #define SP_FORMAT_YUV422 (0<<26) | |
4601 | #define SP_FORMAT_BGR565 (5<<26) | |
4602 | #define SP_FORMAT_BGRX8888 (6<<26) | |
4603 | #define SP_FORMAT_BGRA8888 (7<<26) | |
4604 | #define SP_FORMAT_RGBX1010102 (8<<26) | |
4605 | #define SP_FORMAT_RGBA1010102 (9<<26) | |
4606 | #define SP_FORMAT_RGBX8888 (0xe<<26) | |
4607 | #define SP_FORMAT_RGBA8888 (0xf<<26) | |
4608 | #define SP_ALPHA_PREMULTIPLY (1<<23) /* CHV pipe B */ | |
4609 | #define SP_SOURCE_KEY (1<<22) | |
4610 | #define SP_YUV_BYTE_ORDER_MASK (3<<16) | |
4611 | #define SP_YUV_ORDER_YUYV (0<<16) | |
4612 | #define SP_YUV_ORDER_UYVY (1<<16) | |
4613 | #define SP_YUV_ORDER_YVYU (2<<16) | |
4614 | #define SP_YUV_ORDER_VYUY (3<<16) | |
4615 | #define SP_ROTATE_180 (1<<15) | |
4616 | #define SP_TILED (1<<10) | |
4617 | #define SP_MIRROR (1<<8) /* CHV pipe B */ | |
4618 | #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) | |
4619 | #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) | |
4620 | #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) | |
4621 | #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) | |
4622 | #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) | |
4623 | #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) | |
4624 | #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) | |
4625 | #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) | |
4626 | #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) | |
4627 | #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) | |
4628 | #define SP_CONST_ALPHA_ENABLE (1<<31) | |
4629 | #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4) | |
4630 | ||
4631 | #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) | |
4632 | #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) | |
4633 | #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) | |
4634 | #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) | |
4635 | #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) | |
4636 | #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) | |
4637 | #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) | |
4638 | #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) | |
4639 | #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) | |
4640 | #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) | |
4641 | #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) | |
4642 | #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4) | |
4643 | ||
4644 | #define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR) | |
4645 | #define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF) | |
4646 | #define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE) | |
4647 | #define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS) | |
4648 | #define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE) | |
4649 | #define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL) | |
4650 | #define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK) | |
4651 | #define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF) | |
4652 | #define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL) | |
4653 | #define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF) | |
4654 | #define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA) | |
4655 | #define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC) | |
4656 | ||
4657 | /* | |
4658 | * CHV pipe B sprite CSC | |
4659 | * | |
4660 | * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| | |
4661 | * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| | |
4662 | * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| | |
4663 | */ | |
4664 | #define SPCSCYGOFF(sprite) (VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000) | |
4665 | #define SPCSCCBOFF(sprite) (VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000) | |
4666 | #define SPCSCCROFF(sprite) (VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000) | |
4667 | #define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */ | |
4668 | #define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */ | |
4669 | ||
4670 | #define SPCSCC01(sprite) (VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000) | |
4671 | #define SPCSCC23(sprite) (VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000) | |
4672 | #define SPCSCC45(sprite) (VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000) | |
4673 | #define SPCSCC67(sprite) (VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000) | |
4674 | #define SPCSCC8(sprite) (VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000) | |
4675 | #define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */ | |
4676 | #define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */ | |
4677 | ||
4678 | #define SPCSCYGICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000) | |
4679 | #define SPCSCCBICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000) | |
4680 | #define SPCSCCRICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000) | |
4681 | #define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */ | |
4682 | #define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */ | |
4683 | ||
4684 | #define SPCSCYGOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000) | |
4685 | #define SPCSCCBOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000) | |
4686 | #define SPCSCCROCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000) | |
4687 | #define SPCSC_OMAX(x) ((x) << 16) /* u10 */ | |
4688 | #define SPCSC_OMIN(x) ((x) << 0) /* u10 */ | |
4689 | ||
4690 | /* Skylake plane registers */ | |
4691 | ||
4692 | #define _PLANE_CTL_1_A 0x70180 | |
4693 | #define _PLANE_CTL_2_A 0x70280 | |
4694 | #define _PLANE_CTL_3_A 0x70380 | |
4695 | #define PLANE_CTL_ENABLE (1 << 31) | |
4696 | #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) | |
4697 | #define PLANE_CTL_FORMAT_MASK (0xf << 24) | |
4698 | #define PLANE_CTL_FORMAT_YUV422 ( 0 << 24) | |
4699 | #define PLANE_CTL_FORMAT_NV12 ( 1 << 24) | |
4700 | #define PLANE_CTL_FORMAT_XRGB_2101010 ( 2 << 24) | |
4701 | #define PLANE_CTL_FORMAT_XRGB_8888 ( 4 << 24) | |
4702 | #define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24) | |
4703 | #define PLANE_CTL_FORMAT_AYUV ( 8 << 24) | |
4704 | #define PLANE_CTL_FORMAT_INDEXED ( 12 << 24) | |
4705 | #define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24) | |
4706 | #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) | |
4707 | #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21) | |
4708 | #define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21) | |
4709 | #define PLANE_CTL_KEY_ENABLE_DESTINATION ( 2 << 21) | |
4710 | #define PLANE_CTL_ORDER_BGRX (0 << 20) | |
4711 | #define PLANE_CTL_ORDER_RGBX (1 << 20) | |
4712 | #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16) | |
4713 | #define PLANE_CTL_YUV422_YUYV ( 0 << 16) | |
4714 | #define PLANE_CTL_YUV422_UYVY ( 1 << 16) | |
4715 | #define PLANE_CTL_YUV422_YVYU ( 2 << 16) | |
4716 | #define PLANE_CTL_YUV422_VYUY ( 3 << 16) | |
4717 | #define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15) | |
4718 | #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14) | |
4719 | #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) | |
4720 | #define PLANE_CTL_TILED_MASK (0x7 << 10) | |
4721 | #define PLANE_CTL_TILED_LINEAR ( 0 << 10) | |
4722 | #define PLANE_CTL_TILED_X ( 1 << 10) | |
4723 | #define PLANE_CTL_TILED_Y ( 4 << 10) | |
4724 | #define PLANE_CTL_TILED_YF ( 5 << 10) | |
4725 | #define PLANE_CTL_ALPHA_MASK (0x3 << 4) | |
4726 | #define PLANE_CTL_ALPHA_DISABLE ( 0 << 4) | |
4727 | #define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4) | |
4728 | #define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4) | |
4729 | #define PLANE_CTL_ROTATE_MASK 0x3 | |
4730 | #define PLANE_CTL_ROTATE_0 0x0 | |
4731 | #define PLANE_CTL_ROTATE_180 0x2 | |
4732 | #define _PLANE_STRIDE_1_A 0x70188 | |
4733 | #define _PLANE_STRIDE_2_A 0x70288 | |
4734 | #define _PLANE_STRIDE_3_A 0x70388 | |
4735 | #define _PLANE_POS_1_A 0x7018c | |
4736 | #define _PLANE_POS_2_A 0x7028c | |
4737 | #define _PLANE_POS_3_A 0x7038c | |
4738 | #define _PLANE_SIZE_1_A 0x70190 | |
4739 | #define _PLANE_SIZE_2_A 0x70290 | |
4740 | #define _PLANE_SIZE_3_A 0x70390 | |
4741 | #define _PLANE_SURF_1_A 0x7019c | |
4742 | #define _PLANE_SURF_2_A 0x7029c | |
4743 | #define _PLANE_SURF_3_A 0x7039c | |
4744 | #define _PLANE_OFFSET_1_A 0x701a4 | |
4745 | #define _PLANE_OFFSET_2_A 0x702a4 | |
4746 | #define _PLANE_OFFSET_3_A 0x703a4 | |
4747 | #define _PLANE_KEYVAL_1_A 0x70194 | |
4748 | #define _PLANE_KEYVAL_2_A 0x70294 | |
4749 | #define _PLANE_KEYMSK_1_A 0x70198 | |
4750 | #define _PLANE_KEYMSK_2_A 0x70298 | |
4751 | #define _PLANE_KEYMAX_1_A 0x701a0 | |
4752 | #define _PLANE_KEYMAX_2_A 0x702a0 | |
4753 | #define _PLANE_BUF_CFG_1_A 0x7027c | |
4754 | #define _PLANE_BUF_CFG_2_A 0x7037c | |
4755 | ||
4756 | #define _PLANE_CTL_1_B 0x71180 | |
4757 | #define _PLANE_CTL_2_B 0x71280 | |
4758 | #define _PLANE_CTL_3_B 0x71380 | |
4759 | #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) | |
4760 | #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) | |
4761 | #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) | |
4762 | #define PLANE_CTL(pipe, plane) \ | |
4763 | _PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) | |
4764 | ||
4765 | #define _PLANE_STRIDE_1_B 0x71188 | |
4766 | #define _PLANE_STRIDE_2_B 0x71288 | |
4767 | #define _PLANE_STRIDE_3_B 0x71388 | |
4768 | #define _PLANE_STRIDE_1(pipe) \ | |
4769 | _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) | |
4770 | #define _PLANE_STRIDE_2(pipe) \ | |
4771 | _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) | |
4772 | #define _PLANE_STRIDE_3(pipe) \ | |
4773 | _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) | |
4774 | #define PLANE_STRIDE(pipe, plane) \ | |
4775 | _PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) | |
4776 | ||
4777 | #define _PLANE_POS_1_B 0x7118c | |
4778 | #define _PLANE_POS_2_B 0x7128c | |
4779 | #define _PLANE_POS_3_B 0x7138c | |
4780 | #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) | |
4781 | #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) | |
4782 | #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) | |
4783 | #define PLANE_POS(pipe, plane) \ | |
4784 | _PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) | |
4785 | ||
4786 | #define _PLANE_SIZE_1_B 0x71190 | |
4787 | #define _PLANE_SIZE_2_B 0x71290 | |
4788 | #define _PLANE_SIZE_3_B 0x71390 | |
4789 | #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) | |
4790 | #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) | |
4791 | #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) | |
4792 | #define PLANE_SIZE(pipe, plane) \ | |
4793 | _PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) | |
4794 | ||
4795 | #define _PLANE_SURF_1_B 0x7119c | |
4796 | #define _PLANE_SURF_2_B 0x7129c | |
4797 | #define _PLANE_SURF_3_B 0x7139c | |
4798 | #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) | |
4799 | #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) | |
4800 | #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) | |
4801 | #define PLANE_SURF(pipe, plane) \ | |
4802 | _PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) | |
4803 | ||
4804 | #define _PLANE_OFFSET_1_B 0x711a4 | |
4805 | #define _PLANE_OFFSET_2_B 0x712a4 | |
4806 | #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) | |
4807 | #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) | |
4808 | #define PLANE_OFFSET(pipe, plane) \ | |
4809 | _PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) | |
4810 | ||
4811 | #define _PLANE_KEYVAL_1_B 0x71194 | |
4812 | #define _PLANE_KEYVAL_2_B 0x71294 | |
4813 | #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) | |
4814 | #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) | |
4815 | #define PLANE_KEYVAL(pipe, plane) \ | |
4816 | _PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) | |
4817 | ||
4818 | #define _PLANE_KEYMSK_1_B 0x71198 | |
4819 | #define _PLANE_KEYMSK_2_B 0x71298 | |
4820 | #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) | |
4821 | #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) | |
4822 | #define PLANE_KEYMSK(pipe, plane) \ | |
4823 | _PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) | |
4824 | ||
4825 | #define _PLANE_KEYMAX_1_B 0x711a0 | |
4826 | #define _PLANE_KEYMAX_2_B 0x712a0 | |
4827 | #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) | |
4828 | #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) | |
4829 | #define PLANE_KEYMAX(pipe, plane) \ | |
4830 | _PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) | |
4831 | ||
4832 | #define _PLANE_BUF_CFG_1_B 0x7127c | |
4833 | #define _PLANE_BUF_CFG_2_B 0x7137c | |
4834 | #define _PLANE_BUF_CFG_1(pipe) \ | |
4835 | _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) | |
4836 | #define _PLANE_BUF_CFG_2(pipe) \ | |
4837 | _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) | |
4838 | #define PLANE_BUF_CFG(pipe, plane) \ | |
4839 | _PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) | |
4840 | ||
4841 | /* SKL new cursor registers */ | |
4842 | #define _CUR_BUF_CFG_A 0x7017c | |
4843 | #define _CUR_BUF_CFG_B 0x7117c | |
4844 | #define CUR_BUF_CFG(pipe) _PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) | |
4845 | ||
4846 | /* VBIOS regs */ | |
4847 | #define VGACNTRL 0x71400 | |
4848 | # define VGA_DISP_DISABLE (1 << 31) | |
4849 | # define VGA_2X_MODE (1 << 30) | |
4850 | # define VGA_PIPE_B_SELECT (1 << 29) | |
4851 | ||
4852 | #define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400) | |
4853 | ||
4854 | /* Ironlake */ | |
4855 | ||
4856 | #define CPU_VGACNTRL 0x41000 | |
4857 | ||
4858 | #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 | |
4859 | #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) | |
4860 | #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) | |
4861 | #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) | |
4862 | #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) | |
4863 | #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) | |
4864 | #define DIGITAL_PORTA_NO_DETECT (0 << 0) | |
4865 | #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) | |
4866 | #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) | |
4867 | ||
4868 | /* refresh rate hardware control */ | |
4869 | #define RR_HW_CTL 0x45300 | |
4870 | #define RR_HW_LOW_POWER_FRAMES_MASK 0xff | |
4871 | #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 | |
4872 | ||
4873 | #define FDI_PLL_BIOS_0 0x46000 | |
4874 | #define FDI_PLL_FB_CLOCK_MASK 0xff | |
4875 | #define FDI_PLL_BIOS_1 0x46004 | |
4876 | #define FDI_PLL_BIOS_2 0x46008 | |
4877 | #define DISPLAY_PORT_PLL_BIOS_0 0x4600c | |
4878 | #define DISPLAY_PORT_PLL_BIOS_1 0x46010 | |
4879 | #define DISPLAY_PORT_PLL_BIOS_2 0x46014 | |
4880 | ||
4881 | #define PCH_3DCGDIS0 0x46020 | |
4882 | # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) | |
4883 | # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) | |
4884 | ||
4885 | #define PCH_3DCGDIS1 0x46024 | |
4886 | # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) | |
4887 | ||
4888 | #define FDI_PLL_FREQ_CTL 0x46030 | |
4889 | #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) | |
4890 | #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 | |
4891 | #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff | |
4892 | ||
4893 | ||
4894 | #define _PIPEA_DATA_M1 0x60030 | |
4895 | #define PIPE_DATA_M1_OFFSET 0 | |
4896 | #define _PIPEA_DATA_N1 0x60034 | |
4897 | #define PIPE_DATA_N1_OFFSET 0 | |
4898 | ||
4899 | #define _PIPEA_DATA_M2 0x60038 | |
4900 | #define PIPE_DATA_M2_OFFSET 0 | |
4901 | #define _PIPEA_DATA_N2 0x6003c | |
4902 | #define PIPE_DATA_N2_OFFSET 0 | |
4903 | ||
4904 | #define _PIPEA_LINK_M1 0x60040 | |
4905 | #define PIPE_LINK_M1_OFFSET 0 | |
4906 | #define _PIPEA_LINK_N1 0x60044 | |
4907 | #define PIPE_LINK_N1_OFFSET 0 | |
4908 | ||
4909 | #define _PIPEA_LINK_M2 0x60048 | |
4910 | #define PIPE_LINK_M2_OFFSET 0 | |
4911 | #define _PIPEA_LINK_N2 0x6004c | |
4912 | #define PIPE_LINK_N2_OFFSET 0 | |
4913 | ||
4914 | /* PIPEB timing regs are same start from 0x61000 */ | |
4915 | ||
4916 | #define _PIPEB_DATA_M1 0x61030 | |
4917 | #define _PIPEB_DATA_N1 0x61034 | |
4918 | #define _PIPEB_DATA_M2 0x61038 | |
4919 | #define _PIPEB_DATA_N2 0x6103c | |
4920 | #define _PIPEB_LINK_M1 0x61040 | |
4921 | #define _PIPEB_LINK_N1 0x61044 | |
4922 | #define _PIPEB_LINK_M2 0x61048 | |
4923 | #define _PIPEB_LINK_N2 0x6104c | |
4924 | ||
4925 | #define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1) | |
4926 | #define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1) | |
4927 | #define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2) | |
4928 | #define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2) | |
4929 | #define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1) | |
4930 | #define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1) | |
4931 | #define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2) | |
4932 | #define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2) | |
4933 | ||
4934 | /* CPU panel fitter */ | |
4935 | /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ | |
4936 | #define _PFA_CTL_1 0x68080 | |
4937 | #define _PFB_CTL_1 0x68880 | |
4938 | #define PF_ENABLE (1<<31) | |
4939 | #define PF_PIPE_SEL_MASK_IVB (3<<29) | |
4940 | #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29) | |
4941 | #define PF_FILTER_MASK (3<<23) | |
4942 | #define PF_FILTER_PROGRAMMED (0<<23) | |
4943 | #define PF_FILTER_MED_3x3 (1<<23) | |
4944 | #define PF_FILTER_EDGE_ENHANCE (2<<23) | |
4945 | #define PF_FILTER_EDGE_SOFTEN (3<<23) | |
4946 | #define _PFA_WIN_SZ 0x68074 | |
4947 | #define _PFB_WIN_SZ 0x68874 | |
4948 | #define _PFA_WIN_POS 0x68070 | |
4949 | #define _PFB_WIN_POS 0x68870 | |
4950 | #define _PFA_VSCALE 0x68084 | |
4951 | #define _PFB_VSCALE 0x68884 | |
4952 | #define _PFA_HSCALE 0x68090 | |
4953 | #define _PFB_HSCALE 0x68890 | |
4954 | ||
4955 | #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) | |
4956 | #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) | |
4957 | #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) | |
4958 | #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) | |
4959 | #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) | |
4960 | ||
4961 | #define _PSA_CTL 0x68180 | |
4962 | #define _PSB_CTL 0x68980 | |
4963 | #define PS_ENABLE (1<<31) | |
4964 | #define _PSA_WIN_SZ 0x68174 | |
4965 | #define _PSB_WIN_SZ 0x68974 | |
4966 | #define _PSA_WIN_POS 0x68170 | |
4967 | #define _PSB_WIN_POS 0x68970 | |
4968 | ||
4969 | #define PS_CTL(pipe) _PIPE(pipe, _PSA_CTL, _PSB_CTL) | |
4970 | #define PS_WIN_SZ(pipe) _PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ) | |
4971 | #define PS_WIN_POS(pipe) _PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS) | |
4972 | ||
4973 | /* legacy palette */ | |
4974 | #define _LGC_PALETTE_A 0x4a000 | |
4975 | #define _LGC_PALETTE_B 0x4a800 | |
4976 | #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) | |
4977 | ||
4978 | #define _GAMMA_MODE_A 0x4a480 | |
4979 | #define _GAMMA_MODE_B 0x4ac80 | |
4980 | #define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) | |
4981 | #define GAMMA_MODE_MODE_MASK (3 << 0) | |
4982 | #define GAMMA_MODE_MODE_8BIT (0 << 0) | |
4983 | #define GAMMA_MODE_MODE_10BIT (1 << 0) | |
4984 | #define GAMMA_MODE_MODE_12BIT (2 << 0) | |
4985 | #define GAMMA_MODE_MODE_SPLIT (3 << 0) | |
4986 | ||
4987 | /* interrupts */ | |
4988 | #define DE_MASTER_IRQ_CONTROL (1 << 31) | |
4989 | #define DE_SPRITEB_FLIP_DONE (1 << 29) | |
4990 | #define DE_SPRITEA_FLIP_DONE (1 << 28) | |
4991 | #define DE_PLANEB_FLIP_DONE (1 << 27) | |
4992 | #define DE_PLANEA_FLIP_DONE (1 << 26) | |
4993 | #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) | |
4994 | #define DE_PCU_EVENT (1 << 25) | |
4995 | #define DE_GTT_FAULT (1 << 24) | |
4996 | #define DE_POISON (1 << 23) | |
4997 | #define DE_PERFORM_COUNTER (1 << 22) | |
4998 | #define DE_PCH_EVENT (1 << 21) | |
4999 | #define DE_AUX_CHANNEL_A (1 << 20) | |
5000 | #define DE_DP_A_HOTPLUG (1 << 19) | |
5001 | #define DE_GSE (1 << 18) | |
5002 | #define DE_PIPEB_VBLANK (1 << 15) | |
5003 | #define DE_PIPEB_EVEN_FIELD (1 << 14) | |
5004 | #define DE_PIPEB_ODD_FIELD (1 << 13) | |
5005 | #define DE_PIPEB_LINE_COMPARE (1 << 12) | |
5006 | #define DE_PIPEB_VSYNC (1 << 11) | |
5007 | #define DE_PIPEB_CRC_DONE (1 << 10) | |
5008 | #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) | |
5009 | #define DE_PIPEA_VBLANK (1 << 7) | |
5010 | #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe))) | |
5011 | #define DE_PIPEA_EVEN_FIELD (1 << 6) | |
5012 | #define DE_PIPEA_ODD_FIELD (1 << 5) | |
5013 | #define DE_PIPEA_LINE_COMPARE (1 << 4) | |
5014 | #define DE_PIPEA_VSYNC (1 << 3) | |
5015 | #define DE_PIPEA_CRC_DONE (1 << 2) | |
5016 | #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe))) | |
5017 | #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) | |
5018 | #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe))) | |
5019 | ||
5020 | /* More Ivybridge lolz */ | |
5021 | #define DE_ERR_INT_IVB (1<<30) | |
5022 | #define DE_GSE_IVB (1<<29) | |
5023 | #define DE_PCH_EVENT_IVB (1<<28) | |
5024 | #define DE_DP_A_HOTPLUG_IVB (1<<27) | |
5025 | #define DE_AUX_CHANNEL_A_IVB (1<<26) | |
5026 | #define DE_SPRITEC_FLIP_DONE_IVB (1<<14) | |
5027 | #define DE_PLANEC_FLIP_DONE_IVB (1<<13) | |
5028 | #define DE_PIPEC_VBLANK_IVB (1<<10) | |
5029 | #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) | |
5030 | #define DE_PLANEB_FLIP_DONE_IVB (1<<8) | |
5031 | #define DE_PIPEB_VBLANK_IVB (1<<5) | |
5032 | #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) | |
5033 | #define DE_PLANEA_FLIP_DONE_IVB (1<<3) | |
5034 | #define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane))) | |
5035 | #define DE_PIPEA_VBLANK_IVB (1<<0) | |
5036 | #define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5)) | |
5037 | ||
5038 | #define VLV_MASTER_IER 0x4400c /* Gunit master IER */ | |
5039 | #define MASTER_INTERRUPT_ENABLE (1<<31) | |
5040 | ||
5041 | #define DEISR 0x44000 | |
5042 | #define DEIMR 0x44004 | |
5043 | #define DEIIR 0x44008 | |
5044 | #define DEIER 0x4400c | |
5045 | ||
5046 | #define GTISR 0x44010 | |
5047 | #define GTIMR 0x44014 | |
5048 | #define GTIIR 0x44018 | |
5049 | #define GTIER 0x4401c | |
5050 | ||
5051 | #define GEN8_MASTER_IRQ 0x44200 | |
5052 | #define GEN8_MASTER_IRQ_CONTROL (1<<31) | |
5053 | #define GEN8_PCU_IRQ (1<<30) | |
5054 | #define GEN8_DE_PCH_IRQ (1<<23) | |
5055 | #define GEN8_DE_MISC_IRQ (1<<22) | |
5056 | #define GEN8_DE_PORT_IRQ (1<<20) | |
5057 | #define GEN8_DE_PIPE_C_IRQ (1<<18) | |
5058 | #define GEN8_DE_PIPE_B_IRQ (1<<17) | |
5059 | #define GEN8_DE_PIPE_A_IRQ (1<<16) | |
5060 | #define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+pipe)) | |
5061 | #define GEN8_GT_VECS_IRQ (1<<6) | |
5062 | #define GEN8_GT_PM_IRQ (1<<4) | |
5063 | #define GEN8_GT_VCS2_IRQ (1<<3) | |
5064 | #define GEN8_GT_VCS1_IRQ (1<<2) | |
5065 | #define GEN8_GT_BCS_IRQ (1<<1) | |
5066 | #define GEN8_GT_RCS_IRQ (1<<0) | |
5067 | ||
5068 | #define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which))) | |
5069 | #define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which))) | |
5070 | #define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which))) | |
5071 | #define GEN8_GT_IER(which) (0x4430c + (0x10 * (which))) | |
5072 | ||
5073 | #define GEN8_BCS_IRQ_SHIFT 16 | |
5074 | #define GEN8_RCS_IRQ_SHIFT 0 | |
5075 | #define GEN8_VCS2_IRQ_SHIFT 16 | |
5076 | #define GEN8_VCS1_IRQ_SHIFT 0 | |
5077 | #define GEN8_VECS_IRQ_SHIFT 0 | |
5078 | ||
5079 | #define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe))) | |
5080 | #define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe))) | |
5081 | #define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe))) | |
5082 | #define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe))) | |
5083 | #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) | |
5084 | #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) | |
5085 | #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) | |
5086 | #define GEN8_PIPE_CURSOR_FAULT (1 << 10) | |
5087 | #define GEN8_PIPE_SPRITE_FAULT (1 << 9) | |
5088 | #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) | |
5089 | #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) | |
5090 | #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) | |
5091 | #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) | |
5092 | #define GEN8_PIPE_VSYNC (1 << 1) | |
5093 | #define GEN8_PIPE_VBLANK (1 << 0) | |
5094 | #define GEN9_PIPE_CURSOR_FAULT (1 << 11) | |
5095 | #define GEN9_PIPE_PLANE3_FAULT (1 << 9) | |
5096 | #define GEN9_PIPE_PLANE2_FAULT (1 << 8) | |
5097 | #define GEN9_PIPE_PLANE1_FAULT (1 << 7) | |
5098 | #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) | |
5099 | #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) | |
5100 | #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) | |
5101 | #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + p)) | |
5102 | #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ | |
5103 | (GEN8_PIPE_CURSOR_FAULT | \ | |
5104 | GEN8_PIPE_SPRITE_FAULT | \ | |
5105 | GEN8_PIPE_PRIMARY_FAULT) | |
5106 | #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ | |
5107 | (GEN9_PIPE_CURSOR_FAULT | \ | |
5108 | GEN9_PIPE_PLANE3_FAULT | \ | |
5109 | GEN9_PIPE_PLANE2_FAULT | \ | |
5110 | GEN9_PIPE_PLANE1_FAULT) | |
5111 | ||
5112 | #define GEN8_DE_PORT_ISR 0x44440 | |
5113 | #define GEN8_DE_PORT_IMR 0x44444 | |
5114 | #define GEN8_DE_PORT_IIR 0x44448 | |
5115 | #define GEN8_DE_PORT_IER 0x4444c | |
5116 | #define GEN8_PORT_DP_A_HOTPLUG (1 << 3) | |
5117 | #define GEN9_AUX_CHANNEL_D (1 << 27) | |
5118 | #define GEN9_AUX_CHANNEL_C (1 << 26) | |
5119 | #define GEN9_AUX_CHANNEL_B (1 << 25) | |
5120 | #define GEN8_AUX_CHANNEL_A (1 << 0) | |
5121 | ||
5122 | #define GEN8_DE_MISC_ISR 0x44460 | |
5123 | #define GEN8_DE_MISC_IMR 0x44464 | |
5124 | #define GEN8_DE_MISC_IIR 0x44468 | |
5125 | #define GEN8_DE_MISC_IER 0x4446c | |
5126 | #define GEN8_DE_MISC_GSE (1 << 27) | |
5127 | ||
5128 | #define GEN8_PCU_ISR 0x444e0 | |
5129 | #define GEN8_PCU_IMR 0x444e4 | |
5130 | #define GEN8_PCU_IIR 0x444e8 | |
5131 | #define GEN8_PCU_IER 0x444ec | |
5132 | ||
5133 | #define ILK_DISPLAY_CHICKEN2 0x42004 | |
5134 | /* Required on all Ironlake and Sandybridge according to the B-Spec. */ | |
5135 | #define ILK_ELPIN_409_SELECT (1 << 25) | |
5136 | #define ILK_DPARB_GATE (1<<22) | |
5137 | #define ILK_VSDPFD_FULL (1<<21) | |
5138 | #define FUSE_STRAP 0x42014 | |
5139 | #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) | |
5140 | #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) | |
5141 | #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) | |
5142 | #define ILK_HDCP_DISABLE (1 << 25) | |
5143 | #define ILK_eDP_A_DISABLE (1 << 24) | |
5144 | #define HSW_CDCLK_LIMIT (1 << 24) | |
5145 | #define ILK_DESKTOP (1 << 23) | |
5146 | ||
5147 | #define ILK_DSPCLK_GATE_D 0x42020 | |
5148 | #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) | |
5149 | #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) | |
5150 | #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) | |
5151 | #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) | |
5152 | #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) | |
5153 | ||
5154 | #define IVB_CHICKEN3 0x4200c | |
5155 | # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) | |
5156 | # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) | |
5157 | ||
5158 | #define CHICKEN_PAR1_1 0x42080 | |
5159 | #define DPA_MASK_VBLANK_SRD (1 << 15) | |
5160 | #define FORCE_ARB_IDLE_PLANES (1 << 14) | |
5161 | ||
5162 | #define _CHICKEN_PIPESL_1_A 0x420b0 | |
5163 | #define _CHICKEN_PIPESL_1_B 0x420b4 | |
5164 | #define HSW_FBCQ_DIS (1 << 22) | |
5165 | #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) | |
5166 | #define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) | |
5167 | ||
5168 | #define DISP_ARB_CTL 0x45000 | |
5169 | #define DISP_TILE_SURFACE_SWIZZLING (1<<13) | |
5170 | #define DISP_FBC_WM_DIS (1<<15) | |
5171 | #define DISP_ARB_CTL2 0x45004 | |
5172 | #define DISP_DATA_PARTITION_5_6 (1<<6) | |
5173 | #define GEN7_MSG_CTL 0x45010 | |
5174 | #define WAIT_FOR_PCH_RESET_ACK (1<<1) | |
5175 | #define WAIT_FOR_PCH_FLR_ACK (1<<0) | |
5176 | #define HSW_NDE_RSTWRN_OPT 0x46408 | |
5177 | #define RESET_PCH_HANDSHAKE_ENABLE (1<<4) | |
5178 | ||
5179 | /* GEN7 chicken */ | |
5180 | #define GEN7_COMMON_SLICE_CHICKEN1 0x7010 | |
5181 | # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) | |
5182 | #define COMMON_SLICE_CHICKEN2 0x7014 | |
5183 | # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0) | |
5184 | ||
5185 | #define GEN7_L3SQCREG1 0xB010 | |
5186 | #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 | |
5187 | ||
5188 | #define GEN7_L3CNTLREG1 0xB01C | |
5189 | #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C | |
5190 | #define GEN7_L3AGDIS (1<<19) | |
5191 | #define GEN7_L3CNTLREG2 0xB020 | |
5192 | #define GEN7_L3CNTLREG3 0xB024 | |
5193 | ||
5194 | #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030 | |
5195 | #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 | |
5196 | ||
5197 | #define GEN7_L3SQCREG4 0xb034 | |
5198 | #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) | |
5199 | ||
5200 | /* GEN8 chicken */ | |
5201 | #define HDC_CHICKEN0 0x7300 | |
5202 | #define HDC_FORCE_NON_COHERENT (1<<4) | |
5203 | #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11) | |
5204 | #define HDC_FENCE_DEST_SLM_DISABLE (1<<14) | |
5205 | ||
5206 | /* WaCatErrorRejectionIssue */ | |
5207 | #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 | |
5208 | #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) | |
5209 | ||
5210 | #define HSW_SCRATCH1 0xb038 | |
5211 | #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27) | |
5212 | ||
5213 | /* PCH */ | |
5214 | ||
5215 | /* south display engine interrupt: IBX */ | |
5216 | #define SDE_AUDIO_POWER_D (1 << 27) | |
5217 | #define SDE_AUDIO_POWER_C (1 << 26) | |
5218 | #define SDE_AUDIO_POWER_B (1 << 25) | |
5219 | #define SDE_AUDIO_POWER_SHIFT (25) | |
5220 | #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) | |
5221 | #define SDE_GMBUS (1 << 24) | |
5222 | #define SDE_AUDIO_HDCP_TRANSB (1 << 23) | |
5223 | #define SDE_AUDIO_HDCP_TRANSA (1 << 22) | |
5224 | #define SDE_AUDIO_HDCP_MASK (3 << 22) | |
5225 | #define SDE_AUDIO_TRANSB (1 << 21) | |
5226 | #define SDE_AUDIO_TRANSA (1 << 20) | |
5227 | #define SDE_AUDIO_TRANS_MASK (3 << 20) | |
5228 | #define SDE_POISON (1 << 19) | |
5229 | /* 18 reserved */ | |
5230 | #define SDE_FDI_RXB (1 << 17) | |
5231 | #define SDE_FDI_RXA (1 << 16) | |
5232 | #define SDE_FDI_MASK (3 << 16) | |
5233 | #define SDE_AUXD (1 << 15) | |
5234 | #define SDE_AUXC (1 << 14) | |
5235 | #define SDE_AUXB (1 << 13) | |
5236 | #define SDE_AUX_MASK (7 << 13) | |
5237 | /* 12 reserved */ | |
5238 | #define SDE_CRT_HOTPLUG (1 << 11) | |
5239 | #define SDE_PORTD_HOTPLUG (1 << 10) | |
5240 | #define SDE_PORTC_HOTPLUG (1 << 9) | |
5241 | #define SDE_PORTB_HOTPLUG (1 << 8) | |
5242 | #define SDE_SDVOB_HOTPLUG (1 << 6) | |
5243 | #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ | |
5244 | SDE_SDVOB_HOTPLUG | \ | |
5245 | SDE_PORTB_HOTPLUG | \ | |
5246 | SDE_PORTC_HOTPLUG | \ | |
5247 | SDE_PORTD_HOTPLUG) | |
5248 | #define SDE_TRANSB_CRC_DONE (1 << 5) | |
5249 | #define SDE_TRANSB_CRC_ERR (1 << 4) | |
5250 | #define SDE_TRANSB_FIFO_UNDER (1 << 3) | |
5251 | #define SDE_TRANSA_CRC_DONE (1 << 2) | |
5252 | #define SDE_TRANSA_CRC_ERR (1 << 1) | |
5253 | #define SDE_TRANSA_FIFO_UNDER (1 << 0) | |
5254 | #define SDE_TRANS_MASK (0x3f) | |
5255 | ||
5256 | /* south display engine interrupt: CPT/PPT */ | |
5257 | #define SDE_AUDIO_POWER_D_CPT (1 << 31) | |
5258 | #define SDE_AUDIO_POWER_C_CPT (1 << 30) | |
5259 | #define SDE_AUDIO_POWER_B_CPT (1 << 29) | |
5260 | #define SDE_AUDIO_POWER_SHIFT_CPT 29 | |
5261 | #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) | |
5262 | #define SDE_AUXD_CPT (1 << 27) | |
5263 | #define SDE_AUXC_CPT (1 << 26) | |
5264 | #define SDE_AUXB_CPT (1 << 25) | |
5265 | #define SDE_AUX_MASK_CPT (7 << 25) | |
5266 | #define SDE_PORTD_HOTPLUG_CPT (1 << 23) | |
5267 | #define SDE_PORTC_HOTPLUG_CPT (1 << 22) | |
5268 | #define SDE_PORTB_HOTPLUG_CPT (1 << 21) | |
5269 | #define SDE_CRT_HOTPLUG_CPT (1 << 19) | |
5270 | #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) | |
5271 | #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ | |
5272 | SDE_SDVOB_HOTPLUG_CPT | \ | |
5273 | SDE_PORTD_HOTPLUG_CPT | \ | |
5274 | SDE_PORTC_HOTPLUG_CPT | \ | |
5275 | SDE_PORTB_HOTPLUG_CPT) | |
5276 | #define SDE_GMBUS_CPT (1 << 17) | |
5277 | #define SDE_ERROR_CPT (1 << 16) | |
5278 | #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) | |
5279 | #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) | |
5280 | #define SDE_FDI_RXC_CPT (1 << 8) | |
5281 | #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) | |
5282 | #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) | |
5283 | #define SDE_FDI_RXB_CPT (1 << 4) | |
5284 | #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) | |
5285 | #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) | |
5286 | #define SDE_FDI_RXA_CPT (1 << 0) | |
5287 | #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ | |
5288 | SDE_AUDIO_CP_REQ_B_CPT | \ | |
5289 | SDE_AUDIO_CP_REQ_A_CPT) | |
5290 | #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ | |
5291 | SDE_AUDIO_CP_CHG_B_CPT | \ | |
5292 | SDE_AUDIO_CP_CHG_A_CPT) | |
5293 | #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ | |
5294 | SDE_FDI_RXB_CPT | \ | |
5295 | SDE_FDI_RXA_CPT) | |
5296 | ||
5297 | #define SDEISR 0xc4000 | |
5298 | #define SDEIMR 0xc4004 | |
5299 | #define SDEIIR 0xc4008 | |
5300 | #define SDEIER 0xc400c | |
5301 | ||
5302 | #define SERR_INT 0xc4040 | |
5303 | #define SERR_INT_POISON (1<<31) | |
5304 | #define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6) | |
5305 | #define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3) | |
5306 | #define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0) | |
5307 | #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<(pipe*3)) | |
5308 | ||
5309 | /* digital port hotplug */ | |
5310 | #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ | |
5311 | #define PORTD_HOTPLUG_ENABLE (1 << 20) | |
5312 | #define PORTD_PULSE_DURATION_2ms (0) | |
5313 | #define PORTD_PULSE_DURATION_4_5ms (1 << 18) | |
5314 | #define PORTD_PULSE_DURATION_6ms (2 << 18) | |
5315 | #define PORTD_PULSE_DURATION_100ms (3 << 18) | |
5316 | #define PORTD_PULSE_DURATION_MASK (3 << 18) | |
5317 | #define PORTD_HOTPLUG_STATUS_MASK (0x3 << 16) | |
5318 | #define PORTD_HOTPLUG_NO_DETECT (0 << 16) | |
5319 | #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) | |
5320 | #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) | |
5321 | #define PORTC_HOTPLUG_ENABLE (1 << 12) | |
5322 | #define PORTC_PULSE_DURATION_2ms (0) | |
5323 | #define PORTC_PULSE_DURATION_4_5ms (1 << 10) | |
5324 | #define PORTC_PULSE_DURATION_6ms (2 << 10) | |
5325 | #define PORTC_PULSE_DURATION_100ms (3 << 10) | |
5326 | #define PORTC_PULSE_DURATION_MASK (3 << 10) | |
5327 | #define PORTC_HOTPLUG_STATUS_MASK (0x3 << 8) | |
5328 | #define PORTC_HOTPLUG_NO_DETECT (0 << 8) | |
5329 | #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) | |
5330 | #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) | |
5331 | #define PORTB_HOTPLUG_ENABLE (1 << 4) | |
5332 | #define PORTB_PULSE_DURATION_2ms (0) | |
5333 | #define PORTB_PULSE_DURATION_4_5ms (1 << 2) | |
5334 | #define PORTB_PULSE_DURATION_6ms (2 << 2) | |
5335 | #define PORTB_PULSE_DURATION_100ms (3 << 2) | |
5336 | #define PORTB_PULSE_DURATION_MASK (3 << 2) | |
5337 | #define PORTB_HOTPLUG_STATUS_MASK (0x3 << 0) | |
5338 | #define PORTB_HOTPLUG_NO_DETECT (0 << 0) | |
5339 | #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) | |
5340 | #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) | |
5341 | ||
5342 | #define PCH_GPIOA 0xc5010 | |
5343 | #define PCH_GPIOB 0xc5014 | |
5344 | #define PCH_GPIOC 0xc5018 | |
5345 | #define PCH_GPIOD 0xc501c | |
5346 | #define PCH_GPIOE 0xc5020 | |
5347 | #define PCH_GPIOF 0xc5024 | |
5348 | ||
5349 | #define PCH_GMBUS0 0xc5100 | |
5350 | #define PCH_GMBUS1 0xc5104 | |
5351 | #define PCH_GMBUS2 0xc5108 | |
5352 | #define PCH_GMBUS3 0xc510c | |
5353 | #define PCH_GMBUS4 0xc5110 | |
5354 | #define PCH_GMBUS5 0xc5120 | |
5355 | ||
5356 | #define _PCH_DPLL_A 0xc6014 | |
5357 | #define _PCH_DPLL_B 0xc6018 | |
5358 | #define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) | |
5359 | ||
5360 | #define _PCH_FPA0 0xc6040 | |
5361 | #define FP_CB_TUNE (0x3<<22) | |
5362 | #define _PCH_FPA1 0xc6044 | |
5363 | #define _PCH_FPB0 0xc6048 | |
5364 | #define _PCH_FPB1 0xc604c | |
5365 | #define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0) | |
5366 | #define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1) | |
5367 | ||
5368 | #define PCH_DPLL_TEST 0xc606c | |
5369 | ||
5370 | #define PCH_DREF_CONTROL 0xC6200 | |
5371 | #define DREF_CONTROL_MASK 0x7fc3 | |
5372 | #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) | |
5373 | #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) | |
5374 | #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) | |
5375 | #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) | |
5376 | #define DREF_SSC_SOURCE_DISABLE (0<<11) | |
5377 | #define DREF_SSC_SOURCE_ENABLE (2<<11) | |
5378 | #define DREF_SSC_SOURCE_MASK (3<<11) | |
5379 | #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) | |
5380 | #define DREF_NONSPREAD_CK505_ENABLE (1<<9) | |
5381 | #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) | |
5382 | #define DREF_NONSPREAD_SOURCE_MASK (3<<9) | |
5383 | #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) | |
5384 | #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) | |
5385 | #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) | |
5386 | #define DREF_SSC4_DOWNSPREAD (0<<6) | |
5387 | #define DREF_SSC4_CENTERSPREAD (1<<6) | |
5388 | #define DREF_SSC1_DISABLE (0<<1) | |
5389 | #define DREF_SSC1_ENABLE (1<<1) | |
5390 | #define DREF_SSC4_DISABLE (0) | |
5391 | #define DREF_SSC4_ENABLE (1) | |
5392 | ||
5393 | #define PCH_RAWCLK_FREQ 0xc6204 | |
5394 | #define FDL_TP1_TIMER_SHIFT 12 | |
5395 | #define FDL_TP1_TIMER_MASK (3<<12) | |
5396 | #define FDL_TP2_TIMER_SHIFT 10 | |
5397 | #define FDL_TP2_TIMER_MASK (3<<10) | |
5398 | #define RAWCLK_FREQ_MASK 0x3ff | |
5399 | ||
5400 | #define PCH_DPLL_TMR_CFG 0xc6208 | |
5401 | ||
5402 | #define PCH_SSC4_PARMS 0xc6210 | |
5403 | #define PCH_SSC4_AUX_PARMS 0xc6214 | |
5404 | ||
5405 | #define PCH_DPLL_SEL 0xc7000 | |
5406 | #define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4)) | |
5407 | #define TRANS_DPLLA_SEL(pipe) 0 | |
5408 | #define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3)) | |
5409 | ||
5410 | /* transcoder */ | |
5411 | ||
5412 | #define _PCH_TRANS_HTOTAL_A 0xe0000 | |
5413 | #define TRANS_HTOTAL_SHIFT 16 | |
5414 | #define TRANS_HACTIVE_SHIFT 0 | |
5415 | #define _PCH_TRANS_HBLANK_A 0xe0004 | |
5416 | #define TRANS_HBLANK_END_SHIFT 16 | |
5417 | #define TRANS_HBLANK_START_SHIFT 0 | |
5418 | #define _PCH_TRANS_HSYNC_A 0xe0008 | |
5419 | #define TRANS_HSYNC_END_SHIFT 16 | |
5420 | #define TRANS_HSYNC_START_SHIFT 0 | |
5421 | #define _PCH_TRANS_VTOTAL_A 0xe000c | |
5422 | #define TRANS_VTOTAL_SHIFT 16 | |
5423 | #define TRANS_VACTIVE_SHIFT 0 | |
5424 | #define _PCH_TRANS_VBLANK_A 0xe0010 | |
5425 | #define TRANS_VBLANK_END_SHIFT 16 | |
5426 | #define TRANS_VBLANK_START_SHIFT 0 | |
5427 | #define _PCH_TRANS_VSYNC_A 0xe0014 | |
5428 | #define TRANS_VSYNC_END_SHIFT 16 | |
5429 | #define TRANS_VSYNC_START_SHIFT 0 | |
5430 | #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 | |
5431 | ||
5432 | #define _PCH_TRANSA_DATA_M1 0xe0030 | |
5433 | #define _PCH_TRANSA_DATA_N1 0xe0034 | |
5434 | #define _PCH_TRANSA_DATA_M2 0xe0038 | |
5435 | #define _PCH_TRANSA_DATA_N2 0xe003c | |
5436 | #define _PCH_TRANSA_LINK_M1 0xe0040 | |
5437 | #define _PCH_TRANSA_LINK_N1 0xe0044 | |
5438 | #define _PCH_TRANSA_LINK_M2 0xe0048 | |
5439 | #define _PCH_TRANSA_LINK_N2 0xe004c | |
5440 | ||
5441 | /* Per-transcoder DIP controls (PCH) */ | |
5442 | #define _VIDEO_DIP_CTL_A 0xe0200 | |
5443 | #define _VIDEO_DIP_DATA_A 0xe0208 | |
5444 | #define _VIDEO_DIP_GCP_A 0xe0210 | |
5445 | ||
5446 | #define _VIDEO_DIP_CTL_B 0xe1200 | |
5447 | #define _VIDEO_DIP_DATA_B 0xe1208 | |
5448 | #define _VIDEO_DIP_GCP_B 0xe1210 | |
5449 | ||
5450 | #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) | |
5451 | #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) | |
5452 | #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) | |
5453 | ||
5454 | /* Per-transcoder DIP controls (VLV) */ | |
5455 | #define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) | |
5456 | #define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) | |
5457 | #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) | |
5458 | ||
5459 | #define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) | |
5460 | #define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) | |
5461 | #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) | |
5462 | ||
5463 | #define CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) | |
5464 | #define CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) | |
5465 | #define CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) | |
5466 | ||
5467 | #define VLV_TVIDEO_DIP_CTL(pipe) \ | |
5468 | _PIPE3((pipe), VLV_VIDEO_DIP_CTL_A, \ | |
5469 | VLV_VIDEO_DIP_CTL_B, CHV_VIDEO_DIP_CTL_C) | |
5470 | #define VLV_TVIDEO_DIP_DATA(pipe) \ | |
5471 | _PIPE3((pipe), VLV_VIDEO_DIP_DATA_A, \ | |
5472 | VLV_VIDEO_DIP_DATA_B, CHV_VIDEO_DIP_DATA_C) | |
5473 | #define VLV_TVIDEO_DIP_GCP(pipe) \ | |
5474 | _PIPE3((pipe), VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ | |
5475 | VLV_VIDEO_DIP_GDCP_PAYLOAD_B, CHV_VIDEO_DIP_GDCP_PAYLOAD_C) | |
5476 | ||
5477 | /* Haswell DIP controls */ | |
5478 | #define HSW_VIDEO_DIP_CTL_A 0x60200 | |
5479 | #define HSW_VIDEO_DIP_AVI_DATA_A 0x60220 | |
5480 | #define HSW_VIDEO_DIP_VS_DATA_A 0x60260 | |
5481 | #define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 | |
5482 | #define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 | |
5483 | #define HSW_VIDEO_DIP_VSC_DATA_A 0x60320 | |
5484 | #define HSW_VIDEO_DIP_AVI_ECC_A 0x60240 | |
5485 | #define HSW_VIDEO_DIP_VS_ECC_A 0x60280 | |
5486 | #define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 | |
5487 | #define HSW_VIDEO_DIP_GMP_ECC_A 0x60300 | |
5488 | #define HSW_VIDEO_DIP_VSC_ECC_A 0x60344 | |
5489 | #define HSW_VIDEO_DIP_GCP_A 0x60210 | |
5490 | ||
5491 | #define HSW_VIDEO_DIP_CTL_B 0x61200 | |
5492 | #define HSW_VIDEO_DIP_AVI_DATA_B 0x61220 | |
5493 | #define HSW_VIDEO_DIP_VS_DATA_B 0x61260 | |
5494 | #define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 | |
5495 | #define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 | |
5496 | #define HSW_VIDEO_DIP_VSC_DATA_B 0x61320 | |
5497 | #define HSW_VIDEO_DIP_BVI_ECC_B 0x61240 | |
5498 | #define HSW_VIDEO_DIP_VS_ECC_B 0x61280 | |
5499 | #define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 | |
5500 | #define HSW_VIDEO_DIP_GMP_ECC_B 0x61300 | |
5501 | #define HSW_VIDEO_DIP_VSC_ECC_B 0x61344 | |
5502 | #define HSW_VIDEO_DIP_GCP_B 0x61210 | |
5503 | ||
5504 | #define HSW_TVIDEO_DIP_CTL(trans) \ | |
5505 | _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A) | |
5506 | #define HSW_TVIDEO_DIP_AVI_DATA(trans) \ | |
5507 | _TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A) | |
5508 | #define HSW_TVIDEO_DIP_VS_DATA(trans) \ | |
5509 | _TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A) | |
5510 | #define HSW_TVIDEO_DIP_SPD_DATA(trans) \ | |
5511 | _TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A) | |
5512 | #define HSW_TVIDEO_DIP_GCP(trans) \ | |
5513 | _TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A) | |
5514 | #define HSW_TVIDEO_DIP_VSC_DATA(trans) \ | |
5515 | _TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A) | |
5516 | ||
5517 | #define HSW_STEREO_3D_CTL_A 0x70020 | |
5518 | #define S3D_ENABLE (1<<31) | |
5519 | #define HSW_STEREO_3D_CTL_B 0x71020 | |
5520 | ||
5521 | #define HSW_STEREO_3D_CTL(trans) \ | |
5522 | _PIPE2(trans, HSW_STEREO_3D_CTL_A) | |
5523 | ||
5524 | #define _PCH_TRANS_HTOTAL_B 0xe1000 | |
5525 | #define _PCH_TRANS_HBLANK_B 0xe1004 | |
5526 | #define _PCH_TRANS_HSYNC_B 0xe1008 | |
5527 | #define _PCH_TRANS_VTOTAL_B 0xe100c | |
5528 | #define _PCH_TRANS_VBLANK_B 0xe1010 | |
5529 | #define _PCH_TRANS_VSYNC_B 0xe1014 | |
5530 | #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 | |
5531 | ||
5532 | #define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) | |
5533 | #define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) | |
5534 | #define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) | |
5535 | #define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) | |
5536 | #define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) | |
5537 | #define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) | |
5538 | #define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \ | |
5539 | _PCH_TRANS_VSYNCSHIFT_B) | |
5540 | ||
5541 | #define _PCH_TRANSB_DATA_M1 0xe1030 | |
5542 | #define _PCH_TRANSB_DATA_N1 0xe1034 | |
5543 | #define _PCH_TRANSB_DATA_M2 0xe1038 | |
5544 | #define _PCH_TRANSB_DATA_N2 0xe103c | |
5545 | #define _PCH_TRANSB_LINK_M1 0xe1040 | |
5546 | #define _PCH_TRANSB_LINK_N1 0xe1044 | |
5547 | #define _PCH_TRANSB_LINK_M2 0xe1048 | |
5548 | #define _PCH_TRANSB_LINK_N2 0xe104c | |
5549 | ||
5550 | #define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) | |
5551 | #define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) | |
5552 | #define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) | |
5553 | #define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) | |
5554 | #define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) | |
5555 | #define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) | |
5556 | #define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) | |
5557 | #define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) | |
5558 | ||
5559 | #define _PCH_TRANSACONF 0xf0008 | |
5560 | #define _PCH_TRANSBCONF 0xf1008 | |
5561 | #define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) | |
5562 | #define LPT_TRANSCONF _PCH_TRANSACONF /* lpt has only one transcoder */ | |
5563 | #define TRANS_DISABLE (0<<31) | |
5564 | #define TRANS_ENABLE (1<<31) | |
5565 | #define TRANS_STATE_MASK (1<<30) | |
5566 | #define TRANS_STATE_DISABLE (0<<30) | |
5567 | #define TRANS_STATE_ENABLE (1<<30) | |
5568 | #define TRANS_FSYNC_DELAY_HB1 (0<<27) | |
5569 | #define TRANS_FSYNC_DELAY_HB2 (1<<27) | |
5570 | #define TRANS_FSYNC_DELAY_HB3 (2<<27) | |
5571 | #define TRANS_FSYNC_DELAY_HB4 (3<<27) | |
5572 | #define TRANS_INTERLACE_MASK (7<<21) | |
5573 | #define TRANS_PROGRESSIVE (0<<21) | |
5574 | #define TRANS_INTERLACED (3<<21) | |
5575 | #define TRANS_LEGACY_INTERLACED_ILK (2<<21) | |
5576 | #define TRANS_8BPC (0<<5) | |
5577 | #define TRANS_10BPC (1<<5) | |
5578 | #define TRANS_6BPC (2<<5) | |
5579 | #define TRANS_12BPC (3<<5) | |
5580 | ||
5581 | #define _TRANSA_CHICKEN1 0xf0060 | |
5582 | #define _TRANSB_CHICKEN1 0xf1060 | |
5583 | #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) | |
5584 | #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4) | |
5585 | #define _TRANSA_CHICKEN2 0xf0064 | |
5586 | #define _TRANSB_CHICKEN2 0xf1064 | |
5587 | #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) | |
5588 | #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31) | |
5589 | #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29) | |
5590 | #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27) | |
5591 | #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26) | |
5592 | #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25) | |
5593 | ||
5594 | #define SOUTH_CHICKEN1 0xc2000 | |
5595 | #define FDIA_PHASE_SYNC_SHIFT_OVR 19 | |
5596 | #define FDIA_PHASE_SYNC_SHIFT_EN 18 | |
5597 | #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) | |
5598 | #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) | |
5599 | #define FDI_BC_BIFURCATION_SELECT (1 << 12) | |
5600 | #define SOUTH_CHICKEN2 0xc2004 | |
5601 | #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13) | |
5602 | #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12) | |
5603 | #define DPLS_EDP_PPS_FIX_DIS (1<<0) | |
5604 | ||
5605 | #define _FDI_RXA_CHICKEN 0xc200c | |
5606 | #define _FDI_RXB_CHICKEN 0xc2010 | |
5607 | #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) | |
5608 | #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) | |
5609 | #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) | |
5610 | ||
5611 | #define SOUTH_DSPCLK_GATE_D 0xc2020 | |
5612 | #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30) | |
5613 | #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) | |
5614 | #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14) | |
5615 | #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) | |
5616 | ||
5617 | /* CPU: FDI_TX */ | |
5618 | #define _FDI_TXA_CTL 0x60100 | |
5619 | #define _FDI_TXB_CTL 0x61100 | |
5620 | #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) | |
5621 | #define FDI_TX_DISABLE (0<<31) | |
5622 | #define FDI_TX_ENABLE (1<<31) | |
5623 | #define FDI_LINK_TRAIN_PATTERN_1 (0<<28) | |
5624 | #define FDI_LINK_TRAIN_PATTERN_2 (1<<28) | |
5625 | #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) | |
5626 | #define FDI_LINK_TRAIN_NONE (3<<28) | |
5627 | #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) | |
5628 | #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) | |
5629 | #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) | |
5630 | #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) | |
5631 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) | |
5632 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) | |
5633 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) | |
5634 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) | |
5635 | /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. | |
5636 | SNB has different settings. */ | |
5637 | /* SNB A-stepping */ | |
5638 | #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) | |
5639 | #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) | |
5640 | #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) | |
5641 | #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) | |
5642 | /* SNB B-stepping */ | |
5643 | #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) | |
5644 | #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) | |
5645 | #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) | |
5646 | #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) | |
5647 | #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) | |
5648 | #define FDI_DP_PORT_WIDTH_SHIFT 19 | |
5649 | #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) | |
5650 | #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) | |
5651 | #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) | |
5652 | /* Ironlake: hardwired to 1 */ | |
5653 | #define FDI_TX_PLL_ENABLE (1<<14) | |
5654 | ||
5655 | /* Ivybridge has different bits for lolz */ | |
5656 | #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) | |
5657 | #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) | |
5658 | #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) | |
5659 | #define FDI_LINK_TRAIN_NONE_IVB (3<<8) | |
5660 | ||
5661 | /* both Tx and Rx */ | |
5662 | #define FDI_COMPOSITE_SYNC (1<<11) | |
5663 | #define FDI_LINK_TRAIN_AUTO (1<<10) | |
5664 | #define FDI_SCRAMBLING_ENABLE (0<<7) | |
5665 | #define FDI_SCRAMBLING_DISABLE (1<<7) | |
5666 | ||
5667 | /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ | |
5668 | #define _FDI_RXA_CTL 0xf000c | |
5669 | #define _FDI_RXB_CTL 0xf100c | |
5670 | #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) | |
5671 | #define FDI_RX_ENABLE (1<<31) | |
5672 | /* train, dp width same as FDI_TX */ | |
5673 | #define FDI_FS_ERRC_ENABLE (1<<27) | |
5674 | #define FDI_FE_ERRC_ENABLE (1<<26) | |
5675 | #define FDI_RX_POLARITY_REVERSED_LPT (1<<16) | |
5676 | #define FDI_8BPC (0<<16) | |
5677 | #define FDI_10BPC (1<<16) | |
5678 | #define FDI_6BPC (2<<16) | |
5679 | #define FDI_12BPC (3<<16) | |
5680 | #define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15) | |
5681 | #define FDI_DMI_LINK_REVERSE_MASK (1<<14) | |
5682 | #define FDI_RX_PLL_ENABLE (1<<13) | |
5683 | #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) | |
5684 | #define FDI_FE_ERR_CORRECT_ENABLE (1<<10) | |
5685 | #define FDI_FS_ERR_REPORT_ENABLE (1<<9) | |
5686 | #define FDI_FE_ERR_REPORT_ENABLE (1<<8) | |
5687 | #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) | |
5688 | #define FDI_PCDCLK (1<<4) | |
5689 | /* CPT */ | |
5690 | #define FDI_AUTO_TRAINING (1<<10) | |
5691 | #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) | |
5692 | #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) | |
5693 | #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) | |
5694 | #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) | |
5695 | #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) | |
5696 | ||
5697 | #define _FDI_RXA_MISC 0xf0010 | |
5698 | #define _FDI_RXB_MISC 0xf1010 | |
5699 | #define FDI_RX_PWRDN_LANE1_MASK (3<<26) | |
5700 | #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26) | |
5701 | #define FDI_RX_PWRDN_LANE0_MASK (3<<24) | |
5702 | #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24) | |
5703 | #define FDI_RX_TP1_TO_TP2_48 (2<<20) | |
5704 | #define FDI_RX_TP1_TO_TP2_64 (3<<20) | |
5705 | #define FDI_RX_FDI_DELAY_90 (0x90<<0) | |
5706 | #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) | |
5707 | ||
5708 | #define _FDI_RXA_TUSIZE1 0xf0030 | |
5709 | #define _FDI_RXA_TUSIZE2 0xf0038 | |
5710 | #define _FDI_RXB_TUSIZE1 0xf1030 | |
5711 | #define _FDI_RXB_TUSIZE2 0xf1038 | |
5712 | #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) | |
5713 | #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) | |
5714 | ||
5715 | /* FDI_RX interrupt register format */ | |
5716 | #define FDI_RX_INTER_LANE_ALIGN (1<<10) | |
5717 | #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ | |
5718 | #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ | |
5719 | #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) | |
5720 | #define FDI_RX_FS_CODE_ERR (1<<6) | |
5721 | #define FDI_RX_FE_CODE_ERR (1<<5) | |
5722 | #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) | |
5723 | #define FDI_RX_HDCP_LINK_FAIL (1<<3) | |
5724 | #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) | |
5725 | #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) | |
5726 | #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) | |
5727 | ||
5728 | #define _FDI_RXA_IIR 0xf0014 | |
5729 | #define _FDI_RXA_IMR 0xf0018 | |
5730 | #define _FDI_RXB_IIR 0xf1014 | |
5731 | #define _FDI_RXB_IMR 0xf1018 | |
5732 | #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) | |
5733 | #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) | |
5734 | ||
5735 | #define FDI_PLL_CTL_1 0xfe000 | |
5736 | #define FDI_PLL_CTL_2 0xfe004 | |
5737 | ||
5738 | #define PCH_LVDS 0xe1180 | |
5739 | #define LVDS_DETECTED (1 << 1) | |
5740 | ||
5741 | /* vlv has 2 sets of panel control regs. */ | |
5742 | #define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200) | |
5743 | #define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204) | |
5744 | #define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208) | |
5745 | #define PANEL_PORT_SELECT_VLV(port) ((port) << 30) | |
5746 | #define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c) | |
5747 | #define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210) | |
5748 | ||
5749 | #define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300) | |
5750 | #define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304) | |
5751 | #define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308) | |
5752 | #define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c) | |
5753 | #define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310) | |
5754 | ||
5755 | #define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS) | |
5756 | #define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL) | |
5757 | #define VLV_PIPE_PP_ON_DELAYS(pipe) \ | |
5758 | _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS) | |
5759 | #define VLV_PIPE_PP_OFF_DELAYS(pipe) \ | |
5760 | _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS) | |
5761 | #define VLV_PIPE_PP_DIVISOR(pipe) \ | |
5762 | _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR) | |
5763 | ||
5764 | #define PCH_PP_STATUS 0xc7200 | |
5765 | #define PCH_PP_CONTROL 0xc7204 | |
5766 | #define PANEL_UNLOCK_REGS (0xabcd << 16) | |
5767 | #define PANEL_UNLOCK_MASK (0xffff << 16) | |
5768 | #define EDP_FORCE_VDD (1 << 3) | |
5769 | #define EDP_BLC_ENABLE (1 << 2) | |
5770 | #define PANEL_POWER_RESET (1 << 1) | |
5771 | #define PANEL_POWER_OFF (0 << 0) | |
5772 | #define PANEL_POWER_ON (1 << 0) | |
5773 | #define PCH_PP_ON_DELAYS 0xc7208 | |
5774 | #define PANEL_PORT_SELECT_MASK (3 << 30) | |
5775 | #define PANEL_PORT_SELECT_LVDS (0 << 30) | |
5776 | #define PANEL_PORT_SELECT_DPA (1 << 30) | |
5777 | #define PANEL_PORT_SELECT_DPC (2 << 30) | |
5778 | #define PANEL_PORT_SELECT_DPD (3 << 30) | |
5779 | #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) | |
5780 | #define PANEL_POWER_UP_DELAY_SHIFT 16 | |
5781 | #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) | |
5782 | #define PANEL_LIGHT_ON_DELAY_SHIFT 0 | |
5783 | ||
5784 | #define PCH_PP_OFF_DELAYS 0xc720c | |
5785 | #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) | |
5786 | #define PANEL_POWER_DOWN_DELAY_SHIFT 16 | |
5787 | #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) | |
5788 | #define PANEL_LIGHT_OFF_DELAY_SHIFT 0 | |
5789 | ||
5790 | #define PCH_PP_DIVISOR 0xc7210 | |
5791 | #define PP_REFERENCE_DIVIDER_MASK (0xffffff00) | |
5792 | #define PP_REFERENCE_DIVIDER_SHIFT 8 | |
5793 | #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) | |
5794 | #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 | |
5795 | ||
5796 | #define PCH_DP_B 0xe4100 | |
5797 | #define PCH_DPB_AUX_CH_CTL 0xe4110 | |
5798 | #define PCH_DPB_AUX_CH_DATA1 0xe4114 | |
5799 | #define PCH_DPB_AUX_CH_DATA2 0xe4118 | |
5800 | #define PCH_DPB_AUX_CH_DATA3 0xe411c | |
5801 | #define PCH_DPB_AUX_CH_DATA4 0xe4120 | |
5802 | #define PCH_DPB_AUX_CH_DATA5 0xe4124 | |
5803 | ||
5804 | #define PCH_DP_C 0xe4200 | |
5805 | #define PCH_DPC_AUX_CH_CTL 0xe4210 | |
5806 | #define PCH_DPC_AUX_CH_DATA1 0xe4214 | |
5807 | #define PCH_DPC_AUX_CH_DATA2 0xe4218 | |
5808 | #define PCH_DPC_AUX_CH_DATA3 0xe421c | |
5809 | #define PCH_DPC_AUX_CH_DATA4 0xe4220 | |
5810 | #define PCH_DPC_AUX_CH_DATA5 0xe4224 | |
5811 | ||
5812 | #define PCH_DP_D 0xe4300 | |
5813 | #define PCH_DPD_AUX_CH_CTL 0xe4310 | |
5814 | #define PCH_DPD_AUX_CH_DATA1 0xe4314 | |
5815 | #define PCH_DPD_AUX_CH_DATA2 0xe4318 | |
5816 | #define PCH_DPD_AUX_CH_DATA3 0xe431c | |
5817 | #define PCH_DPD_AUX_CH_DATA4 0xe4320 | |
5818 | #define PCH_DPD_AUX_CH_DATA5 0xe4324 | |
5819 | ||
5820 | /* CPT */ | |
5821 | #define PORT_TRANS_A_SEL_CPT 0 | |
5822 | #define PORT_TRANS_B_SEL_CPT (1<<29) | |
5823 | #define PORT_TRANS_C_SEL_CPT (2<<29) | |
5824 | #define PORT_TRANS_SEL_MASK (3<<29) | |
5825 | #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) | |
5826 | #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30) | |
5827 | #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29) | |
5828 | #define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24) | |
5829 | #define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16) | |
5830 | ||
5831 | #define TRANS_DP_CTL_A 0xe0300 | |
5832 | #define TRANS_DP_CTL_B 0xe1300 | |
5833 | #define TRANS_DP_CTL_C 0xe2300 | |
5834 | #define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B) | |
5835 | #define TRANS_DP_OUTPUT_ENABLE (1<<31) | |
5836 | #define TRANS_DP_PORT_SEL_B (0<<29) | |
5837 | #define TRANS_DP_PORT_SEL_C (1<<29) | |
5838 | #define TRANS_DP_PORT_SEL_D (2<<29) | |
5839 | #define TRANS_DP_PORT_SEL_NONE (3<<29) | |
5840 | #define TRANS_DP_PORT_SEL_MASK (3<<29) | |
5841 | #define TRANS_DP_AUDIO_ONLY (1<<26) | |
5842 | #define TRANS_DP_ENH_FRAMING (1<<18) | |
5843 | #define TRANS_DP_8BPC (0<<9) | |
5844 | #define TRANS_DP_10BPC (1<<9) | |
5845 | #define TRANS_DP_6BPC (2<<9) | |
5846 | #define TRANS_DP_12BPC (3<<9) | |
5847 | #define TRANS_DP_BPC_MASK (3<<9) | |
5848 | #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) | |
5849 | #define TRANS_DP_VSYNC_ACTIVE_LOW 0 | |
5850 | #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) | |
5851 | #define TRANS_DP_HSYNC_ACTIVE_LOW 0 | |
5852 | #define TRANS_DP_SYNC_MASK (3<<3) | |
5853 | ||
5854 | /* SNB eDP training params */ | |
5855 | /* SNB A-stepping */ | |
5856 | #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) | |
5857 | #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) | |
5858 | #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) | |
5859 | #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) | |
5860 | /* SNB B-stepping */ | |
5861 | #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) | |
5862 | #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) | |
5863 | #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) | |
5864 | #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) | |
5865 | #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) | |
5866 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) | |
5867 | ||
5868 | /* IVB */ | |
5869 | #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22) | |
5870 | #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22) | |
5871 | #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22) | |
5872 | #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22) | |
5873 | #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22) | |
5874 | #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22) | |
5875 | #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22) | |
5876 | ||
5877 | /* legacy values */ | |
5878 | #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22) | |
5879 | #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22) | |
5880 | #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22) | |
5881 | #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22) | |
5882 | #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22) | |
5883 | ||
5884 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) | |
5885 | ||
5886 | #define VLV_PMWGICZ 0x1300a4 | |
5887 | ||
5888 | #define FORCEWAKE 0xA18C | |
5889 | #define FORCEWAKE_VLV 0x1300b0 | |
5890 | #define FORCEWAKE_ACK_VLV 0x1300b4 | |
5891 | #define FORCEWAKE_MEDIA_VLV 0x1300b8 | |
5892 | #define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc | |
5893 | #define FORCEWAKE_ACK_HSW 0x130044 | |
5894 | #define FORCEWAKE_ACK 0x130090 | |
5895 | #define VLV_GTLC_WAKE_CTRL 0x130090 | |
5896 | #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25) | |
5897 | #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24) | |
5898 | #define VLV_GTLC_ALLOWWAKEREQ (1 << 0) | |
5899 | ||
5900 | #define VLV_GTLC_PW_STATUS 0x130094 | |
5901 | #define VLV_GTLC_ALLOWWAKEACK (1 << 0) | |
5902 | #define VLV_GTLC_ALLOWWAKEERR (1 << 1) | |
5903 | #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5) | |
5904 | #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7) | |
5905 | #define FORCEWAKE_MT 0xa188 /* multi-threaded */ | |
5906 | #define FORCEWAKE_MEDIA_GEN9 0xa270 | |
5907 | #define FORCEWAKE_RENDER_GEN9 0xa278 | |
5908 | #define FORCEWAKE_BLITTER_GEN9 0xa188 | |
5909 | #define FORCEWAKE_ACK_MEDIA_GEN9 0x0D88 | |
5910 | #define FORCEWAKE_ACK_RENDER_GEN9 0x0D84 | |
5911 | #define FORCEWAKE_ACK_BLITTER_GEN9 0x130044 | |
5912 | #define FORCEWAKE_KERNEL 0x1 | |
5913 | #define FORCEWAKE_USER 0x2 | |
5914 | #define FORCEWAKE_MT_ACK 0x130040 | |
5915 | #define ECOBUS 0xa180 | |
5916 | #define FORCEWAKE_MT_ENABLE (1<<5) | |
5917 | #define VLV_SPAREG2H 0xA194 | |
5918 | ||
5919 | #define GTFIFODBG 0x120000 | |
5920 | #define GT_FIFO_SBDROPERR (1<<6) | |
5921 | #define GT_FIFO_BLOBDROPERR (1<<5) | |
5922 | #define GT_FIFO_SB_READ_ABORTERR (1<<4) | |
5923 | #define GT_FIFO_DROPERR (1<<3) | |
5924 | #define GT_FIFO_OVFERR (1<<2) | |
5925 | #define GT_FIFO_IAWRERR (1<<1) | |
5926 | #define GT_FIFO_IARDERR (1<<0) | |
5927 | ||
5928 | #define GTFIFOCTL 0x120008 | |
5929 | #define GT_FIFO_FREE_ENTRIES_MASK 0x7f | |
5930 | #define GT_FIFO_NUM_RESERVED_ENTRIES 20 | |
5931 | ||
5932 | #define HSW_IDICR 0x9008 | |
5933 | #define IDIHASHMSK(x) (((x) & 0x3f) << 16) | |
5934 | #define HSW_EDRAM_PRESENT 0x120010 | |
5935 | ||
5936 | #define GEN6_UCGCTL1 0x9400 | |
5937 | # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16) | |
5938 | # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) | |
5939 | # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) | |
5940 | ||
5941 | #define GEN6_UCGCTL2 0x9404 | |
5942 | # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) | |
5943 | # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) | |
5944 | # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) | |
5945 | # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) | |
5946 | # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) | |
5947 | ||
5948 | #define GEN6_UCGCTL3 0x9408 | |
5949 | ||
5950 | #define GEN7_UCGCTL4 0x940c | |
5951 | #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25) | |
5952 | ||
5953 | #define GEN6_RCGCTL1 0x9410 | |
5954 | #define GEN6_RCGCTL2 0x9414 | |
5955 | #define GEN6_RSTCTL 0x9420 | |
5956 | ||
5957 | #define GEN8_UCGCTL6 0x9430 | |
5958 | #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14) | |
5959 | ||
5960 | #define GEN6_GFXPAUSE 0xA000 | |
5961 | #define GEN6_RPNSWREQ 0xA008 | |
5962 | #define GEN6_TURBO_DISABLE (1<<31) | |
5963 | #define GEN6_FREQUENCY(x) ((x)<<25) | |
5964 | #define HSW_FREQUENCY(x) ((x)<<24) | |
5965 | #define GEN6_OFFSET(x) ((x)<<19) | |
5966 | #define GEN6_AGGRESSIVE_TURBO (0<<15) | |
5967 | #define GEN6_RC_VIDEO_FREQ 0xA00C | |
5968 | #define GEN6_RC_CONTROL 0xA090 | |
5969 | #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) | |
5970 | #define GEN6_RC_CTL_RC6p_ENABLE (1<<17) | |
5971 | #define GEN6_RC_CTL_RC6_ENABLE (1<<18) | |
5972 | #define GEN6_RC_CTL_RC1e_ENABLE (1<<20) | |
5973 | #define GEN6_RC_CTL_RC7_ENABLE (1<<22) | |
5974 | #define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24) | |
5975 | #define GEN7_RC_CTL_TO_MODE (1<<28) | |
5976 | #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) | |
5977 | #define GEN6_RC_CTL_HW_ENABLE (1<<31) | |
5978 | #define GEN6_RP_DOWN_TIMEOUT 0xA010 | |
5979 | #define GEN6_RP_INTERRUPT_LIMITS 0xA014 | |
5980 | #define GEN6_RPSTAT1 0xA01C | |
5981 | #define GEN6_CAGF_SHIFT 8 | |
5982 | #define HSW_CAGF_SHIFT 7 | |
5983 | #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) | |
5984 | #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT) | |
5985 | #define GEN6_RP_CONTROL 0xA024 | |
5986 | #define GEN6_RP_MEDIA_TURBO (1<<11) | |
5987 | #define GEN6_RP_MEDIA_MODE_MASK (3<<9) | |
5988 | #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) | |
5989 | #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) | |
5990 | #define GEN6_RP_MEDIA_HW_MODE (1<<9) | |
5991 | #define GEN6_RP_MEDIA_SW_MODE (0<<9) | |
5992 | #define GEN6_RP_MEDIA_IS_GFX (1<<8) | |
5993 | #define GEN6_RP_ENABLE (1<<7) | |
5994 | #define GEN6_RP_UP_IDLE_MIN (0x1<<3) | |
5995 | #define GEN6_RP_UP_BUSY_AVG (0x2<<3) | |
5996 | #define GEN6_RP_UP_BUSY_CONT (0x4<<3) | |
5997 | #define GEN6_RP_DOWN_IDLE_AVG (0x2<<0) | |
5998 | #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) | |
5999 | #define GEN6_RP_UP_THRESHOLD 0xA02C | |
6000 | #define GEN6_RP_DOWN_THRESHOLD 0xA030 | |
6001 | #define GEN6_RP_CUR_UP_EI 0xA050 | |
6002 | #define GEN6_CURICONT_MASK 0xffffff | |
6003 | #define GEN6_RP_CUR_UP 0xA054 | |
6004 | #define GEN6_CURBSYTAVG_MASK 0xffffff | |
6005 | #define GEN6_RP_PREV_UP 0xA058 | |
6006 | #define GEN6_RP_CUR_DOWN_EI 0xA05C | |
6007 | #define GEN6_CURIAVG_MASK 0xffffff | |
6008 | #define GEN6_RP_CUR_DOWN 0xA060 | |
6009 | #define GEN6_RP_PREV_DOWN 0xA064 | |
6010 | #define GEN6_RP_UP_EI 0xA068 | |
6011 | #define GEN6_RP_DOWN_EI 0xA06C | |
6012 | #define GEN6_RP_IDLE_HYSTERSIS 0xA070 | |
6013 | #define GEN6_RPDEUHWTC 0xA080 | |
6014 | #define GEN6_RPDEUC 0xA084 | |
6015 | #define GEN6_RPDEUCSW 0xA088 | |
6016 | #define GEN6_RC_STATE 0xA094 | |
6017 | #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098 | |
6018 | #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C | |
6019 | #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0 | |
6020 | #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8 | |
6021 | #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC | |
6022 | #define GEN6_RC_SLEEP 0xA0B0 | |
6023 | #define GEN6_RCUBMABDTMR 0xA0B0 | |
6024 | #define GEN6_RC1e_THRESHOLD 0xA0B4 | |
6025 | #define GEN6_RC6_THRESHOLD 0xA0B8 | |
6026 | #define GEN6_RC6p_THRESHOLD 0xA0BC | |
6027 | #define VLV_RCEDATA 0xA0BC | |
6028 | #define GEN6_RC6pp_THRESHOLD 0xA0C0 | |
6029 | #define GEN6_PMINTRMSK 0xA168 | |
6030 | #define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31) | |
6031 | #define VLV_PWRDWNUPCTL 0xA294 | |
6032 | ||
6033 | #define GEN6_PMISR 0x44020 | |
6034 | #define GEN6_PMIMR 0x44024 /* rps_lock */ | |
6035 | #define GEN6_PMIIR 0x44028 | |
6036 | #define GEN6_PMIER 0x4402C | |
6037 | #define GEN6_PM_MBOX_EVENT (1<<25) | |
6038 | #define GEN6_PM_THERMAL_EVENT (1<<24) | |
6039 | #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6) | |
6040 | #define GEN6_PM_RP_UP_THRESHOLD (1<<5) | |
6041 | #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4) | |
6042 | #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2) | |
6043 | #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) | |
6044 | #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ | |
6045 | GEN6_PM_RP_DOWN_THRESHOLD | \ | |
6046 | GEN6_PM_RP_DOWN_TIMEOUT) | |
6047 | ||
6048 | #define GEN7_GT_SCRATCH_BASE 0x4F100 | |
6049 | #define GEN7_GT_SCRATCH_REG_NUM 8 | |
6050 | ||
6051 | #define VLV_GTLC_SURVIVABILITY_REG 0x130098 | |
6052 | #define VLV_GFX_CLK_STATUS_BIT (1<<3) | |
6053 | #define VLV_GFX_CLK_FORCE_ON_BIT (1<<2) | |
6054 | ||
6055 | #define GEN6_GT_GFX_RC6_LOCKED 0x138104 | |
6056 | #define VLV_COUNTER_CONTROL 0x138104 | |
6057 | #define VLV_COUNT_RANGE_HIGH (1<<15) | |
6058 | #define VLV_MEDIA_RC0_COUNT_EN (1<<5) | |
6059 | #define VLV_RENDER_RC0_COUNT_EN (1<<4) | |
6060 | #define VLV_MEDIA_RC6_COUNT_EN (1<<1) | |
6061 | #define VLV_RENDER_RC6_COUNT_EN (1<<0) | |
6062 | #define GEN6_GT_GFX_RC6 0x138108 | |
6063 | #define VLV_GT_RENDER_RC6 0x138108 | |
6064 | #define VLV_GT_MEDIA_RC6 0x13810C | |
6065 | ||
6066 | #define GEN6_GT_GFX_RC6p 0x13810C | |
6067 | #define GEN6_GT_GFX_RC6pp 0x138110 | |
6068 | #define VLV_RENDER_C0_COUNT_REG 0x138118 | |
6069 | #define VLV_MEDIA_C0_COUNT_REG 0x13811C | |
6070 | ||
6071 | #define GEN6_PCODE_MAILBOX 0x138124 | |
6072 | #define GEN6_PCODE_READY (1<<31) | |
6073 | #define GEN6_READ_OC_PARAMS 0xc | |
6074 | #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 | |
6075 | #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 | |
6076 | #define GEN6_PCODE_WRITE_RC6VIDS 0x4 | |
6077 | #define GEN6_PCODE_READ_RC6VIDS 0x5 | |
6078 | #define GEN6_PCODE_READ_D_COMP 0x10 | |
6079 | #define GEN6_PCODE_WRITE_D_COMP 0x11 | |
6080 | #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) | |
6081 | #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) | |
6082 | #define DISPLAY_IPS_CONTROL 0x19 | |
6083 | #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A | |
6084 | #define GEN6_PCODE_DATA 0x138128 | |
6085 | #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 | |
6086 | #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 | |
6087 | #define GEN6_PCODE_DATA1 0x13812C | |
6088 | ||
6089 | #define GEN9_PCODE_READ_MEM_LATENCY 0x6 | |
6090 | #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF | |
6091 | #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 | |
6092 | #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 | |
6093 | #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 | |
6094 | ||
6095 | #define GEN6_GT_CORE_STATUS 0x138060 | |
6096 | #define GEN6_CORE_CPD_STATE_MASK (7<<4) | |
6097 | #define GEN6_RCn_MASK 7 | |
6098 | #define GEN6_RC0 0 | |
6099 | #define GEN6_RC3 2 | |
6100 | #define GEN6_RC6 3 | |
6101 | #define GEN6_RC7 4 | |
6102 | ||
6103 | #define GEN7_MISCCPCTL (0x9424) | |
6104 | #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0) | |
6105 | ||
6106 | /* IVYBRIDGE DPF */ | |
6107 | #define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */ | |
6108 | #define HSW_L3CDERRST11 0xB208 /* L3CD Error Status register 1 slice 1 */ | |
6109 | #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14) | |
6110 | #define GEN7_PARITY_ERROR_VALID (1<<13) | |
6111 | #define GEN7_L3CDERRST1_BANK_MASK (3<<11) | |
6112 | #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8) | |
6113 | #define GEN7_PARITY_ERROR_ROW(reg) \ | |
6114 | ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14) | |
6115 | #define GEN7_PARITY_ERROR_BANK(reg) \ | |
6116 | ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11) | |
6117 | #define GEN7_PARITY_ERROR_SUBBANK(reg) \ | |
6118 | ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) | |
6119 | #define GEN7_L3CDERRST1_ENABLE (1<<7) | |
6120 | ||
6121 | #define GEN7_L3LOG_BASE 0xB070 | |
6122 | #define HSW_L3LOG_BASE_SLICE1 0xB270 | |
6123 | #define GEN7_L3LOG_SIZE 0x80 | |
6124 | ||
6125 | #define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */ | |
6126 | #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100 | |
6127 | #define GEN7_MAX_PS_THREAD_DEP (8<<12) | |
6128 | #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10) | |
6129 | #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) | |
6130 | ||
6131 | #define GEN9_HALF_SLICE_CHICKEN5 0xe188 | |
6132 | #define GEN9_DG_MIRROR_FIX_ENABLE (1<<5) | |
6133 | ||
6134 | #define GEN8_ROW_CHICKEN 0xe4f0 | |
6135 | #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8) | |
6136 | #define STALL_DOP_GATING_DISABLE (1<<5) | |
6137 | ||
6138 | #define GEN7_ROW_CHICKEN2 0xe4f4 | |
6139 | #define GEN7_ROW_CHICKEN2_GT2 0xf4f4 | |
6140 | #define DOP_CLOCK_GATING_DISABLE (1<<0) | |
6141 | ||
6142 | #define HSW_ROW_CHICKEN3 0xe49c | |
6143 | #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) | |
6144 | ||
6145 | #define HALF_SLICE_CHICKEN3 0xe184 | |
6146 | #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8) | |
6147 | #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1) | |
6148 | ||
6149 | /* Audio */ | |
6150 | #define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020) | |
6151 | #define INTEL_AUDIO_DEVCL 0x808629FB | |
6152 | #define INTEL_AUDIO_DEVBLC 0x80862801 | |
6153 | #define INTEL_AUDIO_DEVCTG 0x80862802 | |
6154 | ||
6155 | #define G4X_AUD_CNTL_ST 0x620B4 | |
6156 | #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) | |
6157 | #define G4X_ELDV_DEVCTG (1 << 14) | |
6158 | #define G4X_ELD_ADDR_MASK (0xf << 5) | |
6159 | #define G4X_ELD_ACK (1 << 4) | |
6160 | #define G4X_HDMIW_HDMIEDID 0x6210C | |
6161 | ||
6162 | #define _IBX_HDMIW_HDMIEDID_A 0xE2050 | |
6163 | #define _IBX_HDMIW_HDMIEDID_B 0xE2150 | |
6164 | #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ | |
6165 | _IBX_HDMIW_HDMIEDID_A, \ | |
6166 | _IBX_HDMIW_HDMIEDID_B) | |
6167 | #define _IBX_AUD_CNTL_ST_A 0xE20B4 | |
6168 | #define _IBX_AUD_CNTL_ST_B 0xE21B4 | |
6169 | #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \ | |
6170 | _IBX_AUD_CNTL_ST_A, \ | |
6171 | _IBX_AUD_CNTL_ST_B) | |
6172 | #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10) | |
6173 | #define IBX_ELD_ADDRESS_MASK (0x1f << 5) | |
6174 | #define IBX_ELD_ACK (1 << 4) | |
6175 | #define IBX_AUD_CNTL_ST2 0xE20C0 | |
6176 | #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4)) | |
6177 | #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4)) | |
6178 | ||
6179 | #define _CPT_HDMIW_HDMIEDID_A 0xE5050 | |
6180 | #define _CPT_HDMIW_HDMIEDID_B 0xE5150 | |
6181 | #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ | |
6182 | _CPT_HDMIW_HDMIEDID_A, \ | |
6183 | _CPT_HDMIW_HDMIEDID_B) | |
6184 | #define _CPT_AUD_CNTL_ST_A 0xE50B4 | |
6185 | #define _CPT_AUD_CNTL_ST_B 0xE51B4 | |
6186 | #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \ | |
6187 | _CPT_AUD_CNTL_ST_A, \ | |
6188 | _CPT_AUD_CNTL_ST_B) | |
6189 | #define CPT_AUD_CNTRL_ST2 0xE50C0 | |
6190 | ||
6191 | #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) | |
6192 | #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) | |
6193 | #define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ | |
6194 | _VLV_HDMIW_HDMIEDID_A, \ | |
6195 | _VLV_HDMIW_HDMIEDID_B) | |
6196 | #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) | |
6197 | #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) | |
6198 | #define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \ | |
6199 | _VLV_AUD_CNTL_ST_A, \ | |
6200 | _VLV_AUD_CNTL_ST_B) | |
6201 | #define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0) | |
6202 | ||
6203 | /* These are the 4 32-bit write offset registers for each stream | |
6204 | * output buffer. It determines the offset from the | |
6205 | * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. | |
6206 | */ | |
6207 | #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4) | |
6208 | ||
6209 | #define _IBX_AUD_CONFIG_A 0xe2000 | |
6210 | #define _IBX_AUD_CONFIG_B 0xe2100 | |
6211 | #define IBX_AUD_CFG(pipe) _PIPE(pipe, \ | |
6212 | _IBX_AUD_CONFIG_A, \ | |
6213 | _IBX_AUD_CONFIG_B) | |
6214 | #define _CPT_AUD_CONFIG_A 0xe5000 | |
6215 | #define _CPT_AUD_CONFIG_B 0xe5100 | |
6216 | #define CPT_AUD_CFG(pipe) _PIPE(pipe, \ | |
6217 | _CPT_AUD_CONFIG_A, \ | |
6218 | _CPT_AUD_CONFIG_B) | |
6219 | #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) | |
6220 | #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) | |
6221 | #define VLV_AUD_CFG(pipe) _PIPE(pipe, \ | |
6222 | _VLV_AUD_CONFIG_A, \ | |
6223 | _VLV_AUD_CONFIG_B) | |
6224 | ||
6225 | #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) | |
6226 | #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) | |
6227 | #define AUD_CONFIG_UPPER_N_SHIFT 20 | |
6228 | #define AUD_CONFIG_UPPER_N_MASK (0xff << 20) | |
6229 | #define AUD_CONFIG_LOWER_N_SHIFT 4 | |
6230 | #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4) | |
6231 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 | |
6232 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) | |
6233 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) | |
6234 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) | |
6235 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) | |
6236 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) | |
6237 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) | |
6238 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) | |
6239 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) | |
6240 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) | |
6241 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) | |
6242 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) | |
6243 | #define AUD_CONFIG_DISABLE_NCTS (1 << 3) | |
6244 | ||
6245 | /* HSW Audio */ | |
6246 | #define _HSW_AUD_CONFIG_A 0x65000 | |
6247 | #define _HSW_AUD_CONFIG_B 0x65100 | |
6248 | #define HSW_AUD_CFG(pipe) _PIPE(pipe, \ | |
6249 | _HSW_AUD_CONFIG_A, \ | |
6250 | _HSW_AUD_CONFIG_B) | |
6251 | ||
6252 | #define _HSW_AUD_MISC_CTRL_A 0x65010 | |
6253 | #define _HSW_AUD_MISC_CTRL_B 0x65110 | |
6254 | #define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \ | |
6255 | _HSW_AUD_MISC_CTRL_A, \ | |
6256 | _HSW_AUD_MISC_CTRL_B) | |
6257 | ||
6258 | #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 | |
6259 | #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 | |
6260 | #define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \ | |
6261 | _HSW_AUD_DIP_ELD_CTRL_ST_A, \ | |
6262 | _HSW_AUD_DIP_ELD_CTRL_ST_B) | |
6263 | ||
6264 | /* Audio Digital Converter */ | |
6265 | #define _HSW_AUD_DIG_CNVT_1 0x65080 | |
6266 | #define _HSW_AUD_DIG_CNVT_2 0x65180 | |
6267 | #define AUD_DIG_CNVT(pipe) _PIPE(pipe, \ | |
6268 | _HSW_AUD_DIG_CNVT_1, \ | |
6269 | _HSW_AUD_DIG_CNVT_2) | |
6270 | #define DIP_PORT_SEL_MASK 0x3 | |
6271 | ||
6272 | #define _HSW_AUD_EDID_DATA_A 0x65050 | |
6273 | #define _HSW_AUD_EDID_DATA_B 0x65150 | |
6274 | #define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \ | |
6275 | _HSW_AUD_EDID_DATA_A, \ | |
6276 | _HSW_AUD_EDID_DATA_B) | |
6277 | ||
6278 | #define HSW_AUD_PIPE_CONV_CFG 0x6507c | |
6279 | #define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 | |
6280 | #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) | |
6281 | #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) | |
6282 | #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) | |
6283 | #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) | |
6284 | ||
6285 | /* HSW Power Wells */ | |
6286 | #define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */ | |
6287 | #define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */ | |
6288 | #define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */ | |
6289 | #define HSW_PWR_WELL_DEBUG 0x4540C /* CTL4 */ | |
6290 | #define HSW_PWR_WELL_ENABLE_REQUEST (1<<31) | |
6291 | #define HSW_PWR_WELL_STATE_ENABLED (1<<30) | |
6292 | #define HSW_PWR_WELL_CTL5 0x45410 | |
6293 | #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) | |
6294 | #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) | |
6295 | #define HSW_PWR_WELL_FORCE_ON (1<<19) | |
6296 | #define HSW_PWR_WELL_CTL6 0x45414 | |
6297 | ||
6298 | /* Per-pipe DDI Function Control */ | |
6299 | #define TRANS_DDI_FUNC_CTL_A 0x60400 | |
6300 | #define TRANS_DDI_FUNC_CTL_B 0x61400 | |
6301 | #define TRANS_DDI_FUNC_CTL_C 0x62400 | |
6302 | #define TRANS_DDI_FUNC_CTL_EDP 0x6F400 | |
6303 | #define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, TRANS_DDI_FUNC_CTL_A) | |
6304 | ||
6305 | #define TRANS_DDI_FUNC_ENABLE (1<<31) | |
6306 | /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ | |
6307 | #define TRANS_DDI_PORT_MASK (7<<28) | |
6308 | #define TRANS_DDI_PORT_SHIFT 28 | |
6309 | #define TRANS_DDI_SELECT_PORT(x) ((x)<<28) | |
6310 | #define TRANS_DDI_PORT_NONE (0<<28) | |
6311 | #define TRANS_DDI_MODE_SELECT_MASK (7<<24) | |
6312 | #define TRANS_DDI_MODE_SELECT_HDMI (0<<24) | |
6313 | #define TRANS_DDI_MODE_SELECT_DVI (1<<24) | |
6314 | #define TRANS_DDI_MODE_SELECT_DP_SST (2<<24) | |
6315 | #define TRANS_DDI_MODE_SELECT_DP_MST (3<<24) | |
6316 | #define TRANS_DDI_MODE_SELECT_FDI (4<<24) | |
6317 | #define TRANS_DDI_BPC_MASK (7<<20) | |
6318 | #define TRANS_DDI_BPC_8 (0<<20) | |
6319 | #define TRANS_DDI_BPC_10 (1<<20) | |
6320 | #define TRANS_DDI_BPC_6 (2<<20) | |
6321 | #define TRANS_DDI_BPC_12 (3<<20) | |
6322 | #define TRANS_DDI_PVSYNC (1<<17) | |
6323 | #define TRANS_DDI_PHSYNC (1<<16) | |
6324 | #define TRANS_DDI_EDP_INPUT_MASK (7<<12) | |
6325 | #define TRANS_DDI_EDP_INPUT_A_ON (0<<12) | |
6326 | #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12) | |
6327 | #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) | |
6328 | #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) | |
6329 | #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8) | |
6330 | #define TRANS_DDI_BFI_ENABLE (1<<4) | |
6331 | ||
6332 | /* DisplayPort Transport Control */ | |
6333 | #define DP_TP_CTL_A 0x64040 | |
6334 | #define DP_TP_CTL_B 0x64140 | |
6335 | #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B) | |
6336 | #define DP_TP_CTL_ENABLE (1<<31) | |
6337 | #define DP_TP_CTL_MODE_SST (0<<27) | |
6338 | #define DP_TP_CTL_MODE_MST (1<<27) | |
6339 | #define DP_TP_CTL_FORCE_ACT (1<<25) | |
6340 | #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) | |
6341 | #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) | |
6342 | #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) | |
6343 | #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) | |
6344 | #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8) | |
6345 | #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8) | |
6346 | #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8) | |
6347 | #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) | |
6348 | #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7) | |
6349 | ||
6350 | /* DisplayPort Transport Status */ | |
6351 | #define DP_TP_STATUS_A 0x64044 | |
6352 | #define DP_TP_STATUS_B 0x64144 | |
6353 | #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B) | |
6354 | #define DP_TP_STATUS_IDLE_DONE (1<<25) | |
6355 | #define DP_TP_STATUS_ACT_SENT (1<<24) | |
6356 | #define DP_TP_STATUS_MODE_STATUS_MST (1<<23) | |
6357 | #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) | |
6358 | #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) | |
6359 | #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) | |
6360 | #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) | |
6361 | ||
6362 | /* DDI Buffer Control */ | |
6363 | #define DDI_BUF_CTL_A 0x64000 | |
6364 | #define DDI_BUF_CTL_B 0x64100 | |
6365 | #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B) | |
6366 | #define DDI_BUF_CTL_ENABLE (1<<31) | |
6367 | #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) | |
6368 | #define DDI_BUF_EMP_MASK (0xf<<24) | |
6369 | #define DDI_BUF_PORT_REVERSAL (1<<16) | |
6370 | #define DDI_BUF_IS_IDLE (1<<7) | |
6371 | #define DDI_A_4_LANES (1<<4) | |
6372 | #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) | |
6373 | #define DDI_INIT_DISPLAY_DETECTED (1<<0) | |
6374 | ||
6375 | /* DDI Buffer Translations */ | |
6376 | #define DDI_BUF_TRANS_A 0x64E00 | |
6377 | #define DDI_BUF_TRANS_B 0x64E60 | |
6378 | #define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) | |
6379 | ||
6380 | /* Sideband Interface (SBI) is programmed indirectly, via | |
6381 | * SBI_ADDR, which contains the register offset; and SBI_DATA, | |
6382 | * which contains the payload */ | |
6383 | #define SBI_ADDR 0xC6000 | |
6384 | #define SBI_DATA 0xC6004 | |
6385 | #define SBI_CTL_STAT 0xC6008 | |
6386 | #define SBI_CTL_DEST_ICLK (0x0<<16) | |
6387 | #define SBI_CTL_DEST_MPHY (0x1<<16) | |
6388 | #define SBI_CTL_OP_IORD (0x2<<8) | |
6389 | #define SBI_CTL_OP_IOWR (0x3<<8) | |
6390 | #define SBI_CTL_OP_CRRD (0x6<<8) | |
6391 | #define SBI_CTL_OP_CRWR (0x7<<8) | |
6392 | #define SBI_RESPONSE_FAIL (0x1<<1) | |
6393 | #define SBI_RESPONSE_SUCCESS (0x0<<1) | |
6394 | #define SBI_BUSY (0x1<<0) | |
6395 | #define SBI_READY (0x0<<0) | |
6396 | ||
6397 | /* SBI offsets */ | |
6398 | #define SBI_SSCDIVINTPHASE6 0x0600 | |
6399 | #define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1) | |
6400 | #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1) | |
6401 | #define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8) | |
6402 | #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8) | |
6403 | #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15) | |
6404 | #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0) | |
6405 | #define SBI_SSCCTL 0x020c | |
6406 | #define SBI_SSCCTL6 0x060C | |
6407 | #define SBI_SSCCTL_PATHALT (1<<3) | |
6408 | #define SBI_SSCCTL_DISABLE (1<<0) | |
6409 | #define SBI_SSCAUXDIV6 0x0610 | |
6410 | #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4) | |
6411 | #define SBI_DBUFF0 0x2a00 | |
6412 | #define SBI_GEN0 0x1f00 | |
6413 | #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0) | |
6414 | ||
6415 | /* LPT PIXCLK_GATE */ | |
6416 | #define PIXCLK_GATE 0xC6020 | |
6417 | #define PIXCLK_GATE_UNGATE (1<<0) | |
6418 | #define PIXCLK_GATE_GATE (0<<0) | |
6419 | ||
6420 | /* SPLL */ | |
6421 | #define SPLL_CTL 0x46020 | |
6422 | #define SPLL_PLL_ENABLE (1<<31) | |
6423 | #define SPLL_PLL_SSC (1<<28) | |
6424 | #define SPLL_PLL_NON_SSC (2<<28) | |
6425 | #define SPLL_PLL_LCPLL (3<<28) | |
6426 | #define SPLL_PLL_REF_MASK (3<<28) | |
6427 | #define SPLL_PLL_FREQ_810MHz (0<<26) | |
6428 | #define SPLL_PLL_FREQ_1350MHz (1<<26) | |
6429 | #define SPLL_PLL_FREQ_2700MHz (2<<26) | |
6430 | #define SPLL_PLL_FREQ_MASK (3<<26) | |
6431 | ||
6432 | /* WRPLL */ | |
6433 | #define WRPLL_CTL1 0x46040 | |
6434 | #define WRPLL_CTL2 0x46060 | |
6435 | #define WRPLL_CTL(pll) (pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2) | |
6436 | #define WRPLL_PLL_ENABLE (1<<31) | |
6437 | #define WRPLL_PLL_SSC (1<<28) | |
6438 | #define WRPLL_PLL_NON_SSC (2<<28) | |
6439 | #define WRPLL_PLL_LCPLL (3<<28) | |
6440 | #define WRPLL_PLL_REF_MASK (3<<28) | |
6441 | /* WRPLL divider programming */ | |
6442 | #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0) | |
6443 | #define WRPLL_DIVIDER_REF_MASK (0xff) | |
6444 | #define WRPLL_DIVIDER_POST(x) ((x)<<8) | |
6445 | #define WRPLL_DIVIDER_POST_MASK (0x3f<<8) | |
6446 | #define WRPLL_DIVIDER_POST_SHIFT 8 | |
6447 | #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16) | |
6448 | #define WRPLL_DIVIDER_FB_SHIFT 16 | |
6449 | #define WRPLL_DIVIDER_FB_MASK (0xff<<16) | |
6450 | ||
6451 | /* Port clock selection */ | |
6452 | #define PORT_CLK_SEL_A 0x46100 | |
6453 | #define PORT_CLK_SEL_B 0x46104 | |
6454 | #define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B) | |
6455 | #define PORT_CLK_SEL_LCPLL_2700 (0<<29) | |
6456 | #define PORT_CLK_SEL_LCPLL_1350 (1<<29) | |
6457 | #define PORT_CLK_SEL_LCPLL_810 (2<<29) | |
6458 | #define PORT_CLK_SEL_SPLL (3<<29) | |
6459 | #define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29) | |
6460 | #define PORT_CLK_SEL_WRPLL1 (4<<29) | |
6461 | #define PORT_CLK_SEL_WRPLL2 (5<<29) | |
6462 | #define PORT_CLK_SEL_NONE (7<<29) | |
6463 | #define PORT_CLK_SEL_MASK (7<<29) | |
6464 | ||
6465 | /* Transcoder clock selection */ | |
6466 | #define TRANS_CLK_SEL_A 0x46140 | |
6467 | #define TRANS_CLK_SEL_B 0x46144 | |
6468 | #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B) | |
6469 | /* For each transcoder, we need to select the corresponding port clock */ | |
6470 | #define TRANS_CLK_SEL_DISABLED (0x0<<29) | |
6471 | #define TRANS_CLK_SEL_PORT(x) ((x+1)<<29) | |
6472 | ||
6473 | #define TRANSA_MSA_MISC 0x60410 | |
6474 | #define TRANSB_MSA_MISC 0x61410 | |
6475 | #define TRANSC_MSA_MISC 0x62410 | |
6476 | #define TRANS_EDP_MSA_MISC 0x6f410 | |
6477 | #define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, TRANSA_MSA_MISC) | |
6478 | ||
6479 | #define TRANS_MSA_SYNC_CLK (1<<0) | |
6480 | #define TRANS_MSA_6_BPC (0<<5) | |
6481 | #define TRANS_MSA_8_BPC (1<<5) | |
6482 | #define TRANS_MSA_10_BPC (2<<5) | |
6483 | #define TRANS_MSA_12_BPC (3<<5) | |
6484 | #define TRANS_MSA_16_BPC (4<<5) | |
6485 | ||
6486 | /* LCPLL Control */ | |
6487 | #define LCPLL_CTL 0x130040 | |
6488 | #define LCPLL_PLL_DISABLE (1<<31) | |
6489 | #define LCPLL_PLL_LOCK (1<<30) | |
6490 | #define LCPLL_CLK_FREQ_MASK (3<<26) | |
6491 | #define LCPLL_CLK_FREQ_450 (0<<26) | |
6492 | #define LCPLL_CLK_FREQ_54O_BDW (1<<26) | |
6493 | #define LCPLL_CLK_FREQ_337_5_BDW (2<<26) | |
6494 | #define LCPLL_CLK_FREQ_675_BDW (3<<26) | |
6495 | #define LCPLL_CD_CLOCK_DISABLE (1<<25) | |
6496 | #define LCPLL_CD2X_CLOCK_DISABLE (1<<23) | |
6497 | #define LCPLL_POWER_DOWN_ALLOW (1<<22) | |
6498 | #define LCPLL_CD_SOURCE_FCLK (1<<21) | |
6499 | #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19) | |
6500 | ||
6501 | /* | |
6502 | * SKL Clocks | |
6503 | */ | |
6504 | ||
6505 | /* CDCLK_CTL */ | |
6506 | #define CDCLK_CTL 0x46000 | |
6507 | #define CDCLK_FREQ_SEL_MASK (3<<26) | |
6508 | #define CDCLK_FREQ_450_432 (0<<26) | |
6509 | #define CDCLK_FREQ_540 (1<<26) | |
6510 | #define CDCLK_FREQ_337_308 (2<<26) | |
6511 | #define CDCLK_FREQ_675_617 (3<<26) | |
6512 | #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) | |
6513 | ||
6514 | /* LCPLL_CTL */ | |
6515 | #define LCPLL1_CTL 0x46010 | |
6516 | #define LCPLL2_CTL 0x46014 | |
6517 | #define LCPLL_PLL_ENABLE (1<<31) | |
6518 | ||
6519 | /* DPLL control1 */ | |
6520 | #define DPLL_CTRL1 0x6C058 | |
6521 | #define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5)) | |
6522 | #define DPLL_CTRL1_SSC(id) (1<<((id)*6+4)) | |
6523 | #define DPLL_CRTL1_LINK_RATE_MASK(id) (7<<((id)*6+1)) | |
6524 | #define DPLL_CRTL1_LINK_RATE_SHIFT(id) ((id)*6+1) | |
6525 | #define DPLL_CRTL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1)) | |
6526 | #define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6)) | |
6527 | #define DPLL_CRTL1_LINK_RATE_2700 0 | |
6528 | #define DPLL_CRTL1_LINK_RATE_1350 1 | |
6529 | #define DPLL_CRTL1_LINK_RATE_810 2 | |
6530 | #define DPLL_CRTL1_LINK_RATE_1620 3 | |
6531 | #define DPLL_CRTL1_LINK_RATE_1080 4 | |
6532 | #define DPLL_CRTL1_LINK_RATE_2160 5 | |
6533 | ||
6534 | /* DPLL control2 */ | |
6535 | #define DPLL_CTRL2 0x6C05C | |
6536 | #define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<(port+15)) | |
6537 | #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1)) | |
6538 | #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1) | |
6539 | #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) (clk<<((port)*3+1)) | |
6540 | #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3)) | |
6541 | ||
6542 | /* DPLL Status */ | |
6543 | #define DPLL_STATUS 0x6C060 | |
6544 | #define DPLL_LOCK(id) (1<<((id)*8)) | |
6545 | ||
6546 | /* DPLL cfg */ | |
6547 | #define DPLL1_CFGCR1 0x6C040 | |
6548 | #define DPLL2_CFGCR1 0x6C048 | |
6549 | #define DPLL3_CFGCR1 0x6C050 | |
6550 | #define DPLL_CFGCR1_FREQ_ENABLE (1<<31) | |
6551 | #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9) | |
6552 | #define DPLL_CFGCR1_DCO_FRACTION(x) (x<<9) | |
6553 | #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) | |
6554 | ||
6555 | #define DPLL1_CFGCR2 0x6C044 | |
6556 | #define DPLL2_CFGCR2 0x6C04C | |
6557 | #define DPLL3_CFGCR2 0x6C054 | |
6558 | #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8) | |
6559 | #define DPLL_CFGCR2_QDIV_RATIO(x) (x<<8) | |
6560 | #define DPLL_CFGCR2_QDIV_MODE(x) (x<<7) | |
6561 | #define DPLL_CFGCR2_KDIV_MASK (3<<5) | |
6562 | #define DPLL_CFGCR2_KDIV(x) (x<<5) | |
6563 | #define DPLL_CFGCR2_KDIV_5 (0<<5) | |
6564 | #define DPLL_CFGCR2_KDIV_2 (1<<5) | |
6565 | #define DPLL_CFGCR2_KDIV_3 (2<<5) | |
6566 | #define DPLL_CFGCR2_KDIV_1 (3<<5) | |
6567 | #define DPLL_CFGCR2_PDIV_MASK (7<<2) | |
6568 | #define DPLL_CFGCR2_PDIV(x) (x<<2) | |
6569 | #define DPLL_CFGCR2_PDIV_1 (0<<2) | |
6570 | #define DPLL_CFGCR2_PDIV_2 (1<<2) | |
6571 | #define DPLL_CFGCR2_PDIV_3 (2<<2) | |
6572 | #define DPLL_CFGCR2_PDIV_7 (4<<2) | |
6573 | #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) | |
6574 | ||
6575 | #define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8) | |
6576 | #define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8) | |
6577 | ||
6578 | /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, | |
6579 | * since on HSW we can't write to it using I915_WRITE. */ | |
6580 | #define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C) | |
6581 | #define D_COMP_BDW 0x138144 | |
6582 | #define D_COMP_RCOMP_IN_PROGRESS (1<<9) | |
6583 | #define D_COMP_COMP_FORCE (1<<8) | |
6584 | #define D_COMP_COMP_DISABLE (1<<0) | |
6585 | ||
6586 | /* Pipe WM_LINETIME - watermark line time */ | |
6587 | #define PIPE_WM_LINETIME_A 0x45270 | |
6588 | #define PIPE_WM_LINETIME_B 0x45274 | |
6589 | #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \ | |
6590 | PIPE_WM_LINETIME_B) | |
6591 | #define PIPE_WM_LINETIME_MASK (0x1ff) | |
6592 | #define PIPE_WM_LINETIME_TIME(x) ((x)) | |
6593 | #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16) | |
6594 | #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16) | |
6595 | ||
6596 | /* SFUSE_STRAP */ | |
6597 | #define SFUSE_STRAP 0xc2014 | |
6598 | #define SFUSE_STRAP_FUSE_LOCK (1<<13) | |
6599 | #define SFUSE_STRAP_DISPLAY_DISABLED (1<<7) | |
6600 | #define SFUSE_STRAP_DDIB_DETECTED (1<<2) | |
6601 | #define SFUSE_STRAP_DDIC_DETECTED (1<<1) | |
6602 | #define SFUSE_STRAP_DDID_DETECTED (1<<0) | |
6603 | ||
6604 | #define WM_MISC 0x45260 | |
6605 | #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) | |
6606 | ||
6607 | #define WM_DBG 0x45280 | |
6608 | #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0) | |
6609 | #define WM_DBG_DISALLOW_MAXFIFO (1<<1) | |
6610 | #define WM_DBG_DISALLOW_SPRITE (1<<2) | |
6611 | ||
6612 | /* pipe CSC */ | |
6613 | #define _PIPE_A_CSC_COEFF_RY_GY 0x49010 | |
6614 | #define _PIPE_A_CSC_COEFF_BY 0x49014 | |
6615 | #define _PIPE_A_CSC_COEFF_RU_GU 0x49018 | |
6616 | #define _PIPE_A_CSC_COEFF_BU 0x4901c | |
6617 | #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 | |
6618 | #define _PIPE_A_CSC_COEFF_BV 0x49024 | |
6619 | #define _PIPE_A_CSC_MODE 0x49028 | |
6620 | #define CSC_BLACK_SCREEN_OFFSET (1 << 2) | |
6621 | #define CSC_POSITION_BEFORE_GAMMA (1 << 1) | |
6622 | #define CSC_MODE_YUV_TO_RGB (1 << 0) | |
6623 | #define _PIPE_A_CSC_PREOFF_HI 0x49030 | |
6624 | #define _PIPE_A_CSC_PREOFF_ME 0x49034 | |
6625 | #define _PIPE_A_CSC_PREOFF_LO 0x49038 | |
6626 | #define _PIPE_A_CSC_POSTOFF_HI 0x49040 | |
6627 | #define _PIPE_A_CSC_POSTOFF_ME 0x49044 | |
6628 | #define _PIPE_A_CSC_POSTOFF_LO 0x49048 | |
6629 | ||
6630 | #define _PIPE_B_CSC_COEFF_RY_GY 0x49110 | |
6631 | #define _PIPE_B_CSC_COEFF_BY 0x49114 | |
6632 | #define _PIPE_B_CSC_COEFF_RU_GU 0x49118 | |
6633 | #define _PIPE_B_CSC_COEFF_BU 0x4911c | |
6634 | #define _PIPE_B_CSC_COEFF_RV_GV 0x49120 | |
6635 | #define _PIPE_B_CSC_COEFF_BV 0x49124 | |
6636 | #define _PIPE_B_CSC_MODE 0x49128 | |
6637 | #define _PIPE_B_CSC_PREOFF_HI 0x49130 | |
6638 | #define _PIPE_B_CSC_PREOFF_ME 0x49134 | |
6639 | #define _PIPE_B_CSC_PREOFF_LO 0x49138 | |
6640 | #define _PIPE_B_CSC_POSTOFF_HI 0x49140 | |
6641 | #define _PIPE_B_CSC_POSTOFF_ME 0x49144 | |
6642 | #define _PIPE_B_CSC_POSTOFF_LO 0x49148 | |
6643 | ||
6644 | #define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) | |
6645 | #define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) | |
6646 | #define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) | |
6647 | #define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) | |
6648 | #define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) | |
6649 | #define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) | |
6650 | #define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) | |
6651 | #define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) | |
6652 | #define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) | |
6653 | #define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) | |
6654 | #define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) | |
6655 | #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) | |
6656 | #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) | |
6657 | ||
6658 | /* MIPI DSI registers */ | |
6659 | ||
6660 | #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */ | |
6661 | ||
6662 | #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) | |
6663 | #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) | |
6664 | #define MIPI_PORT_CTRL(port) _MIPI_PORT(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) | |
6665 | #define DPI_ENABLE (1 << 31) /* A + C */ | |
6666 | #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 | |
6667 | #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) | |
6668 | #define DUAL_LINK_MODE_MASK (1 << 26) | |
6669 | #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) | |
6670 | #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) | |
6671 | #define DITHERING_ENABLE (1 << 25) /* A + C */ | |
6672 | #define FLOPPED_HSTX (1 << 23) | |
6673 | #define DE_INVERT (1 << 19) /* XXX */ | |
6674 | #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 | |
6675 | #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) | |
6676 | #define AFE_LATCHOUT (1 << 17) | |
6677 | #define LP_OUTPUT_HOLD (1 << 16) | |
6678 | #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 | |
6679 | #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) | |
6680 | #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11 | |
6681 | #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) | |
6682 | #define CSB_SHIFT 9 | |
6683 | #define CSB_MASK (3 << 9) | |
6684 | #define CSB_20MHZ (0 << 9) | |
6685 | #define CSB_10MHZ (1 << 9) | |
6686 | #define CSB_40MHZ (2 << 9) | |
6687 | #define BANDGAP_MASK (1 << 8) | |
6688 | #define BANDGAP_PNW_CIRCUIT (0 << 8) | |
6689 | #define BANDGAP_LNC_CIRCUIT (1 << 8) | |
6690 | #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 | |
6691 | #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) | |
6692 | #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */ | |
6693 | #define TEARING_EFFECT_SHIFT 2 /* A + C */ | |
6694 | #define TEARING_EFFECT_MASK (3 << 2) | |
6695 | #define TEARING_EFFECT_OFF (0 << 2) | |
6696 | #define TEARING_EFFECT_DSI (1 << 2) | |
6697 | #define TEARING_EFFECT_GPIO (2 << 2) | |
6698 | #define LANE_CONFIGURATION_SHIFT 0 | |
6699 | #define LANE_CONFIGURATION_MASK (3 << 0) | |
6700 | #define LANE_CONFIGURATION_4LANE (0 << 0) | |
6701 | #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) | |
6702 | #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) | |
6703 | ||
6704 | #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) | |
6705 | #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) | |
6706 | #define MIPI_TEARING_CTRL(port) _MIPI_PORT(port, \ | |
6707 | _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) | |
6708 | #define TEARING_EFFECT_DELAY_SHIFT 0 | |
6709 | #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) | |
6710 | ||
6711 | /* XXX: all bits reserved */ | |
6712 | #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) | |
6713 | ||
6714 | /* MIPI DSI Controller and D-PHY registers */ | |
6715 | ||
6716 | #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) | |
6717 | #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) | |
6718 | #define MIPI_DEVICE_READY(port) _MIPI_PORT(port, _MIPIA_DEVICE_READY, \ | |
6719 | _MIPIC_DEVICE_READY) | |
6720 | #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ | |
6721 | #define ULPS_STATE_MASK (3 << 1) | |
6722 | #define ULPS_STATE_ENTER (2 << 1) | |
6723 | #define ULPS_STATE_EXIT (1 << 1) | |
6724 | #define ULPS_STATE_NORMAL_OPERATION (0 << 1) | |
6725 | #define DEVICE_READY (1 << 0) | |
6726 | ||
6727 | #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) | |
6728 | #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) | |
6729 | #define MIPI_INTR_STAT(port) _MIPI_PORT(port, _MIPIA_INTR_STAT, \ | |
6730 | _MIPIC_INTR_STAT) | |
6731 | #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) | |
6732 | #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) | |
6733 | #define MIPI_INTR_EN(port) _MIPI_PORT(port, _MIPIA_INTR_EN, \ | |
6734 | _MIPIC_INTR_EN) | |
6735 | #define TEARING_EFFECT (1 << 31) | |
6736 | #define SPL_PKT_SENT_INTERRUPT (1 << 30) | |
6737 | #define GEN_READ_DATA_AVAIL (1 << 29) | |
6738 | #define LP_GENERIC_WR_FIFO_FULL (1 << 28) | |
6739 | #define HS_GENERIC_WR_FIFO_FULL (1 << 27) | |
6740 | #define RX_PROT_VIOLATION (1 << 26) | |
6741 | #define RX_INVALID_TX_LENGTH (1 << 25) | |
6742 | #define ACK_WITH_NO_ERROR (1 << 24) | |
6743 | #define TURN_AROUND_ACK_TIMEOUT (1 << 23) | |
6744 | #define LP_RX_TIMEOUT (1 << 22) | |
6745 | #define HS_TX_TIMEOUT (1 << 21) | |
6746 | #define DPI_FIFO_UNDERRUN (1 << 20) | |
6747 | #define LOW_CONTENTION (1 << 19) | |
6748 | #define HIGH_CONTENTION (1 << 18) | |
6749 | #define TXDSI_VC_ID_INVALID (1 << 17) | |
6750 | #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16) | |
6751 | #define TXCHECKSUM_ERROR (1 << 15) | |
6752 | #define TXECC_MULTIBIT_ERROR (1 << 14) | |
6753 | #define TXECC_SINGLE_BIT_ERROR (1 << 13) | |
6754 | #define TXFALSE_CONTROL_ERROR (1 << 12) | |
6755 | #define RXDSI_VC_ID_INVALID (1 << 11) | |
6756 | #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10) | |
6757 | #define RXCHECKSUM_ERROR (1 << 9) | |
6758 | #define RXECC_MULTIBIT_ERROR (1 << 8) | |
6759 | #define RXECC_SINGLE_BIT_ERROR (1 << 7) | |
6760 | #define RXFALSE_CONTROL_ERROR (1 << 6) | |
6761 | #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5) | |
6762 | #define RX_LP_TX_SYNC_ERROR (1 << 4) | |
6763 | #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3) | |
6764 | #define RXEOT_SYNC_ERROR (1 << 2) | |
6765 | #define RXSOT_SYNC_ERROR (1 << 1) | |
6766 | #define RXSOT_ERROR (1 << 0) | |
6767 | ||
6768 | #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) | |
6769 | #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) | |
6770 | #define MIPI_DSI_FUNC_PRG(port) _MIPI_PORT(port, _MIPIA_DSI_FUNC_PRG, \ | |
6771 | _MIPIC_DSI_FUNC_PRG) | |
6772 | #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) | |
6773 | #define CMD_MODE_NOT_SUPPORTED (0 << 13) | |
6774 | #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) | |
6775 | #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) | |
6776 | #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13) | |
6777 | #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13) | |
6778 | #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13) | |
6779 | #define VID_MODE_FORMAT_MASK (0xf << 7) | |
6780 | #define VID_MODE_NOT_SUPPORTED (0 << 7) | |
6781 | #define VID_MODE_FORMAT_RGB565 (1 << 7) | |
6782 | #define VID_MODE_FORMAT_RGB666 (2 << 7) | |
6783 | #define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7) | |
6784 | #define VID_MODE_FORMAT_RGB888 (4 << 7) | |
6785 | #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5 | |
6786 | #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5) | |
6787 | #define VID_MODE_CHANNEL_NUMBER_SHIFT 3 | |
6788 | #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) | |
6789 | #define DATA_LANES_PRG_REG_SHIFT 0 | |
6790 | #define DATA_LANES_PRG_REG_MASK (7 << 0) | |
6791 | ||
6792 | #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) | |
6793 | #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) | |
6794 | #define MIPI_HS_TX_TIMEOUT(port) _MIPI_PORT(port, _MIPIA_HS_TX_TIMEOUT, \ | |
6795 | _MIPIC_HS_TX_TIMEOUT) | |
6796 | #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff | |
6797 | ||
6798 | #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) | |
6799 | #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) | |
6800 | #define MIPI_LP_RX_TIMEOUT(port) _MIPI_PORT(port, _MIPIA_LP_RX_TIMEOUT, \ | |
6801 | _MIPIC_LP_RX_TIMEOUT) | |
6802 | #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff | |
6803 | ||
6804 | #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) | |
6805 | #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) | |
6806 | #define MIPI_TURN_AROUND_TIMEOUT(port) _MIPI_PORT(port, \ | |
6807 | _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) | |
6808 | #define TURN_AROUND_TIMEOUT_MASK 0x3f | |
6809 | ||
6810 | #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) | |
6811 | #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) | |
6812 | #define MIPI_DEVICE_RESET_TIMER(port) _MIPI_PORT(port, \ | |
6813 | _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) | |
6814 | #define DEVICE_RESET_TIMER_MASK 0xffff | |
6815 | ||
6816 | #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) | |
6817 | #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) | |
6818 | #define MIPI_DPI_RESOLUTION(port) _MIPI_PORT(port, _MIPIA_DPI_RESOLUTION, \ | |
6819 | _MIPIC_DPI_RESOLUTION) | |
6820 | #define VERTICAL_ADDRESS_SHIFT 16 | |
6821 | #define VERTICAL_ADDRESS_MASK (0xffff << 16) | |
6822 | #define HORIZONTAL_ADDRESS_SHIFT 0 | |
6823 | #define HORIZONTAL_ADDRESS_MASK 0xffff | |
6824 | ||
6825 | #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) | |
6826 | #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) | |
6827 | #define MIPI_DBI_FIFO_THROTTLE(port) _MIPI_PORT(port, \ | |
6828 | _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) | |
6829 | #define DBI_FIFO_EMPTY_HALF (0 << 0) | |
6830 | #define DBI_FIFO_EMPTY_QUARTER (1 << 0) | |
6831 | #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) | |
6832 | ||
6833 | /* regs below are bits 15:0 */ | |
6834 | #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) | |
6835 | #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) | |
6836 | #define MIPI_HSYNC_PADDING_COUNT(port) _MIPI_PORT(port, \ | |
6837 | _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) | |
6838 | ||
6839 | #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) | |
6840 | #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) | |
6841 | #define MIPI_HBP_COUNT(port) _MIPI_PORT(port, _MIPIA_HBP_COUNT, \ | |
6842 | _MIPIC_HBP_COUNT) | |
6843 | ||
6844 | #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) | |
6845 | #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) | |
6846 | #define MIPI_HFP_COUNT(port) _MIPI_PORT(port, _MIPIA_HFP_COUNT, \ | |
6847 | _MIPIC_HFP_COUNT) | |
6848 | ||
6849 | #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) | |
6850 | #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) | |
6851 | #define MIPI_HACTIVE_AREA_COUNT(port) _MIPI_PORT(port, \ | |
6852 | _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) | |
6853 | ||
6854 | #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) | |
6855 | #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) | |
6856 | #define MIPI_VSYNC_PADDING_COUNT(port) _MIPI_PORT(port, \ | |
6857 | _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) | |
6858 | ||
6859 | #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) | |
6860 | #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) | |
6861 | #define MIPI_VBP_COUNT(port) _MIPI_PORT(port, _MIPIA_VBP_COUNT, \ | |
6862 | _MIPIC_VBP_COUNT) | |
6863 | ||
6864 | #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) | |
6865 | #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) | |
6866 | #define MIPI_VFP_COUNT(port) _MIPI_PORT(port, _MIPIA_VFP_COUNT, \ | |
6867 | _MIPIC_VFP_COUNT) | |
6868 | ||
6869 | #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) | |
6870 | #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) | |
6871 | #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MIPI_PORT(port, \ | |
6872 | _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) | |
6873 | ||
6874 | /* regs above are bits 15:0 */ | |
6875 | ||
6876 | #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) | |
6877 | #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) | |
6878 | #define MIPI_DPI_CONTROL(port) _MIPI_PORT(port, _MIPIA_DPI_CONTROL, \ | |
6879 | _MIPIC_DPI_CONTROL) | |
6880 | #define DPI_LP_MODE (1 << 6) | |
6881 | #define BACKLIGHT_OFF (1 << 5) | |
6882 | #define BACKLIGHT_ON (1 << 4) | |
6883 | #define COLOR_MODE_OFF (1 << 3) | |
6884 | #define COLOR_MODE_ON (1 << 2) | |
6885 | #define TURN_ON (1 << 1) | |
6886 | #define SHUTDOWN (1 << 0) | |
6887 | ||
6888 | #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) | |
6889 | #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) | |
6890 | #define MIPI_DPI_DATA(port) _MIPI_PORT(port, _MIPIA_DPI_DATA, \ | |
6891 | _MIPIC_DPI_DATA) | |
6892 | #define COMMAND_BYTE_SHIFT 0 | |
6893 | #define COMMAND_BYTE_MASK (0x3f << 0) | |
6894 | ||
6895 | #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) | |
6896 | #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) | |
6897 | #define MIPI_INIT_COUNT(port) _MIPI_PORT(port, _MIPIA_INIT_COUNT, \ | |
6898 | _MIPIC_INIT_COUNT) | |
6899 | #define MASTER_INIT_TIMER_SHIFT 0 | |
6900 | #define MASTER_INIT_TIMER_MASK (0xffff << 0) | |
6901 | ||
6902 | #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) | |
6903 | #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) | |
6904 | #define MIPI_MAX_RETURN_PKT_SIZE(port) _MIPI_PORT(port, \ | |
6905 | _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) | |
6906 | #define MAX_RETURN_PKT_SIZE_SHIFT 0 | |
6907 | #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) | |
6908 | ||
6909 | #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) | |
6910 | #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) | |
6911 | #define MIPI_VIDEO_MODE_FORMAT(port) _MIPI_PORT(port, \ | |
6912 | _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) | |
6913 | #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) | |
6914 | #define DISABLE_VIDEO_BTA (1 << 3) | |
6915 | #define IP_TG_CONFIG (1 << 2) | |
6916 | #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) | |
6917 | #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) | |
6918 | #define VIDEO_MODE_BURST (3 << 0) | |
6919 | ||
6920 | #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) | |
6921 | #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) | |
6922 | #define MIPI_EOT_DISABLE(port) _MIPI_PORT(port, _MIPIA_EOT_DISABLE, \ | |
6923 | _MIPIC_EOT_DISABLE) | |
6924 | #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) | |
6925 | #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) | |
6926 | #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) | |
6927 | #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) | |
6928 | #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) | |
6929 | #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) | |
6930 | #define CLOCKSTOP (1 << 1) | |
6931 | #define EOT_DISABLE (1 << 0) | |
6932 | ||
6933 | #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) | |
6934 | #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) | |
6935 | #define MIPI_LP_BYTECLK(port) _MIPI_PORT(port, _MIPIA_LP_BYTECLK, \ | |
6936 | _MIPIC_LP_BYTECLK) | |
6937 | #define LP_BYTECLK_SHIFT 0 | |
6938 | #define LP_BYTECLK_MASK (0xffff << 0) | |
6939 | ||
6940 | /* bits 31:0 */ | |
6941 | #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) | |
6942 | #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) | |
6943 | #define MIPI_LP_GEN_DATA(port) _MIPI_PORT(port, _MIPIA_LP_GEN_DATA, \ | |
6944 | _MIPIC_LP_GEN_DATA) | |
6945 | ||
6946 | /* bits 31:0 */ | |
6947 | #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) | |
6948 | #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) | |
6949 | #define MIPI_HS_GEN_DATA(port) _MIPI_PORT(port, _MIPIA_HS_GEN_DATA, \ | |
6950 | _MIPIC_HS_GEN_DATA) | |
6951 | ||
6952 | #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) | |
6953 | #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) | |
6954 | #define MIPI_LP_GEN_CTRL(port) _MIPI_PORT(port, _MIPIA_LP_GEN_CTRL, \ | |
6955 | _MIPIC_LP_GEN_CTRL) | |
6956 | #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070) | |
6957 | #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) | |
6958 | #define MIPI_HS_GEN_CTRL(port) _MIPI_PORT(port, _MIPIA_HS_GEN_CTRL, \ | |
6959 | _MIPIC_HS_GEN_CTRL) | |
6960 | #define LONG_PACKET_WORD_COUNT_SHIFT 8 | |
6961 | #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) | |
6962 | #define SHORT_PACKET_PARAM_SHIFT 8 | |
6963 | #define SHORT_PACKET_PARAM_MASK (0xffff << 8) | |
6964 | #define VIRTUAL_CHANNEL_SHIFT 6 | |
6965 | #define VIRTUAL_CHANNEL_MASK (3 << 6) | |
6966 | #define DATA_TYPE_SHIFT 0 | |
6967 | #define DATA_TYPE_MASK (3f << 0) | |
6968 | /* data type values, see include/video/mipi_display.h */ | |
6969 | ||
6970 | #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074) | |
6971 | #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) | |
6972 | #define MIPI_GEN_FIFO_STAT(port) _MIPI_PORT(port, _MIPIA_GEN_FIFO_STAT, \ | |
6973 | _MIPIC_GEN_FIFO_STAT) | |
6974 | #define DPI_FIFO_EMPTY (1 << 28) | |
6975 | #define DBI_FIFO_EMPTY (1 << 27) | |
6976 | #define LP_CTRL_FIFO_EMPTY (1 << 26) | |
6977 | #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) | |
6978 | #define LP_CTRL_FIFO_FULL (1 << 24) | |
6979 | #define HS_CTRL_FIFO_EMPTY (1 << 18) | |
6980 | #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) | |
6981 | #define HS_CTRL_FIFO_FULL (1 << 16) | |
6982 | #define LP_DATA_FIFO_EMPTY (1 << 10) | |
6983 | #define LP_DATA_FIFO_HALF_EMPTY (1 << 9) | |
6984 | #define LP_DATA_FIFO_FULL (1 << 8) | |
6985 | #define HS_DATA_FIFO_EMPTY (1 << 2) | |
6986 | #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) | |
6987 | #define HS_DATA_FIFO_FULL (1 << 0) | |
6988 | ||
6989 | #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) | |
6990 | #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) | |
6991 | #define MIPI_HS_LP_DBI_ENABLE(port) _MIPI_PORT(port, \ | |
6992 | _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) | |
6993 | #define DBI_HS_LP_MODE_MASK (1 << 0) | |
6994 | #define DBI_LP_MODE (1 << 0) | |
6995 | #define DBI_HS_MODE (0 << 0) | |
6996 | ||
6997 | #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) | |
6998 | #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) | |
6999 | #define MIPI_DPHY_PARAM(port) _MIPI_PORT(port, _MIPIA_DPHY_PARAM, \ | |
7000 | _MIPIC_DPHY_PARAM) | |
7001 | #define EXIT_ZERO_COUNT_SHIFT 24 | |
7002 | #define EXIT_ZERO_COUNT_MASK (0x3f << 24) | |
7003 | #define TRAIL_COUNT_SHIFT 16 | |
7004 | #define TRAIL_COUNT_MASK (0x1f << 16) | |
7005 | #define CLK_ZERO_COUNT_SHIFT 8 | |
7006 | #define CLK_ZERO_COUNT_MASK (0xff << 8) | |
7007 | #define PREPARE_COUNT_SHIFT 0 | |
7008 | #define PREPARE_COUNT_MASK (0x3f << 0) | |
7009 | ||
7010 | /* bits 31:0 */ | |
7011 | #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) | |
7012 | #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) | |
7013 | #define MIPI_DBI_BW_CTRL(port) _MIPI_PORT(port, _MIPIA_DBI_BW_CTRL, \ | |
7014 | _MIPIC_DBI_BW_CTRL) | |
7015 | ||
7016 | #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ | |
7017 | + 0xb088) | |
7018 | #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ | |
7019 | + 0xb888) | |
7020 | #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MIPI_PORT(port, \ | |
7021 | _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) | |
7022 | #define LP_HS_SSW_CNT_SHIFT 16 | |
7023 | #define LP_HS_SSW_CNT_MASK (0xffff << 16) | |
7024 | #define HS_LP_PWR_SW_CNT_SHIFT 0 | |
7025 | #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) | |
7026 | ||
7027 | #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) | |
7028 | #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) | |
7029 | #define MIPI_STOP_STATE_STALL(port) _MIPI_PORT(port, \ | |
7030 | _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) | |
7031 | #define STOP_STATE_STALL_COUNTER_SHIFT 0 | |
7032 | #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) | |
7033 | ||
7034 | #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) | |
7035 | #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) | |
7036 | #define MIPI_INTR_STAT_REG_1(port) _MIPI_PORT(port, \ | |
7037 | _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) | |
7038 | #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) | |
7039 | #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) | |
7040 | #define MIPI_INTR_EN_REG_1(port) _MIPI_PORT(port, _MIPIA_INTR_EN_REG_1, \ | |
7041 | _MIPIC_INTR_EN_REG_1) | |
7042 | #define RX_CONTENTION_DETECTED (1 << 0) | |
7043 | ||
7044 | /* XXX: only pipe A ?!? */ | |
7045 | #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100) | |
7046 | #define DBI_TYPEC_ENABLE (1 << 31) | |
7047 | #define DBI_TYPEC_WIP (1 << 30) | |
7048 | #define DBI_TYPEC_OPTION_SHIFT 28 | |
7049 | #define DBI_TYPEC_OPTION_MASK (3 << 28) | |
7050 | #define DBI_TYPEC_FREQ_SHIFT 24 | |
7051 | #define DBI_TYPEC_FREQ_MASK (0xf << 24) | |
7052 | #define DBI_TYPEC_OVERRIDE (1 << 8) | |
7053 | #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0 | |
7054 | #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0) | |
7055 | ||
7056 | ||
7057 | /* MIPI adapter registers */ | |
7058 | ||
7059 | #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) | |
7060 | #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904) | |
7061 | #define MIPI_CTRL(port) _MIPI_PORT(port, _MIPIA_CTRL, \ | |
7062 | _MIPIC_CTRL) | |
7063 | #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ | |
7064 | #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) | |
7065 | #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) | |
7066 | #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5) | |
7067 | #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5) | |
7068 | #define READ_REQUEST_PRIORITY_SHIFT 3 | |
7069 | #define READ_REQUEST_PRIORITY_MASK (3 << 3) | |
7070 | #define READ_REQUEST_PRIORITY_LOW (0 << 3) | |
7071 | #define READ_REQUEST_PRIORITY_HIGH (3 << 3) | |
7072 | #define RGB_FLIP_TO_BGR (1 << 2) | |
7073 | ||
7074 | #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) | |
7075 | #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) | |
7076 | #define MIPI_DATA_ADDRESS(port) _MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \ | |
7077 | _MIPIC_DATA_ADDRESS) | |
7078 | #define DATA_MEM_ADDRESS_SHIFT 5 | |
7079 | #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) | |
7080 | #define DATA_VALID (1 << 0) | |
7081 | ||
7082 | #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) | |
7083 | #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) | |
7084 | #define MIPI_DATA_LENGTH(port) _MIPI_PORT(port, _MIPIA_DATA_LENGTH, \ | |
7085 | _MIPIC_DATA_LENGTH) | |
7086 | #define DATA_LENGTH_SHIFT 0 | |
7087 | #define DATA_LENGTH_MASK (0xfffff << 0) | |
7088 | ||
7089 | #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) | |
7090 | #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) | |
7091 | #define MIPI_COMMAND_ADDRESS(port) _MIPI_PORT(port, \ | |
7092 | _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) | |
7093 | #define COMMAND_MEM_ADDRESS_SHIFT 5 | |
7094 | #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) | |
7095 | #define AUTO_PWG_ENABLE (1 << 2) | |
7096 | #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) | |
7097 | #define COMMAND_VALID (1 << 0) | |
7098 | ||
7099 | #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) | |
7100 | #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) | |
7101 | #define MIPI_COMMAND_LENGTH(port) _MIPI_PORT(port, _MIPIA_COMMAND_LENGTH, \ | |
7102 | _MIPIC_COMMAND_LENGTH) | |
7103 | #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ | |
7104 | #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) | |
7105 | ||
7106 | #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) | |
7107 | #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) | |
7108 | #define MIPI_READ_DATA_RETURN(port, n) \ | |
7109 | (_MIPI_PORT(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) \ | |
7110 | + 4 * (n)) /* n: 0...7 */ | |
7111 | ||
7112 | #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) | |
7113 | #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) | |
7114 | #define MIPI_READ_DATA_VALID(port) _MIPI_PORT(port, \ | |
7115 | _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) | |
7116 | #define READ_DATA_VALID(n) (1 << (n)) | |
7117 | ||
7118 | /* For UMS only (deprecated): */ | |
7119 | #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000) | |
7120 | #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800) | |
7121 | ||
7122 | #endif /* _I915_REG_H_ */ |