]>
Commit | Line | Data |
---|---|---|
1 | /* | |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
27 | #include <linux/dmi.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/input.h> | |
30 | #include <linux/i2c.h> | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/slab.h> | |
33 | #include <linux/vgaarb.h> | |
34 | #include <drm/drm_edid.h> | |
35 | #include <drm/drmP.h> | |
36 | #include "intel_drv.h" | |
37 | #include <drm/i915_drm.h> | |
38 | #include "i915_drv.h" | |
39 | #include "intel_dsi.h" | |
40 | #include "i915_trace.h" | |
41 | #include <drm/drm_atomic.h> | |
42 | #include <drm/drm_atomic_helper.h> | |
43 | #include <drm/drm_dp_helper.h> | |
44 | #include <drm/drm_crtc_helper.h> | |
45 | #include <drm/drm_plane_helper.h> | |
46 | #include <drm/drm_rect.h> | |
47 | #include <linux/dma_remapping.h> | |
48 | #include <linux/reservation.h> | |
49 | #include <linux/dma-buf.h> | |
50 | ||
51 | /* Primary plane formats for gen <= 3 */ | |
52 | static const uint32_t i8xx_primary_formats[] = { | |
53 | DRM_FORMAT_C8, | |
54 | DRM_FORMAT_RGB565, | |
55 | DRM_FORMAT_XRGB1555, | |
56 | DRM_FORMAT_XRGB8888, | |
57 | }; | |
58 | ||
59 | /* Primary plane formats for gen >= 4 */ | |
60 | static const uint32_t i965_primary_formats[] = { | |
61 | DRM_FORMAT_C8, | |
62 | DRM_FORMAT_RGB565, | |
63 | DRM_FORMAT_XRGB8888, | |
64 | DRM_FORMAT_XBGR8888, | |
65 | DRM_FORMAT_XRGB2101010, | |
66 | DRM_FORMAT_XBGR2101010, | |
67 | }; | |
68 | ||
69 | static const uint32_t skl_primary_formats[] = { | |
70 | DRM_FORMAT_C8, | |
71 | DRM_FORMAT_RGB565, | |
72 | DRM_FORMAT_XRGB8888, | |
73 | DRM_FORMAT_XBGR8888, | |
74 | DRM_FORMAT_ARGB8888, | |
75 | DRM_FORMAT_ABGR8888, | |
76 | DRM_FORMAT_XRGB2101010, | |
77 | DRM_FORMAT_XBGR2101010, | |
78 | DRM_FORMAT_YUYV, | |
79 | DRM_FORMAT_YVYU, | |
80 | DRM_FORMAT_UYVY, | |
81 | DRM_FORMAT_VYUY, | |
82 | }; | |
83 | ||
84 | /* Cursor formats */ | |
85 | static const uint32_t intel_cursor_formats[] = { | |
86 | DRM_FORMAT_ARGB8888, | |
87 | }; | |
88 | ||
89 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, | |
90 | struct intel_crtc_state *pipe_config); | |
91 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, | |
92 | struct intel_crtc_state *pipe_config); | |
93 | ||
94 | static int intel_framebuffer_init(struct drm_device *dev, | |
95 | struct intel_framebuffer *ifb, | |
96 | struct drm_mode_fb_cmd2 *mode_cmd, | |
97 | struct drm_i915_gem_object *obj); | |
98 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); | |
99 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
100 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); | |
101 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
102 | struct intel_link_m_n *m_n, | |
103 | struct intel_link_m_n *m2_n2); | |
104 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); | |
105 | static void haswell_set_pipeconf(struct drm_crtc *crtc); | |
106 | static void haswell_set_pipemisc(struct drm_crtc *crtc); | |
107 | static void vlv_prepare_pll(struct intel_crtc *crtc, | |
108 | const struct intel_crtc_state *pipe_config); | |
109 | static void chv_prepare_pll(struct intel_crtc *crtc, | |
110 | const struct intel_crtc_state *pipe_config); | |
111 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
112 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
113 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, | |
114 | struct intel_crtc_state *crtc_state); | |
115 | static void skylake_pfit_enable(struct intel_crtc *crtc); | |
116 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
117 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
118 | static void intel_modeset_setup_hw_state(struct drm_device *dev); | |
119 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); | |
120 | ||
121 | typedef struct { | |
122 | int min, max; | |
123 | } intel_range_t; | |
124 | ||
125 | typedef struct { | |
126 | int dot_limit; | |
127 | int p2_slow, p2_fast; | |
128 | } intel_p2_t; | |
129 | ||
130 | typedef struct intel_limit intel_limit_t; | |
131 | struct intel_limit { | |
132 | intel_range_t dot, vco, n, m, m1, m2, p, p1; | |
133 | intel_p2_t p2; | |
134 | }; | |
135 | ||
136 | /* returns HPLL frequency in kHz */ | |
137 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
138 | { | |
139 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
140 | ||
141 | /* Obtain SKU information */ | |
142 | mutex_lock(&dev_priv->sb_lock); | |
143 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
144 | CCK_FUSE_HPLL_FREQ_MASK; | |
145 | mutex_unlock(&dev_priv->sb_lock); | |
146 | ||
147 | return vco_freq[hpll_freq] * 1000; | |
148 | } | |
149 | ||
150 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, | |
151 | const char *name, u32 reg, int ref_freq) | |
152 | { | |
153 | u32 val; | |
154 | int divider; | |
155 | ||
156 | mutex_lock(&dev_priv->sb_lock); | |
157 | val = vlv_cck_read(dev_priv, reg); | |
158 | mutex_unlock(&dev_priv->sb_lock); | |
159 | ||
160 | divider = val & CCK_FREQUENCY_VALUES; | |
161 | ||
162 | WARN((val & CCK_FREQUENCY_STATUS) != | |
163 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
164 | "%s change in progress\n", name); | |
165 | ||
166 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); | |
167 | } | |
168 | ||
169 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
170 | const char *name, u32 reg) | |
171 | { | |
172 | if (dev_priv->hpll_freq == 0) | |
173 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
174 | ||
175 | return vlv_get_cck_clock(dev_priv, name, reg, | |
176 | dev_priv->hpll_freq); | |
177 | } | |
178 | ||
179 | static int | |
180 | intel_pch_rawclk(struct drm_i915_private *dev_priv) | |
181 | { | |
182 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; | |
183 | } | |
184 | ||
185 | static int | |
186 | intel_vlv_hrawclk(struct drm_i915_private *dev_priv) | |
187 | { | |
188 | /* RAWCLK_FREQ_VLV register updated from power well code */ | |
189 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", | |
190 | CCK_DISPLAY_REF_CLOCK_CONTROL); | |
191 | } | |
192 | ||
193 | static int | |
194 | intel_g4x_hrawclk(struct drm_i915_private *dev_priv) | |
195 | { | |
196 | uint32_t clkcfg; | |
197 | ||
198 | /* hrawclock is 1/4 the FSB frequency */ | |
199 | clkcfg = I915_READ(CLKCFG); | |
200 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
201 | case CLKCFG_FSB_400: | |
202 | return 100000; | |
203 | case CLKCFG_FSB_533: | |
204 | return 133333; | |
205 | case CLKCFG_FSB_667: | |
206 | return 166667; | |
207 | case CLKCFG_FSB_800: | |
208 | return 200000; | |
209 | case CLKCFG_FSB_1067: | |
210 | return 266667; | |
211 | case CLKCFG_FSB_1333: | |
212 | return 333333; | |
213 | /* these two are just a guess; one of them might be right */ | |
214 | case CLKCFG_FSB_1600: | |
215 | case CLKCFG_FSB_1600_ALT: | |
216 | return 400000; | |
217 | default: | |
218 | return 133333; | |
219 | } | |
220 | } | |
221 | ||
222 | void intel_update_rawclk(struct drm_i915_private *dev_priv) | |
223 | { | |
224 | if (HAS_PCH_SPLIT(dev_priv)) | |
225 | dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv); | |
226 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
227 | dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv); | |
228 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) | |
229 | dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv); | |
230 | else | |
231 | return; /* no rawclk on other platforms, or no need to know it */ | |
232 | ||
233 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); | |
234 | } | |
235 | ||
236 | static void intel_update_czclk(struct drm_i915_private *dev_priv) | |
237 | { | |
238 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) | |
239 | return; | |
240 | ||
241 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
242 | CCK_CZ_CLOCK_CONTROL); | |
243 | ||
244 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
245 | } | |
246 | ||
247 | static inline u32 /* units of 100MHz */ | |
248 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, | |
249 | const struct intel_crtc_state *pipe_config) | |
250 | { | |
251 | if (HAS_DDI(dev_priv)) | |
252 | return pipe_config->port_clock; /* SPLL */ | |
253 | else if (IS_GEN5(dev_priv)) | |
254 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
255 | else | |
256 | return 270000; | |
257 | } | |
258 | ||
259 | static const intel_limit_t intel_limits_i8xx_dac = { | |
260 | .dot = { .min = 25000, .max = 350000 }, | |
261 | .vco = { .min = 908000, .max = 1512000 }, | |
262 | .n = { .min = 2, .max = 16 }, | |
263 | .m = { .min = 96, .max = 140 }, | |
264 | .m1 = { .min = 18, .max = 26 }, | |
265 | .m2 = { .min = 6, .max = 16 }, | |
266 | .p = { .min = 4, .max = 128 }, | |
267 | .p1 = { .min = 2, .max = 33 }, | |
268 | .p2 = { .dot_limit = 165000, | |
269 | .p2_slow = 4, .p2_fast = 2 }, | |
270 | }; | |
271 | ||
272 | static const intel_limit_t intel_limits_i8xx_dvo = { | |
273 | .dot = { .min = 25000, .max = 350000 }, | |
274 | .vco = { .min = 908000, .max = 1512000 }, | |
275 | .n = { .min = 2, .max = 16 }, | |
276 | .m = { .min = 96, .max = 140 }, | |
277 | .m1 = { .min = 18, .max = 26 }, | |
278 | .m2 = { .min = 6, .max = 16 }, | |
279 | .p = { .min = 4, .max = 128 }, | |
280 | .p1 = { .min = 2, .max = 33 }, | |
281 | .p2 = { .dot_limit = 165000, | |
282 | .p2_slow = 4, .p2_fast = 4 }, | |
283 | }; | |
284 | ||
285 | static const intel_limit_t intel_limits_i8xx_lvds = { | |
286 | .dot = { .min = 25000, .max = 350000 }, | |
287 | .vco = { .min = 908000, .max = 1512000 }, | |
288 | .n = { .min = 2, .max = 16 }, | |
289 | .m = { .min = 96, .max = 140 }, | |
290 | .m1 = { .min = 18, .max = 26 }, | |
291 | .m2 = { .min = 6, .max = 16 }, | |
292 | .p = { .min = 4, .max = 128 }, | |
293 | .p1 = { .min = 1, .max = 6 }, | |
294 | .p2 = { .dot_limit = 165000, | |
295 | .p2_slow = 14, .p2_fast = 7 }, | |
296 | }; | |
297 | ||
298 | static const intel_limit_t intel_limits_i9xx_sdvo = { | |
299 | .dot = { .min = 20000, .max = 400000 }, | |
300 | .vco = { .min = 1400000, .max = 2800000 }, | |
301 | .n = { .min = 1, .max = 6 }, | |
302 | .m = { .min = 70, .max = 120 }, | |
303 | .m1 = { .min = 8, .max = 18 }, | |
304 | .m2 = { .min = 3, .max = 7 }, | |
305 | .p = { .min = 5, .max = 80 }, | |
306 | .p1 = { .min = 1, .max = 8 }, | |
307 | .p2 = { .dot_limit = 200000, | |
308 | .p2_slow = 10, .p2_fast = 5 }, | |
309 | }; | |
310 | ||
311 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
312 | .dot = { .min = 20000, .max = 400000 }, | |
313 | .vco = { .min = 1400000, .max = 2800000 }, | |
314 | .n = { .min = 1, .max = 6 }, | |
315 | .m = { .min = 70, .max = 120 }, | |
316 | .m1 = { .min = 8, .max = 18 }, | |
317 | .m2 = { .min = 3, .max = 7 }, | |
318 | .p = { .min = 7, .max = 98 }, | |
319 | .p1 = { .min = 1, .max = 8 }, | |
320 | .p2 = { .dot_limit = 112000, | |
321 | .p2_slow = 14, .p2_fast = 7 }, | |
322 | }; | |
323 | ||
324 | ||
325 | static const intel_limit_t intel_limits_g4x_sdvo = { | |
326 | .dot = { .min = 25000, .max = 270000 }, | |
327 | .vco = { .min = 1750000, .max = 3500000}, | |
328 | .n = { .min = 1, .max = 4 }, | |
329 | .m = { .min = 104, .max = 138 }, | |
330 | .m1 = { .min = 17, .max = 23 }, | |
331 | .m2 = { .min = 5, .max = 11 }, | |
332 | .p = { .min = 10, .max = 30 }, | |
333 | .p1 = { .min = 1, .max = 3}, | |
334 | .p2 = { .dot_limit = 270000, | |
335 | .p2_slow = 10, | |
336 | .p2_fast = 10 | |
337 | }, | |
338 | }; | |
339 | ||
340 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
341 | .dot = { .min = 22000, .max = 400000 }, | |
342 | .vco = { .min = 1750000, .max = 3500000}, | |
343 | .n = { .min = 1, .max = 4 }, | |
344 | .m = { .min = 104, .max = 138 }, | |
345 | .m1 = { .min = 16, .max = 23 }, | |
346 | .m2 = { .min = 5, .max = 11 }, | |
347 | .p = { .min = 5, .max = 80 }, | |
348 | .p1 = { .min = 1, .max = 8}, | |
349 | .p2 = { .dot_limit = 165000, | |
350 | .p2_slow = 10, .p2_fast = 5 }, | |
351 | }; | |
352 | ||
353 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
354 | .dot = { .min = 20000, .max = 115000 }, | |
355 | .vco = { .min = 1750000, .max = 3500000 }, | |
356 | .n = { .min = 1, .max = 3 }, | |
357 | .m = { .min = 104, .max = 138 }, | |
358 | .m1 = { .min = 17, .max = 23 }, | |
359 | .m2 = { .min = 5, .max = 11 }, | |
360 | .p = { .min = 28, .max = 112 }, | |
361 | .p1 = { .min = 2, .max = 8 }, | |
362 | .p2 = { .dot_limit = 0, | |
363 | .p2_slow = 14, .p2_fast = 14 | |
364 | }, | |
365 | }; | |
366 | ||
367 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
368 | .dot = { .min = 80000, .max = 224000 }, | |
369 | .vco = { .min = 1750000, .max = 3500000 }, | |
370 | .n = { .min = 1, .max = 3 }, | |
371 | .m = { .min = 104, .max = 138 }, | |
372 | .m1 = { .min = 17, .max = 23 }, | |
373 | .m2 = { .min = 5, .max = 11 }, | |
374 | .p = { .min = 14, .max = 42 }, | |
375 | .p1 = { .min = 2, .max = 6 }, | |
376 | .p2 = { .dot_limit = 0, | |
377 | .p2_slow = 7, .p2_fast = 7 | |
378 | }, | |
379 | }; | |
380 | ||
381 | static const intel_limit_t intel_limits_pineview_sdvo = { | |
382 | .dot = { .min = 20000, .max = 400000}, | |
383 | .vco = { .min = 1700000, .max = 3500000 }, | |
384 | /* Pineview's Ncounter is a ring counter */ | |
385 | .n = { .min = 3, .max = 6 }, | |
386 | .m = { .min = 2, .max = 256 }, | |
387 | /* Pineview only has one combined m divider, which we treat as m2. */ | |
388 | .m1 = { .min = 0, .max = 0 }, | |
389 | .m2 = { .min = 0, .max = 254 }, | |
390 | .p = { .min = 5, .max = 80 }, | |
391 | .p1 = { .min = 1, .max = 8 }, | |
392 | .p2 = { .dot_limit = 200000, | |
393 | .p2_slow = 10, .p2_fast = 5 }, | |
394 | }; | |
395 | ||
396 | static const intel_limit_t intel_limits_pineview_lvds = { | |
397 | .dot = { .min = 20000, .max = 400000 }, | |
398 | .vco = { .min = 1700000, .max = 3500000 }, | |
399 | .n = { .min = 3, .max = 6 }, | |
400 | .m = { .min = 2, .max = 256 }, | |
401 | .m1 = { .min = 0, .max = 0 }, | |
402 | .m2 = { .min = 0, .max = 254 }, | |
403 | .p = { .min = 7, .max = 112 }, | |
404 | .p1 = { .min = 1, .max = 8 }, | |
405 | .p2 = { .dot_limit = 112000, | |
406 | .p2_slow = 14, .p2_fast = 14 }, | |
407 | }; | |
408 | ||
409 | /* Ironlake / Sandybridge | |
410 | * | |
411 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
412 | * the range value for them is (actual_value - 2). | |
413 | */ | |
414 | static const intel_limit_t intel_limits_ironlake_dac = { | |
415 | .dot = { .min = 25000, .max = 350000 }, | |
416 | .vco = { .min = 1760000, .max = 3510000 }, | |
417 | .n = { .min = 1, .max = 5 }, | |
418 | .m = { .min = 79, .max = 127 }, | |
419 | .m1 = { .min = 12, .max = 22 }, | |
420 | .m2 = { .min = 5, .max = 9 }, | |
421 | .p = { .min = 5, .max = 80 }, | |
422 | .p1 = { .min = 1, .max = 8 }, | |
423 | .p2 = { .dot_limit = 225000, | |
424 | .p2_slow = 10, .p2_fast = 5 }, | |
425 | }; | |
426 | ||
427 | static const intel_limit_t intel_limits_ironlake_single_lvds = { | |
428 | .dot = { .min = 25000, .max = 350000 }, | |
429 | .vco = { .min = 1760000, .max = 3510000 }, | |
430 | .n = { .min = 1, .max = 3 }, | |
431 | .m = { .min = 79, .max = 118 }, | |
432 | .m1 = { .min = 12, .max = 22 }, | |
433 | .m2 = { .min = 5, .max = 9 }, | |
434 | .p = { .min = 28, .max = 112 }, | |
435 | .p1 = { .min = 2, .max = 8 }, | |
436 | .p2 = { .dot_limit = 225000, | |
437 | .p2_slow = 14, .p2_fast = 14 }, | |
438 | }; | |
439 | ||
440 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
441 | .dot = { .min = 25000, .max = 350000 }, | |
442 | .vco = { .min = 1760000, .max = 3510000 }, | |
443 | .n = { .min = 1, .max = 3 }, | |
444 | .m = { .min = 79, .max = 127 }, | |
445 | .m1 = { .min = 12, .max = 22 }, | |
446 | .m2 = { .min = 5, .max = 9 }, | |
447 | .p = { .min = 14, .max = 56 }, | |
448 | .p1 = { .min = 2, .max = 8 }, | |
449 | .p2 = { .dot_limit = 225000, | |
450 | .p2_slow = 7, .p2_fast = 7 }, | |
451 | }; | |
452 | ||
453 | /* LVDS 100mhz refclk limits. */ | |
454 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { | |
455 | .dot = { .min = 25000, .max = 350000 }, | |
456 | .vco = { .min = 1760000, .max = 3510000 }, | |
457 | .n = { .min = 1, .max = 2 }, | |
458 | .m = { .min = 79, .max = 126 }, | |
459 | .m1 = { .min = 12, .max = 22 }, | |
460 | .m2 = { .min = 5, .max = 9 }, | |
461 | .p = { .min = 28, .max = 112 }, | |
462 | .p1 = { .min = 2, .max = 8 }, | |
463 | .p2 = { .dot_limit = 225000, | |
464 | .p2_slow = 14, .p2_fast = 14 }, | |
465 | }; | |
466 | ||
467 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
468 | .dot = { .min = 25000, .max = 350000 }, | |
469 | .vco = { .min = 1760000, .max = 3510000 }, | |
470 | .n = { .min = 1, .max = 3 }, | |
471 | .m = { .min = 79, .max = 126 }, | |
472 | .m1 = { .min = 12, .max = 22 }, | |
473 | .m2 = { .min = 5, .max = 9 }, | |
474 | .p = { .min = 14, .max = 42 }, | |
475 | .p1 = { .min = 2, .max = 6 }, | |
476 | .p2 = { .dot_limit = 225000, | |
477 | .p2_slow = 7, .p2_fast = 7 }, | |
478 | }; | |
479 | ||
480 | static const intel_limit_t intel_limits_vlv = { | |
481 | /* | |
482 | * These are the data rate limits (measured in fast clocks) | |
483 | * since those are the strictest limits we have. The fast | |
484 | * clock and actual rate limits are more relaxed, so checking | |
485 | * them would make no difference. | |
486 | */ | |
487 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
488 | .vco = { .min = 4000000, .max = 6000000 }, | |
489 | .n = { .min = 1, .max = 7 }, | |
490 | .m1 = { .min = 2, .max = 3 }, | |
491 | .m2 = { .min = 11, .max = 156 }, | |
492 | .p1 = { .min = 2, .max = 3 }, | |
493 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ | |
494 | }; | |
495 | ||
496 | static const intel_limit_t intel_limits_chv = { | |
497 | /* | |
498 | * These are the data rate limits (measured in fast clocks) | |
499 | * since those are the strictest limits we have. The fast | |
500 | * clock and actual rate limits are more relaxed, so checking | |
501 | * them would make no difference. | |
502 | */ | |
503 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
504 | .vco = { .min = 4800000, .max = 6480000 }, | |
505 | .n = { .min = 1, .max = 1 }, | |
506 | .m1 = { .min = 2, .max = 2 }, | |
507 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
508 | .p1 = { .min = 2, .max = 4 }, | |
509 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
510 | }; | |
511 | ||
512 | static const intel_limit_t intel_limits_bxt = { | |
513 | /* FIXME: find real dot limits */ | |
514 | .dot = { .min = 0, .max = INT_MAX }, | |
515 | .vco = { .min = 4800000, .max = 6700000 }, | |
516 | .n = { .min = 1, .max = 1 }, | |
517 | .m1 = { .min = 2, .max = 2 }, | |
518 | /* FIXME: find real m2 limits */ | |
519 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
520 | .p1 = { .min = 2, .max = 4 }, | |
521 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
522 | }; | |
523 | ||
524 | static bool | |
525 | needs_modeset(struct drm_crtc_state *state) | |
526 | { | |
527 | return drm_atomic_crtc_needs_modeset(state); | |
528 | } | |
529 | ||
530 | /** | |
531 | * Returns whether any output on the specified pipe is of the specified type | |
532 | */ | |
533 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) | |
534 | { | |
535 | struct drm_device *dev = crtc->base.dev; | |
536 | struct intel_encoder *encoder; | |
537 | ||
538 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
539 | if (encoder->type == type) | |
540 | return true; | |
541 | ||
542 | return false; | |
543 | } | |
544 | ||
545 | /** | |
546 | * Returns whether any output on the specified pipe will have the specified | |
547 | * type after a staged modeset is complete, i.e., the same as | |
548 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
549 | * encoder->crtc. | |
550 | */ | |
551 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, | |
552 | int type) | |
553 | { | |
554 | struct drm_atomic_state *state = crtc_state->base.state; | |
555 | struct drm_connector *connector; | |
556 | struct drm_connector_state *connector_state; | |
557 | struct intel_encoder *encoder; | |
558 | int i, num_connectors = 0; | |
559 | ||
560 | for_each_connector_in_state(state, connector, connector_state, i) { | |
561 | if (connector_state->crtc != crtc_state->base.crtc) | |
562 | continue; | |
563 | ||
564 | num_connectors++; | |
565 | ||
566 | encoder = to_intel_encoder(connector_state->best_encoder); | |
567 | if (encoder->type == type) | |
568 | return true; | |
569 | } | |
570 | ||
571 | WARN_ON(num_connectors == 0); | |
572 | ||
573 | return false; | |
574 | } | |
575 | ||
576 | /* | |
577 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
578 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
579 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
580 | * The helpers' return value is the rate of the clock that is fed to the | |
581 | * display engine's pipe which can be the above fast dot clock rate or a | |
582 | * divided-down version of it. | |
583 | */ | |
584 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ | |
585 | static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock) | |
586 | { | |
587 | clock->m = clock->m2 + 2; | |
588 | clock->p = clock->p1 * clock->p2; | |
589 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
590 | return 0; | |
591 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); | |
592 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
593 | ||
594 | return clock->dot; | |
595 | } | |
596 | ||
597 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) | |
598 | { | |
599 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
600 | } | |
601 | ||
602 | static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock) | |
603 | { | |
604 | clock->m = i9xx_dpll_compute_m(clock); | |
605 | clock->p = clock->p1 * clock->p2; | |
606 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) | |
607 | return 0; | |
608 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); | |
609 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
610 | ||
611 | return clock->dot; | |
612 | } | |
613 | ||
614 | static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock) | |
615 | { | |
616 | clock->m = clock->m1 * clock->m2; | |
617 | clock->p = clock->p1 * clock->p2; | |
618 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
619 | return 0; | |
620 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); | |
621 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
622 | ||
623 | return clock->dot / 5; | |
624 | } | |
625 | ||
626 | int chv_calc_dpll_params(int refclk, intel_clock_t *clock) | |
627 | { | |
628 | clock->m = clock->m1 * clock->m2; | |
629 | clock->p = clock->p1 * clock->p2; | |
630 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
631 | return 0; | |
632 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
633 | clock->n << 22); | |
634 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
635 | ||
636 | return clock->dot / 5; | |
637 | } | |
638 | ||
639 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) | |
640 | /** | |
641 | * Returns whether the given set of divisors are valid for a given refclk with | |
642 | * the given connectors. | |
643 | */ | |
644 | ||
645 | static bool intel_PLL_is_valid(struct drm_device *dev, | |
646 | const intel_limit_t *limit, | |
647 | const intel_clock_t *clock) | |
648 | { | |
649 | if (clock->n < limit->n.min || limit->n.max < clock->n) | |
650 | INTELPllInvalid("n out of range\n"); | |
651 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) | |
652 | INTELPllInvalid("p1 out of range\n"); | |
653 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) | |
654 | INTELPllInvalid("m2 out of range\n"); | |
655 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) | |
656 | INTELPllInvalid("m1 out of range\n"); | |
657 | ||
658 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && | |
659 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
660 | if (clock->m1 <= clock->m2) | |
661 | INTELPllInvalid("m1 <= m2\n"); | |
662 | ||
663 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { | |
664 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
665 | INTELPllInvalid("p out of range\n"); | |
666 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
667 | INTELPllInvalid("m out of range\n"); | |
668 | } | |
669 | ||
670 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) | |
671 | INTELPllInvalid("vco out of range\n"); | |
672 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, | |
673 | * connector, etc., rather than just a single range. | |
674 | */ | |
675 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
676 | INTELPllInvalid("dot out of range\n"); | |
677 | ||
678 | return true; | |
679 | } | |
680 | ||
681 | static int | |
682 | i9xx_select_p2_div(const intel_limit_t *limit, | |
683 | const struct intel_crtc_state *crtc_state, | |
684 | int target) | |
685 | { | |
686 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
687 | ||
688 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { | |
689 | /* | |
690 | * For LVDS just rely on its current settings for dual-channel. | |
691 | * We haven't figured out how to reliably set up different | |
692 | * single/dual channel state, if we even can. | |
693 | */ | |
694 | if (intel_is_dual_link_lvds(dev)) | |
695 | return limit->p2.p2_fast; | |
696 | else | |
697 | return limit->p2.p2_slow; | |
698 | } else { | |
699 | if (target < limit->p2.dot_limit) | |
700 | return limit->p2.p2_slow; | |
701 | else | |
702 | return limit->p2.p2_fast; | |
703 | } | |
704 | } | |
705 | ||
706 | /* | |
707 | * Returns a set of divisors for the desired target clock with the given | |
708 | * refclk, or FALSE. The returned values represent the clock equation: | |
709 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
710 | * | |
711 | * Target and reference clocks are specified in kHz. | |
712 | * | |
713 | * If match_clock is provided, then best_clock P divider must match the P | |
714 | * divider from @match_clock used for LVDS downclocking. | |
715 | */ | |
716 | static bool | |
717 | i9xx_find_best_dpll(const intel_limit_t *limit, | |
718 | struct intel_crtc_state *crtc_state, | |
719 | int target, int refclk, intel_clock_t *match_clock, | |
720 | intel_clock_t *best_clock) | |
721 | { | |
722 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
723 | intel_clock_t clock; | |
724 | int err = target; | |
725 | ||
726 | memset(best_clock, 0, sizeof(*best_clock)); | |
727 | ||
728 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
729 | ||
730 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; | |
731 | clock.m1++) { | |
732 | for (clock.m2 = limit->m2.min; | |
733 | clock.m2 <= limit->m2.max; clock.m2++) { | |
734 | if (clock.m2 >= clock.m1) | |
735 | break; | |
736 | for (clock.n = limit->n.min; | |
737 | clock.n <= limit->n.max; clock.n++) { | |
738 | for (clock.p1 = limit->p1.min; | |
739 | clock.p1 <= limit->p1.max; clock.p1++) { | |
740 | int this_err; | |
741 | ||
742 | i9xx_calc_dpll_params(refclk, &clock); | |
743 | if (!intel_PLL_is_valid(dev, limit, | |
744 | &clock)) | |
745 | continue; | |
746 | if (match_clock && | |
747 | clock.p != match_clock->p) | |
748 | continue; | |
749 | ||
750 | this_err = abs(clock.dot - target); | |
751 | if (this_err < err) { | |
752 | *best_clock = clock; | |
753 | err = this_err; | |
754 | } | |
755 | } | |
756 | } | |
757 | } | |
758 | } | |
759 | ||
760 | return (err != target); | |
761 | } | |
762 | ||
763 | /* | |
764 | * Returns a set of divisors for the desired target clock with the given | |
765 | * refclk, or FALSE. The returned values represent the clock equation: | |
766 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
767 | * | |
768 | * Target and reference clocks are specified in kHz. | |
769 | * | |
770 | * If match_clock is provided, then best_clock P divider must match the P | |
771 | * divider from @match_clock used for LVDS downclocking. | |
772 | */ | |
773 | static bool | |
774 | pnv_find_best_dpll(const intel_limit_t *limit, | |
775 | struct intel_crtc_state *crtc_state, | |
776 | int target, int refclk, intel_clock_t *match_clock, | |
777 | intel_clock_t *best_clock) | |
778 | { | |
779 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
780 | intel_clock_t clock; | |
781 | int err = target; | |
782 | ||
783 | memset(best_clock, 0, sizeof(*best_clock)); | |
784 | ||
785 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
786 | ||
787 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; | |
788 | clock.m1++) { | |
789 | for (clock.m2 = limit->m2.min; | |
790 | clock.m2 <= limit->m2.max; clock.m2++) { | |
791 | for (clock.n = limit->n.min; | |
792 | clock.n <= limit->n.max; clock.n++) { | |
793 | for (clock.p1 = limit->p1.min; | |
794 | clock.p1 <= limit->p1.max; clock.p1++) { | |
795 | int this_err; | |
796 | ||
797 | pnv_calc_dpll_params(refclk, &clock); | |
798 | if (!intel_PLL_is_valid(dev, limit, | |
799 | &clock)) | |
800 | continue; | |
801 | if (match_clock && | |
802 | clock.p != match_clock->p) | |
803 | continue; | |
804 | ||
805 | this_err = abs(clock.dot - target); | |
806 | if (this_err < err) { | |
807 | *best_clock = clock; | |
808 | err = this_err; | |
809 | } | |
810 | } | |
811 | } | |
812 | } | |
813 | } | |
814 | ||
815 | return (err != target); | |
816 | } | |
817 | ||
818 | /* | |
819 | * Returns a set of divisors for the desired target clock with the given | |
820 | * refclk, or FALSE. The returned values represent the clock equation: | |
821 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
822 | * | |
823 | * Target and reference clocks are specified in kHz. | |
824 | * | |
825 | * If match_clock is provided, then best_clock P divider must match the P | |
826 | * divider from @match_clock used for LVDS downclocking. | |
827 | */ | |
828 | static bool | |
829 | g4x_find_best_dpll(const intel_limit_t *limit, | |
830 | struct intel_crtc_state *crtc_state, | |
831 | int target, int refclk, intel_clock_t *match_clock, | |
832 | intel_clock_t *best_clock) | |
833 | { | |
834 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
835 | intel_clock_t clock; | |
836 | int max_n; | |
837 | bool found = false; | |
838 | /* approximately equals target * 0.00585 */ | |
839 | int err_most = (target >> 8) + (target >> 9); | |
840 | ||
841 | memset(best_clock, 0, sizeof(*best_clock)); | |
842 | ||
843 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
844 | ||
845 | max_n = limit->n.max; | |
846 | /* based on hardware requirement, prefer smaller n to precision */ | |
847 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { | |
848 | /* based on hardware requirement, prefere larger m1,m2 */ | |
849 | for (clock.m1 = limit->m1.max; | |
850 | clock.m1 >= limit->m1.min; clock.m1--) { | |
851 | for (clock.m2 = limit->m2.max; | |
852 | clock.m2 >= limit->m2.min; clock.m2--) { | |
853 | for (clock.p1 = limit->p1.max; | |
854 | clock.p1 >= limit->p1.min; clock.p1--) { | |
855 | int this_err; | |
856 | ||
857 | i9xx_calc_dpll_params(refclk, &clock); | |
858 | if (!intel_PLL_is_valid(dev, limit, | |
859 | &clock)) | |
860 | continue; | |
861 | ||
862 | this_err = abs(clock.dot - target); | |
863 | if (this_err < err_most) { | |
864 | *best_clock = clock; | |
865 | err_most = this_err; | |
866 | max_n = clock.n; | |
867 | found = true; | |
868 | } | |
869 | } | |
870 | } | |
871 | } | |
872 | } | |
873 | return found; | |
874 | } | |
875 | ||
876 | /* | |
877 | * Check if the calculated PLL configuration is more optimal compared to the | |
878 | * best configuration and error found so far. Return the calculated error. | |
879 | */ | |
880 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
881 | const intel_clock_t *calculated_clock, | |
882 | const intel_clock_t *best_clock, | |
883 | unsigned int best_error_ppm, | |
884 | unsigned int *error_ppm) | |
885 | { | |
886 | /* | |
887 | * For CHV ignore the error and consider only the P value. | |
888 | * Prefer a bigger P value based on HW requirements. | |
889 | */ | |
890 | if (IS_CHERRYVIEW(dev)) { | |
891 | *error_ppm = 0; | |
892 | ||
893 | return calculated_clock->p > best_clock->p; | |
894 | } | |
895 | ||
896 | if (WARN_ON_ONCE(!target_freq)) | |
897 | return false; | |
898 | ||
899 | *error_ppm = div_u64(1000000ULL * | |
900 | abs(target_freq - calculated_clock->dot), | |
901 | target_freq); | |
902 | /* | |
903 | * Prefer a better P value over a better (smaller) error if the error | |
904 | * is small. Ensure this preference for future configurations too by | |
905 | * setting the error to 0. | |
906 | */ | |
907 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
908 | *error_ppm = 0; | |
909 | ||
910 | return true; | |
911 | } | |
912 | ||
913 | return *error_ppm + 10 < best_error_ppm; | |
914 | } | |
915 | ||
916 | /* | |
917 | * Returns a set of divisors for the desired target clock with the given | |
918 | * refclk, or FALSE. The returned values represent the clock equation: | |
919 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
920 | */ | |
921 | static bool | |
922 | vlv_find_best_dpll(const intel_limit_t *limit, | |
923 | struct intel_crtc_state *crtc_state, | |
924 | int target, int refclk, intel_clock_t *match_clock, | |
925 | intel_clock_t *best_clock) | |
926 | { | |
927 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
928 | struct drm_device *dev = crtc->base.dev; | |
929 | intel_clock_t clock; | |
930 | unsigned int bestppm = 1000000; | |
931 | /* min update 19.2 MHz */ | |
932 | int max_n = min(limit->n.max, refclk / 19200); | |
933 | bool found = false; | |
934 | ||
935 | target *= 5; /* fast clock */ | |
936 | ||
937 | memset(best_clock, 0, sizeof(*best_clock)); | |
938 | ||
939 | /* based on hardware requirement, prefer smaller n to precision */ | |
940 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { | |
941 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
942 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; | |
943 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
944 | clock.p = clock.p1 * clock.p2; | |
945 | /* based on hardware requirement, prefer bigger m1,m2 values */ | |
946 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { | |
947 | unsigned int ppm; | |
948 | ||
949 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, | |
950 | refclk * clock.m1); | |
951 | ||
952 | vlv_calc_dpll_params(refclk, &clock); | |
953 | ||
954 | if (!intel_PLL_is_valid(dev, limit, | |
955 | &clock)) | |
956 | continue; | |
957 | ||
958 | if (!vlv_PLL_is_optimal(dev, target, | |
959 | &clock, | |
960 | best_clock, | |
961 | bestppm, &ppm)) | |
962 | continue; | |
963 | ||
964 | *best_clock = clock; | |
965 | bestppm = ppm; | |
966 | found = true; | |
967 | } | |
968 | } | |
969 | } | |
970 | } | |
971 | ||
972 | return found; | |
973 | } | |
974 | ||
975 | /* | |
976 | * Returns a set of divisors for the desired target clock with the given | |
977 | * refclk, or FALSE. The returned values represent the clock equation: | |
978 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
979 | */ | |
980 | static bool | |
981 | chv_find_best_dpll(const intel_limit_t *limit, | |
982 | struct intel_crtc_state *crtc_state, | |
983 | int target, int refclk, intel_clock_t *match_clock, | |
984 | intel_clock_t *best_clock) | |
985 | { | |
986 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
987 | struct drm_device *dev = crtc->base.dev; | |
988 | unsigned int best_error_ppm; | |
989 | intel_clock_t clock; | |
990 | uint64_t m2; | |
991 | int found = false; | |
992 | ||
993 | memset(best_clock, 0, sizeof(*best_clock)); | |
994 | best_error_ppm = 1000000; | |
995 | ||
996 | /* | |
997 | * Based on hardware doc, the n always set to 1, and m1 always | |
998 | * set to 2. If requires to support 200Mhz refclk, we need to | |
999 | * revisit this because n may not 1 anymore. | |
1000 | */ | |
1001 | clock.n = 1, clock.m1 = 2; | |
1002 | target *= 5; /* fast clock */ | |
1003 | ||
1004 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
1005 | for (clock.p2 = limit->p2.p2_fast; | |
1006 | clock.p2 >= limit->p2.p2_slow; | |
1007 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
1008 | unsigned int error_ppm; | |
1009 | ||
1010 | clock.p = clock.p1 * clock.p2; | |
1011 | ||
1012 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
1013 | clock.n) << 22, refclk * clock.m1); | |
1014 | ||
1015 | if (m2 > INT_MAX/clock.m1) | |
1016 | continue; | |
1017 | ||
1018 | clock.m2 = m2; | |
1019 | ||
1020 | chv_calc_dpll_params(refclk, &clock); | |
1021 | ||
1022 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
1023 | continue; | |
1024 | ||
1025 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, | |
1026 | best_error_ppm, &error_ppm)) | |
1027 | continue; | |
1028 | ||
1029 | *best_clock = clock; | |
1030 | best_error_ppm = error_ppm; | |
1031 | found = true; | |
1032 | } | |
1033 | } | |
1034 | ||
1035 | return found; | |
1036 | } | |
1037 | ||
1038 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, | |
1039 | intel_clock_t *best_clock) | |
1040 | { | |
1041 | int refclk = 100000; | |
1042 | const intel_limit_t *limit = &intel_limits_bxt; | |
1043 | ||
1044 | return chv_find_best_dpll(limit, crtc_state, | |
1045 | target_clock, refclk, NULL, best_clock); | |
1046 | } | |
1047 | ||
1048 | bool intel_crtc_active(struct drm_crtc *crtc) | |
1049 | { | |
1050 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1051 | ||
1052 | /* Be paranoid as we can arrive here with only partial | |
1053 | * state retrieved from the hardware during setup. | |
1054 | * | |
1055 | * We can ditch the adjusted_mode.crtc_clock check as soon | |
1056 | * as Haswell has gained clock readout/fastboot support. | |
1057 | * | |
1058 | * We can ditch the crtc->primary->fb check as soon as we can | |
1059 | * properly reconstruct framebuffers. | |
1060 | * | |
1061 | * FIXME: The intel_crtc->active here should be switched to | |
1062 | * crtc->state->active once we have proper CRTC states wired up | |
1063 | * for atomic. | |
1064 | */ | |
1065 | return intel_crtc->active && crtc->primary->state->fb && | |
1066 | intel_crtc->config->base.adjusted_mode.crtc_clock; | |
1067 | } | |
1068 | ||
1069 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, | |
1070 | enum pipe pipe) | |
1071 | { | |
1072 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1073 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1074 | ||
1075 | return intel_crtc->config->cpu_transcoder; | |
1076 | } | |
1077 | ||
1078 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) | |
1079 | { | |
1080 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1081 | i915_reg_t reg = PIPEDSL(pipe); | |
1082 | u32 line1, line2; | |
1083 | u32 line_mask; | |
1084 | ||
1085 | if (IS_GEN2(dev)) | |
1086 | line_mask = DSL_LINEMASK_GEN2; | |
1087 | else | |
1088 | line_mask = DSL_LINEMASK_GEN3; | |
1089 | ||
1090 | line1 = I915_READ(reg) & line_mask; | |
1091 | msleep(5); | |
1092 | line2 = I915_READ(reg) & line_mask; | |
1093 | ||
1094 | return line1 == line2; | |
1095 | } | |
1096 | ||
1097 | /* | |
1098 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
1099 | * @crtc: crtc whose pipe to wait for | |
1100 | * | |
1101 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1102 | * spinning on the vblank interrupt status bit, since we won't actually | |
1103 | * see an interrupt when the pipe is disabled. | |
1104 | * | |
1105 | * On Gen4 and above: | |
1106 | * wait for the pipe register state bit to turn off | |
1107 | * | |
1108 | * Otherwise: | |
1109 | * wait for the display line value to settle (it usually | |
1110 | * ends up stopping at the start of the next frame). | |
1111 | * | |
1112 | */ | |
1113 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) | |
1114 | { | |
1115 | struct drm_device *dev = crtc->base.dev; | |
1116 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1117 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; | |
1118 | enum pipe pipe = crtc->pipe; | |
1119 | ||
1120 | if (INTEL_INFO(dev)->gen >= 4) { | |
1121 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
1122 | ||
1123 | /* Wait for the Pipe State to go off */ | |
1124 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, | |
1125 | 100)) | |
1126 | WARN(1, "pipe_off wait timed out\n"); | |
1127 | } else { | |
1128 | /* Wait for the display line to settle */ | |
1129 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) | |
1130 | WARN(1, "pipe_off wait timed out\n"); | |
1131 | } | |
1132 | } | |
1133 | ||
1134 | /* Only for pre-ILK configs */ | |
1135 | void assert_pll(struct drm_i915_private *dev_priv, | |
1136 | enum pipe pipe, bool state) | |
1137 | { | |
1138 | u32 val; | |
1139 | bool cur_state; | |
1140 | ||
1141 | val = I915_READ(DPLL(pipe)); | |
1142 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1143 | I915_STATE_WARN(cur_state != state, | |
1144 | "PLL state assertion failure (expected %s, current %s)\n", | |
1145 | onoff(state), onoff(cur_state)); | |
1146 | } | |
1147 | ||
1148 | /* XXX: the dsi pll is shared between MIPI DSI ports */ | |
1149 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1150 | { | |
1151 | u32 val; | |
1152 | bool cur_state; | |
1153 | ||
1154 | mutex_lock(&dev_priv->sb_lock); | |
1155 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1156 | mutex_unlock(&dev_priv->sb_lock); | |
1157 | ||
1158 | cur_state = val & DSI_PLL_VCO_EN; | |
1159 | I915_STATE_WARN(cur_state != state, | |
1160 | "DSI PLL state assertion failure (expected %s, current %s)\n", | |
1161 | onoff(state), onoff(cur_state)); | |
1162 | } | |
1163 | ||
1164 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1165 | enum pipe pipe, bool state) | |
1166 | { | |
1167 | bool cur_state; | |
1168 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, | |
1169 | pipe); | |
1170 | ||
1171 | if (HAS_DDI(dev_priv)) { | |
1172 | /* DDI does not have a specific FDI_TX register */ | |
1173 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1174 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); | |
1175 | } else { | |
1176 | u32 val = I915_READ(FDI_TX_CTL(pipe)); | |
1177 | cur_state = !!(val & FDI_TX_ENABLE); | |
1178 | } | |
1179 | I915_STATE_WARN(cur_state != state, | |
1180 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1181 | onoff(state), onoff(cur_state)); | |
1182 | } | |
1183 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1184 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1185 | ||
1186 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1187 | enum pipe pipe, bool state) | |
1188 | { | |
1189 | u32 val; | |
1190 | bool cur_state; | |
1191 | ||
1192 | val = I915_READ(FDI_RX_CTL(pipe)); | |
1193 | cur_state = !!(val & FDI_RX_ENABLE); | |
1194 | I915_STATE_WARN(cur_state != state, | |
1195 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1196 | onoff(state), onoff(cur_state)); | |
1197 | } | |
1198 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1199 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1200 | ||
1201 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1202 | enum pipe pipe) | |
1203 | { | |
1204 | u32 val; | |
1205 | ||
1206 | /* ILK FDI PLL is always enabled */ | |
1207 | if (INTEL_INFO(dev_priv)->gen == 5) | |
1208 | return; | |
1209 | ||
1210 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ | |
1211 | if (HAS_DDI(dev_priv)) | |
1212 | return; | |
1213 | ||
1214 | val = I915_READ(FDI_TX_CTL(pipe)); | |
1215 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1216 | } | |
1217 | ||
1218 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, | |
1219 | enum pipe pipe, bool state) | |
1220 | { | |
1221 | u32 val; | |
1222 | bool cur_state; | |
1223 | ||
1224 | val = I915_READ(FDI_RX_CTL(pipe)); | |
1225 | cur_state = !!(val & FDI_RX_PLL_ENABLE); | |
1226 | I915_STATE_WARN(cur_state != state, | |
1227 | "FDI RX PLL assertion failure (expected %s, current %s)\n", | |
1228 | onoff(state), onoff(cur_state)); | |
1229 | } | |
1230 | ||
1231 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, | |
1232 | enum pipe pipe) | |
1233 | { | |
1234 | struct drm_device *dev = dev_priv->dev; | |
1235 | i915_reg_t pp_reg; | |
1236 | u32 val; | |
1237 | enum pipe panel_pipe = PIPE_A; | |
1238 | bool locked = true; | |
1239 | ||
1240 | if (WARN_ON(HAS_DDI(dev))) | |
1241 | return; | |
1242 | ||
1243 | if (HAS_PCH_SPLIT(dev)) { | |
1244 | u32 port_sel; | |
1245 | ||
1246 | pp_reg = PCH_PP_CONTROL; | |
1247 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; | |
1248 | ||
1249 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1250 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1251 | panel_pipe = PIPE_B; | |
1252 | /* XXX: else fix for eDP */ | |
1253 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { | |
1254 | /* presumably write lock depends on pipe, not port select */ | |
1255 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1256 | panel_pipe = pipe; | |
1257 | } else { | |
1258 | pp_reg = PP_CONTROL; | |
1259 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) | |
1260 | panel_pipe = PIPE_B; | |
1261 | } | |
1262 | ||
1263 | val = I915_READ(pp_reg); | |
1264 | if (!(val & PANEL_POWER_ON) || | |
1265 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) | |
1266 | locked = false; | |
1267 | ||
1268 | I915_STATE_WARN(panel_pipe == pipe && locked, | |
1269 | "panel assertion failure, pipe %c regs locked\n", | |
1270 | pipe_name(pipe)); | |
1271 | } | |
1272 | ||
1273 | static void assert_cursor(struct drm_i915_private *dev_priv, | |
1274 | enum pipe pipe, bool state) | |
1275 | { | |
1276 | struct drm_device *dev = dev_priv->dev; | |
1277 | bool cur_state; | |
1278 | ||
1279 | if (IS_845G(dev) || IS_I865G(dev)) | |
1280 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; | |
1281 | else | |
1282 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; | |
1283 | ||
1284 | I915_STATE_WARN(cur_state != state, | |
1285 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", | |
1286 | pipe_name(pipe), onoff(state), onoff(cur_state)); | |
1287 | } | |
1288 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1289 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1290 | ||
1291 | void assert_pipe(struct drm_i915_private *dev_priv, | |
1292 | enum pipe pipe, bool state) | |
1293 | { | |
1294 | bool cur_state; | |
1295 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, | |
1296 | pipe); | |
1297 | enum intel_display_power_domain power_domain; | |
1298 | ||
1299 | /* if we need the pipe quirk it must be always on */ | |
1300 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1301 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
1302 | state = true; | |
1303 | ||
1304 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
1305 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
1306 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); | |
1307 | cur_state = !!(val & PIPECONF_ENABLE); | |
1308 | ||
1309 | intel_display_power_put(dev_priv, power_domain); | |
1310 | } else { | |
1311 | cur_state = false; | |
1312 | } | |
1313 | ||
1314 | I915_STATE_WARN(cur_state != state, | |
1315 | "pipe %c assertion failure (expected %s, current %s)\n", | |
1316 | pipe_name(pipe), onoff(state), onoff(cur_state)); | |
1317 | } | |
1318 | ||
1319 | static void assert_plane(struct drm_i915_private *dev_priv, | |
1320 | enum plane plane, bool state) | |
1321 | { | |
1322 | u32 val; | |
1323 | bool cur_state; | |
1324 | ||
1325 | val = I915_READ(DSPCNTR(plane)); | |
1326 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); | |
1327 | I915_STATE_WARN(cur_state != state, | |
1328 | "plane %c assertion failure (expected %s, current %s)\n", | |
1329 | plane_name(plane), onoff(state), onoff(cur_state)); | |
1330 | } | |
1331 | ||
1332 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) | |
1333 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1334 | ||
1335 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, | |
1336 | enum pipe pipe) | |
1337 | { | |
1338 | struct drm_device *dev = dev_priv->dev; | |
1339 | int i; | |
1340 | ||
1341 | /* Primary planes are fixed to pipes on gen4+ */ | |
1342 | if (INTEL_INFO(dev)->gen >= 4) { | |
1343 | u32 val = I915_READ(DSPCNTR(pipe)); | |
1344 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, | |
1345 | "plane %c assertion failure, should be disabled but not\n", | |
1346 | plane_name(pipe)); | |
1347 | return; | |
1348 | } | |
1349 | ||
1350 | /* Need to check both planes against the pipe */ | |
1351 | for_each_pipe(dev_priv, i) { | |
1352 | u32 val = I915_READ(DSPCNTR(i)); | |
1353 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1354 | DISPPLANE_SEL_PIPE_SHIFT; | |
1355 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
1356 | "plane %c assertion failure, should be off on pipe %c but is still active\n", | |
1357 | plane_name(i), pipe_name(pipe)); | |
1358 | } | |
1359 | } | |
1360 | ||
1361 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, | |
1362 | enum pipe pipe) | |
1363 | { | |
1364 | struct drm_device *dev = dev_priv->dev; | |
1365 | int sprite; | |
1366 | ||
1367 | if (INTEL_INFO(dev)->gen >= 9) { | |
1368 | for_each_sprite(dev_priv, pipe, sprite) { | |
1369 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); | |
1370 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, | |
1371 | "plane %d assertion failure, should be off on pipe %c but is still active\n", | |
1372 | sprite, pipe_name(pipe)); | |
1373 | } | |
1374 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { | |
1375 | for_each_sprite(dev_priv, pipe, sprite) { | |
1376 | u32 val = I915_READ(SPCNTR(pipe, sprite)); | |
1377 | I915_STATE_WARN(val & SP_ENABLE, | |
1378 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", | |
1379 | sprite_name(pipe, sprite), pipe_name(pipe)); | |
1380 | } | |
1381 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1382 | u32 val = I915_READ(SPRCTL(pipe)); | |
1383 | I915_STATE_WARN(val & SPRITE_ENABLE, | |
1384 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", | |
1385 | plane_name(pipe), pipe_name(pipe)); | |
1386 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1387 | u32 val = I915_READ(DVSCNTR(pipe)); | |
1388 | I915_STATE_WARN(val & DVS_ENABLE, | |
1389 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", | |
1390 | plane_name(pipe), pipe_name(pipe)); | |
1391 | } | |
1392 | } | |
1393 | ||
1394 | static void assert_vblank_disabled(struct drm_crtc *crtc) | |
1395 | { | |
1396 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) | |
1397 | drm_crtc_vblank_put(crtc); | |
1398 | } | |
1399 | ||
1400 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, | |
1401 | enum pipe pipe) | |
1402 | { | |
1403 | u32 val; | |
1404 | bool enabled; | |
1405 | ||
1406 | val = I915_READ(PCH_TRANSCONF(pipe)); | |
1407 | enabled = !!(val & TRANS_ENABLE); | |
1408 | I915_STATE_WARN(enabled, | |
1409 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1410 | pipe_name(pipe)); | |
1411 | } | |
1412 | ||
1413 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, | |
1414 | enum pipe pipe, u32 port_sel, u32 val) | |
1415 | { | |
1416 | if ((val & DP_PORT_EN) == 0) | |
1417 | return false; | |
1418 | ||
1419 | if (HAS_PCH_CPT(dev_priv)) { | |
1420 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); | |
1421 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1422 | return false; | |
1423 | } else if (IS_CHERRYVIEW(dev_priv)) { | |
1424 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1425 | return false; | |
1426 | } else { | |
1427 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1428 | return false; | |
1429 | } | |
1430 | return true; | |
1431 | } | |
1432 | ||
1433 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, | |
1434 | enum pipe pipe, u32 val) | |
1435 | { | |
1436 | if ((val & SDVO_ENABLE) == 0) | |
1437 | return false; | |
1438 | ||
1439 | if (HAS_PCH_CPT(dev_priv)) { | |
1440 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) | |
1441 | return false; | |
1442 | } else if (IS_CHERRYVIEW(dev_priv)) { | |
1443 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1444 | return false; | |
1445 | } else { | |
1446 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) | |
1447 | return false; | |
1448 | } | |
1449 | return true; | |
1450 | } | |
1451 | ||
1452 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1453 | enum pipe pipe, u32 val) | |
1454 | { | |
1455 | if ((val & LVDS_PORT_EN) == 0) | |
1456 | return false; | |
1457 | ||
1458 | if (HAS_PCH_CPT(dev_priv)) { | |
1459 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1460 | return false; | |
1461 | } else { | |
1462 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1463 | return false; | |
1464 | } | |
1465 | return true; | |
1466 | } | |
1467 | ||
1468 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1469 | enum pipe pipe, u32 val) | |
1470 | { | |
1471 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1472 | return false; | |
1473 | if (HAS_PCH_CPT(dev_priv)) { | |
1474 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1475 | return false; | |
1476 | } else { | |
1477 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1478 | return false; | |
1479 | } | |
1480 | return true; | |
1481 | } | |
1482 | ||
1483 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, | |
1484 | enum pipe pipe, i915_reg_t reg, | |
1485 | u32 port_sel) | |
1486 | { | |
1487 | u32 val = I915_READ(reg); | |
1488 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), | |
1489 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", | |
1490 | i915_mmio_reg_offset(reg), pipe_name(pipe)); | |
1491 | ||
1492 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 | |
1493 | && (val & DP_PIPEB_SELECT), | |
1494 | "IBX PCH dp port still using transcoder B\n"); | |
1495 | } | |
1496 | ||
1497 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1498 | enum pipe pipe, i915_reg_t reg) | |
1499 | { | |
1500 | u32 val = I915_READ(reg); | |
1501 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), | |
1502 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", | |
1503 | i915_mmio_reg_offset(reg), pipe_name(pipe)); | |
1504 | ||
1505 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 | |
1506 | && (val & SDVO_PIPE_B_SELECT), | |
1507 | "IBX PCH hdmi port still using transcoder B\n"); | |
1508 | } | |
1509 | ||
1510 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1511 | enum pipe pipe) | |
1512 | { | |
1513 | u32 val; | |
1514 | ||
1515 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); | |
1516 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1517 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
1518 | ||
1519 | val = I915_READ(PCH_ADPA); | |
1520 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), | |
1521 | "PCH VGA enabled on transcoder %c, should be disabled\n", | |
1522 | pipe_name(pipe)); | |
1523 | ||
1524 | val = I915_READ(PCH_LVDS); | |
1525 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), | |
1526 | "PCH LVDS enabled on transcoder %c, should be disabled\n", | |
1527 | pipe_name(pipe)); | |
1528 | ||
1529 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); | |
1530 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1531 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
1532 | } | |
1533 | ||
1534 | static void _vlv_enable_pll(struct intel_crtc *crtc, | |
1535 | const struct intel_crtc_state *pipe_config) | |
1536 | { | |
1537 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1538 | enum pipe pipe = crtc->pipe; | |
1539 | ||
1540 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1541 | POSTING_READ(DPLL(pipe)); | |
1542 | udelay(150); | |
1543 | ||
1544 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1545 | DRM_ERROR("DPLL %d failed to lock\n", pipe); | |
1546 | } | |
1547 | ||
1548 | static void vlv_enable_pll(struct intel_crtc *crtc, | |
1549 | const struct intel_crtc_state *pipe_config) | |
1550 | { | |
1551 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1552 | enum pipe pipe = crtc->pipe; | |
1553 | ||
1554 | assert_pipe_disabled(dev_priv, pipe); | |
1555 | ||
1556 | /* PLL is protected by panel, make sure we can write it */ | |
1557 | assert_panel_unlocked(dev_priv, pipe); | |
1558 | ||
1559 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1560 | _vlv_enable_pll(crtc, pipe_config); | |
1561 | ||
1562 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1563 | POSTING_READ(DPLL_MD(pipe)); | |
1564 | } | |
1565 | ||
1566 | ||
1567 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1568 | const struct intel_crtc_state *pipe_config) | |
1569 | { | |
1570 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1571 | enum pipe pipe = crtc->pipe; | |
1572 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
1573 | u32 tmp; | |
1574 | ||
1575 | mutex_lock(&dev_priv->sb_lock); | |
1576 | ||
1577 | /* Enable back the 10bit clock to display controller */ | |
1578 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1579 | tmp |= DPIO_DCLKP_EN; | |
1580 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1581 | ||
1582 | mutex_unlock(&dev_priv->sb_lock); | |
1583 | ||
1584 | /* | |
1585 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1586 | */ | |
1587 | udelay(1); | |
1588 | ||
1589 | /* Enable PLL */ | |
1590 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1591 | ||
1592 | /* Check PLL is locked */ | |
1593 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1594 | DRM_ERROR("PLL %d failed to lock\n", pipe); | |
1595 | } | |
1596 | ||
1597 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1598 | const struct intel_crtc_state *pipe_config) | |
1599 | { | |
1600 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1601 | enum pipe pipe = crtc->pipe; | |
1602 | ||
1603 | assert_pipe_disabled(dev_priv, pipe); | |
1604 | ||
1605 | /* PLL is protected by panel, make sure we can write it */ | |
1606 | assert_panel_unlocked(dev_priv, pipe); | |
1607 | ||
1608 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1609 | _chv_enable_pll(crtc, pipe_config); | |
1610 | ||
1611 | if (pipe != PIPE_A) { | |
1612 | /* | |
1613 | * WaPixelRepeatModeFixForC0:chv | |
1614 | * | |
1615 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1616 | * the value from DPLLBMD to either pipe B or C. | |
1617 | */ | |
1618 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1619 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1620 | I915_WRITE(CBR4_VLV, 0); | |
1621 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1622 | ||
1623 | /* | |
1624 | * DPLLB VGA mode also seems to cause problems. | |
1625 | * We should always have it disabled. | |
1626 | */ | |
1627 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1628 | } else { | |
1629 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1630 | POSTING_READ(DPLL_MD(pipe)); | |
1631 | } | |
1632 | } | |
1633 | ||
1634 | static int intel_num_dvo_pipes(struct drm_device *dev) | |
1635 | { | |
1636 | struct intel_crtc *crtc; | |
1637 | int count = 0; | |
1638 | ||
1639 | for_each_intel_crtc(dev, crtc) | |
1640 | count += crtc->base.state->active && | |
1641 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); | |
1642 | ||
1643 | return count; | |
1644 | } | |
1645 | ||
1646 | static void i9xx_enable_pll(struct intel_crtc *crtc) | |
1647 | { | |
1648 | struct drm_device *dev = crtc->base.dev; | |
1649 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1650 | i915_reg_t reg = DPLL(crtc->pipe); | |
1651 | u32 dpll = crtc->config->dpll_hw_state.dpll; | |
1652 | ||
1653 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1654 | ||
1655 | /* PLL is protected by panel, make sure we can write it */ | |
1656 | if (IS_MOBILE(dev) && !IS_I830(dev)) | |
1657 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
1658 | ||
1659 | /* Enable DVO 2x clock on both PLLs if necessary */ | |
1660 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1661 | /* | |
1662 | * It appears to be important that we don't enable this | |
1663 | * for the current pipe before otherwise configuring the | |
1664 | * PLL. No idea how this should be handled if multiple | |
1665 | * DVO outputs are enabled simultaneosly. | |
1666 | */ | |
1667 | dpll |= DPLL_DVO_2X_MODE; | |
1668 | I915_WRITE(DPLL(!crtc->pipe), | |
1669 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1670 | } | |
1671 | ||
1672 | /* | |
1673 | * Apparently we need to have VGA mode enabled prior to changing | |
1674 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1675 | * dividers, even though the register value does change. | |
1676 | */ | |
1677 | I915_WRITE(reg, 0); | |
1678 | ||
1679 | I915_WRITE(reg, dpll); | |
1680 | ||
1681 | /* Wait for the clocks to stabilize. */ | |
1682 | POSTING_READ(reg); | |
1683 | udelay(150); | |
1684 | ||
1685 | if (INTEL_INFO(dev)->gen >= 4) { | |
1686 | I915_WRITE(DPLL_MD(crtc->pipe), | |
1687 | crtc->config->dpll_hw_state.dpll_md); | |
1688 | } else { | |
1689 | /* The pixel multiplier can only be updated once the | |
1690 | * DPLL is enabled and the clocks are stable. | |
1691 | * | |
1692 | * So write it again. | |
1693 | */ | |
1694 | I915_WRITE(reg, dpll); | |
1695 | } | |
1696 | ||
1697 | /* We do this three times for luck */ | |
1698 | I915_WRITE(reg, dpll); | |
1699 | POSTING_READ(reg); | |
1700 | udelay(150); /* wait for warmup */ | |
1701 | I915_WRITE(reg, dpll); | |
1702 | POSTING_READ(reg); | |
1703 | udelay(150); /* wait for warmup */ | |
1704 | I915_WRITE(reg, dpll); | |
1705 | POSTING_READ(reg); | |
1706 | udelay(150); /* wait for warmup */ | |
1707 | } | |
1708 | ||
1709 | /** | |
1710 | * i9xx_disable_pll - disable a PLL | |
1711 | * @dev_priv: i915 private structure | |
1712 | * @pipe: pipe PLL to disable | |
1713 | * | |
1714 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1715 | * | |
1716 | * Note! This is for pre-ILK only. | |
1717 | */ | |
1718 | static void i9xx_disable_pll(struct intel_crtc *crtc) | |
1719 | { | |
1720 | struct drm_device *dev = crtc->base.dev; | |
1721 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1722 | enum pipe pipe = crtc->pipe; | |
1723 | ||
1724 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1725 | if (IS_I830(dev) && | |
1726 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && | |
1727 | !intel_num_dvo_pipes(dev)) { | |
1728 | I915_WRITE(DPLL(PIPE_B), | |
1729 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1730 | I915_WRITE(DPLL(PIPE_A), | |
1731 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1732 | } | |
1733 | ||
1734 | /* Don't disable pipe or pipe PLLs if needed */ | |
1735 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1736 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
1737 | return; | |
1738 | ||
1739 | /* Make sure the pipe isn't still relying on us */ | |
1740 | assert_pipe_disabled(dev_priv, pipe); | |
1741 | ||
1742 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); | |
1743 | POSTING_READ(DPLL(pipe)); | |
1744 | } | |
1745 | ||
1746 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1747 | { | |
1748 | u32 val; | |
1749 | ||
1750 | /* Make sure the pipe isn't still relying on us */ | |
1751 | assert_pipe_disabled(dev_priv, pipe); | |
1752 | ||
1753 | val = DPLL_INTEGRATED_REF_CLK_VLV | | |
1754 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1755 | if (pipe != PIPE_A) | |
1756 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1757 | ||
1758 | I915_WRITE(DPLL(pipe), val); | |
1759 | POSTING_READ(DPLL(pipe)); | |
1760 | } | |
1761 | ||
1762 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1763 | { | |
1764 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
1765 | u32 val; | |
1766 | ||
1767 | /* Make sure the pipe isn't still relying on us */ | |
1768 | assert_pipe_disabled(dev_priv, pipe); | |
1769 | ||
1770 | val = DPLL_SSC_REF_CLK_CHV | | |
1771 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1772 | if (pipe != PIPE_A) | |
1773 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1774 | ||
1775 | I915_WRITE(DPLL(pipe), val); | |
1776 | POSTING_READ(DPLL(pipe)); | |
1777 | ||
1778 | mutex_lock(&dev_priv->sb_lock); | |
1779 | ||
1780 | /* Disable 10bit clock to display controller */ | |
1781 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1782 | val &= ~DPIO_DCLKP_EN; | |
1783 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1784 | ||
1785 | mutex_unlock(&dev_priv->sb_lock); | |
1786 | } | |
1787 | ||
1788 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, | |
1789 | struct intel_digital_port *dport, | |
1790 | unsigned int expected_mask) | |
1791 | { | |
1792 | u32 port_mask; | |
1793 | i915_reg_t dpll_reg; | |
1794 | ||
1795 | switch (dport->port) { | |
1796 | case PORT_B: | |
1797 | port_mask = DPLL_PORTB_READY_MASK; | |
1798 | dpll_reg = DPLL(0); | |
1799 | break; | |
1800 | case PORT_C: | |
1801 | port_mask = DPLL_PORTC_READY_MASK; | |
1802 | dpll_reg = DPLL(0); | |
1803 | expected_mask <<= 4; | |
1804 | break; | |
1805 | case PORT_D: | |
1806 | port_mask = DPLL_PORTD_READY_MASK; | |
1807 | dpll_reg = DPIO_PHY_STATUS; | |
1808 | break; | |
1809 | default: | |
1810 | BUG(); | |
1811 | } | |
1812 | ||
1813 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) | |
1814 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1815 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
1816 | } | |
1817 | ||
1818 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, | |
1819 | enum pipe pipe) | |
1820 | { | |
1821 | struct drm_device *dev = dev_priv->dev; | |
1822 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1823 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1824 | i915_reg_t reg; | |
1825 | uint32_t val, pipeconf_val; | |
1826 | ||
1827 | /* Make sure PCH DPLL is enabled */ | |
1828 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); | |
1829 | ||
1830 | /* FDI must be feeding us bits for PCH ports */ | |
1831 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1832 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1833 | ||
1834 | if (HAS_PCH_CPT(dev)) { | |
1835 | /* Workaround: Set the timing override bit before enabling the | |
1836 | * pch transcoder. */ | |
1837 | reg = TRANS_CHICKEN2(pipe); | |
1838 | val = I915_READ(reg); | |
1839 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1840 | I915_WRITE(reg, val); | |
1841 | } | |
1842 | ||
1843 | reg = PCH_TRANSCONF(pipe); | |
1844 | val = I915_READ(reg); | |
1845 | pipeconf_val = I915_READ(PIPECONF(pipe)); | |
1846 | ||
1847 | if (HAS_PCH_IBX(dev_priv)) { | |
1848 | /* | |
1849 | * Make the BPC in transcoder be consistent with | |
1850 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1851 | * here for both 8bpc and 12bpc. | |
1852 | */ | |
1853 | val &= ~PIPECONF_BPC_MASK; | |
1854 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) | |
1855 | val |= PIPECONF_8BPC; | |
1856 | else | |
1857 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
1858 | } | |
1859 | ||
1860 | val &= ~TRANS_INTERLACE_MASK; | |
1861 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
1862 | if (HAS_PCH_IBX(dev_priv) && | |
1863 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) | |
1864 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1865 | else | |
1866 | val |= TRANS_INTERLACED; | |
1867 | else | |
1868 | val |= TRANS_PROGRESSIVE; | |
1869 | ||
1870 | I915_WRITE(reg, val | TRANS_ENABLE); | |
1871 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
1872 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); | |
1873 | } | |
1874 | ||
1875 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, | |
1876 | enum transcoder cpu_transcoder) | |
1877 | { | |
1878 | u32 val, pipeconf_val; | |
1879 | ||
1880 | /* FDI must be feeding us bits for PCH ports */ | |
1881 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); | |
1882 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); | |
1883 | ||
1884 | /* Workaround: set timing override bit. */ | |
1885 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); | |
1886 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1887 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); | |
1888 | ||
1889 | val = TRANS_ENABLE; | |
1890 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); | |
1891 | ||
1892 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == | |
1893 | PIPECONF_INTERLACED_ILK) | |
1894 | val |= TRANS_INTERLACED; | |
1895 | else | |
1896 | val |= TRANS_PROGRESSIVE; | |
1897 | ||
1898 | I915_WRITE(LPT_TRANSCONF, val); | |
1899 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
1900 | DRM_ERROR("Failed to enable PCH transcoder\n"); | |
1901 | } | |
1902 | ||
1903 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, | |
1904 | enum pipe pipe) | |
1905 | { | |
1906 | struct drm_device *dev = dev_priv->dev; | |
1907 | i915_reg_t reg; | |
1908 | uint32_t val; | |
1909 | ||
1910 | /* FDI relies on the transcoder */ | |
1911 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1912 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1913 | ||
1914 | /* Ports must be off as well */ | |
1915 | assert_pch_ports_disabled(dev_priv, pipe); | |
1916 | ||
1917 | reg = PCH_TRANSCONF(pipe); | |
1918 | val = I915_READ(reg); | |
1919 | val &= ~TRANS_ENABLE; | |
1920 | I915_WRITE(reg, val); | |
1921 | /* wait for PCH transcoder off, transcoder state */ | |
1922 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
1923 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); | |
1924 | ||
1925 | if (HAS_PCH_CPT(dev)) { | |
1926 | /* Workaround: Clear the timing override chicken bit again. */ | |
1927 | reg = TRANS_CHICKEN2(pipe); | |
1928 | val = I915_READ(reg); | |
1929 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1930 | I915_WRITE(reg, val); | |
1931 | } | |
1932 | } | |
1933 | ||
1934 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) | |
1935 | { | |
1936 | u32 val; | |
1937 | ||
1938 | val = I915_READ(LPT_TRANSCONF); | |
1939 | val &= ~TRANS_ENABLE; | |
1940 | I915_WRITE(LPT_TRANSCONF, val); | |
1941 | /* wait for PCH transcoder off, transcoder state */ | |
1942 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) | |
1943 | DRM_ERROR("Failed to disable PCH transcoder\n"); | |
1944 | ||
1945 | /* Workaround: clear timing override bit. */ | |
1946 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); | |
1947 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1948 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); | |
1949 | } | |
1950 | ||
1951 | /** | |
1952 | * intel_enable_pipe - enable a pipe, asserting requirements | |
1953 | * @crtc: crtc responsible for the pipe | |
1954 | * | |
1955 | * Enable @crtc's pipe, making sure that various hardware specific requirements | |
1956 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. | |
1957 | */ | |
1958 | static void intel_enable_pipe(struct intel_crtc *crtc) | |
1959 | { | |
1960 | struct drm_device *dev = crtc->base.dev; | |
1961 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1962 | enum pipe pipe = crtc->pipe; | |
1963 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; | |
1964 | enum pipe pch_transcoder; | |
1965 | i915_reg_t reg; | |
1966 | u32 val; | |
1967 | ||
1968 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); | |
1969 | ||
1970 | assert_planes_disabled(dev_priv, pipe); | |
1971 | assert_cursor_disabled(dev_priv, pipe); | |
1972 | assert_sprites_disabled(dev_priv, pipe); | |
1973 | ||
1974 | if (HAS_PCH_LPT(dev_priv)) | |
1975 | pch_transcoder = TRANSCODER_A; | |
1976 | else | |
1977 | pch_transcoder = pipe; | |
1978 | ||
1979 | /* | |
1980 | * A pipe without a PLL won't actually be able to drive bits from | |
1981 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1982 | * need the check. | |
1983 | */ | |
1984 | if (HAS_GMCH_DISPLAY(dev_priv)) | |
1985 | if (crtc->config->has_dsi_encoder) | |
1986 | assert_dsi_pll_enabled(dev_priv); | |
1987 | else | |
1988 | assert_pll_enabled(dev_priv, pipe); | |
1989 | else { | |
1990 | if (crtc->config->has_pch_encoder) { | |
1991 | /* if driving the PCH, we need FDI enabled */ | |
1992 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); | |
1993 | assert_fdi_tx_pll_enabled(dev_priv, | |
1994 | (enum pipe) cpu_transcoder); | |
1995 | } | |
1996 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1997 | } | |
1998 | ||
1999 | reg = PIPECONF(cpu_transcoder); | |
2000 | val = I915_READ(reg); | |
2001 | if (val & PIPECONF_ENABLE) { | |
2002 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
2003 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
2004 | return; | |
2005 | } | |
2006 | ||
2007 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
2008 | POSTING_READ(reg); | |
2009 | ||
2010 | /* | |
2011 | * Until the pipe starts DSL will read as 0, which would cause | |
2012 | * an apparent vblank timestamp jump, which messes up also the | |
2013 | * frame count when it's derived from the timestamps. So let's | |
2014 | * wait for the pipe to start properly before we call | |
2015 | * drm_crtc_vblank_on() | |
2016 | */ | |
2017 | if (dev->max_vblank_count == 0 && | |
2018 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
2019 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
2020 | } | |
2021 | ||
2022 | /** | |
2023 | * intel_disable_pipe - disable a pipe, asserting requirements | |
2024 | * @crtc: crtc whose pipes is to be disabled | |
2025 | * | |
2026 | * Disable the pipe of @crtc, making sure that various hardware | |
2027 | * specific requirements are met, if applicable, e.g. plane | |
2028 | * disabled, panel fitter off, etc. | |
2029 | * | |
2030 | * Will wait until the pipe has shut down before returning. | |
2031 | */ | |
2032 | static void intel_disable_pipe(struct intel_crtc *crtc) | |
2033 | { | |
2034 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
2035 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; | |
2036 | enum pipe pipe = crtc->pipe; | |
2037 | i915_reg_t reg; | |
2038 | u32 val; | |
2039 | ||
2040 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); | |
2041 | ||
2042 | /* | |
2043 | * Make sure planes won't keep trying to pump pixels to us, | |
2044 | * or we might hang the display. | |
2045 | */ | |
2046 | assert_planes_disabled(dev_priv, pipe); | |
2047 | assert_cursor_disabled(dev_priv, pipe); | |
2048 | assert_sprites_disabled(dev_priv, pipe); | |
2049 | ||
2050 | reg = PIPECONF(cpu_transcoder); | |
2051 | val = I915_READ(reg); | |
2052 | if ((val & PIPECONF_ENABLE) == 0) | |
2053 | return; | |
2054 | ||
2055 | /* | |
2056 | * Double wide has implications for planes | |
2057 | * so best keep it disabled when not needed. | |
2058 | */ | |
2059 | if (crtc->config->double_wide) | |
2060 | val &= ~PIPECONF_DOUBLE_WIDE; | |
2061 | ||
2062 | /* Don't disable pipe or pipe PLLs if needed */ | |
2063 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && | |
2064 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
2065 | val &= ~PIPECONF_ENABLE; | |
2066 | ||
2067 | I915_WRITE(reg, val); | |
2068 | if ((val & PIPECONF_ENABLE) == 0) | |
2069 | intel_wait_for_pipe_off(crtc); | |
2070 | } | |
2071 | ||
2072 | static bool need_vtd_wa(struct drm_device *dev) | |
2073 | { | |
2074 | #ifdef CONFIG_INTEL_IOMMU | |
2075 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2076 | return true; | |
2077 | #endif | |
2078 | return false; | |
2079 | } | |
2080 | ||
2081 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) | |
2082 | { | |
2083 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2084 | } | |
2085 | ||
2086 | static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv, | |
2087 | uint64_t fb_modifier, unsigned int cpp) | |
2088 | { | |
2089 | switch (fb_modifier) { | |
2090 | case DRM_FORMAT_MOD_NONE: | |
2091 | return cpp; | |
2092 | case I915_FORMAT_MOD_X_TILED: | |
2093 | if (IS_GEN2(dev_priv)) | |
2094 | return 128; | |
2095 | else | |
2096 | return 512; | |
2097 | case I915_FORMAT_MOD_Y_TILED: | |
2098 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2099 | return 128; | |
2100 | else | |
2101 | return 512; | |
2102 | case I915_FORMAT_MOD_Yf_TILED: | |
2103 | switch (cpp) { | |
2104 | case 1: | |
2105 | return 64; | |
2106 | case 2: | |
2107 | case 4: | |
2108 | return 128; | |
2109 | case 8: | |
2110 | case 16: | |
2111 | return 256; | |
2112 | default: | |
2113 | MISSING_CASE(cpp); | |
2114 | return cpp; | |
2115 | } | |
2116 | break; | |
2117 | default: | |
2118 | MISSING_CASE(fb_modifier); | |
2119 | return cpp; | |
2120 | } | |
2121 | } | |
2122 | ||
2123 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, | |
2124 | uint64_t fb_modifier, unsigned int cpp) | |
2125 | { | |
2126 | if (fb_modifier == DRM_FORMAT_MOD_NONE) | |
2127 | return 1; | |
2128 | else | |
2129 | return intel_tile_size(dev_priv) / | |
2130 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); | |
2131 | } | |
2132 | ||
2133 | /* Return the tile dimensions in pixel units */ | |
2134 | static void intel_tile_dims(const struct drm_i915_private *dev_priv, | |
2135 | unsigned int *tile_width, | |
2136 | unsigned int *tile_height, | |
2137 | uint64_t fb_modifier, | |
2138 | unsigned int cpp) | |
2139 | { | |
2140 | unsigned int tile_width_bytes = | |
2141 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); | |
2142 | ||
2143 | *tile_width = tile_width_bytes / cpp; | |
2144 | *tile_height = intel_tile_size(dev_priv) / tile_width_bytes; | |
2145 | } | |
2146 | ||
2147 | unsigned int | |
2148 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
2149 | uint32_t pixel_format, uint64_t fb_modifier) | |
2150 | { | |
2151 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); | |
2152 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2153 | ||
2154 | return ALIGN(height, tile_height); | |
2155 | } | |
2156 | ||
2157 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) | |
2158 | { | |
2159 | unsigned int size = 0; | |
2160 | int i; | |
2161 | ||
2162 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2163 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2164 | ||
2165 | return size; | |
2166 | } | |
2167 | ||
2168 | static void | |
2169 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, | |
2170 | const struct drm_framebuffer *fb, | |
2171 | unsigned int rotation) | |
2172 | { | |
2173 | if (intel_rotation_90_or_270(rotation)) { | |
2174 | *view = i915_ggtt_view_rotated; | |
2175 | view->params.rotated = to_intel_framebuffer(fb)->rot_info; | |
2176 | } else { | |
2177 | *view = i915_ggtt_view_normal; | |
2178 | } | |
2179 | } | |
2180 | ||
2181 | static void | |
2182 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2183 | struct drm_framebuffer *fb) | |
2184 | { | |
2185 | struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info; | |
2186 | unsigned int tile_size, tile_width, tile_height, cpp; | |
2187 | ||
2188 | tile_size = intel_tile_size(dev_priv); | |
2189 | ||
2190 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
2191 | intel_tile_dims(dev_priv, &tile_width, &tile_height, | |
2192 | fb->modifier[0], cpp); | |
2193 | ||
2194 | info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp); | |
2195 | info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height); | |
2196 | ||
2197 | if (info->pixel_format == DRM_FORMAT_NV12) { | |
2198 | cpp = drm_format_plane_cpp(fb->pixel_format, 1); | |
2199 | intel_tile_dims(dev_priv, &tile_width, &tile_height, | |
2200 | fb->modifier[1], cpp); | |
2201 | ||
2202 | info->uv_offset = fb->offsets[1]; | |
2203 | info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp); | |
2204 | info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height); | |
2205 | } | |
2206 | } | |
2207 | ||
2208 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) | |
2209 | { | |
2210 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2211 | return 256 * 1024; | |
2212 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || | |
2213 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
2214 | return 128 * 1024; | |
2215 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2216 | return 4 * 1024; | |
2217 | else | |
2218 | return 0; | |
2219 | } | |
2220 | ||
2221 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, | |
2222 | uint64_t fb_modifier) | |
2223 | { | |
2224 | switch (fb_modifier) { | |
2225 | case DRM_FORMAT_MOD_NONE: | |
2226 | return intel_linear_alignment(dev_priv); | |
2227 | case I915_FORMAT_MOD_X_TILED: | |
2228 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2229 | return 256 * 1024; | |
2230 | return 0; | |
2231 | case I915_FORMAT_MOD_Y_TILED: | |
2232 | case I915_FORMAT_MOD_Yf_TILED: | |
2233 | return 1 * 1024 * 1024; | |
2234 | default: | |
2235 | MISSING_CASE(fb_modifier); | |
2236 | return 0; | |
2237 | } | |
2238 | } | |
2239 | ||
2240 | int | |
2241 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, | |
2242 | unsigned int rotation) | |
2243 | { | |
2244 | struct drm_device *dev = fb->dev; | |
2245 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2246 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2247 | struct i915_ggtt_view view; | |
2248 | u32 alignment; | |
2249 | int ret; | |
2250 | ||
2251 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
2252 | ||
2253 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); | |
2254 | ||
2255 | intel_fill_fb_ggtt_view(&view, fb, rotation); | |
2256 | ||
2257 | /* Note that the w/a also requires 64 PTE of padding following the | |
2258 | * bo. We currently fill all unused PTE with the shadow page and so | |
2259 | * we should always have valid PTE following the scanout preventing | |
2260 | * the VT-d warning. | |
2261 | */ | |
2262 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2263 | alignment = 256 * 1024; | |
2264 | ||
2265 | /* | |
2266 | * Global gtt pte registers are special registers which actually forward | |
2267 | * writes to a chunk of system memory. Which means that there is no risk | |
2268 | * that the register values disappear as soon as we call | |
2269 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2270 | * pin/unpin/fence and not more. | |
2271 | */ | |
2272 | intel_runtime_pm_get(dev_priv); | |
2273 | ||
2274 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, | |
2275 | &view); | |
2276 | if (ret) | |
2277 | goto err_pm; | |
2278 | ||
2279 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2280 | * fence, whereas 965+ only requires a fence if using | |
2281 | * framebuffer compression. For simplicity, we always install | |
2282 | * a fence as the cost is not that onerous. | |
2283 | */ | |
2284 | if (view.type == I915_GGTT_VIEW_NORMAL) { | |
2285 | ret = i915_gem_object_get_fence(obj); | |
2286 | if (ret == -EDEADLK) { | |
2287 | /* | |
2288 | * -EDEADLK means there are no free fences | |
2289 | * no pending flips. | |
2290 | * | |
2291 | * This is propagated to atomic, but it uses | |
2292 | * -EDEADLK to force a locking recovery, so | |
2293 | * change the returned error to -EBUSY. | |
2294 | */ | |
2295 | ret = -EBUSY; | |
2296 | goto err_unpin; | |
2297 | } else if (ret) | |
2298 | goto err_unpin; | |
2299 | ||
2300 | i915_gem_object_pin_fence(obj); | |
2301 | } | |
2302 | ||
2303 | intel_runtime_pm_put(dev_priv); | |
2304 | return 0; | |
2305 | ||
2306 | err_unpin: | |
2307 | i915_gem_object_unpin_from_display_plane(obj, &view); | |
2308 | err_pm: | |
2309 | intel_runtime_pm_put(dev_priv); | |
2310 | return ret; | |
2311 | } | |
2312 | ||
2313 | void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) | |
2314 | { | |
2315 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2316 | struct i915_ggtt_view view; | |
2317 | ||
2318 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); | |
2319 | ||
2320 | intel_fill_fb_ggtt_view(&view, fb, rotation); | |
2321 | ||
2322 | if (view.type == I915_GGTT_VIEW_NORMAL) | |
2323 | i915_gem_object_unpin_fence(obj); | |
2324 | ||
2325 | i915_gem_object_unpin_from_display_plane(obj, &view); | |
2326 | } | |
2327 | ||
2328 | /* | |
2329 | * Adjust the tile offset by moving the difference into | |
2330 | * the x/y offsets. | |
2331 | * | |
2332 | * Input tile dimensions and pitch must already be | |
2333 | * rotated to match x and y, and in pixel units. | |
2334 | */ | |
2335 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2336 | unsigned int tile_width, | |
2337 | unsigned int tile_height, | |
2338 | unsigned int tile_size, | |
2339 | unsigned int pitch_tiles, | |
2340 | u32 old_offset, | |
2341 | u32 new_offset) | |
2342 | { | |
2343 | unsigned int tiles; | |
2344 | ||
2345 | WARN_ON(old_offset & (tile_size - 1)); | |
2346 | WARN_ON(new_offset & (tile_size - 1)); | |
2347 | WARN_ON(new_offset > old_offset); | |
2348 | ||
2349 | tiles = (old_offset - new_offset) / tile_size; | |
2350 | ||
2351 | *y += tiles / pitch_tiles * tile_height; | |
2352 | *x += tiles % pitch_tiles * tile_width; | |
2353 | ||
2354 | return new_offset; | |
2355 | } | |
2356 | ||
2357 | /* | |
2358 | * Computes the linear offset to the base tile and adjusts | |
2359 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2360 | * | |
2361 | * In the 90/270 rotated case, x and y are assumed | |
2362 | * to be already rotated to match the rotated GTT view, and | |
2363 | * pitch is the tile_height aligned framebuffer height. | |
2364 | */ | |
2365 | u32 intel_compute_tile_offset(int *x, int *y, | |
2366 | const struct drm_framebuffer *fb, int plane, | |
2367 | unsigned int pitch, | |
2368 | unsigned int rotation) | |
2369 | { | |
2370 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); | |
2371 | uint64_t fb_modifier = fb->modifier[plane]; | |
2372 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
2373 | u32 offset, offset_aligned, alignment; | |
2374 | ||
2375 | alignment = intel_surf_alignment(dev_priv, fb_modifier); | |
2376 | if (alignment) | |
2377 | alignment--; | |
2378 | ||
2379 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { | |
2380 | unsigned int tile_size, tile_width, tile_height; | |
2381 | unsigned int tile_rows, tiles, pitch_tiles; | |
2382 | ||
2383 | tile_size = intel_tile_size(dev_priv); | |
2384 | intel_tile_dims(dev_priv, &tile_width, &tile_height, | |
2385 | fb_modifier, cpp); | |
2386 | ||
2387 | if (intel_rotation_90_or_270(rotation)) { | |
2388 | pitch_tiles = pitch / tile_height; | |
2389 | swap(tile_width, tile_height); | |
2390 | } else { | |
2391 | pitch_tiles = pitch / (tile_width * cpp); | |
2392 | } | |
2393 | ||
2394 | tile_rows = *y / tile_height; | |
2395 | *y %= tile_height; | |
2396 | ||
2397 | tiles = *x / tile_width; | |
2398 | *x %= tile_width; | |
2399 | ||
2400 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; | |
2401 | offset_aligned = offset & ~alignment; | |
2402 | ||
2403 | intel_adjust_tile_offset(x, y, tile_width, tile_height, | |
2404 | tile_size, pitch_tiles, | |
2405 | offset, offset_aligned); | |
2406 | } else { | |
2407 | offset = *y * pitch + *x * cpp; | |
2408 | offset_aligned = offset & ~alignment; | |
2409 | ||
2410 | *y = (offset & alignment) / pitch; | |
2411 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
2412 | } | |
2413 | ||
2414 | return offset_aligned; | |
2415 | } | |
2416 | ||
2417 | static int i9xx_format_to_fourcc(int format) | |
2418 | { | |
2419 | switch (format) { | |
2420 | case DISPPLANE_8BPP: | |
2421 | return DRM_FORMAT_C8; | |
2422 | case DISPPLANE_BGRX555: | |
2423 | return DRM_FORMAT_XRGB1555; | |
2424 | case DISPPLANE_BGRX565: | |
2425 | return DRM_FORMAT_RGB565; | |
2426 | default: | |
2427 | case DISPPLANE_BGRX888: | |
2428 | return DRM_FORMAT_XRGB8888; | |
2429 | case DISPPLANE_RGBX888: | |
2430 | return DRM_FORMAT_XBGR8888; | |
2431 | case DISPPLANE_BGRX101010: | |
2432 | return DRM_FORMAT_XRGB2101010; | |
2433 | case DISPPLANE_RGBX101010: | |
2434 | return DRM_FORMAT_XBGR2101010; | |
2435 | } | |
2436 | } | |
2437 | ||
2438 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) | |
2439 | { | |
2440 | switch (format) { | |
2441 | case PLANE_CTL_FORMAT_RGB_565: | |
2442 | return DRM_FORMAT_RGB565; | |
2443 | default: | |
2444 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2445 | if (rgb_order) { | |
2446 | if (alpha) | |
2447 | return DRM_FORMAT_ABGR8888; | |
2448 | else | |
2449 | return DRM_FORMAT_XBGR8888; | |
2450 | } else { | |
2451 | if (alpha) | |
2452 | return DRM_FORMAT_ARGB8888; | |
2453 | else | |
2454 | return DRM_FORMAT_XRGB8888; | |
2455 | } | |
2456 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2457 | if (rgb_order) | |
2458 | return DRM_FORMAT_XBGR2101010; | |
2459 | else | |
2460 | return DRM_FORMAT_XRGB2101010; | |
2461 | } | |
2462 | } | |
2463 | ||
2464 | static bool | |
2465 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, | |
2466 | struct intel_initial_plane_config *plane_config) | |
2467 | { | |
2468 | struct drm_device *dev = crtc->base.dev; | |
2469 | struct drm_i915_private *dev_priv = to_i915(dev); | |
2470 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
2471 | struct drm_i915_gem_object *obj = NULL; | |
2472 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2473 | struct drm_framebuffer *fb = &plane_config->fb->base; | |
2474 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); | |
2475 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2476 | PAGE_SIZE); | |
2477 | ||
2478 | size_aligned -= base_aligned; | |
2479 | ||
2480 | if (plane_config->size == 0) | |
2481 | return false; | |
2482 | ||
2483 | /* If the FB is too big, just don't use it since fbdev is not very | |
2484 | * important and we should probably use that space with FBC or other | |
2485 | * features. */ | |
2486 | if (size_aligned * 2 > ggtt->stolen_usable_size) | |
2487 | return false; | |
2488 | ||
2489 | mutex_lock(&dev->struct_mutex); | |
2490 | ||
2491 | obj = i915_gem_object_create_stolen_for_preallocated(dev, | |
2492 | base_aligned, | |
2493 | base_aligned, | |
2494 | size_aligned); | |
2495 | if (!obj) { | |
2496 | mutex_unlock(&dev->struct_mutex); | |
2497 | return false; | |
2498 | } | |
2499 | ||
2500 | obj->tiling_mode = plane_config->tiling; | |
2501 | if (obj->tiling_mode == I915_TILING_X) | |
2502 | obj->stride = fb->pitches[0]; | |
2503 | ||
2504 | mode_cmd.pixel_format = fb->pixel_format; | |
2505 | mode_cmd.width = fb->width; | |
2506 | mode_cmd.height = fb->height; | |
2507 | mode_cmd.pitches[0] = fb->pitches[0]; | |
2508 | mode_cmd.modifier[0] = fb->modifier[0]; | |
2509 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
2510 | ||
2511 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), | |
2512 | &mode_cmd, obj)) { | |
2513 | DRM_DEBUG_KMS("intel fb init failed\n"); | |
2514 | goto out_unref_obj; | |
2515 | } | |
2516 | ||
2517 | mutex_unlock(&dev->struct_mutex); | |
2518 | ||
2519 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); | |
2520 | return true; | |
2521 | ||
2522 | out_unref_obj: | |
2523 | drm_gem_object_unreference(&obj->base); | |
2524 | mutex_unlock(&dev->struct_mutex); | |
2525 | return false; | |
2526 | } | |
2527 | ||
2528 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ | |
2529 | static void | |
2530 | update_state_fb(struct drm_plane *plane) | |
2531 | { | |
2532 | if (plane->fb == plane->state->fb) | |
2533 | return; | |
2534 | ||
2535 | if (plane->state->fb) | |
2536 | drm_framebuffer_unreference(plane->state->fb); | |
2537 | plane->state->fb = plane->fb; | |
2538 | if (plane->state->fb) | |
2539 | drm_framebuffer_reference(plane->state->fb); | |
2540 | } | |
2541 | ||
2542 | static void | |
2543 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, | |
2544 | struct intel_initial_plane_config *plane_config) | |
2545 | { | |
2546 | struct drm_device *dev = intel_crtc->base.dev; | |
2547 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2548 | struct drm_crtc *c; | |
2549 | struct intel_crtc *i; | |
2550 | struct drm_i915_gem_object *obj; | |
2551 | struct drm_plane *primary = intel_crtc->base.primary; | |
2552 | struct drm_plane_state *plane_state = primary->state; | |
2553 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; | |
2554 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
2555 | struct intel_plane_state *intel_state = | |
2556 | to_intel_plane_state(plane_state); | |
2557 | struct drm_framebuffer *fb; | |
2558 | ||
2559 | if (!plane_config->fb) | |
2560 | return; | |
2561 | ||
2562 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { | |
2563 | fb = &plane_config->fb->base; | |
2564 | goto valid_fb; | |
2565 | } | |
2566 | ||
2567 | kfree(plane_config->fb); | |
2568 | ||
2569 | /* | |
2570 | * Failed to alloc the obj, check to see if we should share | |
2571 | * an fb with another CRTC instead | |
2572 | */ | |
2573 | for_each_crtc(dev, c) { | |
2574 | i = to_intel_crtc(c); | |
2575 | ||
2576 | if (c == &intel_crtc->base) | |
2577 | continue; | |
2578 | ||
2579 | if (!i->active) | |
2580 | continue; | |
2581 | ||
2582 | fb = c->primary->fb; | |
2583 | if (!fb) | |
2584 | continue; | |
2585 | ||
2586 | obj = intel_fb_obj(fb); | |
2587 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { | |
2588 | drm_framebuffer_reference(fb); | |
2589 | goto valid_fb; | |
2590 | } | |
2591 | } | |
2592 | ||
2593 | /* | |
2594 | * We've failed to reconstruct the BIOS FB. Current display state | |
2595 | * indicates that the primary plane is visible, but has a NULL FB, | |
2596 | * which will lead to problems later if we don't fix it up. The | |
2597 | * simplest solution is to just disable the primary plane now and | |
2598 | * pretend the BIOS never had it enabled. | |
2599 | */ | |
2600 | to_intel_plane_state(plane_state)->visible = false; | |
2601 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); | |
2602 | intel_pre_disable_primary_noatomic(&intel_crtc->base); | |
2603 | intel_plane->disable_plane(primary, &intel_crtc->base); | |
2604 | ||
2605 | return; | |
2606 | ||
2607 | valid_fb: | |
2608 | plane_state->src_x = 0; | |
2609 | plane_state->src_y = 0; | |
2610 | plane_state->src_w = fb->width << 16; | |
2611 | plane_state->src_h = fb->height << 16; | |
2612 | ||
2613 | plane_state->crtc_x = 0; | |
2614 | plane_state->crtc_y = 0; | |
2615 | plane_state->crtc_w = fb->width; | |
2616 | plane_state->crtc_h = fb->height; | |
2617 | ||
2618 | intel_state->src.x1 = plane_state->src_x; | |
2619 | intel_state->src.y1 = plane_state->src_y; | |
2620 | intel_state->src.x2 = plane_state->src_x + plane_state->src_w; | |
2621 | intel_state->src.y2 = plane_state->src_y + plane_state->src_h; | |
2622 | intel_state->dst.x1 = plane_state->crtc_x; | |
2623 | intel_state->dst.y1 = plane_state->crtc_y; | |
2624 | intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w; | |
2625 | intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h; | |
2626 | ||
2627 | obj = intel_fb_obj(fb); | |
2628 | if (obj->tiling_mode != I915_TILING_NONE) | |
2629 | dev_priv->preserve_bios_swizzle = true; | |
2630 | ||
2631 | drm_framebuffer_reference(fb); | |
2632 | primary->fb = primary->state->fb = fb; | |
2633 | primary->crtc = primary->state->crtc = &intel_crtc->base; | |
2634 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); | |
2635 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; | |
2636 | } | |
2637 | ||
2638 | static void i9xx_update_primary_plane(struct drm_plane *primary, | |
2639 | const struct intel_crtc_state *crtc_state, | |
2640 | const struct intel_plane_state *plane_state) | |
2641 | { | |
2642 | struct drm_device *dev = primary->dev; | |
2643 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2644 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
2645 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2646 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2647 | int plane = intel_crtc->plane; | |
2648 | u32 linear_offset; | |
2649 | u32 dspcntr; | |
2650 | i915_reg_t reg = DSPCNTR(plane); | |
2651 | unsigned int rotation = plane_state->base.rotation; | |
2652 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
2653 | int x = plane_state->src.x1 >> 16; | |
2654 | int y = plane_state->src.y1 >> 16; | |
2655 | ||
2656 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
2657 | ||
2658 | dspcntr |= DISPLAY_PLANE_ENABLE; | |
2659 | ||
2660 | if (INTEL_INFO(dev)->gen < 4) { | |
2661 | if (intel_crtc->pipe == PIPE_B) | |
2662 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2663 | ||
2664 | /* pipesrc and dspsize control the size that is scaled from, | |
2665 | * which should always be the user's requested size. | |
2666 | */ | |
2667 | I915_WRITE(DSPSIZE(plane), | |
2668 | ((crtc_state->pipe_src_h - 1) << 16) | | |
2669 | (crtc_state->pipe_src_w - 1)); | |
2670 | I915_WRITE(DSPPOS(plane), 0); | |
2671 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { | |
2672 | I915_WRITE(PRIMSIZE(plane), | |
2673 | ((crtc_state->pipe_src_h - 1) << 16) | | |
2674 | (crtc_state->pipe_src_w - 1)); | |
2675 | I915_WRITE(PRIMPOS(plane), 0); | |
2676 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
2677 | } | |
2678 | ||
2679 | switch (fb->pixel_format) { | |
2680 | case DRM_FORMAT_C8: | |
2681 | dspcntr |= DISPPLANE_8BPP; | |
2682 | break; | |
2683 | case DRM_FORMAT_XRGB1555: | |
2684 | dspcntr |= DISPPLANE_BGRX555; | |
2685 | break; | |
2686 | case DRM_FORMAT_RGB565: | |
2687 | dspcntr |= DISPPLANE_BGRX565; | |
2688 | break; | |
2689 | case DRM_FORMAT_XRGB8888: | |
2690 | dspcntr |= DISPPLANE_BGRX888; | |
2691 | break; | |
2692 | case DRM_FORMAT_XBGR8888: | |
2693 | dspcntr |= DISPPLANE_RGBX888; | |
2694 | break; | |
2695 | case DRM_FORMAT_XRGB2101010: | |
2696 | dspcntr |= DISPPLANE_BGRX101010; | |
2697 | break; | |
2698 | case DRM_FORMAT_XBGR2101010: | |
2699 | dspcntr |= DISPPLANE_RGBX101010; | |
2700 | break; | |
2701 | default: | |
2702 | BUG(); | |
2703 | } | |
2704 | ||
2705 | if (INTEL_INFO(dev)->gen >= 4 && | |
2706 | obj->tiling_mode != I915_TILING_NONE) | |
2707 | dspcntr |= DISPPLANE_TILED; | |
2708 | ||
2709 | if (IS_G4X(dev)) | |
2710 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2711 | ||
2712 | linear_offset = y * fb->pitches[0] + x * cpp; | |
2713 | ||
2714 | if (INTEL_INFO(dev)->gen >= 4) { | |
2715 | intel_crtc->dspaddr_offset = | |
2716 | intel_compute_tile_offset(&x, &y, fb, 0, | |
2717 | fb->pitches[0], rotation); | |
2718 | linear_offset -= intel_crtc->dspaddr_offset; | |
2719 | } else { | |
2720 | intel_crtc->dspaddr_offset = linear_offset; | |
2721 | } | |
2722 | ||
2723 | if (rotation == BIT(DRM_ROTATE_180)) { | |
2724 | dspcntr |= DISPPLANE_ROTATE_180; | |
2725 | ||
2726 | x += (crtc_state->pipe_src_w - 1); | |
2727 | y += (crtc_state->pipe_src_h - 1); | |
2728 | ||
2729 | /* Finding the last pixel of the last line of the display | |
2730 | data and adding to linear_offset*/ | |
2731 | linear_offset += | |
2732 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + | |
2733 | (crtc_state->pipe_src_w - 1) * cpp; | |
2734 | } | |
2735 | ||
2736 | intel_crtc->adjusted_x = x; | |
2737 | intel_crtc->adjusted_y = y; | |
2738 | ||
2739 | I915_WRITE(reg, dspcntr); | |
2740 | ||
2741 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); | |
2742 | if (INTEL_INFO(dev)->gen >= 4) { | |
2743 | I915_WRITE(DSPSURF(plane), | |
2744 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
2745 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2746 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2747 | } else | |
2748 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); | |
2749 | POSTING_READ(reg); | |
2750 | } | |
2751 | ||
2752 | static void i9xx_disable_primary_plane(struct drm_plane *primary, | |
2753 | struct drm_crtc *crtc) | |
2754 | { | |
2755 | struct drm_device *dev = crtc->dev; | |
2756 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2757 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2758 | int plane = intel_crtc->plane; | |
2759 | ||
2760 | I915_WRITE(DSPCNTR(plane), 0); | |
2761 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
2762 | I915_WRITE(DSPSURF(plane), 0); | |
2763 | else | |
2764 | I915_WRITE(DSPADDR(plane), 0); | |
2765 | POSTING_READ(DSPCNTR(plane)); | |
2766 | } | |
2767 | ||
2768 | static void ironlake_update_primary_plane(struct drm_plane *primary, | |
2769 | const struct intel_crtc_state *crtc_state, | |
2770 | const struct intel_plane_state *plane_state) | |
2771 | { | |
2772 | struct drm_device *dev = primary->dev; | |
2773 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2774 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
2775 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2776 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2777 | int plane = intel_crtc->plane; | |
2778 | u32 linear_offset; | |
2779 | u32 dspcntr; | |
2780 | i915_reg_t reg = DSPCNTR(plane); | |
2781 | unsigned int rotation = plane_state->base.rotation; | |
2782 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
2783 | int x = plane_state->src.x1 >> 16; | |
2784 | int y = plane_state->src.y1 >> 16; | |
2785 | ||
2786 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
2787 | dspcntr |= DISPLAY_PLANE_ENABLE; | |
2788 | ||
2789 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2790 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
2791 | ||
2792 | switch (fb->pixel_format) { | |
2793 | case DRM_FORMAT_C8: | |
2794 | dspcntr |= DISPPLANE_8BPP; | |
2795 | break; | |
2796 | case DRM_FORMAT_RGB565: | |
2797 | dspcntr |= DISPPLANE_BGRX565; | |
2798 | break; | |
2799 | case DRM_FORMAT_XRGB8888: | |
2800 | dspcntr |= DISPPLANE_BGRX888; | |
2801 | break; | |
2802 | case DRM_FORMAT_XBGR8888: | |
2803 | dspcntr |= DISPPLANE_RGBX888; | |
2804 | break; | |
2805 | case DRM_FORMAT_XRGB2101010: | |
2806 | dspcntr |= DISPPLANE_BGRX101010; | |
2807 | break; | |
2808 | case DRM_FORMAT_XBGR2101010: | |
2809 | dspcntr |= DISPPLANE_RGBX101010; | |
2810 | break; | |
2811 | default: | |
2812 | BUG(); | |
2813 | } | |
2814 | ||
2815 | if (obj->tiling_mode != I915_TILING_NONE) | |
2816 | dspcntr |= DISPPLANE_TILED; | |
2817 | ||
2818 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) | |
2819 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2820 | ||
2821 | linear_offset = y * fb->pitches[0] + x * cpp; | |
2822 | intel_crtc->dspaddr_offset = | |
2823 | intel_compute_tile_offset(&x, &y, fb, 0, | |
2824 | fb->pitches[0], rotation); | |
2825 | linear_offset -= intel_crtc->dspaddr_offset; | |
2826 | if (rotation == BIT(DRM_ROTATE_180)) { | |
2827 | dspcntr |= DISPPLANE_ROTATE_180; | |
2828 | ||
2829 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
2830 | x += (crtc_state->pipe_src_w - 1); | |
2831 | y += (crtc_state->pipe_src_h - 1); | |
2832 | ||
2833 | /* Finding the last pixel of the last line of the display | |
2834 | data and adding to linear_offset*/ | |
2835 | linear_offset += | |
2836 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + | |
2837 | (crtc_state->pipe_src_w - 1) * cpp; | |
2838 | } | |
2839 | } | |
2840 | ||
2841 | intel_crtc->adjusted_x = x; | |
2842 | intel_crtc->adjusted_y = y; | |
2843 | ||
2844 | I915_WRITE(reg, dspcntr); | |
2845 | ||
2846 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); | |
2847 | I915_WRITE(DSPSURF(plane), | |
2848 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
2849 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
2850 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); | |
2851 | } else { | |
2852 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2853 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2854 | } | |
2855 | POSTING_READ(reg); | |
2856 | } | |
2857 | ||
2858 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, | |
2859 | uint64_t fb_modifier, uint32_t pixel_format) | |
2860 | { | |
2861 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { | |
2862 | return 64; | |
2863 | } else { | |
2864 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
2865 | ||
2866 | return intel_tile_width_bytes(dev_priv, fb_modifier, cpp); | |
2867 | } | |
2868 | } | |
2869 | ||
2870 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, | |
2871 | struct drm_i915_gem_object *obj, | |
2872 | unsigned int plane) | |
2873 | { | |
2874 | struct i915_ggtt_view view; | |
2875 | struct i915_vma *vma; | |
2876 | u64 offset; | |
2877 | ||
2878 | intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb, | |
2879 | intel_plane->base.state->rotation); | |
2880 | ||
2881 | vma = i915_gem_obj_to_ggtt_view(obj, &view); | |
2882 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", | |
2883 | view.type)) | |
2884 | return -1; | |
2885 | ||
2886 | offset = vma->node.start; | |
2887 | ||
2888 | if (plane == 1) { | |
2889 | offset += vma->ggtt_view.params.rotated.uv_start_page * | |
2890 | PAGE_SIZE; | |
2891 | } | |
2892 | ||
2893 | WARN_ON(upper_32_bits(offset)); | |
2894 | ||
2895 | return lower_32_bits(offset); | |
2896 | } | |
2897 | ||
2898 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) | |
2899 | { | |
2900 | struct drm_device *dev = intel_crtc->base.dev; | |
2901 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2902 | ||
2903 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2904 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2905 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
2906 | } | |
2907 | ||
2908 | /* | |
2909 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2910 | */ | |
2911 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) | |
2912 | { | |
2913 | struct intel_crtc_scaler_state *scaler_state; | |
2914 | int i; | |
2915 | ||
2916 | scaler_state = &intel_crtc->config->scaler_state; | |
2917 | ||
2918 | /* loop through and disable scalers that aren't in use */ | |
2919 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
2920 | if (!scaler_state->scalers[i].in_use) | |
2921 | skl_detach_scaler(intel_crtc, i); | |
2922 | } | |
2923 | } | |
2924 | ||
2925 | u32 skl_plane_ctl_format(uint32_t pixel_format) | |
2926 | { | |
2927 | switch (pixel_format) { | |
2928 | case DRM_FORMAT_C8: | |
2929 | return PLANE_CTL_FORMAT_INDEXED; | |
2930 | case DRM_FORMAT_RGB565: | |
2931 | return PLANE_CTL_FORMAT_RGB_565; | |
2932 | case DRM_FORMAT_XBGR8888: | |
2933 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; | |
2934 | case DRM_FORMAT_XRGB8888: | |
2935 | return PLANE_CTL_FORMAT_XRGB_8888; | |
2936 | /* | |
2937 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
2938 | * to be already pre-multiplied. We need to add a knob (or a different | |
2939 | * DRM_FORMAT) for user-space to configure that. | |
2940 | */ | |
2941 | case DRM_FORMAT_ABGR8888: | |
2942 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | | |
2943 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; | |
2944 | case DRM_FORMAT_ARGB8888: | |
2945 | return PLANE_CTL_FORMAT_XRGB_8888 | | |
2946 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; | |
2947 | case DRM_FORMAT_XRGB2101010: | |
2948 | return PLANE_CTL_FORMAT_XRGB_2101010; | |
2949 | case DRM_FORMAT_XBGR2101010: | |
2950 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; | |
2951 | case DRM_FORMAT_YUYV: | |
2952 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; | |
2953 | case DRM_FORMAT_YVYU: | |
2954 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; | |
2955 | case DRM_FORMAT_UYVY: | |
2956 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; | |
2957 | case DRM_FORMAT_VYUY: | |
2958 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; | |
2959 | default: | |
2960 | MISSING_CASE(pixel_format); | |
2961 | } | |
2962 | ||
2963 | return 0; | |
2964 | } | |
2965 | ||
2966 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) | |
2967 | { | |
2968 | switch (fb_modifier) { | |
2969 | case DRM_FORMAT_MOD_NONE: | |
2970 | break; | |
2971 | case I915_FORMAT_MOD_X_TILED: | |
2972 | return PLANE_CTL_TILED_X; | |
2973 | case I915_FORMAT_MOD_Y_TILED: | |
2974 | return PLANE_CTL_TILED_Y; | |
2975 | case I915_FORMAT_MOD_Yf_TILED: | |
2976 | return PLANE_CTL_TILED_YF; | |
2977 | default: | |
2978 | MISSING_CASE(fb_modifier); | |
2979 | } | |
2980 | ||
2981 | return 0; | |
2982 | } | |
2983 | ||
2984 | u32 skl_plane_ctl_rotation(unsigned int rotation) | |
2985 | { | |
2986 | switch (rotation) { | |
2987 | case BIT(DRM_ROTATE_0): | |
2988 | break; | |
2989 | /* | |
2990 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
2991 | * while i915 HW rotation is clockwise, thats why this swapping. | |
2992 | */ | |
2993 | case BIT(DRM_ROTATE_90): | |
2994 | return PLANE_CTL_ROTATE_270; | |
2995 | case BIT(DRM_ROTATE_180): | |
2996 | return PLANE_CTL_ROTATE_180; | |
2997 | case BIT(DRM_ROTATE_270): | |
2998 | return PLANE_CTL_ROTATE_90; | |
2999 | default: | |
3000 | MISSING_CASE(rotation); | |
3001 | } | |
3002 | ||
3003 | return 0; | |
3004 | } | |
3005 | ||
3006 | static void skylake_update_primary_plane(struct drm_plane *plane, | |
3007 | const struct intel_crtc_state *crtc_state, | |
3008 | const struct intel_plane_state *plane_state) | |
3009 | { | |
3010 | struct drm_device *dev = plane->dev; | |
3011 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3012 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
3013 | struct drm_framebuffer *fb = plane_state->base.fb; | |
3014 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
3015 | int pipe = intel_crtc->pipe; | |
3016 | u32 plane_ctl, stride_div, stride; | |
3017 | u32 tile_height, plane_offset, plane_size; | |
3018 | unsigned int rotation = plane_state->base.rotation; | |
3019 | int x_offset, y_offset; | |
3020 | u32 surf_addr; | |
3021 | int scaler_id = plane_state->scaler_id; | |
3022 | int src_x = plane_state->src.x1 >> 16; | |
3023 | int src_y = plane_state->src.y1 >> 16; | |
3024 | int src_w = drm_rect_width(&plane_state->src) >> 16; | |
3025 | int src_h = drm_rect_height(&plane_state->src) >> 16; | |
3026 | int dst_x = plane_state->dst.x1; | |
3027 | int dst_y = plane_state->dst.y1; | |
3028 | int dst_w = drm_rect_width(&plane_state->dst); | |
3029 | int dst_h = drm_rect_height(&plane_state->dst); | |
3030 | ||
3031 | plane_ctl = PLANE_CTL_ENABLE | | |
3032 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3033 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3034 | ||
3035 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3036 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3037 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3038 | plane_ctl |= skl_plane_ctl_rotation(rotation); | |
3039 | ||
3040 | stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], | |
3041 | fb->pixel_format); | |
3042 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); | |
3043 | ||
3044 | WARN_ON(drm_rect_width(&plane_state->src) == 0); | |
3045 | ||
3046 | if (intel_rotation_90_or_270(rotation)) { | |
3047 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
3048 | ||
3049 | /* stride = Surface height in tiles */ | |
3050 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp); | |
3051 | stride = DIV_ROUND_UP(fb->height, tile_height); | |
3052 | x_offset = stride * tile_height - src_y - src_h; | |
3053 | y_offset = src_x; | |
3054 | plane_size = (src_w - 1) << 16 | (src_h - 1); | |
3055 | } else { | |
3056 | stride = fb->pitches[0] / stride_div; | |
3057 | x_offset = src_x; | |
3058 | y_offset = src_y; | |
3059 | plane_size = (src_h - 1) << 16 | (src_w - 1); | |
3060 | } | |
3061 | plane_offset = y_offset << 16 | x_offset; | |
3062 | ||
3063 | intel_crtc->adjusted_x = x_offset; | |
3064 | intel_crtc->adjusted_y = y_offset; | |
3065 | ||
3066 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); | |
3067 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); | |
3068 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3069 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
3070 | ||
3071 | if (scaler_id >= 0) { | |
3072 | uint32_t ps_ctrl = 0; | |
3073 | ||
3074 | WARN_ON(!dst_w || !dst_h); | |
3075 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3076 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3077 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3078 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3079 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3080 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3081 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3082 | } else { | |
3083 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3084 | } | |
3085 | ||
3086 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); | |
3087 | ||
3088 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3089 | } | |
3090 | ||
3091 | static void skylake_disable_primary_plane(struct drm_plane *primary, | |
3092 | struct drm_crtc *crtc) | |
3093 | { | |
3094 | struct drm_device *dev = crtc->dev; | |
3095 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3096 | int pipe = to_intel_crtc(crtc)->pipe; | |
3097 | ||
3098 | I915_WRITE(PLANE_CTL(pipe, 0), 0); | |
3099 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3100 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3101 | } | |
3102 | ||
3103 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
3104 | static int | |
3105 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3106 | int x, int y, enum mode_set_atomic state) | |
3107 | { | |
3108 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3109 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3110 | ||
3111 | return -ENODEV; | |
3112 | } | |
3113 | ||
3114 | static void intel_complete_page_flips(struct drm_device *dev) | |
3115 | { | |
3116 | struct drm_crtc *crtc; | |
3117 | ||
3118 | for_each_crtc(dev, crtc) { | |
3119 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3120 | enum plane plane = intel_crtc->plane; | |
3121 | ||
3122 | intel_prepare_page_flip(dev, plane); | |
3123 | intel_finish_page_flip_plane(dev, plane); | |
3124 | } | |
3125 | } | |
3126 | ||
3127 | static void intel_update_primary_planes(struct drm_device *dev) | |
3128 | { | |
3129 | struct drm_crtc *crtc; | |
3130 | ||
3131 | for_each_crtc(dev, crtc) { | |
3132 | struct intel_plane *plane = to_intel_plane(crtc->primary); | |
3133 | struct intel_plane_state *plane_state; | |
3134 | ||
3135 | drm_modeset_lock_crtc(crtc, &plane->base); | |
3136 | plane_state = to_intel_plane_state(plane->base.state); | |
3137 | ||
3138 | if (plane_state->visible) | |
3139 | plane->update_plane(&plane->base, | |
3140 | to_intel_crtc_state(crtc->state), | |
3141 | plane_state); | |
3142 | ||
3143 | drm_modeset_unlock_crtc(crtc); | |
3144 | } | |
3145 | } | |
3146 | ||
3147 | void intel_prepare_reset(struct drm_device *dev) | |
3148 | { | |
3149 | /* no reset support for gen2 */ | |
3150 | if (IS_GEN2(dev)) | |
3151 | return; | |
3152 | ||
3153 | /* reset doesn't touch the display */ | |
3154 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3155 | return; | |
3156 | ||
3157 | drm_modeset_lock_all(dev); | |
3158 | /* | |
3159 | * Disabling the crtcs gracefully seems nicer. Also the | |
3160 | * g33 docs say we should at least disable all the planes. | |
3161 | */ | |
3162 | intel_display_suspend(dev); | |
3163 | } | |
3164 | ||
3165 | void intel_finish_reset(struct drm_device *dev) | |
3166 | { | |
3167 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3168 | ||
3169 | /* | |
3170 | * Flips in the rings will be nuked by the reset, | |
3171 | * so complete all pending flips so that user space | |
3172 | * will get its events and not get stuck. | |
3173 | */ | |
3174 | intel_complete_page_flips(dev); | |
3175 | ||
3176 | /* no reset support for gen2 */ | |
3177 | if (IS_GEN2(dev)) | |
3178 | return; | |
3179 | ||
3180 | /* reset doesn't touch the display */ | |
3181 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3182 | /* | |
3183 | * Flips in the rings have been nuked by the reset, | |
3184 | * so update the base address of all primary | |
3185 | * planes to the the last fb to make sure we're | |
3186 | * showing the correct fb after a reset. | |
3187 | * | |
3188 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3189 | * CS-based flips (which might get lost in gpu resets) any more. | |
3190 | */ | |
3191 | intel_update_primary_planes(dev); | |
3192 | return; | |
3193 | } | |
3194 | ||
3195 | /* | |
3196 | * The display has been reset as well, | |
3197 | * so need a full re-initialization. | |
3198 | */ | |
3199 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3200 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3201 | ||
3202 | intel_modeset_init_hw(dev); | |
3203 | ||
3204 | spin_lock_irq(&dev_priv->irq_lock); | |
3205 | if (dev_priv->display.hpd_irq_setup) | |
3206 | dev_priv->display.hpd_irq_setup(dev); | |
3207 | spin_unlock_irq(&dev_priv->irq_lock); | |
3208 | ||
3209 | intel_display_resume(dev); | |
3210 | ||
3211 | intel_hpd_init(dev_priv); | |
3212 | ||
3213 | drm_modeset_unlock_all(dev); | |
3214 | } | |
3215 | ||
3216 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) | |
3217 | { | |
3218 | struct drm_device *dev = crtc->dev; | |
3219 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3220 | unsigned reset_counter; | |
3221 | bool pending; | |
3222 | ||
3223 | reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error); | |
3224 | if (intel_crtc->reset_counter != reset_counter) | |
3225 | return false; | |
3226 | ||
3227 | spin_lock_irq(&dev->event_lock); | |
3228 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
3229 | spin_unlock_irq(&dev->event_lock); | |
3230 | ||
3231 | return pending; | |
3232 | } | |
3233 | ||
3234 | static void intel_update_pipe_config(struct intel_crtc *crtc, | |
3235 | struct intel_crtc_state *old_crtc_state) | |
3236 | { | |
3237 | struct drm_device *dev = crtc->base.dev; | |
3238 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3239 | struct intel_crtc_state *pipe_config = | |
3240 | to_intel_crtc_state(crtc->base.state); | |
3241 | ||
3242 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ | |
3243 | crtc->base.mode = crtc->base.state->mode; | |
3244 | ||
3245 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3246 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3247 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
3248 | ||
3249 | /* | |
3250 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3251 | * that in compute_mode_changes we check the native mode (not the pfit | |
3252 | * mode) to see if we can flip rather than do a full mode set. In the | |
3253 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3254 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3255 | * sized surface. | |
3256 | */ | |
3257 | ||
3258 | I915_WRITE(PIPESRC(crtc->pipe), | |
3259 | ((pipe_config->pipe_src_w - 1) << 16) | | |
3260 | (pipe_config->pipe_src_h - 1)); | |
3261 | ||
3262 | /* on skylake this is done by detaching scalers */ | |
3263 | if (INTEL_INFO(dev)->gen >= 9) { | |
3264 | skl_detach_scalers(crtc); | |
3265 | ||
3266 | if (pipe_config->pch_pfit.enabled) | |
3267 | skylake_pfit_enable(crtc); | |
3268 | } else if (HAS_PCH_SPLIT(dev)) { | |
3269 | if (pipe_config->pch_pfit.enabled) | |
3270 | ironlake_pfit_enable(crtc); | |
3271 | else if (old_crtc_state->pch_pfit.enabled) | |
3272 | ironlake_pfit_disable(crtc, true); | |
3273 | } | |
3274 | } | |
3275 | ||
3276 | static void intel_fdi_normal_train(struct drm_crtc *crtc) | |
3277 | { | |
3278 | struct drm_device *dev = crtc->dev; | |
3279 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3280 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3281 | int pipe = intel_crtc->pipe; | |
3282 | i915_reg_t reg; | |
3283 | u32 temp; | |
3284 | ||
3285 | /* enable normal train */ | |
3286 | reg = FDI_TX_CTL(pipe); | |
3287 | temp = I915_READ(reg); | |
3288 | if (IS_IVYBRIDGE(dev)) { | |
3289 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; | |
3290 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
3291 | } else { | |
3292 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3293 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
3294 | } | |
3295 | I915_WRITE(reg, temp); | |
3296 | ||
3297 | reg = FDI_RX_CTL(pipe); | |
3298 | temp = I915_READ(reg); | |
3299 | if (HAS_PCH_CPT(dev)) { | |
3300 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3301 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3302 | } else { | |
3303 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3304 | temp |= FDI_LINK_TRAIN_NONE; | |
3305 | } | |
3306 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3307 | ||
3308 | /* wait one idle pattern time */ | |
3309 | POSTING_READ(reg); | |
3310 | udelay(1000); | |
3311 | ||
3312 | /* IVB wants error correction enabled */ | |
3313 | if (IS_IVYBRIDGE(dev)) | |
3314 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3315 | FDI_FE_ERRC_ENABLE); | |
3316 | } | |
3317 | ||
3318 | /* The FDI link training functions for ILK/Ibexpeak. */ | |
3319 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3320 | { | |
3321 | struct drm_device *dev = crtc->dev; | |
3322 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3323 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3324 | int pipe = intel_crtc->pipe; | |
3325 | i915_reg_t reg; | |
3326 | u32 temp, tries; | |
3327 | ||
3328 | /* FDI needs bits from pipe first */ | |
3329 | assert_pipe_enabled(dev_priv, pipe); | |
3330 | ||
3331 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3332 | for train result */ | |
3333 | reg = FDI_RX_IMR(pipe); | |
3334 | temp = I915_READ(reg); | |
3335 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3336 | temp &= ~FDI_RX_BIT_LOCK; | |
3337 | I915_WRITE(reg, temp); | |
3338 | I915_READ(reg); | |
3339 | udelay(150); | |
3340 | ||
3341 | /* enable CPU FDI TX and PCH FDI RX */ | |
3342 | reg = FDI_TX_CTL(pipe); | |
3343 | temp = I915_READ(reg); | |
3344 | temp &= ~FDI_DP_PORT_WIDTH_MASK; | |
3345 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); | |
3346 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3347 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3348 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
3349 | ||
3350 | reg = FDI_RX_CTL(pipe); | |
3351 | temp = I915_READ(reg); | |
3352 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3353 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3354 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
3355 | ||
3356 | POSTING_READ(reg); | |
3357 | udelay(150); | |
3358 | ||
3359 | /* Ironlake workaround, enable clock pointer after FDI enable*/ | |
3360 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
3361 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3362 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
3363 | ||
3364 | reg = FDI_RX_IIR(pipe); | |
3365 | for (tries = 0; tries < 5; tries++) { | |
3366 | temp = I915_READ(reg); | |
3367 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3368 | ||
3369 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3370 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3371 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3372 | break; | |
3373 | } | |
3374 | } | |
3375 | if (tries == 5) | |
3376 | DRM_ERROR("FDI train 1 fail!\n"); | |
3377 | ||
3378 | /* Train 2 */ | |
3379 | reg = FDI_TX_CTL(pipe); | |
3380 | temp = I915_READ(reg); | |
3381 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3382 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3383 | I915_WRITE(reg, temp); | |
3384 | ||
3385 | reg = FDI_RX_CTL(pipe); | |
3386 | temp = I915_READ(reg); | |
3387 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3388 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3389 | I915_WRITE(reg, temp); | |
3390 | ||
3391 | POSTING_READ(reg); | |
3392 | udelay(150); | |
3393 | ||
3394 | reg = FDI_RX_IIR(pipe); | |
3395 | for (tries = 0; tries < 5; tries++) { | |
3396 | temp = I915_READ(reg); | |
3397 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3398 | ||
3399 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3400 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3401 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3402 | break; | |
3403 | } | |
3404 | } | |
3405 | if (tries == 5) | |
3406 | DRM_ERROR("FDI train 2 fail!\n"); | |
3407 | ||
3408 | DRM_DEBUG_KMS("FDI train done\n"); | |
3409 | ||
3410 | } | |
3411 | ||
3412 | static const int snb_b_fdi_train_param[] = { | |
3413 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, | |
3414 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3415 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3416 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3417 | }; | |
3418 | ||
3419 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3420 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3421 | { | |
3422 | struct drm_device *dev = crtc->dev; | |
3423 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3424 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3425 | int pipe = intel_crtc->pipe; | |
3426 | i915_reg_t reg; | |
3427 | u32 temp, i, retry; | |
3428 | ||
3429 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3430 | for train result */ | |
3431 | reg = FDI_RX_IMR(pipe); | |
3432 | temp = I915_READ(reg); | |
3433 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3434 | temp &= ~FDI_RX_BIT_LOCK; | |
3435 | I915_WRITE(reg, temp); | |
3436 | ||
3437 | POSTING_READ(reg); | |
3438 | udelay(150); | |
3439 | ||
3440 | /* enable CPU FDI TX and PCH FDI RX */ | |
3441 | reg = FDI_TX_CTL(pipe); | |
3442 | temp = I915_READ(reg); | |
3443 | temp &= ~FDI_DP_PORT_WIDTH_MASK; | |
3444 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); | |
3445 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3446 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3447 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3448 | /* SNB-B */ | |
3449 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3450 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
3451 | ||
3452 | I915_WRITE(FDI_RX_MISC(pipe), | |
3453 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3454 | ||
3455 | reg = FDI_RX_CTL(pipe); | |
3456 | temp = I915_READ(reg); | |
3457 | if (HAS_PCH_CPT(dev)) { | |
3458 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3459 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3460 | } else { | |
3461 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3462 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3463 | } | |
3464 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
3465 | ||
3466 | POSTING_READ(reg); | |
3467 | udelay(150); | |
3468 | ||
3469 | for (i = 0; i < 4; i++) { | |
3470 | reg = FDI_TX_CTL(pipe); | |
3471 | temp = I915_READ(reg); | |
3472 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3473 | temp |= snb_b_fdi_train_param[i]; | |
3474 | I915_WRITE(reg, temp); | |
3475 | ||
3476 | POSTING_READ(reg); | |
3477 | udelay(500); | |
3478 | ||
3479 | for (retry = 0; retry < 5; retry++) { | |
3480 | reg = FDI_RX_IIR(pipe); | |
3481 | temp = I915_READ(reg); | |
3482 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3483 | if (temp & FDI_RX_BIT_LOCK) { | |
3484 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3485 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3486 | break; | |
3487 | } | |
3488 | udelay(50); | |
3489 | } | |
3490 | if (retry < 5) | |
3491 | break; | |
3492 | } | |
3493 | if (i == 4) | |
3494 | DRM_ERROR("FDI train 1 fail!\n"); | |
3495 | ||
3496 | /* Train 2 */ | |
3497 | reg = FDI_TX_CTL(pipe); | |
3498 | temp = I915_READ(reg); | |
3499 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3500 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3501 | if (IS_GEN6(dev)) { | |
3502 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3503 | /* SNB-B */ | |
3504 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3505 | } | |
3506 | I915_WRITE(reg, temp); | |
3507 | ||
3508 | reg = FDI_RX_CTL(pipe); | |
3509 | temp = I915_READ(reg); | |
3510 | if (HAS_PCH_CPT(dev)) { | |
3511 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3512 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3513 | } else { | |
3514 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3515 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3516 | } | |
3517 | I915_WRITE(reg, temp); | |
3518 | ||
3519 | POSTING_READ(reg); | |
3520 | udelay(150); | |
3521 | ||
3522 | for (i = 0; i < 4; i++) { | |
3523 | reg = FDI_TX_CTL(pipe); | |
3524 | temp = I915_READ(reg); | |
3525 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3526 | temp |= snb_b_fdi_train_param[i]; | |
3527 | I915_WRITE(reg, temp); | |
3528 | ||
3529 | POSTING_READ(reg); | |
3530 | udelay(500); | |
3531 | ||
3532 | for (retry = 0; retry < 5; retry++) { | |
3533 | reg = FDI_RX_IIR(pipe); | |
3534 | temp = I915_READ(reg); | |
3535 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3536 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3537 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3538 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3539 | break; | |
3540 | } | |
3541 | udelay(50); | |
3542 | } | |
3543 | if (retry < 5) | |
3544 | break; | |
3545 | } | |
3546 | if (i == 4) | |
3547 | DRM_ERROR("FDI train 2 fail!\n"); | |
3548 | ||
3549 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3550 | } | |
3551 | ||
3552 | /* Manual link training for Ivy Bridge A0 parts */ | |
3553 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3554 | { | |
3555 | struct drm_device *dev = crtc->dev; | |
3556 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3557 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3558 | int pipe = intel_crtc->pipe; | |
3559 | i915_reg_t reg; | |
3560 | u32 temp, i, j; | |
3561 | ||
3562 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3563 | for train result */ | |
3564 | reg = FDI_RX_IMR(pipe); | |
3565 | temp = I915_READ(reg); | |
3566 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3567 | temp &= ~FDI_RX_BIT_LOCK; | |
3568 | I915_WRITE(reg, temp); | |
3569 | ||
3570 | POSTING_READ(reg); | |
3571 | udelay(150); | |
3572 | ||
3573 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", | |
3574 | I915_READ(FDI_RX_IIR(pipe))); | |
3575 | ||
3576 | /* Try each vswing and preemphasis setting twice before moving on */ | |
3577 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3578 | /* disable first in case we need to retry */ | |
3579 | reg = FDI_TX_CTL(pipe); | |
3580 | temp = I915_READ(reg); | |
3581 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3582 | temp &= ~FDI_TX_ENABLE; | |
3583 | I915_WRITE(reg, temp); | |
3584 | ||
3585 | reg = FDI_RX_CTL(pipe); | |
3586 | temp = I915_READ(reg); | |
3587 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3588 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3589 | temp &= ~FDI_RX_ENABLE; | |
3590 | I915_WRITE(reg, temp); | |
3591 | ||
3592 | /* enable CPU FDI TX and PCH FDI RX */ | |
3593 | reg = FDI_TX_CTL(pipe); | |
3594 | temp = I915_READ(reg); | |
3595 | temp &= ~FDI_DP_PORT_WIDTH_MASK; | |
3596 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); | |
3597 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
3598 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3599 | temp |= snb_b_fdi_train_param[j/2]; | |
3600 | temp |= FDI_COMPOSITE_SYNC; | |
3601 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
3602 | ||
3603 | I915_WRITE(FDI_RX_MISC(pipe), | |
3604 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3605 | ||
3606 | reg = FDI_RX_CTL(pipe); | |
3607 | temp = I915_READ(reg); | |
3608 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3609 | temp |= FDI_COMPOSITE_SYNC; | |
3610 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
3611 | ||
3612 | POSTING_READ(reg); | |
3613 | udelay(1); /* should be 0.5us */ | |
3614 | ||
3615 | for (i = 0; i < 4; i++) { | |
3616 | reg = FDI_RX_IIR(pipe); | |
3617 | temp = I915_READ(reg); | |
3618 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3619 | ||
3620 | if (temp & FDI_RX_BIT_LOCK || | |
3621 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3622 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3623 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3624 | i); | |
3625 | break; | |
3626 | } | |
3627 | udelay(1); /* should be 0.5us */ | |
3628 | } | |
3629 | if (i == 4) { | |
3630 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3631 | continue; | |
3632 | } | |
3633 | ||
3634 | /* Train 2 */ | |
3635 | reg = FDI_TX_CTL(pipe); | |
3636 | temp = I915_READ(reg); | |
3637 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; | |
3638 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3639 | I915_WRITE(reg, temp); | |
3640 | ||
3641 | reg = FDI_RX_CTL(pipe); | |
3642 | temp = I915_READ(reg); | |
3643 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3644 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3645 | I915_WRITE(reg, temp); | |
3646 | ||
3647 | POSTING_READ(reg); | |
3648 | udelay(2); /* should be 1.5us */ | |
3649 | ||
3650 | for (i = 0; i < 4; i++) { | |
3651 | reg = FDI_RX_IIR(pipe); | |
3652 | temp = I915_READ(reg); | |
3653 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3654 | ||
3655 | if (temp & FDI_RX_SYMBOL_LOCK || | |
3656 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3657 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3658 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3659 | i); | |
3660 | goto train_done; | |
3661 | } | |
3662 | udelay(2); /* should be 1.5us */ | |
3663 | } | |
3664 | if (i == 4) | |
3665 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
3666 | } | |
3667 | ||
3668 | train_done: | |
3669 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3670 | } | |
3671 | ||
3672 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) | |
3673 | { | |
3674 | struct drm_device *dev = intel_crtc->base.dev; | |
3675 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3676 | int pipe = intel_crtc->pipe; | |
3677 | i915_reg_t reg; | |
3678 | u32 temp; | |
3679 | ||
3680 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ | |
3681 | reg = FDI_RX_CTL(pipe); | |
3682 | temp = I915_READ(reg); | |
3683 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); | |
3684 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); | |
3685 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; | |
3686 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); | |
3687 | ||
3688 | POSTING_READ(reg); | |
3689 | udelay(200); | |
3690 | ||
3691 | /* Switch from Rawclk to PCDclk */ | |
3692 | temp = I915_READ(reg); | |
3693 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3694 | ||
3695 | POSTING_READ(reg); | |
3696 | udelay(200); | |
3697 | ||
3698 | /* Enable CPU FDI TX PLL, always on for Ironlake */ | |
3699 | reg = FDI_TX_CTL(pipe); | |
3700 | temp = I915_READ(reg); | |
3701 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3702 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
3703 | ||
3704 | POSTING_READ(reg); | |
3705 | udelay(100); | |
3706 | } | |
3707 | } | |
3708 | ||
3709 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) | |
3710 | { | |
3711 | struct drm_device *dev = intel_crtc->base.dev; | |
3712 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3713 | int pipe = intel_crtc->pipe; | |
3714 | i915_reg_t reg; | |
3715 | u32 temp; | |
3716 | ||
3717 | /* Switch from PCDclk to Rawclk */ | |
3718 | reg = FDI_RX_CTL(pipe); | |
3719 | temp = I915_READ(reg); | |
3720 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3721 | ||
3722 | /* Disable CPU FDI TX PLL */ | |
3723 | reg = FDI_TX_CTL(pipe); | |
3724 | temp = I915_READ(reg); | |
3725 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3726 | ||
3727 | POSTING_READ(reg); | |
3728 | udelay(100); | |
3729 | ||
3730 | reg = FDI_RX_CTL(pipe); | |
3731 | temp = I915_READ(reg); | |
3732 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3733 | ||
3734 | /* Wait for the clocks to turn off. */ | |
3735 | POSTING_READ(reg); | |
3736 | udelay(100); | |
3737 | } | |
3738 | ||
3739 | static void ironlake_fdi_disable(struct drm_crtc *crtc) | |
3740 | { | |
3741 | struct drm_device *dev = crtc->dev; | |
3742 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3743 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3744 | int pipe = intel_crtc->pipe; | |
3745 | i915_reg_t reg; | |
3746 | u32 temp; | |
3747 | ||
3748 | /* disable CPU FDI tx and PCH FDI rx */ | |
3749 | reg = FDI_TX_CTL(pipe); | |
3750 | temp = I915_READ(reg); | |
3751 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3752 | POSTING_READ(reg); | |
3753 | ||
3754 | reg = FDI_RX_CTL(pipe); | |
3755 | temp = I915_READ(reg); | |
3756 | temp &= ~(0x7 << 16); | |
3757 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; | |
3758 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); | |
3759 | ||
3760 | POSTING_READ(reg); | |
3761 | udelay(100); | |
3762 | ||
3763 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
3764 | if (HAS_PCH_IBX(dev)) | |
3765 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
3766 | ||
3767 | /* still set train pattern 1 */ | |
3768 | reg = FDI_TX_CTL(pipe); | |
3769 | temp = I915_READ(reg); | |
3770 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3771 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3772 | I915_WRITE(reg, temp); | |
3773 | ||
3774 | reg = FDI_RX_CTL(pipe); | |
3775 | temp = I915_READ(reg); | |
3776 | if (HAS_PCH_CPT(dev)) { | |
3777 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3778 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3779 | } else { | |
3780 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3781 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3782 | } | |
3783 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3784 | temp &= ~(0x07 << 16); | |
3785 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; | |
3786 | I915_WRITE(reg, temp); | |
3787 | ||
3788 | POSTING_READ(reg); | |
3789 | udelay(100); | |
3790 | } | |
3791 | ||
3792 | bool intel_has_pending_fb_unpin(struct drm_device *dev) | |
3793 | { | |
3794 | struct intel_crtc *crtc; | |
3795 | ||
3796 | /* Note that we don't need to be called with mode_config.lock here | |
3797 | * as our list of CRTC objects is static for the lifetime of the | |
3798 | * device and so cannot disappear as we iterate. Similarly, we can | |
3799 | * happily treat the predicates as racy, atomic checks as userspace | |
3800 | * cannot claim and pin a new fb without at least acquring the | |
3801 | * struct_mutex and so serialising with us. | |
3802 | */ | |
3803 | for_each_intel_crtc(dev, crtc) { | |
3804 | if (atomic_read(&crtc->unpin_work_count) == 0) | |
3805 | continue; | |
3806 | ||
3807 | if (crtc->unpin_work) | |
3808 | intel_wait_for_vblank(dev, crtc->pipe); | |
3809 | ||
3810 | return true; | |
3811 | } | |
3812 | ||
3813 | return false; | |
3814 | } | |
3815 | ||
3816 | static void page_flip_completed(struct intel_crtc *intel_crtc) | |
3817 | { | |
3818 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3819 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3820 | ||
3821 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3822 | smp_rmb(); | |
3823 | intel_crtc->unpin_work = NULL; | |
3824 | ||
3825 | if (work->event) | |
3826 | drm_crtc_send_vblank_event(&intel_crtc->base, work->event); | |
3827 | ||
3828 | drm_crtc_vblank_put(&intel_crtc->base); | |
3829 | ||
3830 | wake_up_all(&dev_priv->pending_flip_queue); | |
3831 | queue_work(dev_priv->wq, &work->work); | |
3832 | ||
3833 | trace_i915_flip_complete(intel_crtc->plane, | |
3834 | work->pending_flip_obj); | |
3835 | } | |
3836 | ||
3837 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) | |
3838 | { | |
3839 | struct drm_device *dev = crtc->dev; | |
3840 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3841 | long ret; | |
3842 | ||
3843 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); | |
3844 | ||
3845 | ret = wait_event_interruptible_timeout( | |
3846 | dev_priv->pending_flip_queue, | |
3847 | !intel_crtc_has_pending_flip(crtc), | |
3848 | 60*HZ); | |
3849 | ||
3850 | if (ret < 0) | |
3851 | return ret; | |
3852 | ||
3853 | if (ret == 0) { | |
3854 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3855 | ||
3856 | spin_lock_irq(&dev->event_lock); | |
3857 | if (intel_crtc->unpin_work) { | |
3858 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3859 | page_flip_completed(intel_crtc); | |
3860 | } | |
3861 | spin_unlock_irq(&dev->event_lock); | |
3862 | } | |
3863 | ||
3864 | return 0; | |
3865 | } | |
3866 | ||
3867 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) | |
3868 | { | |
3869 | u32 temp; | |
3870 | ||
3871 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3872 | ||
3873 | mutex_lock(&dev_priv->sb_lock); | |
3874 | ||
3875 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3876 | temp |= SBI_SSCCTL_DISABLE; | |
3877 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
3878 | ||
3879 | mutex_unlock(&dev_priv->sb_lock); | |
3880 | } | |
3881 | ||
3882 | /* Program iCLKIP clock to the desired frequency */ | |
3883 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3884 | { | |
3885 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
3886 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; | |
3887 | u32 divsel, phaseinc, auxdiv, phasedir = 0; | |
3888 | u32 temp; | |
3889 | ||
3890 | lpt_disable_iclkip(dev_priv); | |
3891 | ||
3892 | /* The iCLK virtual clock root frequency is in MHz, | |
3893 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
3894 | * divisors, it is necessary to divide one by another, so we | |
3895 | * convert the virtual clock precision to KHz here for higher | |
3896 | * precision. | |
3897 | */ | |
3898 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
3899 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3900 | u32 iclk_pi_range = 64; | |
3901 | u32 desired_divisor; | |
3902 | ||
3903 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
3904 | clock << auxdiv); | |
3905 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
3906 | phaseinc = desired_divisor % iclk_pi_range; | |
3907 | ||
3908 | /* | |
3909 | * Near 20MHz is a corner case which is | |
3910 | * out of range for the 7-bit divisor | |
3911 | */ | |
3912 | if (divsel <= 0x7f) | |
3913 | break; | |
3914 | } | |
3915 | ||
3916 | /* This should not happen with any sane values */ | |
3917 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3918 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3919 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3920 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3921 | ||
3922 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
3923 | clock, | |
3924 | auxdiv, | |
3925 | divsel, | |
3926 | phasedir, | |
3927 | phaseinc); | |
3928 | ||
3929 | mutex_lock(&dev_priv->sb_lock); | |
3930 | ||
3931 | /* Program SSCDIVINTPHASE6 */ | |
3932 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
3933 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; | |
3934 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3935 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3936 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3937 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3938 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
3939 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); | |
3940 | ||
3941 | /* Program SSCAUXDIV */ | |
3942 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
3943 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); | |
3944 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
3945 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); | |
3946 | ||
3947 | /* Enable modulator and associated divider */ | |
3948 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3949 | temp &= ~SBI_SSCCTL_DISABLE; | |
3950 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
3951 | ||
3952 | mutex_unlock(&dev_priv->sb_lock); | |
3953 | ||
3954 | /* Wait for initialization time */ | |
3955 | udelay(24); | |
3956 | ||
3957 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
3958 | } | |
3959 | ||
3960 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) | |
3961 | { | |
3962 | u32 divsel, phaseinc, auxdiv; | |
3963 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3964 | u32 iclk_pi_range = 64; | |
3965 | u32 desired_divisor; | |
3966 | u32 temp; | |
3967 | ||
3968 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
3969 | return 0; | |
3970 | ||
3971 | mutex_lock(&dev_priv->sb_lock); | |
3972 | ||
3973 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3974 | if (temp & SBI_SSCCTL_DISABLE) { | |
3975 | mutex_unlock(&dev_priv->sb_lock); | |
3976 | return 0; | |
3977 | } | |
3978 | ||
3979 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
3980 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
3981 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
3982 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
3983 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
3984 | ||
3985 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
3986 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
3987 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
3988 | ||
3989 | mutex_unlock(&dev_priv->sb_lock); | |
3990 | ||
3991 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
3992 | ||
3993 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
3994 | desired_divisor << auxdiv); | |
3995 | } | |
3996 | ||
3997 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, | |
3998 | enum pipe pch_transcoder) | |
3999 | { | |
4000 | struct drm_device *dev = crtc->base.dev; | |
4001 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4002 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; | |
4003 | ||
4004 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4005 | I915_READ(HTOTAL(cpu_transcoder))); | |
4006 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4007 | I915_READ(HBLANK(cpu_transcoder))); | |
4008 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4009 | I915_READ(HSYNC(cpu_transcoder))); | |
4010 | ||
4011 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4012 | I915_READ(VTOTAL(cpu_transcoder))); | |
4013 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4014 | I915_READ(VBLANK(cpu_transcoder))); | |
4015 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4016 | I915_READ(VSYNC(cpu_transcoder))); | |
4017 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4018 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4019 | } | |
4020 | ||
4021 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) | |
4022 | { | |
4023 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4024 | uint32_t temp; | |
4025 | ||
4026 | temp = I915_READ(SOUTH_CHICKEN1); | |
4027 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) | |
4028 | return; | |
4029 | ||
4030 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4031 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4032 | ||
4033 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
4034 | if (enable) | |
4035 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4036 | ||
4037 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
4038 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
4039 | POSTING_READ(SOUTH_CHICKEN1); | |
4040 | } | |
4041 | ||
4042 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4043 | { | |
4044 | struct drm_device *dev = intel_crtc->base.dev; | |
4045 | ||
4046 | switch (intel_crtc->pipe) { | |
4047 | case PIPE_A: | |
4048 | break; | |
4049 | case PIPE_B: | |
4050 | if (intel_crtc->config->fdi_lanes > 2) | |
4051 | cpt_set_fdi_bc_bifurcation(dev, false); | |
4052 | else | |
4053 | cpt_set_fdi_bc_bifurcation(dev, true); | |
4054 | ||
4055 | break; | |
4056 | case PIPE_C: | |
4057 | cpt_set_fdi_bc_bifurcation(dev, true); | |
4058 | ||
4059 | break; | |
4060 | default: | |
4061 | BUG(); | |
4062 | } | |
4063 | } | |
4064 | ||
4065 | /* Return which DP Port should be selected for Transcoder DP control */ | |
4066 | static enum port | |
4067 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4068 | { | |
4069 | struct drm_device *dev = crtc->dev; | |
4070 | struct intel_encoder *encoder; | |
4071 | ||
4072 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
4073 | if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
4074 | encoder->type == INTEL_OUTPUT_EDP) | |
4075 | return enc_to_dig_port(&encoder->base)->port; | |
4076 | } | |
4077 | ||
4078 | return -1; | |
4079 | } | |
4080 | ||
4081 | /* | |
4082 | * Enable PCH resources required for PCH ports: | |
4083 | * - PCH PLLs | |
4084 | * - FDI training & RX/TX | |
4085 | * - update transcoder timings | |
4086 | * - DP transcoding bits | |
4087 | * - transcoder | |
4088 | */ | |
4089 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
4090 | { | |
4091 | struct drm_device *dev = crtc->dev; | |
4092 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4093 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4094 | int pipe = intel_crtc->pipe; | |
4095 | u32 temp; | |
4096 | ||
4097 | assert_pch_transcoder_disabled(dev_priv, pipe); | |
4098 | ||
4099 | if (IS_IVYBRIDGE(dev)) | |
4100 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4101 | ||
4102 | /* Write the TU size bits before fdi link training, so that error | |
4103 | * detection works. */ | |
4104 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4105 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4106 | ||
4107 | /* For PCH output, training FDI link */ | |
4108 | dev_priv->display.fdi_link_train(crtc); | |
4109 | ||
4110 | /* We need to program the right clock selection before writing the pixel | |
4111 | * mutliplier into the DPLL. */ | |
4112 | if (HAS_PCH_CPT(dev)) { | |
4113 | u32 sel; | |
4114 | ||
4115 | temp = I915_READ(PCH_DPLL_SEL); | |
4116 | temp |= TRANS_DPLL_ENABLE(pipe); | |
4117 | sel = TRANS_DPLLB_SEL(pipe); | |
4118 | if (intel_crtc->config->shared_dpll == | |
4119 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) | |
4120 | temp |= sel; | |
4121 | else | |
4122 | temp &= ~sel; | |
4123 | I915_WRITE(PCH_DPLL_SEL, temp); | |
4124 | } | |
4125 | ||
4126 | /* XXX: pch pll's can be enabled any time before we enable the PCH | |
4127 | * transcoder, and we actually should do this to not upset any PCH | |
4128 | * transcoder that already use the clock when we share it. | |
4129 | * | |
4130 | * Note that enable_shared_dpll tries to do the right thing, but | |
4131 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4132 | * the right LVDS enable sequence. */ | |
4133 | intel_enable_shared_dpll(intel_crtc); | |
4134 | ||
4135 | /* set transcoder timing, panel must allow it */ | |
4136 | assert_panel_unlocked(dev_priv, pipe); | |
4137 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); | |
4138 | ||
4139 | intel_fdi_normal_train(crtc); | |
4140 | ||
4141 | /* For PCH DP, enable TRANS_DP_CTL */ | |
4142 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { | |
4143 | const struct drm_display_mode *adjusted_mode = | |
4144 | &intel_crtc->config->base.adjusted_mode; | |
4145 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; | |
4146 | i915_reg_t reg = TRANS_DP_CTL(pipe); | |
4147 | temp = I915_READ(reg); | |
4148 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
4149 | TRANS_DP_SYNC_MASK | | |
4150 | TRANS_DP_BPC_MASK); | |
4151 | temp |= TRANS_DP_OUTPUT_ENABLE; | |
4152 | temp |= bpc << 9; /* same format but at 11:9 */ | |
4153 | ||
4154 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
4155 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; | |
4156 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
4157 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; | |
4158 | ||
4159 | switch (intel_trans_dp_port_sel(crtc)) { | |
4160 | case PORT_B: | |
4161 | temp |= TRANS_DP_PORT_SEL_B; | |
4162 | break; | |
4163 | case PORT_C: | |
4164 | temp |= TRANS_DP_PORT_SEL_C; | |
4165 | break; | |
4166 | case PORT_D: | |
4167 | temp |= TRANS_DP_PORT_SEL_D; | |
4168 | break; | |
4169 | default: | |
4170 | BUG(); | |
4171 | } | |
4172 | ||
4173 | I915_WRITE(reg, temp); | |
4174 | } | |
4175 | ||
4176 | ironlake_enable_pch_transcoder(dev_priv, pipe); | |
4177 | } | |
4178 | ||
4179 | static void lpt_pch_enable(struct drm_crtc *crtc) | |
4180 | { | |
4181 | struct drm_device *dev = crtc->dev; | |
4182 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4183 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4184 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; | |
4185 | ||
4186 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); | |
4187 | ||
4188 | lpt_program_iclkip(crtc); | |
4189 | ||
4190 | /* Set transcoder timing. */ | |
4191 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); | |
4192 | ||
4193 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); | |
4194 | } | |
4195 | ||
4196 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) | |
4197 | { | |
4198 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4199 | i915_reg_t dslreg = PIPEDSL(pipe); | |
4200 | u32 temp; | |
4201 | ||
4202 | temp = I915_READ(dslreg); | |
4203 | udelay(500); | |
4204 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
4205 | if (wait_for(I915_READ(dslreg) != temp, 5)) | |
4206 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); | |
4207 | } | |
4208 | } | |
4209 | ||
4210 | static int | |
4211 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4212 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4213 | int src_w, int src_h, int dst_w, int dst_h) | |
4214 | { | |
4215 | struct intel_crtc_scaler_state *scaler_state = | |
4216 | &crtc_state->scaler_state; | |
4217 | struct intel_crtc *intel_crtc = | |
4218 | to_intel_crtc(crtc_state->base.crtc); | |
4219 | int need_scaling; | |
4220 | ||
4221 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4222 | (src_h != dst_w || src_w != dst_h): | |
4223 | (src_w != dst_w || src_h != dst_h); | |
4224 | ||
4225 | /* | |
4226 | * if plane is being disabled or scaler is no more required or force detach | |
4227 | * - free scaler binded to this plane/crtc | |
4228 | * - in order to do this, update crtc->scaler_usage | |
4229 | * | |
4230 | * Here scaler state in crtc_state is set free so that | |
4231 | * scaler can be assigned to other user. Actual register | |
4232 | * update to free the scaler is done in plane/panel-fit programming. | |
4233 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4234 | */ | |
4235 | if (force_detach || !need_scaling) { | |
4236 | if (*scaler_id >= 0) { | |
4237 | scaler_state->scaler_users &= ~(1 << scaler_user); | |
4238 | scaler_state->scalers[*scaler_id].in_use = 0; | |
4239 | ||
4240 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4241 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4242 | intel_crtc->pipe, scaler_user, *scaler_id, | |
4243 | scaler_state->scaler_users); | |
4244 | *scaler_id = -1; | |
4245 | } | |
4246 | return 0; | |
4247 | } | |
4248 | ||
4249 | /* range checks */ | |
4250 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4251 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4252 | ||
4253 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4254 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
4255 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " | |
4256 | "size is out of scaler range\n", | |
4257 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); | |
4258 | return -EINVAL; | |
4259 | } | |
4260 | ||
4261 | /* mark this plane as a scaler user in crtc_state */ | |
4262 | scaler_state->scaler_users |= (1 << scaler_user); | |
4263 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4264 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4265 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4266 | scaler_state->scaler_users); | |
4267 | ||
4268 | return 0; | |
4269 | } | |
4270 | ||
4271 | /** | |
4272 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4273 | * | |
4274 | * @state: crtc's scaler state | |
4275 | * | |
4276 | * Return | |
4277 | * 0 - scaler_usage updated successfully | |
4278 | * error - requested scaling cannot be supported or other error condition | |
4279 | */ | |
4280 | int skl_update_scaler_crtc(struct intel_crtc_state *state) | |
4281 | { | |
4282 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
4283 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; | |
4284 | ||
4285 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", | |
4286 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); | |
4287 | ||
4288 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, | |
4289 | &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0), | |
4290 | state->pipe_src_w, state->pipe_src_h, | |
4291 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); | |
4292 | } | |
4293 | ||
4294 | /** | |
4295 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4296 | * | |
4297 | * @state: crtc's scaler state | |
4298 | * @plane_state: atomic plane state to update | |
4299 | * | |
4300 | * Return | |
4301 | * 0 - scaler_usage updated successfully | |
4302 | * error - requested scaling cannot be supported or other error condition | |
4303 | */ | |
4304 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, | |
4305 | struct intel_plane_state *plane_state) | |
4306 | { | |
4307 | ||
4308 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
4309 | struct intel_plane *intel_plane = | |
4310 | to_intel_plane(plane_state->base.plane); | |
4311 | struct drm_framebuffer *fb = plane_state->base.fb; | |
4312 | int ret; | |
4313 | ||
4314 | bool force_detach = !fb || !plane_state->visible; | |
4315 | ||
4316 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", | |
4317 | intel_plane->base.base.id, intel_crtc->pipe, | |
4318 | drm_plane_index(&intel_plane->base)); | |
4319 | ||
4320 | ret = skl_update_scaler(crtc_state, force_detach, | |
4321 | drm_plane_index(&intel_plane->base), | |
4322 | &plane_state->scaler_id, | |
4323 | plane_state->base.rotation, | |
4324 | drm_rect_width(&plane_state->src) >> 16, | |
4325 | drm_rect_height(&plane_state->src) >> 16, | |
4326 | drm_rect_width(&plane_state->dst), | |
4327 | drm_rect_height(&plane_state->dst)); | |
4328 | ||
4329 | if (ret || plane_state->scaler_id < 0) | |
4330 | return ret; | |
4331 | ||
4332 | /* check colorkey */ | |
4333 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { | |
4334 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", | |
4335 | intel_plane->base.base.id); | |
4336 | return -EINVAL; | |
4337 | } | |
4338 | ||
4339 | /* Check src format */ | |
4340 | switch (fb->pixel_format) { | |
4341 | case DRM_FORMAT_RGB565: | |
4342 | case DRM_FORMAT_XBGR8888: | |
4343 | case DRM_FORMAT_XRGB8888: | |
4344 | case DRM_FORMAT_ABGR8888: | |
4345 | case DRM_FORMAT_ARGB8888: | |
4346 | case DRM_FORMAT_XRGB2101010: | |
4347 | case DRM_FORMAT_XBGR2101010: | |
4348 | case DRM_FORMAT_YUYV: | |
4349 | case DRM_FORMAT_YVYU: | |
4350 | case DRM_FORMAT_UYVY: | |
4351 | case DRM_FORMAT_VYUY: | |
4352 | break; | |
4353 | default: | |
4354 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", | |
4355 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4356 | return -EINVAL; | |
4357 | } | |
4358 | ||
4359 | return 0; | |
4360 | } | |
4361 | ||
4362 | static void skylake_scaler_disable(struct intel_crtc *crtc) | |
4363 | { | |
4364 | int i; | |
4365 | ||
4366 | for (i = 0; i < crtc->num_scalers; i++) | |
4367 | skl_detach_scaler(crtc, i); | |
4368 | } | |
4369 | ||
4370 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
4371 | { | |
4372 | struct drm_device *dev = crtc->base.dev; | |
4373 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4374 | int pipe = crtc->pipe; | |
4375 | struct intel_crtc_scaler_state *scaler_state = | |
4376 | &crtc->config->scaler_state; | |
4377 | ||
4378 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4379 | ||
4380 | if (crtc->config->pch_pfit.enabled) { | |
4381 | int id; | |
4382 | ||
4383 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4384 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4385 | return; | |
4386 | } | |
4387 | ||
4388 | id = scaler_state->scaler_id; | |
4389 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4390 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4391 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4392 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4393 | ||
4394 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
4395 | } | |
4396 | } | |
4397 | ||
4398 | static void ironlake_pfit_enable(struct intel_crtc *crtc) | |
4399 | { | |
4400 | struct drm_device *dev = crtc->base.dev; | |
4401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4402 | int pipe = crtc->pipe; | |
4403 | ||
4404 | if (crtc->config->pch_pfit.enabled) { | |
4405 | /* Force use of hard-coded filter coefficients | |
4406 | * as some pre-programmed values are broken, | |
4407 | * e.g. x201. | |
4408 | */ | |
4409 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4410 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4411 | PF_PIPE_SEL_IVB(pipe)); | |
4412 | else | |
4413 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
4414 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); | |
4415 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
4416 | } | |
4417 | } | |
4418 | ||
4419 | void hsw_enable_ips(struct intel_crtc *crtc) | |
4420 | { | |
4421 | struct drm_device *dev = crtc->base.dev; | |
4422 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4423 | ||
4424 | if (!crtc->config->ips_enabled) | |
4425 | return; | |
4426 | ||
4427 | /* | |
4428 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4429 | * This function is called from post_plane_update, which is run after | |
4430 | * a vblank wait. | |
4431 | */ | |
4432 | ||
4433 | assert_plane_enabled(dev_priv, crtc->plane); | |
4434 | if (IS_BROADWELL(dev)) { | |
4435 | mutex_lock(&dev_priv->rps.hw_lock); | |
4436 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4437 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4438 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4439 | * value in IPS_CTL bit 31 after enabling IPS through the | |
4440 | * mailbox." Moreover, the mailbox may return a bogus state, | |
4441 | * so we need to just enable it and continue on. | |
4442 | */ | |
4443 | } else { | |
4444 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4445 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4446 | * is essentially intel_wait_for_vblank. If we don't have this | |
4447 | * and don't wait for vblanks until the end of crtc_enable, then | |
4448 | * the HW state readout code will complain that the expected | |
4449 | * IPS_CTL value is not the one we read. */ | |
4450 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4451 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4452 | } | |
4453 | } | |
4454 | ||
4455 | void hsw_disable_ips(struct intel_crtc *crtc) | |
4456 | { | |
4457 | struct drm_device *dev = crtc->base.dev; | |
4458 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4459 | ||
4460 | if (!crtc->config->ips_enabled) | |
4461 | return; | |
4462 | ||
4463 | assert_plane_enabled(dev_priv, crtc->plane); | |
4464 | if (IS_BROADWELL(dev)) { | |
4465 | mutex_lock(&dev_priv->rps.hw_lock); | |
4466 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4467 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4468 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ | |
4469 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4470 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
4471 | } else { | |
4472 | I915_WRITE(IPS_CTL, 0); | |
4473 | POSTING_READ(IPS_CTL); | |
4474 | } | |
4475 | ||
4476 | /* We need to wait for a vblank before we can disable the plane. */ | |
4477 | intel_wait_for_vblank(dev, crtc->pipe); | |
4478 | } | |
4479 | ||
4480 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) | |
4481 | { | |
4482 | if (intel_crtc->overlay) { | |
4483 | struct drm_device *dev = intel_crtc->base.dev; | |
4484 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4485 | ||
4486 | mutex_lock(&dev->struct_mutex); | |
4487 | dev_priv->mm.interruptible = false; | |
4488 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4489 | dev_priv->mm.interruptible = true; | |
4490 | mutex_unlock(&dev->struct_mutex); | |
4491 | } | |
4492 | ||
4493 | /* Let userspace switch the overlay on again. In most cases userspace | |
4494 | * has to recompute where to put it anyway. | |
4495 | */ | |
4496 | } | |
4497 | ||
4498 | /** | |
4499 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4500 | * @crtc: the CRTC whose primary plane was just enabled | |
4501 | * | |
4502 | * Performs potentially sleeping operations that must be done after the primary | |
4503 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4504 | * called due to an explicit primary plane update, or due to an implicit | |
4505 | * re-enable that is caused when a sprite plane is updated to no longer | |
4506 | * completely hide the primary plane. | |
4507 | */ | |
4508 | static void | |
4509 | intel_post_enable_primary(struct drm_crtc *crtc) | |
4510 | { | |
4511 | struct drm_device *dev = crtc->dev; | |
4512 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4513 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4514 | int pipe = intel_crtc->pipe; | |
4515 | ||
4516 | /* | |
4517 | * FIXME IPS should be fine as long as one plane is | |
4518 | * enabled, but in practice it seems to have problems | |
4519 | * when going from primary only to sprite only and vice | |
4520 | * versa. | |
4521 | */ | |
4522 | hsw_enable_ips(intel_crtc); | |
4523 | ||
4524 | /* | |
4525 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4526 | * So don't enable underrun reporting before at least some planes | |
4527 | * are enabled. | |
4528 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4529 | * but leave the pipe running. | |
4530 | */ | |
4531 | if (IS_GEN2(dev)) | |
4532 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4533 | ||
4534 | /* Underruns don't always raise interrupts, so check manually. */ | |
4535 | intel_check_cpu_fifo_underruns(dev_priv); | |
4536 | intel_check_pch_fifo_underruns(dev_priv); | |
4537 | } | |
4538 | ||
4539 | /* FIXME move all this to pre_plane_update() with proper state tracking */ | |
4540 | static void | |
4541 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
4542 | { | |
4543 | struct drm_device *dev = crtc->dev; | |
4544 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4545 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4546 | int pipe = intel_crtc->pipe; | |
4547 | ||
4548 | /* | |
4549 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4550 | * So diasble underrun reporting before all the planes get disabled. | |
4551 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4552 | * but leave the pipe running. | |
4553 | */ | |
4554 | if (IS_GEN2(dev)) | |
4555 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4556 | ||
4557 | /* | |
4558 | * FIXME IPS should be fine as long as one plane is | |
4559 | * enabled, but in practice it seems to have problems | |
4560 | * when going from primary only to sprite only and vice | |
4561 | * versa. | |
4562 | */ | |
4563 | hsw_disable_ips(intel_crtc); | |
4564 | } | |
4565 | ||
4566 | /* FIXME get rid of this and use pre_plane_update */ | |
4567 | static void | |
4568 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
4569 | { | |
4570 | struct drm_device *dev = crtc->dev; | |
4571 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4572 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4573 | int pipe = intel_crtc->pipe; | |
4574 | ||
4575 | intel_pre_disable_primary(crtc); | |
4576 | ||
4577 | /* | |
4578 | * Vblank time updates from the shadow to live plane control register | |
4579 | * are blocked if the memory self-refresh mode is active at that | |
4580 | * moment. So to make sure the plane gets truly disabled, disable | |
4581 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4582 | * will be checked/applied by the HW only at the next frame start | |
4583 | * event which is after the vblank start event, so we need to have a | |
4584 | * wait-for-vblank between disabling the plane and the pipe. | |
4585 | */ | |
4586 | if (HAS_GMCH_DISPLAY(dev)) { | |
4587 | intel_set_memory_cxsr(dev_priv, false); | |
4588 | dev_priv->wm.vlv.cxsr = false; | |
4589 | intel_wait_for_vblank(dev, pipe); | |
4590 | } | |
4591 | } | |
4592 | ||
4593 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) | |
4594 | { | |
4595 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
4596 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
4597 | struct intel_crtc_state *pipe_config = | |
4598 | to_intel_crtc_state(crtc->base.state); | |
4599 | struct drm_device *dev = crtc->base.dev; | |
4600 | struct drm_plane *primary = crtc->base.primary; | |
4601 | struct drm_plane_state *old_pri_state = | |
4602 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4603 | ||
4604 | intel_frontbuffer_flip(dev, pipe_config->fb_bits); | |
4605 | ||
4606 | crtc->wm.cxsr_allowed = true; | |
4607 | ||
4608 | if (pipe_config->update_wm_post && pipe_config->base.active) | |
4609 | intel_update_watermarks(&crtc->base); | |
4610 | ||
4611 | if (old_pri_state) { | |
4612 | struct intel_plane_state *primary_state = | |
4613 | to_intel_plane_state(primary->state); | |
4614 | struct intel_plane_state *old_primary_state = | |
4615 | to_intel_plane_state(old_pri_state); | |
4616 | ||
4617 | intel_fbc_post_update(crtc); | |
4618 | ||
4619 | if (primary_state->visible && | |
4620 | (needs_modeset(&pipe_config->base) || | |
4621 | !old_primary_state->visible)) | |
4622 | intel_post_enable_primary(&crtc->base); | |
4623 | } | |
4624 | } | |
4625 | ||
4626 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) | |
4627 | { | |
4628 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
4629 | struct drm_device *dev = crtc->base.dev; | |
4630 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4631 | struct intel_crtc_state *pipe_config = | |
4632 | to_intel_crtc_state(crtc->base.state); | |
4633 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
4634 | struct drm_plane *primary = crtc->base.primary; | |
4635 | struct drm_plane_state *old_pri_state = | |
4636 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4637 | bool modeset = needs_modeset(&pipe_config->base); | |
4638 | ||
4639 | if (old_pri_state) { | |
4640 | struct intel_plane_state *primary_state = | |
4641 | to_intel_plane_state(primary->state); | |
4642 | struct intel_plane_state *old_primary_state = | |
4643 | to_intel_plane_state(old_pri_state); | |
4644 | ||
4645 | intel_fbc_pre_update(crtc); | |
4646 | ||
4647 | if (old_primary_state->visible && | |
4648 | (modeset || !primary_state->visible)) | |
4649 | intel_pre_disable_primary(&crtc->base); | |
4650 | } | |
4651 | ||
4652 | if (pipe_config->disable_cxsr) { | |
4653 | crtc->wm.cxsr_allowed = false; | |
4654 | ||
4655 | /* | |
4656 | * Vblank time updates from the shadow to live plane control register | |
4657 | * are blocked if the memory self-refresh mode is active at that | |
4658 | * moment. So to make sure the plane gets truly disabled, disable | |
4659 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4660 | * will be checked/applied by the HW only at the next frame start | |
4661 | * event which is after the vblank start event, so we need to have a | |
4662 | * wait-for-vblank between disabling the plane and the pipe. | |
4663 | */ | |
4664 | if (old_crtc_state->base.active) { | |
4665 | intel_set_memory_cxsr(dev_priv, false); | |
4666 | dev_priv->wm.vlv.cxsr = false; | |
4667 | intel_wait_for_vblank(dev, crtc->pipe); | |
4668 | } | |
4669 | } | |
4670 | ||
4671 | /* | |
4672 | * IVB workaround: must disable low power watermarks for at least | |
4673 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
4674 | * when scaling is disabled. | |
4675 | * | |
4676 | * WaCxSRDisabledForSpriteScaling:ivb | |
4677 | */ | |
4678 | if (pipe_config->disable_lp_wm) { | |
4679 | ilk_disable_lp_wm(dev); | |
4680 | intel_wait_for_vblank(dev, crtc->pipe); | |
4681 | } | |
4682 | ||
4683 | /* | |
4684 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
4685 | * watermark programming here. | |
4686 | */ | |
4687 | if (needs_modeset(&pipe_config->base)) | |
4688 | return; | |
4689 | ||
4690 | /* | |
4691 | * For platforms that support atomic watermarks, program the | |
4692 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
4693 | * will be the intermediate values that are safe for both pre- and | |
4694 | * post- vblank; when vblank happens, the 'active' values will be set | |
4695 | * to the final 'target' values and we'll do this again to get the | |
4696 | * optimal watermarks. For gen9+ platforms, the values we program here | |
4697 | * will be the final target values which will get automatically latched | |
4698 | * at vblank time; no further programming will be necessary. | |
4699 | * | |
4700 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
4701 | * we'll continue to update watermarks the old way, if flags tell | |
4702 | * us to. | |
4703 | */ | |
4704 | if (dev_priv->display.initial_watermarks != NULL) | |
4705 | dev_priv->display.initial_watermarks(pipe_config); | |
4706 | else if (pipe_config->update_wm_pre) | |
4707 | intel_update_watermarks(&crtc->base); | |
4708 | } | |
4709 | ||
4710 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) | |
4711 | { | |
4712 | struct drm_device *dev = crtc->dev; | |
4713 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4714 | struct drm_plane *p; | |
4715 | int pipe = intel_crtc->pipe; | |
4716 | ||
4717 | intel_crtc_dpms_overlay_disable(intel_crtc); | |
4718 | ||
4719 | drm_for_each_plane_mask(p, dev, plane_mask) | |
4720 | to_intel_plane(p)->disable_plane(p, crtc); | |
4721 | ||
4722 | /* | |
4723 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4724 | * to compute the mask of flip planes precisely. For the time being | |
4725 | * consider this a flip to a NULL plane. | |
4726 | */ | |
4727 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
4728 | } | |
4729 | ||
4730 | static void ironlake_crtc_enable(struct drm_crtc *crtc) | |
4731 | { | |
4732 | struct drm_device *dev = crtc->dev; | |
4733 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4734 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4735 | struct intel_encoder *encoder; | |
4736 | int pipe = intel_crtc->pipe; | |
4737 | struct intel_crtc_state *pipe_config = | |
4738 | to_intel_crtc_state(crtc->state); | |
4739 | ||
4740 | if (WARN_ON(intel_crtc->active)) | |
4741 | return; | |
4742 | ||
4743 | /* | |
4744 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4745 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4746 | * | |
4747 | * On ILK we get an occasional spurious CPU pipe underruns | |
4748 | * between eDP port A enable and vdd enable. Also PCH port | |
4749 | * enable seems to result in the occasional CPU pipe underrun. | |
4750 | * | |
4751 | * Spurious PCH underruns also occur during PCH enabling. | |
4752 | */ | |
4753 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
4754 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4755 | if (intel_crtc->config->has_pch_encoder) | |
4756 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4757 | ||
4758 | if (intel_crtc->config->has_pch_encoder) | |
4759 | intel_prepare_shared_dpll(intel_crtc); | |
4760 | ||
4761 | if (intel_crtc->config->has_dp_encoder) | |
4762 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
4763 | ||
4764 | intel_set_pipe_timings(intel_crtc); | |
4765 | intel_set_pipe_src_size(intel_crtc); | |
4766 | ||
4767 | if (intel_crtc->config->has_pch_encoder) { | |
4768 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
4769 | &intel_crtc->config->fdi_m_n, NULL); | |
4770 | } | |
4771 | ||
4772 | ironlake_set_pipeconf(crtc); | |
4773 | ||
4774 | intel_crtc->active = true; | |
4775 | ||
4776 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4777 | if (encoder->pre_enable) | |
4778 | encoder->pre_enable(encoder); | |
4779 | ||
4780 | if (intel_crtc->config->has_pch_encoder) { | |
4781 | /* Note: FDI PLL enabling _must_ be done before we enable the | |
4782 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4783 | * enabling. */ | |
4784 | ironlake_fdi_pll_enable(intel_crtc); | |
4785 | } else { | |
4786 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4787 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4788 | } | |
4789 | ||
4790 | ironlake_pfit_enable(intel_crtc); | |
4791 | ||
4792 | /* | |
4793 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4794 | * clocks enabled | |
4795 | */ | |
4796 | intel_color_load_luts(&pipe_config->base); | |
4797 | ||
4798 | if (dev_priv->display.initial_watermarks != NULL) | |
4799 | dev_priv->display.initial_watermarks(intel_crtc->config); | |
4800 | intel_enable_pipe(intel_crtc); | |
4801 | ||
4802 | if (intel_crtc->config->has_pch_encoder) | |
4803 | ironlake_pch_enable(crtc); | |
4804 | ||
4805 | assert_vblank_disabled(crtc); | |
4806 | drm_crtc_vblank_on(crtc); | |
4807 | ||
4808 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4809 | encoder->enable(encoder); | |
4810 | ||
4811 | if (HAS_PCH_CPT(dev)) | |
4812 | cpt_verify_modeset(dev, intel_crtc->pipe); | |
4813 | ||
4814 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
4815 | if (intel_crtc->config->has_pch_encoder) | |
4816 | intel_wait_for_vblank(dev, pipe); | |
4817 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4818 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
4819 | } | |
4820 | ||
4821 | /* IPS only exists on ULT machines and is tied to pipe A. */ | |
4822 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4823 | { | |
4824 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; | |
4825 | } | |
4826 | ||
4827 | static void haswell_crtc_enable(struct drm_crtc *crtc) | |
4828 | { | |
4829 | struct drm_device *dev = crtc->dev; | |
4830 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4831 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4832 | struct intel_encoder *encoder; | |
4833 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; | |
4834 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; | |
4835 | struct intel_crtc_state *pipe_config = | |
4836 | to_intel_crtc_state(crtc->state); | |
4837 | ||
4838 | if (WARN_ON(intel_crtc->active)) | |
4839 | return; | |
4840 | ||
4841 | if (intel_crtc->config->has_pch_encoder) | |
4842 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
4843 | false); | |
4844 | ||
4845 | if (intel_crtc->config->shared_dpll) | |
4846 | intel_enable_shared_dpll(intel_crtc); | |
4847 | ||
4848 | if (intel_crtc->config->has_dp_encoder) | |
4849 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
4850 | ||
4851 | if (!intel_crtc->config->has_dsi_encoder) | |
4852 | intel_set_pipe_timings(intel_crtc); | |
4853 | ||
4854 | intel_set_pipe_src_size(intel_crtc); | |
4855 | ||
4856 | if (cpu_transcoder != TRANSCODER_EDP && | |
4857 | !transcoder_is_dsi(cpu_transcoder)) { | |
4858 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
4859 | intel_crtc->config->pixel_multiplier - 1); | |
4860 | } | |
4861 | ||
4862 | if (intel_crtc->config->has_pch_encoder) { | |
4863 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
4864 | &intel_crtc->config->fdi_m_n, NULL); | |
4865 | } | |
4866 | ||
4867 | if (!intel_crtc->config->has_dsi_encoder) | |
4868 | haswell_set_pipeconf(crtc); | |
4869 | ||
4870 | haswell_set_pipemisc(crtc); | |
4871 | ||
4872 | intel_color_set_csc(&pipe_config->base); | |
4873 | ||
4874 | intel_crtc->active = true; | |
4875 | ||
4876 | if (intel_crtc->config->has_pch_encoder) | |
4877 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4878 | else | |
4879 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4880 | ||
4881 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
4882 | if (encoder->pre_enable) | |
4883 | encoder->pre_enable(encoder); | |
4884 | } | |
4885 | ||
4886 | if (intel_crtc->config->has_pch_encoder) | |
4887 | dev_priv->display.fdi_link_train(crtc); | |
4888 | ||
4889 | if (!intel_crtc->config->has_dsi_encoder) | |
4890 | intel_ddi_enable_pipe_clock(intel_crtc); | |
4891 | ||
4892 | if (INTEL_INFO(dev)->gen >= 9) | |
4893 | skylake_pfit_enable(intel_crtc); | |
4894 | else | |
4895 | ironlake_pfit_enable(intel_crtc); | |
4896 | ||
4897 | /* | |
4898 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4899 | * clocks enabled | |
4900 | */ | |
4901 | intel_color_load_luts(&pipe_config->base); | |
4902 | ||
4903 | intel_ddi_set_pipe_settings(crtc); | |
4904 | if (!intel_crtc->config->has_dsi_encoder) | |
4905 | intel_ddi_enable_transcoder_func(crtc); | |
4906 | ||
4907 | if (dev_priv->display.initial_watermarks != NULL) | |
4908 | dev_priv->display.initial_watermarks(pipe_config); | |
4909 | else | |
4910 | intel_update_watermarks(crtc); | |
4911 | ||
4912 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
4913 | if (!intel_crtc->config->has_dsi_encoder) | |
4914 | intel_enable_pipe(intel_crtc); | |
4915 | ||
4916 | if (intel_crtc->config->has_pch_encoder) | |
4917 | lpt_pch_enable(crtc); | |
4918 | ||
4919 | if (intel_crtc->config->dp_encoder_is_mst) | |
4920 | intel_ddi_set_vc_payload_alloc(crtc, true); | |
4921 | ||
4922 | assert_vblank_disabled(crtc); | |
4923 | drm_crtc_vblank_on(crtc); | |
4924 | ||
4925 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
4926 | encoder->enable(encoder); | |
4927 | intel_opregion_notify_encoder(encoder, true); | |
4928 | } | |
4929 | ||
4930 | if (intel_crtc->config->has_pch_encoder) { | |
4931 | intel_wait_for_vblank(dev, pipe); | |
4932 | intel_wait_for_vblank(dev, pipe); | |
4933 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4934 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
4935 | true); | |
4936 | } | |
4937 | ||
4938 | /* If we change the relative order between pipe/planes enabling, we need | |
4939 | * to change the workaround. */ | |
4940 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; | |
4941 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
4942 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4943 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4944 | } | |
4945 | } | |
4946 | ||
4947 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) | |
4948 | { | |
4949 | struct drm_device *dev = crtc->base.dev; | |
4950 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4951 | int pipe = crtc->pipe; | |
4952 | ||
4953 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4954 | * it's in use. The hw state code will make sure we get this right. */ | |
4955 | if (force || crtc->config->pch_pfit.enabled) { | |
4956 | I915_WRITE(PF_CTL(pipe), 0); | |
4957 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4958 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4959 | } | |
4960 | } | |
4961 | ||
4962 | static void ironlake_crtc_disable(struct drm_crtc *crtc) | |
4963 | { | |
4964 | struct drm_device *dev = crtc->dev; | |
4965 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4966 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4967 | struct intel_encoder *encoder; | |
4968 | int pipe = intel_crtc->pipe; | |
4969 | ||
4970 | /* | |
4971 | * Sometimes spurious CPU pipe underruns happen when the | |
4972 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
4973 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
4974 | */ | |
4975 | if (intel_crtc->config->has_pch_encoder) { | |
4976 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4977 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4978 | } | |
4979 | ||
4980 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4981 | encoder->disable(encoder); | |
4982 | ||
4983 | drm_crtc_vblank_off(crtc); | |
4984 | assert_vblank_disabled(crtc); | |
4985 | ||
4986 | intel_disable_pipe(intel_crtc); | |
4987 | ||
4988 | ironlake_pfit_disable(intel_crtc, false); | |
4989 | ||
4990 | if (intel_crtc->config->has_pch_encoder) | |
4991 | ironlake_fdi_disable(crtc); | |
4992 | ||
4993 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4994 | if (encoder->post_disable) | |
4995 | encoder->post_disable(encoder); | |
4996 | ||
4997 | if (intel_crtc->config->has_pch_encoder) { | |
4998 | ironlake_disable_pch_transcoder(dev_priv, pipe); | |
4999 | ||
5000 | if (HAS_PCH_CPT(dev)) { | |
5001 | i915_reg_t reg; | |
5002 | u32 temp; | |
5003 | ||
5004 | /* disable TRANS_DP_CTL */ | |
5005 | reg = TRANS_DP_CTL(pipe); | |
5006 | temp = I915_READ(reg); | |
5007 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5008 | TRANS_DP_PORT_SEL_MASK); | |
5009 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5010 | I915_WRITE(reg, temp); | |
5011 | ||
5012 | /* disable DPLL_SEL */ | |
5013 | temp = I915_READ(PCH_DPLL_SEL); | |
5014 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); | |
5015 | I915_WRITE(PCH_DPLL_SEL, temp); | |
5016 | } | |
5017 | ||
5018 | ironlake_fdi_pll_disable(intel_crtc); | |
5019 | } | |
5020 | ||
5021 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5022 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
5023 | } | |
5024 | ||
5025 | static void haswell_crtc_disable(struct drm_crtc *crtc) | |
5026 | { | |
5027 | struct drm_device *dev = crtc->dev; | |
5028 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5029 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5030 | struct intel_encoder *encoder; | |
5031 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; | |
5032 | ||
5033 | if (intel_crtc->config->has_pch_encoder) | |
5034 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5035 | false); | |
5036 | ||
5037 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
5038 | intel_opregion_notify_encoder(encoder, false); | |
5039 | encoder->disable(encoder); | |
5040 | } | |
5041 | ||
5042 | drm_crtc_vblank_off(crtc); | |
5043 | assert_vblank_disabled(crtc); | |
5044 | ||
5045 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
5046 | if (!intel_crtc->config->has_dsi_encoder) | |
5047 | intel_disable_pipe(intel_crtc); | |
5048 | ||
5049 | if (intel_crtc->config->dp_encoder_is_mst) | |
5050 | intel_ddi_set_vc_payload_alloc(crtc, false); | |
5051 | ||
5052 | if (!intel_crtc->config->has_dsi_encoder) | |
5053 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); | |
5054 | ||
5055 | if (INTEL_INFO(dev)->gen >= 9) | |
5056 | skylake_scaler_disable(intel_crtc); | |
5057 | else | |
5058 | ironlake_pfit_disable(intel_crtc, false); | |
5059 | ||
5060 | if (!intel_crtc->config->has_dsi_encoder) | |
5061 | intel_ddi_disable_pipe_clock(intel_crtc); | |
5062 | ||
5063 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
5064 | if (encoder->post_disable) | |
5065 | encoder->post_disable(encoder); | |
5066 | ||
5067 | if (intel_crtc->config->has_pch_encoder) { | |
5068 | lpt_disable_pch_transcoder(dev_priv); | |
5069 | lpt_disable_iclkip(dev_priv); | |
5070 | intel_ddi_fdi_disable(crtc); | |
5071 | ||
5072 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5073 | true); | |
5074 | } | |
5075 | } | |
5076 | ||
5077 | static void i9xx_pfit_enable(struct intel_crtc *crtc) | |
5078 | { | |
5079 | struct drm_device *dev = crtc->base.dev; | |
5080 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5081 | struct intel_crtc_state *pipe_config = crtc->config; | |
5082 | ||
5083 | if (!pipe_config->gmch_pfit.control) | |
5084 | return; | |
5085 | ||
5086 | /* | |
5087 | * The panel fitter should only be adjusted whilst the pipe is disabled, | |
5088 | * according to register description and PRM. | |
5089 | */ | |
5090 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); | |
5091 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
5092 | ||
5093 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); | |
5094 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5095 | ||
5096 | /* Border color in case we don't scale up to the full screen. Black by | |
5097 | * default, change to something else for debugging. */ | |
5098 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
5099 | } | |
5100 | ||
5101 | static enum intel_display_power_domain port_to_power_domain(enum port port) | |
5102 | { | |
5103 | switch (port) { | |
5104 | case PORT_A: | |
5105 | return POWER_DOMAIN_PORT_DDI_A_LANES; | |
5106 | case PORT_B: | |
5107 | return POWER_DOMAIN_PORT_DDI_B_LANES; | |
5108 | case PORT_C: | |
5109 | return POWER_DOMAIN_PORT_DDI_C_LANES; | |
5110 | case PORT_D: | |
5111 | return POWER_DOMAIN_PORT_DDI_D_LANES; | |
5112 | case PORT_E: | |
5113 | return POWER_DOMAIN_PORT_DDI_E_LANES; | |
5114 | default: | |
5115 | MISSING_CASE(port); | |
5116 | return POWER_DOMAIN_PORT_OTHER; | |
5117 | } | |
5118 | } | |
5119 | ||
5120 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) | |
5121 | { | |
5122 | switch (port) { | |
5123 | case PORT_A: | |
5124 | return POWER_DOMAIN_AUX_A; | |
5125 | case PORT_B: | |
5126 | return POWER_DOMAIN_AUX_B; | |
5127 | case PORT_C: | |
5128 | return POWER_DOMAIN_AUX_C; | |
5129 | case PORT_D: | |
5130 | return POWER_DOMAIN_AUX_D; | |
5131 | case PORT_E: | |
5132 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5133 | return POWER_DOMAIN_AUX_D; | |
5134 | default: | |
5135 | MISSING_CASE(port); | |
5136 | return POWER_DOMAIN_AUX_A; | |
5137 | } | |
5138 | } | |
5139 | ||
5140 | enum intel_display_power_domain | |
5141 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5142 | { | |
5143 | struct drm_device *dev = intel_encoder->base.dev; | |
5144 | struct intel_digital_port *intel_dig_port; | |
5145 | ||
5146 | switch (intel_encoder->type) { | |
5147 | case INTEL_OUTPUT_UNKNOWN: | |
5148 | /* Only DDI platforms should ever use this output type */ | |
5149 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5150 | case INTEL_OUTPUT_DISPLAYPORT: | |
5151 | case INTEL_OUTPUT_HDMI: | |
5152 | case INTEL_OUTPUT_EDP: | |
5153 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5154 | return port_to_power_domain(intel_dig_port->port); | |
5155 | case INTEL_OUTPUT_DP_MST: | |
5156 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5157 | return port_to_power_domain(intel_dig_port->port); | |
5158 | case INTEL_OUTPUT_ANALOG: | |
5159 | return POWER_DOMAIN_PORT_CRT; | |
5160 | case INTEL_OUTPUT_DSI: | |
5161 | return POWER_DOMAIN_PORT_DSI; | |
5162 | default: | |
5163 | return POWER_DOMAIN_PORT_OTHER; | |
5164 | } | |
5165 | } | |
5166 | ||
5167 | enum intel_display_power_domain | |
5168 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5169 | { | |
5170 | struct drm_device *dev = intel_encoder->base.dev; | |
5171 | struct intel_digital_port *intel_dig_port; | |
5172 | ||
5173 | switch (intel_encoder->type) { | |
5174 | case INTEL_OUTPUT_UNKNOWN: | |
5175 | case INTEL_OUTPUT_HDMI: | |
5176 | /* | |
5177 | * Only DDI platforms should ever use these output types. | |
5178 | * We can get here after the HDMI detect code has already set | |
5179 | * the type of the shared encoder. Since we can't be sure | |
5180 | * what's the status of the given connectors, play safe and | |
5181 | * run the DP detection too. | |
5182 | */ | |
5183 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5184 | case INTEL_OUTPUT_DISPLAYPORT: | |
5185 | case INTEL_OUTPUT_EDP: | |
5186 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5187 | return port_to_aux_power_domain(intel_dig_port->port); | |
5188 | case INTEL_OUTPUT_DP_MST: | |
5189 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5190 | return port_to_aux_power_domain(intel_dig_port->port); | |
5191 | default: | |
5192 | MISSING_CASE(intel_encoder->type); | |
5193 | return POWER_DOMAIN_AUX_A; | |
5194 | } | |
5195 | } | |
5196 | ||
5197 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, | |
5198 | struct intel_crtc_state *crtc_state) | |
5199 | { | |
5200 | struct drm_device *dev = crtc->dev; | |
5201 | struct drm_encoder *encoder; | |
5202 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5203 | enum pipe pipe = intel_crtc->pipe; | |
5204 | unsigned long mask; | |
5205 | enum transcoder transcoder = crtc_state->cpu_transcoder; | |
5206 | ||
5207 | if (!crtc_state->base.active) | |
5208 | return 0; | |
5209 | ||
5210 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
5211 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
5212 | if (crtc_state->pch_pfit.enabled || | |
5213 | crtc_state->pch_pfit.force_thru) | |
5214 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); | |
5215 | ||
5216 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { | |
5217 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5218 | ||
5219 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
5220 | } | |
5221 | ||
5222 | if (crtc_state->shared_dpll) | |
5223 | mask |= BIT(POWER_DOMAIN_PLLS); | |
5224 | ||
5225 | return mask; | |
5226 | } | |
5227 | ||
5228 | static unsigned long | |
5229 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, | |
5230 | struct intel_crtc_state *crtc_state) | |
5231 | { | |
5232 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
5233 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5234 | enum intel_display_power_domain domain; | |
5235 | unsigned long domains, new_domains, old_domains; | |
5236 | ||
5237 | old_domains = intel_crtc->enabled_power_domains; | |
5238 | intel_crtc->enabled_power_domains = new_domains = | |
5239 | get_crtc_power_domains(crtc, crtc_state); | |
5240 | ||
5241 | domains = new_domains & ~old_domains; | |
5242 | ||
5243 | for_each_power_domain(domain, domains) | |
5244 | intel_display_power_get(dev_priv, domain); | |
5245 | ||
5246 | return old_domains & ~new_domains; | |
5247 | } | |
5248 | ||
5249 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5250 | unsigned long domains) | |
5251 | { | |
5252 | enum intel_display_power_domain domain; | |
5253 | ||
5254 | for_each_power_domain(domain, domains) | |
5255 | intel_display_power_put(dev_priv, domain); | |
5256 | } | |
5257 | ||
5258 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) | |
5259 | { | |
5260 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5261 | ||
5262 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5263 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5264 | return max_cdclk_freq; | |
5265 | else if (IS_CHERRYVIEW(dev_priv)) | |
5266 | return max_cdclk_freq*95/100; | |
5267 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5268 | return 2*max_cdclk_freq*90/100; | |
5269 | else | |
5270 | return max_cdclk_freq*90/100; | |
5271 | } | |
5272 | ||
5273 | static void intel_update_max_cdclk(struct drm_device *dev) | |
5274 | { | |
5275 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5276 | ||
5277 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { | |
5278 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; | |
5279 | ||
5280 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
5281 | dev_priv->max_cdclk_freq = 675000; | |
5282 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
5283 | dev_priv->max_cdclk_freq = 540000; | |
5284 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
5285 | dev_priv->max_cdclk_freq = 450000; | |
5286 | else | |
5287 | dev_priv->max_cdclk_freq = 337500; | |
5288 | } else if (IS_BROXTON(dev)) { | |
5289 | dev_priv->max_cdclk_freq = 624000; | |
5290 | } else if (IS_BROADWELL(dev)) { | |
5291 | /* | |
5292 | * FIXME with extra cooling we can allow | |
5293 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5294 | * How can we know if extra cooling is | |
5295 | * available? PCI ID, VTB, something else? | |
5296 | */ | |
5297 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5298 | dev_priv->max_cdclk_freq = 450000; | |
5299 | else if (IS_BDW_ULX(dev)) | |
5300 | dev_priv->max_cdclk_freq = 450000; | |
5301 | else if (IS_BDW_ULT(dev)) | |
5302 | dev_priv->max_cdclk_freq = 540000; | |
5303 | else | |
5304 | dev_priv->max_cdclk_freq = 675000; | |
5305 | } else if (IS_CHERRYVIEW(dev)) { | |
5306 | dev_priv->max_cdclk_freq = 320000; | |
5307 | } else if (IS_VALLEYVIEW(dev)) { | |
5308 | dev_priv->max_cdclk_freq = 400000; | |
5309 | } else { | |
5310 | /* otherwise assume cdclk is fixed */ | |
5311 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5312 | } | |
5313 | ||
5314 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); | |
5315 | ||
5316 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", | |
5317 | dev_priv->max_cdclk_freq); | |
5318 | ||
5319 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5320 | dev_priv->max_dotclk_freq); | |
5321 | } | |
5322 | ||
5323 | static void intel_update_cdclk(struct drm_device *dev) | |
5324 | { | |
5325 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5326 | ||
5327 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5328 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5329 | dev_priv->cdclk_freq); | |
5330 | ||
5331 | /* | |
5332 | * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): | |
5333 | * Programmng [sic] note: bit[9:2] should be programmed to the number | |
5334 | * of cdclk that generates 4MHz reference clock freq which is used to | |
5335 | * generate GMBus clock. This will vary with the cdclk freq. | |
5336 | */ | |
5337 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
5338 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); | |
5339 | ||
5340 | if (dev_priv->max_cdclk_freq == 0) | |
5341 | intel_update_max_cdclk(dev); | |
5342 | } | |
5343 | ||
5344 | static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int frequency) | |
5345 | { | |
5346 | uint32_t divider; | |
5347 | uint32_t ratio; | |
5348 | uint32_t current_freq; | |
5349 | int ret; | |
5350 | ||
5351 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5352 | switch (frequency) { | |
5353 | case 144000: | |
5354 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5355 | ratio = BXT_DE_PLL_RATIO(60); | |
5356 | break; | |
5357 | case 288000: | |
5358 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5359 | ratio = BXT_DE_PLL_RATIO(60); | |
5360 | break; | |
5361 | case 384000: | |
5362 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5363 | ratio = BXT_DE_PLL_RATIO(60); | |
5364 | break; | |
5365 | case 576000: | |
5366 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5367 | ratio = BXT_DE_PLL_RATIO(60); | |
5368 | break; | |
5369 | case 624000: | |
5370 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5371 | ratio = BXT_DE_PLL_RATIO(65); | |
5372 | break; | |
5373 | case 19200: | |
5374 | /* | |
5375 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5376 | * to suppress GCC warning. | |
5377 | */ | |
5378 | ratio = 0; | |
5379 | divider = 0; | |
5380 | break; | |
5381 | default: | |
5382 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5383 | ||
5384 | return; | |
5385 | } | |
5386 | ||
5387 | mutex_lock(&dev_priv->rps.hw_lock); | |
5388 | /* Inform power controller of upcoming frequency change */ | |
5389 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5390 | 0x80000000); | |
5391 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5392 | ||
5393 | if (ret) { | |
5394 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5395 | ret, frequency); | |
5396 | return; | |
5397 | } | |
5398 | ||
5399 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5400 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5401 | current_freq = current_freq * 500 + 1000; | |
5402 | ||
5403 | /* | |
5404 | * DE PLL has to be disabled when | |
5405 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5406 | * - before setting to 624MHz (PLL needs toggling) | |
5407 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5408 | */ | |
5409 | if (frequency == 19200 || frequency == 624000 || | |
5410 | current_freq == 624000) { | |
5411 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5412 | /* Timeout 200us */ | |
5413 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5414 | 1)) | |
5415 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5416 | } | |
5417 | ||
5418 | if (frequency != 19200) { | |
5419 | uint32_t val; | |
5420 | ||
5421 | val = I915_READ(BXT_DE_PLL_CTL); | |
5422 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5423 | val |= ratio; | |
5424 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5425 | ||
5426 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5427 | /* Timeout 200us */ | |
5428 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5429 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5430 | ||
5431 | val = I915_READ(CDCLK_CTL); | |
5432 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5433 | val |= divider; | |
5434 | /* | |
5435 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5436 | * enable otherwise. | |
5437 | */ | |
5438 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5439 | if (frequency >= 500000) | |
5440 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5441 | ||
5442 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5443 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5444 | val |= (frequency - 1000) / 500; | |
5445 | I915_WRITE(CDCLK_CTL, val); | |
5446 | } | |
5447 | ||
5448 | mutex_lock(&dev_priv->rps.hw_lock); | |
5449 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5450 | DIV_ROUND_UP(frequency, 25000)); | |
5451 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5452 | ||
5453 | if (ret) { | |
5454 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5455 | ret, frequency); | |
5456 | return; | |
5457 | } | |
5458 | ||
5459 | intel_update_cdclk(dev_priv->dev); | |
5460 | } | |
5461 | ||
5462 | static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv) | |
5463 | { | |
5464 | if (!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE)) | |
5465 | return false; | |
5466 | ||
5467 | /* TODO: Check for a valid CDCLK rate */ | |
5468 | ||
5469 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_REQUEST)) { | |
5470 | DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power not requested\n"); | |
5471 | ||
5472 | return false; | |
5473 | } | |
5474 | ||
5475 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) { | |
5476 | DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power hasn't settled\n"); | |
5477 | ||
5478 | return false; | |
5479 | } | |
5480 | ||
5481 | return true; | |
5482 | } | |
5483 | ||
5484 | bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv) | |
5485 | { | |
5486 | return broxton_cdclk_is_enabled(dev_priv); | |
5487 | } | |
5488 | ||
5489 | void broxton_init_cdclk(struct drm_i915_private *dev_priv) | |
5490 | { | |
5491 | /* check if cd clock is enabled */ | |
5492 | if (broxton_cdclk_is_enabled(dev_priv)) { | |
5493 | DRM_DEBUG_KMS("CDCLK already enabled, won't reprogram it\n"); | |
5494 | return; | |
5495 | } | |
5496 | ||
5497 | DRM_DEBUG_KMS("CDCLK not enabled, enabling it\n"); | |
5498 | ||
5499 | /* | |
5500 | * FIXME: | |
5501 | * - The initial CDCLK needs to be read from VBT. | |
5502 | * Need to make this change after VBT has changes for BXT. | |
5503 | * - check if setting the max (or any) cdclk freq is really necessary | |
5504 | * here, it belongs to modeset time | |
5505 | */ | |
5506 | broxton_set_cdclk(dev_priv, 624000); | |
5507 | ||
5508 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5509 | POSTING_READ(DBUF_CTL); | |
5510 | ||
5511 | udelay(10); | |
5512 | ||
5513 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5514 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5515 | } | |
5516 | ||
5517 | void broxton_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5518 | { | |
5519 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5520 | POSTING_READ(DBUF_CTL); | |
5521 | ||
5522 | udelay(10); | |
5523 | ||
5524 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5525 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5526 | ||
5527 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5528 | broxton_set_cdclk(dev_priv, 19200); | |
5529 | } | |
5530 | ||
5531 | static const struct skl_cdclk_entry { | |
5532 | unsigned int freq; | |
5533 | unsigned int vco; | |
5534 | } skl_cdclk_frequencies[] = { | |
5535 | { .freq = 308570, .vco = 8640 }, | |
5536 | { .freq = 337500, .vco = 8100 }, | |
5537 | { .freq = 432000, .vco = 8640 }, | |
5538 | { .freq = 450000, .vco = 8100 }, | |
5539 | { .freq = 540000, .vco = 8100 }, | |
5540 | { .freq = 617140, .vco = 8640 }, | |
5541 | { .freq = 675000, .vco = 8100 }, | |
5542 | }; | |
5543 | ||
5544 | static unsigned int skl_cdclk_decimal(unsigned int freq) | |
5545 | { | |
5546 | return (freq - 1000) / 500; | |
5547 | } | |
5548 | ||
5549 | static unsigned int skl_cdclk_get_vco(unsigned int freq) | |
5550 | { | |
5551 | unsigned int i; | |
5552 | ||
5553 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5554 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5555 | ||
5556 | if (e->freq == freq) | |
5557 | return e->vco; | |
5558 | } | |
5559 | ||
5560 | return 8100; | |
5561 | } | |
5562 | ||
5563 | static void | |
5564 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) | |
5565 | { | |
5566 | unsigned int min_freq; | |
5567 | u32 val; | |
5568 | ||
5569 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
5570 | val = I915_READ(CDCLK_CTL); | |
5571 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; | |
5572 | val |= CDCLK_FREQ_337_308; | |
5573 | ||
5574 | if (required_vco == 8640) | |
5575 | min_freq = 308570; | |
5576 | else | |
5577 | min_freq = 337500; | |
5578 | ||
5579 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); | |
5580 | ||
5581 | I915_WRITE(CDCLK_CTL, val); | |
5582 | POSTING_READ(CDCLK_CTL); | |
5583 | ||
5584 | /* | |
5585 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5586 | * taking into account the VCO required to operate the eDP panel at the | |
5587 | * desired frequency. The usual DP link rates operate with a VCO of | |
5588 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5589 | * The modeset code is responsible for the selection of the exact link | |
5590 | * rate later on, with the constraint of choosing a frequency that | |
5591 | * works with required_vco. | |
5592 | */ | |
5593 | val = I915_READ(DPLL_CTRL1); | |
5594 | ||
5595 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5596 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5597 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
5598 | if (required_vco == 8640) | |
5599 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
5600 | SKL_DPLL0); | |
5601 | else | |
5602 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5603 | SKL_DPLL0); | |
5604 | ||
5605 | I915_WRITE(DPLL_CTRL1, val); | |
5606 | POSTING_READ(DPLL_CTRL1); | |
5607 | ||
5608 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5609 | ||
5610 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5611 | DRM_ERROR("DPLL0 not locked\n"); | |
5612 | } | |
5613 | ||
5614 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) | |
5615 | { | |
5616 | int ret; | |
5617 | u32 val; | |
5618 | ||
5619 | /* inform PCU we want to change CDCLK */ | |
5620 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5621 | mutex_lock(&dev_priv->rps.hw_lock); | |
5622 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5623 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5624 | ||
5625 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5626 | } | |
5627 | ||
5628 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5629 | { | |
5630 | unsigned int i; | |
5631 | ||
5632 | for (i = 0; i < 15; i++) { | |
5633 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5634 | return true; | |
5635 | udelay(10); | |
5636 | } | |
5637 | ||
5638 | return false; | |
5639 | } | |
5640 | ||
5641 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) | |
5642 | { | |
5643 | struct drm_device *dev = dev_priv->dev; | |
5644 | u32 freq_select, pcu_ack; | |
5645 | ||
5646 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); | |
5647 | ||
5648 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5649 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5650 | return; | |
5651 | } | |
5652 | ||
5653 | /* set CDCLK_CTL */ | |
5654 | switch(freq) { | |
5655 | case 450000: | |
5656 | case 432000: | |
5657 | freq_select = CDCLK_FREQ_450_432; | |
5658 | pcu_ack = 1; | |
5659 | break; | |
5660 | case 540000: | |
5661 | freq_select = CDCLK_FREQ_540; | |
5662 | pcu_ack = 2; | |
5663 | break; | |
5664 | case 308570: | |
5665 | case 337500: | |
5666 | default: | |
5667 | freq_select = CDCLK_FREQ_337_308; | |
5668 | pcu_ack = 0; | |
5669 | break; | |
5670 | case 617140: | |
5671 | case 675000: | |
5672 | freq_select = CDCLK_FREQ_675_617; | |
5673 | pcu_ack = 3; | |
5674 | break; | |
5675 | } | |
5676 | ||
5677 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); | |
5678 | POSTING_READ(CDCLK_CTL); | |
5679 | ||
5680 | /* inform PCU of the change */ | |
5681 | mutex_lock(&dev_priv->rps.hw_lock); | |
5682 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5683 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5684 | ||
5685 | intel_update_cdclk(dev); | |
5686 | } | |
5687 | ||
5688 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5689 | { | |
5690 | /* disable DBUF power */ | |
5691 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5692 | POSTING_READ(DBUF_CTL); | |
5693 | ||
5694 | udelay(10); | |
5695 | ||
5696 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5697 | DRM_ERROR("DBuf power disable timeout\n"); | |
5698 | ||
5699 | /* disable DPLL0 */ | |
5700 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5701 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5702 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5703 | } | |
5704 | ||
5705 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5706 | { | |
5707 | unsigned int required_vco; | |
5708 | ||
5709 | /* DPLL0 not enabled (happens on early BIOS versions) */ | |
5710 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { | |
5711 | /* enable DPLL0 */ | |
5712 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); | |
5713 | skl_dpll0_enable(dev_priv, required_vco); | |
5714 | } | |
5715 | ||
5716 | /* set CDCLK to the frequency the BIOS chose */ | |
5717 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5718 | ||
5719 | /* enable DBUF power */ | |
5720 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5721 | POSTING_READ(DBUF_CTL); | |
5722 | ||
5723 | udelay(10); | |
5724 | ||
5725 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5726 | DRM_ERROR("DBuf power enable timeout\n"); | |
5727 | } | |
5728 | ||
5729 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) | |
5730 | { | |
5731 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
5732 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
5733 | int freq = dev_priv->skl_boot_cdclk; | |
5734 | ||
5735 | /* | |
5736 | * check if the pre-os intialized the display | |
5737 | * There is SWF18 scratchpad register defined which is set by the | |
5738 | * pre-os which can be used by the OS drivers to check the status | |
5739 | */ | |
5740 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
5741 | goto sanitize; | |
5742 | ||
5743 | /* Is PLL enabled and locked ? */ | |
5744 | if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) | |
5745 | goto sanitize; | |
5746 | ||
5747 | /* DPLL okay; verify the cdclock | |
5748 | * | |
5749 | * Noticed in some instances that the freq selection is correct but | |
5750 | * decimal part is programmed wrong from BIOS where pre-os does not | |
5751 | * enable display. Verify the same as well. | |
5752 | */ | |
5753 | if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq))) | |
5754 | /* All well; nothing to sanitize */ | |
5755 | return false; | |
5756 | sanitize: | |
5757 | /* | |
5758 | * As of now initialize with max cdclk till | |
5759 | * we get dynamic cdclk support | |
5760 | * */ | |
5761 | dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq; | |
5762 | skl_init_cdclk(dev_priv); | |
5763 | ||
5764 | /* we did have to sanitize */ | |
5765 | return true; | |
5766 | } | |
5767 | ||
5768 | /* Adjust CDclk dividers to allow high res or save power if possible */ | |
5769 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5770 | { | |
5771 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5772 | u32 val, cmd; | |
5773 | ||
5774 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) | |
5775 | != dev_priv->cdclk_freq); | |
5776 | ||
5777 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ | |
5778 | cmd = 2; | |
5779 | else if (cdclk == 266667) | |
5780 | cmd = 1; | |
5781 | else | |
5782 | cmd = 0; | |
5783 | ||
5784 | mutex_lock(&dev_priv->rps.hw_lock); | |
5785 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5786 | val &= ~DSPFREQGUAR_MASK; | |
5787 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5788 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5789 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5790 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5791 | 50)) { | |
5792 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5793 | } | |
5794 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5795 | ||
5796 | mutex_lock(&dev_priv->sb_lock); | |
5797 | ||
5798 | if (cdclk == 400000) { | |
5799 | u32 divider; | |
5800 | ||
5801 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5802 | ||
5803 | /* adjust cdclk divider */ | |
5804 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
5805 | val &= ~CCK_FREQUENCY_VALUES; | |
5806 | val |= divider; | |
5807 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
5808 | ||
5809 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
5810 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
5811 | 50)) | |
5812 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5813 | } | |
5814 | ||
5815 | /* adjust self-refresh exit latency value */ | |
5816 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5817 | val &= ~0x7f; | |
5818 | ||
5819 | /* | |
5820 | * For high bandwidth configs, we set a higher latency in the bunit | |
5821 | * so that the core display fetch happens in time to avoid underruns. | |
5822 | */ | |
5823 | if (cdclk == 400000) | |
5824 | val |= 4500 / 250; /* 4.5 usec */ | |
5825 | else | |
5826 | val |= 3000 / 250; /* 3.0 usec */ | |
5827 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
5828 | ||
5829 | mutex_unlock(&dev_priv->sb_lock); | |
5830 | ||
5831 | intel_update_cdclk(dev); | |
5832 | } | |
5833 | ||
5834 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) | |
5835 | { | |
5836 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5837 | u32 val, cmd; | |
5838 | ||
5839 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) | |
5840 | != dev_priv->cdclk_freq); | |
5841 | ||
5842 | switch (cdclk) { | |
5843 | case 333333: | |
5844 | case 320000: | |
5845 | case 266667: | |
5846 | case 200000: | |
5847 | break; | |
5848 | default: | |
5849 | MISSING_CASE(cdclk); | |
5850 | return; | |
5851 | } | |
5852 | ||
5853 | /* | |
5854 | * Specs are full of misinformation, but testing on actual | |
5855 | * hardware has shown that we just need to write the desired | |
5856 | * CCK divider into the Punit register. | |
5857 | */ | |
5858 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5859 | ||
5860 | mutex_lock(&dev_priv->rps.hw_lock); | |
5861 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5862 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5863 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5864 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5865 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5866 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5867 | 50)) { | |
5868 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5869 | } | |
5870 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5871 | ||
5872 | intel_update_cdclk(dev); | |
5873 | } | |
5874 | ||
5875 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, | |
5876 | int max_pixclk) | |
5877 | { | |
5878 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; | |
5879 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; | |
5880 | ||
5881 | /* | |
5882 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5883 | * 200MHz | |
5884 | * 267MHz | |
5885 | * 320/333MHz (depends on HPLL freq) | |
5886 | * 400MHz (VLV only) | |
5887 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5888 | * of the lower bin and adjust if needed. | |
5889 | * | |
5890 | * We seem to get an unstable or solid color picture at 200MHz. | |
5891 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5892 | * are off. | |
5893 | */ | |
5894 | if (!IS_CHERRYVIEW(dev_priv) && | |
5895 | max_pixclk > freq_320*limit/100) | |
5896 | return 400000; | |
5897 | else if (max_pixclk > 266667*limit/100) | |
5898 | return freq_320; | |
5899 | else if (max_pixclk > 0) | |
5900 | return 266667; | |
5901 | else | |
5902 | return 200000; | |
5903 | } | |
5904 | ||
5905 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, | |
5906 | int max_pixclk) | |
5907 | { | |
5908 | /* | |
5909 | * FIXME: | |
5910 | * - remove the guardband, it's not needed on BXT | |
5911 | * - set 19.2MHz bypass frequency if there are no active pipes | |
5912 | */ | |
5913 | if (max_pixclk > 576000*9/10) | |
5914 | return 624000; | |
5915 | else if (max_pixclk > 384000*9/10) | |
5916 | return 576000; | |
5917 | else if (max_pixclk > 288000*9/10) | |
5918 | return 384000; | |
5919 | else if (max_pixclk > 144000*9/10) | |
5920 | return 288000; | |
5921 | else | |
5922 | return 144000; | |
5923 | } | |
5924 | ||
5925 | /* Compute the max pixel clock for new configuration. */ | |
5926 | static int intel_mode_max_pixclk(struct drm_device *dev, | |
5927 | struct drm_atomic_state *state) | |
5928 | { | |
5929 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
5930 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5931 | struct drm_crtc *crtc; | |
5932 | struct drm_crtc_state *crtc_state; | |
5933 | unsigned max_pixclk = 0, i; | |
5934 | enum pipe pipe; | |
5935 | ||
5936 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, | |
5937 | sizeof(intel_state->min_pixclk)); | |
5938 | ||
5939 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
5940 | int pixclk = 0; | |
5941 | ||
5942 | if (crtc_state->enable) | |
5943 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
5944 | ||
5945 | intel_state->min_pixclk[i] = pixclk; | |
5946 | } | |
5947 | ||
5948 | for_each_pipe(dev_priv, pipe) | |
5949 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
5950 | ||
5951 | return max_pixclk; | |
5952 | } | |
5953 | ||
5954 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) | |
5955 | { | |
5956 | struct drm_device *dev = state->dev; | |
5957 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5958 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
5959 | struct intel_atomic_state *intel_state = | |
5960 | to_intel_atomic_state(state); | |
5961 | ||
5962 | if (max_pixclk < 0) | |
5963 | return max_pixclk; | |
5964 | ||
5965 | intel_state->cdclk = intel_state->dev_cdclk = | |
5966 | valleyview_calc_cdclk(dev_priv, max_pixclk); | |
5967 | ||
5968 | if (!intel_state->active_crtcs) | |
5969 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
5970 | ||
5971 | return 0; | |
5972 | } | |
5973 | ||
5974 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) | |
5975 | { | |
5976 | struct drm_device *dev = state->dev; | |
5977 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5978 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
5979 | struct intel_atomic_state *intel_state = | |
5980 | to_intel_atomic_state(state); | |
5981 | ||
5982 | if (max_pixclk < 0) | |
5983 | return max_pixclk; | |
5984 | ||
5985 | intel_state->cdclk = intel_state->dev_cdclk = | |
5986 | broxton_calc_cdclk(dev_priv, max_pixclk); | |
5987 | ||
5988 | if (!intel_state->active_crtcs) | |
5989 | intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0); | |
5990 | ||
5991 | return 0; | |
5992 | } | |
5993 | ||
5994 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) | |
5995 | { | |
5996 | unsigned int credits, default_credits; | |
5997 | ||
5998 | if (IS_CHERRYVIEW(dev_priv)) | |
5999 | default_credits = PFI_CREDIT(12); | |
6000 | else | |
6001 | default_credits = PFI_CREDIT(8); | |
6002 | ||
6003 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { | |
6004 | /* CHV suggested value is 31 or 63 */ | |
6005 | if (IS_CHERRYVIEW(dev_priv)) | |
6006 | credits = PFI_CREDIT_63; | |
6007 | else | |
6008 | credits = PFI_CREDIT(15); | |
6009 | } else { | |
6010 | credits = default_credits; | |
6011 | } | |
6012 | ||
6013 | /* | |
6014 | * WA - write default credits before re-programming | |
6015 | * FIXME: should we also set the resend bit here? | |
6016 | */ | |
6017 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6018 | default_credits); | |
6019 | ||
6020 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6021 | credits | PFI_CREDIT_RESEND); | |
6022 | ||
6023 | /* | |
6024 | * FIXME is this guaranteed to clear | |
6025 | * immediately or should we poll for it? | |
6026 | */ | |
6027 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6028 | } | |
6029 | ||
6030 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) | |
6031 | { | |
6032 | struct drm_device *dev = old_state->dev; | |
6033 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6034 | struct intel_atomic_state *old_intel_state = | |
6035 | to_intel_atomic_state(old_state); | |
6036 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
6037 | ||
6038 | /* | |
6039 | * FIXME: We can end up here with all power domains off, yet | |
6040 | * with a CDCLK frequency other than the minimum. To account | |
6041 | * for this take the PIPE-A power domain, which covers the HW | |
6042 | * blocks needed for the following programming. This can be | |
6043 | * removed once it's guaranteed that we get here either with | |
6044 | * the minimum CDCLK set, or the required power domains | |
6045 | * enabled. | |
6046 | */ | |
6047 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
6048 | ||
6049 | if (IS_CHERRYVIEW(dev)) | |
6050 | cherryview_set_cdclk(dev, req_cdclk); | |
6051 | else | |
6052 | valleyview_set_cdclk(dev, req_cdclk); | |
6053 | ||
6054 | vlv_program_pfi_credits(dev_priv); | |
6055 | ||
6056 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); | |
6057 | } | |
6058 | ||
6059 | static void valleyview_crtc_enable(struct drm_crtc *crtc) | |
6060 | { | |
6061 | struct drm_device *dev = crtc->dev; | |
6062 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6063 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6064 | struct intel_encoder *encoder; | |
6065 | struct intel_crtc_state *pipe_config = | |
6066 | to_intel_crtc_state(crtc->state); | |
6067 | int pipe = intel_crtc->pipe; | |
6068 | ||
6069 | if (WARN_ON(intel_crtc->active)) | |
6070 | return; | |
6071 | ||
6072 | if (intel_crtc->config->has_dp_encoder) | |
6073 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
6074 | ||
6075 | intel_set_pipe_timings(intel_crtc); | |
6076 | intel_set_pipe_src_size(intel_crtc); | |
6077 | ||
6078 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { | |
6079 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6080 | ||
6081 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6082 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6083 | } | |
6084 | ||
6085 | i9xx_set_pipeconf(intel_crtc); | |
6086 | ||
6087 | intel_crtc->active = true; | |
6088 | ||
6089 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
6090 | ||
6091 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6092 | if (encoder->pre_pll_enable) | |
6093 | encoder->pre_pll_enable(encoder); | |
6094 | ||
6095 | if (IS_CHERRYVIEW(dev)) { | |
6096 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6097 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
6098 | } else { | |
6099 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6100 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
6101 | } | |
6102 | ||
6103 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6104 | if (encoder->pre_enable) | |
6105 | encoder->pre_enable(encoder); | |
6106 | ||
6107 | i9xx_pfit_enable(intel_crtc); | |
6108 | ||
6109 | intel_color_load_luts(&pipe_config->base); | |
6110 | ||
6111 | intel_update_watermarks(crtc); | |
6112 | intel_enable_pipe(intel_crtc); | |
6113 | ||
6114 | assert_vblank_disabled(crtc); | |
6115 | drm_crtc_vblank_on(crtc); | |
6116 | ||
6117 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6118 | encoder->enable(encoder); | |
6119 | } | |
6120 | ||
6121 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) | |
6122 | { | |
6123 | struct drm_device *dev = crtc->base.dev; | |
6124 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6125 | ||
6126 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); | |
6127 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
6128 | } | |
6129 | ||
6130 | static void i9xx_crtc_enable(struct drm_crtc *crtc) | |
6131 | { | |
6132 | struct drm_device *dev = crtc->dev; | |
6133 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6134 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6135 | struct intel_encoder *encoder; | |
6136 | struct intel_crtc_state *pipe_config = | |
6137 | to_intel_crtc_state(crtc->state); | |
6138 | enum pipe pipe = intel_crtc->pipe; | |
6139 | ||
6140 | if (WARN_ON(intel_crtc->active)) | |
6141 | return; | |
6142 | ||
6143 | i9xx_set_pll_dividers(intel_crtc); | |
6144 | ||
6145 | if (intel_crtc->config->has_dp_encoder) | |
6146 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
6147 | ||
6148 | intel_set_pipe_timings(intel_crtc); | |
6149 | intel_set_pipe_src_size(intel_crtc); | |
6150 | ||
6151 | i9xx_set_pipeconf(intel_crtc); | |
6152 | ||
6153 | intel_crtc->active = true; | |
6154 | ||
6155 | if (!IS_GEN2(dev)) | |
6156 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
6157 | ||
6158 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6159 | if (encoder->pre_enable) | |
6160 | encoder->pre_enable(encoder); | |
6161 | ||
6162 | i9xx_enable_pll(intel_crtc); | |
6163 | ||
6164 | i9xx_pfit_enable(intel_crtc); | |
6165 | ||
6166 | intel_color_load_luts(&pipe_config->base); | |
6167 | ||
6168 | intel_update_watermarks(crtc); | |
6169 | intel_enable_pipe(intel_crtc); | |
6170 | ||
6171 | assert_vblank_disabled(crtc); | |
6172 | drm_crtc_vblank_on(crtc); | |
6173 | ||
6174 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6175 | encoder->enable(encoder); | |
6176 | } | |
6177 | ||
6178 | static void i9xx_pfit_disable(struct intel_crtc *crtc) | |
6179 | { | |
6180 | struct drm_device *dev = crtc->base.dev; | |
6181 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6182 | ||
6183 | if (!crtc->config->gmch_pfit.control) | |
6184 | return; | |
6185 | ||
6186 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
6187 | ||
6188 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", | |
6189 | I915_READ(PFIT_CONTROL)); | |
6190 | I915_WRITE(PFIT_CONTROL, 0); | |
6191 | } | |
6192 | ||
6193 | static void i9xx_crtc_disable(struct drm_crtc *crtc) | |
6194 | { | |
6195 | struct drm_device *dev = crtc->dev; | |
6196 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6197 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6198 | struct intel_encoder *encoder; | |
6199 | int pipe = intel_crtc->pipe; | |
6200 | ||
6201 | /* | |
6202 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6203 | * wait for planes to fully turn off before disabling the pipe. | |
6204 | */ | |
6205 | if (IS_GEN2(dev)) | |
6206 | intel_wait_for_vblank(dev, pipe); | |
6207 | ||
6208 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6209 | encoder->disable(encoder); | |
6210 | ||
6211 | drm_crtc_vblank_off(crtc); | |
6212 | assert_vblank_disabled(crtc); | |
6213 | ||
6214 | intel_disable_pipe(intel_crtc); | |
6215 | ||
6216 | i9xx_pfit_disable(intel_crtc); | |
6217 | ||
6218 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6219 | if (encoder->post_disable) | |
6220 | encoder->post_disable(encoder); | |
6221 | ||
6222 | if (!intel_crtc->config->has_dsi_encoder) { | |
6223 | if (IS_CHERRYVIEW(dev)) | |
6224 | chv_disable_pll(dev_priv, pipe); | |
6225 | else if (IS_VALLEYVIEW(dev)) | |
6226 | vlv_disable_pll(dev_priv, pipe); | |
6227 | else | |
6228 | i9xx_disable_pll(intel_crtc); | |
6229 | } | |
6230 | ||
6231 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6232 | if (encoder->post_pll_disable) | |
6233 | encoder->post_pll_disable(encoder); | |
6234 | ||
6235 | if (!IS_GEN2(dev)) | |
6236 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
6237 | } | |
6238 | ||
6239 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) | |
6240 | { | |
6241 | struct intel_encoder *encoder; | |
6242 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6243 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6244 | enum intel_display_power_domain domain; | |
6245 | unsigned long domains; | |
6246 | ||
6247 | if (!intel_crtc->active) | |
6248 | return; | |
6249 | ||
6250 | if (to_intel_plane_state(crtc->primary->state)->visible) { | |
6251 | WARN_ON(intel_crtc->unpin_work); | |
6252 | ||
6253 | intel_pre_disable_primary_noatomic(crtc); | |
6254 | ||
6255 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
6256 | to_intel_plane_state(crtc->primary->state)->visible = false; | |
6257 | } | |
6258 | ||
6259 | dev_priv->display.crtc_disable(crtc); | |
6260 | ||
6261 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n", | |
6262 | crtc->base.id); | |
6263 | ||
6264 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
6265 | crtc->state->active = false; | |
6266 | intel_crtc->active = false; | |
6267 | crtc->enabled = false; | |
6268 | crtc->state->connector_mask = 0; | |
6269 | crtc->state->encoder_mask = 0; | |
6270 | ||
6271 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
6272 | encoder->base.crtc = NULL; | |
6273 | ||
6274 | intel_fbc_disable(intel_crtc); | |
6275 | intel_update_watermarks(crtc); | |
6276 | intel_disable_shared_dpll(intel_crtc); | |
6277 | ||
6278 | domains = intel_crtc->enabled_power_domains; | |
6279 | for_each_power_domain(domain, domains) | |
6280 | intel_display_power_put(dev_priv, domain); | |
6281 | intel_crtc->enabled_power_domains = 0; | |
6282 | ||
6283 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6284 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
6285 | } | |
6286 | ||
6287 | /* | |
6288 | * turn all crtc's off, but do not adjust state | |
6289 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6290 | */ | |
6291 | int intel_display_suspend(struct drm_device *dev) | |
6292 | { | |
6293 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6294 | struct drm_atomic_state *state; | |
6295 | int ret; | |
6296 | ||
6297 | state = drm_atomic_helper_suspend(dev); | |
6298 | ret = PTR_ERR_OR_ZERO(state); | |
6299 | if (ret) | |
6300 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
6301 | else | |
6302 | dev_priv->modeset_restore_state = state; | |
6303 | return ret; | |
6304 | } | |
6305 | ||
6306 | void intel_encoder_destroy(struct drm_encoder *encoder) | |
6307 | { | |
6308 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
6309 | ||
6310 | drm_encoder_cleanup(encoder); | |
6311 | kfree(intel_encoder); | |
6312 | } | |
6313 | ||
6314 | /* Cross check the actual hw state with our own modeset state tracking (and it's | |
6315 | * internal consistency). */ | |
6316 | static void intel_connector_verify_state(struct intel_connector *connector) | |
6317 | { | |
6318 | struct drm_crtc *crtc = connector->base.state->crtc; | |
6319 | ||
6320 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6321 | connector->base.base.id, | |
6322 | connector->base.name); | |
6323 | ||
6324 | if (connector->get_hw_state(connector)) { | |
6325 | struct intel_encoder *encoder = connector->encoder; | |
6326 | struct drm_connector_state *conn_state = connector->base.state; | |
6327 | ||
6328 | I915_STATE_WARN(!crtc, | |
6329 | "connector enabled without attached crtc\n"); | |
6330 | ||
6331 | if (!crtc) | |
6332 | return; | |
6333 | ||
6334 | I915_STATE_WARN(!crtc->state->active, | |
6335 | "connector is active, but attached crtc isn't\n"); | |
6336 | ||
6337 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) | |
6338 | return; | |
6339 | ||
6340 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, | |
6341 | "atomic encoder doesn't match attached encoder\n"); | |
6342 | ||
6343 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, | |
6344 | "attached encoder crtc differs from connector crtc\n"); | |
6345 | } else { | |
6346 | I915_STATE_WARN(crtc && crtc->state->active, | |
6347 | "attached crtc is active, but connector isn't\n"); | |
6348 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, | |
6349 | "best encoder set without crtc!\n"); | |
6350 | } | |
6351 | } | |
6352 | ||
6353 | int intel_connector_init(struct intel_connector *connector) | |
6354 | { | |
6355 | drm_atomic_helper_connector_reset(&connector->base); | |
6356 | ||
6357 | if (!connector->base.state) | |
6358 | return -ENOMEM; | |
6359 | ||
6360 | return 0; | |
6361 | } | |
6362 | ||
6363 | struct intel_connector *intel_connector_alloc(void) | |
6364 | { | |
6365 | struct intel_connector *connector; | |
6366 | ||
6367 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6368 | if (!connector) | |
6369 | return NULL; | |
6370 | ||
6371 | if (intel_connector_init(connector) < 0) { | |
6372 | kfree(connector); | |
6373 | return NULL; | |
6374 | } | |
6375 | ||
6376 | return connector; | |
6377 | } | |
6378 | ||
6379 | /* Simple connector->get_hw_state implementation for encoders that support only | |
6380 | * one connector and no cloning and hence the encoder state determines the state | |
6381 | * of the connector. */ | |
6382 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
6383 | { | |
6384 | enum pipe pipe = 0; | |
6385 | struct intel_encoder *encoder = connector->encoder; | |
6386 | ||
6387 | return encoder->get_hw_state(encoder, &pipe); | |
6388 | } | |
6389 | ||
6390 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) | |
6391 | { | |
6392 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) | |
6393 | return crtc_state->fdi_lanes; | |
6394 | ||
6395 | return 0; | |
6396 | } | |
6397 | ||
6398 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, | |
6399 | struct intel_crtc_state *pipe_config) | |
6400 | { | |
6401 | struct drm_atomic_state *state = pipe_config->base.state; | |
6402 | struct intel_crtc *other_crtc; | |
6403 | struct intel_crtc_state *other_crtc_state; | |
6404 | ||
6405 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
6406 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6407 | if (pipe_config->fdi_lanes > 4) { | |
6408 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6409 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6410 | return -EINVAL; | |
6411 | } | |
6412 | ||
6413 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
6414 | if (pipe_config->fdi_lanes > 2) { | |
6415 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6416 | pipe_config->fdi_lanes); | |
6417 | return -EINVAL; | |
6418 | } else { | |
6419 | return 0; | |
6420 | } | |
6421 | } | |
6422 | ||
6423 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6424 | return 0; | |
6425 | ||
6426 | /* Ivybridge 3 pipe is really complicated */ | |
6427 | switch (pipe) { | |
6428 | case PIPE_A: | |
6429 | return 0; | |
6430 | case PIPE_B: | |
6431 | if (pipe_config->fdi_lanes <= 2) | |
6432 | return 0; | |
6433 | ||
6434 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6435 | other_crtc_state = | |
6436 | intel_atomic_get_crtc_state(state, other_crtc); | |
6437 | if (IS_ERR(other_crtc_state)) | |
6438 | return PTR_ERR(other_crtc_state); | |
6439 | ||
6440 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
6441 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
6442 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6443 | return -EINVAL; | |
6444 | } | |
6445 | return 0; | |
6446 | case PIPE_C: | |
6447 | if (pipe_config->fdi_lanes > 2) { | |
6448 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6449 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6450 | return -EINVAL; | |
6451 | } | |
6452 | ||
6453 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6454 | other_crtc_state = | |
6455 | intel_atomic_get_crtc_state(state, other_crtc); | |
6456 | if (IS_ERR(other_crtc_state)) | |
6457 | return PTR_ERR(other_crtc_state); | |
6458 | ||
6459 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
6460 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
6461 | return -EINVAL; | |
6462 | } | |
6463 | return 0; | |
6464 | default: | |
6465 | BUG(); | |
6466 | } | |
6467 | } | |
6468 | ||
6469 | #define RETRY 1 | |
6470 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
6471 | struct intel_crtc_state *pipe_config) | |
6472 | { | |
6473 | struct drm_device *dev = intel_crtc->base.dev; | |
6474 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; | |
6475 | int lane, link_bw, fdi_dotclock, ret; | |
6476 | bool needs_recompute = false; | |
6477 | ||
6478 | retry: | |
6479 | /* FDI is a binary signal running at ~2.7GHz, encoding | |
6480 | * each output octet as 10 bits. The actual frequency | |
6481 | * is stored as a divider into a 100MHz clock, and the | |
6482 | * mode pixel clock is stored in units of 1KHz. | |
6483 | * Hence the bw of each lane in terms of the mode signal | |
6484 | * is: | |
6485 | */ | |
6486 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); | |
6487 | ||
6488 | fdi_dotclock = adjusted_mode->crtc_clock; | |
6489 | ||
6490 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, | |
6491 | pipe_config->pipe_bpp); | |
6492 | ||
6493 | pipe_config->fdi_lanes = lane; | |
6494 | ||
6495 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, | |
6496 | link_bw, &pipe_config->fdi_m_n); | |
6497 | ||
6498 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); | |
6499 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
6500 | pipe_config->pipe_bpp -= 2*3; | |
6501 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6502 | pipe_config->pipe_bpp); | |
6503 | needs_recompute = true; | |
6504 | pipe_config->bw_constrained = true; | |
6505 | ||
6506 | goto retry; | |
6507 | } | |
6508 | ||
6509 | if (needs_recompute) | |
6510 | return RETRY; | |
6511 | ||
6512 | return ret; | |
6513 | } | |
6514 | ||
6515 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, | |
6516 | struct intel_crtc_state *pipe_config) | |
6517 | { | |
6518 | if (pipe_config->pipe_bpp > 24) | |
6519 | return false; | |
6520 | ||
6521 | /* HSW can handle pixel rate up to cdclk? */ | |
6522 | if (IS_HASWELL(dev_priv)) | |
6523 | return true; | |
6524 | ||
6525 | /* | |
6526 | * We compare against max which means we must take | |
6527 | * the increased cdclk requirement into account when | |
6528 | * calculating the new cdclk. | |
6529 | * | |
6530 | * Should measure whether using a lower cdclk w/o IPS | |
6531 | */ | |
6532 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6533 | dev_priv->max_cdclk_freq * 95 / 100; | |
6534 | } | |
6535 | ||
6536 | static void hsw_compute_ips_config(struct intel_crtc *crtc, | |
6537 | struct intel_crtc_state *pipe_config) | |
6538 | { | |
6539 | struct drm_device *dev = crtc->base.dev; | |
6540 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6541 | ||
6542 | pipe_config->ips_enabled = i915.enable_ips && | |
6543 | hsw_crtc_supports_ips(crtc) && | |
6544 | pipe_config_supports_ips(dev_priv, pipe_config); | |
6545 | } | |
6546 | ||
6547 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) | |
6548 | { | |
6549 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6550 | ||
6551 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6552 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6553 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6554 | } | |
6555 | ||
6556 | static int intel_crtc_compute_config(struct intel_crtc *crtc, | |
6557 | struct intel_crtc_state *pipe_config) | |
6558 | { | |
6559 | struct drm_device *dev = crtc->base.dev; | |
6560 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6561 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; | |
6562 | ||
6563 | /* FIXME should check pixel clock limits on all platforms */ | |
6564 | if (INTEL_INFO(dev)->gen < 4) { | |
6565 | int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; | |
6566 | ||
6567 | /* | |
6568 | * Enable double wide mode when the dot clock | |
6569 | * is > 90% of the (display) core speed. | |
6570 | */ | |
6571 | if (intel_crtc_supports_double_wide(crtc) && | |
6572 | adjusted_mode->crtc_clock > clock_limit) { | |
6573 | clock_limit *= 2; | |
6574 | pipe_config->double_wide = true; | |
6575 | } | |
6576 | ||
6577 | if (adjusted_mode->crtc_clock > clock_limit) { | |
6578 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6579 | adjusted_mode->crtc_clock, clock_limit, | |
6580 | yesno(pipe_config->double_wide)); | |
6581 | return -EINVAL; | |
6582 | } | |
6583 | } | |
6584 | ||
6585 | /* | |
6586 | * Pipe horizontal size must be even in: | |
6587 | * - DVO ganged mode | |
6588 | * - LVDS dual channel mode | |
6589 | * - Double wide pipe | |
6590 | */ | |
6591 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && | |
6592 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
6593 | pipe_config->pipe_src_w &= ~1; | |
6594 | ||
6595 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. | |
6596 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
6597 | */ | |
6598 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
6599 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) | |
6600 | return -EINVAL; | |
6601 | ||
6602 | if (HAS_IPS(dev)) | |
6603 | hsw_compute_ips_config(crtc, pipe_config); | |
6604 | ||
6605 | if (pipe_config->has_pch_encoder) | |
6606 | return ironlake_fdi_compute_config(crtc, pipe_config); | |
6607 | ||
6608 | return 0; | |
6609 | } | |
6610 | ||
6611 | static int skylake_get_display_clock_speed(struct drm_device *dev) | |
6612 | { | |
6613 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6614 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6615 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6616 | uint32_t linkrate; | |
6617 | ||
6618 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) | |
6619 | return 24000; /* 24MHz is the cd freq with NSSC ref */ | |
6620 | ||
6621 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6622 | return 540000; | |
6623 | ||
6624 | linkrate = (I915_READ(DPLL_CTRL1) & | |
6625 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; | |
6626 | ||
6627 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || | |
6628 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
6629 | /* vco 8640 */ | |
6630 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6631 | case CDCLK_FREQ_450_432: | |
6632 | return 432000; | |
6633 | case CDCLK_FREQ_337_308: | |
6634 | return 308570; | |
6635 | case CDCLK_FREQ_675_617: | |
6636 | return 617140; | |
6637 | default: | |
6638 | WARN(1, "Unknown cd freq selection\n"); | |
6639 | } | |
6640 | } else { | |
6641 | /* vco 8100 */ | |
6642 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6643 | case CDCLK_FREQ_450_432: | |
6644 | return 450000; | |
6645 | case CDCLK_FREQ_337_308: | |
6646 | return 337500; | |
6647 | case CDCLK_FREQ_675_617: | |
6648 | return 675000; | |
6649 | default: | |
6650 | WARN(1, "Unknown cd freq selection\n"); | |
6651 | } | |
6652 | } | |
6653 | ||
6654 | /* error case, do as if DPLL0 isn't enabled */ | |
6655 | return 24000; | |
6656 | } | |
6657 | ||
6658 | static int broxton_get_display_clock_speed(struct drm_device *dev) | |
6659 | { | |
6660 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6661 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6662 | uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; | |
6663 | uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); | |
6664 | int cdclk; | |
6665 | ||
6666 | if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) | |
6667 | return 19200; | |
6668 | ||
6669 | cdclk = 19200 * pll_ratio / 2; | |
6670 | ||
6671 | switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { | |
6672 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
6673 | return cdclk; /* 576MHz or 624MHz */ | |
6674 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
6675 | return cdclk * 2 / 3; /* 384MHz */ | |
6676 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
6677 | return cdclk / 2; /* 288MHz */ | |
6678 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
6679 | return cdclk / 4; /* 144MHz */ | |
6680 | } | |
6681 | ||
6682 | /* error case, do as if DE PLL isn't enabled */ | |
6683 | return 19200; | |
6684 | } | |
6685 | ||
6686 | static int broadwell_get_display_clock_speed(struct drm_device *dev) | |
6687 | { | |
6688 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6689 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6690 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6691 | ||
6692 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6693 | return 800000; | |
6694 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6695 | return 450000; | |
6696 | else if (freq == LCPLL_CLK_FREQ_450) | |
6697 | return 450000; | |
6698 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6699 | return 540000; | |
6700 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6701 | return 337500; | |
6702 | else | |
6703 | return 675000; | |
6704 | } | |
6705 | ||
6706 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6707 | { | |
6708 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6709 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6710 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6711 | ||
6712 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6713 | return 800000; | |
6714 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6715 | return 450000; | |
6716 | else if (freq == LCPLL_CLK_FREQ_450) | |
6717 | return 450000; | |
6718 | else if (IS_HSW_ULT(dev)) | |
6719 | return 337500; | |
6720 | else | |
6721 | return 540000; | |
6722 | } | |
6723 | ||
6724 | static int valleyview_get_display_clock_speed(struct drm_device *dev) | |
6725 | { | |
6726 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", | |
6727 | CCK_DISPLAY_CLOCK_CONTROL); | |
6728 | } | |
6729 | ||
6730 | static int ilk_get_display_clock_speed(struct drm_device *dev) | |
6731 | { | |
6732 | return 450000; | |
6733 | } | |
6734 | ||
6735 | static int i945_get_display_clock_speed(struct drm_device *dev) | |
6736 | { | |
6737 | return 400000; | |
6738 | } | |
6739 | ||
6740 | static int i915_get_display_clock_speed(struct drm_device *dev) | |
6741 | { | |
6742 | return 333333; | |
6743 | } | |
6744 | ||
6745 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) | |
6746 | { | |
6747 | return 200000; | |
6748 | } | |
6749 | ||
6750 | static int pnv_get_display_clock_speed(struct drm_device *dev) | |
6751 | { | |
6752 | u16 gcfgc = 0; | |
6753 | ||
6754 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6755 | ||
6756 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6757 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
6758 | return 266667; | |
6759 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
6760 | return 333333; | |
6761 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
6762 | return 444444; | |
6763 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
6764 | return 200000; | |
6765 | default: | |
6766 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6767 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
6768 | return 133333; | |
6769 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
6770 | return 166667; | |
6771 | } | |
6772 | } | |
6773 | ||
6774 | static int i915gm_get_display_clock_speed(struct drm_device *dev) | |
6775 | { | |
6776 | u16 gcfgc = 0; | |
6777 | ||
6778 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6779 | ||
6780 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
6781 | return 133333; | |
6782 | else { | |
6783 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6784 | case GC_DISPLAY_CLOCK_333_MHZ: | |
6785 | return 333333; | |
6786 | default: | |
6787 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6788 | return 190000; | |
6789 | } | |
6790 | } | |
6791 | } | |
6792 | ||
6793 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6794 | { | |
6795 | return 266667; | |
6796 | } | |
6797 | ||
6798 | static int i85x_get_display_clock_speed(struct drm_device *dev) | |
6799 | { | |
6800 | u16 hpllcc = 0; | |
6801 | ||
6802 | /* | |
6803 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6804 | * encoding is different :( | |
6805 | * FIXME is this the right way to detect 852GM/852GMV? | |
6806 | */ | |
6807 | if (dev->pdev->revision == 0x1) | |
6808 | return 133333; | |
6809 | ||
6810 | pci_bus_read_config_word(dev->pdev->bus, | |
6811 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6812 | ||
6813 | /* Assume that the hardware is in the high speed state. This | |
6814 | * should be the default. | |
6815 | */ | |
6816 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6817 | case GC_CLOCK_133_200: | |
6818 | case GC_CLOCK_133_200_2: | |
6819 | case GC_CLOCK_100_200: | |
6820 | return 200000; | |
6821 | case GC_CLOCK_166_250: | |
6822 | return 250000; | |
6823 | case GC_CLOCK_100_133: | |
6824 | return 133333; | |
6825 | case GC_CLOCK_133_266: | |
6826 | case GC_CLOCK_133_266_2: | |
6827 | case GC_CLOCK_166_266: | |
6828 | return 266667; | |
6829 | } | |
6830 | ||
6831 | /* Shouldn't happen */ | |
6832 | return 0; | |
6833 | } | |
6834 | ||
6835 | static int i830_get_display_clock_speed(struct drm_device *dev) | |
6836 | { | |
6837 | return 133333; | |
6838 | } | |
6839 | ||
6840 | static unsigned int intel_hpll_vco(struct drm_device *dev) | |
6841 | { | |
6842 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6843 | static const unsigned int blb_vco[8] = { | |
6844 | [0] = 3200000, | |
6845 | [1] = 4000000, | |
6846 | [2] = 5333333, | |
6847 | [3] = 4800000, | |
6848 | [4] = 6400000, | |
6849 | }; | |
6850 | static const unsigned int pnv_vco[8] = { | |
6851 | [0] = 3200000, | |
6852 | [1] = 4000000, | |
6853 | [2] = 5333333, | |
6854 | [3] = 4800000, | |
6855 | [4] = 2666667, | |
6856 | }; | |
6857 | static const unsigned int cl_vco[8] = { | |
6858 | [0] = 3200000, | |
6859 | [1] = 4000000, | |
6860 | [2] = 5333333, | |
6861 | [3] = 6400000, | |
6862 | [4] = 3333333, | |
6863 | [5] = 3566667, | |
6864 | [6] = 4266667, | |
6865 | }; | |
6866 | static const unsigned int elk_vco[8] = { | |
6867 | [0] = 3200000, | |
6868 | [1] = 4000000, | |
6869 | [2] = 5333333, | |
6870 | [3] = 4800000, | |
6871 | }; | |
6872 | static const unsigned int ctg_vco[8] = { | |
6873 | [0] = 3200000, | |
6874 | [1] = 4000000, | |
6875 | [2] = 5333333, | |
6876 | [3] = 6400000, | |
6877 | [4] = 2666667, | |
6878 | [5] = 4266667, | |
6879 | }; | |
6880 | const unsigned int *vco_table; | |
6881 | unsigned int vco; | |
6882 | uint8_t tmp = 0; | |
6883 | ||
6884 | /* FIXME other chipsets? */ | |
6885 | if (IS_GM45(dev)) | |
6886 | vco_table = ctg_vco; | |
6887 | else if (IS_G4X(dev)) | |
6888 | vco_table = elk_vco; | |
6889 | else if (IS_CRESTLINE(dev)) | |
6890 | vco_table = cl_vco; | |
6891 | else if (IS_PINEVIEW(dev)) | |
6892 | vco_table = pnv_vco; | |
6893 | else if (IS_G33(dev)) | |
6894 | vco_table = blb_vco; | |
6895 | else | |
6896 | return 0; | |
6897 | ||
6898 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
6899 | ||
6900 | vco = vco_table[tmp & 0x7]; | |
6901 | if (vco == 0) | |
6902 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
6903 | else | |
6904 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
6905 | ||
6906 | return vco; | |
6907 | } | |
6908 | ||
6909 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
6910 | { | |
6911 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6912 | uint16_t tmp = 0; | |
6913 | ||
6914 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6915 | ||
6916 | cdclk_sel = (tmp >> 12) & 0x1; | |
6917 | ||
6918 | switch (vco) { | |
6919 | case 2666667: | |
6920 | case 4000000: | |
6921 | case 5333333: | |
6922 | return cdclk_sel ? 333333 : 222222; | |
6923 | case 3200000: | |
6924 | return cdclk_sel ? 320000 : 228571; | |
6925 | default: | |
6926 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
6927 | return 222222; | |
6928 | } | |
6929 | } | |
6930 | ||
6931 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
6932 | { | |
6933 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
6934 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
6935 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
6936 | const uint8_t *div_table; | |
6937 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6938 | uint16_t tmp = 0; | |
6939 | ||
6940 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6941 | ||
6942 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
6943 | ||
6944 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
6945 | goto fail; | |
6946 | ||
6947 | switch (vco) { | |
6948 | case 3200000: | |
6949 | div_table = div_3200; | |
6950 | break; | |
6951 | case 4000000: | |
6952 | div_table = div_4000; | |
6953 | break; | |
6954 | case 5333333: | |
6955 | div_table = div_5333; | |
6956 | break; | |
6957 | default: | |
6958 | goto fail; | |
6959 | } | |
6960 | ||
6961 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
6962 | ||
6963 | fail: | |
6964 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); | |
6965 | return 200000; | |
6966 | } | |
6967 | ||
6968 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
6969 | { | |
6970 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
6971 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
6972 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
6973 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
6974 | const uint8_t *div_table; | |
6975 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6976 | uint16_t tmp = 0; | |
6977 | ||
6978 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6979 | ||
6980 | cdclk_sel = (tmp >> 4) & 0x7; | |
6981 | ||
6982 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
6983 | goto fail; | |
6984 | ||
6985 | switch (vco) { | |
6986 | case 3200000: | |
6987 | div_table = div_3200; | |
6988 | break; | |
6989 | case 4000000: | |
6990 | div_table = div_4000; | |
6991 | break; | |
6992 | case 4800000: | |
6993 | div_table = div_4800; | |
6994 | break; | |
6995 | case 5333333: | |
6996 | div_table = div_5333; | |
6997 | break; | |
6998 | default: | |
6999 | goto fail; | |
7000 | } | |
7001 | ||
7002 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7003 | ||
7004 | fail: | |
7005 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); | |
7006 | return 190476; | |
7007 | } | |
7008 | ||
7009 | static void | |
7010 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) | |
7011 | { | |
7012 | while (*num > DATA_LINK_M_N_MASK || | |
7013 | *den > DATA_LINK_M_N_MASK) { | |
7014 | *num >>= 1; | |
7015 | *den >>= 1; | |
7016 | } | |
7017 | } | |
7018 | ||
7019 | static void compute_m_n(unsigned int m, unsigned int n, | |
7020 | uint32_t *ret_m, uint32_t *ret_n) | |
7021 | { | |
7022 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7023 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7024 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7025 | } | |
7026 | ||
7027 | void | |
7028 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7029 | int pixel_clock, int link_clock, | |
7030 | struct intel_link_m_n *m_n) | |
7031 | { | |
7032 | m_n->tu = 64; | |
7033 | ||
7034 | compute_m_n(bits_per_pixel * pixel_clock, | |
7035 | link_clock * nlanes * 8, | |
7036 | &m_n->gmch_m, &m_n->gmch_n); | |
7037 | ||
7038 | compute_m_n(pixel_clock, link_clock, | |
7039 | &m_n->link_m, &m_n->link_n); | |
7040 | } | |
7041 | ||
7042 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) | |
7043 | { | |
7044 | if (i915.panel_use_ssc >= 0) | |
7045 | return i915.panel_use_ssc != 0; | |
7046 | return dev_priv->vbt.lvds_use_ssc | |
7047 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); | |
7048 | } | |
7049 | ||
7050 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) | |
7051 | { | |
7052 | return (1 << dpll->n) << 16 | dpll->m2; | |
7053 | } | |
7054 | ||
7055 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) | |
7056 | { | |
7057 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
7058 | } | |
7059 | ||
7060 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, | |
7061 | struct intel_crtc_state *crtc_state, | |
7062 | intel_clock_t *reduced_clock) | |
7063 | { | |
7064 | struct drm_device *dev = crtc->base.dev; | |
7065 | u32 fp, fp2 = 0; | |
7066 | ||
7067 | if (IS_PINEVIEW(dev)) { | |
7068 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); | |
7069 | if (reduced_clock) | |
7070 | fp2 = pnv_dpll_compute_fp(reduced_clock); | |
7071 | } else { | |
7072 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
7073 | if (reduced_clock) | |
7074 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
7075 | } | |
7076 | ||
7077 | crtc_state->dpll_hw_state.fp0 = fp; | |
7078 | ||
7079 | crtc->lowfreq_avail = false; | |
7080 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && | |
7081 | reduced_clock) { | |
7082 | crtc_state->dpll_hw_state.fp1 = fp2; | |
7083 | crtc->lowfreq_avail = true; | |
7084 | } else { | |
7085 | crtc_state->dpll_hw_state.fp1 = fp; | |
7086 | } | |
7087 | } | |
7088 | ||
7089 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe | |
7090 | pipe) | |
7091 | { | |
7092 | u32 reg_val; | |
7093 | ||
7094 | /* | |
7095 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7096 | * and set it to a reasonable value instead. | |
7097 | */ | |
7098 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); | |
7099 | reg_val &= 0xffffff00; | |
7100 | reg_val |= 0x00000030; | |
7101 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); | |
7102 | ||
7103 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); | |
7104 | reg_val &= 0x8cffffff; | |
7105 | reg_val = 0x8c000000; | |
7106 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); | |
7107 | ||
7108 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); | |
7109 | reg_val &= 0xffffff00; | |
7110 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); | |
7111 | ||
7112 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); | |
7113 | reg_val &= 0x00ffffff; | |
7114 | reg_val |= 0xb0000000; | |
7115 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); | |
7116 | } | |
7117 | ||
7118 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, | |
7119 | struct intel_link_m_n *m_n) | |
7120 | { | |
7121 | struct drm_device *dev = crtc->base.dev; | |
7122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7123 | int pipe = crtc->pipe; | |
7124 | ||
7125 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7126 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7127 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7128 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
7129 | } | |
7130 | ||
7131 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
7132 | struct intel_link_m_n *m_n, | |
7133 | struct intel_link_m_n *m2_n2) | |
7134 | { | |
7135 | struct drm_device *dev = crtc->base.dev; | |
7136 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7137 | int pipe = crtc->pipe; | |
7138 | enum transcoder transcoder = crtc->config->cpu_transcoder; | |
7139 | ||
7140 | if (INTEL_INFO(dev)->gen >= 5) { | |
7141 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7142 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7143 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7144 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
7145 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available | |
7146 | * for gen < 8) and if DRRS is supported (to make sure the | |
7147 | * registers are not unnecessarily accessed). | |
7148 | */ | |
7149 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && | |
7150 | crtc->config->has_drrs) { | |
7151 | I915_WRITE(PIPE_DATA_M2(transcoder), | |
7152 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7153 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7154 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7155 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7156 | } | |
7157 | } else { | |
7158 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7159 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7160 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7161 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
7162 | } | |
7163 | } | |
7164 | ||
7165 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) | |
7166 | { | |
7167 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; | |
7168 | ||
7169 | if (m_n == M1_N1) { | |
7170 | dp_m_n = &crtc->config->dp_m_n; | |
7171 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7172 | } else if (m_n == M2_N2) { | |
7173 | ||
7174 | /* | |
7175 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7176 | * needs to be programmed into M1_N1. | |
7177 | */ | |
7178 | dp_m_n = &crtc->config->dp_m2_n2; | |
7179 | } else { | |
7180 | DRM_ERROR("Unsupported divider value\n"); | |
7181 | return; | |
7182 | } | |
7183 | ||
7184 | if (crtc->config->has_pch_encoder) | |
7185 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
7186 | else | |
7187 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); | |
7188 | } | |
7189 | ||
7190 | static void vlv_compute_dpll(struct intel_crtc *crtc, | |
7191 | struct intel_crtc_state *pipe_config) | |
7192 | { | |
7193 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | | |
7194 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
7195 | if (crtc->pipe != PIPE_A) | |
7196 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7197 | ||
7198 | /* DPLL not used with DSI, but still need the rest set up */ | |
7199 | if (!pipe_config->has_dsi_encoder) | |
7200 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | | |
7201 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
7202 | ||
7203 | pipe_config->dpll_hw_state.dpll_md = | |
7204 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
7205 | } | |
7206 | ||
7207 | static void chv_compute_dpll(struct intel_crtc *crtc, | |
7208 | struct intel_crtc_state *pipe_config) | |
7209 | { | |
7210 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
7211 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
7212 | if (crtc->pipe != PIPE_A) | |
7213 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7214 | ||
7215 | /* DPLL not used with DSI, but still need the rest set up */ | |
7216 | if (!pipe_config->has_dsi_encoder) | |
7217 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; | |
7218 | ||
7219 | pipe_config->dpll_hw_state.dpll_md = | |
7220 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
7221 | } | |
7222 | ||
7223 | static void vlv_prepare_pll(struct intel_crtc *crtc, | |
7224 | const struct intel_crtc_state *pipe_config) | |
7225 | { | |
7226 | struct drm_device *dev = crtc->base.dev; | |
7227 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7228 | enum pipe pipe = crtc->pipe; | |
7229 | u32 mdiv; | |
7230 | u32 bestn, bestm1, bestm2, bestp1, bestp2; | |
7231 | u32 coreclk, reg_val; | |
7232 | ||
7233 | /* Enable Refclk */ | |
7234 | I915_WRITE(DPLL(pipe), | |
7235 | pipe_config->dpll_hw_state.dpll & | |
7236 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
7237 | ||
7238 | /* No need to actually set up the DPLL with DSI */ | |
7239 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7240 | return; | |
7241 | ||
7242 | mutex_lock(&dev_priv->sb_lock); | |
7243 | ||
7244 | bestn = pipe_config->dpll.n; | |
7245 | bestm1 = pipe_config->dpll.m1; | |
7246 | bestm2 = pipe_config->dpll.m2; | |
7247 | bestp1 = pipe_config->dpll.p1; | |
7248 | bestp2 = pipe_config->dpll.p2; | |
7249 | ||
7250 | /* See eDP HDMI DPIO driver vbios notes doc */ | |
7251 | ||
7252 | /* PLL B needs special handling */ | |
7253 | if (pipe == PIPE_B) | |
7254 | vlv_pllb_recal_opamp(dev_priv, pipe); | |
7255 | ||
7256 | /* Set up Tx target for periodic Rcomp update */ | |
7257 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); | |
7258 | ||
7259 | /* Disable target IRef on PLL */ | |
7260 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); | |
7261 | reg_val &= 0x00ffffff; | |
7262 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); | |
7263 | ||
7264 | /* Disable fast lock */ | |
7265 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); | |
7266 | ||
7267 | /* Set idtafcrecal before PLL is enabled */ | |
7268 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); | |
7269 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7270 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
7271 | mdiv |= (1 << DPIO_K_SHIFT); | |
7272 | ||
7273 | /* | |
7274 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7275 | * but we don't support that). | |
7276 | * Note: don't use the DAC post divider as it seems unstable. | |
7277 | */ | |
7278 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
7279 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); | |
7280 | ||
7281 | mdiv |= DPIO_ENABLE_CALIBRATION; | |
7282 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); | |
7283 | ||
7284 | /* Set HBR and RBR LPF coefficients */ | |
7285 | if (pipe_config->port_clock == 162000 || | |
7286 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || | |
7287 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
7288 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), | |
7289 | 0x009f0003); | |
7290 | else | |
7291 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), | |
7292 | 0x00d0000f); | |
7293 | ||
7294 | if (pipe_config->has_dp_encoder) { | |
7295 | /* Use SSC source */ | |
7296 | if (pipe == PIPE_A) | |
7297 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), | |
7298 | 0x0df40000); | |
7299 | else | |
7300 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), | |
7301 | 0x0df70000); | |
7302 | } else { /* HDMI or VGA */ | |
7303 | /* Use bend source */ | |
7304 | if (pipe == PIPE_A) | |
7305 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), | |
7306 | 0x0df70000); | |
7307 | else | |
7308 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), | |
7309 | 0x0df40000); | |
7310 | } | |
7311 | ||
7312 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); | |
7313 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; | |
7314 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || | |
7315 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
7316 | coreclk |= 0x01000000; | |
7317 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); | |
7318 | ||
7319 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); | |
7320 | mutex_unlock(&dev_priv->sb_lock); | |
7321 | } | |
7322 | ||
7323 | static void chv_prepare_pll(struct intel_crtc *crtc, | |
7324 | const struct intel_crtc_state *pipe_config) | |
7325 | { | |
7326 | struct drm_device *dev = crtc->base.dev; | |
7327 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7328 | enum pipe pipe = crtc->pipe; | |
7329 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
7330 | u32 loopfilter, tribuf_calcntr; | |
7331 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; | |
7332 | u32 dpio_val; | |
7333 | int vco; | |
7334 | ||
7335 | /* Enable Refclk and SSC */ | |
7336 | I915_WRITE(DPLL(pipe), | |
7337 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
7338 | ||
7339 | /* No need to actually set up the DPLL with DSI */ | |
7340 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7341 | return; | |
7342 | ||
7343 | bestn = pipe_config->dpll.n; | |
7344 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7345 | bestm1 = pipe_config->dpll.m1; | |
7346 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7347 | bestp1 = pipe_config->dpll.p1; | |
7348 | bestp2 = pipe_config->dpll.p2; | |
7349 | vco = pipe_config->dpll.vco; | |
7350 | dpio_val = 0; | |
7351 | loopfilter = 0; | |
7352 | ||
7353 | mutex_lock(&dev_priv->sb_lock); | |
7354 | ||
7355 | /* p1 and p2 divider */ | |
7356 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7357 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7358 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7359 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7360 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7361 | ||
7362 | /* Feedback post-divider - m2 */ | |
7363 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7364 | ||
7365 | /* Feedback refclk divider - n and m1 */ | |
7366 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7367 | DPIO_CHV_M1_DIV_BY_2 | | |
7368 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7369 | ||
7370 | /* M2 fraction division */ | |
7371 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
7372 | ||
7373 | /* M2 fraction division enable */ | |
7374 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); | |
7375 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7376 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7377 | if (bestm2_frac) | |
7378 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7379 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
7380 | ||
7381 | /* Program digital lock detect threshold */ | |
7382 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7383 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7384 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7385 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7386 | if (!bestm2_frac) | |
7387 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7388 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7389 | ||
7390 | /* Loop filter */ | |
7391 | if (vco == 5400000) { | |
7392 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7393 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7394 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7395 | tribuf_calcntr = 0x9; | |
7396 | } else if (vco <= 6200000) { | |
7397 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7398 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7399 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7400 | tribuf_calcntr = 0x9; | |
7401 | } else if (vco <= 6480000) { | |
7402 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7403 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7404 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7405 | tribuf_calcntr = 0x8; | |
7406 | } else { | |
7407 | /* Not supported. Apply the same limits as in the max case */ | |
7408 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7409 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7410 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7411 | tribuf_calcntr = 0; | |
7412 | } | |
7413 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); | |
7414 | ||
7415 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); | |
7416 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; | |
7417 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7418 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7419 | ||
7420 | /* AFC Recal */ | |
7421 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7422 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7423 | DPIO_AFC_RECAL); | |
7424 | ||
7425 | mutex_unlock(&dev_priv->sb_lock); | |
7426 | } | |
7427 | ||
7428 | /** | |
7429 | * vlv_force_pll_on - forcibly enable just the PLL | |
7430 | * @dev_priv: i915 private structure | |
7431 | * @pipe: pipe PLL to enable | |
7432 | * @dpll: PLL configuration | |
7433 | * | |
7434 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7435 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7436 | * be enabled. | |
7437 | */ | |
7438 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
7439 | const struct dpll *dpll) | |
7440 | { | |
7441 | struct intel_crtc *crtc = | |
7442 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
7443 | struct intel_crtc_state *pipe_config; | |
7444 | ||
7445 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
7446 | if (!pipe_config) | |
7447 | return -ENOMEM; | |
7448 | ||
7449 | pipe_config->base.crtc = &crtc->base; | |
7450 | pipe_config->pixel_multiplier = 1; | |
7451 | pipe_config->dpll = *dpll; | |
7452 | ||
7453 | if (IS_CHERRYVIEW(dev)) { | |
7454 | chv_compute_dpll(crtc, pipe_config); | |
7455 | chv_prepare_pll(crtc, pipe_config); | |
7456 | chv_enable_pll(crtc, pipe_config); | |
7457 | } else { | |
7458 | vlv_compute_dpll(crtc, pipe_config); | |
7459 | vlv_prepare_pll(crtc, pipe_config); | |
7460 | vlv_enable_pll(crtc, pipe_config); | |
7461 | } | |
7462 | ||
7463 | kfree(pipe_config); | |
7464 | ||
7465 | return 0; | |
7466 | } | |
7467 | ||
7468 | /** | |
7469 | * vlv_force_pll_off - forcibly disable just the PLL | |
7470 | * @dev_priv: i915 private structure | |
7471 | * @pipe: pipe PLL to disable | |
7472 | * | |
7473 | * Disable the PLL for @pipe. To be used in cases where we need | |
7474 | * the PLL enabled even when @pipe is not going to be enabled. | |
7475 | */ | |
7476 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7477 | { | |
7478 | if (IS_CHERRYVIEW(dev)) | |
7479 | chv_disable_pll(to_i915(dev), pipe); | |
7480 | else | |
7481 | vlv_disable_pll(to_i915(dev), pipe); | |
7482 | } | |
7483 | ||
7484 | static void i9xx_compute_dpll(struct intel_crtc *crtc, | |
7485 | struct intel_crtc_state *crtc_state, | |
7486 | intel_clock_t *reduced_clock) | |
7487 | { | |
7488 | struct drm_device *dev = crtc->base.dev; | |
7489 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7490 | u32 dpll; | |
7491 | bool is_sdvo; | |
7492 | struct dpll *clock = &crtc_state->dpll; | |
7493 | ||
7494 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); | |
7495 | ||
7496 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || | |
7497 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
7498 | ||
7499 | dpll = DPLL_VGA_MODE_DIS; | |
7500 | ||
7501 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) | |
7502 | dpll |= DPLLB_MODE_LVDS; | |
7503 | else | |
7504 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
7505 | ||
7506 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { | |
7507 | dpll |= (crtc_state->pixel_multiplier - 1) | |
7508 | << SDVO_MULTIPLIER_SHIFT_HIRES; | |
7509 | } | |
7510 | ||
7511 | if (is_sdvo) | |
7512 | dpll |= DPLL_SDVO_HIGH_SPEED; | |
7513 | ||
7514 | if (crtc_state->has_dp_encoder) | |
7515 | dpll |= DPLL_SDVO_HIGH_SPEED; | |
7516 | ||
7517 | /* compute bitmask from p1 value */ | |
7518 | if (IS_PINEVIEW(dev)) | |
7519 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7520 | else { | |
7521 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7522 | if (IS_G4X(dev) && reduced_clock) | |
7523 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7524 | } | |
7525 | switch (clock->p2) { | |
7526 | case 5: | |
7527 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7528 | break; | |
7529 | case 7: | |
7530 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7531 | break; | |
7532 | case 10: | |
7533 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7534 | break; | |
7535 | case 14: | |
7536 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7537 | break; | |
7538 | } | |
7539 | if (INTEL_INFO(dev)->gen >= 4) | |
7540 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7541 | ||
7542 | if (crtc_state->sdvo_tv_clock) | |
7543 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
7544 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && | |
7545 | intel_panel_use_ssc(dev_priv)) | |
7546 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7547 | else | |
7548 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7549 | ||
7550 | dpll |= DPLL_VCO_ENABLE; | |
7551 | crtc_state->dpll_hw_state.dpll = dpll; | |
7552 | ||
7553 | if (INTEL_INFO(dev)->gen >= 4) { | |
7554 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) | |
7555 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
7556 | crtc_state->dpll_hw_state.dpll_md = dpll_md; | |
7557 | } | |
7558 | } | |
7559 | ||
7560 | static void i8xx_compute_dpll(struct intel_crtc *crtc, | |
7561 | struct intel_crtc_state *crtc_state, | |
7562 | intel_clock_t *reduced_clock) | |
7563 | { | |
7564 | struct drm_device *dev = crtc->base.dev; | |
7565 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7566 | u32 dpll; | |
7567 | struct dpll *clock = &crtc_state->dpll; | |
7568 | ||
7569 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); | |
7570 | ||
7571 | dpll = DPLL_VGA_MODE_DIS; | |
7572 | ||
7573 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { | |
7574 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7575 | } else { | |
7576 | if (clock->p1 == 2) | |
7577 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7578 | else | |
7579 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7580 | if (clock->p2 == 4) | |
7581 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7582 | } | |
7583 | ||
7584 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) | |
7585 | dpll |= DPLL_DVO_2X_MODE; | |
7586 | ||
7587 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && | |
7588 | intel_panel_use_ssc(dev_priv)) | |
7589 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7590 | else | |
7591 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7592 | ||
7593 | dpll |= DPLL_VCO_ENABLE; | |
7594 | crtc_state->dpll_hw_state.dpll = dpll; | |
7595 | } | |
7596 | ||
7597 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) | |
7598 | { | |
7599 | struct drm_device *dev = intel_crtc->base.dev; | |
7600 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7601 | enum pipe pipe = intel_crtc->pipe; | |
7602 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; | |
7603 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; | |
7604 | uint32_t crtc_vtotal, crtc_vblank_end; | |
7605 | int vsyncshift = 0; | |
7606 | ||
7607 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7608 | * the hw state checker will get angry at the mismatch. */ | |
7609 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7610 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
7611 | ||
7612 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
7613 | /* the chip adds 2 halflines automatically */ | |
7614 | crtc_vtotal -= 1; | |
7615 | crtc_vblank_end -= 1; | |
7616 | ||
7617 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) | |
7618 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; | |
7619 | else | |
7620 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7621 | adjusted_mode->crtc_htotal / 2; | |
7622 | if (vsyncshift < 0) | |
7623 | vsyncshift += adjusted_mode->crtc_htotal; | |
7624 | } | |
7625 | ||
7626 | if (INTEL_INFO(dev)->gen > 3) | |
7627 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); | |
7628 | ||
7629 | I915_WRITE(HTOTAL(cpu_transcoder), | |
7630 | (adjusted_mode->crtc_hdisplay - 1) | | |
7631 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
7632 | I915_WRITE(HBLANK(cpu_transcoder), | |
7633 | (adjusted_mode->crtc_hblank_start - 1) | | |
7634 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
7635 | I915_WRITE(HSYNC(cpu_transcoder), | |
7636 | (adjusted_mode->crtc_hsync_start - 1) | | |
7637 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7638 | ||
7639 | I915_WRITE(VTOTAL(cpu_transcoder), | |
7640 | (adjusted_mode->crtc_vdisplay - 1) | | |
7641 | ((crtc_vtotal - 1) << 16)); | |
7642 | I915_WRITE(VBLANK(cpu_transcoder), | |
7643 | (adjusted_mode->crtc_vblank_start - 1) | | |
7644 | ((crtc_vblank_end - 1) << 16)); | |
7645 | I915_WRITE(VSYNC(cpu_transcoder), | |
7646 | (adjusted_mode->crtc_vsync_start - 1) | | |
7647 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7648 | ||
7649 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be | |
7650 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7651 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7652 | * bits. */ | |
7653 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7654 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7655 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7656 | ||
7657 | } | |
7658 | ||
7659 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
7660 | { | |
7661 | struct drm_device *dev = intel_crtc->base.dev; | |
7662 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7663 | enum pipe pipe = intel_crtc->pipe; | |
7664 | ||
7665 | /* pipesrc controls the size that is scaled from, which should | |
7666 | * always be the user's requested size. | |
7667 | */ | |
7668 | I915_WRITE(PIPESRC(pipe), | |
7669 | ((intel_crtc->config->pipe_src_w - 1) << 16) | | |
7670 | (intel_crtc->config->pipe_src_h - 1)); | |
7671 | } | |
7672 | ||
7673 | static void intel_get_pipe_timings(struct intel_crtc *crtc, | |
7674 | struct intel_crtc_state *pipe_config) | |
7675 | { | |
7676 | struct drm_device *dev = crtc->base.dev; | |
7677 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7678 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7679 | uint32_t tmp; | |
7680 | ||
7681 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
7682 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
7683 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
7684 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
7685 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
7686 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
7687 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
7688 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
7689 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
7690 | ||
7691 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
7692 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
7693 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
7694 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
7695 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
7696 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
7697 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
7698 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
7699 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
7700 | ||
7701 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
7702 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
7703 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7704 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
7705 | } | |
7706 | } | |
7707 | ||
7708 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
7709 | struct intel_crtc_state *pipe_config) | |
7710 | { | |
7711 | struct drm_device *dev = crtc->base.dev; | |
7712 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7713 | u32 tmp; | |
7714 | ||
7715 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
7716 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; | |
7717 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7718 | ||
7719 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; | |
7720 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
7721 | } | |
7722 | ||
7723 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, | |
7724 | struct intel_crtc_state *pipe_config) | |
7725 | { | |
7726 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; | |
7727 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7728 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7729 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
7730 | ||
7731 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; | |
7732 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7733 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7734 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
7735 | ||
7736 | mode->flags = pipe_config->base.adjusted_mode.flags; | |
7737 | mode->type = DRM_MODE_TYPE_DRIVER; | |
7738 | ||
7739 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; | |
7740 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
7741 | ||
7742 | mode->hsync = drm_mode_hsync(mode); | |
7743 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7744 | drm_mode_set_name(mode); | |
7745 | } | |
7746 | ||
7747 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) | |
7748 | { | |
7749 | struct drm_device *dev = intel_crtc->base.dev; | |
7750 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7751 | uint32_t pipeconf; | |
7752 | ||
7753 | pipeconf = 0; | |
7754 | ||
7755 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
7756 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7757 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
7758 | ||
7759 | if (intel_crtc->config->double_wide) | |
7760 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
7761 | ||
7762 | /* only g4x and later have fancy bpc/dither controls */ | |
7763 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { | |
7764 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ | |
7765 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) | |
7766 | pipeconf |= PIPECONF_DITHER_EN | | |
7767 | PIPECONF_DITHER_TYPE_SP; | |
7768 | ||
7769 | switch (intel_crtc->config->pipe_bpp) { | |
7770 | case 18: | |
7771 | pipeconf |= PIPECONF_6BPC; | |
7772 | break; | |
7773 | case 24: | |
7774 | pipeconf |= PIPECONF_8BPC; | |
7775 | break; | |
7776 | case 30: | |
7777 | pipeconf |= PIPECONF_10BPC; | |
7778 | break; | |
7779 | default: | |
7780 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7781 | BUG(); | |
7782 | } | |
7783 | } | |
7784 | ||
7785 | if (HAS_PIPE_CXSR(dev)) { | |
7786 | if (intel_crtc->lowfreq_avail) { | |
7787 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7788 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7789 | } else { | |
7790 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
7791 | } | |
7792 | } | |
7793 | ||
7794 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { | |
7795 | if (INTEL_INFO(dev)->gen < 4 || | |
7796 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) | |
7797 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
7798 | else | |
7799 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7800 | } else | |
7801 | pipeconf |= PIPECONF_PROGRESSIVE; | |
7802 | ||
7803 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && | |
7804 | intel_crtc->config->limited_color_range) | |
7805 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
7806 | ||
7807 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); | |
7808 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7809 | } | |
7810 | ||
7811 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, | |
7812 | struct intel_crtc_state *crtc_state) | |
7813 | { | |
7814 | struct drm_device *dev = crtc->base.dev; | |
7815 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7816 | const intel_limit_t *limit; | |
7817 | int refclk = 48000; | |
7818 | ||
7819 | memset(&crtc_state->dpll_hw_state, 0, | |
7820 | sizeof(crtc_state->dpll_hw_state)); | |
7821 | ||
7822 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { | |
7823 | if (intel_panel_use_ssc(dev_priv)) { | |
7824 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7825 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7826 | } | |
7827 | ||
7828 | limit = &intel_limits_i8xx_lvds; | |
7829 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) { | |
7830 | limit = &intel_limits_i8xx_dvo; | |
7831 | } else { | |
7832 | limit = &intel_limits_i8xx_dac; | |
7833 | } | |
7834 | ||
7835 | if (!crtc_state->clock_set && | |
7836 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7837 | refclk, NULL, &crtc_state->dpll)) { | |
7838 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7839 | return -EINVAL; | |
7840 | } | |
7841 | ||
7842 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
7843 | ||
7844 | return 0; | |
7845 | } | |
7846 | ||
7847 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, | |
7848 | struct intel_crtc_state *crtc_state) | |
7849 | { | |
7850 | struct drm_device *dev = crtc->base.dev; | |
7851 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7852 | const intel_limit_t *limit; | |
7853 | int refclk = 96000; | |
7854 | ||
7855 | memset(&crtc_state->dpll_hw_state, 0, | |
7856 | sizeof(crtc_state->dpll_hw_state)); | |
7857 | ||
7858 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { | |
7859 | if (intel_panel_use_ssc(dev_priv)) { | |
7860 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7861 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7862 | } | |
7863 | ||
7864 | if (intel_is_dual_link_lvds(dev)) | |
7865 | limit = &intel_limits_g4x_dual_channel_lvds; | |
7866 | else | |
7867 | limit = &intel_limits_g4x_single_channel_lvds; | |
7868 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || | |
7869 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
7870 | limit = &intel_limits_g4x_hdmi; | |
7871 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { | |
7872 | limit = &intel_limits_g4x_sdvo; | |
7873 | } else { | |
7874 | /* The option is for other outputs */ | |
7875 | limit = &intel_limits_i9xx_sdvo; | |
7876 | } | |
7877 | ||
7878 | if (!crtc_state->clock_set && | |
7879 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7880 | refclk, NULL, &crtc_state->dpll)) { | |
7881 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7882 | return -EINVAL; | |
7883 | } | |
7884 | ||
7885 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7886 | ||
7887 | return 0; | |
7888 | } | |
7889 | ||
7890 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, | |
7891 | struct intel_crtc_state *crtc_state) | |
7892 | { | |
7893 | struct drm_device *dev = crtc->base.dev; | |
7894 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7895 | const intel_limit_t *limit; | |
7896 | int refclk = 96000; | |
7897 | ||
7898 | memset(&crtc_state->dpll_hw_state, 0, | |
7899 | sizeof(crtc_state->dpll_hw_state)); | |
7900 | ||
7901 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { | |
7902 | if (intel_panel_use_ssc(dev_priv)) { | |
7903 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7904 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7905 | } | |
7906 | ||
7907 | limit = &intel_limits_pineview_lvds; | |
7908 | } else { | |
7909 | limit = &intel_limits_pineview_sdvo; | |
7910 | } | |
7911 | ||
7912 | if (!crtc_state->clock_set && | |
7913 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7914 | refclk, NULL, &crtc_state->dpll)) { | |
7915 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7916 | return -EINVAL; | |
7917 | } | |
7918 | ||
7919 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7920 | ||
7921 | return 0; | |
7922 | } | |
7923 | ||
7924 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, | |
7925 | struct intel_crtc_state *crtc_state) | |
7926 | { | |
7927 | struct drm_device *dev = crtc->base.dev; | |
7928 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7929 | const intel_limit_t *limit; | |
7930 | int refclk = 96000; | |
7931 | ||
7932 | memset(&crtc_state->dpll_hw_state, 0, | |
7933 | sizeof(crtc_state->dpll_hw_state)); | |
7934 | ||
7935 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { | |
7936 | if (intel_panel_use_ssc(dev_priv)) { | |
7937 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7938 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7939 | } | |
7940 | ||
7941 | limit = &intel_limits_i9xx_lvds; | |
7942 | } else { | |
7943 | limit = &intel_limits_i9xx_sdvo; | |
7944 | } | |
7945 | ||
7946 | if (!crtc_state->clock_set && | |
7947 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7948 | refclk, NULL, &crtc_state->dpll)) { | |
7949 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7950 | return -EINVAL; | |
7951 | } | |
7952 | ||
7953 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7954 | ||
7955 | return 0; | |
7956 | } | |
7957 | ||
7958 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, | |
7959 | struct intel_crtc_state *crtc_state) | |
7960 | { | |
7961 | int refclk = 100000; | |
7962 | const intel_limit_t *limit = &intel_limits_chv; | |
7963 | ||
7964 | memset(&crtc_state->dpll_hw_state, 0, | |
7965 | sizeof(crtc_state->dpll_hw_state)); | |
7966 | ||
7967 | if (!crtc_state->clock_set && | |
7968 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7969 | refclk, NULL, &crtc_state->dpll)) { | |
7970 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7971 | return -EINVAL; | |
7972 | } | |
7973 | ||
7974 | chv_compute_dpll(crtc, crtc_state); | |
7975 | ||
7976 | return 0; | |
7977 | } | |
7978 | ||
7979 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
7980 | struct intel_crtc_state *crtc_state) | |
7981 | { | |
7982 | int refclk = 100000; | |
7983 | const intel_limit_t *limit = &intel_limits_vlv; | |
7984 | ||
7985 | memset(&crtc_state->dpll_hw_state, 0, | |
7986 | sizeof(crtc_state->dpll_hw_state)); | |
7987 | ||
7988 | if (!crtc_state->clock_set && | |
7989 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7990 | refclk, NULL, &crtc_state->dpll)) { | |
7991 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7992 | return -EINVAL; | |
7993 | } | |
7994 | ||
7995 | vlv_compute_dpll(crtc, crtc_state); | |
7996 | ||
7997 | return 0; | |
7998 | } | |
7999 | ||
8000 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, | |
8001 | struct intel_crtc_state *pipe_config) | |
8002 | { | |
8003 | struct drm_device *dev = crtc->base.dev; | |
8004 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8005 | uint32_t tmp; | |
8006 | ||
8007 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) | |
8008 | return; | |
8009 | ||
8010 | tmp = I915_READ(PFIT_CONTROL); | |
8011 | if (!(tmp & PFIT_ENABLE)) | |
8012 | return; | |
8013 | ||
8014 | /* Check whether the pfit is attached to our pipe. */ | |
8015 | if (INTEL_INFO(dev)->gen < 4) { | |
8016 | if (crtc->pipe != PIPE_B) | |
8017 | return; | |
8018 | } else { | |
8019 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
8020 | return; | |
8021 | } | |
8022 | ||
8023 | pipe_config->gmch_pfit.control = tmp; | |
8024 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); | |
8025 | } | |
8026 | ||
8027 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, | |
8028 | struct intel_crtc_state *pipe_config) | |
8029 | { | |
8030 | struct drm_device *dev = crtc->base.dev; | |
8031 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8032 | int pipe = pipe_config->cpu_transcoder; | |
8033 | intel_clock_t clock; | |
8034 | u32 mdiv; | |
8035 | int refclk = 100000; | |
8036 | ||
8037 | /* In case of DSI, DPLL will not be used */ | |
8038 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
8039 | return; | |
8040 | ||
8041 | mutex_lock(&dev_priv->sb_lock); | |
8042 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); | |
8043 | mutex_unlock(&dev_priv->sb_lock); | |
8044 | ||
8045 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8046 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8047 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8048 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8049 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8050 | ||
8051 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); | |
8052 | } | |
8053 | ||
8054 | static void | |
8055 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8056 | struct intel_initial_plane_config *plane_config) | |
8057 | { | |
8058 | struct drm_device *dev = crtc->base.dev; | |
8059 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8060 | u32 val, base, offset; | |
8061 | int pipe = crtc->pipe, plane = crtc->plane; | |
8062 | int fourcc, pixel_format; | |
8063 | unsigned int aligned_height; | |
8064 | struct drm_framebuffer *fb; | |
8065 | struct intel_framebuffer *intel_fb; | |
8066 | ||
8067 | val = I915_READ(DSPCNTR(plane)); | |
8068 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8069 | return; | |
8070 | ||
8071 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
8072 | if (!intel_fb) { | |
8073 | DRM_DEBUG_KMS("failed to alloc fb\n"); | |
8074 | return; | |
8075 | } | |
8076 | ||
8077 | fb = &intel_fb->base; | |
8078 | ||
8079 | if (INTEL_INFO(dev)->gen >= 4) { | |
8080 | if (val & DISPPLANE_TILED) { | |
8081 | plane_config->tiling = I915_TILING_X; | |
8082 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
8083 | } | |
8084 | } | |
8085 | ||
8086 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
8087 | fourcc = i9xx_format_to_fourcc(pixel_format); | |
8088 | fb->pixel_format = fourcc; | |
8089 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
8090 | ||
8091 | if (INTEL_INFO(dev)->gen >= 4) { | |
8092 | if (plane_config->tiling) | |
8093 | offset = I915_READ(DSPTILEOFF(plane)); | |
8094 | else | |
8095 | offset = I915_READ(DSPLINOFF(plane)); | |
8096 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8097 | } else { | |
8098 | base = I915_READ(DSPADDR(plane)); | |
8099 | } | |
8100 | plane_config->base = base; | |
8101 | ||
8102 | val = I915_READ(PIPESRC(pipe)); | |
8103 | fb->width = ((val >> 16) & 0xfff) + 1; | |
8104 | fb->height = ((val >> 0) & 0xfff) + 1; | |
8105 | ||
8106 | val = I915_READ(DSPSTRIDE(pipe)); | |
8107 | fb->pitches[0] = val & 0xffffffc0; | |
8108 | ||
8109 | aligned_height = intel_fb_align_height(dev, fb->height, | |
8110 | fb->pixel_format, | |
8111 | fb->modifier[0]); | |
8112 | ||
8113 | plane_config->size = fb->pitches[0] * aligned_height; | |
8114 | ||
8115 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
8116 | pipe_name(pipe), plane, fb->width, fb->height, | |
8117 | fb->bits_per_pixel, base, fb->pitches[0], | |
8118 | plane_config->size); | |
8119 | ||
8120 | plane_config->fb = intel_fb; | |
8121 | } | |
8122 | ||
8123 | static void chv_crtc_clock_get(struct intel_crtc *crtc, | |
8124 | struct intel_crtc_state *pipe_config) | |
8125 | { | |
8126 | struct drm_device *dev = crtc->base.dev; | |
8127 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8128 | int pipe = pipe_config->cpu_transcoder; | |
8129 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
8130 | intel_clock_t clock; | |
8131 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; | |
8132 | int refclk = 100000; | |
8133 | ||
8134 | /* In case of DSI, DPLL will not be used */ | |
8135 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
8136 | return; | |
8137 | ||
8138 | mutex_lock(&dev_priv->sb_lock); | |
8139 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
8140 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8141 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8142 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
8143 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); | |
8144 | mutex_unlock(&dev_priv->sb_lock); | |
8145 | ||
8146 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
8147 | clock.m2 = (pll_dw0 & 0xff) << 22; | |
8148 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8149 | clock.m2 |= pll_dw2 & 0x3fffff; | |
8150 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
8151 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8152 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8153 | ||
8154 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); | |
8155 | } | |
8156 | ||
8157 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, | |
8158 | struct intel_crtc_state *pipe_config) | |
8159 | { | |
8160 | struct drm_device *dev = crtc->base.dev; | |
8161 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8162 | enum intel_display_power_domain power_domain; | |
8163 | uint32_t tmp; | |
8164 | bool ret; | |
8165 | ||
8166 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); | |
8167 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
8168 | return false; | |
8169 | ||
8170 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; | |
8171 | pipe_config->shared_dpll = NULL; | |
8172 | ||
8173 | ret = false; | |
8174 | ||
8175 | tmp = I915_READ(PIPECONF(crtc->pipe)); | |
8176 | if (!(tmp & PIPECONF_ENABLE)) | |
8177 | goto out; | |
8178 | ||
8179 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { | |
8180 | switch (tmp & PIPECONF_BPC_MASK) { | |
8181 | case PIPECONF_6BPC: | |
8182 | pipe_config->pipe_bpp = 18; | |
8183 | break; | |
8184 | case PIPECONF_8BPC: | |
8185 | pipe_config->pipe_bpp = 24; | |
8186 | break; | |
8187 | case PIPECONF_10BPC: | |
8188 | pipe_config->pipe_bpp = 30; | |
8189 | break; | |
8190 | default: | |
8191 | break; | |
8192 | } | |
8193 | } | |
8194 | ||
8195 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && | |
8196 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
8197 | pipe_config->limited_color_range = true; | |
8198 | ||
8199 | if (INTEL_INFO(dev)->gen < 4) | |
8200 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8201 | ||
8202 | intel_get_pipe_timings(crtc, pipe_config); | |
8203 | intel_get_pipe_src_size(crtc, pipe_config); | |
8204 | ||
8205 | i9xx_get_pfit_config(crtc, pipe_config); | |
8206 | ||
8207 | if (INTEL_INFO(dev)->gen >= 4) { | |
8208 | /* No way to read it out on pipes B and C */ | |
8209 | if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A) | |
8210 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; | |
8211 | else | |
8212 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
8213 | pipe_config->pixel_multiplier = | |
8214 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8215 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8216 | pipe_config->dpll_hw_state.dpll_md = tmp; | |
8217 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { | |
8218 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8219 | pipe_config->pixel_multiplier = | |
8220 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8221 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8222 | } else { | |
8223 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8224 | * port and will be fixed up in the encoder->get_config | |
8225 | * function. */ | |
8226 | pipe_config->pixel_multiplier = 1; | |
8227 | } | |
8228 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); | |
8229 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { | |
8230 | /* | |
8231 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8232 | * on 830. Filter it out here so that we don't | |
8233 | * report errors due to that. | |
8234 | */ | |
8235 | if (IS_I830(dev)) | |
8236 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8237 | ||
8238 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); | |
8239 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
8240 | } else { | |
8241 | /* Mask out read-only status bits. */ | |
8242 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8243 | DPLL_PORTC_READY_MASK | | |
8244 | DPLL_PORTB_READY_MASK); | |
8245 | } | |
8246 | ||
8247 | if (IS_CHERRYVIEW(dev)) | |
8248 | chv_crtc_clock_get(crtc, pipe_config); | |
8249 | else if (IS_VALLEYVIEW(dev)) | |
8250 | vlv_crtc_clock_get(crtc, pipe_config); | |
8251 | else | |
8252 | i9xx_crtc_clock_get(crtc, pipe_config); | |
8253 | ||
8254 | /* | |
8255 | * Normally the dotclock is filled in by the encoder .get_config() | |
8256 | * but in case the pipe is enabled w/o any ports we need a sane | |
8257 | * default. | |
8258 | */ | |
8259 | pipe_config->base.adjusted_mode.crtc_clock = | |
8260 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8261 | ||
8262 | ret = true; | |
8263 | ||
8264 | out: | |
8265 | intel_display_power_put(dev_priv, power_domain); | |
8266 | ||
8267 | return ret; | |
8268 | } | |
8269 | ||
8270 | static void ironlake_init_pch_refclk(struct drm_device *dev) | |
8271 | { | |
8272 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8273 | struct intel_encoder *encoder; | |
8274 | u32 val, final; | |
8275 | bool has_lvds = false; | |
8276 | bool has_cpu_edp = false; | |
8277 | bool has_panel = false; | |
8278 | bool has_ck505 = false; | |
8279 | bool can_ssc = false; | |
8280 | ||
8281 | /* We need to take the global config into account */ | |
8282 | for_each_intel_encoder(dev, encoder) { | |
8283 | switch (encoder->type) { | |
8284 | case INTEL_OUTPUT_LVDS: | |
8285 | has_panel = true; | |
8286 | has_lvds = true; | |
8287 | break; | |
8288 | case INTEL_OUTPUT_EDP: | |
8289 | has_panel = true; | |
8290 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) | |
8291 | has_cpu_edp = true; | |
8292 | break; | |
8293 | default: | |
8294 | break; | |
8295 | } | |
8296 | } | |
8297 | ||
8298 | if (HAS_PCH_IBX(dev)) { | |
8299 | has_ck505 = dev_priv->vbt.display_clock_mode; | |
8300 | can_ssc = has_ck505; | |
8301 | } else { | |
8302 | has_ck505 = false; | |
8303 | can_ssc = true; | |
8304 | } | |
8305 | ||
8306 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", | |
8307 | has_panel, has_lvds, has_ck505); | |
8308 | ||
8309 | /* Ironlake: try to setup display ref clock before DPLL | |
8310 | * enabling. This is only under driver's control after | |
8311 | * PCH B stepping, previous chipset stepping should be | |
8312 | * ignoring this setting. | |
8313 | */ | |
8314 | val = I915_READ(PCH_DREF_CONTROL); | |
8315 | ||
8316 | /* As we must carefully and slowly disable/enable each source in turn, | |
8317 | * compute the final state we want first and check if we need to | |
8318 | * make any changes at all. | |
8319 | */ | |
8320 | final = val; | |
8321 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8322 | if (has_ck505) | |
8323 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8324 | else | |
8325 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8326 | ||
8327 | final &= ~DREF_SSC_SOURCE_MASK; | |
8328 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8329 | final &= ~DREF_SSC1_ENABLE; | |
8330 | ||
8331 | if (has_panel) { | |
8332 | final |= DREF_SSC_SOURCE_ENABLE; | |
8333 | ||
8334 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8335 | final |= DREF_SSC1_ENABLE; | |
8336 | ||
8337 | if (has_cpu_edp) { | |
8338 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8339 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8340 | else | |
8341 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8342 | } else | |
8343 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8344 | } else { | |
8345 | final |= DREF_SSC_SOURCE_DISABLE; | |
8346 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8347 | } | |
8348 | ||
8349 | if (final == val) | |
8350 | return; | |
8351 | ||
8352 | /* Always enable nonspread source */ | |
8353 | val &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8354 | ||
8355 | if (has_ck505) | |
8356 | val |= DREF_NONSPREAD_CK505_ENABLE; | |
8357 | else | |
8358 | val |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8359 | ||
8360 | if (has_panel) { | |
8361 | val &= ~DREF_SSC_SOURCE_MASK; | |
8362 | val |= DREF_SSC_SOURCE_ENABLE; | |
8363 | ||
8364 | /* SSC must be turned on before enabling the CPU output */ | |
8365 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { | |
8366 | DRM_DEBUG_KMS("Using SSC on panel\n"); | |
8367 | val |= DREF_SSC1_ENABLE; | |
8368 | } else | |
8369 | val &= ~DREF_SSC1_ENABLE; | |
8370 | ||
8371 | /* Get SSC going before enabling the outputs */ | |
8372 | I915_WRITE(PCH_DREF_CONTROL, val); | |
8373 | POSTING_READ(PCH_DREF_CONTROL); | |
8374 | udelay(200); | |
8375 | ||
8376 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8377 | ||
8378 | /* Enable CPU source on CPU attached eDP */ | |
8379 | if (has_cpu_edp) { | |
8380 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { | |
8381 | DRM_DEBUG_KMS("Using SSC on eDP\n"); | |
8382 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8383 | } else | |
8384 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8385 | } else | |
8386 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8387 | ||
8388 | I915_WRITE(PCH_DREF_CONTROL, val); | |
8389 | POSTING_READ(PCH_DREF_CONTROL); | |
8390 | udelay(200); | |
8391 | } else { | |
8392 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8393 | ||
8394 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8395 | ||
8396 | /* Turn off CPU output */ | |
8397 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8398 | ||
8399 | I915_WRITE(PCH_DREF_CONTROL, val); | |
8400 | POSTING_READ(PCH_DREF_CONTROL); | |
8401 | udelay(200); | |
8402 | ||
8403 | /* Turn off the SSC source */ | |
8404 | val &= ~DREF_SSC_SOURCE_MASK; | |
8405 | val |= DREF_SSC_SOURCE_DISABLE; | |
8406 | ||
8407 | /* Turn off SSC1 */ | |
8408 | val &= ~DREF_SSC1_ENABLE; | |
8409 | ||
8410 | I915_WRITE(PCH_DREF_CONTROL, val); | |
8411 | POSTING_READ(PCH_DREF_CONTROL); | |
8412 | udelay(200); | |
8413 | } | |
8414 | ||
8415 | BUG_ON(val != final); | |
8416 | } | |
8417 | ||
8418 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) | |
8419 | { | |
8420 | uint32_t tmp; | |
8421 | ||
8422 | tmp = I915_READ(SOUTH_CHICKEN2); | |
8423 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8424 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
8425 | ||
8426 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & | |
8427 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8428 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
8429 | ||
8430 | tmp = I915_READ(SOUTH_CHICKEN2); | |
8431 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8432 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
8433 | ||
8434 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & | |
8435 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8436 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
8437 | } | |
8438 | ||
8439 | /* WaMPhyProgramming:hsw */ | |
8440 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8441 | { | |
8442 | uint32_t tmp; | |
8443 | ||
8444 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8445 | tmp &= ~(0xFF << 24); | |
8446 | tmp |= (0x12 << 24); | |
8447 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8448 | ||
8449 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); | |
8450 | tmp |= (1 << 11); | |
8451 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8452 | ||
8453 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8454 | tmp |= (1 << 11); | |
8455 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8456 | ||
8457 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); | |
8458 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8459 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8460 | ||
8461 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8462 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8463 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8464 | ||
8465 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); | |
8466 | tmp &= ~(7 << 13); | |
8467 | tmp |= (5 << 13); | |
8468 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
8469 | ||
8470 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); | |
8471 | tmp &= ~(7 << 13); | |
8472 | tmp |= (5 << 13); | |
8473 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
8474 | ||
8475 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8476 | tmp &= ~0xFF; | |
8477 | tmp |= 0x1C; | |
8478 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8479 | ||
8480 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8481 | tmp &= ~0xFF; | |
8482 | tmp |= 0x1C; | |
8483 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8484 | ||
8485 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8486 | tmp &= ~(0xFF << 16); | |
8487 | tmp |= (0x1C << 16); | |
8488 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8489 | ||
8490 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8491 | tmp &= ~(0xFF << 16); | |
8492 | tmp |= (0x1C << 16); | |
8493 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8494 | ||
8495 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); | |
8496 | tmp |= (1 << 27); | |
8497 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
8498 | ||
8499 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); | |
8500 | tmp |= (1 << 27); | |
8501 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
8502 | ||
8503 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); | |
8504 | tmp &= ~(0xF << 28); | |
8505 | tmp |= (4 << 28); | |
8506 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
8507 | ||
8508 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); | |
8509 | tmp &= ~(0xF << 28); | |
8510 | tmp |= (4 << 28); | |
8511 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
8512 | } | |
8513 | ||
8514 | /* Implements 3 different sequences from BSpec chapter "Display iCLK | |
8515 | * Programming" based on the parameters passed: | |
8516 | * - Sequence to enable CLKOUT_DP | |
8517 | * - Sequence to enable CLKOUT_DP without spread | |
8518 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8519 | */ | |
8520 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8521 | bool with_fdi) | |
8522 | { | |
8523 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8524 | uint32_t reg, tmp; | |
8525 | ||
8526 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8527 | with_spread = true; | |
8528 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) | |
8529 | with_fdi = false; | |
8530 | ||
8531 | mutex_lock(&dev_priv->sb_lock); | |
8532 | ||
8533 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8534 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8535 | tmp |= SBI_SSCCTL_PATHALT; | |
8536 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8537 | ||
8538 | udelay(24); | |
8539 | ||
8540 | if (with_spread) { | |
8541 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8542 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8543 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8544 | ||
8545 | if (with_fdi) { | |
8546 | lpt_reset_fdi_mphy(dev_priv); | |
8547 | lpt_program_fdi_mphy(dev_priv); | |
8548 | } | |
8549 | } | |
8550 | ||
8551 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; | |
8552 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
8553 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8554 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8555 | ||
8556 | mutex_unlock(&dev_priv->sb_lock); | |
8557 | } | |
8558 | ||
8559 | /* Sequence to disable CLKOUT_DP */ | |
8560 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8561 | { | |
8562 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8563 | uint32_t reg, tmp; | |
8564 | ||
8565 | mutex_lock(&dev_priv->sb_lock); | |
8566 | ||
8567 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; | |
8568 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
8569 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8570 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8571 | ||
8572 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8573 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8574 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8575 | tmp |= SBI_SSCCTL_PATHALT; | |
8576 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8577 | udelay(32); | |
8578 | } | |
8579 | tmp |= SBI_SSCCTL_DISABLE; | |
8580 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8581 | } | |
8582 | ||
8583 | mutex_unlock(&dev_priv->sb_lock); | |
8584 | } | |
8585 | ||
8586 | #define BEND_IDX(steps) ((50 + (steps)) / 5) | |
8587 | ||
8588 | static const uint16_t sscdivintphase[] = { | |
8589 | [BEND_IDX( 50)] = 0x3B23, | |
8590 | [BEND_IDX( 45)] = 0x3B23, | |
8591 | [BEND_IDX( 40)] = 0x3C23, | |
8592 | [BEND_IDX( 35)] = 0x3C23, | |
8593 | [BEND_IDX( 30)] = 0x3D23, | |
8594 | [BEND_IDX( 25)] = 0x3D23, | |
8595 | [BEND_IDX( 20)] = 0x3E23, | |
8596 | [BEND_IDX( 15)] = 0x3E23, | |
8597 | [BEND_IDX( 10)] = 0x3F23, | |
8598 | [BEND_IDX( 5)] = 0x3F23, | |
8599 | [BEND_IDX( 0)] = 0x0025, | |
8600 | [BEND_IDX( -5)] = 0x0025, | |
8601 | [BEND_IDX(-10)] = 0x0125, | |
8602 | [BEND_IDX(-15)] = 0x0125, | |
8603 | [BEND_IDX(-20)] = 0x0225, | |
8604 | [BEND_IDX(-25)] = 0x0225, | |
8605 | [BEND_IDX(-30)] = 0x0325, | |
8606 | [BEND_IDX(-35)] = 0x0325, | |
8607 | [BEND_IDX(-40)] = 0x0425, | |
8608 | [BEND_IDX(-45)] = 0x0425, | |
8609 | [BEND_IDX(-50)] = 0x0525, | |
8610 | }; | |
8611 | ||
8612 | /* | |
8613 | * Bend CLKOUT_DP | |
8614 | * steps -50 to 50 inclusive, in steps of 5 | |
8615 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8616 | * change in clock period = -(steps / 10) * 5.787 ps | |
8617 | */ | |
8618 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8619 | { | |
8620 | uint32_t tmp; | |
8621 | int idx = BEND_IDX(steps); | |
8622 | ||
8623 | if (WARN_ON(steps % 5 != 0)) | |
8624 | return; | |
8625 | ||
8626 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8627 | return; | |
8628 | ||
8629 | mutex_lock(&dev_priv->sb_lock); | |
8630 | ||
8631 | if (steps % 10 != 0) | |
8632 | tmp = 0xAAAAAAAB; | |
8633 | else | |
8634 | tmp = 0x00000000; | |
8635 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8636 | ||
8637 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8638 | tmp &= 0xffff0000; | |
8639 | tmp |= sscdivintphase[idx]; | |
8640 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8641 | ||
8642 | mutex_unlock(&dev_priv->sb_lock); | |
8643 | } | |
8644 | ||
8645 | #undef BEND_IDX | |
8646 | ||
8647 | static void lpt_init_pch_refclk(struct drm_device *dev) | |
8648 | { | |
8649 | struct intel_encoder *encoder; | |
8650 | bool has_vga = false; | |
8651 | ||
8652 | for_each_intel_encoder(dev, encoder) { | |
8653 | switch (encoder->type) { | |
8654 | case INTEL_OUTPUT_ANALOG: | |
8655 | has_vga = true; | |
8656 | break; | |
8657 | default: | |
8658 | break; | |
8659 | } | |
8660 | } | |
8661 | ||
8662 | if (has_vga) { | |
8663 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
8664 | lpt_enable_clkout_dp(dev, true, true); | |
8665 | } else { | |
8666 | lpt_disable_clkout_dp(dev); | |
8667 | } | |
8668 | } | |
8669 | ||
8670 | /* | |
8671 | * Initialize reference clocks when the driver loads | |
8672 | */ | |
8673 | void intel_init_pch_refclk(struct drm_device *dev) | |
8674 | { | |
8675 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8676 | ironlake_init_pch_refclk(dev); | |
8677 | else if (HAS_PCH_LPT(dev)) | |
8678 | lpt_init_pch_refclk(dev); | |
8679 | } | |
8680 | ||
8681 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) | |
8682 | { | |
8683 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
8684 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8685 | int pipe = intel_crtc->pipe; | |
8686 | uint32_t val; | |
8687 | ||
8688 | val = 0; | |
8689 | ||
8690 | switch (intel_crtc->config->pipe_bpp) { | |
8691 | case 18: | |
8692 | val |= PIPECONF_6BPC; | |
8693 | break; | |
8694 | case 24: | |
8695 | val |= PIPECONF_8BPC; | |
8696 | break; | |
8697 | case 30: | |
8698 | val |= PIPECONF_10BPC; | |
8699 | break; | |
8700 | case 36: | |
8701 | val |= PIPECONF_12BPC; | |
8702 | break; | |
8703 | default: | |
8704 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
8705 | BUG(); | |
8706 | } | |
8707 | ||
8708 | if (intel_crtc->config->dither) | |
8709 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); | |
8710 | ||
8711 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) | |
8712 | val |= PIPECONF_INTERLACED_ILK; | |
8713 | else | |
8714 | val |= PIPECONF_PROGRESSIVE; | |
8715 | ||
8716 | if (intel_crtc->config->limited_color_range) | |
8717 | val |= PIPECONF_COLOR_RANGE_SELECT; | |
8718 | ||
8719 | I915_WRITE(PIPECONF(pipe), val); | |
8720 | POSTING_READ(PIPECONF(pipe)); | |
8721 | } | |
8722 | ||
8723 | static void haswell_set_pipeconf(struct drm_crtc *crtc) | |
8724 | { | |
8725 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
8726 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8727 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; | |
8728 | u32 val = 0; | |
8729 | ||
8730 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) | |
8731 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); | |
8732 | ||
8733 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) | |
8734 | val |= PIPECONF_INTERLACED_ILK; | |
8735 | else | |
8736 | val |= PIPECONF_PROGRESSIVE; | |
8737 | ||
8738 | I915_WRITE(PIPECONF(cpu_transcoder), val); | |
8739 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
8740 | } | |
8741 | ||
8742 | static void haswell_set_pipemisc(struct drm_crtc *crtc) | |
8743 | { | |
8744 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
8745 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8746 | ||
8747 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { | |
8748 | u32 val = 0; | |
8749 | ||
8750 | switch (intel_crtc->config->pipe_bpp) { | |
8751 | case 18: | |
8752 | val |= PIPEMISC_DITHER_6_BPC; | |
8753 | break; | |
8754 | case 24: | |
8755 | val |= PIPEMISC_DITHER_8_BPC; | |
8756 | break; | |
8757 | case 30: | |
8758 | val |= PIPEMISC_DITHER_10_BPC; | |
8759 | break; | |
8760 | case 36: | |
8761 | val |= PIPEMISC_DITHER_12_BPC; | |
8762 | break; | |
8763 | default: | |
8764 | /* Case prevented by pipe_config_set_bpp. */ | |
8765 | BUG(); | |
8766 | } | |
8767 | ||
8768 | if (intel_crtc->config->dither) | |
8769 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; | |
8770 | ||
8771 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); | |
8772 | } | |
8773 | } | |
8774 | ||
8775 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) | |
8776 | { | |
8777 | /* | |
8778 | * Account for spread spectrum to avoid | |
8779 | * oversubscribing the link. Max center spread | |
8780 | * is 2.5%; use 5% for safety's sake. | |
8781 | */ | |
8782 | u32 bps = target_clock * bpp * 21 / 20; | |
8783 | return DIV_ROUND_UP(bps, link_bw * 8); | |
8784 | } | |
8785 | ||
8786 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) | |
8787 | { | |
8788 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; | |
8789 | } | |
8790 | ||
8791 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, | |
8792 | struct intel_crtc_state *crtc_state, | |
8793 | intel_clock_t *reduced_clock) | |
8794 | { | |
8795 | struct drm_crtc *crtc = &intel_crtc->base; | |
8796 | struct drm_device *dev = crtc->dev; | |
8797 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8798 | struct drm_atomic_state *state = crtc_state->base.state; | |
8799 | struct drm_connector *connector; | |
8800 | struct drm_connector_state *connector_state; | |
8801 | struct intel_encoder *encoder; | |
8802 | u32 dpll, fp, fp2; | |
8803 | int factor, i; | |
8804 | bool is_lvds = false, is_sdvo = false; | |
8805 | ||
8806 | for_each_connector_in_state(state, connector, connector_state, i) { | |
8807 | if (connector_state->crtc != crtc_state->base.crtc) | |
8808 | continue; | |
8809 | ||
8810 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8811 | ||
8812 | switch (encoder->type) { | |
8813 | case INTEL_OUTPUT_LVDS: | |
8814 | is_lvds = true; | |
8815 | break; | |
8816 | case INTEL_OUTPUT_SDVO: | |
8817 | case INTEL_OUTPUT_HDMI: | |
8818 | is_sdvo = true; | |
8819 | break; | |
8820 | default: | |
8821 | break; | |
8822 | } | |
8823 | } | |
8824 | ||
8825 | /* Enable autotuning of the PLL clock (if permissible) */ | |
8826 | factor = 21; | |
8827 | if (is_lvds) { | |
8828 | if ((intel_panel_use_ssc(dev_priv) && | |
8829 | dev_priv->vbt.lvds_ssc_freq == 100000) || | |
8830 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) | |
8831 | factor = 25; | |
8832 | } else if (crtc_state->sdvo_tv_clock) | |
8833 | factor = 20; | |
8834 | ||
8835 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
8836 | ||
8837 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) | |
8838 | fp |= FP_CB_TUNE; | |
8839 | ||
8840 | if (reduced_clock) { | |
8841 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
8842 | ||
8843 | if (reduced_clock->m < factor * reduced_clock->n) | |
8844 | fp2 |= FP_CB_TUNE; | |
8845 | } else { | |
8846 | fp2 = fp; | |
8847 | } | |
8848 | ||
8849 | dpll = 0; | |
8850 | ||
8851 | if (is_lvds) | |
8852 | dpll |= DPLLB_MODE_LVDS; | |
8853 | else | |
8854 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
8855 | ||
8856 | dpll |= (crtc_state->pixel_multiplier - 1) | |
8857 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
8858 | ||
8859 | if (is_sdvo) | |
8860 | dpll |= DPLL_SDVO_HIGH_SPEED; | |
8861 | if (crtc_state->has_dp_encoder) | |
8862 | dpll |= DPLL_SDVO_HIGH_SPEED; | |
8863 | ||
8864 | /* compute bitmask from p1 value */ | |
8865 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
8866 | /* also FPA1 */ | |
8867 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
8868 | ||
8869 | switch (crtc_state->dpll.p2) { | |
8870 | case 5: | |
8871 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8872 | break; | |
8873 | case 7: | |
8874 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8875 | break; | |
8876 | case 10: | |
8877 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8878 | break; | |
8879 | case 14: | |
8880 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8881 | break; | |
8882 | } | |
8883 | ||
8884 | if (is_lvds && intel_panel_use_ssc(dev_priv)) | |
8885 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
8886 | else | |
8887 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8888 | ||
8889 | dpll |= DPLL_VCO_ENABLE; | |
8890 | ||
8891 | crtc_state->dpll_hw_state.dpll = dpll; | |
8892 | crtc_state->dpll_hw_state.fp0 = fp; | |
8893 | crtc_state->dpll_hw_state.fp1 = fp2; | |
8894 | } | |
8895 | ||
8896 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, | |
8897 | struct intel_crtc_state *crtc_state) | |
8898 | { | |
8899 | struct drm_device *dev = crtc->base.dev; | |
8900 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8901 | intel_clock_t reduced_clock; | |
8902 | bool has_reduced_clock = false; | |
8903 | struct intel_shared_dpll *pll; | |
8904 | const intel_limit_t *limit; | |
8905 | int refclk = 120000; | |
8906 | ||
8907 | memset(&crtc_state->dpll_hw_state, 0, | |
8908 | sizeof(crtc_state->dpll_hw_state)); | |
8909 | ||
8910 | crtc->lowfreq_avail = false; | |
8911 | ||
8912 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
8913 | if (!crtc_state->has_pch_encoder) | |
8914 | return 0; | |
8915 | ||
8916 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { | |
8917 | if (intel_panel_use_ssc(dev_priv)) { | |
8918 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
8919 | dev_priv->vbt.lvds_ssc_freq); | |
8920 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8921 | } | |
8922 | ||
8923 | if (intel_is_dual_link_lvds(dev)) { | |
8924 | if (refclk == 100000) | |
8925 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
8926 | else | |
8927 | limit = &intel_limits_ironlake_dual_lvds; | |
8928 | } else { | |
8929 | if (refclk == 100000) | |
8930 | limit = &intel_limits_ironlake_single_lvds_100m; | |
8931 | else | |
8932 | limit = &intel_limits_ironlake_single_lvds; | |
8933 | } | |
8934 | } else { | |
8935 | limit = &intel_limits_ironlake_dac; | |
8936 | } | |
8937 | ||
8938 | if (!crtc_state->clock_set && | |
8939 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8940 | refclk, NULL, &crtc_state->dpll)) { | |
8941 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8942 | return -EINVAL; | |
8943 | } | |
8944 | ||
8945 | ironlake_compute_dpll(crtc, crtc_state, | |
8946 | has_reduced_clock ? &reduced_clock : NULL); | |
8947 | ||
8948 | pll = intel_get_shared_dpll(crtc, crtc_state, NULL); | |
8949 | if (pll == NULL) { | |
8950 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
8951 | pipe_name(crtc->pipe)); | |
8952 | return -EINVAL; | |
8953 | } | |
8954 | ||
8955 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && | |
8956 | has_reduced_clock) | |
8957 | crtc->lowfreq_avail = true; | |
8958 | ||
8959 | return 0; | |
8960 | } | |
8961 | ||
8962 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, | |
8963 | struct intel_link_m_n *m_n) | |
8964 | { | |
8965 | struct drm_device *dev = crtc->base.dev; | |
8966 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8967 | enum pipe pipe = crtc->pipe; | |
8968 | ||
8969 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8970 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8971 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8972 | & ~TU_SIZE_MASK; | |
8973 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8974 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8975 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8976 | } | |
8977 | ||
8978 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8979 | enum transcoder transcoder, | |
8980 | struct intel_link_m_n *m_n, | |
8981 | struct intel_link_m_n *m2_n2) | |
8982 | { | |
8983 | struct drm_device *dev = crtc->base.dev; | |
8984 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8985 | enum pipe pipe = crtc->pipe; | |
8986 | ||
8987 | if (INTEL_INFO(dev)->gen >= 5) { | |
8988 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
8989 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8990 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8991 | & ~TU_SIZE_MASK; | |
8992 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8993 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8994 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8995 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for | |
8996 | * gen < 8) and if DRRS is supported (to make sure the | |
8997 | * registers are not unnecessarily read). | |
8998 | */ | |
8999 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
9000 | crtc->config->has_drrs) { | |
9001 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); | |
9002 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9003 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9004 | & ~TU_SIZE_MASK; | |
9005 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9006 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9007 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9008 | } | |
9009 | } else { | |
9010 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9011 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9012 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9013 | & ~TU_SIZE_MASK; | |
9014 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9015 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9016 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9017 | } | |
9018 | } | |
9019 | ||
9020 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
9021 | struct intel_crtc_state *pipe_config) | |
9022 | { | |
9023 | if (pipe_config->has_pch_encoder) | |
9024 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); | |
9025 | else | |
9026 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
9027 | &pipe_config->dp_m_n, | |
9028 | &pipe_config->dp_m2_n2); | |
9029 | } | |
9030 | ||
9031 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, | |
9032 | struct intel_crtc_state *pipe_config) | |
9033 | { | |
9034 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
9035 | &pipe_config->fdi_m_n, NULL); | |
9036 | } | |
9037 | ||
9038 | static void skylake_get_pfit_config(struct intel_crtc *crtc, | |
9039 | struct intel_crtc_state *pipe_config) | |
9040 | { | |
9041 | struct drm_device *dev = crtc->base.dev; | |
9042 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9043 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; | |
9044 | uint32_t ps_ctrl = 0; | |
9045 | int id = -1; | |
9046 | int i; | |
9047 | ||
9048 | /* find scaler attached to this pipe */ | |
9049 | for (i = 0; i < crtc->num_scalers; i++) { | |
9050 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9051 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9052 | id = i; | |
9053 | pipe_config->pch_pfit.enabled = true; | |
9054 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9055 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9056 | break; | |
9057 | } | |
9058 | } | |
9059 | ||
9060 | scaler_state->scaler_id = id; | |
9061 | if (id >= 0) { | |
9062 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9063 | } else { | |
9064 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
9065 | } | |
9066 | } | |
9067 | ||
9068 | static void | |
9069 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9070 | struct intel_initial_plane_config *plane_config) | |
9071 | { | |
9072 | struct drm_device *dev = crtc->base.dev; | |
9073 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9074 | u32 val, base, offset, stride_mult, tiling; | |
9075 | int pipe = crtc->pipe; | |
9076 | int fourcc, pixel_format; | |
9077 | unsigned int aligned_height; | |
9078 | struct drm_framebuffer *fb; | |
9079 | struct intel_framebuffer *intel_fb; | |
9080 | ||
9081 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
9082 | if (!intel_fb) { | |
9083 | DRM_DEBUG_KMS("failed to alloc fb\n"); | |
9084 | return; | |
9085 | } | |
9086 | ||
9087 | fb = &intel_fb->base; | |
9088 | ||
9089 | val = I915_READ(PLANE_CTL(pipe, 0)); | |
9090 | if (!(val & PLANE_CTL_ENABLE)) | |
9091 | goto error; | |
9092 | ||
9093 | pixel_format = val & PLANE_CTL_FORMAT_MASK; | |
9094 | fourcc = skl_format_to_fourcc(pixel_format, | |
9095 | val & PLANE_CTL_ORDER_RGBX, | |
9096 | val & PLANE_CTL_ALPHA_MASK); | |
9097 | fb->pixel_format = fourcc; | |
9098 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9099 | ||
9100 | tiling = val & PLANE_CTL_TILED_MASK; | |
9101 | switch (tiling) { | |
9102 | case PLANE_CTL_TILED_LINEAR: | |
9103 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9104 | break; | |
9105 | case PLANE_CTL_TILED_X: | |
9106 | plane_config->tiling = I915_TILING_X; | |
9107 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9108 | break; | |
9109 | case PLANE_CTL_TILED_Y: | |
9110 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9111 | break; | |
9112 | case PLANE_CTL_TILED_YF: | |
9113 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9114 | break; | |
9115 | default: | |
9116 | MISSING_CASE(tiling); | |
9117 | goto error; | |
9118 | } | |
9119 | ||
9120 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; | |
9121 | plane_config->base = base; | |
9122 | ||
9123 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9124 | ||
9125 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9126 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9127 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9128 | ||
9129 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
9130 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], | |
9131 | fb->pixel_format); | |
9132 | fb->pitches[0] = (val & 0x3ff) * stride_mult; | |
9133 | ||
9134 | aligned_height = intel_fb_align_height(dev, fb->height, | |
9135 | fb->pixel_format, | |
9136 | fb->modifier[0]); | |
9137 | ||
9138 | plane_config->size = fb->pitches[0] * aligned_height; | |
9139 | ||
9140 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9141 | pipe_name(pipe), fb->width, fb->height, | |
9142 | fb->bits_per_pixel, base, fb->pitches[0], | |
9143 | plane_config->size); | |
9144 | ||
9145 | plane_config->fb = intel_fb; | |
9146 | return; | |
9147 | ||
9148 | error: | |
9149 | kfree(fb); | |
9150 | } | |
9151 | ||
9152 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, | |
9153 | struct intel_crtc_state *pipe_config) | |
9154 | { | |
9155 | struct drm_device *dev = crtc->base.dev; | |
9156 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9157 | uint32_t tmp; | |
9158 | ||
9159 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9160 | ||
9161 | if (tmp & PF_ENABLE) { | |
9162 | pipe_config->pch_pfit.enabled = true; | |
9163 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); | |
9164 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
9165 | ||
9166 | /* We currently do not free assignements of panel fitters on | |
9167 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9168 | * differentiates them) so just WARN about this case for now. */ | |
9169 | if (IS_GEN7(dev)) { | |
9170 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9171 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9172 | } | |
9173 | } | |
9174 | } | |
9175 | ||
9176 | static void | |
9177 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9178 | struct intel_initial_plane_config *plane_config) | |
9179 | { | |
9180 | struct drm_device *dev = crtc->base.dev; | |
9181 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9182 | u32 val, base, offset; | |
9183 | int pipe = crtc->pipe; | |
9184 | int fourcc, pixel_format; | |
9185 | unsigned int aligned_height; | |
9186 | struct drm_framebuffer *fb; | |
9187 | struct intel_framebuffer *intel_fb; | |
9188 | ||
9189 | val = I915_READ(DSPCNTR(pipe)); | |
9190 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9191 | return; | |
9192 | ||
9193 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
9194 | if (!intel_fb) { | |
9195 | DRM_DEBUG_KMS("failed to alloc fb\n"); | |
9196 | return; | |
9197 | } | |
9198 | ||
9199 | fb = &intel_fb->base; | |
9200 | ||
9201 | if (INTEL_INFO(dev)->gen >= 4) { | |
9202 | if (val & DISPPLANE_TILED) { | |
9203 | plane_config->tiling = I915_TILING_X; | |
9204 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9205 | } | |
9206 | } | |
9207 | ||
9208 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
9209 | fourcc = i9xx_format_to_fourcc(pixel_format); | |
9210 | fb->pixel_format = fourcc; | |
9211 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9212 | ||
9213 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; | |
9214 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
9215 | offset = I915_READ(DSPOFFSET(pipe)); | |
9216 | } else { | |
9217 | if (plane_config->tiling) | |
9218 | offset = I915_READ(DSPTILEOFF(pipe)); | |
9219 | else | |
9220 | offset = I915_READ(DSPLINOFF(pipe)); | |
9221 | } | |
9222 | plane_config->base = base; | |
9223 | ||
9224 | val = I915_READ(PIPESRC(pipe)); | |
9225 | fb->width = ((val >> 16) & 0xfff) + 1; | |
9226 | fb->height = ((val >> 0) & 0xfff) + 1; | |
9227 | ||
9228 | val = I915_READ(DSPSTRIDE(pipe)); | |
9229 | fb->pitches[0] = val & 0xffffffc0; | |
9230 | ||
9231 | aligned_height = intel_fb_align_height(dev, fb->height, | |
9232 | fb->pixel_format, | |
9233 | fb->modifier[0]); | |
9234 | ||
9235 | plane_config->size = fb->pitches[0] * aligned_height; | |
9236 | ||
9237 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9238 | pipe_name(pipe), fb->width, fb->height, | |
9239 | fb->bits_per_pixel, base, fb->pitches[0], | |
9240 | plane_config->size); | |
9241 | ||
9242 | plane_config->fb = intel_fb; | |
9243 | } | |
9244 | ||
9245 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, | |
9246 | struct intel_crtc_state *pipe_config) | |
9247 | { | |
9248 | struct drm_device *dev = crtc->base.dev; | |
9249 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9250 | enum intel_display_power_domain power_domain; | |
9251 | uint32_t tmp; | |
9252 | bool ret; | |
9253 | ||
9254 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); | |
9255 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9256 | return false; | |
9257 | ||
9258 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; | |
9259 | pipe_config->shared_dpll = NULL; | |
9260 | ||
9261 | ret = false; | |
9262 | tmp = I915_READ(PIPECONF(crtc->pipe)); | |
9263 | if (!(tmp & PIPECONF_ENABLE)) | |
9264 | goto out; | |
9265 | ||
9266 | switch (tmp & PIPECONF_BPC_MASK) { | |
9267 | case PIPECONF_6BPC: | |
9268 | pipe_config->pipe_bpp = 18; | |
9269 | break; | |
9270 | case PIPECONF_8BPC: | |
9271 | pipe_config->pipe_bpp = 24; | |
9272 | break; | |
9273 | case PIPECONF_10BPC: | |
9274 | pipe_config->pipe_bpp = 30; | |
9275 | break; | |
9276 | case PIPECONF_12BPC: | |
9277 | pipe_config->pipe_bpp = 36; | |
9278 | break; | |
9279 | default: | |
9280 | break; | |
9281 | } | |
9282 | ||
9283 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) | |
9284 | pipe_config->limited_color_range = true; | |
9285 | ||
9286 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { | |
9287 | struct intel_shared_dpll *pll; | |
9288 | enum intel_dpll_id pll_id; | |
9289 | ||
9290 | pipe_config->has_pch_encoder = true; | |
9291 | ||
9292 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); | |
9293 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9294 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9295 | ||
9296 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9297 | ||
9298 | if (HAS_PCH_IBX(dev_priv)) { | |
9299 | pll_id = (enum intel_dpll_id) crtc->pipe; | |
9300 | } else { | |
9301 | tmp = I915_READ(PCH_DPLL_SEL); | |
9302 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
9303 | pll_id = DPLL_ID_PCH_PLL_B; | |
9304 | else | |
9305 | pll_id= DPLL_ID_PCH_PLL_A; | |
9306 | } | |
9307 | ||
9308 | pipe_config->shared_dpll = | |
9309 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
9310 | pll = pipe_config->shared_dpll; | |
9311 | ||
9312 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, | |
9313 | &pipe_config->dpll_hw_state)); | |
9314 | ||
9315 | tmp = pipe_config->dpll_hw_state.dpll; | |
9316 | pipe_config->pixel_multiplier = | |
9317 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9318 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
9319 | ||
9320 | ironlake_pch_clock_get(crtc, pipe_config); | |
9321 | } else { | |
9322 | pipe_config->pixel_multiplier = 1; | |
9323 | } | |
9324 | ||
9325 | intel_get_pipe_timings(crtc, pipe_config); | |
9326 | intel_get_pipe_src_size(crtc, pipe_config); | |
9327 | ||
9328 | ironlake_get_pfit_config(crtc, pipe_config); | |
9329 | ||
9330 | ret = true; | |
9331 | ||
9332 | out: | |
9333 | intel_display_power_put(dev_priv, power_domain); | |
9334 | ||
9335 | return ret; | |
9336 | } | |
9337 | ||
9338 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) | |
9339 | { | |
9340 | struct drm_device *dev = dev_priv->dev; | |
9341 | struct intel_crtc *crtc; | |
9342 | ||
9343 | for_each_intel_crtc(dev, crtc) | |
9344 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", | |
9345 | pipe_name(crtc->pipe)); | |
9346 | ||
9347 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); | |
9348 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
9349 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
9350 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
9351 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
9352 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
9353 | "CPU PWM1 enabled\n"); | |
9354 | if (IS_HASWELL(dev)) | |
9355 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, | |
9356 | "CPU PWM2 enabled\n"); | |
9357 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, | |
9358 | "PCH PWM1 enabled\n"); | |
9359 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
9360 | "Utility pin enabled\n"); | |
9361 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); | |
9362 | ||
9363 | /* | |
9364 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9365 | * interrupts remain enabled. We used to check for that, but since it's | |
9366 | * gen-specific and since we only disable LCPLL after we fully disable | |
9367 | * the interrupts, the check below should be enough. | |
9368 | */ | |
9369 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); | |
9370 | } | |
9371 | ||
9372 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) | |
9373 | { | |
9374 | struct drm_device *dev = dev_priv->dev; | |
9375 | ||
9376 | if (IS_HASWELL(dev)) | |
9377 | return I915_READ(D_COMP_HSW); | |
9378 | else | |
9379 | return I915_READ(D_COMP_BDW); | |
9380 | } | |
9381 | ||
9382 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) | |
9383 | { | |
9384 | struct drm_device *dev = dev_priv->dev; | |
9385 | ||
9386 | if (IS_HASWELL(dev)) { | |
9387 | mutex_lock(&dev_priv->rps.hw_lock); | |
9388 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9389 | val)) | |
9390 | DRM_ERROR("Failed to write to D_COMP\n"); | |
9391 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9392 | } else { | |
9393 | I915_WRITE(D_COMP_BDW, val); | |
9394 | POSTING_READ(D_COMP_BDW); | |
9395 | } | |
9396 | } | |
9397 | ||
9398 | /* | |
9399 | * This function implements pieces of two sequences from BSpec: | |
9400 | * - Sequence for display software to disable LCPLL | |
9401 | * - Sequence for display software to allow package C8+ | |
9402 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9403 | * register. Callers should take care of disabling all the display engine | |
9404 | * functions, doing the mode unset, fixing interrupts, etc. | |
9405 | */ | |
9406 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, | |
9407 | bool switch_to_fclk, bool allow_power_down) | |
9408 | { | |
9409 | uint32_t val; | |
9410 | ||
9411 | assert_can_disable_lcpll(dev_priv); | |
9412 | ||
9413 | val = I915_READ(LCPLL_CTL); | |
9414 | ||
9415 | if (switch_to_fclk) { | |
9416 | val |= LCPLL_CD_SOURCE_FCLK; | |
9417 | I915_WRITE(LCPLL_CTL, val); | |
9418 | ||
9419 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9420 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9421 | DRM_ERROR("Switching to FCLK failed\n"); | |
9422 | ||
9423 | val = I915_READ(LCPLL_CTL); | |
9424 | } | |
9425 | ||
9426 | val |= LCPLL_PLL_DISABLE; | |
9427 | I915_WRITE(LCPLL_CTL, val); | |
9428 | POSTING_READ(LCPLL_CTL); | |
9429 | ||
9430 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9431 | DRM_ERROR("LCPLL still locked\n"); | |
9432 | ||
9433 | val = hsw_read_dcomp(dev_priv); | |
9434 | val |= D_COMP_COMP_DISABLE; | |
9435 | hsw_write_dcomp(dev_priv, val); | |
9436 | ndelay(100); | |
9437 | ||
9438 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, | |
9439 | 1)) | |
9440 | DRM_ERROR("D_COMP RCOMP still in progress\n"); | |
9441 | ||
9442 | if (allow_power_down) { | |
9443 | val = I915_READ(LCPLL_CTL); | |
9444 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9445 | I915_WRITE(LCPLL_CTL, val); | |
9446 | POSTING_READ(LCPLL_CTL); | |
9447 | } | |
9448 | } | |
9449 | ||
9450 | /* | |
9451 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9452 | * source. | |
9453 | */ | |
9454 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) | |
9455 | { | |
9456 | uint32_t val; | |
9457 | ||
9458 | val = I915_READ(LCPLL_CTL); | |
9459 | ||
9460 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9461 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9462 | return; | |
9463 | ||
9464 | /* | |
9465 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9466 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
9467 | */ | |
9468 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
9469 | ||
9470 | if (val & LCPLL_POWER_DOWN_ALLOW) { | |
9471 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9472 | I915_WRITE(LCPLL_CTL, val); | |
9473 | POSTING_READ(LCPLL_CTL); | |
9474 | } | |
9475 | ||
9476 | val = hsw_read_dcomp(dev_priv); | |
9477 | val |= D_COMP_COMP_FORCE; | |
9478 | val &= ~D_COMP_COMP_DISABLE; | |
9479 | hsw_write_dcomp(dev_priv, val); | |
9480 | ||
9481 | val = I915_READ(LCPLL_CTL); | |
9482 | val &= ~LCPLL_PLL_DISABLE; | |
9483 | I915_WRITE(LCPLL_CTL, val); | |
9484 | ||
9485 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9486 | DRM_ERROR("LCPLL not locked yet\n"); | |
9487 | ||
9488 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9489 | val = I915_READ(LCPLL_CTL); | |
9490 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9491 | I915_WRITE(LCPLL_CTL, val); | |
9492 | ||
9493 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9494 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9495 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9496 | } | |
9497 | ||
9498 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
9499 | intel_update_cdclk(dev_priv->dev); | |
9500 | } | |
9501 | ||
9502 | /* | |
9503 | * Package states C8 and deeper are really deep PC states that can only be | |
9504 | * reached when all the devices on the system allow it, so even if the graphics | |
9505 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9506 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9507 | * | |
9508 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9509 | * well is disabled and most interrupts are disabled, and these are also | |
9510 | * requirements for runtime PM. When these conditions are met, we manually do | |
9511 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9512 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9513 | * hang the machine. | |
9514 | * | |
9515 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9516 | * the state of some registers, so when we come back from PC8+ we need to | |
9517 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9518 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9519 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9520 | * because of the runtime PM support). | |
9521 | * | |
9522 | * For more, read "Display Sequences for Package C8" on the hardware | |
9523 | * documentation. | |
9524 | */ | |
9525 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) | |
9526 | { | |
9527 | struct drm_device *dev = dev_priv->dev; | |
9528 | uint32_t val; | |
9529 | ||
9530 | DRM_DEBUG_KMS("Enabling package C8+\n"); | |
9531 | ||
9532 | if (HAS_PCH_LPT_LP(dev)) { | |
9533 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
9534 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9535 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9536 | } | |
9537 | ||
9538 | lpt_disable_clkout_dp(dev); | |
9539 | hsw_disable_lcpll(dev_priv, true, true); | |
9540 | } | |
9541 | ||
9542 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) | |
9543 | { | |
9544 | struct drm_device *dev = dev_priv->dev; | |
9545 | uint32_t val; | |
9546 | ||
9547 | DRM_DEBUG_KMS("Disabling package C8+\n"); | |
9548 | ||
9549 | hsw_restore_lcpll(dev_priv); | |
9550 | lpt_init_pch_refclk(dev); | |
9551 | ||
9552 | if (HAS_PCH_LPT_LP(dev)) { | |
9553 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
9554 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9555 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9556 | } | |
9557 | } | |
9558 | ||
9559 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) | |
9560 | { | |
9561 | struct drm_device *dev = old_state->dev; | |
9562 | struct intel_atomic_state *old_intel_state = | |
9563 | to_intel_atomic_state(old_state); | |
9564 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
9565 | ||
9566 | broxton_set_cdclk(to_i915(dev), req_cdclk); | |
9567 | } | |
9568 | ||
9569 | /* compute the max rate for new configuration */ | |
9570 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) | |
9571 | { | |
9572 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
9573 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
9574 | struct drm_crtc *crtc; | |
9575 | struct drm_crtc_state *cstate; | |
9576 | struct intel_crtc_state *crtc_state; | |
9577 | unsigned max_pixel_rate = 0, i; | |
9578 | enum pipe pipe; | |
9579 | ||
9580 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, | |
9581 | sizeof(intel_state->min_pixclk)); | |
9582 | ||
9583 | for_each_crtc_in_state(state, crtc, cstate, i) { | |
9584 | int pixel_rate; | |
9585 | ||
9586 | crtc_state = to_intel_crtc_state(cstate); | |
9587 | if (!crtc_state->base.enable) { | |
9588 | intel_state->min_pixclk[i] = 0; | |
9589 | continue; | |
9590 | } | |
9591 | ||
9592 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); | |
9593 | ||
9594 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
9595 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) | |
9596 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); | |
9597 | ||
9598 | intel_state->min_pixclk[i] = pixel_rate; | |
9599 | } | |
9600 | ||
9601 | for_each_pipe(dev_priv, pipe) | |
9602 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
9603 | ||
9604 | return max_pixel_rate; | |
9605 | } | |
9606 | ||
9607 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9608 | { | |
9609 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9610 | uint32_t val, data; | |
9611 | int ret; | |
9612 | ||
9613 | if (WARN((I915_READ(LCPLL_CTL) & | |
9614 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9615 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9616 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9617 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9618 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9619 | return; | |
9620 | ||
9621 | mutex_lock(&dev_priv->rps.hw_lock); | |
9622 | ret = sandybridge_pcode_write(dev_priv, | |
9623 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9624 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9625 | if (ret) { | |
9626 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9627 | return; | |
9628 | } | |
9629 | ||
9630 | val = I915_READ(LCPLL_CTL); | |
9631 | val |= LCPLL_CD_SOURCE_FCLK; | |
9632 | I915_WRITE(LCPLL_CTL, val); | |
9633 | ||
9634 | if (wait_for_us(I915_READ(LCPLL_CTL) & | |
9635 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9636 | DRM_ERROR("Switching to FCLK failed\n"); | |
9637 | ||
9638 | val = I915_READ(LCPLL_CTL); | |
9639 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9640 | ||
9641 | switch (cdclk) { | |
9642 | case 450000: | |
9643 | val |= LCPLL_CLK_FREQ_450; | |
9644 | data = 0; | |
9645 | break; | |
9646 | case 540000: | |
9647 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9648 | data = 1; | |
9649 | break; | |
9650 | case 337500: | |
9651 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9652 | data = 2; | |
9653 | break; | |
9654 | case 675000: | |
9655 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9656 | data = 3; | |
9657 | break; | |
9658 | default: | |
9659 | WARN(1, "invalid cdclk frequency\n"); | |
9660 | return; | |
9661 | } | |
9662 | ||
9663 | I915_WRITE(LCPLL_CTL, val); | |
9664 | ||
9665 | val = I915_READ(LCPLL_CTL); | |
9666 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9667 | I915_WRITE(LCPLL_CTL, val); | |
9668 | ||
9669 | if (wait_for_us((I915_READ(LCPLL_CTL) & | |
9670 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9671 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9672 | ||
9673 | mutex_lock(&dev_priv->rps.hw_lock); | |
9674 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9675 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9676 | ||
9677 | I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); | |
9678 | ||
9679 | intel_update_cdclk(dev); | |
9680 | ||
9681 | WARN(cdclk != dev_priv->cdclk_freq, | |
9682 | "cdclk requested %d kHz but got %d kHz\n", | |
9683 | cdclk, dev_priv->cdclk_freq); | |
9684 | } | |
9685 | ||
9686 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) | |
9687 | { | |
9688 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
9689 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
9690 | int max_pixclk = ilk_max_pixel_rate(state); | |
9691 | int cdclk; | |
9692 | ||
9693 | /* | |
9694 | * FIXME should also account for plane ratio | |
9695 | * once 64bpp pixel formats are supported. | |
9696 | */ | |
9697 | if (max_pixclk > 540000) | |
9698 | cdclk = 675000; | |
9699 | else if (max_pixclk > 450000) | |
9700 | cdclk = 540000; | |
9701 | else if (max_pixclk > 337500) | |
9702 | cdclk = 450000; | |
9703 | else | |
9704 | cdclk = 337500; | |
9705 | ||
9706 | if (cdclk > dev_priv->max_cdclk_freq) { | |
9707 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
9708 | cdclk, dev_priv->max_cdclk_freq); | |
9709 | return -EINVAL; | |
9710 | } | |
9711 | ||
9712 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; | |
9713 | if (!intel_state->active_crtcs) | |
9714 | intel_state->dev_cdclk = 337500; | |
9715 | ||
9716 | return 0; | |
9717 | } | |
9718 | ||
9719 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) | |
9720 | { | |
9721 | struct drm_device *dev = old_state->dev; | |
9722 | struct intel_atomic_state *old_intel_state = | |
9723 | to_intel_atomic_state(old_state); | |
9724 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
9725 | ||
9726 | broadwell_set_cdclk(dev, req_cdclk); | |
9727 | } | |
9728 | ||
9729 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, | |
9730 | struct intel_crtc_state *crtc_state) | |
9731 | { | |
9732 | struct intel_encoder *intel_encoder = | |
9733 | intel_ddi_get_crtc_new_encoder(crtc_state); | |
9734 | ||
9735 | if (intel_encoder->type != INTEL_OUTPUT_DSI) { | |
9736 | if (!intel_ddi_pll_select(crtc, crtc_state)) | |
9737 | return -EINVAL; | |
9738 | } | |
9739 | ||
9740 | crtc->lowfreq_avail = false; | |
9741 | ||
9742 | return 0; | |
9743 | } | |
9744 | ||
9745 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, | |
9746 | enum port port, | |
9747 | struct intel_crtc_state *pipe_config) | |
9748 | { | |
9749 | enum intel_dpll_id id; | |
9750 | ||
9751 | switch (port) { | |
9752 | case PORT_A: | |
9753 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
9754 | id = DPLL_ID_SKL_DPLL0; | |
9755 | break; | |
9756 | case PORT_B: | |
9757 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
9758 | id = DPLL_ID_SKL_DPLL1; | |
9759 | break; | |
9760 | case PORT_C: | |
9761 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
9762 | id = DPLL_ID_SKL_DPLL2; | |
9763 | break; | |
9764 | default: | |
9765 | DRM_ERROR("Incorrect port type\n"); | |
9766 | return; | |
9767 | } | |
9768 | ||
9769 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
9770 | } | |
9771 | ||
9772 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, | |
9773 | enum port port, | |
9774 | struct intel_crtc_state *pipe_config) | |
9775 | { | |
9776 | enum intel_dpll_id id; | |
9777 | u32 temp; | |
9778 | ||
9779 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9780 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9781 | ||
9782 | switch (pipe_config->ddi_pll_sel) { | |
9783 | case SKL_DPLL0: | |
9784 | id = DPLL_ID_SKL_DPLL0; | |
9785 | break; | |
9786 | case SKL_DPLL1: | |
9787 | id = DPLL_ID_SKL_DPLL1; | |
9788 | break; | |
9789 | case SKL_DPLL2: | |
9790 | id = DPLL_ID_SKL_DPLL2; | |
9791 | break; | |
9792 | case SKL_DPLL3: | |
9793 | id = DPLL_ID_SKL_DPLL3; | |
9794 | break; | |
9795 | default: | |
9796 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
9797 | return; | |
9798 | } | |
9799 | ||
9800 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
9801 | } | |
9802 | ||
9803 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, | |
9804 | enum port port, | |
9805 | struct intel_crtc_state *pipe_config) | |
9806 | { | |
9807 | enum intel_dpll_id id; | |
9808 | ||
9809 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
9810 | ||
9811 | switch (pipe_config->ddi_pll_sel) { | |
9812 | case PORT_CLK_SEL_WRPLL1: | |
9813 | id = DPLL_ID_WRPLL1; | |
9814 | break; | |
9815 | case PORT_CLK_SEL_WRPLL2: | |
9816 | id = DPLL_ID_WRPLL2; | |
9817 | break; | |
9818 | case PORT_CLK_SEL_SPLL: | |
9819 | id = DPLL_ID_SPLL; | |
9820 | break; | |
9821 | case PORT_CLK_SEL_LCPLL_810: | |
9822 | id = DPLL_ID_LCPLL_810; | |
9823 | break; | |
9824 | case PORT_CLK_SEL_LCPLL_1350: | |
9825 | id = DPLL_ID_LCPLL_1350; | |
9826 | break; | |
9827 | case PORT_CLK_SEL_LCPLL_2700: | |
9828 | id = DPLL_ID_LCPLL_2700; | |
9829 | break; | |
9830 | default: | |
9831 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
9832 | /* fall through */ | |
9833 | case PORT_CLK_SEL_NONE: | |
9834 | return; | |
9835 | } | |
9836 | ||
9837 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
9838 | } | |
9839 | ||
9840 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, | |
9841 | struct intel_crtc_state *pipe_config, | |
9842 | unsigned long *power_domain_mask) | |
9843 | { | |
9844 | struct drm_device *dev = crtc->base.dev; | |
9845 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9846 | enum intel_display_power_domain power_domain; | |
9847 | u32 tmp; | |
9848 | ||
9849 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; | |
9850 | ||
9851 | /* | |
9852 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
9853 | * consistency and less surprising code; it's in always on power). | |
9854 | */ | |
9855 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
9856 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9857 | enum pipe trans_edp_pipe; | |
9858 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9859 | default: | |
9860 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9861 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9862 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9863 | trans_edp_pipe = PIPE_A; | |
9864 | break; | |
9865 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9866 | trans_edp_pipe = PIPE_B; | |
9867 | break; | |
9868 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9869 | trans_edp_pipe = PIPE_C; | |
9870 | break; | |
9871 | } | |
9872 | ||
9873 | if (trans_edp_pipe == crtc->pipe) | |
9874 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9875 | } | |
9876 | ||
9877 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
9878 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9879 | return false; | |
9880 | *power_domain_mask |= BIT(power_domain); | |
9881 | ||
9882 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
9883 | ||
9884 | return tmp & PIPECONF_ENABLE; | |
9885 | } | |
9886 | ||
9887 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, | |
9888 | struct intel_crtc_state *pipe_config, | |
9889 | unsigned long *power_domain_mask) | |
9890 | { | |
9891 | struct drm_device *dev = crtc->base.dev; | |
9892 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9893 | enum intel_display_power_domain power_domain; | |
9894 | enum port port; | |
9895 | enum transcoder cpu_transcoder; | |
9896 | u32 tmp; | |
9897 | ||
9898 | pipe_config->has_dsi_encoder = false; | |
9899 | ||
9900 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { | |
9901 | if (port == PORT_A) | |
9902 | cpu_transcoder = TRANSCODER_DSI_A; | |
9903 | else | |
9904 | cpu_transcoder = TRANSCODER_DSI_C; | |
9905 | ||
9906 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
9907 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9908 | continue; | |
9909 | *power_domain_mask |= BIT(power_domain); | |
9910 | ||
9911 | /* | |
9912 | * The PLL needs to be enabled with a valid divider | |
9913 | * configuration, otherwise accessing DSI registers will hang | |
9914 | * the machine. See BSpec North Display Engine | |
9915 | * registers/MIPI[BXT]. We can break out here early, since we | |
9916 | * need the same DSI PLL to be enabled for both DSI ports. | |
9917 | */ | |
9918 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
9919 | break; | |
9920 | ||
9921 | /* XXX: this works for video mode only */ | |
9922 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
9923 | if (!(tmp & DPI_ENABLE)) | |
9924 | continue; | |
9925 | ||
9926 | tmp = I915_READ(MIPI_CTRL(port)); | |
9927 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
9928 | continue; | |
9929 | ||
9930 | pipe_config->cpu_transcoder = cpu_transcoder; | |
9931 | pipe_config->has_dsi_encoder = true; | |
9932 | break; | |
9933 | } | |
9934 | ||
9935 | return pipe_config->has_dsi_encoder; | |
9936 | } | |
9937 | ||
9938 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, | |
9939 | struct intel_crtc_state *pipe_config) | |
9940 | { | |
9941 | struct drm_device *dev = crtc->base.dev; | |
9942 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9943 | struct intel_shared_dpll *pll; | |
9944 | enum port port; | |
9945 | uint32_t tmp; | |
9946 | ||
9947 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9948 | ||
9949 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9950 | ||
9951 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) | |
9952 | skylake_get_ddi_pll(dev_priv, port, pipe_config); | |
9953 | else if (IS_BROXTON(dev)) | |
9954 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
9955 | else | |
9956 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9957 | ||
9958 | pll = pipe_config->shared_dpll; | |
9959 | if (pll) { | |
9960 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, | |
9961 | &pipe_config->dpll_hw_state)); | |
9962 | } | |
9963 | ||
9964 | /* | |
9965 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9966 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9967 | * the PCH transcoder is on. | |
9968 | */ | |
9969 | if (INTEL_INFO(dev)->gen < 9 && | |
9970 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
9971 | pipe_config->has_pch_encoder = true; | |
9972 | ||
9973 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9974 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9975 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9976 | ||
9977 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9978 | } | |
9979 | } | |
9980 | ||
9981 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, | |
9982 | struct intel_crtc_state *pipe_config) | |
9983 | { | |
9984 | struct drm_device *dev = crtc->base.dev; | |
9985 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9986 | enum intel_display_power_domain power_domain; | |
9987 | unsigned long power_domain_mask; | |
9988 | bool active; | |
9989 | ||
9990 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); | |
9991 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9992 | return false; | |
9993 | power_domain_mask = BIT(power_domain); | |
9994 | ||
9995 | pipe_config->shared_dpll = NULL; | |
9996 | ||
9997 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); | |
9998 | ||
9999 | if (IS_BROXTON(dev_priv)) { | |
10000 | bxt_get_dsi_transcoder_state(crtc, pipe_config, | |
10001 | &power_domain_mask); | |
10002 | WARN_ON(active && pipe_config->has_dsi_encoder); | |
10003 | if (pipe_config->has_dsi_encoder) | |
10004 | active = true; | |
10005 | } | |
10006 | ||
10007 | if (!active) | |
10008 | goto out; | |
10009 | ||
10010 | if (!pipe_config->has_dsi_encoder) { | |
10011 | haswell_get_ddi_port_state(crtc, pipe_config); | |
10012 | intel_get_pipe_timings(crtc, pipe_config); | |
10013 | } | |
10014 | ||
10015 | intel_get_pipe_src_size(crtc, pipe_config); | |
10016 | ||
10017 | pipe_config->gamma_mode = | |
10018 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
10019 | ||
10020 | if (INTEL_INFO(dev)->gen >= 9) { | |
10021 | skl_init_scalers(dev, crtc, pipe_config); | |
10022 | } | |
10023 | ||
10024 | if (INTEL_INFO(dev)->gen >= 9) { | |
10025 | pipe_config->scaler_state.scaler_id = -1; | |
10026 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
10027 | } | |
10028 | ||
10029 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); | |
10030 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
10031 | power_domain_mask |= BIT(power_domain); | |
10032 | if (INTEL_INFO(dev)->gen >= 9) | |
10033 | skylake_get_pfit_config(crtc, pipe_config); | |
10034 | else | |
10035 | ironlake_get_pfit_config(crtc, pipe_config); | |
10036 | } | |
10037 | ||
10038 | if (IS_HASWELL(dev)) | |
10039 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
10040 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
10041 | ||
10042 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && | |
10043 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
10044 | pipe_config->pixel_multiplier = | |
10045 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10046 | } else { | |
10047 | pipe_config->pixel_multiplier = 1; | |
10048 | } | |
10049 | ||
10050 | out: | |
10051 | for_each_power_domain(power_domain, power_domain_mask) | |
10052 | intel_display_power_put(dev_priv, power_domain); | |
10053 | ||
10054 | return active; | |
10055 | } | |
10056 | ||
10057 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, | |
10058 | const struct intel_plane_state *plane_state) | |
10059 | { | |
10060 | struct drm_device *dev = crtc->dev; | |
10061 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10062 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10063 | uint32_t cntl = 0, size = 0; | |
10064 | ||
10065 | if (plane_state && plane_state->visible) { | |
10066 | unsigned int width = plane_state->base.crtc_w; | |
10067 | unsigned int height = plane_state->base.crtc_h; | |
10068 | unsigned int stride = roundup_pow_of_two(width) * 4; | |
10069 | ||
10070 | switch (stride) { | |
10071 | default: | |
10072 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10073 | width, stride); | |
10074 | stride = 256; | |
10075 | /* fallthrough */ | |
10076 | case 256: | |
10077 | case 512: | |
10078 | case 1024: | |
10079 | case 2048: | |
10080 | break; | |
10081 | } | |
10082 | ||
10083 | cntl |= CURSOR_ENABLE | | |
10084 | CURSOR_GAMMA_ENABLE | | |
10085 | CURSOR_FORMAT_ARGB | | |
10086 | CURSOR_STRIDE(stride); | |
10087 | ||
10088 | size = (height << 12) | width; | |
10089 | } | |
10090 | ||
10091 | if (intel_crtc->cursor_cntl != 0 && | |
10092 | (intel_crtc->cursor_base != base || | |
10093 | intel_crtc->cursor_size != size || | |
10094 | intel_crtc->cursor_cntl != cntl)) { | |
10095 | /* On these chipsets we can only modify the base/size/stride | |
10096 | * whilst the cursor is disabled. | |
10097 | */ | |
10098 | I915_WRITE(CURCNTR(PIPE_A), 0); | |
10099 | POSTING_READ(CURCNTR(PIPE_A)); | |
10100 | intel_crtc->cursor_cntl = 0; | |
10101 | } | |
10102 | ||
10103 | if (intel_crtc->cursor_base != base) { | |
10104 | I915_WRITE(CURBASE(PIPE_A), base); | |
10105 | intel_crtc->cursor_base = base; | |
10106 | } | |
10107 | ||
10108 | if (intel_crtc->cursor_size != size) { | |
10109 | I915_WRITE(CURSIZE, size); | |
10110 | intel_crtc->cursor_size = size; | |
10111 | } | |
10112 | ||
10113 | if (intel_crtc->cursor_cntl != cntl) { | |
10114 | I915_WRITE(CURCNTR(PIPE_A), cntl); | |
10115 | POSTING_READ(CURCNTR(PIPE_A)); | |
10116 | intel_crtc->cursor_cntl = cntl; | |
10117 | } | |
10118 | } | |
10119 | ||
10120 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, | |
10121 | const struct intel_plane_state *plane_state) | |
10122 | { | |
10123 | struct drm_device *dev = crtc->dev; | |
10124 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10125 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10126 | int pipe = intel_crtc->pipe; | |
10127 | uint32_t cntl = 0; | |
10128 | ||
10129 | if (plane_state && plane_state->visible) { | |
10130 | cntl = MCURSOR_GAMMA_ENABLE; | |
10131 | switch (plane_state->base.crtc_w) { | |
10132 | case 64: | |
10133 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10134 | break; | |
10135 | case 128: | |
10136 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10137 | break; | |
10138 | case 256: | |
10139 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10140 | break; | |
10141 | default: | |
10142 | MISSING_CASE(plane_state->base.crtc_w); | |
10143 | return; | |
10144 | } | |
10145 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
10146 | ||
10147 | if (HAS_DDI(dev)) | |
10148 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
10149 | ||
10150 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) | |
10151 | cntl |= CURSOR_ROTATE_180; | |
10152 | } | |
10153 | ||
10154 | if (intel_crtc->cursor_cntl != cntl) { | |
10155 | I915_WRITE(CURCNTR(pipe), cntl); | |
10156 | POSTING_READ(CURCNTR(pipe)); | |
10157 | intel_crtc->cursor_cntl = cntl; | |
10158 | } | |
10159 | ||
10160 | /* and commit changes on next vblank */ | |
10161 | I915_WRITE(CURBASE(pipe), base); | |
10162 | POSTING_READ(CURBASE(pipe)); | |
10163 | ||
10164 | intel_crtc->cursor_base = base; | |
10165 | } | |
10166 | ||
10167 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ | |
10168 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, | |
10169 | const struct intel_plane_state *plane_state) | |
10170 | { | |
10171 | struct drm_device *dev = crtc->dev; | |
10172 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10173 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10174 | int pipe = intel_crtc->pipe; | |
10175 | u32 base = intel_crtc->cursor_addr; | |
10176 | u32 pos = 0; | |
10177 | ||
10178 | if (plane_state) { | |
10179 | int x = plane_state->base.crtc_x; | |
10180 | int y = plane_state->base.crtc_y; | |
10181 | ||
10182 | if (x < 0) { | |
10183 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10184 | x = -x; | |
10185 | } | |
10186 | pos |= x << CURSOR_X_SHIFT; | |
10187 | ||
10188 | if (y < 0) { | |
10189 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10190 | y = -y; | |
10191 | } | |
10192 | pos |= y << CURSOR_Y_SHIFT; | |
10193 | ||
10194 | /* ILK+ do this automagically */ | |
10195 | if (HAS_GMCH_DISPLAY(dev) && | |
10196 | plane_state->base.rotation == BIT(DRM_ROTATE_180)) { | |
10197 | base += (plane_state->base.crtc_h * | |
10198 | plane_state->base.crtc_w - 1) * 4; | |
10199 | } | |
10200 | } | |
10201 | ||
10202 | I915_WRITE(CURPOS(pipe), pos); | |
10203 | ||
10204 | if (IS_845G(dev) || IS_I865G(dev)) | |
10205 | i845_update_cursor(crtc, base, plane_state); | |
10206 | else | |
10207 | i9xx_update_cursor(crtc, base, plane_state); | |
10208 | } | |
10209 | ||
10210 | static bool cursor_size_ok(struct drm_device *dev, | |
10211 | uint32_t width, uint32_t height) | |
10212 | { | |
10213 | if (width == 0 || height == 0) | |
10214 | return false; | |
10215 | ||
10216 | /* | |
10217 | * 845g/865g are special in that they are only limited by | |
10218 | * the width of their cursors, the height is arbitrary up to | |
10219 | * the precision of the register. Everything else requires | |
10220 | * square cursors, limited to a few power-of-two sizes. | |
10221 | */ | |
10222 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10223 | if ((width & 63) != 0) | |
10224 | return false; | |
10225 | ||
10226 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10227 | return false; | |
10228 | ||
10229 | if (height > 1023) | |
10230 | return false; | |
10231 | } else { | |
10232 | switch (width | height) { | |
10233 | case 256: | |
10234 | case 128: | |
10235 | if (IS_GEN2(dev)) | |
10236 | return false; | |
10237 | case 64: | |
10238 | break; | |
10239 | default: | |
10240 | return false; | |
10241 | } | |
10242 | } | |
10243 | ||
10244 | return true; | |
10245 | } | |
10246 | ||
10247 | /* VESA 640x480x72Hz mode to set on the pipe */ | |
10248 | static struct drm_display_mode load_detect_mode = { | |
10249 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10250 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10251 | }; | |
10252 | ||
10253 | struct drm_framebuffer * | |
10254 | __intel_framebuffer_create(struct drm_device *dev, | |
10255 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10256 | struct drm_i915_gem_object *obj) | |
10257 | { | |
10258 | struct intel_framebuffer *intel_fb; | |
10259 | int ret; | |
10260 | ||
10261 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
10262 | if (!intel_fb) | |
10263 | return ERR_PTR(-ENOMEM); | |
10264 | ||
10265 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
10266 | if (ret) | |
10267 | goto err; | |
10268 | ||
10269 | return &intel_fb->base; | |
10270 | ||
10271 | err: | |
10272 | kfree(intel_fb); | |
10273 | return ERR_PTR(ret); | |
10274 | } | |
10275 | ||
10276 | static struct drm_framebuffer * | |
10277 | intel_framebuffer_create(struct drm_device *dev, | |
10278 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10279 | struct drm_i915_gem_object *obj) | |
10280 | { | |
10281 | struct drm_framebuffer *fb; | |
10282 | int ret; | |
10283 | ||
10284 | ret = i915_mutex_lock_interruptible(dev); | |
10285 | if (ret) | |
10286 | return ERR_PTR(ret); | |
10287 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10288 | mutex_unlock(&dev->struct_mutex); | |
10289 | ||
10290 | return fb; | |
10291 | } | |
10292 | ||
10293 | static u32 | |
10294 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10295 | { | |
10296 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10297 | return ALIGN(pitch, 64); | |
10298 | } | |
10299 | ||
10300 | static u32 | |
10301 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10302 | { | |
10303 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
10304 | return PAGE_ALIGN(pitch * mode->vdisplay); | |
10305 | } | |
10306 | ||
10307 | static struct drm_framebuffer * | |
10308 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10309 | struct drm_display_mode *mode, | |
10310 | int depth, int bpp) | |
10311 | { | |
10312 | struct drm_framebuffer *fb; | |
10313 | struct drm_i915_gem_object *obj; | |
10314 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
10315 | ||
10316 | obj = i915_gem_object_create(dev, | |
10317 | intel_framebuffer_size_for_mode(mode, bpp)); | |
10318 | if (IS_ERR(obj)) | |
10319 | return ERR_CAST(obj); | |
10320 | ||
10321 | mode_cmd.width = mode->hdisplay; | |
10322 | mode_cmd.height = mode->vdisplay; | |
10323 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, | |
10324 | bpp); | |
10325 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); | |
10326 | ||
10327 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); | |
10328 | if (IS_ERR(fb)) | |
10329 | drm_gem_object_unreference_unlocked(&obj->base); | |
10330 | ||
10331 | return fb; | |
10332 | } | |
10333 | ||
10334 | static struct drm_framebuffer * | |
10335 | mode_fits_in_fbdev(struct drm_device *dev, | |
10336 | struct drm_display_mode *mode) | |
10337 | { | |
10338 | #ifdef CONFIG_DRM_FBDEV_EMULATION | |
10339 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10340 | struct drm_i915_gem_object *obj; | |
10341 | struct drm_framebuffer *fb; | |
10342 | ||
10343 | if (!dev_priv->fbdev) | |
10344 | return NULL; | |
10345 | ||
10346 | if (!dev_priv->fbdev->fb) | |
10347 | return NULL; | |
10348 | ||
10349 | obj = dev_priv->fbdev->fb->obj; | |
10350 | BUG_ON(!obj); | |
10351 | ||
10352 | fb = &dev_priv->fbdev->fb->base; | |
10353 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, | |
10354 | fb->bits_per_pixel)) | |
10355 | return NULL; | |
10356 | ||
10357 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) | |
10358 | return NULL; | |
10359 | ||
10360 | drm_framebuffer_reference(fb); | |
10361 | return fb; | |
10362 | #else | |
10363 | return NULL; | |
10364 | #endif | |
10365 | } | |
10366 | ||
10367 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, | |
10368 | struct drm_crtc *crtc, | |
10369 | struct drm_display_mode *mode, | |
10370 | struct drm_framebuffer *fb, | |
10371 | int x, int y) | |
10372 | { | |
10373 | struct drm_plane_state *plane_state; | |
10374 | int hdisplay, vdisplay; | |
10375 | int ret; | |
10376 | ||
10377 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10378 | if (IS_ERR(plane_state)) | |
10379 | return PTR_ERR(plane_state); | |
10380 | ||
10381 | if (mode) | |
10382 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10383 | else | |
10384 | hdisplay = vdisplay = 0; | |
10385 | ||
10386 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10387 | if (ret) | |
10388 | return ret; | |
10389 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10390 | plane_state->crtc_x = 0; | |
10391 | plane_state->crtc_y = 0; | |
10392 | plane_state->crtc_w = hdisplay; | |
10393 | plane_state->crtc_h = vdisplay; | |
10394 | plane_state->src_x = x << 16; | |
10395 | plane_state->src_y = y << 16; | |
10396 | plane_state->src_w = hdisplay << 16; | |
10397 | plane_state->src_h = vdisplay << 16; | |
10398 | ||
10399 | return 0; | |
10400 | } | |
10401 | ||
10402 | bool intel_get_load_detect_pipe(struct drm_connector *connector, | |
10403 | struct drm_display_mode *mode, | |
10404 | struct intel_load_detect_pipe *old, | |
10405 | struct drm_modeset_acquire_ctx *ctx) | |
10406 | { | |
10407 | struct intel_crtc *intel_crtc; | |
10408 | struct intel_encoder *intel_encoder = | |
10409 | intel_attached_encoder(connector); | |
10410 | struct drm_crtc *possible_crtc; | |
10411 | struct drm_encoder *encoder = &intel_encoder->base; | |
10412 | struct drm_crtc *crtc = NULL; | |
10413 | struct drm_device *dev = encoder->dev; | |
10414 | struct drm_framebuffer *fb; | |
10415 | struct drm_mode_config *config = &dev->mode_config; | |
10416 | struct drm_atomic_state *state = NULL, *restore_state = NULL; | |
10417 | struct drm_connector_state *connector_state; | |
10418 | struct intel_crtc_state *crtc_state; | |
10419 | int ret, i = -1; | |
10420 | ||
10421 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
10422 | connector->base.id, connector->name, | |
10423 | encoder->base.id, encoder->name); | |
10424 | ||
10425 | old->restore_state = NULL; | |
10426 | ||
10427 | retry: | |
10428 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10429 | if (ret) | |
10430 | goto fail; | |
10431 | ||
10432 | /* | |
10433 | * Algorithm gets a little messy: | |
10434 | * | |
10435 | * - if the connector already has an assigned crtc, use it (but make | |
10436 | * sure it's on first) | |
10437 | * | |
10438 | * - try to find the first unused crtc that can drive this connector, | |
10439 | * and use that if we find one | |
10440 | */ | |
10441 | ||
10442 | /* See if we already have a CRTC for this connector */ | |
10443 | if (connector->state->crtc) { | |
10444 | crtc = connector->state->crtc; | |
10445 | ||
10446 | ret = drm_modeset_lock(&crtc->mutex, ctx); | |
10447 | if (ret) | |
10448 | goto fail; | |
10449 | ||
10450 | /* Make sure the crtc and connector are running */ | |
10451 | goto found; | |
10452 | } | |
10453 | ||
10454 | /* Find an unused one (if possible) */ | |
10455 | for_each_crtc(dev, possible_crtc) { | |
10456 | i++; | |
10457 | if (!(encoder->possible_crtcs & (1 << i))) | |
10458 | continue; | |
10459 | ||
10460 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
10461 | if (ret) | |
10462 | goto fail; | |
10463 | ||
10464 | if (possible_crtc->state->enable) { | |
10465 | drm_modeset_unlock(&possible_crtc->mutex); | |
10466 | continue; | |
10467 | } | |
10468 | ||
10469 | crtc = possible_crtc; | |
10470 | break; | |
10471 | } | |
10472 | ||
10473 | /* | |
10474 | * If we didn't find an unused CRTC, don't use any. | |
10475 | */ | |
10476 | if (!crtc) { | |
10477 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); | |
10478 | goto fail; | |
10479 | } | |
10480 | ||
10481 | found: | |
10482 | intel_crtc = to_intel_crtc(crtc); | |
10483 | ||
10484 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
10485 | if (ret) | |
10486 | goto fail; | |
10487 | ||
10488 | state = drm_atomic_state_alloc(dev); | |
10489 | restore_state = drm_atomic_state_alloc(dev); | |
10490 | if (!state || !restore_state) { | |
10491 | ret = -ENOMEM; | |
10492 | goto fail; | |
10493 | } | |
10494 | ||
10495 | state->acquire_ctx = ctx; | |
10496 | restore_state->acquire_ctx = ctx; | |
10497 | ||
10498 | connector_state = drm_atomic_get_connector_state(state, connector); | |
10499 | if (IS_ERR(connector_state)) { | |
10500 | ret = PTR_ERR(connector_state); | |
10501 | goto fail; | |
10502 | } | |
10503 | ||
10504 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); | |
10505 | if (ret) | |
10506 | goto fail; | |
10507 | ||
10508 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
10509 | if (IS_ERR(crtc_state)) { | |
10510 | ret = PTR_ERR(crtc_state); | |
10511 | goto fail; | |
10512 | } | |
10513 | ||
10514 | crtc_state->base.active = crtc_state->base.enable = true; | |
10515 | ||
10516 | if (!mode) | |
10517 | mode = &load_detect_mode; | |
10518 | ||
10519 | /* We need a framebuffer large enough to accommodate all accesses | |
10520 | * that the plane may generate whilst we perform load detection. | |
10521 | * We can not rely on the fbcon either being present (we get called | |
10522 | * during its initialisation to detect all boot displays, or it may | |
10523 | * not even exist) or that it is large enough to satisfy the | |
10524 | * requested mode. | |
10525 | */ | |
10526 | fb = mode_fits_in_fbdev(dev, mode); | |
10527 | if (fb == NULL) { | |
10528 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); | |
10529 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); | |
10530 | } else | |
10531 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
10532 | if (IS_ERR(fb)) { | |
10533 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); | |
10534 | goto fail; | |
10535 | } | |
10536 | ||
10537 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); | |
10538 | if (ret) | |
10539 | goto fail; | |
10540 | ||
10541 | drm_framebuffer_unreference(fb); | |
10542 | ||
10543 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
10544 | if (ret) | |
10545 | goto fail; | |
10546 | ||
10547 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
10548 | if (!ret) | |
10549 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
10550 | if (!ret) | |
10551 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
10552 | if (ret) { | |
10553 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
10554 | goto fail; | |
10555 | } | |
10556 | ||
10557 | ret = drm_atomic_commit(state); | |
10558 | if (ret) { | |
10559 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); | |
10560 | goto fail; | |
10561 | } | |
10562 | ||
10563 | old->restore_state = restore_state; | |
10564 | ||
10565 | /* let the connector get through one full cycle before testing */ | |
10566 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
10567 | return true; | |
10568 | ||
10569 | fail: | |
10570 | drm_atomic_state_free(state); | |
10571 | drm_atomic_state_free(restore_state); | |
10572 | restore_state = state = NULL; | |
10573 | ||
10574 | if (ret == -EDEADLK) { | |
10575 | drm_modeset_backoff(ctx); | |
10576 | goto retry; | |
10577 | } | |
10578 | ||
10579 | return false; | |
10580 | } | |
10581 | ||
10582 | void intel_release_load_detect_pipe(struct drm_connector *connector, | |
10583 | struct intel_load_detect_pipe *old, | |
10584 | struct drm_modeset_acquire_ctx *ctx) | |
10585 | { | |
10586 | struct intel_encoder *intel_encoder = | |
10587 | intel_attached_encoder(connector); | |
10588 | struct drm_encoder *encoder = &intel_encoder->base; | |
10589 | struct drm_atomic_state *state = old->restore_state; | |
10590 | int ret; | |
10591 | ||
10592 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
10593 | connector->base.id, connector->name, | |
10594 | encoder->base.id, encoder->name); | |
10595 | ||
10596 | if (!state) | |
10597 | return; | |
10598 | ||
10599 | ret = drm_atomic_commit(state); | |
10600 | if (ret) { | |
10601 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); | |
10602 | drm_atomic_state_free(state); | |
10603 | } | |
10604 | } | |
10605 | ||
10606 | static int i9xx_pll_refclk(struct drm_device *dev, | |
10607 | const struct intel_crtc_state *pipe_config) | |
10608 | { | |
10609 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10610 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10611 | ||
10612 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
10613 | return dev_priv->vbt.lvds_ssc_freq; | |
10614 | else if (HAS_PCH_SPLIT(dev)) | |
10615 | return 120000; | |
10616 | else if (!IS_GEN2(dev)) | |
10617 | return 96000; | |
10618 | else | |
10619 | return 48000; | |
10620 | } | |
10621 | ||
10622 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
10623 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, | |
10624 | struct intel_crtc_state *pipe_config) | |
10625 | { | |
10626 | struct drm_device *dev = crtc->base.dev; | |
10627 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10628 | int pipe = pipe_config->cpu_transcoder; | |
10629 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10630 | u32 fp; | |
10631 | intel_clock_t clock; | |
10632 | int port_clock; | |
10633 | int refclk = i9xx_pll_refclk(dev, pipe_config); | |
10634 | ||
10635 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
10636 | fp = pipe_config->dpll_hw_state.fp0; | |
10637 | else | |
10638 | fp = pipe_config->dpll_hw_state.fp1; | |
10639 | ||
10640 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
10641 | if (IS_PINEVIEW(dev)) { | |
10642 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10643 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10644 | } else { | |
10645 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10646 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10647 | } | |
10648 | ||
10649 | if (!IS_GEN2(dev)) { | |
10650 | if (IS_PINEVIEW(dev)) | |
10651 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10652 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
10653 | else | |
10654 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
10655 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
10656 | ||
10657 | switch (dpll & DPLL_MODE_MASK) { | |
10658 | case DPLLB_MODE_DAC_SERIAL: | |
10659 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10660 | 5 : 10; | |
10661 | break; | |
10662 | case DPLLB_MODE_LVDS: | |
10663 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10664 | 7 : 14; | |
10665 | break; | |
10666 | default: | |
10667 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " | |
10668 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); | |
10669 | return; | |
10670 | } | |
10671 | ||
10672 | if (IS_PINEVIEW(dev)) | |
10673 | port_clock = pnv_calc_dpll_params(refclk, &clock); | |
10674 | else | |
10675 | port_clock = i9xx_calc_dpll_params(refclk, &clock); | |
10676 | } else { | |
10677 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); | |
10678 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); | |
10679 | ||
10680 | if (is_lvds) { | |
10681 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10682 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
10683 | ||
10684 | if (lvds & LVDS_CLKB_POWER_UP) | |
10685 | clock.p2 = 7; | |
10686 | else | |
10687 | clock.p2 = 14; | |
10688 | } else { | |
10689 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10690 | clock.p1 = 2; | |
10691 | else { | |
10692 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10693 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10694 | } | |
10695 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10696 | clock.p2 = 4; | |
10697 | else | |
10698 | clock.p2 = 2; | |
10699 | } | |
10700 | ||
10701 | port_clock = i9xx_calc_dpll_params(refclk, &clock); | |
10702 | } | |
10703 | ||
10704 | /* | |
10705 | * This value includes pixel_multiplier. We will use | |
10706 | * port_clock to compute adjusted_mode.crtc_clock in the | |
10707 | * encoder's get_config() function. | |
10708 | */ | |
10709 | pipe_config->port_clock = port_clock; | |
10710 | } | |
10711 | ||
10712 | int intel_dotclock_calculate(int link_freq, | |
10713 | const struct intel_link_m_n *m_n) | |
10714 | { | |
10715 | /* | |
10716 | * The calculation for the data clock is: | |
10717 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp | |
10718 | * But we want to avoid losing precison if possible, so: | |
10719 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) | |
10720 | * | |
10721 | * and the link clock is simpler: | |
10722 | * link_clock = (m * link_clock) / n | |
10723 | */ | |
10724 | ||
10725 | if (!m_n->link_n) | |
10726 | return 0; | |
10727 | ||
10728 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); | |
10729 | } | |
10730 | ||
10731 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, | |
10732 | struct intel_crtc_state *pipe_config) | |
10733 | { | |
10734 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
10735 | ||
10736 | /* read out port_clock from the DPLL */ | |
10737 | i9xx_crtc_clock_get(crtc, pipe_config); | |
10738 | ||
10739 | /* | |
10740 | * In case there is an active pipe without active ports, | |
10741 | * we may need some idea for the dotclock anyway. | |
10742 | * Calculate one based on the FDI configuration. | |
10743 | */ | |
10744 | pipe_config->base.adjusted_mode.crtc_clock = | |
10745 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), | |
10746 | &pipe_config->fdi_m_n); | |
10747 | } | |
10748 | ||
10749 | /** Returns the currently programmed mode of the given pipe. */ | |
10750 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10751 | struct drm_crtc *crtc) | |
10752 | { | |
10753 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10754 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10755 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; | |
10756 | struct drm_display_mode *mode; | |
10757 | struct intel_crtc_state *pipe_config; | |
10758 | int htot = I915_READ(HTOTAL(cpu_transcoder)); | |
10759 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10760 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10761 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
10762 | enum pipe pipe = intel_crtc->pipe; | |
10763 | ||
10764 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10765 | if (!mode) | |
10766 | return NULL; | |
10767 | ||
10768 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
10769 | if (!pipe_config) { | |
10770 | kfree(mode); | |
10771 | return NULL; | |
10772 | } | |
10773 | ||
10774 | /* | |
10775 | * Construct a pipe_config sufficient for getting the clock info | |
10776 | * back out of crtc_clock_get. | |
10777 | * | |
10778 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10779 | * to use a real value here instead. | |
10780 | */ | |
10781 | pipe_config->cpu_transcoder = (enum transcoder) pipe; | |
10782 | pipe_config->pixel_multiplier = 1; | |
10783 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
10784 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10785 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
10786 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
10787 | ||
10788 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
10789 | mode->hdisplay = (htot & 0xffff) + 1; | |
10790 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10791 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10792 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10793 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10794 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10795 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10796 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10797 | ||
10798 | drm_mode_set_name(mode); | |
10799 | ||
10800 | kfree(pipe_config); | |
10801 | ||
10802 | return mode; | |
10803 | } | |
10804 | ||
10805 | void intel_mark_busy(struct drm_i915_private *dev_priv) | |
10806 | { | |
10807 | if (dev_priv->mm.busy) | |
10808 | return; | |
10809 | ||
10810 | intel_runtime_pm_get(dev_priv); | |
10811 | i915_update_gfx_val(dev_priv); | |
10812 | if (INTEL_GEN(dev_priv) >= 6) | |
10813 | gen6_rps_busy(dev_priv); | |
10814 | dev_priv->mm.busy = true; | |
10815 | } | |
10816 | ||
10817 | void intel_mark_idle(struct drm_i915_private *dev_priv) | |
10818 | { | |
10819 | if (!dev_priv->mm.busy) | |
10820 | return; | |
10821 | ||
10822 | dev_priv->mm.busy = false; | |
10823 | ||
10824 | if (INTEL_GEN(dev_priv) >= 6) | |
10825 | gen6_rps_idle(dev_priv); | |
10826 | ||
10827 | intel_runtime_pm_put(dev_priv); | |
10828 | } | |
10829 | ||
10830 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
10831 | { | |
10832 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10833 | struct drm_device *dev = crtc->dev; | |
10834 | struct intel_unpin_work *work; | |
10835 | ||
10836 | spin_lock_irq(&dev->event_lock); | |
10837 | work = intel_crtc->unpin_work; | |
10838 | intel_crtc->unpin_work = NULL; | |
10839 | spin_unlock_irq(&dev->event_lock); | |
10840 | ||
10841 | if (work) { | |
10842 | cancel_work_sync(&work->work); | |
10843 | kfree(work); | |
10844 | } | |
10845 | ||
10846 | drm_crtc_cleanup(crtc); | |
10847 | ||
10848 | kfree(intel_crtc); | |
10849 | } | |
10850 | ||
10851 | static void intel_unpin_work_fn(struct work_struct *__work) | |
10852 | { | |
10853 | struct intel_unpin_work *work = | |
10854 | container_of(__work, struct intel_unpin_work, work); | |
10855 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); | |
10856 | struct drm_device *dev = crtc->base.dev; | |
10857 | struct drm_plane *primary = crtc->base.primary; | |
10858 | ||
10859 | mutex_lock(&dev->struct_mutex); | |
10860 | intel_unpin_fb_obj(work->old_fb, primary->state->rotation); | |
10861 | drm_gem_object_unreference(&work->pending_flip_obj->base); | |
10862 | ||
10863 | if (work->flip_queued_req) | |
10864 | i915_gem_request_assign(&work->flip_queued_req, NULL); | |
10865 | mutex_unlock(&dev->struct_mutex); | |
10866 | ||
10867 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); | |
10868 | intel_fbc_post_update(crtc); | |
10869 | drm_framebuffer_unreference(work->old_fb); | |
10870 | ||
10871 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); | |
10872 | atomic_dec(&crtc->unpin_work_count); | |
10873 | ||
10874 | kfree(work); | |
10875 | } | |
10876 | ||
10877 | static void do_intel_finish_page_flip(struct drm_device *dev, | |
10878 | struct drm_crtc *crtc) | |
10879 | { | |
10880 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10881 | struct intel_unpin_work *work; | |
10882 | unsigned long flags; | |
10883 | ||
10884 | /* Ignore early vblank irqs */ | |
10885 | if (intel_crtc == NULL) | |
10886 | return; | |
10887 | ||
10888 | /* | |
10889 | * This is called both by irq handlers and the reset code (to complete | |
10890 | * lost pageflips) so needs the full irqsave spinlocks. | |
10891 | */ | |
10892 | spin_lock_irqsave(&dev->event_lock, flags); | |
10893 | work = intel_crtc->unpin_work; | |
10894 | ||
10895 | /* Ensure we don't miss a work->pending update ... */ | |
10896 | smp_rmb(); | |
10897 | ||
10898 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
10899 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
10900 | return; | |
10901 | } | |
10902 | ||
10903 | page_flip_completed(intel_crtc); | |
10904 | ||
10905 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
10906 | } | |
10907 | ||
10908 | void intel_finish_page_flip(struct drm_device *dev, int pipe) | |
10909 | { | |
10910 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10911 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
10912 | ||
10913 | do_intel_finish_page_flip(dev, crtc); | |
10914 | } | |
10915 | ||
10916 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10917 | { | |
10918 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10919 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
10920 | ||
10921 | do_intel_finish_page_flip(dev, crtc); | |
10922 | } | |
10923 | ||
10924 | /* Is 'a' after or equal to 'b'? */ | |
10925 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10926 | { | |
10927 | return !((a - b) & 0x80000000); | |
10928 | } | |
10929 | ||
10930 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10931 | { | |
10932 | struct drm_device *dev = crtc->base.dev; | |
10933 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10934 | unsigned reset_counter; | |
10935 | ||
10936 | reset_counter = i915_reset_counter(&dev_priv->gpu_error); | |
10937 | if (crtc->reset_counter != reset_counter) | |
10938 | return true; | |
10939 | ||
10940 | /* | |
10941 | * The relevant registers doen't exist on pre-ctg. | |
10942 | * As the flip done interrupt doesn't trigger for mmio | |
10943 | * flips on gmch platforms, a flip count check isn't | |
10944 | * really needed there. But since ctg has the registers, | |
10945 | * include it in the check anyway. | |
10946 | */ | |
10947 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10948 | return true; | |
10949 | ||
10950 | /* | |
10951 | * BDW signals flip done immediately if the plane | |
10952 | * is disabled, even if the plane enable is already | |
10953 | * armed to occur at the next vblank :( | |
10954 | */ | |
10955 | ||
10956 | /* | |
10957 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10958 | * used the same base address. In that case the mmio flip might | |
10959 | * have completed, but the CS hasn't even executed the flip yet. | |
10960 | * | |
10961 | * A flip count check isn't enough as the CS might have updated | |
10962 | * the base address just after start of vblank, but before we | |
10963 | * managed to process the interrupt. This means we'd complete the | |
10964 | * CS flip too soon. | |
10965 | * | |
10966 | * Combining both checks should get us a good enough result. It may | |
10967 | * still happen that the CS flip has been executed, but has not | |
10968 | * yet actually completed. But in case the base address is the same | |
10969 | * anyway, we don't really care. | |
10970 | */ | |
10971 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
10972 | crtc->unpin_work->gtt_offset && | |
10973 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), | |
10974 | crtc->unpin_work->flip_count); | |
10975 | } | |
10976 | ||
10977 | void intel_prepare_page_flip(struct drm_device *dev, int plane) | |
10978 | { | |
10979 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10980 | struct intel_crtc *intel_crtc = | |
10981 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
10982 | unsigned long flags; | |
10983 | ||
10984 | ||
10985 | /* | |
10986 | * This is called both by irq handlers and the reset code (to complete | |
10987 | * lost pageflips) so needs the full irqsave spinlocks. | |
10988 | * | |
10989 | * NB: An MMIO update of the plane base pointer will also | |
10990 | * generate a page-flip completion irq, i.e. every modeset | |
10991 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
10992 | */ | |
10993 | spin_lock_irqsave(&dev->event_lock, flags); | |
10994 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) | |
10995 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); | |
10996 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
10997 | } | |
10998 | ||
10999 | static inline void intel_mark_page_flip_active(struct intel_unpin_work *work) | |
11000 | { | |
11001 | /* Ensure that the work item is consistent when activating it ... */ | |
11002 | smp_wmb(); | |
11003 | atomic_set(&work->pending, INTEL_FLIP_PENDING); | |
11004 | /* and that it is marked active as soon as the irq could fire. */ | |
11005 | smp_wmb(); | |
11006 | } | |
11007 | ||
11008 | static int intel_gen2_queue_flip(struct drm_device *dev, | |
11009 | struct drm_crtc *crtc, | |
11010 | struct drm_framebuffer *fb, | |
11011 | struct drm_i915_gem_object *obj, | |
11012 | struct drm_i915_gem_request *req, | |
11013 | uint32_t flags) | |
11014 | { | |
11015 | struct intel_engine_cs *engine = req->engine; | |
11016 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11017 | u32 flip_mask; | |
11018 | int ret; | |
11019 | ||
11020 | ret = intel_ring_begin(req, 6); | |
11021 | if (ret) | |
11022 | return ret; | |
11023 | ||
11024 | /* Can't queue multiple flips, so wait for the previous | |
11025 | * one to finish before executing the next. | |
11026 | */ | |
11027 | if (intel_crtc->plane) | |
11028 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11029 | else | |
11030 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
11031 | intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask); | |
11032 | intel_ring_emit(engine, MI_NOOP); | |
11033 | intel_ring_emit(engine, MI_DISPLAY_FLIP | | |
11034 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11035 | intel_ring_emit(engine, fb->pitches[0]); | |
11036 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
11037 | intel_ring_emit(engine, 0); /* aux display base address, unused */ | |
11038 | ||
11039 | intel_mark_page_flip_active(intel_crtc->unpin_work); | |
11040 | return 0; | |
11041 | } | |
11042 | ||
11043 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
11044 | struct drm_crtc *crtc, | |
11045 | struct drm_framebuffer *fb, | |
11046 | struct drm_i915_gem_object *obj, | |
11047 | struct drm_i915_gem_request *req, | |
11048 | uint32_t flags) | |
11049 | { | |
11050 | struct intel_engine_cs *engine = req->engine; | |
11051 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11052 | u32 flip_mask; | |
11053 | int ret; | |
11054 | ||
11055 | ret = intel_ring_begin(req, 6); | |
11056 | if (ret) | |
11057 | return ret; | |
11058 | ||
11059 | if (intel_crtc->plane) | |
11060 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11061 | else | |
11062 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
11063 | intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask); | |
11064 | intel_ring_emit(engine, MI_NOOP); | |
11065 | intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | | |
11066 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11067 | intel_ring_emit(engine, fb->pitches[0]); | |
11068 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
11069 | intel_ring_emit(engine, MI_NOOP); | |
11070 | ||
11071 | intel_mark_page_flip_active(intel_crtc->unpin_work); | |
11072 | return 0; | |
11073 | } | |
11074 | ||
11075 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
11076 | struct drm_crtc *crtc, | |
11077 | struct drm_framebuffer *fb, | |
11078 | struct drm_i915_gem_object *obj, | |
11079 | struct drm_i915_gem_request *req, | |
11080 | uint32_t flags) | |
11081 | { | |
11082 | struct intel_engine_cs *engine = req->engine; | |
11083 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11084 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11085 | uint32_t pf, pipesrc; | |
11086 | int ret; | |
11087 | ||
11088 | ret = intel_ring_begin(req, 4); | |
11089 | if (ret) | |
11090 | return ret; | |
11091 | ||
11092 | /* i965+ uses the linear or tiled offsets from the | |
11093 | * Display Registers (which do not change across a page-flip) | |
11094 | * so we need only reprogram the base address. | |
11095 | */ | |
11096 | intel_ring_emit(engine, MI_DISPLAY_FLIP | | |
11097 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11098 | intel_ring_emit(engine, fb->pitches[0]); | |
11099 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset | | |
11100 | obj->tiling_mode); | |
11101 | ||
11102 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11103 | * untested on non-native modes, so ignore it for now. | |
11104 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11105 | */ | |
11106 | pf = 0; | |
11107 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
11108 | intel_ring_emit(engine, pf | pipesrc); | |
11109 | ||
11110 | intel_mark_page_flip_active(intel_crtc->unpin_work); | |
11111 | return 0; | |
11112 | } | |
11113 | ||
11114 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
11115 | struct drm_crtc *crtc, | |
11116 | struct drm_framebuffer *fb, | |
11117 | struct drm_i915_gem_object *obj, | |
11118 | struct drm_i915_gem_request *req, | |
11119 | uint32_t flags) | |
11120 | { | |
11121 | struct intel_engine_cs *engine = req->engine; | |
11122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11123 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11124 | uint32_t pf, pipesrc; | |
11125 | int ret; | |
11126 | ||
11127 | ret = intel_ring_begin(req, 4); | |
11128 | if (ret) | |
11129 | return ret; | |
11130 | ||
11131 | intel_ring_emit(engine, MI_DISPLAY_FLIP | | |
11132 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11133 | intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode); | |
11134 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
11135 | ||
11136 | /* Contrary to the suggestions in the documentation, | |
11137 | * "Enable Panel Fitter" does not seem to be required when page | |
11138 | * flipping with a non-native mode, and worse causes a normal | |
11139 | * modeset to fail. | |
11140 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11141 | */ | |
11142 | pf = 0; | |
11143 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
11144 | intel_ring_emit(engine, pf | pipesrc); | |
11145 | ||
11146 | intel_mark_page_flip_active(intel_crtc->unpin_work); | |
11147 | return 0; | |
11148 | } | |
11149 | ||
11150 | static int intel_gen7_queue_flip(struct drm_device *dev, | |
11151 | struct drm_crtc *crtc, | |
11152 | struct drm_framebuffer *fb, | |
11153 | struct drm_i915_gem_object *obj, | |
11154 | struct drm_i915_gem_request *req, | |
11155 | uint32_t flags) | |
11156 | { | |
11157 | struct intel_engine_cs *engine = req->engine; | |
11158 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11159 | uint32_t plane_bit = 0; | |
11160 | int len, ret; | |
11161 | ||
11162 | switch (intel_crtc->plane) { | |
11163 | case PLANE_A: | |
11164 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11165 | break; | |
11166 | case PLANE_B: | |
11167 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11168 | break; | |
11169 | case PLANE_C: | |
11170 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11171 | break; | |
11172 | default: | |
11173 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
11174 | return -ENODEV; | |
11175 | } | |
11176 | ||
11177 | len = 4; | |
11178 | if (engine->id == RCS) { | |
11179 | len += 6; | |
11180 | /* | |
11181 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11182 | * 48bits addresses, and we need a NOOP for the batch size to | |
11183 | * stay even. | |
11184 | */ | |
11185 | if (IS_GEN8(dev)) | |
11186 | len += 2; | |
11187 | } | |
11188 | ||
11189 | /* | |
11190 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11191 | * "The full packet must be contained within the same cache line." | |
11192 | * | |
11193 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11194 | * cacheline, if we ever start emitting more commands before | |
11195 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11196 | * then do the cacheline alignment, and finally emit the | |
11197 | * MI_DISPLAY_FLIP. | |
11198 | */ | |
11199 | ret = intel_ring_cacheline_align(req); | |
11200 | if (ret) | |
11201 | return ret; | |
11202 | ||
11203 | ret = intel_ring_begin(req, len); | |
11204 | if (ret) | |
11205 | return ret; | |
11206 | ||
11207 | /* Unmask the flip-done completion message. Note that the bspec says that | |
11208 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11209 | * more than one flip event at any time (or ensure that one flip message | |
11210 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11211 | * Experimentation says that BCS works despite DERRMR masking all | |
11212 | * flip-done completion events and that unmasking all planes at once | |
11213 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11214 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11215 | */ | |
11216 | if (engine->id == RCS) { | |
11217 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); | |
11218 | intel_ring_emit_reg(engine, DERRMR); | |
11219 | intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
11220 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11221 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
11222 | if (IS_GEN8(dev)) | |
11223 | intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 | | |
11224 | MI_SRM_LRM_GLOBAL_GTT); | |
11225 | else | |
11226 | intel_ring_emit(engine, MI_STORE_REGISTER_MEM | | |
11227 | MI_SRM_LRM_GLOBAL_GTT); | |
11228 | intel_ring_emit_reg(engine, DERRMR); | |
11229 | intel_ring_emit(engine, engine->scratch.gtt_offset + 256); | |
11230 | if (IS_GEN8(dev)) { | |
11231 | intel_ring_emit(engine, 0); | |
11232 | intel_ring_emit(engine, MI_NOOP); | |
11233 | } | |
11234 | } | |
11235 | ||
11236 | intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit); | |
11237 | intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode)); | |
11238 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
11239 | intel_ring_emit(engine, (MI_NOOP)); | |
11240 | ||
11241 | intel_mark_page_flip_active(intel_crtc->unpin_work); | |
11242 | return 0; | |
11243 | } | |
11244 | ||
11245 | static bool use_mmio_flip(struct intel_engine_cs *engine, | |
11246 | struct drm_i915_gem_object *obj) | |
11247 | { | |
11248 | /* | |
11249 | * This is not being used for older platforms, because | |
11250 | * non-availability of flip done interrupt forces us to use | |
11251 | * CS flips. Older platforms derive flip done using some clever | |
11252 | * tricks involving the flip_pending status bits and vblank irqs. | |
11253 | * So using MMIO flips there would disrupt this mechanism. | |
11254 | */ | |
11255 | ||
11256 | if (engine == NULL) | |
11257 | return true; | |
11258 | ||
11259 | if (INTEL_INFO(engine->dev)->gen < 5) | |
11260 | return false; | |
11261 | ||
11262 | if (i915.use_mmio_flip < 0) | |
11263 | return false; | |
11264 | else if (i915.use_mmio_flip > 0) | |
11265 | return true; | |
11266 | else if (i915.enable_execlists) | |
11267 | return true; | |
11268 | else if (obj->base.dma_buf && | |
11269 | !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv, | |
11270 | false)) | |
11271 | return true; | |
11272 | else | |
11273 | return engine != i915_gem_request_get_engine(obj->last_write_req); | |
11274 | } | |
11275 | ||
11276 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, | |
11277 | unsigned int rotation, | |
11278 | struct intel_unpin_work *work) | |
11279 | { | |
11280 | struct drm_device *dev = intel_crtc->base.dev; | |
11281 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11282 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
11283 | const enum pipe pipe = intel_crtc->pipe; | |
11284 | u32 ctl, stride, tile_height; | |
11285 | ||
11286 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11287 | ctl &= ~PLANE_CTL_TILED_MASK; | |
11288 | switch (fb->modifier[0]) { | |
11289 | case DRM_FORMAT_MOD_NONE: | |
11290 | break; | |
11291 | case I915_FORMAT_MOD_X_TILED: | |
11292 | ctl |= PLANE_CTL_TILED_X; | |
11293 | break; | |
11294 | case I915_FORMAT_MOD_Y_TILED: | |
11295 | ctl |= PLANE_CTL_TILED_Y; | |
11296 | break; | |
11297 | case I915_FORMAT_MOD_Yf_TILED: | |
11298 | ctl |= PLANE_CTL_TILED_YF; | |
11299 | break; | |
11300 | default: | |
11301 | MISSING_CASE(fb->modifier[0]); | |
11302 | } | |
11303 | ||
11304 | /* | |
11305 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11306 | * linear buffers or in number of tiles for tiled buffers. | |
11307 | */ | |
11308 | if (intel_rotation_90_or_270(rotation)) { | |
11309 | /* stride = Surface height in tiles */ | |
11310 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0); | |
11311 | stride = DIV_ROUND_UP(fb->height, tile_height); | |
11312 | } else { | |
11313 | stride = fb->pitches[0] / | |
11314 | intel_fb_stride_alignment(dev_priv, fb->modifier[0], | |
11315 | fb->pixel_format); | |
11316 | } | |
11317 | ||
11318 | /* | |
11319 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11320 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11321 | */ | |
11322 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11323 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11324 | ||
11325 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); | |
11326 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
11327 | } | |
11328 | ||
11329 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, | |
11330 | struct intel_unpin_work *work) | |
11331 | { | |
11332 | struct drm_device *dev = intel_crtc->base.dev; | |
11333 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11334 | struct intel_framebuffer *intel_fb = | |
11335 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11336 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
11337 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); | |
11338 | u32 dspcntr; | |
11339 | ||
11340 | dspcntr = I915_READ(reg); | |
11341 | ||
11342 | if (obj->tiling_mode != I915_TILING_NONE) | |
11343 | dspcntr |= DISPPLANE_TILED; | |
11344 | else | |
11345 | dspcntr &= ~DISPPLANE_TILED; | |
11346 | ||
11347 | I915_WRITE(reg, dspcntr); | |
11348 | ||
11349 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); | |
11350 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
11351 | } | |
11352 | ||
11353 | /* | |
11354 | * XXX: This is the temporary way to update the plane registers until we get | |
11355 | * around to using the usual plane update functions for MMIO flips | |
11356 | */ | |
11357 | static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) | |
11358 | { | |
11359 | struct intel_crtc *crtc = mmio_flip->crtc; | |
11360 | struct intel_unpin_work *work; | |
11361 | ||
11362 | spin_lock_irq(&crtc->base.dev->event_lock); | |
11363 | work = crtc->unpin_work; | |
11364 | spin_unlock_irq(&crtc->base.dev->event_lock); | |
11365 | if (work == NULL) | |
11366 | return; | |
11367 | ||
11368 | intel_mark_page_flip_active(work); | |
11369 | ||
11370 | intel_pipe_update_start(crtc); | |
11371 | ||
11372 | if (INTEL_INFO(mmio_flip->i915)->gen >= 9) | |
11373 | skl_do_mmio_flip(crtc, mmio_flip->rotation, work); | |
11374 | else | |
11375 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
11376 | ilk_do_mmio_flip(crtc, work); | |
11377 | ||
11378 | intel_pipe_update_end(crtc); | |
11379 | } | |
11380 | ||
11381 | static void intel_mmio_flip_work_func(struct work_struct *work) | |
11382 | { | |
11383 | struct intel_mmio_flip *mmio_flip = | |
11384 | container_of(work, struct intel_mmio_flip, work); | |
11385 | struct intel_framebuffer *intel_fb = | |
11386 | to_intel_framebuffer(mmio_flip->crtc->base.primary->fb); | |
11387 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
11388 | ||
11389 | if (mmio_flip->req) { | |
11390 | WARN_ON(__i915_wait_request(mmio_flip->req, | |
11391 | false, NULL, | |
11392 | &mmio_flip->i915->rps.mmioflips)); | |
11393 | i915_gem_request_unreference(mmio_flip->req); | |
11394 | } | |
11395 | ||
11396 | /* For framebuffer backed by dmabuf, wait for fence */ | |
11397 | if (obj->base.dma_buf) | |
11398 | WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
11399 | false, false, | |
11400 | MAX_SCHEDULE_TIMEOUT) < 0); | |
11401 | ||
11402 | intel_do_mmio_flip(mmio_flip); | |
11403 | kfree(mmio_flip); | |
11404 | } | |
11405 | ||
11406 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11407 | struct drm_crtc *crtc, | |
11408 | struct drm_i915_gem_object *obj) | |
11409 | { | |
11410 | struct intel_mmio_flip *mmio_flip; | |
11411 | ||
11412 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11413 | if (mmio_flip == NULL) | |
11414 | return -ENOMEM; | |
11415 | ||
11416 | mmio_flip->i915 = to_i915(dev); | |
11417 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); | |
11418 | mmio_flip->crtc = to_intel_crtc(crtc); | |
11419 | mmio_flip->rotation = crtc->primary->state->rotation; | |
11420 | ||
11421 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); | |
11422 | schedule_work(&mmio_flip->work); | |
11423 | ||
11424 | return 0; | |
11425 | } | |
11426 | ||
11427 | static int intel_default_queue_flip(struct drm_device *dev, | |
11428 | struct drm_crtc *crtc, | |
11429 | struct drm_framebuffer *fb, | |
11430 | struct drm_i915_gem_object *obj, | |
11431 | struct drm_i915_gem_request *req, | |
11432 | uint32_t flags) | |
11433 | { | |
11434 | return -ENODEV; | |
11435 | } | |
11436 | ||
11437 | static bool __intel_pageflip_stall_check(struct drm_device *dev, | |
11438 | struct drm_crtc *crtc) | |
11439 | { | |
11440 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11441 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11442 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11443 | u32 addr; | |
11444 | ||
11445 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
11446 | return true; | |
11447 | ||
11448 | if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) | |
11449 | return false; | |
11450 | ||
11451 | if (!work->enable_stall_check) | |
11452 | return false; | |
11453 | ||
11454 | if (work->flip_ready_vblank == 0) { | |
11455 | if (work->flip_queued_req && | |
11456 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
11457 | return false; | |
11458 | ||
11459 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); | |
11460 | } | |
11461 | ||
11462 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) | |
11463 | return false; | |
11464 | ||
11465 | /* Potential stall - if we see that the flip has happened, | |
11466 | * assume a missed interrupt. */ | |
11467 | if (INTEL_INFO(dev)->gen >= 4) | |
11468 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11469 | else | |
11470 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11471 | ||
11472 | /* There is a potential issue here with a false positive after a flip | |
11473 | * to the same address. We could address this by checking for a | |
11474 | * non-incrementing frame counter. | |
11475 | */ | |
11476 | return addr == work->gtt_offset; | |
11477 | } | |
11478 | ||
11479 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
11480 | { | |
11481 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11482 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11483 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11484 | struct intel_unpin_work *work; | |
11485 | ||
11486 | WARN_ON(!in_interrupt()); | |
11487 | ||
11488 | if (crtc == NULL) | |
11489 | return; | |
11490 | ||
11491 | spin_lock(&dev->event_lock); | |
11492 | work = intel_crtc->unpin_work; | |
11493 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
11494 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", | |
11495 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); | |
11496 | page_flip_completed(intel_crtc); | |
11497 | work = NULL; | |
11498 | } | |
11499 | if (work != NULL && | |
11500 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
11501 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
11502 | spin_unlock(&dev->event_lock); | |
11503 | } | |
11504 | ||
11505 | static int intel_crtc_page_flip(struct drm_crtc *crtc, | |
11506 | struct drm_framebuffer *fb, | |
11507 | struct drm_pending_vblank_event *event, | |
11508 | uint32_t page_flip_flags) | |
11509 | { | |
11510 | struct drm_device *dev = crtc->dev; | |
11511 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11512 | struct drm_framebuffer *old_fb = crtc->primary->fb; | |
11513 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
11514 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11515 | struct drm_plane *primary = crtc->primary; | |
11516 | enum pipe pipe = intel_crtc->pipe; | |
11517 | struct intel_unpin_work *work; | |
11518 | struct intel_engine_cs *engine; | |
11519 | bool mmio_flip; | |
11520 | struct drm_i915_gem_request *request = NULL; | |
11521 | int ret; | |
11522 | ||
11523 | /* | |
11524 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11525 | * check to be safe. In the future we may enable pageflipping from | |
11526 | * a disabled primary plane. | |
11527 | */ | |
11528 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11529 | return -EBUSY; | |
11530 | ||
11531 | /* Can't change pixel format via MI display flips. */ | |
11532 | if (fb->pixel_format != crtc->primary->fb->pixel_format) | |
11533 | return -EINVAL; | |
11534 | ||
11535 | /* | |
11536 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11537 | * Note that pitch changes could also affect these register. | |
11538 | */ | |
11539 | if (INTEL_INFO(dev)->gen > 3 && | |
11540 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || | |
11541 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
11542 | return -EINVAL; | |
11543 | ||
11544 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
11545 | goto out_hang; | |
11546 | ||
11547 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
11548 | if (work == NULL) | |
11549 | return -ENOMEM; | |
11550 | ||
11551 | work->event = event; | |
11552 | work->crtc = crtc; | |
11553 | work->old_fb = old_fb; | |
11554 | INIT_WORK(&work->work, intel_unpin_work_fn); | |
11555 | ||
11556 | ret = drm_crtc_vblank_get(crtc); | |
11557 | if (ret) | |
11558 | goto free_work; | |
11559 | ||
11560 | /* We borrow the event spin lock for protecting unpin_work */ | |
11561 | spin_lock_irq(&dev->event_lock); | |
11562 | if (intel_crtc->unpin_work) { | |
11563 | /* Before declaring the flip queue wedged, check if | |
11564 | * the hardware completed the operation behind our backs. | |
11565 | */ | |
11566 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11567 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11568 | page_flip_completed(intel_crtc); | |
11569 | } else { | |
11570 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
11571 | spin_unlock_irq(&dev->event_lock); | |
11572 | ||
11573 | drm_crtc_vblank_put(crtc); | |
11574 | kfree(work); | |
11575 | return -EBUSY; | |
11576 | } | |
11577 | } | |
11578 | intel_crtc->unpin_work = work; | |
11579 | spin_unlock_irq(&dev->event_lock); | |
11580 | ||
11581 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) | |
11582 | flush_workqueue(dev_priv->wq); | |
11583 | ||
11584 | /* Reference the objects for the scheduled work. */ | |
11585 | drm_framebuffer_reference(work->old_fb); | |
11586 | drm_gem_object_reference(&obj->base); | |
11587 | ||
11588 | crtc->primary->fb = fb; | |
11589 | update_state_fb(crtc->primary); | |
11590 | intel_fbc_pre_update(intel_crtc); | |
11591 | ||
11592 | work->pending_flip_obj = obj; | |
11593 | ||
11594 | ret = i915_mutex_lock_interruptible(dev); | |
11595 | if (ret) | |
11596 | goto cleanup; | |
11597 | ||
11598 | intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error); | |
11599 | if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) { | |
11600 | ret = -EIO; | |
11601 | goto cleanup; | |
11602 | } | |
11603 | ||
11604 | atomic_inc(&intel_crtc->unpin_work_count); | |
11605 | ||
11606 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
11607 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; | |
11608 | ||
11609 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { | |
11610 | engine = &dev_priv->engine[BCS]; | |
11611 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) | |
11612 | /* vlv: DISPLAY_FLIP fails to change tiling */ | |
11613 | engine = NULL; | |
11614 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { | |
11615 | engine = &dev_priv->engine[BCS]; | |
11616 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
11617 | engine = i915_gem_request_get_engine(obj->last_write_req); | |
11618 | if (engine == NULL || engine->id != RCS) | |
11619 | engine = &dev_priv->engine[BCS]; | |
11620 | } else { | |
11621 | engine = &dev_priv->engine[RCS]; | |
11622 | } | |
11623 | ||
11624 | mmio_flip = use_mmio_flip(engine, obj); | |
11625 | ||
11626 | /* When using CS flips, we want to emit semaphores between rings. | |
11627 | * However, when using mmio flips we will create a task to do the | |
11628 | * synchronisation, so all we want here is to pin the framebuffer | |
11629 | * into the display plane and skip any waits. | |
11630 | */ | |
11631 | if (!mmio_flip) { | |
11632 | ret = i915_gem_object_sync(obj, engine, &request); | |
11633 | if (ret) | |
11634 | goto cleanup_pending; | |
11635 | } | |
11636 | ||
11637 | ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); | |
11638 | if (ret) | |
11639 | goto cleanup_pending; | |
11640 | ||
11641 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), | |
11642 | obj, 0); | |
11643 | work->gtt_offset += intel_crtc->dspaddr_offset; | |
11644 | ||
11645 | if (mmio_flip) { | |
11646 | ret = intel_queue_mmio_flip(dev, crtc, obj); | |
11647 | if (ret) | |
11648 | goto cleanup_unpin; | |
11649 | ||
11650 | i915_gem_request_assign(&work->flip_queued_req, | |
11651 | obj->last_write_req); | |
11652 | } else { | |
11653 | if (!request) { | |
11654 | request = i915_gem_request_alloc(engine, NULL); | |
11655 | if (IS_ERR(request)) { | |
11656 | ret = PTR_ERR(request); | |
11657 | goto cleanup_unpin; | |
11658 | } | |
11659 | } | |
11660 | ||
11661 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, | |
11662 | page_flip_flags); | |
11663 | if (ret) | |
11664 | goto cleanup_unpin; | |
11665 | ||
11666 | i915_gem_request_assign(&work->flip_queued_req, request); | |
11667 | } | |
11668 | ||
11669 | if (request) | |
11670 | i915_add_request_no_flush(request); | |
11671 | ||
11672 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); | |
11673 | work->enable_stall_check = true; | |
11674 | ||
11675 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, | |
11676 | to_intel_plane(primary)->frontbuffer_bit); | |
11677 | mutex_unlock(&dev->struct_mutex); | |
11678 | ||
11679 | intel_frontbuffer_flip_prepare(dev, | |
11680 | to_intel_plane(primary)->frontbuffer_bit); | |
11681 | ||
11682 | trace_i915_flip_request(intel_crtc->plane, obj); | |
11683 | ||
11684 | return 0; | |
11685 | ||
11686 | cleanup_unpin: | |
11687 | intel_unpin_fb_obj(fb, crtc->primary->state->rotation); | |
11688 | cleanup_pending: | |
11689 | if (!IS_ERR_OR_NULL(request)) | |
11690 | i915_add_request_no_flush(request); | |
11691 | atomic_dec(&intel_crtc->unpin_work_count); | |
11692 | mutex_unlock(&dev->struct_mutex); | |
11693 | cleanup: | |
11694 | crtc->primary->fb = old_fb; | |
11695 | update_state_fb(crtc->primary); | |
11696 | ||
11697 | drm_gem_object_unreference_unlocked(&obj->base); | |
11698 | drm_framebuffer_unreference(work->old_fb); | |
11699 | ||
11700 | spin_lock_irq(&dev->event_lock); | |
11701 | intel_crtc->unpin_work = NULL; | |
11702 | spin_unlock_irq(&dev->event_lock); | |
11703 | ||
11704 | drm_crtc_vblank_put(crtc); | |
11705 | free_work: | |
11706 | kfree(work); | |
11707 | ||
11708 | if (ret == -EIO) { | |
11709 | struct drm_atomic_state *state; | |
11710 | struct drm_plane_state *plane_state; | |
11711 | ||
11712 | out_hang: | |
11713 | state = drm_atomic_state_alloc(dev); | |
11714 | if (!state) | |
11715 | return -ENOMEM; | |
11716 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11717 | ||
11718 | retry: | |
11719 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11720 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11721 | if (!ret) { | |
11722 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11723 | ||
11724 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11725 | if (!ret) | |
11726 | ret = drm_atomic_commit(state); | |
11727 | } | |
11728 | ||
11729 | if (ret == -EDEADLK) { | |
11730 | drm_modeset_backoff(state->acquire_ctx); | |
11731 | drm_atomic_state_clear(state); | |
11732 | goto retry; | |
11733 | } | |
11734 | ||
11735 | if (ret) | |
11736 | drm_atomic_state_free(state); | |
11737 | ||
11738 | if (ret == 0 && event) { | |
11739 | spin_lock_irq(&dev->event_lock); | |
11740 | drm_crtc_send_vblank_event(crtc, event); | |
11741 | spin_unlock_irq(&dev->event_lock); | |
11742 | } | |
11743 | } | |
11744 | return ret; | |
11745 | } | |
11746 | ||
11747 | ||
11748 | /** | |
11749 | * intel_wm_need_update - Check whether watermarks need updating | |
11750 | * @plane: drm plane | |
11751 | * @state: new plane state | |
11752 | * | |
11753 | * Check current plane state versus the new one to determine whether | |
11754 | * watermarks need to be recalculated. | |
11755 | * | |
11756 | * Returns true or false. | |
11757 | */ | |
11758 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11759 | struct drm_plane_state *state) | |
11760 | { | |
11761 | struct intel_plane_state *new = to_intel_plane_state(state); | |
11762 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
11763 | ||
11764 | /* Update watermarks on tiling or size changes. */ | |
11765 | if (new->visible != cur->visible) | |
11766 | return true; | |
11767 | ||
11768 | if (!cur->base.fb || !new->base.fb) | |
11769 | return false; | |
11770 | ||
11771 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
11772 | cur->base.rotation != new->base.rotation || | |
11773 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || | |
11774 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
11775 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
11776 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
11777 | return true; | |
11778 | ||
11779 | return false; | |
11780 | } | |
11781 | ||
11782 | static bool needs_scaling(struct intel_plane_state *state) | |
11783 | { | |
11784 | int src_w = drm_rect_width(&state->src) >> 16; | |
11785 | int src_h = drm_rect_height(&state->src) >> 16; | |
11786 | int dst_w = drm_rect_width(&state->dst); | |
11787 | int dst_h = drm_rect_height(&state->dst); | |
11788 | ||
11789 | return (src_w != dst_w || src_h != dst_h); | |
11790 | } | |
11791 | ||
11792 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, | |
11793 | struct drm_plane_state *plane_state) | |
11794 | { | |
11795 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); | |
11796 | struct drm_crtc *crtc = crtc_state->crtc; | |
11797 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11798 | struct drm_plane *plane = plane_state->plane; | |
11799 | struct drm_device *dev = crtc->dev; | |
11800 | struct drm_i915_private *dev_priv = to_i915(dev); | |
11801 | struct intel_plane_state *old_plane_state = | |
11802 | to_intel_plane_state(plane->state); | |
11803 | int idx = intel_crtc->base.base.id, ret; | |
11804 | bool mode_changed = needs_modeset(crtc_state); | |
11805 | bool was_crtc_enabled = crtc->state->active; | |
11806 | bool is_crtc_enabled = crtc_state->active; | |
11807 | bool turn_off, turn_on, visible, was_visible; | |
11808 | struct drm_framebuffer *fb = plane_state->fb; | |
11809 | ||
11810 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && | |
11811 | plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11812 | ret = skl_update_scaler_plane( | |
11813 | to_intel_crtc_state(crtc_state), | |
11814 | to_intel_plane_state(plane_state)); | |
11815 | if (ret) | |
11816 | return ret; | |
11817 | } | |
11818 | ||
11819 | was_visible = old_plane_state->visible; | |
11820 | visible = to_intel_plane_state(plane_state)->visible; | |
11821 | ||
11822 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11823 | was_visible = false; | |
11824 | ||
11825 | /* | |
11826 | * Visibility is calculated as if the crtc was on, but | |
11827 | * after scaler setup everything depends on it being off | |
11828 | * when the crtc isn't active. | |
11829 | */ | |
11830 | if (!is_crtc_enabled) | |
11831 | to_intel_plane_state(plane_state)->visible = visible = false; | |
11832 | ||
11833 | if (!was_visible && !visible) | |
11834 | return 0; | |
11835 | ||
11836 | if (fb != old_plane_state->base.fb) | |
11837 | pipe_config->fb_changed = true; | |
11838 | ||
11839 | turn_off = was_visible && (!visible || mode_changed); | |
11840 | turn_on = visible && (!was_visible || mode_changed); | |
11841 | ||
11842 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, | |
11843 | plane->base.id, fb ? fb->base.id : -1); | |
11844 | ||
11845 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", | |
11846 | plane->base.id, was_visible, visible, | |
11847 | turn_off, turn_on, mode_changed); | |
11848 | ||
11849 | if (turn_on) { | |
11850 | pipe_config->update_wm_pre = true; | |
11851 | ||
11852 | /* must disable cxsr around plane enable/disable */ | |
11853 | if (plane->type != DRM_PLANE_TYPE_CURSOR) | |
11854 | pipe_config->disable_cxsr = true; | |
11855 | } else if (turn_off) { | |
11856 | pipe_config->update_wm_post = true; | |
11857 | ||
11858 | /* must disable cxsr around plane enable/disable */ | |
11859 | if (plane->type != DRM_PLANE_TYPE_CURSOR) | |
11860 | pipe_config->disable_cxsr = true; | |
11861 | } else if (intel_wm_need_update(plane, plane_state)) { | |
11862 | /* FIXME bollocks */ | |
11863 | pipe_config->update_wm_pre = true; | |
11864 | pipe_config->update_wm_post = true; | |
11865 | } | |
11866 | ||
11867 | /* Pre-gen9 platforms need two-step watermark updates */ | |
11868 | if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && | |
11869 | INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks) | |
11870 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; | |
11871 | ||
11872 | if (visible || was_visible) | |
11873 | pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit; | |
11874 | ||
11875 | /* | |
11876 | * WaCxSRDisabledForSpriteScaling:ivb | |
11877 | * | |
11878 | * cstate->update_wm was already set above, so this flag will | |
11879 | * take effect when we commit and program watermarks. | |
11880 | */ | |
11881 | if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) && | |
11882 | needs_scaling(to_intel_plane_state(plane_state)) && | |
11883 | !needs_scaling(old_plane_state)) | |
11884 | pipe_config->disable_lp_wm = true; | |
11885 | ||
11886 | return 0; | |
11887 | } | |
11888 | ||
11889 | static bool encoders_cloneable(const struct intel_encoder *a, | |
11890 | const struct intel_encoder *b) | |
11891 | { | |
11892 | /* masks could be asymmetric, so check both ways */ | |
11893 | return a == b || (a->cloneable & (1 << b->type) && | |
11894 | b->cloneable & (1 << a->type)); | |
11895 | } | |
11896 | ||
11897 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
11898 | struct intel_crtc *crtc, | |
11899 | struct intel_encoder *encoder) | |
11900 | { | |
11901 | struct intel_encoder *source_encoder; | |
11902 | struct drm_connector *connector; | |
11903 | struct drm_connector_state *connector_state; | |
11904 | int i; | |
11905 | ||
11906 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11907 | if (connector_state->crtc != &crtc->base) | |
11908 | continue; | |
11909 | ||
11910 | source_encoder = | |
11911 | to_intel_encoder(connector_state->best_encoder); | |
11912 | if (!encoders_cloneable(encoder, source_encoder)) | |
11913 | return false; | |
11914 | } | |
11915 | ||
11916 | return true; | |
11917 | } | |
11918 | ||
11919 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
11920 | struct intel_crtc *crtc) | |
11921 | { | |
11922 | struct intel_encoder *encoder; | |
11923 | struct drm_connector *connector; | |
11924 | struct drm_connector_state *connector_state; | |
11925 | int i; | |
11926 | ||
11927 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11928 | if (connector_state->crtc != &crtc->base) | |
11929 | continue; | |
11930 | ||
11931 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11932 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
11933 | return false; | |
11934 | } | |
11935 | ||
11936 | return true; | |
11937 | } | |
11938 | ||
11939 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
11940 | struct drm_crtc_state *crtc_state) | |
11941 | { | |
11942 | struct drm_device *dev = crtc->dev; | |
11943 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11944 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11945 | struct intel_crtc_state *pipe_config = | |
11946 | to_intel_crtc_state(crtc_state); | |
11947 | struct drm_atomic_state *state = crtc_state->state; | |
11948 | int ret; | |
11949 | bool mode_changed = needs_modeset(crtc_state); | |
11950 | ||
11951 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
11952 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
11953 | return -EINVAL; | |
11954 | } | |
11955 | ||
11956 | if (mode_changed && !crtc_state->active) | |
11957 | pipe_config->update_wm_post = true; | |
11958 | ||
11959 | if (mode_changed && crtc_state->enable && | |
11960 | dev_priv->display.crtc_compute_clock && | |
11961 | !WARN_ON(pipe_config->shared_dpll)) { | |
11962 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, | |
11963 | pipe_config); | |
11964 | if (ret) | |
11965 | return ret; | |
11966 | } | |
11967 | ||
11968 | if (crtc_state->color_mgmt_changed) { | |
11969 | ret = intel_color_check(crtc, crtc_state); | |
11970 | if (ret) | |
11971 | return ret; | |
11972 | } | |
11973 | ||
11974 | ret = 0; | |
11975 | if (dev_priv->display.compute_pipe_wm) { | |
11976 | ret = dev_priv->display.compute_pipe_wm(pipe_config); | |
11977 | if (ret) { | |
11978 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
11979 | return ret; | |
11980 | } | |
11981 | } | |
11982 | ||
11983 | if (dev_priv->display.compute_intermediate_wm && | |
11984 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
11985 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
11986 | return 0; | |
11987 | ||
11988 | /* | |
11989 | * Calculate 'intermediate' watermarks that satisfy both the | |
11990 | * old state and the new state. We can program these | |
11991 | * immediately. | |
11992 | */ | |
11993 | ret = dev_priv->display.compute_intermediate_wm(crtc->dev, | |
11994 | intel_crtc, | |
11995 | pipe_config); | |
11996 | if (ret) { | |
11997 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
11998 | return ret; | |
11999 | } | |
12000 | } | |
12001 | ||
12002 | if (INTEL_INFO(dev)->gen >= 9) { | |
12003 | if (mode_changed) | |
12004 | ret = skl_update_scaler_crtc(pipe_config); | |
12005 | ||
12006 | if (!ret) | |
12007 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
12008 | pipe_config); | |
12009 | } | |
12010 | ||
12011 | return ret; | |
12012 | } | |
12013 | ||
12014 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { | |
12015 | .mode_set_base_atomic = intel_pipe_set_base_atomic, | |
12016 | .atomic_begin = intel_begin_crtc_commit, | |
12017 | .atomic_flush = intel_finish_crtc_commit, | |
12018 | .atomic_check = intel_crtc_atomic_check, | |
12019 | }; | |
12020 | ||
12021 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) | |
12022 | { | |
12023 | struct intel_connector *connector; | |
12024 | ||
12025 | for_each_intel_connector(dev, connector) { | |
12026 | if (connector->base.encoder) { | |
12027 | connector->base.state->best_encoder = | |
12028 | connector->base.encoder; | |
12029 | connector->base.state->crtc = | |
12030 | connector->base.encoder->crtc; | |
12031 | } else { | |
12032 | connector->base.state->best_encoder = NULL; | |
12033 | connector->base.state->crtc = NULL; | |
12034 | } | |
12035 | } | |
12036 | } | |
12037 | ||
12038 | static void | |
12039 | connected_sink_compute_bpp(struct intel_connector *connector, | |
12040 | struct intel_crtc_state *pipe_config) | |
12041 | { | |
12042 | int bpp = pipe_config->pipe_bpp; | |
12043 | ||
12044 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
12045 | connector->base.base.id, | |
12046 | connector->base.name); | |
12047 | ||
12048 | /* Don't use an invalid EDID bpc value */ | |
12049 | if (connector->base.display_info.bpc && | |
12050 | connector->base.display_info.bpc * 3 < bpp) { | |
12051 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
12052 | bpp, connector->base.display_info.bpc*3); | |
12053 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
12054 | } | |
12055 | ||
12056 | /* Clamp bpp to default limit on screens without EDID 1.4 */ | |
12057 | if (connector->base.display_info.bpc == 0) { | |
12058 | int type = connector->base.connector_type; | |
12059 | int clamp_bpp = 24; | |
12060 | ||
12061 | /* Fall back to 18 bpp when DP sink capability is unknown. */ | |
12062 | if (type == DRM_MODE_CONNECTOR_DisplayPort || | |
12063 | type == DRM_MODE_CONNECTOR_eDP) | |
12064 | clamp_bpp = 18; | |
12065 | ||
12066 | if (bpp > clamp_bpp) { | |
12067 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n", | |
12068 | bpp, clamp_bpp); | |
12069 | pipe_config->pipe_bpp = clamp_bpp; | |
12070 | } | |
12071 | } | |
12072 | } | |
12073 | ||
12074 | static int | |
12075 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, | |
12076 | struct intel_crtc_state *pipe_config) | |
12077 | { | |
12078 | struct drm_device *dev = crtc->base.dev; | |
12079 | struct drm_atomic_state *state; | |
12080 | struct drm_connector *connector; | |
12081 | struct drm_connector_state *connector_state; | |
12082 | int bpp, i; | |
12083 | ||
12084 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) | |
12085 | bpp = 10*3; | |
12086 | else if (INTEL_INFO(dev)->gen >= 5) | |
12087 | bpp = 12*3; | |
12088 | else | |
12089 | bpp = 8*3; | |
12090 | ||
12091 | ||
12092 | pipe_config->pipe_bpp = bpp; | |
12093 | ||
12094 | state = pipe_config->base.state; | |
12095 | ||
12096 | /* Clamp display bpp to EDID value */ | |
12097 | for_each_connector_in_state(state, connector, connector_state, i) { | |
12098 | if (connector_state->crtc != &crtc->base) | |
12099 | continue; | |
12100 | ||
12101 | connected_sink_compute_bpp(to_intel_connector(connector), | |
12102 | pipe_config); | |
12103 | } | |
12104 | ||
12105 | return bpp; | |
12106 | } | |
12107 | ||
12108 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) | |
12109 | { | |
12110 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12111 | "type: 0x%x flags: 0x%x\n", | |
12112 | mode->crtc_clock, | |
12113 | mode->crtc_hdisplay, mode->crtc_hsync_start, | |
12114 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12115 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12116 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12117 | } | |
12118 | ||
12119 | static void intel_dump_pipe_config(struct intel_crtc *crtc, | |
12120 | struct intel_crtc_state *pipe_config, | |
12121 | const char *context) | |
12122 | { | |
12123 | struct drm_device *dev = crtc->base.dev; | |
12124 | struct drm_plane *plane; | |
12125 | struct intel_plane *intel_plane; | |
12126 | struct intel_plane_state *state; | |
12127 | struct drm_framebuffer *fb; | |
12128 | ||
12129 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
12130 | context, pipe_config, pipe_name(crtc->pipe)); | |
12131 | ||
12132 | DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder)); | |
12133 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
12134 | pipe_config->pipe_bpp, pipe_config->dither); | |
12135 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12136 | pipe_config->has_pch_encoder, | |
12137 | pipe_config->fdi_lanes, | |
12138 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12139 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12140 | pipe_config->fdi_m_n.tu); | |
12141 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12142 | pipe_config->has_dp_encoder, | |
12143 | pipe_config->lane_count, | |
12144 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
12145 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12146 | pipe_config->dp_m_n.tu); | |
12147 | ||
12148 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", | |
12149 | pipe_config->has_dp_encoder, | |
12150 | pipe_config->lane_count, | |
12151 | pipe_config->dp_m2_n2.gmch_m, | |
12152 | pipe_config->dp_m2_n2.gmch_n, | |
12153 | pipe_config->dp_m2_n2.link_m, | |
12154 | pipe_config->dp_m2_n2.link_n, | |
12155 | pipe_config->dp_m2_n2.tu); | |
12156 | ||
12157 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", | |
12158 | pipe_config->has_audio, | |
12159 | pipe_config->has_infoframe); | |
12160 | ||
12161 | DRM_DEBUG_KMS("requested mode:\n"); | |
12162 | drm_mode_debug_printmodeline(&pipe_config->base.mode); | |
12163 | DRM_DEBUG_KMS("adjusted mode:\n"); | |
12164 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); | |
12165 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
12166 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); | |
12167 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", | |
12168 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
12169 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", | |
12170 | crtc->num_scalers, | |
12171 | pipe_config->scaler_state.scaler_users, | |
12172 | pipe_config->scaler_state.scaler_id); | |
12173 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", | |
12174 | pipe_config->gmch_pfit.control, | |
12175 | pipe_config->gmch_pfit.pgm_ratios, | |
12176 | pipe_config->gmch_pfit.lvds_border_bits); | |
12177 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", | |
12178 | pipe_config->pch_pfit.pos, | |
12179 | pipe_config->pch_pfit.size, | |
12180 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
12181 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); | |
12182 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); | |
12183 | ||
12184 | if (IS_BROXTON(dev)) { | |
12185 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," | |
12186 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " | |
12187 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", | |
12188 | pipe_config->ddi_pll_sel, | |
12189 | pipe_config->dpll_hw_state.ebb0, | |
12190 | pipe_config->dpll_hw_state.ebb4, | |
12191 | pipe_config->dpll_hw_state.pll0, | |
12192 | pipe_config->dpll_hw_state.pll1, | |
12193 | pipe_config->dpll_hw_state.pll2, | |
12194 | pipe_config->dpll_hw_state.pll3, | |
12195 | pipe_config->dpll_hw_state.pll6, | |
12196 | pipe_config->dpll_hw_state.pll8, | |
12197 | pipe_config->dpll_hw_state.pll9, | |
12198 | pipe_config->dpll_hw_state.pll10, | |
12199 | pipe_config->dpll_hw_state.pcsdw12); | |
12200 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { | |
12201 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " | |
12202 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12203 | pipe_config->ddi_pll_sel, | |
12204 | pipe_config->dpll_hw_state.ctrl1, | |
12205 | pipe_config->dpll_hw_state.cfgcr1, | |
12206 | pipe_config->dpll_hw_state.cfgcr2); | |
12207 | } else if (HAS_DDI(dev)) { | |
12208 | DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", | |
12209 | pipe_config->ddi_pll_sel, | |
12210 | pipe_config->dpll_hw_state.wrpll, | |
12211 | pipe_config->dpll_hw_state.spll); | |
12212 | } else { | |
12213 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12214 | "fp0: 0x%x, fp1: 0x%x\n", | |
12215 | pipe_config->dpll_hw_state.dpll, | |
12216 | pipe_config->dpll_hw_state.dpll_md, | |
12217 | pipe_config->dpll_hw_state.fp0, | |
12218 | pipe_config->dpll_hw_state.fp1); | |
12219 | } | |
12220 | ||
12221 | DRM_DEBUG_KMS("planes on this crtc\n"); | |
12222 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12223 | intel_plane = to_intel_plane(plane); | |
12224 | if (intel_plane->pipe != crtc->pipe) | |
12225 | continue; | |
12226 | ||
12227 | state = to_intel_plane_state(plane->state); | |
12228 | fb = state->base.fb; | |
12229 | if (!fb) { | |
12230 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
12231 | "disabled, scaler_id = %d\n", | |
12232 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12233 | plane->base.id, intel_plane->pipe, | |
12234 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
12235 | drm_plane_index(plane), state->scaler_id); | |
12236 | continue; | |
12237 | } | |
12238 | ||
12239 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
12240 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12241 | plane->base.id, intel_plane->pipe, | |
12242 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
12243 | drm_plane_index(plane)); | |
12244 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
12245 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
12246 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
12247 | state->scaler_id, | |
12248 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12249 | drm_rect_width(&state->src) >> 16, | |
12250 | drm_rect_height(&state->src) >> 16, | |
12251 | state->dst.x1, state->dst.y1, | |
12252 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
12253 | } | |
12254 | } | |
12255 | ||
12256 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) | |
12257 | { | |
12258 | struct drm_device *dev = state->dev; | |
12259 | struct drm_connector *connector; | |
12260 | unsigned int used_ports = 0; | |
12261 | ||
12262 | /* | |
12263 | * Walk the connector list instead of the encoder | |
12264 | * list to detect the problem on ddi platforms | |
12265 | * where there's just one encoder per digital port. | |
12266 | */ | |
12267 | drm_for_each_connector(connector, dev) { | |
12268 | struct drm_connector_state *connector_state; | |
12269 | struct intel_encoder *encoder; | |
12270 | ||
12271 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12272 | if (!connector_state) | |
12273 | connector_state = connector->state; | |
12274 | ||
12275 | if (!connector_state->best_encoder) | |
12276 | continue; | |
12277 | ||
12278 | encoder = to_intel_encoder(connector_state->best_encoder); | |
12279 | ||
12280 | WARN_ON(!connector_state->crtc); | |
12281 | ||
12282 | switch (encoder->type) { | |
12283 | unsigned int port_mask; | |
12284 | case INTEL_OUTPUT_UNKNOWN: | |
12285 | if (WARN_ON(!HAS_DDI(dev))) | |
12286 | break; | |
12287 | case INTEL_OUTPUT_DISPLAYPORT: | |
12288 | case INTEL_OUTPUT_HDMI: | |
12289 | case INTEL_OUTPUT_EDP: | |
12290 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12291 | ||
12292 | /* the same port mustn't appear more than once */ | |
12293 | if (used_ports & port_mask) | |
12294 | return false; | |
12295 | ||
12296 | used_ports |= port_mask; | |
12297 | default: | |
12298 | break; | |
12299 | } | |
12300 | } | |
12301 | ||
12302 | return true; | |
12303 | } | |
12304 | ||
12305 | static void | |
12306 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12307 | { | |
12308 | struct drm_crtc_state tmp_state; | |
12309 | struct intel_crtc_scaler_state scaler_state; | |
12310 | struct intel_dpll_hw_state dpll_hw_state; | |
12311 | struct intel_shared_dpll *shared_dpll; | |
12312 | uint32_t ddi_pll_sel; | |
12313 | bool force_thru; | |
12314 | ||
12315 | /* FIXME: before the switch to atomic started, a new pipe_config was | |
12316 | * kzalloc'd. Code that depends on any field being zero should be | |
12317 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12318 | * only fields that are know to not cause problems are preserved. */ | |
12319 | ||
12320 | tmp_state = crtc_state->base; | |
12321 | scaler_state = crtc_state->scaler_state; | |
12322 | shared_dpll = crtc_state->shared_dpll; | |
12323 | dpll_hw_state = crtc_state->dpll_hw_state; | |
12324 | ddi_pll_sel = crtc_state->ddi_pll_sel; | |
12325 | force_thru = crtc_state->pch_pfit.force_thru; | |
12326 | ||
12327 | memset(crtc_state, 0, sizeof *crtc_state); | |
12328 | ||
12329 | crtc_state->base = tmp_state; | |
12330 | crtc_state->scaler_state = scaler_state; | |
12331 | crtc_state->shared_dpll = shared_dpll; | |
12332 | crtc_state->dpll_hw_state = dpll_hw_state; | |
12333 | crtc_state->ddi_pll_sel = ddi_pll_sel; | |
12334 | crtc_state->pch_pfit.force_thru = force_thru; | |
12335 | } | |
12336 | ||
12337 | static int | |
12338 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
12339 | struct intel_crtc_state *pipe_config) | |
12340 | { | |
12341 | struct drm_atomic_state *state = pipe_config->base.state; | |
12342 | struct intel_encoder *encoder; | |
12343 | struct drm_connector *connector; | |
12344 | struct drm_connector_state *connector_state; | |
12345 | int base_bpp, ret = -EINVAL; | |
12346 | int i; | |
12347 | bool retry = true; | |
12348 | ||
12349 | clear_intel_crtc_state(pipe_config); | |
12350 | ||
12351 | pipe_config->cpu_transcoder = | |
12352 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
12353 | ||
12354 | /* | |
12355 | * Sanitize sync polarity flags based on requested ones. If neither | |
12356 | * positive or negative polarity is requested, treat this as meaning | |
12357 | * negative polarity. | |
12358 | */ | |
12359 | if (!(pipe_config->base.adjusted_mode.flags & | |
12360 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) | |
12361 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
12362 | ||
12363 | if (!(pipe_config->base.adjusted_mode.flags & | |
12364 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) | |
12365 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
12366 | ||
12367 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
12368 | pipe_config); | |
12369 | if (base_bpp < 0) | |
12370 | goto fail; | |
12371 | ||
12372 | /* | |
12373 | * Determine the real pipe dimensions. Note that stereo modes can | |
12374 | * increase the actual pipe size due to the frame doubling and | |
12375 | * insertion of additional space for blanks between the frame. This | |
12376 | * is stored in the crtc timings. We use the requested mode to do this | |
12377 | * computation to clearly distinguish it from the adjusted mode, which | |
12378 | * can be changed by the connectors in the below retry loop. | |
12379 | */ | |
12380 | drm_crtc_get_hv_timing(&pipe_config->base.mode, | |
12381 | &pipe_config->pipe_src_w, | |
12382 | &pipe_config->pipe_src_h); | |
12383 | ||
12384 | encoder_retry: | |
12385 | /* Ensure the port clock defaults are reset when retrying. */ | |
12386 | pipe_config->port_clock = 0; | |
12387 | pipe_config->pixel_multiplier = 1; | |
12388 | ||
12389 | /* Fill in default crtc timings, allow encoders to overwrite them. */ | |
12390 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, | |
12391 | CRTC_STEREO_DOUBLE); | |
12392 | ||
12393 | /* Pass our mode to the connectors and the CRTC to give them a chance to | |
12394 | * adjust it according to limitations or connector properties, and also | |
12395 | * a chance to reject the mode entirely. | |
12396 | */ | |
12397 | for_each_connector_in_state(state, connector, connector_state, i) { | |
12398 | if (connector_state->crtc != crtc) | |
12399 | continue; | |
12400 | ||
12401 | encoder = to_intel_encoder(connector_state->best_encoder); | |
12402 | ||
12403 | if (!(encoder->compute_config(encoder, pipe_config))) { | |
12404 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
12405 | goto fail; | |
12406 | } | |
12407 | } | |
12408 | ||
12409 | /* Set default port clock if not overwritten by the encoder. Needs to be | |
12410 | * done afterwards in case the encoder adjusts the mode. */ | |
12411 | if (!pipe_config->port_clock) | |
12412 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock | |
12413 | * pipe_config->pixel_multiplier; | |
12414 | ||
12415 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); | |
12416 | if (ret < 0) { | |
12417 | DRM_DEBUG_KMS("CRTC fixup failed\n"); | |
12418 | goto fail; | |
12419 | } | |
12420 | ||
12421 | if (ret == RETRY) { | |
12422 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12423 | ret = -EINVAL; | |
12424 | goto fail; | |
12425 | } | |
12426 | ||
12427 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12428 | retry = false; | |
12429 | goto encoder_retry; | |
12430 | } | |
12431 | ||
12432 | /* Dithering seems to not pass-through bits correctly when it should, so | |
12433 | * only enable it on 6bpc panels. */ | |
12434 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
12435 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", | |
12436 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
12437 | ||
12438 | fail: | |
12439 | return ret; | |
12440 | } | |
12441 | ||
12442 | static void | |
12443 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) | |
12444 | { | |
12445 | struct drm_crtc *crtc; | |
12446 | struct drm_crtc_state *crtc_state; | |
12447 | int i; | |
12448 | ||
12449 | /* Double check state. */ | |
12450 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
12451 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); | |
12452 | ||
12453 | /* Update hwmode for vblank functions */ | |
12454 | if (crtc->state->active) | |
12455 | crtc->hwmode = crtc->state->adjusted_mode; | |
12456 | else | |
12457 | crtc->hwmode.crtc_clock = 0; | |
12458 | ||
12459 | /* | |
12460 | * Update legacy state to satisfy fbc code. This can | |
12461 | * be removed when fbc uses the atomic state. | |
12462 | */ | |
12463 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12464 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12465 | ||
12466 | crtc->primary->fb = plane_state->fb; | |
12467 | crtc->x = plane_state->src_x >> 16; | |
12468 | crtc->y = plane_state->src_y >> 16; | |
12469 | } | |
12470 | } | |
12471 | } | |
12472 | ||
12473 | static bool intel_fuzzy_clock_check(int clock1, int clock2) | |
12474 | { | |
12475 | int diff; | |
12476 | ||
12477 | if (clock1 == clock2) | |
12478 | return true; | |
12479 | ||
12480 | if (!clock1 || !clock2) | |
12481 | return false; | |
12482 | ||
12483 | diff = abs(clock1 - clock2); | |
12484 | ||
12485 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12486 | return true; | |
12487 | ||
12488 | return false; | |
12489 | } | |
12490 | ||
12491 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ | |
12492 | list_for_each_entry((intel_crtc), \ | |
12493 | &(dev)->mode_config.crtc_list, \ | |
12494 | base.head) \ | |
12495 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) | |
12496 | ||
12497 | static bool | |
12498 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12499 | unsigned int m2, unsigned int n2, | |
12500 | bool exact) | |
12501 | { | |
12502 | if (m == m2 && n == n2) | |
12503 | return true; | |
12504 | ||
12505 | if (exact || !m || !n || !m2 || !n2) | |
12506 | return false; | |
12507 | ||
12508 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12509 | ||
12510 | if (n > n2) { | |
12511 | while (n > n2) { | |
12512 | m2 <<= 1; | |
12513 | n2 <<= 1; | |
12514 | } | |
12515 | } else if (n < n2) { | |
12516 | while (n < n2) { | |
12517 | m <<= 1; | |
12518 | n <<= 1; | |
12519 | } | |
12520 | } | |
12521 | ||
12522 | if (n != n2) | |
12523 | return false; | |
12524 | ||
12525 | return intel_fuzzy_clock_check(m, m2); | |
12526 | } | |
12527 | ||
12528 | static bool | |
12529 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12530 | struct intel_link_m_n *m2_n2, | |
12531 | bool adjust) | |
12532 | { | |
12533 | if (m_n->tu == m2_n2->tu && | |
12534 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12535 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12536 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12537 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12538 | if (adjust) | |
12539 | *m2_n2 = *m_n; | |
12540 | ||
12541 | return true; | |
12542 | } | |
12543 | ||
12544 | return false; | |
12545 | } | |
12546 | ||
12547 | static bool | |
12548 | intel_pipe_config_compare(struct drm_device *dev, | |
12549 | struct intel_crtc_state *current_config, | |
12550 | struct intel_crtc_state *pipe_config, | |
12551 | bool adjust) | |
12552 | { | |
12553 | bool ret = true; | |
12554 | ||
12555 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12556 | do { \ | |
12557 | if (!adjust) \ | |
12558 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12559 | else \ | |
12560 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12561 | } while (0) | |
12562 | ||
12563 | #define PIPE_CONF_CHECK_X(name) \ | |
12564 | if (current_config->name != pipe_config->name) { \ | |
12565 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12566 | "(expected 0x%08x, found 0x%08x)\n", \ | |
12567 | current_config->name, \ | |
12568 | pipe_config->name); \ | |
12569 | ret = false; \ | |
12570 | } | |
12571 | ||
12572 | #define PIPE_CONF_CHECK_I(name) \ | |
12573 | if (current_config->name != pipe_config->name) { \ | |
12574 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12575 | "(expected %i, found %i)\n", \ | |
12576 | current_config->name, \ | |
12577 | pipe_config->name); \ | |
12578 | ret = false; \ | |
12579 | } | |
12580 | ||
12581 | #define PIPE_CONF_CHECK_P(name) \ | |
12582 | if (current_config->name != pipe_config->name) { \ | |
12583 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12584 | "(expected %p, found %p)\n", \ | |
12585 | current_config->name, \ | |
12586 | pipe_config->name); \ | |
12587 | ret = false; \ | |
12588 | } | |
12589 | ||
12590 | #define PIPE_CONF_CHECK_M_N(name) \ | |
12591 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12592 | &pipe_config->name,\ | |
12593 | adjust)) { \ | |
12594 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12595 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12596 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12597 | current_config->name.tu, \ | |
12598 | current_config->name.gmch_m, \ | |
12599 | current_config->name.gmch_n, \ | |
12600 | current_config->name.link_m, \ | |
12601 | current_config->name.link_n, \ | |
12602 | pipe_config->name.tu, \ | |
12603 | pipe_config->name.gmch_m, \ | |
12604 | pipe_config->name.gmch_n, \ | |
12605 | pipe_config->name.link_m, \ | |
12606 | pipe_config->name.link_n); \ | |
12607 | ret = false; \ | |
12608 | } | |
12609 | ||
12610 | /* This is required for BDW+ where there is only one set of registers for | |
12611 | * switching between high and low RR. | |
12612 | * This macro can be used whenever a comparison has to be made between one | |
12613 | * hw state and multiple sw state variables. | |
12614 | */ | |
12615 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ | |
12616 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12617 | &pipe_config->name, adjust) && \ | |
12618 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12619 | &pipe_config->name, adjust)) { \ | |
12620 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12621 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12622 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12623 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12624 | current_config->name.tu, \ | |
12625 | current_config->name.gmch_m, \ | |
12626 | current_config->name.gmch_n, \ | |
12627 | current_config->name.link_m, \ | |
12628 | current_config->name.link_n, \ | |
12629 | current_config->alt_name.tu, \ | |
12630 | current_config->alt_name.gmch_m, \ | |
12631 | current_config->alt_name.gmch_n, \ | |
12632 | current_config->alt_name.link_m, \ | |
12633 | current_config->alt_name.link_n, \ | |
12634 | pipe_config->name.tu, \ | |
12635 | pipe_config->name.gmch_m, \ | |
12636 | pipe_config->name.gmch_n, \ | |
12637 | pipe_config->name.link_m, \ | |
12638 | pipe_config->name.link_n); \ | |
12639 | ret = false; \ | |
12640 | } | |
12641 | ||
12642 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ | |
12643 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
12644 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ | |
12645 | "(expected %i, found %i)\n", \ | |
12646 | current_config->name & (mask), \ | |
12647 | pipe_config->name & (mask)); \ | |
12648 | ret = false; \ | |
12649 | } | |
12650 | ||
12651 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ | |
12652 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
12653 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12654 | "(expected %i, found %i)\n", \ | |
12655 | current_config->name, \ | |
12656 | pipe_config->name); \ | |
12657 | ret = false; \ | |
12658 | } | |
12659 | ||
12660 | #define PIPE_CONF_QUIRK(quirk) \ | |
12661 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12662 | ||
12663 | PIPE_CONF_CHECK_I(cpu_transcoder); | |
12664 | ||
12665 | PIPE_CONF_CHECK_I(has_pch_encoder); | |
12666 | PIPE_CONF_CHECK_I(fdi_lanes); | |
12667 | PIPE_CONF_CHECK_M_N(fdi_m_n); | |
12668 | ||
12669 | PIPE_CONF_CHECK_I(has_dp_encoder); | |
12670 | PIPE_CONF_CHECK_I(lane_count); | |
12671 | ||
12672 | if (INTEL_INFO(dev)->gen < 8) { | |
12673 | PIPE_CONF_CHECK_M_N(dp_m_n); | |
12674 | ||
12675 | if (current_config->has_drrs) | |
12676 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12677 | } else | |
12678 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
12679 | ||
12680 | PIPE_CONF_CHECK_I(has_dsi_encoder); | |
12681 | ||
12682 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); | |
12683 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12684 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12685 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12686 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12687 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
12688 | ||
12689 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); | |
12690 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12691 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12692 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12693 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12694 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
12695 | ||
12696 | PIPE_CONF_CHECK_I(pixel_multiplier); | |
12697 | PIPE_CONF_CHECK_I(has_hdmi_sink); | |
12698 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || | |
12699 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) | |
12700 | PIPE_CONF_CHECK_I(limited_color_range); | |
12701 | PIPE_CONF_CHECK_I(has_infoframe); | |
12702 | ||
12703 | PIPE_CONF_CHECK_I(has_audio); | |
12704 | ||
12705 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, | |
12706 | DRM_MODE_FLAG_INTERLACE); | |
12707 | ||
12708 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { | |
12709 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, | |
12710 | DRM_MODE_FLAG_PHSYNC); | |
12711 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, | |
12712 | DRM_MODE_FLAG_NHSYNC); | |
12713 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, | |
12714 | DRM_MODE_FLAG_PVSYNC); | |
12715 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, | |
12716 | DRM_MODE_FLAG_NVSYNC); | |
12717 | } | |
12718 | ||
12719 | PIPE_CONF_CHECK_X(gmch_pfit.control); | |
12720 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
12721 | if (INTEL_INFO(dev)->gen < 4) | |
12722 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); | |
12723 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); | |
12724 | ||
12725 | if (!adjust) { | |
12726 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12727 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12728 | ||
12729 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12730 | if (current_config->pch_pfit.enabled) { | |
12731 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12732 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12733 | } | |
12734 | ||
12735 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); | |
12736 | } | |
12737 | ||
12738 | /* BDW+ don't expose a synchronous way to read the state */ | |
12739 | if (IS_HASWELL(dev)) | |
12740 | PIPE_CONF_CHECK_I(ips_enabled); | |
12741 | ||
12742 | PIPE_CONF_CHECK_I(double_wide); | |
12743 | ||
12744 | PIPE_CONF_CHECK_X(ddi_pll_sel); | |
12745 | ||
12746 | PIPE_CONF_CHECK_P(shared_dpll); | |
12747 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); | |
12748 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); | |
12749 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); | |
12750 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
12751 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); | |
12752 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); | |
12753 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); | |
12754 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12755 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
12756 | ||
12757 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); | |
12758 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
12759 | ||
12760 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) | |
12761 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12762 | ||
12763 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); | |
12764 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); | |
12765 | ||
12766 | #undef PIPE_CONF_CHECK_X | |
12767 | #undef PIPE_CONF_CHECK_I | |
12768 | #undef PIPE_CONF_CHECK_P | |
12769 | #undef PIPE_CONF_CHECK_FLAGS | |
12770 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY | |
12771 | #undef PIPE_CONF_QUIRK | |
12772 | #undef INTEL_ERR_OR_DBG_KMS | |
12773 | ||
12774 | return ret; | |
12775 | } | |
12776 | ||
12777 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, | |
12778 | const struct intel_crtc_state *pipe_config) | |
12779 | { | |
12780 | if (pipe_config->has_pch_encoder) { | |
12781 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), | |
12782 | &pipe_config->fdi_m_n); | |
12783 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
12784 | ||
12785 | /* | |
12786 | * FDI already provided one idea for the dotclock. | |
12787 | * Yell if the encoder disagrees. | |
12788 | */ | |
12789 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
12790 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
12791 | fdi_dotclock, dotclock); | |
12792 | } | |
12793 | } | |
12794 | ||
12795 | static void verify_wm_state(struct drm_crtc *crtc, | |
12796 | struct drm_crtc_state *new_state) | |
12797 | { | |
12798 | struct drm_device *dev = crtc->dev; | |
12799 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12800 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
12801 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
12802 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12803 | const enum pipe pipe = intel_crtc->pipe; | |
12804 | int plane; | |
12805 | ||
12806 | if (INTEL_INFO(dev)->gen < 9 || !new_state->active) | |
12807 | return; | |
12808 | ||
12809 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12810 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12811 | ||
12812 | /* planes */ | |
12813 | for_each_plane(dev_priv, pipe, plane) { | |
12814 | hw_entry = &hw_ddb.plane[pipe][plane]; | |
12815 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
12816 | ||
12817 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12818 | continue; | |
12819 | ||
12820 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
12821 | "(expected (%u,%u), found (%u,%u))\n", | |
12822 | pipe_name(pipe), plane + 1, | |
12823 | sw_entry->start, sw_entry->end, | |
12824 | hw_entry->start, hw_entry->end); | |
12825 | } | |
12826 | ||
12827 | /* cursor */ | |
12828 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
12829 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
12830 | ||
12831 | if (!skl_ddb_entry_equal(hw_entry, sw_entry)) { | |
12832 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
12833 | "(expected (%u,%u), found (%u,%u))\n", | |
12834 | pipe_name(pipe), | |
12835 | sw_entry->start, sw_entry->end, | |
12836 | hw_entry->start, hw_entry->end); | |
12837 | } | |
12838 | } | |
12839 | ||
12840 | static void | |
12841 | verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc) | |
12842 | { | |
12843 | struct drm_connector *connector; | |
12844 | ||
12845 | drm_for_each_connector(connector, dev) { | |
12846 | struct drm_encoder *encoder = connector->encoder; | |
12847 | struct drm_connector_state *state = connector->state; | |
12848 | ||
12849 | if (state->crtc != crtc) | |
12850 | continue; | |
12851 | ||
12852 | intel_connector_verify_state(to_intel_connector(connector)); | |
12853 | ||
12854 | I915_STATE_WARN(state->best_encoder != encoder, | |
12855 | "connector's atomic encoder doesn't match legacy encoder\n"); | |
12856 | } | |
12857 | } | |
12858 | ||
12859 | static void | |
12860 | verify_encoder_state(struct drm_device *dev) | |
12861 | { | |
12862 | struct intel_encoder *encoder; | |
12863 | struct intel_connector *connector; | |
12864 | ||
12865 | for_each_intel_encoder(dev, encoder) { | |
12866 | bool enabled = false; | |
12867 | enum pipe pipe; | |
12868 | ||
12869 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12870 | encoder->base.base.id, | |
12871 | encoder->base.name); | |
12872 | ||
12873 | for_each_intel_connector(dev, connector) { | |
12874 | if (connector->base.state->best_encoder != &encoder->base) | |
12875 | continue; | |
12876 | enabled = true; | |
12877 | ||
12878 | I915_STATE_WARN(connector->base.state->crtc != | |
12879 | encoder->base.crtc, | |
12880 | "connector's crtc doesn't match encoder crtc\n"); | |
12881 | } | |
12882 | ||
12883 | I915_STATE_WARN(!!encoder->base.crtc != enabled, | |
12884 | "encoder's enabled state mismatch " | |
12885 | "(expected %i, found %i)\n", | |
12886 | !!encoder->base.crtc, enabled); | |
12887 | ||
12888 | if (!encoder->base.crtc) { | |
12889 | bool active; | |
12890 | ||
12891 | active = encoder->get_hw_state(encoder, &pipe); | |
12892 | I915_STATE_WARN(active, | |
12893 | "encoder detached but still enabled on pipe %c.\n", | |
12894 | pipe_name(pipe)); | |
12895 | } | |
12896 | } | |
12897 | } | |
12898 | ||
12899 | static void | |
12900 | verify_crtc_state(struct drm_crtc *crtc, | |
12901 | struct drm_crtc_state *old_crtc_state, | |
12902 | struct drm_crtc_state *new_crtc_state) | |
12903 | { | |
12904 | struct drm_device *dev = crtc->dev; | |
12905 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12906 | struct intel_encoder *encoder; | |
12907 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12908 | struct intel_crtc_state *pipe_config, *sw_config; | |
12909 | struct drm_atomic_state *old_state; | |
12910 | bool active; | |
12911 | ||
12912 | old_state = old_crtc_state->state; | |
12913 | __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); | |
12914 | pipe_config = to_intel_crtc_state(old_crtc_state); | |
12915 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
12916 | pipe_config->base.crtc = crtc; | |
12917 | pipe_config->base.state = old_state; | |
12918 | ||
12919 | DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id); | |
12920 | ||
12921 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); | |
12922 | ||
12923 | /* hw state is inconsistent with the pipe quirk */ | |
12924 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
12925 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
12926 | active = new_crtc_state->active; | |
12927 | ||
12928 | I915_STATE_WARN(new_crtc_state->active != active, | |
12929 | "crtc active state doesn't match with hw state " | |
12930 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
12931 | ||
12932 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, | |
12933 | "transitional active state does not match atomic hw state " | |
12934 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
12935 | ||
12936 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
12937 | enum pipe pipe; | |
12938 | ||
12939 | active = encoder->get_hw_state(encoder, &pipe); | |
12940 | I915_STATE_WARN(active != new_crtc_state->active, | |
12941 | "[ENCODER:%i] active %i with crtc active %i\n", | |
12942 | encoder->base.base.id, active, new_crtc_state->active); | |
12943 | ||
12944 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, | |
12945 | "Encoder connected to wrong pipe %c\n", | |
12946 | pipe_name(pipe)); | |
12947 | ||
12948 | if (active) | |
12949 | encoder->get_config(encoder, pipe_config); | |
12950 | } | |
12951 | ||
12952 | if (!new_crtc_state->active) | |
12953 | return; | |
12954 | ||
12955 | intel_pipe_config_sanity_check(dev_priv, pipe_config); | |
12956 | ||
12957 | sw_config = to_intel_crtc_state(crtc->state); | |
12958 | if (!intel_pipe_config_compare(dev, sw_config, | |
12959 | pipe_config, false)) { | |
12960 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
12961 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
12962 | "[hw state]"); | |
12963 | intel_dump_pipe_config(intel_crtc, sw_config, | |
12964 | "[sw state]"); | |
12965 | } | |
12966 | } | |
12967 | ||
12968 | static void | |
12969 | verify_single_dpll_state(struct drm_i915_private *dev_priv, | |
12970 | struct intel_shared_dpll *pll, | |
12971 | struct drm_crtc *crtc, | |
12972 | struct drm_crtc_state *new_state) | |
12973 | { | |
12974 | struct intel_dpll_hw_state dpll_hw_state; | |
12975 | unsigned crtc_mask; | |
12976 | bool active; | |
12977 | ||
12978 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
12979 | ||
12980 | DRM_DEBUG_KMS("%s\n", pll->name); | |
12981 | ||
12982 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); | |
12983 | ||
12984 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { | |
12985 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
12986 | "pll in active use but not on in sw tracking\n"); | |
12987 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
12988 | "pll is on but not used by any active crtc\n"); | |
12989 | I915_STATE_WARN(pll->on != active, | |
12990 | "pll on state mismatch (expected %i, found %i)\n", | |
12991 | pll->on, active); | |
12992 | } | |
12993 | ||
12994 | if (!crtc) { | |
12995 | I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask, | |
12996 | "more active pll users than references: %x vs %x\n", | |
12997 | pll->active_mask, pll->config.crtc_mask); | |
12998 | ||
12999 | return; | |
13000 | } | |
13001 | ||
13002 | crtc_mask = 1 << drm_crtc_index(crtc); | |
13003 | ||
13004 | if (new_state->active) | |
13005 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
13006 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
13007 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
13008 | else | |
13009 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13010 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
13011 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
13012 | ||
13013 | I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask), | |
13014 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", | |
13015 | crtc_mask, pll->config.crtc_mask); | |
13016 | ||
13017 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, | |
13018 | &dpll_hw_state, | |
13019 | sizeof(dpll_hw_state)), | |
13020 | "pll hw state mismatch\n"); | |
13021 | } | |
13022 | ||
13023 | static void | |
13024 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, | |
13025 | struct drm_crtc_state *old_crtc_state, | |
13026 | struct drm_crtc_state *new_crtc_state) | |
13027 | { | |
13028 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13029 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); | |
13030 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
13031 | ||
13032 | if (new_state->shared_dpll) | |
13033 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); | |
13034 | ||
13035 | if (old_state->shared_dpll && | |
13036 | old_state->shared_dpll != new_state->shared_dpll) { | |
13037 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
13038 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
13039 | ||
13040 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13041 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
13042 | pipe_name(drm_crtc_index(crtc))); | |
13043 | I915_STATE_WARN(pll->config.crtc_mask & crtc_mask, | |
13044 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", | |
13045 | pipe_name(drm_crtc_index(crtc))); | |
13046 | } | |
13047 | } | |
13048 | ||
13049 | static void | |
13050 | intel_modeset_verify_crtc(struct drm_crtc *crtc, | |
13051 | struct drm_crtc_state *old_state, | |
13052 | struct drm_crtc_state *new_state) | |
13053 | { | |
13054 | if (!needs_modeset(new_state) && | |
13055 | !to_intel_crtc_state(new_state)->update_pipe) | |
13056 | return; | |
13057 | ||
13058 | verify_wm_state(crtc, new_state); | |
13059 | verify_connector_state(crtc->dev, crtc); | |
13060 | verify_crtc_state(crtc, old_state, new_state); | |
13061 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
13062 | } | |
13063 | ||
13064 | static void | |
13065 | verify_disabled_dpll_state(struct drm_device *dev) | |
13066 | { | |
13067 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13068 | int i; | |
13069 | ||
13070 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
13071 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); | |
13072 | } | |
13073 | ||
13074 | static void | |
13075 | intel_modeset_verify_disabled(struct drm_device *dev) | |
13076 | { | |
13077 | verify_encoder_state(dev); | |
13078 | verify_connector_state(dev, NULL); | |
13079 | verify_disabled_dpll_state(dev); | |
13080 | } | |
13081 | ||
13082 | static void update_scanline_offset(struct intel_crtc *crtc) | |
13083 | { | |
13084 | struct drm_device *dev = crtc->base.dev; | |
13085 | ||
13086 | /* | |
13087 | * The scanline counter increments at the leading edge of hsync. | |
13088 | * | |
13089 | * On most platforms it starts counting from vtotal-1 on the | |
13090 | * first active line. That means the scanline counter value is | |
13091 | * always one less than what we would expect. Ie. just after | |
13092 | * start of vblank, which also occurs at start of hsync (on the | |
13093 | * last active line), the scanline counter will read vblank_start-1. | |
13094 | * | |
13095 | * On gen2 the scanline counter starts counting from 1 instead | |
13096 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13097 | * to keep the value positive), instead of adding one. | |
13098 | * | |
13099 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13100 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13101 | * there's an extra 1 line difference. So we need to add two instead of | |
13102 | * one to the value. | |
13103 | */ | |
13104 | if (IS_GEN2(dev)) { | |
13105 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; | |
13106 | int vtotal; | |
13107 | ||
13108 | vtotal = adjusted_mode->crtc_vtotal; | |
13109 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
13110 | vtotal /= 2; | |
13111 | ||
13112 | crtc->scanline_offset = vtotal - 1; | |
13113 | } else if (HAS_DDI(dev) && | |
13114 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { | |
13115 | crtc->scanline_offset = 2; | |
13116 | } else | |
13117 | crtc->scanline_offset = 1; | |
13118 | } | |
13119 | ||
13120 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) | |
13121 | { | |
13122 | struct drm_device *dev = state->dev; | |
13123 | struct drm_i915_private *dev_priv = to_i915(dev); | |
13124 | struct intel_shared_dpll_config *shared_dpll = NULL; | |
13125 | struct drm_crtc *crtc; | |
13126 | struct drm_crtc_state *crtc_state; | |
13127 | int i; | |
13128 | ||
13129 | if (!dev_priv->display.crtc_compute_clock) | |
13130 | return; | |
13131 | ||
13132 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13133 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13134 | struct intel_shared_dpll *old_dpll = | |
13135 | to_intel_crtc_state(crtc->state)->shared_dpll; | |
13136 | ||
13137 | if (!needs_modeset(crtc_state)) | |
13138 | continue; | |
13139 | ||
13140 | to_intel_crtc_state(crtc_state)->shared_dpll = NULL; | |
13141 | ||
13142 | if (!old_dpll) | |
13143 | continue; | |
13144 | ||
13145 | if (!shared_dpll) | |
13146 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
13147 | ||
13148 | intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc); | |
13149 | } | |
13150 | } | |
13151 | ||
13152 | /* | |
13153 | * This implements the workaround described in the "notes" section of the mode | |
13154 | * set sequence documentation. When going from no pipes or single pipe to | |
13155 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13156 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13157 | */ | |
13158 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13159 | { | |
13160 | struct drm_crtc_state *crtc_state; | |
13161 | struct intel_crtc *intel_crtc; | |
13162 | struct drm_crtc *crtc; | |
13163 | struct intel_crtc_state *first_crtc_state = NULL; | |
13164 | struct intel_crtc_state *other_crtc_state = NULL; | |
13165 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13166 | int i; | |
13167 | ||
13168 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13169 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13170 | intel_crtc = to_intel_crtc(crtc); | |
13171 | ||
13172 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13173 | continue; | |
13174 | ||
13175 | if (first_crtc_state) { | |
13176 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13177 | break; | |
13178 | } else { | |
13179 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13180 | first_pipe = intel_crtc->pipe; | |
13181 | } | |
13182 | } | |
13183 | ||
13184 | /* No workaround needed? */ | |
13185 | if (!first_crtc_state) | |
13186 | return 0; | |
13187 | ||
13188 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13189 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13190 | struct intel_crtc_state *pipe_config; | |
13191 | ||
13192 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13193 | if (IS_ERR(pipe_config)) | |
13194 | return PTR_ERR(pipe_config); | |
13195 | ||
13196 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13197 | ||
13198 | if (!pipe_config->base.active || | |
13199 | needs_modeset(&pipe_config->base)) | |
13200 | continue; | |
13201 | ||
13202 | /* 2 or more enabled crtcs means no need for w/a */ | |
13203 | if (enabled_pipe != INVALID_PIPE) | |
13204 | return 0; | |
13205 | ||
13206 | enabled_pipe = intel_crtc->pipe; | |
13207 | } | |
13208 | ||
13209 | if (enabled_pipe != INVALID_PIPE) | |
13210 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13211 | else if (other_crtc_state) | |
13212 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13213 | ||
13214 | return 0; | |
13215 | } | |
13216 | ||
13217 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) | |
13218 | { | |
13219 | struct drm_crtc *crtc; | |
13220 | struct drm_crtc_state *crtc_state; | |
13221 | int ret = 0; | |
13222 | ||
13223 | /* add all active pipes to the state */ | |
13224 | for_each_crtc(state->dev, crtc) { | |
13225 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13226 | if (IS_ERR(crtc_state)) | |
13227 | return PTR_ERR(crtc_state); | |
13228 | ||
13229 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13230 | continue; | |
13231 | ||
13232 | crtc_state->mode_changed = true; | |
13233 | ||
13234 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13235 | if (ret) | |
13236 | break; | |
13237 | ||
13238 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13239 | if (ret) | |
13240 | break; | |
13241 | } | |
13242 | ||
13243 | return ret; | |
13244 | } | |
13245 | ||
13246 | static int intel_modeset_checks(struct drm_atomic_state *state) | |
13247 | { | |
13248 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
13249 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
13250 | struct drm_crtc *crtc; | |
13251 | struct drm_crtc_state *crtc_state; | |
13252 | int ret = 0, i; | |
13253 | ||
13254 | if (!check_digital_port_conflicts(state)) { | |
13255 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13256 | return -EINVAL; | |
13257 | } | |
13258 | ||
13259 | intel_state->modeset = true; | |
13260 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13261 | ||
13262 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13263 | if (crtc_state->active) | |
13264 | intel_state->active_crtcs |= 1 << i; | |
13265 | else | |
13266 | intel_state->active_crtcs &= ~(1 << i); | |
13267 | } | |
13268 | ||
13269 | /* | |
13270 | * See if the config requires any additional preparation, e.g. | |
13271 | * to adjust global state with pipes off. We need to do this | |
13272 | * here so we can get the modeset_pipe updated config for the new | |
13273 | * mode set on this crtc. For other crtcs we need to use the | |
13274 | * adjusted_mode bits in the crtc directly. | |
13275 | */ | |
13276 | if (dev_priv->display.modeset_calc_cdclk) { | |
13277 | ret = dev_priv->display.modeset_calc_cdclk(state); | |
13278 | ||
13279 | if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq) | |
13280 | ret = intel_modeset_all_pipes(state); | |
13281 | ||
13282 | if (ret < 0) | |
13283 | return ret; | |
13284 | ||
13285 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", | |
13286 | intel_state->cdclk, intel_state->dev_cdclk); | |
13287 | } else | |
13288 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; | |
13289 | ||
13290 | intel_modeset_clear_plls(state); | |
13291 | ||
13292 | if (IS_HASWELL(dev_priv)) | |
13293 | return haswell_mode_set_planes_workaround(state); | |
13294 | ||
13295 | return 0; | |
13296 | } | |
13297 | ||
13298 | /* | |
13299 | * Handle calculation of various watermark data at the end of the atomic check | |
13300 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13301 | * handlers to ensure that all derived state has been updated. | |
13302 | */ | |
13303 | static void calc_watermark_data(struct drm_atomic_state *state) | |
13304 | { | |
13305 | struct drm_device *dev = state->dev; | |
13306 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
13307 | struct drm_crtc *crtc; | |
13308 | struct drm_crtc_state *cstate; | |
13309 | struct drm_plane *plane; | |
13310 | struct drm_plane_state *pstate; | |
13311 | ||
13312 | /* | |
13313 | * Calculate watermark configuration details now that derived | |
13314 | * plane/crtc state is all properly updated. | |
13315 | */ | |
13316 | drm_for_each_crtc(crtc, dev) { | |
13317 | cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?: | |
13318 | crtc->state; | |
13319 | ||
13320 | if (cstate->active) | |
13321 | intel_state->wm_config.num_pipes_active++; | |
13322 | } | |
13323 | drm_for_each_legacy_plane(plane, dev) { | |
13324 | pstate = drm_atomic_get_existing_plane_state(state, plane) ?: | |
13325 | plane->state; | |
13326 | ||
13327 | if (!to_intel_plane_state(pstate)->visible) | |
13328 | continue; | |
13329 | ||
13330 | intel_state->wm_config.sprites_enabled = true; | |
13331 | if (pstate->crtc_w != pstate->src_w >> 16 || | |
13332 | pstate->crtc_h != pstate->src_h >> 16) | |
13333 | intel_state->wm_config.sprites_scaled = true; | |
13334 | } | |
13335 | } | |
13336 | ||
13337 | /** | |
13338 | * intel_atomic_check - validate state object | |
13339 | * @dev: drm device | |
13340 | * @state: state to validate | |
13341 | */ | |
13342 | static int intel_atomic_check(struct drm_device *dev, | |
13343 | struct drm_atomic_state *state) | |
13344 | { | |
13345 | struct drm_i915_private *dev_priv = to_i915(dev); | |
13346 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
13347 | struct drm_crtc *crtc; | |
13348 | struct drm_crtc_state *crtc_state; | |
13349 | int ret, i; | |
13350 | bool any_ms = false; | |
13351 | ||
13352 | ret = drm_atomic_helper_check_modeset(dev, state); | |
13353 | if (ret) | |
13354 | return ret; | |
13355 | ||
13356 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13357 | struct intel_crtc_state *pipe_config = | |
13358 | to_intel_crtc_state(crtc_state); | |
13359 | ||
13360 | /* Catch I915_MODE_FLAG_INHERITED */ | |
13361 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13362 | crtc_state->mode_changed = true; | |
13363 | ||
13364 | if (!crtc_state->enable) { | |
13365 | if (needs_modeset(crtc_state)) | |
13366 | any_ms = true; | |
13367 | continue; | |
13368 | } | |
13369 | ||
13370 | if (!needs_modeset(crtc_state)) | |
13371 | continue; | |
13372 | ||
13373 | /* FIXME: For only active_changed we shouldn't need to do any | |
13374 | * state recomputation at all. */ | |
13375 | ||
13376 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13377 | if (ret) | |
13378 | return ret; | |
13379 | ||
13380 | ret = intel_modeset_pipe_config(crtc, pipe_config); | |
13381 | if (ret) { | |
13382 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
13383 | pipe_config, "[failed]"); | |
13384 | return ret; | |
13385 | } | |
13386 | ||
13387 | if (i915.fastboot && | |
13388 | intel_pipe_config_compare(dev, | |
13389 | to_intel_crtc_state(crtc->state), | |
13390 | pipe_config, true)) { | |
13391 | crtc_state->mode_changed = false; | |
13392 | to_intel_crtc_state(crtc_state)->update_pipe = true; | |
13393 | } | |
13394 | ||
13395 | if (needs_modeset(crtc_state)) { | |
13396 | any_ms = true; | |
13397 | ||
13398 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13399 | if (ret) | |
13400 | return ret; | |
13401 | } | |
13402 | ||
13403 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, | |
13404 | needs_modeset(crtc_state) ? | |
13405 | "[modeset]" : "[fastset]"); | |
13406 | } | |
13407 | ||
13408 | if (any_ms) { | |
13409 | ret = intel_modeset_checks(state); | |
13410 | ||
13411 | if (ret) | |
13412 | return ret; | |
13413 | } else | |
13414 | intel_state->cdclk = dev_priv->cdclk_freq; | |
13415 | ||
13416 | ret = drm_atomic_helper_check_planes(dev, state); | |
13417 | if (ret) | |
13418 | return ret; | |
13419 | ||
13420 | intel_fbc_choose_crtc(dev_priv, state); | |
13421 | calc_watermark_data(state); | |
13422 | ||
13423 | return 0; | |
13424 | } | |
13425 | ||
13426 | static int intel_atomic_prepare_commit(struct drm_device *dev, | |
13427 | struct drm_atomic_state *state, | |
13428 | bool async) | |
13429 | { | |
13430 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13431 | struct drm_plane_state *plane_state; | |
13432 | struct drm_crtc_state *crtc_state; | |
13433 | struct drm_plane *plane; | |
13434 | struct drm_crtc *crtc; | |
13435 | int i, ret; | |
13436 | ||
13437 | if (async) { | |
13438 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); | |
13439 | return -EINVAL; | |
13440 | } | |
13441 | ||
13442 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13443 | if (state->legacy_cursor_update) | |
13444 | continue; | |
13445 | ||
13446 | ret = intel_crtc_wait_for_pending_flips(crtc); | |
13447 | if (ret) | |
13448 | return ret; | |
13449 | ||
13450 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) | |
13451 | flush_workqueue(dev_priv->wq); | |
13452 | } | |
13453 | ||
13454 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
13455 | if (ret) | |
13456 | return ret; | |
13457 | ||
13458 | ret = drm_atomic_helper_prepare_planes(dev, state); | |
13459 | mutex_unlock(&dev->struct_mutex); | |
13460 | ||
13461 | if (!ret && !async) { | |
13462 | for_each_plane_in_state(state, plane, plane_state, i) { | |
13463 | struct intel_plane_state *intel_plane_state = | |
13464 | to_intel_plane_state(plane_state); | |
13465 | ||
13466 | if (!intel_plane_state->wait_req) | |
13467 | continue; | |
13468 | ||
13469 | ret = __i915_wait_request(intel_plane_state->wait_req, | |
13470 | true, NULL, NULL); | |
13471 | if (ret) { | |
13472 | /* Any hang should be swallowed by the wait */ | |
13473 | WARN_ON(ret == -EIO); | |
13474 | mutex_lock(&dev->struct_mutex); | |
13475 | drm_atomic_helper_cleanup_planes(dev, state); | |
13476 | mutex_unlock(&dev->struct_mutex); | |
13477 | break; | |
13478 | } | |
13479 | } | |
13480 | } | |
13481 | ||
13482 | return ret; | |
13483 | } | |
13484 | ||
13485 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, | |
13486 | struct drm_i915_private *dev_priv, | |
13487 | unsigned crtc_mask) | |
13488 | { | |
13489 | unsigned last_vblank_count[I915_MAX_PIPES]; | |
13490 | enum pipe pipe; | |
13491 | int ret; | |
13492 | ||
13493 | if (!crtc_mask) | |
13494 | return; | |
13495 | ||
13496 | for_each_pipe(dev_priv, pipe) { | |
13497 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13498 | ||
13499 | if (!((1 << pipe) & crtc_mask)) | |
13500 | continue; | |
13501 | ||
13502 | ret = drm_crtc_vblank_get(crtc); | |
13503 | if (WARN_ON(ret != 0)) { | |
13504 | crtc_mask &= ~(1 << pipe); | |
13505 | continue; | |
13506 | } | |
13507 | ||
13508 | last_vblank_count[pipe] = drm_crtc_vblank_count(crtc); | |
13509 | } | |
13510 | ||
13511 | for_each_pipe(dev_priv, pipe) { | |
13512 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13513 | long lret; | |
13514 | ||
13515 | if (!((1 << pipe) & crtc_mask)) | |
13516 | continue; | |
13517 | ||
13518 | lret = wait_event_timeout(dev->vblank[pipe].queue, | |
13519 | last_vblank_count[pipe] != | |
13520 | drm_crtc_vblank_count(crtc), | |
13521 | msecs_to_jiffies(50)); | |
13522 | ||
13523 | WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe)); | |
13524 | ||
13525 | drm_crtc_vblank_put(crtc); | |
13526 | } | |
13527 | } | |
13528 | ||
13529 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) | |
13530 | { | |
13531 | /* fb updated, need to unpin old fb */ | |
13532 | if (crtc_state->fb_changed) | |
13533 | return true; | |
13534 | ||
13535 | /* wm changes, need vblank before final wm's */ | |
13536 | if (crtc_state->update_wm_post) | |
13537 | return true; | |
13538 | ||
13539 | /* | |
13540 | * cxsr is re-enabled after vblank. | |
13541 | * This is already handled by crtc_state->update_wm_post, | |
13542 | * but added for clarity. | |
13543 | */ | |
13544 | if (crtc_state->disable_cxsr) | |
13545 | return true; | |
13546 | ||
13547 | return false; | |
13548 | } | |
13549 | ||
13550 | /** | |
13551 | * intel_atomic_commit - commit validated state object | |
13552 | * @dev: DRM device | |
13553 | * @state: the top-level driver state object | |
13554 | * @async: asynchronous commit | |
13555 | * | |
13556 | * This function commits a top-level state object that has been validated | |
13557 | * with drm_atomic_helper_check(). | |
13558 | * | |
13559 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13560 | * we can only handle plane-related operations and do not yet support | |
13561 | * asynchronous commit. | |
13562 | * | |
13563 | * RETURNS | |
13564 | * Zero for success or -errno. | |
13565 | */ | |
13566 | static int intel_atomic_commit(struct drm_device *dev, | |
13567 | struct drm_atomic_state *state, | |
13568 | bool async) | |
13569 | { | |
13570 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
13571 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13572 | struct drm_crtc_state *old_crtc_state; | |
13573 | struct drm_crtc *crtc; | |
13574 | struct intel_crtc_state *intel_cstate; | |
13575 | int ret = 0, i; | |
13576 | bool hw_check = intel_state->modeset; | |
13577 | unsigned long put_domains[I915_MAX_PIPES] = {}; | |
13578 | unsigned crtc_vblank_mask = 0; | |
13579 | ||
13580 | ret = intel_atomic_prepare_commit(dev, state, async); | |
13581 | if (ret) { | |
13582 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
13583 | return ret; | |
13584 | } | |
13585 | ||
13586 | drm_atomic_helper_swap_state(dev, state); | |
13587 | dev_priv->wm.config = intel_state->wm_config; | |
13588 | intel_shared_dpll_commit(state); | |
13589 | ||
13590 | if (intel_state->modeset) { | |
13591 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13592 | sizeof(intel_state->min_pixclk)); | |
13593 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
13594 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; | |
13595 | ||
13596 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
13597 | } | |
13598 | ||
13599 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
13600 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13601 | ||
13602 | if (needs_modeset(crtc->state) || | |
13603 | to_intel_crtc_state(crtc->state)->update_pipe) { | |
13604 | hw_check = true; | |
13605 | ||
13606 | put_domains[to_intel_crtc(crtc)->pipe] = | |
13607 | modeset_get_crtc_power_domains(crtc, | |
13608 | to_intel_crtc_state(crtc->state)); | |
13609 | } | |
13610 | ||
13611 | if (!needs_modeset(crtc->state)) | |
13612 | continue; | |
13613 | ||
13614 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); | |
13615 | ||
13616 | if (old_crtc_state->active) { | |
13617 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
13618 | dev_priv->display.crtc_disable(crtc); | |
13619 | intel_crtc->active = false; | |
13620 | intel_fbc_disable(intel_crtc); | |
13621 | intel_disable_shared_dpll(intel_crtc); | |
13622 | ||
13623 | /* | |
13624 | * Underruns don't always raise | |
13625 | * interrupts, so check manually. | |
13626 | */ | |
13627 | intel_check_cpu_fifo_underruns(dev_priv); | |
13628 | intel_check_pch_fifo_underruns(dev_priv); | |
13629 | ||
13630 | if (!crtc->state->active) | |
13631 | intel_update_watermarks(crtc); | |
13632 | } | |
13633 | } | |
13634 | ||
13635 | /* Only after disabling all output pipelines that will be changed can we | |
13636 | * update the the output configuration. */ | |
13637 | intel_modeset_update_crtc_state(state); | |
13638 | ||
13639 | if (intel_state->modeset) { | |
13640 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); | |
13641 | ||
13642 | if (dev_priv->display.modeset_commit_cdclk && | |
13643 | intel_state->dev_cdclk != dev_priv->cdclk_freq) | |
13644 | dev_priv->display.modeset_commit_cdclk(state); | |
13645 | ||
13646 | intel_modeset_verify_disabled(dev); | |
13647 | } | |
13648 | ||
13649 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
13650 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
13651 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13652 | bool modeset = needs_modeset(crtc->state); | |
13653 | struct intel_crtc_state *pipe_config = | |
13654 | to_intel_crtc_state(crtc->state); | |
13655 | bool update_pipe = !modeset && pipe_config->update_pipe; | |
13656 | ||
13657 | if (modeset && crtc->state->active) { | |
13658 | update_scanline_offset(to_intel_crtc(crtc)); | |
13659 | dev_priv->display.crtc_enable(crtc); | |
13660 | } | |
13661 | ||
13662 | if (!modeset) | |
13663 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); | |
13664 | ||
13665 | if (crtc->state->active && | |
13666 | drm_atomic_get_existing_plane_state(state, crtc->primary)) | |
13667 | intel_fbc_enable(intel_crtc); | |
13668 | ||
13669 | if (crtc->state->active && | |
13670 | (crtc->state->planes_changed || update_pipe)) | |
13671 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); | |
13672 | ||
13673 | if (pipe_config->base.active && needs_vblank_wait(pipe_config)) | |
13674 | crtc_vblank_mask |= 1 << i; | |
13675 | } | |
13676 | ||
13677 | /* FIXME: add subpixel order */ | |
13678 | ||
13679 | if (!state->legacy_cursor_update) | |
13680 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
13681 | ||
13682 | /* | |
13683 | * Now that the vblank has passed, we can go ahead and program the | |
13684 | * optimal watermarks on platforms that need two-step watermark | |
13685 | * programming. | |
13686 | * | |
13687 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
13688 | */ | |
13689 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
13690 | intel_cstate = to_intel_crtc_state(crtc->state); | |
13691 | ||
13692 | if (dev_priv->display.optimize_watermarks) | |
13693 | dev_priv->display.optimize_watermarks(intel_cstate); | |
13694 | } | |
13695 | ||
13696 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
13697 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); | |
13698 | ||
13699 | if (put_domains[i]) | |
13700 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
13701 | ||
13702 | intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state); | |
13703 | } | |
13704 | ||
13705 | if (intel_state->modeset) | |
13706 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
13707 | ||
13708 | mutex_lock(&dev->struct_mutex); | |
13709 | drm_atomic_helper_cleanup_planes(dev, state); | |
13710 | mutex_unlock(&dev->struct_mutex); | |
13711 | ||
13712 | drm_atomic_state_free(state); | |
13713 | ||
13714 | /* As one of the primary mmio accessors, KMS has a high likelihood | |
13715 | * of triggering bugs in unclaimed access. After we finish | |
13716 | * modesetting, see if an error has been flagged, and if so | |
13717 | * enable debugging for the next modeset - and hope we catch | |
13718 | * the culprit. | |
13719 | * | |
13720 | * XXX note that we assume display power is on at this point. | |
13721 | * This might hold true now but we need to add pm helper to check | |
13722 | * unclaimed only when the hardware is on, as atomic commits | |
13723 | * can happen also when the device is completely off. | |
13724 | */ | |
13725 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
13726 | ||
13727 | return 0; | |
13728 | } | |
13729 | ||
13730 | void intel_crtc_restore_mode(struct drm_crtc *crtc) | |
13731 | { | |
13732 | struct drm_device *dev = crtc->dev; | |
13733 | struct drm_atomic_state *state; | |
13734 | struct drm_crtc_state *crtc_state; | |
13735 | int ret; | |
13736 | ||
13737 | state = drm_atomic_state_alloc(dev); | |
13738 | if (!state) { | |
13739 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", | |
13740 | crtc->base.id); | |
13741 | return; | |
13742 | } | |
13743 | ||
13744 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
13745 | ||
13746 | retry: | |
13747 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13748 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13749 | if (!ret) { | |
13750 | if (!crtc_state->active) | |
13751 | goto out; | |
13752 | ||
13753 | crtc_state->mode_changed = true; | |
13754 | ret = drm_atomic_commit(state); | |
13755 | } | |
13756 | ||
13757 | if (ret == -EDEADLK) { | |
13758 | drm_atomic_state_clear(state); | |
13759 | drm_modeset_backoff(state->acquire_ctx); | |
13760 | goto retry; | |
13761 | } | |
13762 | ||
13763 | if (ret) | |
13764 | out: | |
13765 | drm_atomic_state_free(state); | |
13766 | } | |
13767 | ||
13768 | #undef for_each_intel_crtc_masked | |
13769 | ||
13770 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
13771 | .gamma_set = drm_atomic_helper_legacy_gamma_set, | |
13772 | .set_config = drm_atomic_helper_set_config, | |
13773 | .set_property = drm_atomic_helper_crtc_set_property, | |
13774 | .destroy = intel_crtc_destroy, | |
13775 | .page_flip = intel_crtc_page_flip, | |
13776 | .atomic_duplicate_state = intel_crtc_duplicate_state, | |
13777 | .atomic_destroy_state = intel_crtc_destroy_state, | |
13778 | }; | |
13779 | ||
13780 | /** | |
13781 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13782 | * @plane: drm plane to prepare for | |
13783 | * @fb: framebuffer to prepare for presentation | |
13784 | * | |
13785 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13786 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13787 | * bits. Some older platforms need special physical address handling for | |
13788 | * cursor planes. | |
13789 | * | |
13790 | * Must be called with struct_mutex held. | |
13791 | * | |
13792 | * Returns 0 on success, negative error code on failure. | |
13793 | */ | |
13794 | int | |
13795 | intel_prepare_plane_fb(struct drm_plane *plane, | |
13796 | const struct drm_plane_state *new_state) | |
13797 | { | |
13798 | struct drm_device *dev = plane->dev; | |
13799 | struct drm_framebuffer *fb = new_state->fb; | |
13800 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13801 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
13802 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); | |
13803 | int ret = 0; | |
13804 | ||
13805 | if (!obj && !old_obj) | |
13806 | return 0; | |
13807 | ||
13808 | if (old_obj) { | |
13809 | struct drm_crtc_state *crtc_state = | |
13810 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
13811 | ||
13812 | /* Big Hammer, we also need to ensure that any pending | |
13813 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
13814 | * current scanout is retired before unpinning the old | |
13815 | * framebuffer. Note that we rely on userspace rendering | |
13816 | * into the buffer attached to the pipe they are waiting | |
13817 | * on. If not, userspace generates a GPU hang with IPEHR | |
13818 | * point to the MI_WAIT_FOR_EVENT. | |
13819 | * | |
13820 | * This should only fail upon a hung GPU, in which case we | |
13821 | * can safely continue. | |
13822 | */ | |
13823 | if (needs_modeset(crtc_state)) | |
13824 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
13825 | if (ret) { | |
13826 | /* GPU hangs should have been swallowed by the wait */ | |
13827 | WARN_ON(ret == -EIO); | |
13828 | return ret; | |
13829 | } | |
13830 | } | |
13831 | ||
13832 | /* For framebuffer backed by dmabuf, wait for fence */ | |
13833 | if (obj && obj->base.dma_buf) { | |
13834 | long lret; | |
13835 | ||
13836 | lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
13837 | false, true, | |
13838 | MAX_SCHEDULE_TIMEOUT); | |
13839 | if (lret == -ERESTARTSYS) | |
13840 | return lret; | |
13841 | ||
13842 | WARN(lret < 0, "waiting returns %li\n", lret); | |
13843 | } | |
13844 | ||
13845 | if (!obj) { | |
13846 | ret = 0; | |
13847 | } else if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
13848 | INTEL_INFO(dev)->cursor_needs_physical) { | |
13849 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13850 | ret = i915_gem_object_attach_phys(obj, align); | |
13851 | if (ret) | |
13852 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13853 | } else { | |
13854 | ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation); | |
13855 | } | |
13856 | ||
13857 | if (ret == 0) { | |
13858 | if (obj) { | |
13859 | struct intel_plane_state *plane_state = | |
13860 | to_intel_plane_state(new_state); | |
13861 | ||
13862 | i915_gem_request_assign(&plane_state->wait_req, | |
13863 | obj->last_write_req); | |
13864 | } | |
13865 | ||
13866 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); | |
13867 | } | |
13868 | ||
13869 | return ret; | |
13870 | } | |
13871 | ||
13872 | /** | |
13873 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13874 | * @plane: drm plane to clean up for | |
13875 | * @fb: old framebuffer that was on plane | |
13876 | * | |
13877 | * Cleans up a framebuffer that has just been removed from a plane. | |
13878 | * | |
13879 | * Must be called with struct_mutex held. | |
13880 | */ | |
13881 | void | |
13882 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
13883 | const struct drm_plane_state *old_state) | |
13884 | { | |
13885 | struct drm_device *dev = plane->dev; | |
13886 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13887 | struct intel_plane_state *old_intel_state; | |
13888 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); | |
13889 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
13890 | ||
13891 | old_intel_state = to_intel_plane_state(old_state); | |
13892 | ||
13893 | if (!obj && !old_obj) | |
13894 | return; | |
13895 | ||
13896 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || | |
13897 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
13898 | intel_unpin_fb_obj(old_state->fb, old_state->rotation); | |
13899 | ||
13900 | /* prepare_fb aborted? */ | |
13901 | if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) || | |
13902 | (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit))) | |
13903 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); | |
13904 | ||
13905 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); | |
13906 | } | |
13907 | ||
13908 | int | |
13909 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13910 | { | |
13911 | int max_scale; | |
13912 | struct drm_device *dev; | |
13913 | struct drm_i915_private *dev_priv; | |
13914 | int crtc_clock, cdclk; | |
13915 | ||
13916 | if (!intel_crtc || !crtc_state->base.enable) | |
13917 | return DRM_PLANE_HELPER_NO_SCALING; | |
13918 | ||
13919 | dev = intel_crtc->base.dev; | |
13920 | dev_priv = dev->dev_private; | |
13921 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
13922 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; | |
13923 | ||
13924 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) | |
13925 | return DRM_PLANE_HELPER_NO_SCALING; | |
13926 | ||
13927 | /* | |
13928 | * skl max scale is lower of: | |
13929 | * close to 3 but not 3, -1 is for that purpose | |
13930 | * or | |
13931 | * cdclk/crtc_clock | |
13932 | */ | |
13933 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13934 | ||
13935 | return max_scale; | |
13936 | } | |
13937 | ||
13938 | static int | |
13939 | intel_check_primary_plane(struct drm_plane *plane, | |
13940 | struct intel_crtc_state *crtc_state, | |
13941 | struct intel_plane_state *state) | |
13942 | { | |
13943 | struct drm_crtc *crtc = state->base.crtc; | |
13944 | struct drm_framebuffer *fb = state->base.fb; | |
13945 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; | |
13946 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; | |
13947 | bool can_position = false; | |
13948 | ||
13949 | if (INTEL_INFO(plane->dev)->gen >= 9) { | |
13950 | /* use scaler when colorkey is not required */ | |
13951 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
13952 | min_scale = 1; | |
13953 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
13954 | } | |
13955 | can_position = true; | |
13956 | } | |
13957 | ||
13958 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, | |
13959 | &state->dst, &state->clip, | |
13960 | min_scale, max_scale, | |
13961 | can_position, true, | |
13962 | &state->visible); | |
13963 | } | |
13964 | ||
13965 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, | |
13966 | struct drm_crtc_state *old_crtc_state) | |
13967 | { | |
13968 | struct drm_device *dev = crtc->dev; | |
13969 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13970 | struct intel_crtc_state *old_intel_state = | |
13971 | to_intel_crtc_state(old_crtc_state); | |
13972 | bool modeset = needs_modeset(crtc->state); | |
13973 | ||
13974 | /* Perform vblank evasion around commit operation */ | |
13975 | intel_pipe_update_start(intel_crtc); | |
13976 | ||
13977 | if (modeset) | |
13978 | return; | |
13979 | ||
13980 | if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) { | |
13981 | intel_color_set_csc(crtc->state); | |
13982 | intel_color_load_luts(crtc->state); | |
13983 | } | |
13984 | ||
13985 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
13986 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
13987 | else if (INTEL_INFO(dev)->gen >= 9) | |
13988 | skl_detach_scalers(intel_crtc); | |
13989 | } | |
13990 | ||
13991 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, | |
13992 | struct drm_crtc_state *old_crtc_state) | |
13993 | { | |
13994 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13995 | ||
13996 | intel_pipe_update_end(intel_crtc); | |
13997 | } | |
13998 | ||
13999 | /** | |
14000 | * intel_plane_destroy - destroy a plane | |
14001 | * @plane: plane to destroy | |
14002 | * | |
14003 | * Common destruction function for all types of planes (primary, cursor, | |
14004 | * sprite). | |
14005 | */ | |
14006 | void intel_plane_destroy(struct drm_plane *plane) | |
14007 | { | |
14008 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
14009 | drm_plane_cleanup(plane); | |
14010 | kfree(intel_plane); | |
14011 | } | |
14012 | ||
14013 | const struct drm_plane_funcs intel_plane_funcs = { | |
14014 | .update_plane = drm_atomic_helper_update_plane, | |
14015 | .disable_plane = drm_atomic_helper_disable_plane, | |
14016 | .destroy = intel_plane_destroy, | |
14017 | .set_property = drm_atomic_helper_plane_set_property, | |
14018 | .atomic_get_property = intel_plane_atomic_get_property, | |
14019 | .atomic_set_property = intel_plane_atomic_set_property, | |
14020 | .atomic_duplicate_state = intel_plane_duplicate_state, | |
14021 | .atomic_destroy_state = intel_plane_destroy_state, | |
14022 | ||
14023 | }; | |
14024 | ||
14025 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
14026 | int pipe) | |
14027 | { | |
14028 | struct intel_plane *primary = NULL; | |
14029 | struct intel_plane_state *state = NULL; | |
14030 | const uint32_t *intel_primary_formats; | |
14031 | unsigned int num_formats; | |
14032 | int ret; | |
14033 | ||
14034 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
14035 | if (!primary) | |
14036 | goto fail; | |
14037 | ||
14038 | state = intel_create_plane_state(&primary->base); | |
14039 | if (!state) | |
14040 | goto fail; | |
14041 | primary->base.state = &state->base; | |
14042 | ||
14043 | primary->can_scale = false; | |
14044 | primary->max_downscale = 1; | |
14045 | if (INTEL_INFO(dev)->gen >= 9) { | |
14046 | primary->can_scale = true; | |
14047 | state->scaler_id = -1; | |
14048 | } | |
14049 | primary->pipe = pipe; | |
14050 | primary->plane = pipe; | |
14051 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); | |
14052 | primary->check_plane = intel_check_primary_plane; | |
14053 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) | |
14054 | primary->plane = !pipe; | |
14055 | ||
14056 | if (INTEL_INFO(dev)->gen >= 9) { | |
14057 | intel_primary_formats = skl_primary_formats; | |
14058 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
14059 | ||
14060 | primary->update_plane = skylake_update_primary_plane; | |
14061 | primary->disable_plane = skylake_disable_primary_plane; | |
14062 | } else if (HAS_PCH_SPLIT(dev)) { | |
14063 | intel_primary_formats = i965_primary_formats; | |
14064 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
14065 | ||
14066 | primary->update_plane = ironlake_update_primary_plane; | |
14067 | primary->disable_plane = i9xx_disable_primary_plane; | |
14068 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
14069 | intel_primary_formats = i965_primary_formats; | |
14070 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
14071 | ||
14072 | primary->update_plane = i9xx_update_primary_plane; | |
14073 | primary->disable_plane = i9xx_disable_primary_plane; | |
14074 | } else { | |
14075 | intel_primary_formats = i8xx_primary_formats; | |
14076 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
14077 | ||
14078 | primary->update_plane = i9xx_update_primary_plane; | |
14079 | primary->disable_plane = i9xx_disable_primary_plane; | |
14080 | } | |
14081 | ||
14082 | ret = drm_universal_plane_init(dev, &primary->base, 0, | |
14083 | &intel_plane_funcs, | |
14084 | intel_primary_formats, num_formats, | |
14085 | DRM_PLANE_TYPE_PRIMARY, NULL); | |
14086 | if (ret) | |
14087 | goto fail; | |
14088 | ||
14089 | if (INTEL_INFO(dev)->gen >= 4) | |
14090 | intel_create_rotation_property(dev, primary); | |
14091 | ||
14092 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); | |
14093 | ||
14094 | return &primary->base; | |
14095 | ||
14096 | fail: | |
14097 | kfree(state); | |
14098 | kfree(primary); | |
14099 | ||
14100 | return NULL; | |
14101 | } | |
14102 | ||
14103 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) | |
14104 | { | |
14105 | if (!dev->mode_config.rotation_property) { | |
14106 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
14107 | BIT(DRM_ROTATE_180); | |
14108 | ||
14109 | if (INTEL_INFO(dev)->gen >= 9) | |
14110 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
14111 | ||
14112 | dev->mode_config.rotation_property = | |
14113 | drm_mode_create_rotation_property(dev, flags); | |
14114 | } | |
14115 | if (dev->mode_config.rotation_property) | |
14116 | drm_object_attach_property(&plane->base.base, | |
14117 | dev->mode_config.rotation_property, | |
14118 | plane->base.state->rotation); | |
14119 | } | |
14120 | ||
14121 | static int | |
14122 | intel_check_cursor_plane(struct drm_plane *plane, | |
14123 | struct intel_crtc_state *crtc_state, | |
14124 | struct intel_plane_state *state) | |
14125 | { | |
14126 | struct drm_crtc *crtc = crtc_state->base.crtc; | |
14127 | struct drm_framebuffer *fb = state->base.fb; | |
14128 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
14129 | enum pipe pipe = to_intel_plane(plane)->pipe; | |
14130 | unsigned stride; | |
14131 | int ret; | |
14132 | ||
14133 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, | |
14134 | &state->dst, &state->clip, | |
14135 | DRM_PLANE_HELPER_NO_SCALING, | |
14136 | DRM_PLANE_HELPER_NO_SCALING, | |
14137 | true, true, &state->visible); | |
14138 | if (ret) | |
14139 | return ret; | |
14140 | ||
14141 | /* if we want to turn off the cursor ignore width and height */ | |
14142 | if (!obj) | |
14143 | return 0; | |
14144 | ||
14145 | /* Check for which cursor types we support */ | |
14146 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { | |
14147 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
14148 | state->base.crtc_w, state->base.crtc_h); | |
14149 | return -EINVAL; | |
14150 | } | |
14151 | ||
14152 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; | |
14153 | if (obj->base.size < stride * state->base.crtc_h) { | |
14154 | DRM_DEBUG_KMS("buffer is too small\n"); | |
14155 | return -ENOMEM; | |
14156 | } | |
14157 | ||
14158 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { | |
14159 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); | |
14160 | return -EINVAL; | |
14161 | } | |
14162 | ||
14163 | /* | |
14164 | * There's something wrong with the cursor on CHV pipe C. | |
14165 | * If it straddles the left edge of the screen then | |
14166 | * moving it away from the edge or disabling it often | |
14167 | * results in a pipe underrun, and often that can lead to | |
14168 | * dead pipe (constant underrun reported, and it scans | |
14169 | * out just a solid color). To recover from that, the | |
14170 | * display power well must be turned off and on again. | |
14171 | * Refuse the put the cursor into that compromised position. | |
14172 | */ | |
14173 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && | |
14174 | state->visible && state->base.crtc_x < 0) { | |
14175 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
14176 | return -EINVAL; | |
14177 | } | |
14178 | ||
14179 | return 0; | |
14180 | } | |
14181 | ||
14182 | static void | |
14183 | intel_disable_cursor_plane(struct drm_plane *plane, | |
14184 | struct drm_crtc *crtc) | |
14185 | { | |
14186 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
14187 | ||
14188 | intel_crtc->cursor_addr = 0; | |
14189 | intel_crtc_update_cursor(crtc, NULL); | |
14190 | } | |
14191 | ||
14192 | static void | |
14193 | intel_update_cursor_plane(struct drm_plane *plane, | |
14194 | const struct intel_crtc_state *crtc_state, | |
14195 | const struct intel_plane_state *state) | |
14196 | { | |
14197 | struct drm_crtc *crtc = crtc_state->base.crtc; | |
14198 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
14199 | struct drm_device *dev = plane->dev; | |
14200 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); | |
14201 | uint32_t addr; | |
14202 | ||
14203 | if (!obj) | |
14204 | addr = 0; | |
14205 | else if (!INTEL_INFO(dev)->cursor_needs_physical) | |
14206 | addr = i915_gem_obj_ggtt_offset(obj); | |
14207 | else | |
14208 | addr = obj->phys_handle->busaddr; | |
14209 | ||
14210 | intel_crtc->cursor_addr = addr; | |
14211 | intel_crtc_update_cursor(crtc, state); | |
14212 | } | |
14213 | ||
14214 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, | |
14215 | int pipe) | |
14216 | { | |
14217 | struct intel_plane *cursor = NULL; | |
14218 | struct intel_plane_state *state = NULL; | |
14219 | int ret; | |
14220 | ||
14221 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
14222 | if (!cursor) | |
14223 | goto fail; | |
14224 | ||
14225 | state = intel_create_plane_state(&cursor->base); | |
14226 | if (!state) | |
14227 | goto fail; | |
14228 | cursor->base.state = &state->base; | |
14229 | ||
14230 | cursor->can_scale = false; | |
14231 | cursor->max_downscale = 1; | |
14232 | cursor->pipe = pipe; | |
14233 | cursor->plane = pipe; | |
14234 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); | |
14235 | cursor->check_plane = intel_check_cursor_plane; | |
14236 | cursor->update_plane = intel_update_cursor_plane; | |
14237 | cursor->disable_plane = intel_disable_cursor_plane; | |
14238 | ||
14239 | ret = drm_universal_plane_init(dev, &cursor->base, 0, | |
14240 | &intel_plane_funcs, | |
14241 | intel_cursor_formats, | |
14242 | ARRAY_SIZE(intel_cursor_formats), | |
14243 | DRM_PLANE_TYPE_CURSOR, NULL); | |
14244 | if (ret) | |
14245 | goto fail; | |
14246 | ||
14247 | if (INTEL_INFO(dev)->gen >= 4) { | |
14248 | if (!dev->mode_config.rotation_property) | |
14249 | dev->mode_config.rotation_property = | |
14250 | drm_mode_create_rotation_property(dev, | |
14251 | BIT(DRM_ROTATE_0) | | |
14252 | BIT(DRM_ROTATE_180)); | |
14253 | if (dev->mode_config.rotation_property) | |
14254 | drm_object_attach_property(&cursor->base.base, | |
14255 | dev->mode_config.rotation_property, | |
14256 | state->base.rotation); | |
14257 | } | |
14258 | ||
14259 | if (INTEL_INFO(dev)->gen >=9) | |
14260 | state->scaler_id = -1; | |
14261 | ||
14262 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); | |
14263 | ||
14264 | return &cursor->base; | |
14265 | ||
14266 | fail: | |
14267 | kfree(state); | |
14268 | kfree(cursor); | |
14269 | ||
14270 | return NULL; | |
14271 | } | |
14272 | ||
14273 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, | |
14274 | struct intel_crtc_state *crtc_state) | |
14275 | { | |
14276 | int i; | |
14277 | struct intel_scaler *intel_scaler; | |
14278 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14279 | ||
14280 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14281 | intel_scaler = &scaler_state->scalers[i]; | |
14282 | intel_scaler->in_use = 0; | |
14283 | intel_scaler->mode = PS_SCALER_MODE_DYN; | |
14284 | } | |
14285 | ||
14286 | scaler_state->scaler_id = -1; | |
14287 | } | |
14288 | ||
14289 | static void intel_crtc_init(struct drm_device *dev, int pipe) | |
14290 | { | |
14291 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14292 | struct intel_crtc *intel_crtc; | |
14293 | struct intel_crtc_state *crtc_state = NULL; | |
14294 | struct drm_plane *primary = NULL; | |
14295 | struct drm_plane *cursor = NULL; | |
14296 | int ret; | |
14297 | ||
14298 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); | |
14299 | if (intel_crtc == NULL) | |
14300 | return; | |
14301 | ||
14302 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); | |
14303 | if (!crtc_state) | |
14304 | goto fail; | |
14305 | intel_crtc->config = crtc_state; | |
14306 | intel_crtc->base.state = &crtc_state->base; | |
14307 | crtc_state->base.crtc = &intel_crtc->base; | |
14308 | ||
14309 | /* initialize shared scalers */ | |
14310 | if (INTEL_INFO(dev)->gen >= 9) { | |
14311 | if (pipe == PIPE_C) | |
14312 | intel_crtc->num_scalers = 1; | |
14313 | else | |
14314 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14315 | ||
14316 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14317 | } | |
14318 | ||
14319 | primary = intel_primary_plane_create(dev, pipe); | |
14320 | if (!primary) | |
14321 | goto fail; | |
14322 | ||
14323 | cursor = intel_cursor_plane_create(dev, pipe); | |
14324 | if (!cursor) | |
14325 | goto fail; | |
14326 | ||
14327 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, | |
14328 | cursor, &intel_crtc_funcs, NULL); | |
14329 | if (ret) | |
14330 | goto fail; | |
14331 | ||
14332 | /* | |
14333 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
14334 | * is hooked to pipe B. Hence we want plane A feeding pipe B. | |
14335 | */ | |
14336 | intel_crtc->pipe = pipe; | |
14337 | intel_crtc->plane = pipe; | |
14338 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { | |
14339 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); | |
14340 | intel_crtc->plane = !pipe; | |
14341 | } | |
14342 | ||
14343 | intel_crtc->cursor_base = ~0; | |
14344 | intel_crtc->cursor_cntl = ~0; | |
14345 | intel_crtc->cursor_size = ~0; | |
14346 | ||
14347 | intel_crtc->wm.cxsr_allowed = true; | |
14348 | ||
14349 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || | |
14350 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14351 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14352 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14353 | ||
14354 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); | |
14355 | ||
14356 | intel_color_init(&intel_crtc->base); | |
14357 | ||
14358 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
14359 | return; | |
14360 | ||
14361 | fail: | |
14362 | if (primary) | |
14363 | drm_plane_cleanup(primary); | |
14364 | if (cursor) | |
14365 | drm_plane_cleanup(cursor); | |
14366 | kfree(crtc_state); | |
14367 | kfree(intel_crtc); | |
14368 | } | |
14369 | ||
14370 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) | |
14371 | { | |
14372 | struct drm_encoder *encoder = connector->base.encoder; | |
14373 | struct drm_device *dev = connector->base.dev; | |
14374 | ||
14375 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); | |
14376 | ||
14377 | if (!encoder || WARN_ON(!encoder->crtc)) | |
14378 | return INVALID_PIPE; | |
14379 | ||
14380 | return to_intel_crtc(encoder->crtc)->pipe; | |
14381 | } | |
14382 | ||
14383 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, | |
14384 | struct drm_file *file) | |
14385 | { | |
14386 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; | |
14387 | struct drm_crtc *drmmode_crtc; | |
14388 | struct intel_crtc *crtc; | |
14389 | ||
14390 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); | |
14391 | ||
14392 | if (!drmmode_crtc) { | |
14393 | DRM_ERROR("no such CRTC id\n"); | |
14394 | return -ENOENT; | |
14395 | } | |
14396 | ||
14397 | crtc = to_intel_crtc(drmmode_crtc); | |
14398 | pipe_from_crtc_id->pipe = crtc->pipe; | |
14399 | ||
14400 | return 0; | |
14401 | } | |
14402 | ||
14403 | static int intel_encoder_clones(struct intel_encoder *encoder) | |
14404 | { | |
14405 | struct drm_device *dev = encoder->base.dev; | |
14406 | struct intel_encoder *source_encoder; | |
14407 | int index_mask = 0; | |
14408 | int entry = 0; | |
14409 | ||
14410 | for_each_intel_encoder(dev, source_encoder) { | |
14411 | if (encoders_cloneable(encoder, source_encoder)) | |
14412 | index_mask |= (1 << entry); | |
14413 | ||
14414 | entry++; | |
14415 | } | |
14416 | ||
14417 | return index_mask; | |
14418 | } | |
14419 | ||
14420 | static bool has_edp_a(struct drm_device *dev) | |
14421 | { | |
14422 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14423 | ||
14424 | if (!IS_MOBILE(dev)) | |
14425 | return false; | |
14426 | ||
14427 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14428 | return false; | |
14429 | ||
14430 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) | |
14431 | return false; | |
14432 | ||
14433 | return true; | |
14434 | } | |
14435 | ||
14436 | static bool intel_crt_present(struct drm_device *dev) | |
14437 | { | |
14438 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14439 | ||
14440 | if (INTEL_INFO(dev)->gen >= 9) | |
14441 | return false; | |
14442 | ||
14443 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) | |
14444 | return false; | |
14445 | ||
14446 | if (IS_CHERRYVIEW(dev)) | |
14447 | return false; | |
14448 | ||
14449 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) | |
14450 | return false; | |
14451 | ||
14452 | /* DDI E can't be used if DDI A requires 4 lanes */ | |
14453 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
14454 | return false; | |
14455 | ||
14456 | if (!dev_priv->vbt.int_crt_support) | |
14457 | return false; | |
14458 | ||
14459 | return true; | |
14460 | } | |
14461 | ||
14462 | static void intel_setup_outputs(struct drm_device *dev) | |
14463 | { | |
14464 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14465 | struct intel_encoder *encoder; | |
14466 | bool dpd_is_edp = false; | |
14467 | ||
14468 | intel_lvds_init(dev); | |
14469 | ||
14470 | if (intel_crt_present(dev)) | |
14471 | intel_crt_init(dev); | |
14472 | ||
14473 | if (IS_BROXTON(dev)) { | |
14474 | /* | |
14475 | * FIXME: Broxton doesn't support port detection via the | |
14476 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14477 | * detect the ports. | |
14478 | */ | |
14479 | intel_ddi_init(dev, PORT_A); | |
14480 | intel_ddi_init(dev, PORT_B); | |
14481 | intel_ddi_init(dev, PORT_C); | |
14482 | ||
14483 | intel_dsi_init(dev); | |
14484 | } else if (HAS_DDI(dev)) { | |
14485 | int found; | |
14486 | ||
14487 | /* | |
14488 | * Haswell uses DDI functions to detect digital outputs. | |
14489 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14490 | * it's there. | |
14491 | */ | |
14492 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; | |
14493 | /* WaIgnoreDDIAStrap: skl */ | |
14494 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) | |
14495 | intel_ddi_init(dev, PORT_A); | |
14496 | ||
14497 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14498 | * register */ | |
14499 | found = I915_READ(SFUSE_STRAP); | |
14500 | ||
14501 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14502 | intel_ddi_init(dev, PORT_B); | |
14503 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14504 | intel_ddi_init(dev, PORT_C); | |
14505 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14506 | intel_ddi_init(dev, PORT_D); | |
14507 | /* | |
14508 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14509 | */ | |
14510 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && | |
14511 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || | |
14512 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14513 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14514 | intel_ddi_init(dev, PORT_E); | |
14515 | ||
14516 | } else if (HAS_PCH_SPLIT(dev)) { | |
14517 | int found; | |
14518 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); | |
14519 | ||
14520 | if (has_edp_a(dev)) | |
14521 | intel_dp_init(dev, DP_A, PORT_A); | |
14522 | ||
14523 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { | |
14524 | /* PCH SDVOB multiplex with HDMIB */ | |
14525 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); | |
14526 | if (!found) | |
14527 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); | |
14528 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) | |
14529 | intel_dp_init(dev, PCH_DP_B, PORT_B); | |
14530 | } | |
14531 | ||
14532 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) | |
14533 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); | |
14534 | ||
14535 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) | |
14536 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); | |
14537 | ||
14538 | if (I915_READ(PCH_DP_C) & DP_DETECTED) | |
14539 | intel_dp_init(dev, PCH_DP_C, PORT_C); | |
14540 | ||
14541 | if (I915_READ(PCH_DP_D) & DP_DETECTED) | |
14542 | intel_dp_init(dev, PCH_DP_D, PORT_D); | |
14543 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { | |
14544 | /* | |
14545 | * The DP_DETECTED bit is the latched state of the DDC | |
14546 | * SDA pin at boot. However since eDP doesn't require DDC | |
14547 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14548 | * eDP ports may have been muxed to an alternate function. | |
14549 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14550 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14551 | * detect eDP ports. | |
14552 | */ | |
14553 | if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && | |
14554 | !intel_dp_is_edp(dev, PORT_B)) | |
14555 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); | |
14556 | if (I915_READ(VLV_DP_B) & DP_DETECTED || | |
14557 | intel_dp_is_edp(dev, PORT_B)) | |
14558 | intel_dp_init(dev, VLV_DP_B, PORT_B); | |
14559 | ||
14560 | if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && | |
14561 | !intel_dp_is_edp(dev, PORT_C)) | |
14562 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); | |
14563 | if (I915_READ(VLV_DP_C) & DP_DETECTED || | |
14564 | intel_dp_is_edp(dev, PORT_C)) | |
14565 | intel_dp_init(dev, VLV_DP_C, PORT_C); | |
14566 | ||
14567 | if (IS_CHERRYVIEW(dev)) { | |
14568 | /* eDP not supported on port D, so don't check VBT */ | |
14569 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED) | |
14570 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
14571 | if (I915_READ(CHV_DP_D) & DP_DETECTED) | |
14572 | intel_dp_init(dev, CHV_DP_D, PORT_D); | |
14573 | } | |
14574 | ||
14575 | intel_dsi_init(dev); | |
14576 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { | |
14577 | bool found = false; | |
14578 | ||
14579 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { | |
14580 | DRM_DEBUG_KMS("probing SDVOB\n"); | |
14581 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); | |
14582 | if (!found && IS_G4X(dev)) { | |
14583 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
14584 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); | |
14585 | } | |
14586 | ||
14587 | if (!found && IS_G4X(dev)) | |
14588 | intel_dp_init(dev, DP_B, PORT_B); | |
14589 | } | |
14590 | ||
14591 | /* Before G4X SDVOC doesn't have its own detect register */ | |
14592 | ||
14593 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { | |
14594 | DRM_DEBUG_KMS("probing SDVOC\n"); | |
14595 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); | |
14596 | } | |
14597 | ||
14598 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { | |
14599 | ||
14600 | if (IS_G4X(dev)) { | |
14601 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
14602 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); | |
14603 | } | |
14604 | if (IS_G4X(dev)) | |
14605 | intel_dp_init(dev, DP_C, PORT_C); | |
14606 | } | |
14607 | ||
14608 | if (IS_G4X(dev) && | |
14609 | (I915_READ(DP_D) & DP_DETECTED)) | |
14610 | intel_dp_init(dev, DP_D, PORT_D); | |
14611 | } else if (IS_GEN2(dev)) | |
14612 | intel_dvo_init(dev); | |
14613 | ||
14614 | if (SUPPORTS_TV(dev)) | |
14615 | intel_tv_init(dev); | |
14616 | ||
14617 | intel_psr_init(dev); | |
14618 | ||
14619 | for_each_intel_encoder(dev, encoder) { | |
14620 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
14621 | encoder->base.possible_clones = | |
14622 | intel_encoder_clones(encoder); | |
14623 | } | |
14624 | ||
14625 | intel_init_pch_refclk(dev); | |
14626 | ||
14627 | drm_helper_move_panel_connectors_to_head(dev); | |
14628 | } | |
14629 | ||
14630 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14631 | { | |
14632 | struct drm_device *dev = fb->dev; | |
14633 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14634 | ||
14635 | drm_framebuffer_cleanup(fb); | |
14636 | mutex_lock(&dev->struct_mutex); | |
14637 | WARN_ON(!intel_fb->obj->framebuffer_references--); | |
14638 | drm_gem_object_unreference(&intel_fb->obj->base); | |
14639 | mutex_unlock(&dev->struct_mutex); | |
14640 | kfree(intel_fb); | |
14641 | } | |
14642 | ||
14643 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
14644 | struct drm_file *file, | |
14645 | unsigned int *handle) | |
14646 | { | |
14647 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14648 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14649 | ||
14650 | if (obj->userptr.mm) { | |
14651 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14652 | return -EINVAL; | |
14653 | } | |
14654 | ||
14655 | return drm_gem_handle_create(file, &obj->base, handle); | |
14656 | } | |
14657 | ||
14658 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, | |
14659 | struct drm_file *file, | |
14660 | unsigned flags, unsigned color, | |
14661 | struct drm_clip_rect *clips, | |
14662 | unsigned num_clips) | |
14663 | { | |
14664 | struct drm_device *dev = fb->dev; | |
14665 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14666 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14667 | ||
14668 | mutex_lock(&dev->struct_mutex); | |
14669 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); | |
14670 | mutex_unlock(&dev->struct_mutex); | |
14671 | ||
14672 | return 0; | |
14673 | } | |
14674 | ||
14675 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
14676 | .destroy = intel_user_framebuffer_destroy, | |
14677 | .create_handle = intel_user_framebuffer_create_handle, | |
14678 | .dirty = intel_user_framebuffer_dirty, | |
14679 | }; | |
14680 | ||
14681 | static | |
14682 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14683 | uint32_t pixel_format) | |
14684 | { | |
14685 | u32 gen = INTEL_INFO(dev)->gen; | |
14686 | ||
14687 | if (gen >= 9) { | |
14688 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
14689 | ||
14690 | /* "The stride in bytes must not exceed the of the size of 8K | |
14691 | * pixels and 32K bytes." | |
14692 | */ | |
14693 | return min(8192 * cpp, 32768); | |
14694 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { | |
14695 | return 32*1024; | |
14696 | } else if (gen >= 4) { | |
14697 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14698 | return 16*1024; | |
14699 | else | |
14700 | return 32*1024; | |
14701 | } else if (gen >= 3) { | |
14702 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14703 | return 8*1024; | |
14704 | else | |
14705 | return 16*1024; | |
14706 | } else { | |
14707 | /* XXX DSPC is limited to 4k tiled */ | |
14708 | return 8*1024; | |
14709 | } | |
14710 | } | |
14711 | ||
14712 | static int intel_framebuffer_init(struct drm_device *dev, | |
14713 | struct intel_framebuffer *intel_fb, | |
14714 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14715 | struct drm_i915_gem_object *obj) | |
14716 | { | |
14717 | struct drm_i915_private *dev_priv = to_i915(dev); | |
14718 | unsigned int aligned_height; | |
14719 | int ret; | |
14720 | u32 pitch_limit, stride_alignment; | |
14721 | ||
14722 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
14723 | ||
14724 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { | |
14725 | /* Enforce that fb modifier and tiling mode match, but only for | |
14726 | * X-tiled. This is needed for FBC. */ | |
14727 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14728 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14729 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14730 | return -EINVAL; | |
14731 | } | |
14732 | } else { | |
14733 | if (obj->tiling_mode == I915_TILING_X) | |
14734 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14735 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14736 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14737 | return -EINVAL; | |
14738 | } | |
14739 | } | |
14740 | ||
14741 | /* Passed in modifier sanity checking. */ | |
14742 | switch (mode_cmd->modifier[0]) { | |
14743 | case I915_FORMAT_MOD_Y_TILED: | |
14744 | case I915_FORMAT_MOD_Yf_TILED: | |
14745 | if (INTEL_INFO(dev)->gen < 9) { | |
14746 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14747 | mode_cmd->modifier[0]); | |
14748 | return -EINVAL; | |
14749 | } | |
14750 | case DRM_FORMAT_MOD_NONE: | |
14751 | case I915_FORMAT_MOD_X_TILED: | |
14752 | break; | |
14753 | default: | |
14754 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", | |
14755 | mode_cmd->modifier[0]); | |
14756 | return -EINVAL; | |
14757 | } | |
14758 | ||
14759 | stride_alignment = intel_fb_stride_alignment(dev_priv, | |
14760 | mode_cmd->modifier[0], | |
14761 | mode_cmd->pixel_format); | |
14762 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14763 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14764 | mode_cmd->pitches[0], stride_alignment); | |
14765 | return -EINVAL; | |
14766 | } | |
14767 | ||
14768 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], | |
14769 | mode_cmd->pixel_format); | |
14770 | if (mode_cmd->pitches[0] > pitch_limit) { | |
14771 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", | |
14772 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
14773 | "tiled" : "linear", | |
14774 | mode_cmd->pitches[0], pitch_limit); | |
14775 | return -EINVAL; | |
14776 | } | |
14777 | ||
14778 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && | |
14779 | mode_cmd->pitches[0] != obj->stride) { | |
14780 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14781 | mode_cmd->pitches[0], obj->stride); | |
14782 | return -EINVAL; | |
14783 | } | |
14784 | ||
14785 | /* Reject formats not supported by any plane early. */ | |
14786 | switch (mode_cmd->pixel_format) { | |
14787 | case DRM_FORMAT_C8: | |
14788 | case DRM_FORMAT_RGB565: | |
14789 | case DRM_FORMAT_XRGB8888: | |
14790 | case DRM_FORMAT_ARGB8888: | |
14791 | break; | |
14792 | case DRM_FORMAT_XRGB1555: | |
14793 | if (INTEL_INFO(dev)->gen > 3) { | |
14794 | DRM_DEBUG("unsupported pixel format: %s\n", | |
14795 | drm_get_format_name(mode_cmd->pixel_format)); | |
14796 | return -EINVAL; | |
14797 | } | |
14798 | break; | |
14799 | case DRM_FORMAT_ABGR8888: | |
14800 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && | |
14801 | INTEL_INFO(dev)->gen < 9) { | |
14802 | DRM_DEBUG("unsupported pixel format: %s\n", | |
14803 | drm_get_format_name(mode_cmd->pixel_format)); | |
14804 | return -EINVAL; | |
14805 | } | |
14806 | break; | |
14807 | case DRM_FORMAT_XBGR8888: | |
14808 | case DRM_FORMAT_XRGB2101010: | |
14809 | case DRM_FORMAT_XBGR2101010: | |
14810 | if (INTEL_INFO(dev)->gen < 4) { | |
14811 | DRM_DEBUG("unsupported pixel format: %s\n", | |
14812 | drm_get_format_name(mode_cmd->pixel_format)); | |
14813 | return -EINVAL; | |
14814 | } | |
14815 | break; | |
14816 | case DRM_FORMAT_ABGR2101010: | |
14817 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { | |
14818 | DRM_DEBUG("unsupported pixel format: %s\n", | |
14819 | drm_get_format_name(mode_cmd->pixel_format)); | |
14820 | return -EINVAL; | |
14821 | } | |
14822 | break; | |
14823 | case DRM_FORMAT_YUYV: | |
14824 | case DRM_FORMAT_UYVY: | |
14825 | case DRM_FORMAT_YVYU: | |
14826 | case DRM_FORMAT_VYUY: | |
14827 | if (INTEL_INFO(dev)->gen < 5) { | |
14828 | DRM_DEBUG("unsupported pixel format: %s\n", | |
14829 | drm_get_format_name(mode_cmd->pixel_format)); | |
14830 | return -EINVAL; | |
14831 | } | |
14832 | break; | |
14833 | default: | |
14834 | DRM_DEBUG("unsupported pixel format: %s\n", | |
14835 | drm_get_format_name(mode_cmd->pixel_format)); | |
14836 | return -EINVAL; | |
14837 | } | |
14838 | ||
14839 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ | |
14840 | if (mode_cmd->offsets[0] != 0) | |
14841 | return -EINVAL; | |
14842 | ||
14843 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, | |
14844 | mode_cmd->pixel_format, | |
14845 | mode_cmd->modifier[0]); | |
14846 | /* FIXME drm helper for size checks (especially planar formats)? */ | |
14847 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14848 | return -EINVAL; | |
14849 | ||
14850 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); | |
14851 | intel_fb->obj = obj; | |
14852 | ||
14853 | intel_fill_fb_info(dev_priv, &intel_fb->base); | |
14854 | ||
14855 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); | |
14856 | if (ret) { | |
14857 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14858 | return ret; | |
14859 | } | |
14860 | ||
14861 | intel_fb->obj->framebuffer_references++; | |
14862 | ||
14863 | return 0; | |
14864 | } | |
14865 | ||
14866 | static struct drm_framebuffer * | |
14867 | intel_user_framebuffer_create(struct drm_device *dev, | |
14868 | struct drm_file *filp, | |
14869 | const struct drm_mode_fb_cmd2 *user_mode_cmd) | |
14870 | { | |
14871 | struct drm_framebuffer *fb; | |
14872 | struct drm_i915_gem_object *obj; | |
14873 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; | |
14874 | ||
14875 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, | |
14876 | mode_cmd.handles[0])); | |
14877 | if (&obj->base == NULL) | |
14878 | return ERR_PTR(-ENOENT); | |
14879 | ||
14880 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); | |
14881 | if (IS_ERR(fb)) | |
14882 | drm_gem_object_unreference_unlocked(&obj->base); | |
14883 | ||
14884 | return fb; | |
14885 | } | |
14886 | ||
14887 | #ifndef CONFIG_DRM_FBDEV_EMULATION | |
14888 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) | |
14889 | { | |
14890 | } | |
14891 | #endif | |
14892 | ||
14893 | static const struct drm_mode_config_funcs intel_mode_funcs = { | |
14894 | .fb_create = intel_user_framebuffer_create, | |
14895 | .output_poll_changed = intel_fbdev_output_poll_changed, | |
14896 | .atomic_check = intel_atomic_check, | |
14897 | .atomic_commit = intel_atomic_commit, | |
14898 | .atomic_state_alloc = intel_atomic_state_alloc, | |
14899 | .atomic_state_clear = intel_atomic_state_clear, | |
14900 | }; | |
14901 | ||
14902 | /** | |
14903 | * intel_init_display_hooks - initialize the display modesetting hooks | |
14904 | * @dev_priv: device private | |
14905 | */ | |
14906 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
14907 | { | |
14908 | if (INTEL_INFO(dev_priv)->gen >= 9) { | |
14909 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
14910 | dev_priv->display.get_initial_plane_config = | |
14911 | skylake_get_initial_plane_config; | |
14912 | dev_priv->display.crtc_compute_clock = | |
14913 | haswell_crtc_compute_clock; | |
14914 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14915 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
14916 | } else if (HAS_DDI(dev_priv)) { | |
14917 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
14918 | dev_priv->display.get_initial_plane_config = | |
14919 | ironlake_get_initial_plane_config; | |
14920 | dev_priv->display.crtc_compute_clock = | |
14921 | haswell_crtc_compute_clock; | |
14922 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14923 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
14924 | } else if (HAS_PCH_SPLIT(dev_priv)) { | |
14925 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; | |
14926 | dev_priv->display.get_initial_plane_config = | |
14927 | ironlake_get_initial_plane_config; | |
14928 | dev_priv->display.crtc_compute_clock = | |
14929 | ironlake_crtc_compute_clock; | |
14930 | dev_priv->display.crtc_enable = ironlake_crtc_enable; | |
14931 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
14932 | } else if (IS_CHERRYVIEW(dev_priv)) { | |
14933 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14934 | dev_priv->display.get_initial_plane_config = | |
14935 | i9xx_get_initial_plane_config; | |
14936 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; | |
14937 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
14938 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14939 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
14940 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14941 | dev_priv->display.get_initial_plane_config = | |
14942 | i9xx_get_initial_plane_config; | |
14943 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
14944 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
14945 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14946 | } else if (IS_G4X(dev_priv)) { | |
14947 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14948 | dev_priv->display.get_initial_plane_config = | |
14949 | i9xx_get_initial_plane_config; | |
14950 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
14951 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14952 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14953 | } else if (IS_PINEVIEW(dev_priv)) { | |
14954 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14955 | dev_priv->display.get_initial_plane_config = | |
14956 | i9xx_get_initial_plane_config; | |
14957 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
14958 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14959 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14960 | } else if (!IS_GEN2(dev_priv)) { | |
14961 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14962 | dev_priv->display.get_initial_plane_config = | |
14963 | i9xx_get_initial_plane_config; | |
14964 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; | |
14965 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14966 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14967 | } else { | |
14968 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14969 | dev_priv->display.get_initial_plane_config = | |
14970 | i9xx_get_initial_plane_config; | |
14971 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
14972 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14973 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14974 | } | |
14975 | ||
14976 | /* Returns the core display clock speed */ | |
14977 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) | |
14978 | dev_priv->display.get_display_clock_speed = | |
14979 | skylake_get_display_clock_speed; | |
14980 | else if (IS_BROXTON(dev_priv)) | |
14981 | dev_priv->display.get_display_clock_speed = | |
14982 | broxton_get_display_clock_speed; | |
14983 | else if (IS_BROADWELL(dev_priv)) | |
14984 | dev_priv->display.get_display_clock_speed = | |
14985 | broadwell_get_display_clock_speed; | |
14986 | else if (IS_HASWELL(dev_priv)) | |
14987 | dev_priv->display.get_display_clock_speed = | |
14988 | haswell_get_display_clock_speed; | |
14989 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
14990 | dev_priv->display.get_display_clock_speed = | |
14991 | valleyview_get_display_clock_speed; | |
14992 | else if (IS_GEN5(dev_priv)) | |
14993 | dev_priv->display.get_display_clock_speed = | |
14994 | ilk_get_display_clock_speed; | |
14995 | else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) || | |
14996 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
14997 | dev_priv->display.get_display_clock_speed = | |
14998 | i945_get_display_clock_speed; | |
14999 | else if (IS_GM45(dev_priv)) | |
15000 | dev_priv->display.get_display_clock_speed = | |
15001 | gm45_get_display_clock_speed; | |
15002 | else if (IS_CRESTLINE(dev_priv)) | |
15003 | dev_priv->display.get_display_clock_speed = | |
15004 | i965gm_get_display_clock_speed; | |
15005 | else if (IS_PINEVIEW(dev_priv)) | |
15006 | dev_priv->display.get_display_clock_speed = | |
15007 | pnv_get_display_clock_speed; | |
15008 | else if (IS_G33(dev_priv) || IS_G4X(dev_priv)) | |
15009 | dev_priv->display.get_display_clock_speed = | |
15010 | g33_get_display_clock_speed; | |
15011 | else if (IS_I915G(dev_priv)) | |
15012 | dev_priv->display.get_display_clock_speed = | |
15013 | i915_get_display_clock_speed; | |
15014 | else if (IS_I945GM(dev_priv) || IS_845G(dev_priv)) | |
15015 | dev_priv->display.get_display_clock_speed = | |
15016 | i9xx_misc_get_display_clock_speed; | |
15017 | else if (IS_I915GM(dev_priv)) | |
15018 | dev_priv->display.get_display_clock_speed = | |
15019 | i915gm_get_display_clock_speed; | |
15020 | else if (IS_I865G(dev_priv)) | |
15021 | dev_priv->display.get_display_clock_speed = | |
15022 | i865_get_display_clock_speed; | |
15023 | else if (IS_I85X(dev_priv)) | |
15024 | dev_priv->display.get_display_clock_speed = | |
15025 | i85x_get_display_clock_speed; | |
15026 | else { /* 830 */ | |
15027 | WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n"); | |
15028 | dev_priv->display.get_display_clock_speed = | |
15029 | i830_get_display_clock_speed; | |
15030 | } | |
15031 | ||
15032 | if (IS_GEN5(dev_priv)) { | |
15033 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; | |
15034 | } else if (IS_GEN6(dev_priv)) { | |
15035 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
15036 | } else if (IS_IVYBRIDGE(dev_priv)) { | |
15037 | /* FIXME: detect B0+ stepping and use auto training */ | |
15038 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
15039 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { | |
15040 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; | |
15041 | if (IS_BROADWELL(dev_priv)) { | |
15042 | dev_priv->display.modeset_commit_cdclk = | |
15043 | broadwell_modeset_commit_cdclk; | |
15044 | dev_priv->display.modeset_calc_cdclk = | |
15045 | broadwell_modeset_calc_cdclk; | |
15046 | } | |
15047 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
15048 | dev_priv->display.modeset_commit_cdclk = | |
15049 | valleyview_modeset_commit_cdclk; | |
15050 | dev_priv->display.modeset_calc_cdclk = | |
15051 | valleyview_modeset_calc_cdclk; | |
15052 | } else if (IS_BROXTON(dev_priv)) { | |
15053 | dev_priv->display.modeset_commit_cdclk = | |
15054 | broxton_modeset_commit_cdclk; | |
15055 | dev_priv->display.modeset_calc_cdclk = | |
15056 | broxton_modeset_calc_cdclk; | |
15057 | } | |
15058 | ||
15059 | switch (INTEL_INFO(dev_priv)->gen) { | |
15060 | case 2: | |
15061 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
15062 | break; | |
15063 | ||
15064 | case 3: | |
15065 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
15066 | break; | |
15067 | ||
15068 | case 4: | |
15069 | case 5: | |
15070 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
15071 | break; | |
15072 | ||
15073 | case 6: | |
15074 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
15075 | break; | |
15076 | case 7: | |
15077 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ | |
15078 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
15079 | break; | |
15080 | case 9: | |
15081 | /* Drop through - unsupported since execlist only. */ | |
15082 | default: | |
15083 | /* Default just returns -ENODEV to indicate unsupported */ | |
15084 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
15085 | } | |
15086 | } | |
15087 | ||
15088 | /* | |
15089 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
15090 | * resume, or other times. This quirk makes sure that's the case for | |
15091 | * affected systems. | |
15092 | */ | |
15093 | static void quirk_pipea_force(struct drm_device *dev) | |
15094 | { | |
15095 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15096 | ||
15097 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
15098 | DRM_INFO("applying pipe a force quirk\n"); | |
15099 | } | |
15100 | ||
15101 | static void quirk_pipeb_force(struct drm_device *dev) | |
15102 | { | |
15103 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15104 | ||
15105 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
15106 | DRM_INFO("applying pipe b force quirk\n"); | |
15107 | } | |
15108 | ||
15109 | /* | |
15110 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
15111 | */ | |
15112 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
15113 | { | |
15114 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15115 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
15116 | DRM_INFO("applying lvds SSC disable quirk\n"); | |
15117 | } | |
15118 | ||
15119 | /* | |
15120 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight | |
15121 | * brightness value | |
15122 | */ | |
15123 | static void quirk_invert_brightness(struct drm_device *dev) | |
15124 | { | |
15125 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15126 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
15127 | DRM_INFO("applying inverted panel brightness quirk\n"); | |
15128 | } | |
15129 | ||
15130 | /* Some VBT's incorrectly indicate no backlight is present */ | |
15131 | static void quirk_backlight_present(struct drm_device *dev) | |
15132 | { | |
15133 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15134 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
15135 | DRM_INFO("applying backlight present quirk\n"); | |
15136 | } | |
15137 | ||
15138 | struct intel_quirk { | |
15139 | int device; | |
15140 | int subsystem_vendor; | |
15141 | int subsystem_device; | |
15142 | void (*hook)(struct drm_device *dev); | |
15143 | }; | |
15144 | ||
15145 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ | |
15146 | struct intel_dmi_quirk { | |
15147 | void (*hook)(struct drm_device *dev); | |
15148 | const struct dmi_system_id (*dmi_id_list)[]; | |
15149 | }; | |
15150 | ||
15151 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
15152 | { | |
15153 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
15154 | return 1; | |
15155 | } | |
15156 | ||
15157 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
15158 | { | |
15159 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
15160 | { | |
15161 | .callback = intel_dmi_reverse_brightness, | |
15162 | .ident = "NCR Corporation", | |
15163 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
15164 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
15165 | }, | |
15166 | }, | |
15167 | { } /* terminating entry */ | |
15168 | }, | |
15169 | .hook = quirk_invert_brightness, | |
15170 | }, | |
15171 | }; | |
15172 | ||
15173 | static struct intel_quirk intel_quirks[] = { | |
15174 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ | |
15175 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
15176 | ||
15177 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ | |
15178 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
15179 | ||
15180 | /* 830 needs to leave pipe A & dpll A up */ | |
15181 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
15182 | ||
15183 | /* 830 needs to leave pipe B & dpll B up */ | |
15184 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
15185 | ||
15186 | /* Lenovo U160 cannot use SSC on LVDS */ | |
15187 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
15188 | ||
15189 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
15190 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
15191 | ||
15192 | /* Acer Aspire 5734Z must invert backlight brightness */ | |
15193 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
15194 | ||
15195 | /* Acer/eMachines G725 */ | |
15196 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
15197 | ||
15198 | /* Acer/eMachines e725 */ | |
15199 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15200 | ||
15201 | /* Acer/Packard Bell NCL20 */ | |
15202 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15203 | ||
15204 | /* Acer Aspire 4736Z */ | |
15205 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
15206 | ||
15207 | /* Acer Aspire 5336 */ | |
15208 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
15209 | ||
15210 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15211 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
15212 | ||
15213 | /* Acer C720 Chromebook (Core i3 4005U) */ | |
15214 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15215 | ||
15216 | /* Apple Macbook 2,1 (Core 2 T7400) */ | |
15217 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15218 | ||
15219 | /* Apple Macbook 4,1 */ | |
15220 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15221 | ||
15222 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ | |
15223 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
15224 | ||
15225 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15226 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
15227 | ||
15228 | /* Dell Chromebook 11 */ | |
15229 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
15230 | ||
15231 | /* Dell Chromebook 11 (2015 version) */ | |
15232 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
15233 | }; | |
15234 | ||
15235 | static void intel_init_quirks(struct drm_device *dev) | |
15236 | { | |
15237 | struct pci_dev *d = dev->pdev; | |
15238 | int i; | |
15239 | ||
15240 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15241 | struct intel_quirk *q = &intel_quirks[i]; | |
15242 | ||
15243 | if (d->device == q->device && | |
15244 | (d->subsystem_vendor == q->subsystem_vendor || | |
15245 | q->subsystem_vendor == PCI_ANY_ID) && | |
15246 | (d->subsystem_device == q->subsystem_device || | |
15247 | q->subsystem_device == PCI_ANY_ID)) | |
15248 | q->hook(dev); | |
15249 | } | |
15250 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { | |
15251 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15252 | intel_dmi_quirks[i].hook(dev); | |
15253 | } | |
15254 | } | |
15255 | ||
15256 | /* Disable the VGA plane that we never use */ | |
15257 | static void i915_disable_vga(struct drm_device *dev) | |
15258 | { | |
15259 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15260 | u8 sr1; | |
15261 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); | |
15262 | ||
15263 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ | |
15264 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15265 | outb(SR01, VGA_SR_INDEX); | |
15266 | sr1 = inb(VGA_SR_DATA); | |
15267 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15268 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15269 | udelay(300); | |
15270 | ||
15271 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
15272 | POSTING_READ(vga_reg); | |
15273 | } | |
15274 | ||
15275 | void intel_modeset_init_hw(struct drm_device *dev) | |
15276 | { | |
15277 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15278 | ||
15279 | intel_update_cdclk(dev); | |
15280 | ||
15281 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
15282 | ||
15283 | intel_init_clock_gating(dev); | |
15284 | intel_enable_gt_powersave(dev); | |
15285 | } | |
15286 | ||
15287 | /* | |
15288 | * Calculate what we think the watermarks should be for the state we've read | |
15289 | * out of the hardware and then immediately program those watermarks so that | |
15290 | * we ensure the hardware settings match our internal state. | |
15291 | * | |
15292 | * We can calculate what we think WM's should be by creating a duplicate of the | |
15293 | * current state (which was constructed during hardware readout) and running it | |
15294 | * through the atomic check code to calculate new watermark values in the | |
15295 | * state object. | |
15296 | */ | |
15297 | static void sanitize_watermarks(struct drm_device *dev) | |
15298 | { | |
15299 | struct drm_i915_private *dev_priv = to_i915(dev); | |
15300 | struct drm_atomic_state *state; | |
15301 | struct drm_crtc *crtc; | |
15302 | struct drm_crtc_state *cstate; | |
15303 | struct drm_modeset_acquire_ctx ctx; | |
15304 | int ret; | |
15305 | int i; | |
15306 | ||
15307 | /* Only supported on platforms that use atomic watermark design */ | |
15308 | if (!dev_priv->display.optimize_watermarks) | |
15309 | return; | |
15310 | ||
15311 | /* | |
15312 | * We need to hold connection_mutex before calling duplicate_state so | |
15313 | * that the connector loop is protected. | |
15314 | */ | |
15315 | drm_modeset_acquire_init(&ctx, 0); | |
15316 | retry: | |
15317 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
15318 | if (ret == -EDEADLK) { | |
15319 | drm_modeset_backoff(&ctx); | |
15320 | goto retry; | |
15321 | } else if (WARN_ON(ret)) { | |
15322 | goto fail; | |
15323 | } | |
15324 | ||
15325 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
15326 | if (WARN_ON(IS_ERR(state))) | |
15327 | goto fail; | |
15328 | ||
15329 | /* | |
15330 | * Hardware readout is the only time we don't want to calculate | |
15331 | * intermediate watermarks (since we don't trust the current | |
15332 | * watermarks). | |
15333 | */ | |
15334 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
15335 | ||
15336 | ret = intel_atomic_check(dev, state); | |
15337 | if (ret) { | |
15338 | /* | |
15339 | * If we fail here, it means that the hardware appears to be | |
15340 | * programmed in a way that shouldn't be possible, given our | |
15341 | * understanding of watermark requirements. This might mean a | |
15342 | * mistake in the hardware readout code or a mistake in the | |
15343 | * watermark calculations for a given platform. Raise a WARN | |
15344 | * so that this is noticeable. | |
15345 | * | |
15346 | * If this actually happens, we'll have to just leave the | |
15347 | * BIOS-programmed watermarks untouched and hope for the best. | |
15348 | */ | |
15349 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
15350 | goto fail; | |
15351 | } | |
15352 | ||
15353 | /* Write calculated watermark values back */ | |
15354 | to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config; | |
15355 | for_each_crtc_in_state(state, crtc, cstate, i) { | |
15356 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
15357 | ||
15358 | cs->wm.need_postvbl_update = true; | |
15359 | dev_priv->display.optimize_watermarks(cs); | |
15360 | } | |
15361 | ||
15362 | drm_atomic_state_free(state); | |
15363 | fail: | |
15364 | drm_modeset_drop_locks(&ctx); | |
15365 | drm_modeset_acquire_fini(&ctx); | |
15366 | } | |
15367 | ||
15368 | void intel_modeset_init(struct drm_device *dev) | |
15369 | { | |
15370 | struct drm_i915_private *dev_priv = to_i915(dev); | |
15371 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
15372 | int sprite, ret; | |
15373 | enum pipe pipe; | |
15374 | struct intel_crtc *crtc; | |
15375 | ||
15376 | drm_mode_config_init(dev); | |
15377 | ||
15378 | dev->mode_config.min_width = 0; | |
15379 | dev->mode_config.min_height = 0; | |
15380 | ||
15381 | dev->mode_config.preferred_depth = 24; | |
15382 | dev->mode_config.prefer_shadow = 1; | |
15383 | ||
15384 | dev->mode_config.allow_fb_modifiers = true; | |
15385 | ||
15386 | dev->mode_config.funcs = &intel_mode_funcs; | |
15387 | ||
15388 | intel_init_quirks(dev); | |
15389 | ||
15390 | intel_init_pm(dev); | |
15391 | ||
15392 | if (INTEL_INFO(dev)->num_pipes == 0) | |
15393 | return; | |
15394 | ||
15395 | /* | |
15396 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15397 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15398 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15399 | * indicates as much. | |
15400 | */ | |
15401 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
15402 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15403 | DREF_SSC1_ENABLE); | |
15404 | ||
15405 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15406 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15407 | bios_lvds_use_ssc ? "en" : "dis", | |
15408 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15409 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15410 | } | |
15411 | } | |
15412 | ||
15413 | if (IS_GEN2(dev)) { | |
15414 | dev->mode_config.max_width = 2048; | |
15415 | dev->mode_config.max_height = 2048; | |
15416 | } else if (IS_GEN3(dev)) { | |
15417 | dev->mode_config.max_width = 4096; | |
15418 | dev->mode_config.max_height = 4096; | |
15419 | } else { | |
15420 | dev->mode_config.max_width = 8192; | |
15421 | dev->mode_config.max_height = 8192; | |
15422 | } | |
15423 | ||
15424 | if (IS_845G(dev) || IS_I865G(dev)) { | |
15425 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15426 | dev->mode_config.cursor_height = 1023; | |
15427 | } else if (IS_GEN2(dev)) { | |
15428 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; | |
15429 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15430 | } else { | |
15431 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15432 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15433 | } | |
15434 | ||
15435 | dev->mode_config.fb_base = ggtt->mappable_base; | |
15436 | ||
15437 | DRM_DEBUG_KMS("%d display pipe%s available.\n", | |
15438 | INTEL_INFO(dev)->num_pipes, | |
15439 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
15440 | ||
15441 | for_each_pipe(dev_priv, pipe) { | |
15442 | intel_crtc_init(dev, pipe); | |
15443 | for_each_sprite(dev_priv, pipe, sprite) { | |
15444 | ret = intel_plane_init(dev, pipe, sprite); | |
15445 | if (ret) | |
15446 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", | |
15447 | pipe_name(pipe), sprite_name(pipe, sprite), ret); | |
15448 | } | |
15449 | } | |
15450 | ||
15451 | intel_update_czclk(dev_priv); | |
15452 | intel_update_cdclk(dev); | |
15453 | ||
15454 | intel_shared_dpll_init(dev); | |
15455 | ||
15456 | /* Just disable it once at startup */ | |
15457 | i915_disable_vga(dev); | |
15458 | intel_setup_outputs(dev); | |
15459 | ||
15460 | drm_modeset_lock_all(dev); | |
15461 | intel_modeset_setup_hw_state(dev); | |
15462 | drm_modeset_unlock_all(dev); | |
15463 | ||
15464 | for_each_intel_crtc(dev, crtc) { | |
15465 | struct intel_initial_plane_config plane_config = {}; | |
15466 | ||
15467 | if (!crtc->active) | |
15468 | continue; | |
15469 | ||
15470 | /* | |
15471 | * Note that reserving the BIOS fb up front prevents us | |
15472 | * from stuffing other stolen allocations like the ring | |
15473 | * on top. This prevents some ugliness at boot time, and | |
15474 | * can even allow for smooth boot transitions if the BIOS | |
15475 | * fb is large enough for the active pipe configuration. | |
15476 | */ | |
15477 | dev_priv->display.get_initial_plane_config(crtc, | |
15478 | &plane_config); | |
15479 | ||
15480 | /* | |
15481 | * If the fb is shared between multiple heads, we'll | |
15482 | * just get the first one. | |
15483 | */ | |
15484 | intel_find_initial_plane_obj(crtc, &plane_config); | |
15485 | } | |
15486 | ||
15487 | /* | |
15488 | * Make sure hardware watermarks really match the state we read out. | |
15489 | * Note that we need to do this after reconstructing the BIOS fb's | |
15490 | * since the watermark calculation done here will use pstate->fb. | |
15491 | */ | |
15492 | sanitize_watermarks(dev); | |
15493 | } | |
15494 | ||
15495 | static void intel_enable_pipe_a(struct drm_device *dev) | |
15496 | { | |
15497 | struct intel_connector *connector; | |
15498 | struct drm_connector *crt = NULL; | |
15499 | struct intel_load_detect_pipe load_detect_temp; | |
15500 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; | |
15501 | ||
15502 | /* We can't just switch on the pipe A, we need to set things up with a | |
15503 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15504 | * by enabling the load detect pipe once. */ | |
15505 | for_each_intel_connector(dev, connector) { | |
15506 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
15507 | crt = &connector->base; | |
15508 | break; | |
15509 | } | |
15510 | } | |
15511 | ||
15512 | if (!crt) | |
15513 | return; | |
15514 | ||
15515 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) | |
15516 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); | |
15517 | } | |
15518 | ||
15519 | static bool | |
15520 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15521 | { | |
15522 | struct drm_device *dev = crtc->base.dev; | |
15523 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15524 | u32 val; | |
15525 | ||
15526 | if (INTEL_INFO(dev)->num_pipes == 1) | |
15527 | return true; | |
15528 | ||
15529 | val = I915_READ(DSPCNTR(!crtc->plane)); | |
15530 | ||
15531 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15532 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15533 | return false; | |
15534 | ||
15535 | return true; | |
15536 | } | |
15537 | ||
15538 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) | |
15539 | { | |
15540 | struct drm_device *dev = crtc->base.dev; | |
15541 | struct intel_encoder *encoder; | |
15542 | ||
15543 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15544 | return true; | |
15545 | ||
15546 | return false; | |
15547 | } | |
15548 | ||
15549 | static bool intel_encoder_has_connectors(struct intel_encoder *encoder) | |
15550 | { | |
15551 | struct drm_device *dev = encoder->base.dev; | |
15552 | struct intel_connector *connector; | |
15553 | ||
15554 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
15555 | return true; | |
15556 | ||
15557 | return false; | |
15558 | } | |
15559 | ||
15560 | static void intel_sanitize_crtc(struct intel_crtc *crtc) | |
15561 | { | |
15562 | struct drm_device *dev = crtc->base.dev; | |
15563 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15564 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; | |
15565 | ||
15566 | /* Clear any frame start delays used for debugging left by the BIOS */ | |
15567 | if (!transcoder_is_dsi(cpu_transcoder)) { | |
15568 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
15569 | ||
15570 | I915_WRITE(reg, | |
15571 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
15572 | } | |
15573 | ||
15574 | /* restore vblank interrupts to correct state */ | |
15575 | drm_crtc_vblank_reset(&crtc->base); | |
15576 | if (crtc->active) { | |
15577 | struct intel_plane *plane; | |
15578 | ||
15579 | drm_crtc_vblank_on(&crtc->base); | |
15580 | ||
15581 | /* Disable everything but the primary plane */ | |
15582 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15583 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15584 | continue; | |
15585 | ||
15586 | plane->disable_plane(&plane->base, &crtc->base); | |
15587 | } | |
15588 | } | |
15589 | ||
15590 | /* We need to sanitize the plane -> pipe mapping first because this will | |
15591 | * disable the crtc (and hence change the state) if it is wrong. Note | |
15592 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15593 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
15594 | bool plane; | |
15595 | ||
15596 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", | |
15597 | crtc->base.base.id); | |
15598 | ||
15599 | /* Pipe has the wrong plane attached and the plane is active. | |
15600 | * Temporarily change the plane mapping and disable everything | |
15601 | * ... */ | |
15602 | plane = crtc->plane; | |
15603 | to_intel_plane_state(crtc->base.primary->state)->visible = true; | |
15604 | crtc->plane = !plane; | |
15605 | intel_crtc_disable_noatomic(&crtc->base); | |
15606 | crtc->plane = plane; | |
15607 | } | |
15608 | ||
15609 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && | |
15610 | crtc->pipe == PIPE_A && !crtc->active) { | |
15611 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15612 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15613 | * call below we restore the pipe to the right state, but leave | |
15614 | * the required bits on. */ | |
15615 | intel_enable_pipe_a(dev); | |
15616 | } | |
15617 | ||
15618 | /* Adjust the state of the output pipe according to whether we | |
15619 | * have active connectors/encoders. */ | |
15620 | if (crtc->active && !intel_crtc_has_encoders(crtc)) | |
15621 | intel_crtc_disable_noatomic(&crtc->base); | |
15622 | ||
15623 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { | |
15624 | /* | |
15625 | * We start out with underrun reporting disabled to avoid races. | |
15626 | * For correct bookkeeping mark this on active crtcs. | |
15627 | * | |
15628 | * Also on gmch platforms we dont have any hardware bits to | |
15629 | * disable the underrun reporting. Which means we need to start | |
15630 | * out with underrun reporting disabled also on inactive pipes, | |
15631 | * since otherwise we'll complain about the garbage we read when | |
15632 | * e.g. coming up after runtime pm. | |
15633 | * | |
15634 | * No protection against concurrent access is required - at | |
15635 | * worst a fifo underrun happens which also sets this to false. | |
15636 | */ | |
15637 | crtc->cpu_fifo_underrun_disabled = true; | |
15638 | crtc->pch_fifo_underrun_disabled = true; | |
15639 | } | |
15640 | } | |
15641 | ||
15642 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15643 | { | |
15644 | struct intel_connector *connector; | |
15645 | struct drm_device *dev = encoder->base.dev; | |
15646 | ||
15647 | /* We need to check both for a crtc link (meaning that the | |
15648 | * encoder is active and trying to read from a pipe) and the | |
15649 | * pipe itself being active. */ | |
15650 | bool has_active_crtc = encoder->base.crtc && | |
15651 | to_intel_crtc(encoder->base.crtc)->active; | |
15652 | ||
15653 | if (intel_encoder_has_connectors(encoder) && !has_active_crtc) { | |
15654 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
15655 | encoder->base.base.id, | |
15656 | encoder->base.name); | |
15657 | ||
15658 | /* Connector is active, but has no active pipe. This is | |
15659 | * fallout from our resume register restoring. Disable | |
15660 | * the encoder manually again. */ | |
15661 | if (encoder->base.crtc) { | |
15662 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15663 | encoder->base.base.id, | |
15664 | encoder->base.name); | |
15665 | encoder->disable(encoder); | |
15666 | if (encoder->post_disable) | |
15667 | encoder->post_disable(encoder); | |
15668 | } | |
15669 | encoder->base.crtc = NULL; | |
15670 | ||
15671 | /* Inconsistent output/port/pipe state happens presumably due to | |
15672 | * a bug in one of the get_hw_state functions. Or someplace else | |
15673 | * in our code, like the register restore mess on resume. Clamp | |
15674 | * things to off as a safer default. */ | |
15675 | for_each_intel_connector(dev, connector) { | |
15676 | if (connector->encoder != encoder) | |
15677 | continue; | |
15678 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15679 | connector->base.encoder = NULL; | |
15680 | } | |
15681 | } | |
15682 | /* Enabled encoders without active connectors will be fixed in | |
15683 | * the crtc fixup. */ | |
15684 | } | |
15685 | ||
15686 | void i915_redisable_vga_power_on(struct drm_device *dev) | |
15687 | { | |
15688 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15689 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); | |
15690 | ||
15691 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { | |
15692 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15693 | i915_disable_vga(dev); | |
15694 | } | |
15695 | } | |
15696 | ||
15697 | void i915_redisable_vga(struct drm_device *dev) | |
15698 | { | |
15699 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15700 | ||
15701 | /* This function can be called both from intel_modeset_setup_hw_state or | |
15702 | * at a very early point in our resume sequence, where the power well | |
15703 | * structures are not yet restored. Since this function is at a very | |
15704 | * paranoid "someone might have enabled VGA while we were not looking" | |
15705 | * level, just check if the power well is enabled instead of trying to | |
15706 | * follow the "don't touch the power well if we don't need it" policy | |
15707 | * the rest of the driver uses. */ | |
15708 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) | |
15709 | return; | |
15710 | ||
15711 | i915_redisable_vga_power_on(dev); | |
15712 | ||
15713 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
15714 | } | |
15715 | ||
15716 | static bool primary_get_hw_state(struct intel_plane *plane) | |
15717 | { | |
15718 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); | |
15719 | ||
15720 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; | |
15721 | } | |
15722 | ||
15723 | /* FIXME read out full plane state for all planes */ | |
15724 | static void readout_plane_state(struct intel_crtc *crtc) | |
15725 | { | |
15726 | struct drm_plane *primary = crtc->base.primary; | |
15727 | struct intel_plane_state *plane_state = | |
15728 | to_intel_plane_state(primary->state); | |
15729 | ||
15730 | plane_state->visible = crtc->active && | |
15731 | primary_get_hw_state(to_intel_plane(primary)); | |
15732 | ||
15733 | if (plane_state->visible) | |
15734 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
15735 | } | |
15736 | ||
15737 | static void intel_modeset_readout_hw_state(struct drm_device *dev) | |
15738 | { | |
15739 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15740 | enum pipe pipe; | |
15741 | struct intel_crtc *crtc; | |
15742 | struct intel_encoder *encoder; | |
15743 | struct intel_connector *connector; | |
15744 | int i; | |
15745 | ||
15746 | dev_priv->active_crtcs = 0; | |
15747 | ||
15748 | for_each_intel_crtc(dev, crtc) { | |
15749 | struct intel_crtc_state *crtc_state = crtc->config; | |
15750 | int pixclk = 0; | |
15751 | ||
15752 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base); | |
15753 | memset(crtc_state, 0, sizeof(*crtc_state)); | |
15754 | crtc_state->base.crtc = &crtc->base; | |
15755 | ||
15756 | crtc_state->base.active = crtc_state->base.enable = | |
15757 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
15758 | ||
15759 | crtc->base.enabled = crtc_state->base.enable; | |
15760 | crtc->active = crtc_state->base.active; | |
15761 | ||
15762 | if (crtc_state->base.active) { | |
15763 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
15764 | ||
15765 | if (IS_BROADWELL(dev_priv)) { | |
15766 | pixclk = ilk_pipe_pixel_rate(crtc_state); | |
15767 | ||
15768 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
15769 | if (crtc_state->ips_enabled) | |
15770 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
15771 | } else if (IS_VALLEYVIEW(dev_priv) || | |
15772 | IS_CHERRYVIEW(dev_priv) || | |
15773 | IS_BROXTON(dev_priv)) | |
15774 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; | |
15775 | else | |
15776 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
15777 | } | |
15778 | ||
15779 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
15780 | ||
15781 | readout_plane_state(crtc); | |
15782 | ||
15783 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15784 | crtc->base.base.id, | |
15785 | crtc->active ? "enabled" : "disabled"); | |
15786 | } | |
15787 | ||
15788 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
15789 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15790 | ||
15791 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, | |
15792 | &pll->config.hw_state); | |
15793 | pll->config.crtc_mask = 0; | |
15794 | for_each_intel_crtc(dev, crtc) { | |
15795 | if (crtc->active && crtc->config->shared_dpll == pll) | |
15796 | pll->config.crtc_mask |= 1 << crtc->pipe; | |
15797 | } | |
15798 | pll->active_mask = pll->config.crtc_mask; | |
15799 | ||
15800 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", | |
15801 | pll->name, pll->config.crtc_mask, pll->on); | |
15802 | } | |
15803 | ||
15804 | for_each_intel_encoder(dev, encoder) { | |
15805 | pipe = 0; | |
15806 | ||
15807 | if (encoder->get_hw_state(encoder, &pipe)) { | |
15808 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
15809 | encoder->base.crtc = &crtc->base; | |
15810 | encoder->get_config(encoder, crtc->config); | |
15811 | } else { | |
15812 | encoder->base.crtc = NULL; | |
15813 | } | |
15814 | ||
15815 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", | |
15816 | encoder->base.base.id, | |
15817 | encoder->base.name, | |
15818 | encoder->base.crtc ? "enabled" : "disabled", | |
15819 | pipe_name(pipe)); | |
15820 | } | |
15821 | ||
15822 | for_each_intel_connector(dev, connector) { | |
15823 | if (connector->get_hw_state(connector)) { | |
15824 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
15825 | ||
15826 | encoder = connector->encoder; | |
15827 | connector->base.encoder = &encoder->base; | |
15828 | ||
15829 | if (encoder->base.crtc && | |
15830 | encoder->base.crtc->state->active) { | |
15831 | /* | |
15832 | * This has to be done during hardware readout | |
15833 | * because anything calling .crtc_disable may | |
15834 | * rely on the connector_mask being accurate. | |
15835 | */ | |
15836 | encoder->base.crtc->state->connector_mask |= | |
15837 | 1 << drm_connector_index(&connector->base); | |
15838 | encoder->base.crtc->state->encoder_mask |= | |
15839 | 1 << drm_encoder_index(&encoder->base); | |
15840 | } | |
15841 | ||
15842 | } else { | |
15843 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15844 | connector->base.encoder = NULL; | |
15845 | } | |
15846 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15847 | connector->base.base.id, | |
15848 | connector->base.name, | |
15849 | connector->base.encoder ? "enabled" : "disabled"); | |
15850 | } | |
15851 | ||
15852 | for_each_intel_crtc(dev, crtc) { | |
15853 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
15854 | ||
15855 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
15856 | if (crtc->base.state->active) { | |
15857 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
15858 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
15859 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
15860 | ||
15861 | /* | |
15862 | * The initial mode needs to be set in order to keep | |
15863 | * the atomic core happy. It wants a valid mode if the | |
15864 | * crtc's enabled, so we do the above call. | |
15865 | * | |
15866 | * At this point some state updated by the connectors | |
15867 | * in their ->detect() callback has not run yet, so | |
15868 | * no recalculation can be done yet. | |
15869 | * | |
15870 | * Even if we could do a recalculation and modeset | |
15871 | * right now it would cause a double modeset if | |
15872 | * fbdev or userspace chooses a different initial mode. | |
15873 | * | |
15874 | * If that happens, someone indicated they wanted a | |
15875 | * mode change, which means it's safe to do a full | |
15876 | * recalculation. | |
15877 | */ | |
15878 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
15879 | ||
15880 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
15881 | update_scanline_offset(crtc); | |
15882 | } | |
15883 | ||
15884 | intel_pipe_config_sanity_check(dev_priv, crtc->config); | |
15885 | } | |
15886 | } | |
15887 | ||
15888 | /* Scan out the current hw modeset state, | |
15889 | * and sanitizes it to the current state | |
15890 | */ | |
15891 | static void | |
15892 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
15893 | { | |
15894 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15895 | enum pipe pipe; | |
15896 | struct intel_crtc *crtc; | |
15897 | struct intel_encoder *encoder; | |
15898 | int i; | |
15899 | ||
15900 | intel_modeset_readout_hw_state(dev); | |
15901 | ||
15902 | /* HW state is read out, now we need to sanitize this mess. */ | |
15903 | for_each_intel_encoder(dev, encoder) { | |
15904 | intel_sanitize_encoder(encoder); | |
15905 | } | |
15906 | ||
15907 | for_each_pipe(dev_priv, pipe) { | |
15908 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
15909 | intel_sanitize_crtc(crtc); | |
15910 | intel_dump_pipe_config(crtc, crtc->config, | |
15911 | "[setup_hw_state]"); | |
15912 | } | |
15913 | ||
15914 | intel_modeset_update_connector_atomic_state(dev); | |
15915 | ||
15916 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
15917 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15918 | ||
15919 | if (!pll->on || pll->active_mask) | |
15920 | continue; | |
15921 | ||
15922 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15923 | ||
15924 | pll->funcs.disable(dev_priv, pll); | |
15925 | pll->on = false; | |
15926 | } | |
15927 | ||
15928 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) | |
15929 | vlv_wm_get_hw_state(dev); | |
15930 | else if (IS_GEN9(dev)) | |
15931 | skl_wm_get_hw_state(dev); | |
15932 | else if (HAS_PCH_SPLIT(dev)) | |
15933 | ilk_wm_get_hw_state(dev); | |
15934 | ||
15935 | for_each_intel_crtc(dev, crtc) { | |
15936 | unsigned long put_domains; | |
15937 | ||
15938 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); | |
15939 | if (WARN_ON(put_domains)) | |
15940 | modeset_put_power_domains(dev_priv, put_domains); | |
15941 | } | |
15942 | intel_display_set_init_power(dev_priv, false); | |
15943 | ||
15944 | intel_fbc_init_pipe_state(dev_priv); | |
15945 | } | |
15946 | ||
15947 | void intel_display_resume(struct drm_device *dev) | |
15948 | { | |
15949 | struct drm_i915_private *dev_priv = to_i915(dev); | |
15950 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
15951 | struct drm_modeset_acquire_ctx ctx; | |
15952 | int ret; | |
15953 | bool setup = false; | |
15954 | ||
15955 | dev_priv->modeset_restore_state = NULL; | |
15956 | ||
15957 | /* | |
15958 | * This is a cludge because with real atomic modeset mode_config.mutex | |
15959 | * won't be taken. Unfortunately some probed state like | |
15960 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
15961 | * it here for now. | |
15962 | */ | |
15963 | mutex_lock(&dev->mode_config.mutex); | |
15964 | drm_modeset_acquire_init(&ctx, 0); | |
15965 | ||
15966 | retry: | |
15967 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
15968 | ||
15969 | if (ret == 0 && !setup) { | |
15970 | setup = true; | |
15971 | ||
15972 | intel_modeset_setup_hw_state(dev); | |
15973 | i915_redisable_vga(dev); | |
15974 | } | |
15975 | ||
15976 | if (ret == 0 && state) { | |
15977 | struct drm_crtc_state *crtc_state; | |
15978 | struct drm_crtc *crtc; | |
15979 | int i; | |
15980 | ||
15981 | state->acquire_ctx = &ctx; | |
15982 | ||
15983 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
15984 | /* | |
15985 | * Force recalculation even if we restore | |
15986 | * current state. With fast modeset this may not result | |
15987 | * in a modeset when the state is compatible. | |
15988 | */ | |
15989 | crtc_state->mode_changed = true; | |
15990 | } | |
15991 | ||
15992 | ret = drm_atomic_commit(state); | |
15993 | } | |
15994 | ||
15995 | if (ret == -EDEADLK) { | |
15996 | drm_modeset_backoff(&ctx); | |
15997 | goto retry; | |
15998 | } | |
15999 | ||
16000 | drm_modeset_drop_locks(&ctx); | |
16001 | drm_modeset_acquire_fini(&ctx); | |
16002 | mutex_unlock(&dev->mode_config.mutex); | |
16003 | ||
16004 | if (ret) { | |
16005 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
16006 | drm_atomic_state_free(state); | |
16007 | } | |
16008 | } | |
16009 | ||
16010 | void intel_modeset_gem_init(struct drm_device *dev) | |
16011 | { | |
16012 | struct drm_crtc *c; | |
16013 | struct drm_i915_gem_object *obj; | |
16014 | int ret; | |
16015 | ||
16016 | intel_init_gt_powersave(dev); | |
16017 | ||
16018 | intel_modeset_init_hw(dev); | |
16019 | ||
16020 | intel_setup_overlay(dev); | |
16021 | ||
16022 | /* | |
16023 | * Make sure any fbs we allocated at startup are properly | |
16024 | * pinned & fenced. When we do the allocation it's too early | |
16025 | * for this. | |
16026 | */ | |
16027 | for_each_crtc(dev, c) { | |
16028 | obj = intel_fb_obj(c->primary->fb); | |
16029 | if (obj == NULL) | |
16030 | continue; | |
16031 | ||
16032 | mutex_lock(&dev->struct_mutex); | |
16033 | ret = intel_pin_and_fence_fb_obj(c->primary->fb, | |
16034 | c->primary->state->rotation); | |
16035 | mutex_unlock(&dev->struct_mutex); | |
16036 | if (ret) { | |
16037 | DRM_ERROR("failed to pin boot fb on pipe %d\n", | |
16038 | to_intel_crtc(c)->pipe); | |
16039 | drm_framebuffer_unreference(c->primary->fb); | |
16040 | c->primary->fb = NULL; | |
16041 | c->primary->crtc = c->primary->state->crtc = NULL; | |
16042 | update_state_fb(c->primary); | |
16043 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); | |
16044 | } | |
16045 | } | |
16046 | ||
16047 | intel_backlight_register(dev); | |
16048 | } | |
16049 | ||
16050 | void intel_connector_unregister(struct intel_connector *intel_connector) | |
16051 | { | |
16052 | struct drm_connector *connector = &intel_connector->base; | |
16053 | ||
16054 | intel_panel_destroy_backlight(connector); | |
16055 | drm_connector_unregister(connector); | |
16056 | } | |
16057 | ||
16058 | void intel_modeset_cleanup(struct drm_device *dev) | |
16059 | { | |
16060 | struct drm_i915_private *dev_priv = dev->dev_private; | |
16061 | struct intel_connector *connector; | |
16062 | ||
16063 | intel_disable_gt_powersave(dev); | |
16064 | ||
16065 | intel_backlight_unregister(dev); | |
16066 | ||
16067 | /* | |
16068 | * Interrupts and polling as the first thing to avoid creating havoc. | |
16069 | * Too much stuff here (turning of connectors, ...) would | |
16070 | * experience fancy races otherwise. | |
16071 | */ | |
16072 | intel_irq_uninstall(dev_priv); | |
16073 | ||
16074 | /* | |
16075 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
16076 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
16077 | */ | |
16078 | drm_kms_helper_poll_fini(dev); | |
16079 | ||
16080 | intel_unregister_dsm_handler(); | |
16081 | ||
16082 | intel_fbc_global_disable(dev_priv); | |
16083 | ||
16084 | /* flush any delayed tasks or pending work */ | |
16085 | flush_scheduled_work(); | |
16086 | ||
16087 | /* destroy the backlight and sysfs files before encoders/connectors */ | |
16088 | for_each_intel_connector(dev, connector) | |
16089 | connector->unregister(connector); | |
16090 | ||
16091 | drm_mode_config_cleanup(dev); | |
16092 | ||
16093 | intel_cleanup_overlay(dev); | |
16094 | ||
16095 | intel_cleanup_gt_powersave(dev); | |
16096 | ||
16097 | intel_teardown_gmbus(dev); | |
16098 | } | |
16099 | ||
16100 | /* | |
16101 | * Return which encoder is currently attached for connector. | |
16102 | */ | |
16103 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) | |
16104 | { | |
16105 | return &intel_attached_encoder(connector)->base; | |
16106 | } | |
16107 | ||
16108 | void intel_connector_attach_encoder(struct intel_connector *connector, | |
16109 | struct intel_encoder *encoder) | |
16110 | { | |
16111 | connector->encoder = encoder; | |
16112 | drm_mode_connector_attach_encoder(&connector->base, | |
16113 | &encoder->base); | |
16114 | } | |
16115 | ||
16116 | /* | |
16117 | * set vga decode state - true == enable VGA decode | |
16118 | */ | |
16119 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
16120 | { | |
16121 | struct drm_i915_private *dev_priv = dev->dev_private; | |
16122 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; | |
16123 | u16 gmch_ctrl; | |
16124 | ||
16125 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { | |
16126 | DRM_ERROR("failed to read control word\n"); | |
16127 | return -EIO; | |
16128 | } | |
16129 | ||
16130 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) | |
16131 | return 0; | |
16132 | ||
16133 | if (state) | |
16134 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
16135 | else | |
16136 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
16137 | ||
16138 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
16139 | DRM_ERROR("failed to write control word\n"); | |
16140 | return -EIO; | |
16141 | } | |
16142 | ||
16143 | return 0; | |
16144 | } | |
16145 | ||
16146 | struct intel_display_error_state { | |
16147 | ||
16148 | u32 power_well_driver; | |
16149 | ||
16150 | int num_transcoders; | |
16151 | ||
16152 | struct intel_cursor_error_state { | |
16153 | u32 control; | |
16154 | u32 position; | |
16155 | u32 base; | |
16156 | u32 size; | |
16157 | } cursor[I915_MAX_PIPES]; | |
16158 | ||
16159 | struct intel_pipe_error_state { | |
16160 | bool power_domain_on; | |
16161 | u32 source; | |
16162 | u32 stat; | |
16163 | } pipe[I915_MAX_PIPES]; | |
16164 | ||
16165 | struct intel_plane_error_state { | |
16166 | u32 control; | |
16167 | u32 stride; | |
16168 | u32 size; | |
16169 | u32 pos; | |
16170 | u32 addr; | |
16171 | u32 surface; | |
16172 | u32 tile_offset; | |
16173 | } plane[I915_MAX_PIPES]; | |
16174 | ||
16175 | struct intel_transcoder_error_state { | |
16176 | bool power_domain_on; | |
16177 | enum transcoder cpu_transcoder; | |
16178 | ||
16179 | u32 conf; | |
16180 | ||
16181 | u32 htotal; | |
16182 | u32 hblank; | |
16183 | u32 hsync; | |
16184 | u32 vtotal; | |
16185 | u32 vblank; | |
16186 | u32 vsync; | |
16187 | } transcoder[4]; | |
16188 | }; | |
16189 | ||
16190 | struct intel_display_error_state * | |
16191 | intel_display_capture_error_state(struct drm_device *dev) | |
16192 | { | |
16193 | struct drm_i915_private *dev_priv = dev->dev_private; | |
16194 | struct intel_display_error_state *error; | |
16195 | int transcoders[] = { | |
16196 | TRANSCODER_A, | |
16197 | TRANSCODER_B, | |
16198 | TRANSCODER_C, | |
16199 | TRANSCODER_EDP, | |
16200 | }; | |
16201 | int i; | |
16202 | ||
16203 | if (INTEL_INFO(dev)->num_pipes == 0) | |
16204 | return NULL; | |
16205 | ||
16206 | error = kzalloc(sizeof(*error), GFP_ATOMIC); | |
16207 | if (error == NULL) | |
16208 | return NULL; | |
16209 | ||
16210 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
16211 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); | |
16212 | ||
16213 | for_each_pipe(dev_priv, i) { | |
16214 | error->pipe[i].power_domain_on = | |
16215 | __intel_display_power_is_enabled(dev_priv, | |
16216 | POWER_DOMAIN_PIPE(i)); | |
16217 | if (!error->pipe[i].power_domain_on) | |
16218 | continue; | |
16219 | ||
16220 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
16221 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
16222 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
16223 | ||
16224 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
16225 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
16226 | if (INTEL_INFO(dev)->gen <= 3) { | |
16227 | error->plane[i].size = I915_READ(DSPSIZE(i)); | |
16228 | error->plane[i].pos = I915_READ(DSPPOS(i)); | |
16229 | } | |
16230 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) | |
16231 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
16232 | if (INTEL_INFO(dev)->gen >= 4) { | |
16233 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
16234 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
16235 | } | |
16236 | ||
16237 | error->pipe[i].source = I915_READ(PIPESRC(i)); | |
16238 | ||
16239 | if (HAS_GMCH_DISPLAY(dev)) | |
16240 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); | |
16241 | } | |
16242 | ||
16243 | /* Note: this does not include DSI transcoders. */ | |
16244 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
16245 | if (HAS_DDI(dev_priv)) | |
16246 | error->num_transcoders++; /* Account for eDP. */ | |
16247 | ||
16248 | for (i = 0; i < error->num_transcoders; i++) { | |
16249 | enum transcoder cpu_transcoder = transcoders[i]; | |
16250 | ||
16251 | error->transcoder[i].power_domain_on = | |
16252 | __intel_display_power_is_enabled(dev_priv, | |
16253 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); | |
16254 | if (!error->transcoder[i].power_domain_on) | |
16255 | continue; | |
16256 | ||
16257 | error->transcoder[i].cpu_transcoder = cpu_transcoder; | |
16258 | ||
16259 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
16260 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
16261 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
16262 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
16263 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
16264 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
16265 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
16266 | } | |
16267 | ||
16268 | return error; | |
16269 | } | |
16270 | ||
16271 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) | |
16272 | ||
16273 | void | |
16274 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, | |
16275 | struct drm_device *dev, | |
16276 | struct intel_display_error_state *error) | |
16277 | { | |
16278 | struct drm_i915_private *dev_priv = dev->dev_private; | |
16279 | int i; | |
16280 | ||
16281 | if (!error) | |
16282 | return; | |
16283 | ||
16284 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); | |
16285 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
16286 | err_printf(m, "PWR_WELL_CTL2: %08x\n", | |
16287 | error->power_well_driver); | |
16288 | for_each_pipe(dev_priv, i) { | |
16289 | err_printf(m, "Pipe [%d]:\n", i); | |
16290 | err_printf(m, " Power: %s\n", | |
16291 | onoff(error->pipe[i].power_domain_on)); | |
16292 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); | |
16293 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); | |
16294 | ||
16295 | err_printf(m, "Plane [%d]:\n", i); | |
16296 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
16297 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
16298 | if (INTEL_INFO(dev)->gen <= 3) { | |
16299 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); | |
16300 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
16301 | } | |
16302 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) | |
16303 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); | |
16304 | if (INTEL_INFO(dev)->gen >= 4) { | |
16305 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); | |
16306 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
16307 | } | |
16308 | ||
16309 | err_printf(m, "Cursor [%d]:\n", i); | |
16310 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
16311 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
16312 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
16313 | } | |
16314 | ||
16315 | for (i = 0; i < error->num_transcoders; i++) { | |
16316 | err_printf(m, "CPU transcoder: %s\n", | |
16317 | transcoder_name(error->transcoder[i].cpu_transcoder)); | |
16318 | err_printf(m, " Power: %s\n", | |
16319 | onoff(error->transcoder[i].power_domain_on)); | |
16320 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); | |
16321 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
16322 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
16323 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
16324 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
16325 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
16326 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
16327 | } | |
16328 | } |