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drm/i915: Zap call to drm_plane_helper_disable, v2.
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
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1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27#include <linux/dmi.h>
28#include <linux/module.h>
29#include <linux/input.h>
30#include <linux/i2c.h>
31#include <linux/kernel.h>
32#include <linux/slab.h>
33#include <linux/vgaarb.h>
34#include <drm/drm_edid.h>
35#include <drm/drmP.h>
36#include "intel_drv.h"
37#include <drm/i915_drm.h>
38#include "i915_drv.h"
39#include "i915_trace.h"
40#include <drm/drm_atomic.h>
41#include <drm/drm_atomic_helper.h>
42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
46#include <linux/dma_remapping.h>
47
48/* Primary plane formats for gen <= 3 */
49static const uint32_t i8xx_primary_formats[] = {
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_XRGB8888,
54};
55
56/* Primary plane formats for gen >= 4 */
57static const uint32_t i965_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_ARGB8888,
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
75};
76
77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
83
84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
85 struct intel_crtc_state *pipe_config);
86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
87 struct intel_crtc_state *pipe_config);
88
89static int intel_set_mode(struct drm_atomic_state *state);
90static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100static void haswell_set_pipeconf(struct drm_crtc *crtc);
101static void intel_set_pipe_csc(struct drm_crtc *crtc);
102static void vlv_prepare_pll(struct intel_crtc *crtc,
103 const struct intel_crtc_state *pipe_config);
104static void chv_prepare_pll(struct intel_crtc *crtc,
105 const struct intel_crtc_state *pipe_config);
106static void intel_begin_crtc_commit(struct drm_crtc *crtc);
107static void intel_finish_crtc_commit(struct drm_crtc *crtc);
108static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
109 struct intel_crtc_state *crtc_state);
110static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
111 int num_connectors);
112static void intel_crtc_enable_planes(struct drm_crtc *crtc);
113static void intel_crtc_disable_planes(struct drm_crtc *crtc);
114
115static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
116{
117 if (!connector->mst_port)
118 return connector->encoder;
119 else
120 return &connector->mst_port->mst_encoders[pipe]->base;
121}
122
123typedef struct {
124 int min, max;
125} intel_range_t;
126
127typedef struct {
128 int dot_limit;
129 int p2_slow, p2_fast;
130} intel_p2_t;
131
132typedef struct intel_limit intel_limit_t;
133struct intel_limit {
134 intel_range_t dot, vco, n, m, m1, m2, p, p1;
135 intel_p2_t p2;
136};
137
138int
139intel_pch_rawclk(struct drm_device *dev)
140{
141 struct drm_i915_private *dev_priv = dev->dev_private;
142
143 WARN_ON(!HAS_PCH_SPLIT(dev));
144
145 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
146}
147
148static inline u32 /* units of 100MHz */
149intel_fdi_link_freq(struct drm_device *dev)
150{
151 if (IS_GEN5(dev)) {
152 struct drm_i915_private *dev_priv = dev->dev_private;
153 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
154 } else
155 return 27;
156}
157
158static const intel_limit_t intel_limits_i8xx_dac = {
159 .dot = { .min = 25000, .max = 350000 },
160 .vco = { .min = 908000, .max = 1512000 },
161 .n = { .min = 2, .max = 16 },
162 .m = { .min = 96, .max = 140 },
163 .m1 = { .min = 18, .max = 26 },
164 .m2 = { .min = 6, .max = 16 },
165 .p = { .min = 4, .max = 128 },
166 .p1 = { .min = 2, .max = 33 },
167 .p2 = { .dot_limit = 165000,
168 .p2_slow = 4, .p2_fast = 2 },
169};
170
171static const intel_limit_t intel_limits_i8xx_dvo = {
172 .dot = { .min = 25000, .max = 350000 },
173 .vco = { .min = 908000, .max = 1512000 },
174 .n = { .min = 2, .max = 16 },
175 .m = { .min = 96, .max = 140 },
176 .m1 = { .min = 18, .max = 26 },
177 .m2 = { .min = 6, .max = 16 },
178 .p = { .min = 4, .max = 128 },
179 .p1 = { .min = 2, .max = 33 },
180 .p2 = { .dot_limit = 165000,
181 .p2_slow = 4, .p2_fast = 4 },
182};
183
184static const intel_limit_t intel_limits_i8xx_lvds = {
185 .dot = { .min = 25000, .max = 350000 },
186 .vco = { .min = 908000, .max = 1512000 },
187 .n = { .min = 2, .max = 16 },
188 .m = { .min = 96, .max = 140 },
189 .m1 = { .min = 18, .max = 26 },
190 .m2 = { .min = 6, .max = 16 },
191 .p = { .min = 4, .max = 128 },
192 .p1 = { .min = 1, .max = 6 },
193 .p2 = { .dot_limit = 165000,
194 .p2_slow = 14, .p2_fast = 7 },
195};
196
197static const intel_limit_t intel_limits_i9xx_sdvo = {
198 .dot = { .min = 20000, .max = 400000 },
199 .vco = { .min = 1400000, .max = 2800000 },
200 .n = { .min = 1, .max = 6 },
201 .m = { .min = 70, .max = 120 },
202 .m1 = { .min = 8, .max = 18 },
203 .m2 = { .min = 3, .max = 7 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8 },
206 .p2 = { .dot_limit = 200000,
207 .p2_slow = 10, .p2_fast = 5 },
208};
209
210static const intel_limit_t intel_limits_i9xx_lvds = {
211 .dot = { .min = 20000, .max = 400000 },
212 .vco = { .min = 1400000, .max = 2800000 },
213 .n = { .min = 1, .max = 6 },
214 .m = { .min = 70, .max = 120 },
215 .m1 = { .min = 8, .max = 18 },
216 .m2 = { .min = 3, .max = 7 },
217 .p = { .min = 7, .max = 98 },
218 .p1 = { .min = 1, .max = 8 },
219 .p2 = { .dot_limit = 112000,
220 .p2_slow = 14, .p2_fast = 7 },
221};
222
223
224static const intel_limit_t intel_limits_g4x_sdvo = {
225 .dot = { .min = 25000, .max = 270000 },
226 .vco = { .min = 1750000, .max = 3500000},
227 .n = { .min = 1, .max = 4 },
228 .m = { .min = 104, .max = 138 },
229 .m1 = { .min = 17, .max = 23 },
230 .m2 = { .min = 5, .max = 11 },
231 .p = { .min = 10, .max = 30 },
232 .p1 = { .min = 1, .max = 3},
233 .p2 = { .dot_limit = 270000,
234 .p2_slow = 10,
235 .p2_fast = 10
236 },
237};
238
239static const intel_limit_t intel_limits_g4x_hdmi = {
240 .dot = { .min = 22000, .max = 400000 },
241 .vco = { .min = 1750000, .max = 3500000},
242 .n = { .min = 1, .max = 4 },
243 .m = { .min = 104, .max = 138 },
244 .m1 = { .min = 16, .max = 23 },
245 .m2 = { .min = 5, .max = 11 },
246 .p = { .min = 5, .max = 80 },
247 .p1 = { .min = 1, .max = 8},
248 .p2 = { .dot_limit = 165000,
249 .p2_slow = 10, .p2_fast = 5 },
250};
251
252static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
253 .dot = { .min = 20000, .max = 115000 },
254 .vco = { .min = 1750000, .max = 3500000 },
255 .n = { .min = 1, .max = 3 },
256 .m = { .min = 104, .max = 138 },
257 .m1 = { .min = 17, .max = 23 },
258 .m2 = { .min = 5, .max = 11 },
259 .p = { .min = 28, .max = 112 },
260 .p1 = { .min = 2, .max = 8 },
261 .p2 = { .dot_limit = 0,
262 .p2_slow = 14, .p2_fast = 14
263 },
264};
265
266static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
267 .dot = { .min = 80000, .max = 224000 },
268 .vco = { .min = 1750000, .max = 3500000 },
269 .n = { .min = 1, .max = 3 },
270 .m = { .min = 104, .max = 138 },
271 .m1 = { .min = 17, .max = 23 },
272 .m2 = { .min = 5, .max = 11 },
273 .p = { .min = 14, .max = 42 },
274 .p1 = { .min = 2, .max = 6 },
275 .p2 = { .dot_limit = 0,
276 .p2_slow = 7, .p2_fast = 7
277 },
278};
279
280static const intel_limit_t intel_limits_pineview_sdvo = {
281 .dot = { .min = 20000, .max = 400000},
282 .vco = { .min = 1700000, .max = 3500000 },
283 /* Pineview's Ncounter is a ring counter */
284 .n = { .min = 3, .max = 6 },
285 .m = { .min = 2, .max = 256 },
286 /* Pineview only has one combined m divider, which we treat as m2. */
287 .m1 = { .min = 0, .max = 0 },
288 .m2 = { .min = 0, .max = 254 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 200000,
292 .p2_slow = 10, .p2_fast = 5 },
293};
294
295static const intel_limit_t intel_limits_pineview_lvds = {
296 .dot = { .min = 20000, .max = 400000 },
297 .vco = { .min = 1700000, .max = 3500000 },
298 .n = { .min = 3, .max = 6 },
299 .m = { .min = 2, .max = 256 },
300 .m1 = { .min = 0, .max = 0 },
301 .m2 = { .min = 0, .max = 254 },
302 .p = { .min = 7, .max = 112 },
303 .p1 = { .min = 1, .max = 8 },
304 .p2 = { .dot_limit = 112000,
305 .p2_slow = 14, .p2_fast = 14 },
306};
307
308/* Ironlake / Sandybridge
309 *
310 * We calculate clock using (register_value + 2) for N/M1/M2, so here
311 * the range value for them is (actual_value - 2).
312 */
313static const intel_limit_t intel_limits_ironlake_dac = {
314 .dot = { .min = 25000, .max = 350000 },
315 .vco = { .min = 1760000, .max = 3510000 },
316 .n = { .min = 1, .max = 5 },
317 .m = { .min = 79, .max = 127 },
318 .m1 = { .min = 12, .max = 22 },
319 .m2 = { .min = 5, .max = 9 },
320 .p = { .min = 5, .max = 80 },
321 .p1 = { .min = 1, .max = 8 },
322 .p2 = { .dot_limit = 225000,
323 .p2_slow = 10, .p2_fast = 5 },
324};
325
326static const intel_limit_t intel_limits_ironlake_single_lvds = {
327 .dot = { .min = 25000, .max = 350000 },
328 .vco = { .min = 1760000, .max = 3510000 },
329 .n = { .min = 1, .max = 3 },
330 .m = { .min = 79, .max = 118 },
331 .m1 = { .min = 12, .max = 22 },
332 .m2 = { .min = 5, .max = 9 },
333 .p = { .min = 28, .max = 112 },
334 .p1 = { .min = 2, .max = 8 },
335 .p2 = { .dot_limit = 225000,
336 .p2_slow = 14, .p2_fast = 14 },
337};
338
339static const intel_limit_t intel_limits_ironlake_dual_lvds = {
340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 127 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 56 },
347 .p1 = { .min = 2, .max = 8 },
348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
350};
351
352/* LVDS 100mhz refclk limits. */
353static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000 },
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 79, .max = 126 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 28, .max = 112 },
361 .p1 = { .min = 2, .max = 8 },
362 .p2 = { .dot_limit = 225000,
363 .p2_slow = 14, .p2_fast = 14 },
364};
365
366static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
367 .dot = { .min = 25000, .max = 350000 },
368 .vco = { .min = 1760000, .max = 3510000 },
369 .n = { .min = 1, .max = 3 },
370 .m = { .min = 79, .max = 126 },
371 .m1 = { .min = 12, .max = 22 },
372 .m2 = { .min = 5, .max = 9 },
373 .p = { .min = 14, .max = 42 },
374 .p1 = { .min = 2, .max = 6 },
375 .p2 = { .dot_limit = 225000,
376 .p2_slow = 7, .p2_fast = 7 },
377};
378
379static const intel_limit_t intel_limits_vlv = {
380 /*
381 * These are the data rate limits (measured in fast clocks)
382 * since those are the strictest limits we have. The fast
383 * clock and actual rate limits are more relaxed, so checking
384 * them would make no difference.
385 */
386 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
387 .vco = { .min = 4000000, .max = 6000000 },
388 .n = { .min = 1, .max = 7 },
389 .m1 = { .min = 2, .max = 3 },
390 .m2 = { .min = 11, .max = 156 },
391 .p1 = { .min = 2, .max = 3 },
392 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
393};
394
395static const intel_limit_t intel_limits_chv = {
396 /*
397 * These are the data rate limits (measured in fast clocks)
398 * since those are the strictest limits we have. The fast
399 * clock and actual rate limits are more relaxed, so checking
400 * them would make no difference.
401 */
402 .dot = { .min = 25000 * 5, .max = 540000 * 5},
403 .vco = { .min = 4800000, .max = 6480000 },
404 .n = { .min = 1, .max = 1 },
405 .m1 = { .min = 2, .max = 2 },
406 .m2 = { .min = 24 << 22, .max = 175 << 22 },
407 .p1 = { .min = 2, .max = 4 },
408 .p2 = { .p2_slow = 1, .p2_fast = 14 },
409};
410
411static const intel_limit_t intel_limits_bxt = {
412 /* FIXME: find real dot limits */
413 .dot = { .min = 0, .max = INT_MAX },
414 .vco = { .min = 4800000, .max = 6480000 },
415 .n = { .min = 1, .max = 1 },
416 .m1 = { .min = 2, .max = 2 },
417 /* FIXME: find real m2 limits */
418 .m2 = { .min = 2 << 22, .max = 255 << 22 },
419 .p1 = { .min = 2, .max = 4 },
420 .p2 = { .p2_slow = 1, .p2_fast = 20 },
421};
422
423static void vlv_clock(int refclk, intel_clock_t *clock)
424{
425 clock->m = clock->m1 * clock->m2;
426 clock->p = clock->p1 * clock->p2;
427 if (WARN_ON(clock->n == 0 || clock->p == 0))
428 return;
429 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
430 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
431}
432
433static bool
434needs_modeset(struct drm_crtc_state *state)
435{
436 return state->mode_changed || state->active_changed;
437}
438
439/**
440 * Returns whether any output on the specified pipe is of the specified type
441 */
442bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
443{
444 struct drm_device *dev = crtc->base.dev;
445 struct intel_encoder *encoder;
446
447 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
448 if (encoder->type == type)
449 return true;
450
451 return false;
452}
453
454/**
455 * Returns whether any output on the specified pipe will have the specified
456 * type after a staged modeset is complete, i.e., the same as
457 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
458 * encoder->crtc.
459 */
460static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
461 int type)
462{
463 struct drm_atomic_state *state = crtc_state->base.state;
464 struct drm_connector *connector;
465 struct drm_connector_state *connector_state;
466 struct intel_encoder *encoder;
467 int i, num_connectors = 0;
468
469 for_each_connector_in_state(state, connector, connector_state, i) {
470 if (connector_state->crtc != crtc_state->base.crtc)
471 continue;
472
473 num_connectors++;
474
475 encoder = to_intel_encoder(connector_state->best_encoder);
476 if (encoder->type == type)
477 return true;
478 }
479
480 WARN_ON(num_connectors == 0);
481
482 return false;
483}
484
485static const intel_limit_t *
486intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
487{
488 struct drm_device *dev = crtc_state->base.crtc->dev;
489 const intel_limit_t *limit;
490
491 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
492 if (intel_is_dual_link_lvds(dev)) {
493 if (refclk == 100000)
494 limit = &intel_limits_ironlake_dual_lvds_100m;
495 else
496 limit = &intel_limits_ironlake_dual_lvds;
497 } else {
498 if (refclk == 100000)
499 limit = &intel_limits_ironlake_single_lvds_100m;
500 else
501 limit = &intel_limits_ironlake_single_lvds;
502 }
503 } else
504 limit = &intel_limits_ironlake_dac;
505
506 return limit;
507}
508
509static const intel_limit_t *
510intel_g4x_limit(struct intel_crtc_state *crtc_state)
511{
512 struct drm_device *dev = crtc_state->base.crtc->dev;
513 const intel_limit_t *limit;
514
515 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
516 if (intel_is_dual_link_lvds(dev))
517 limit = &intel_limits_g4x_dual_channel_lvds;
518 else
519 limit = &intel_limits_g4x_single_channel_lvds;
520 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
521 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
522 limit = &intel_limits_g4x_hdmi;
523 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
524 limit = &intel_limits_g4x_sdvo;
525 } else /* The option is for other outputs */
526 limit = &intel_limits_i9xx_sdvo;
527
528 return limit;
529}
530
531static const intel_limit_t *
532intel_limit(struct intel_crtc_state *crtc_state, int refclk)
533{
534 struct drm_device *dev = crtc_state->base.crtc->dev;
535 const intel_limit_t *limit;
536
537 if (IS_BROXTON(dev))
538 limit = &intel_limits_bxt;
539 else if (HAS_PCH_SPLIT(dev))
540 limit = intel_ironlake_limit(crtc_state, refclk);
541 else if (IS_G4X(dev)) {
542 limit = intel_g4x_limit(crtc_state);
543 } else if (IS_PINEVIEW(dev)) {
544 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
545 limit = &intel_limits_pineview_lvds;
546 else
547 limit = &intel_limits_pineview_sdvo;
548 } else if (IS_CHERRYVIEW(dev)) {
549 limit = &intel_limits_chv;
550 } else if (IS_VALLEYVIEW(dev)) {
551 limit = &intel_limits_vlv;
552 } else if (!IS_GEN2(dev)) {
553 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
554 limit = &intel_limits_i9xx_lvds;
555 else
556 limit = &intel_limits_i9xx_sdvo;
557 } else {
558 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
559 limit = &intel_limits_i8xx_lvds;
560 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
561 limit = &intel_limits_i8xx_dvo;
562 else
563 limit = &intel_limits_i8xx_dac;
564 }
565 return limit;
566}
567
568/* m1 is reserved as 0 in Pineview, n is a ring counter */
569static void pineview_clock(int refclk, intel_clock_t *clock)
570{
571 clock->m = clock->m2 + 2;
572 clock->p = clock->p1 * clock->p2;
573 if (WARN_ON(clock->n == 0 || clock->p == 0))
574 return;
575 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
576 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
577}
578
579static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
580{
581 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
582}
583
584static void i9xx_clock(int refclk, intel_clock_t *clock)
585{
586 clock->m = i9xx_dpll_compute_m(clock);
587 clock->p = clock->p1 * clock->p2;
588 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
589 return;
590 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
591 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
592}
593
594static void chv_clock(int refclk, intel_clock_t *clock)
595{
596 clock->m = clock->m1 * clock->m2;
597 clock->p = clock->p1 * clock->p2;
598 if (WARN_ON(clock->n == 0 || clock->p == 0))
599 return;
600 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
601 clock->n << 22);
602 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
603}
604
605#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
606/**
607 * Returns whether the given set of divisors are valid for a given refclk with
608 * the given connectors.
609 */
610
611static bool intel_PLL_is_valid(struct drm_device *dev,
612 const intel_limit_t *limit,
613 const intel_clock_t *clock)
614{
615 if (clock->n < limit->n.min || limit->n.max < clock->n)
616 INTELPllInvalid("n out of range\n");
617 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
618 INTELPllInvalid("p1 out of range\n");
619 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
620 INTELPllInvalid("m2 out of range\n");
621 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
622 INTELPllInvalid("m1 out of range\n");
623
624 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
625 if (clock->m1 <= clock->m2)
626 INTELPllInvalid("m1 <= m2\n");
627
628 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
629 if (clock->p < limit->p.min || limit->p.max < clock->p)
630 INTELPllInvalid("p out of range\n");
631 if (clock->m < limit->m.min || limit->m.max < clock->m)
632 INTELPllInvalid("m out of range\n");
633 }
634
635 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
636 INTELPllInvalid("vco out of range\n");
637 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
638 * connector, etc., rather than just a single range.
639 */
640 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
641 INTELPllInvalid("dot out of range\n");
642
643 return true;
644}
645
646static bool
647i9xx_find_best_dpll(const intel_limit_t *limit,
648 struct intel_crtc_state *crtc_state,
649 int target, int refclk, intel_clock_t *match_clock,
650 intel_clock_t *best_clock)
651{
652 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
653 struct drm_device *dev = crtc->base.dev;
654 intel_clock_t clock;
655 int err = target;
656
657 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
658 /*
659 * For LVDS just rely on its current settings for dual-channel.
660 * We haven't figured out how to reliably set up different
661 * single/dual channel state, if we even can.
662 */
663 if (intel_is_dual_link_lvds(dev))
664 clock.p2 = limit->p2.p2_fast;
665 else
666 clock.p2 = limit->p2.p2_slow;
667 } else {
668 if (target < limit->p2.dot_limit)
669 clock.p2 = limit->p2.p2_slow;
670 else
671 clock.p2 = limit->p2.p2_fast;
672 }
673
674 memset(best_clock, 0, sizeof(*best_clock));
675
676 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
677 clock.m1++) {
678 for (clock.m2 = limit->m2.min;
679 clock.m2 <= limit->m2.max; clock.m2++) {
680 if (clock.m2 >= clock.m1)
681 break;
682 for (clock.n = limit->n.min;
683 clock.n <= limit->n.max; clock.n++) {
684 for (clock.p1 = limit->p1.min;
685 clock.p1 <= limit->p1.max; clock.p1++) {
686 int this_err;
687
688 i9xx_clock(refclk, &clock);
689 if (!intel_PLL_is_valid(dev, limit,
690 &clock))
691 continue;
692 if (match_clock &&
693 clock.p != match_clock->p)
694 continue;
695
696 this_err = abs(clock.dot - target);
697 if (this_err < err) {
698 *best_clock = clock;
699 err = this_err;
700 }
701 }
702 }
703 }
704 }
705
706 return (err != target);
707}
708
709static bool
710pnv_find_best_dpll(const intel_limit_t *limit,
711 struct intel_crtc_state *crtc_state,
712 int target, int refclk, intel_clock_t *match_clock,
713 intel_clock_t *best_clock)
714{
715 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
716 struct drm_device *dev = crtc->base.dev;
717 intel_clock_t clock;
718 int err = target;
719
720 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
721 /*
722 * For LVDS just rely on its current settings for dual-channel.
723 * We haven't figured out how to reliably set up different
724 * single/dual channel state, if we even can.
725 */
726 if (intel_is_dual_link_lvds(dev))
727 clock.p2 = limit->p2.p2_fast;
728 else
729 clock.p2 = limit->p2.p2_slow;
730 } else {
731 if (target < limit->p2.dot_limit)
732 clock.p2 = limit->p2.p2_slow;
733 else
734 clock.p2 = limit->p2.p2_fast;
735 }
736
737 memset(best_clock, 0, sizeof(*best_clock));
738
739 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
740 clock.m1++) {
741 for (clock.m2 = limit->m2.min;
742 clock.m2 <= limit->m2.max; clock.m2++) {
743 for (clock.n = limit->n.min;
744 clock.n <= limit->n.max; clock.n++) {
745 for (clock.p1 = limit->p1.min;
746 clock.p1 <= limit->p1.max; clock.p1++) {
747 int this_err;
748
749 pineview_clock(refclk, &clock);
750 if (!intel_PLL_is_valid(dev, limit,
751 &clock))
752 continue;
753 if (match_clock &&
754 clock.p != match_clock->p)
755 continue;
756
757 this_err = abs(clock.dot - target);
758 if (this_err < err) {
759 *best_clock = clock;
760 err = this_err;
761 }
762 }
763 }
764 }
765 }
766
767 return (err != target);
768}
769
770static bool
771g4x_find_best_dpll(const intel_limit_t *limit,
772 struct intel_crtc_state *crtc_state,
773 int target, int refclk, intel_clock_t *match_clock,
774 intel_clock_t *best_clock)
775{
776 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
777 struct drm_device *dev = crtc->base.dev;
778 intel_clock_t clock;
779 int max_n;
780 bool found;
781 /* approximately equals target * 0.00585 */
782 int err_most = (target >> 8) + (target >> 9);
783 found = false;
784
785 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
786 if (intel_is_dual_link_lvds(dev))
787 clock.p2 = limit->p2.p2_fast;
788 else
789 clock.p2 = limit->p2.p2_slow;
790 } else {
791 if (target < limit->p2.dot_limit)
792 clock.p2 = limit->p2.p2_slow;
793 else
794 clock.p2 = limit->p2.p2_fast;
795 }
796
797 memset(best_clock, 0, sizeof(*best_clock));
798 max_n = limit->n.max;
799 /* based on hardware requirement, prefer smaller n to precision */
800 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
801 /* based on hardware requirement, prefere larger m1,m2 */
802 for (clock.m1 = limit->m1.max;
803 clock.m1 >= limit->m1.min; clock.m1--) {
804 for (clock.m2 = limit->m2.max;
805 clock.m2 >= limit->m2.min; clock.m2--) {
806 for (clock.p1 = limit->p1.max;
807 clock.p1 >= limit->p1.min; clock.p1--) {
808 int this_err;
809
810 i9xx_clock(refclk, &clock);
811 if (!intel_PLL_is_valid(dev, limit,
812 &clock))
813 continue;
814
815 this_err = abs(clock.dot - target);
816 if (this_err < err_most) {
817 *best_clock = clock;
818 err_most = this_err;
819 max_n = clock.n;
820 found = true;
821 }
822 }
823 }
824 }
825 }
826 return found;
827}
828
829/*
830 * Check if the calculated PLL configuration is more optimal compared to the
831 * best configuration and error found so far. Return the calculated error.
832 */
833static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
834 const intel_clock_t *calculated_clock,
835 const intel_clock_t *best_clock,
836 unsigned int best_error_ppm,
837 unsigned int *error_ppm)
838{
839 /*
840 * For CHV ignore the error and consider only the P value.
841 * Prefer a bigger P value based on HW requirements.
842 */
843 if (IS_CHERRYVIEW(dev)) {
844 *error_ppm = 0;
845
846 return calculated_clock->p > best_clock->p;
847 }
848
849 if (WARN_ON_ONCE(!target_freq))
850 return false;
851
852 *error_ppm = div_u64(1000000ULL *
853 abs(target_freq - calculated_clock->dot),
854 target_freq);
855 /*
856 * Prefer a better P value over a better (smaller) error if the error
857 * is small. Ensure this preference for future configurations too by
858 * setting the error to 0.
859 */
860 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
861 *error_ppm = 0;
862
863 return true;
864 }
865
866 return *error_ppm + 10 < best_error_ppm;
867}
868
869static bool
870vlv_find_best_dpll(const intel_limit_t *limit,
871 struct intel_crtc_state *crtc_state,
872 int target, int refclk, intel_clock_t *match_clock,
873 intel_clock_t *best_clock)
874{
875 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
876 struct drm_device *dev = crtc->base.dev;
877 intel_clock_t clock;
878 unsigned int bestppm = 1000000;
879 /* min update 19.2 MHz */
880 int max_n = min(limit->n.max, refclk / 19200);
881 bool found = false;
882
883 target *= 5; /* fast clock */
884
885 memset(best_clock, 0, sizeof(*best_clock));
886
887 /* based on hardware requirement, prefer smaller n to precision */
888 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
889 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
890 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
891 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
892 clock.p = clock.p1 * clock.p2;
893 /* based on hardware requirement, prefer bigger m1,m2 values */
894 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
895 unsigned int ppm;
896
897 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
898 refclk * clock.m1);
899
900 vlv_clock(refclk, &clock);
901
902 if (!intel_PLL_is_valid(dev, limit,
903 &clock))
904 continue;
905
906 if (!vlv_PLL_is_optimal(dev, target,
907 &clock,
908 best_clock,
909 bestppm, &ppm))
910 continue;
911
912 *best_clock = clock;
913 bestppm = ppm;
914 found = true;
915 }
916 }
917 }
918 }
919
920 return found;
921}
922
923static bool
924chv_find_best_dpll(const intel_limit_t *limit,
925 struct intel_crtc_state *crtc_state,
926 int target, int refclk, intel_clock_t *match_clock,
927 intel_clock_t *best_clock)
928{
929 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
930 struct drm_device *dev = crtc->base.dev;
931 unsigned int best_error_ppm;
932 intel_clock_t clock;
933 uint64_t m2;
934 int found = false;
935
936 memset(best_clock, 0, sizeof(*best_clock));
937 best_error_ppm = 1000000;
938
939 /*
940 * Based on hardware doc, the n always set to 1, and m1 always
941 * set to 2. If requires to support 200Mhz refclk, we need to
942 * revisit this because n may not 1 anymore.
943 */
944 clock.n = 1, clock.m1 = 2;
945 target *= 5; /* fast clock */
946
947 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
948 for (clock.p2 = limit->p2.p2_fast;
949 clock.p2 >= limit->p2.p2_slow;
950 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
951 unsigned int error_ppm;
952
953 clock.p = clock.p1 * clock.p2;
954
955 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
956 clock.n) << 22, refclk * clock.m1);
957
958 if (m2 > INT_MAX/clock.m1)
959 continue;
960
961 clock.m2 = m2;
962
963 chv_clock(refclk, &clock);
964
965 if (!intel_PLL_is_valid(dev, limit, &clock))
966 continue;
967
968 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
969 best_error_ppm, &error_ppm))
970 continue;
971
972 *best_clock = clock;
973 best_error_ppm = error_ppm;
974 found = true;
975 }
976 }
977
978 return found;
979}
980
981bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
982 intel_clock_t *best_clock)
983{
984 int refclk = i9xx_get_refclk(crtc_state, 0);
985
986 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
987 target_clock, refclk, NULL, best_clock);
988}
989
990bool intel_crtc_active(struct drm_crtc *crtc)
991{
992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
993
994 /* Be paranoid as we can arrive here with only partial
995 * state retrieved from the hardware during setup.
996 *
997 * We can ditch the adjusted_mode.crtc_clock check as soon
998 * as Haswell has gained clock readout/fastboot support.
999 *
1000 * We can ditch the crtc->primary->fb check as soon as we can
1001 * properly reconstruct framebuffers.
1002 *
1003 * FIXME: The intel_crtc->active here should be switched to
1004 * crtc->state->active once we have proper CRTC states wired up
1005 * for atomic.
1006 */
1007 return intel_crtc->active && crtc->primary->state->fb &&
1008 intel_crtc->config->base.adjusted_mode.crtc_clock;
1009}
1010
1011enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1012 enum pipe pipe)
1013{
1014 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1016
1017 return intel_crtc->config->cpu_transcoder;
1018}
1019
1020static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1021{
1022 struct drm_i915_private *dev_priv = dev->dev_private;
1023 u32 reg = PIPEDSL(pipe);
1024 u32 line1, line2;
1025 u32 line_mask;
1026
1027 if (IS_GEN2(dev))
1028 line_mask = DSL_LINEMASK_GEN2;
1029 else
1030 line_mask = DSL_LINEMASK_GEN3;
1031
1032 line1 = I915_READ(reg) & line_mask;
1033 mdelay(5);
1034 line2 = I915_READ(reg) & line_mask;
1035
1036 return line1 == line2;
1037}
1038
1039/*
1040 * intel_wait_for_pipe_off - wait for pipe to turn off
1041 * @crtc: crtc whose pipe to wait for
1042 *
1043 * After disabling a pipe, we can't wait for vblank in the usual way,
1044 * spinning on the vblank interrupt status bit, since we won't actually
1045 * see an interrupt when the pipe is disabled.
1046 *
1047 * On Gen4 and above:
1048 * wait for the pipe register state bit to turn off
1049 *
1050 * Otherwise:
1051 * wait for the display line value to settle (it usually
1052 * ends up stopping at the start of the next frame).
1053 *
1054 */
1055static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1056{
1057 struct drm_device *dev = crtc->base.dev;
1058 struct drm_i915_private *dev_priv = dev->dev_private;
1059 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1060 enum pipe pipe = crtc->pipe;
1061
1062 if (INTEL_INFO(dev)->gen >= 4) {
1063 int reg = PIPECONF(cpu_transcoder);
1064
1065 /* Wait for the Pipe State to go off */
1066 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1067 100))
1068 WARN(1, "pipe_off wait timed out\n");
1069 } else {
1070 /* Wait for the display line to settle */
1071 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1072 WARN(1, "pipe_off wait timed out\n");
1073 }
1074}
1075
1076/*
1077 * ibx_digital_port_connected - is the specified port connected?
1078 * @dev_priv: i915 private structure
1079 * @port: the port to test
1080 *
1081 * Returns true if @port is connected, false otherwise.
1082 */
1083bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1084 struct intel_digital_port *port)
1085{
1086 u32 bit;
1087
1088 if (HAS_PCH_IBX(dev_priv->dev)) {
1089 switch (port->port) {
1090 case PORT_B:
1091 bit = SDE_PORTB_HOTPLUG;
1092 break;
1093 case PORT_C:
1094 bit = SDE_PORTC_HOTPLUG;
1095 break;
1096 case PORT_D:
1097 bit = SDE_PORTD_HOTPLUG;
1098 break;
1099 default:
1100 return true;
1101 }
1102 } else {
1103 switch (port->port) {
1104 case PORT_B:
1105 bit = SDE_PORTB_HOTPLUG_CPT;
1106 break;
1107 case PORT_C:
1108 bit = SDE_PORTC_HOTPLUG_CPT;
1109 break;
1110 case PORT_D:
1111 bit = SDE_PORTD_HOTPLUG_CPT;
1112 break;
1113 default:
1114 return true;
1115 }
1116 }
1117
1118 return I915_READ(SDEISR) & bit;
1119}
1120
1121static const char *state_string(bool enabled)
1122{
1123 return enabled ? "on" : "off";
1124}
1125
1126/* Only for pre-ILK configs */
1127void assert_pll(struct drm_i915_private *dev_priv,
1128 enum pipe pipe, bool state)
1129{
1130 int reg;
1131 u32 val;
1132 bool cur_state;
1133
1134 reg = DPLL(pipe);
1135 val = I915_READ(reg);
1136 cur_state = !!(val & DPLL_VCO_ENABLE);
1137 I915_STATE_WARN(cur_state != state,
1138 "PLL state assertion failure (expected %s, current %s)\n",
1139 state_string(state), state_string(cur_state));
1140}
1141
1142/* XXX: the dsi pll is shared between MIPI DSI ports */
1143static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1144{
1145 u32 val;
1146 bool cur_state;
1147
1148 mutex_lock(&dev_priv->sb_lock);
1149 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1150 mutex_unlock(&dev_priv->sb_lock);
1151
1152 cur_state = val & DSI_PLL_VCO_EN;
1153 I915_STATE_WARN(cur_state != state,
1154 "DSI PLL state assertion failure (expected %s, current %s)\n",
1155 state_string(state), state_string(cur_state));
1156}
1157#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1158#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1159
1160struct intel_shared_dpll *
1161intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1162{
1163 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1164
1165 if (crtc->config->shared_dpll < 0)
1166 return NULL;
1167
1168 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1169}
1170
1171/* For ILK+ */
1172void assert_shared_dpll(struct drm_i915_private *dev_priv,
1173 struct intel_shared_dpll *pll,
1174 bool state)
1175{
1176 bool cur_state;
1177 struct intel_dpll_hw_state hw_state;
1178
1179 if (WARN (!pll,
1180 "asserting DPLL %s with no DPLL\n", state_string(state)))
1181 return;
1182
1183 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1184 I915_STATE_WARN(cur_state != state,
1185 "%s assertion failure (expected %s, current %s)\n",
1186 pll->name, state_string(state), state_string(cur_state));
1187}
1188
1189static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1190 enum pipe pipe, bool state)
1191{
1192 int reg;
1193 u32 val;
1194 bool cur_state;
1195 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1196 pipe);
1197
1198 if (HAS_DDI(dev_priv->dev)) {
1199 /* DDI does not have a specific FDI_TX register */
1200 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1201 val = I915_READ(reg);
1202 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1203 } else {
1204 reg = FDI_TX_CTL(pipe);
1205 val = I915_READ(reg);
1206 cur_state = !!(val & FDI_TX_ENABLE);
1207 }
1208 I915_STATE_WARN(cur_state != state,
1209 "FDI TX state assertion failure (expected %s, current %s)\n",
1210 state_string(state), state_string(cur_state));
1211}
1212#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1213#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1214
1215static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1216 enum pipe pipe, bool state)
1217{
1218 int reg;
1219 u32 val;
1220 bool cur_state;
1221
1222 reg = FDI_RX_CTL(pipe);
1223 val = I915_READ(reg);
1224 cur_state = !!(val & FDI_RX_ENABLE);
1225 I915_STATE_WARN(cur_state != state,
1226 "FDI RX state assertion failure (expected %s, current %s)\n",
1227 state_string(state), state_string(cur_state));
1228}
1229#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1230#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1231
1232static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1233 enum pipe pipe)
1234{
1235 int reg;
1236 u32 val;
1237
1238 /* ILK FDI PLL is always enabled */
1239 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1240 return;
1241
1242 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1243 if (HAS_DDI(dev_priv->dev))
1244 return;
1245
1246 reg = FDI_TX_CTL(pipe);
1247 val = I915_READ(reg);
1248 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1249}
1250
1251void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1252 enum pipe pipe, bool state)
1253{
1254 int reg;
1255 u32 val;
1256 bool cur_state;
1257
1258 reg = FDI_RX_CTL(pipe);
1259 val = I915_READ(reg);
1260 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1261 I915_STATE_WARN(cur_state != state,
1262 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1263 state_string(state), state_string(cur_state));
1264}
1265
1266void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1267 enum pipe pipe)
1268{
1269 struct drm_device *dev = dev_priv->dev;
1270 int pp_reg;
1271 u32 val;
1272 enum pipe panel_pipe = PIPE_A;
1273 bool locked = true;
1274
1275 if (WARN_ON(HAS_DDI(dev)))
1276 return;
1277
1278 if (HAS_PCH_SPLIT(dev)) {
1279 u32 port_sel;
1280
1281 pp_reg = PCH_PP_CONTROL;
1282 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1283
1284 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1285 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1286 panel_pipe = PIPE_B;
1287 /* XXX: else fix for eDP */
1288 } else if (IS_VALLEYVIEW(dev)) {
1289 /* presumably write lock depends on pipe, not port select */
1290 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1291 panel_pipe = pipe;
1292 } else {
1293 pp_reg = PP_CONTROL;
1294 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1295 panel_pipe = PIPE_B;
1296 }
1297
1298 val = I915_READ(pp_reg);
1299 if (!(val & PANEL_POWER_ON) ||
1300 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1301 locked = false;
1302
1303 I915_STATE_WARN(panel_pipe == pipe && locked,
1304 "panel assertion failure, pipe %c regs locked\n",
1305 pipe_name(pipe));
1306}
1307
1308static void assert_cursor(struct drm_i915_private *dev_priv,
1309 enum pipe pipe, bool state)
1310{
1311 struct drm_device *dev = dev_priv->dev;
1312 bool cur_state;
1313
1314 if (IS_845G(dev) || IS_I865G(dev))
1315 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1316 else
1317 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1318
1319 I915_STATE_WARN(cur_state != state,
1320 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1321 pipe_name(pipe), state_string(state), state_string(cur_state));
1322}
1323#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1324#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1325
1326void assert_pipe(struct drm_i915_private *dev_priv,
1327 enum pipe pipe, bool state)
1328{
1329 int reg;
1330 u32 val;
1331 bool cur_state;
1332 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1333 pipe);
1334
1335 /* if we need the pipe quirk it must be always on */
1336 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1337 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1338 state = true;
1339
1340 if (!intel_display_power_is_enabled(dev_priv,
1341 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1342 cur_state = false;
1343 } else {
1344 reg = PIPECONF(cpu_transcoder);
1345 val = I915_READ(reg);
1346 cur_state = !!(val & PIPECONF_ENABLE);
1347 }
1348
1349 I915_STATE_WARN(cur_state != state,
1350 "pipe %c assertion failure (expected %s, current %s)\n",
1351 pipe_name(pipe), state_string(state), state_string(cur_state));
1352}
1353
1354static void assert_plane(struct drm_i915_private *dev_priv,
1355 enum plane plane, bool state)
1356{
1357 int reg;
1358 u32 val;
1359 bool cur_state;
1360
1361 reg = DSPCNTR(plane);
1362 val = I915_READ(reg);
1363 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1364 I915_STATE_WARN(cur_state != state,
1365 "plane %c assertion failure (expected %s, current %s)\n",
1366 plane_name(plane), state_string(state), state_string(cur_state));
1367}
1368
1369#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1370#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1371
1372static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe)
1374{
1375 struct drm_device *dev = dev_priv->dev;
1376 int reg, i;
1377 u32 val;
1378 int cur_pipe;
1379
1380 /* Primary planes are fixed to pipes on gen4+ */
1381 if (INTEL_INFO(dev)->gen >= 4) {
1382 reg = DSPCNTR(pipe);
1383 val = I915_READ(reg);
1384 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1385 "plane %c assertion failure, should be disabled but not\n",
1386 plane_name(pipe));
1387 return;
1388 }
1389
1390 /* Need to check both planes against the pipe */
1391 for_each_pipe(dev_priv, i) {
1392 reg = DSPCNTR(i);
1393 val = I915_READ(reg);
1394 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1395 DISPPLANE_SEL_PIPE_SHIFT;
1396 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1397 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1398 plane_name(i), pipe_name(pipe));
1399 }
1400}
1401
1402static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1403 enum pipe pipe)
1404{
1405 struct drm_device *dev = dev_priv->dev;
1406 int reg, sprite;
1407 u32 val;
1408
1409 if (INTEL_INFO(dev)->gen >= 9) {
1410 for_each_sprite(dev_priv, pipe, sprite) {
1411 val = I915_READ(PLANE_CTL(pipe, sprite));
1412 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1413 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1414 sprite, pipe_name(pipe));
1415 }
1416 } else if (IS_VALLEYVIEW(dev)) {
1417 for_each_sprite(dev_priv, pipe, sprite) {
1418 reg = SPCNTR(pipe, sprite);
1419 val = I915_READ(reg);
1420 I915_STATE_WARN(val & SP_ENABLE,
1421 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1422 sprite_name(pipe, sprite), pipe_name(pipe));
1423 }
1424 } else if (INTEL_INFO(dev)->gen >= 7) {
1425 reg = SPRCTL(pipe);
1426 val = I915_READ(reg);
1427 I915_STATE_WARN(val & SPRITE_ENABLE,
1428 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1429 plane_name(pipe), pipe_name(pipe));
1430 } else if (INTEL_INFO(dev)->gen >= 5) {
1431 reg = DVSCNTR(pipe);
1432 val = I915_READ(reg);
1433 I915_STATE_WARN(val & DVS_ENABLE,
1434 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1435 plane_name(pipe), pipe_name(pipe));
1436 }
1437}
1438
1439static void assert_vblank_disabled(struct drm_crtc *crtc)
1440{
1441 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1442 drm_crtc_vblank_put(crtc);
1443}
1444
1445static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1446{
1447 u32 val;
1448 bool enabled;
1449
1450 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1451
1452 val = I915_READ(PCH_DREF_CONTROL);
1453 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1454 DREF_SUPERSPREAD_SOURCE_MASK));
1455 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1456}
1457
1458static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1459 enum pipe pipe)
1460{
1461 int reg;
1462 u32 val;
1463 bool enabled;
1464
1465 reg = PCH_TRANSCONF(pipe);
1466 val = I915_READ(reg);
1467 enabled = !!(val & TRANS_ENABLE);
1468 I915_STATE_WARN(enabled,
1469 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1470 pipe_name(pipe));
1471}
1472
1473static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1474 enum pipe pipe, u32 port_sel, u32 val)
1475{
1476 if ((val & DP_PORT_EN) == 0)
1477 return false;
1478
1479 if (HAS_PCH_CPT(dev_priv->dev)) {
1480 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1481 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1482 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1483 return false;
1484 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1485 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1486 return false;
1487 } else {
1488 if ((val & DP_PIPE_MASK) != (pipe << 30))
1489 return false;
1490 }
1491 return true;
1492}
1493
1494static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1495 enum pipe pipe, u32 val)
1496{
1497 if ((val & SDVO_ENABLE) == 0)
1498 return false;
1499
1500 if (HAS_PCH_CPT(dev_priv->dev)) {
1501 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1502 return false;
1503 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1504 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1505 return false;
1506 } else {
1507 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1508 return false;
1509 }
1510 return true;
1511}
1512
1513static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1514 enum pipe pipe, u32 val)
1515{
1516 if ((val & LVDS_PORT_EN) == 0)
1517 return false;
1518
1519 if (HAS_PCH_CPT(dev_priv->dev)) {
1520 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1521 return false;
1522 } else {
1523 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1524 return false;
1525 }
1526 return true;
1527}
1528
1529static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1530 enum pipe pipe, u32 val)
1531{
1532 if ((val & ADPA_DAC_ENABLE) == 0)
1533 return false;
1534 if (HAS_PCH_CPT(dev_priv->dev)) {
1535 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1536 return false;
1537 } else {
1538 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1539 return false;
1540 }
1541 return true;
1542}
1543
1544static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1545 enum pipe pipe, int reg, u32 port_sel)
1546{
1547 u32 val = I915_READ(reg);
1548 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1549 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1550 reg, pipe_name(pipe));
1551
1552 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1553 && (val & DP_PIPEB_SELECT),
1554 "IBX PCH dp port still using transcoder B\n");
1555}
1556
1557static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1558 enum pipe pipe, int reg)
1559{
1560 u32 val = I915_READ(reg);
1561 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1562 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1563 reg, pipe_name(pipe));
1564
1565 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1566 && (val & SDVO_PIPE_B_SELECT),
1567 "IBX PCH hdmi port still using transcoder B\n");
1568}
1569
1570static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1571 enum pipe pipe)
1572{
1573 int reg;
1574 u32 val;
1575
1576 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1577 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1578 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1579
1580 reg = PCH_ADPA;
1581 val = I915_READ(reg);
1582 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1583 "PCH VGA enabled on transcoder %c, should be disabled\n",
1584 pipe_name(pipe));
1585
1586 reg = PCH_LVDS;
1587 val = I915_READ(reg);
1588 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1589 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1590 pipe_name(pipe));
1591
1592 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1595}
1596
1597static void intel_init_dpio(struct drm_device *dev)
1598{
1599 struct drm_i915_private *dev_priv = dev->dev_private;
1600
1601 if (!IS_VALLEYVIEW(dev))
1602 return;
1603
1604 /*
1605 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1606 * CHV x1 PHY (DP/HDMI D)
1607 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1608 */
1609 if (IS_CHERRYVIEW(dev)) {
1610 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1611 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1612 } else {
1613 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1614 }
1615}
1616
1617static void vlv_enable_pll(struct intel_crtc *crtc,
1618 const struct intel_crtc_state *pipe_config)
1619{
1620 struct drm_device *dev = crtc->base.dev;
1621 struct drm_i915_private *dev_priv = dev->dev_private;
1622 int reg = DPLL(crtc->pipe);
1623 u32 dpll = pipe_config->dpll_hw_state.dpll;
1624
1625 assert_pipe_disabled(dev_priv, crtc->pipe);
1626
1627 /* No really, not for ILK+ */
1628 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1629
1630 /* PLL is protected by panel, make sure we can write it */
1631 if (IS_MOBILE(dev_priv->dev))
1632 assert_panel_unlocked(dev_priv, crtc->pipe);
1633
1634 I915_WRITE(reg, dpll);
1635 POSTING_READ(reg);
1636 udelay(150);
1637
1638 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1639 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1640
1641 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1642 POSTING_READ(DPLL_MD(crtc->pipe));
1643
1644 /* We do this three times for luck */
1645 I915_WRITE(reg, dpll);
1646 POSTING_READ(reg);
1647 udelay(150); /* wait for warmup */
1648 I915_WRITE(reg, dpll);
1649 POSTING_READ(reg);
1650 udelay(150); /* wait for warmup */
1651 I915_WRITE(reg, dpll);
1652 POSTING_READ(reg);
1653 udelay(150); /* wait for warmup */
1654}
1655
1656static void chv_enable_pll(struct intel_crtc *crtc,
1657 const struct intel_crtc_state *pipe_config)
1658{
1659 struct drm_device *dev = crtc->base.dev;
1660 struct drm_i915_private *dev_priv = dev->dev_private;
1661 int pipe = crtc->pipe;
1662 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1663 u32 tmp;
1664
1665 assert_pipe_disabled(dev_priv, crtc->pipe);
1666
1667 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1668
1669 mutex_lock(&dev_priv->sb_lock);
1670
1671 /* Enable back the 10bit clock to display controller */
1672 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1673 tmp |= DPIO_DCLKP_EN;
1674 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1675
1676 mutex_unlock(&dev_priv->sb_lock);
1677
1678 /*
1679 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1680 */
1681 udelay(1);
1682
1683 /* Enable PLL */
1684 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1685
1686 /* Check PLL is locked */
1687 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1688 DRM_ERROR("PLL %d failed to lock\n", pipe);
1689
1690 /* not sure when this should be written */
1691 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1692 POSTING_READ(DPLL_MD(pipe));
1693}
1694
1695static int intel_num_dvo_pipes(struct drm_device *dev)
1696{
1697 struct intel_crtc *crtc;
1698 int count = 0;
1699
1700 for_each_intel_crtc(dev, crtc)
1701 count += crtc->active &&
1702 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1703
1704 return count;
1705}
1706
1707static void i9xx_enable_pll(struct intel_crtc *crtc)
1708{
1709 struct drm_device *dev = crtc->base.dev;
1710 struct drm_i915_private *dev_priv = dev->dev_private;
1711 int reg = DPLL(crtc->pipe);
1712 u32 dpll = crtc->config->dpll_hw_state.dpll;
1713
1714 assert_pipe_disabled(dev_priv, crtc->pipe);
1715
1716 /* No really, not for ILK+ */
1717 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1718
1719 /* PLL is protected by panel, make sure we can write it */
1720 if (IS_MOBILE(dev) && !IS_I830(dev))
1721 assert_panel_unlocked(dev_priv, crtc->pipe);
1722
1723 /* Enable DVO 2x clock on both PLLs if necessary */
1724 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1725 /*
1726 * It appears to be important that we don't enable this
1727 * for the current pipe before otherwise configuring the
1728 * PLL. No idea how this should be handled if multiple
1729 * DVO outputs are enabled simultaneosly.
1730 */
1731 dpll |= DPLL_DVO_2X_MODE;
1732 I915_WRITE(DPLL(!crtc->pipe),
1733 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1734 }
1735
1736 /* Wait for the clocks to stabilize. */
1737 POSTING_READ(reg);
1738 udelay(150);
1739
1740 if (INTEL_INFO(dev)->gen >= 4) {
1741 I915_WRITE(DPLL_MD(crtc->pipe),
1742 crtc->config->dpll_hw_state.dpll_md);
1743 } else {
1744 /* The pixel multiplier can only be updated once the
1745 * DPLL is enabled and the clocks are stable.
1746 *
1747 * So write it again.
1748 */
1749 I915_WRITE(reg, dpll);
1750 }
1751
1752 /* We do this three times for luck */
1753 I915_WRITE(reg, dpll);
1754 POSTING_READ(reg);
1755 udelay(150); /* wait for warmup */
1756 I915_WRITE(reg, dpll);
1757 POSTING_READ(reg);
1758 udelay(150); /* wait for warmup */
1759 I915_WRITE(reg, dpll);
1760 POSTING_READ(reg);
1761 udelay(150); /* wait for warmup */
1762}
1763
1764/**
1765 * i9xx_disable_pll - disable a PLL
1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe PLL to disable
1768 *
1769 * Disable the PLL for @pipe, making sure the pipe is off first.
1770 *
1771 * Note! This is for pre-ILK only.
1772 */
1773static void i9xx_disable_pll(struct intel_crtc *crtc)
1774{
1775 struct drm_device *dev = crtc->base.dev;
1776 struct drm_i915_private *dev_priv = dev->dev_private;
1777 enum pipe pipe = crtc->pipe;
1778
1779 /* Disable DVO 2x clock on both PLLs if necessary */
1780 if (IS_I830(dev) &&
1781 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1782 intel_num_dvo_pipes(dev) == 1) {
1783 I915_WRITE(DPLL(PIPE_B),
1784 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1785 I915_WRITE(DPLL(PIPE_A),
1786 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1787 }
1788
1789 /* Don't disable pipe or pipe PLLs if needed */
1790 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1791 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1792 return;
1793
1794 /* Make sure the pipe isn't still relying on us */
1795 assert_pipe_disabled(dev_priv, pipe);
1796
1797 I915_WRITE(DPLL(pipe), 0);
1798 POSTING_READ(DPLL(pipe));
1799}
1800
1801static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1802{
1803 u32 val = 0;
1804
1805 /* Make sure the pipe isn't still relying on us */
1806 assert_pipe_disabled(dev_priv, pipe);
1807
1808 /*
1809 * Leave integrated clock source and reference clock enabled for pipe B.
1810 * The latter is needed for VGA hotplug / manual detection.
1811 */
1812 if (pipe == PIPE_B)
1813 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1814 I915_WRITE(DPLL(pipe), val);
1815 POSTING_READ(DPLL(pipe));
1816
1817}
1818
1819static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1820{
1821 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1822 u32 val;
1823
1824 /* Make sure the pipe isn't still relying on us */
1825 assert_pipe_disabled(dev_priv, pipe);
1826
1827 /* Set PLL en = 0 */
1828 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1829 if (pipe != PIPE_A)
1830 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1831 I915_WRITE(DPLL(pipe), val);
1832 POSTING_READ(DPLL(pipe));
1833
1834 mutex_lock(&dev_priv->sb_lock);
1835
1836 /* Disable 10bit clock to display controller */
1837 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1838 val &= ~DPIO_DCLKP_EN;
1839 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1840
1841 /* disable left/right clock distribution */
1842 if (pipe != PIPE_B) {
1843 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1844 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1845 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1846 } else {
1847 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1848 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1849 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1850 }
1851
1852 mutex_unlock(&dev_priv->sb_lock);
1853}
1854
1855void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1856 struct intel_digital_port *dport,
1857 unsigned int expected_mask)
1858{
1859 u32 port_mask;
1860 int dpll_reg;
1861
1862 switch (dport->port) {
1863 case PORT_B:
1864 port_mask = DPLL_PORTB_READY_MASK;
1865 dpll_reg = DPLL(0);
1866 break;
1867 case PORT_C:
1868 port_mask = DPLL_PORTC_READY_MASK;
1869 dpll_reg = DPLL(0);
1870 expected_mask <<= 4;
1871 break;
1872 case PORT_D:
1873 port_mask = DPLL_PORTD_READY_MASK;
1874 dpll_reg = DPIO_PHY_STATUS;
1875 break;
1876 default:
1877 BUG();
1878 }
1879
1880 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1881 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1882 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1883}
1884
1885static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1886{
1887 struct drm_device *dev = crtc->base.dev;
1888 struct drm_i915_private *dev_priv = dev->dev_private;
1889 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1890
1891 if (WARN_ON(pll == NULL))
1892 return;
1893
1894 WARN_ON(!pll->config.crtc_mask);
1895 if (pll->active == 0) {
1896 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1897 WARN_ON(pll->on);
1898 assert_shared_dpll_disabled(dev_priv, pll);
1899
1900 pll->mode_set(dev_priv, pll);
1901 }
1902}
1903
1904/**
1905 * intel_enable_shared_dpll - enable PCH PLL
1906 * @dev_priv: i915 private structure
1907 * @pipe: pipe PLL to enable
1908 *
1909 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1910 * drives the transcoder clock.
1911 */
1912static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1913{
1914 struct drm_device *dev = crtc->base.dev;
1915 struct drm_i915_private *dev_priv = dev->dev_private;
1916 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1917
1918 if (WARN_ON(pll == NULL))
1919 return;
1920
1921 if (WARN_ON(pll->config.crtc_mask == 0))
1922 return;
1923
1924 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1925 pll->name, pll->active, pll->on,
1926 crtc->base.base.id);
1927
1928 if (pll->active++) {
1929 WARN_ON(!pll->on);
1930 assert_shared_dpll_enabled(dev_priv, pll);
1931 return;
1932 }
1933 WARN_ON(pll->on);
1934
1935 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1936
1937 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1938 pll->enable(dev_priv, pll);
1939 pll->on = true;
1940}
1941
1942static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1943{
1944 struct drm_device *dev = crtc->base.dev;
1945 struct drm_i915_private *dev_priv = dev->dev_private;
1946 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1947
1948 /* PCH only available on ILK+ */
1949 BUG_ON(INTEL_INFO(dev)->gen < 5);
1950 if (WARN_ON(pll == NULL))
1951 return;
1952
1953 if (WARN_ON(pll->config.crtc_mask == 0))
1954 return;
1955
1956 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1957 pll->name, pll->active, pll->on,
1958 crtc->base.base.id);
1959
1960 if (WARN_ON(pll->active == 0)) {
1961 assert_shared_dpll_disabled(dev_priv, pll);
1962 return;
1963 }
1964
1965 assert_shared_dpll_enabled(dev_priv, pll);
1966 WARN_ON(!pll->on);
1967 if (--pll->active)
1968 return;
1969
1970 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1971 pll->disable(dev_priv, pll);
1972 pll->on = false;
1973
1974 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1975}
1976
1977static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1978 enum pipe pipe)
1979{
1980 struct drm_device *dev = dev_priv->dev;
1981 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1983 uint32_t reg, val, pipeconf_val;
1984
1985 /* PCH only available on ILK+ */
1986 BUG_ON(!HAS_PCH_SPLIT(dev));
1987
1988 /* Make sure PCH DPLL is enabled */
1989 assert_shared_dpll_enabled(dev_priv,
1990 intel_crtc_to_shared_dpll(intel_crtc));
1991
1992 /* FDI must be feeding us bits for PCH ports */
1993 assert_fdi_tx_enabled(dev_priv, pipe);
1994 assert_fdi_rx_enabled(dev_priv, pipe);
1995
1996 if (HAS_PCH_CPT(dev)) {
1997 /* Workaround: Set the timing override bit before enabling the
1998 * pch transcoder. */
1999 reg = TRANS_CHICKEN2(pipe);
2000 val = I915_READ(reg);
2001 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2002 I915_WRITE(reg, val);
2003 }
2004
2005 reg = PCH_TRANSCONF(pipe);
2006 val = I915_READ(reg);
2007 pipeconf_val = I915_READ(PIPECONF(pipe));
2008
2009 if (HAS_PCH_IBX(dev_priv->dev)) {
2010 /*
2011 * make the BPC in transcoder be consistent with
2012 * that in pipeconf reg.
2013 */
2014 val &= ~PIPECONF_BPC_MASK;
2015 val |= pipeconf_val & PIPECONF_BPC_MASK;
2016 }
2017
2018 val &= ~TRANS_INTERLACE_MASK;
2019 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2020 if (HAS_PCH_IBX(dev_priv->dev) &&
2021 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2022 val |= TRANS_LEGACY_INTERLACED_ILK;
2023 else
2024 val |= TRANS_INTERLACED;
2025 else
2026 val |= TRANS_PROGRESSIVE;
2027
2028 I915_WRITE(reg, val | TRANS_ENABLE);
2029 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2030 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2031}
2032
2033static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2034 enum transcoder cpu_transcoder)
2035{
2036 u32 val, pipeconf_val;
2037
2038 /* PCH only available on ILK+ */
2039 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2040
2041 /* FDI must be feeding us bits for PCH ports */
2042 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2043 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2044
2045 /* Workaround: set timing override bit. */
2046 val = I915_READ(_TRANSA_CHICKEN2);
2047 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2048 I915_WRITE(_TRANSA_CHICKEN2, val);
2049
2050 val = TRANS_ENABLE;
2051 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2052
2053 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2054 PIPECONF_INTERLACED_ILK)
2055 val |= TRANS_INTERLACED;
2056 else
2057 val |= TRANS_PROGRESSIVE;
2058
2059 I915_WRITE(LPT_TRANSCONF, val);
2060 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2061 DRM_ERROR("Failed to enable PCH transcoder\n");
2062}
2063
2064static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2065 enum pipe pipe)
2066{
2067 struct drm_device *dev = dev_priv->dev;
2068 uint32_t reg, val;
2069
2070 /* FDI relies on the transcoder */
2071 assert_fdi_tx_disabled(dev_priv, pipe);
2072 assert_fdi_rx_disabled(dev_priv, pipe);
2073
2074 /* Ports must be off as well */
2075 assert_pch_ports_disabled(dev_priv, pipe);
2076
2077 reg = PCH_TRANSCONF(pipe);
2078 val = I915_READ(reg);
2079 val &= ~TRANS_ENABLE;
2080 I915_WRITE(reg, val);
2081 /* wait for PCH transcoder off, transcoder state */
2082 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2083 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2084
2085 if (!HAS_PCH_IBX(dev)) {
2086 /* Workaround: Clear the timing override chicken bit again. */
2087 reg = TRANS_CHICKEN2(pipe);
2088 val = I915_READ(reg);
2089 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2090 I915_WRITE(reg, val);
2091 }
2092}
2093
2094static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2095{
2096 u32 val;
2097
2098 val = I915_READ(LPT_TRANSCONF);
2099 val &= ~TRANS_ENABLE;
2100 I915_WRITE(LPT_TRANSCONF, val);
2101 /* wait for PCH transcoder off, transcoder state */
2102 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2103 DRM_ERROR("Failed to disable PCH transcoder\n");
2104
2105 /* Workaround: clear timing override bit. */
2106 val = I915_READ(_TRANSA_CHICKEN2);
2107 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2108 I915_WRITE(_TRANSA_CHICKEN2, val);
2109}
2110
2111/**
2112 * intel_enable_pipe - enable a pipe, asserting requirements
2113 * @crtc: crtc responsible for the pipe
2114 *
2115 * Enable @crtc's pipe, making sure that various hardware specific requirements
2116 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2117 */
2118static void intel_enable_pipe(struct intel_crtc *crtc)
2119{
2120 struct drm_device *dev = crtc->base.dev;
2121 struct drm_i915_private *dev_priv = dev->dev_private;
2122 enum pipe pipe = crtc->pipe;
2123 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2124 pipe);
2125 enum pipe pch_transcoder;
2126 int reg;
2127 u32 val;
2128
2129 assert_planes_disabled(dev_priv, pipe);
2130 assert_cursor_disabled(dev_priv, pipe);
2131 assert_sprites_disabled(dev_priv, pipe);
2132
2133 if (HAS_PCH_LPT(dev_priv->dev))
2134 pch_transcoder = TRANSCODER_A;
2135 else
2136 pch_transcoder = pipe;
2137
2138 /*
2139 * A pipe without a PLL won't actually be able to drive bits from
2140 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2141 * need the check.
2142 */
2143 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2144 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2145 assert_dsi_pll_enabled(dev_priv);
2146 else
2147 assert_pll_enabled(dev_priv, pipe);
2148 else {
2149 if (crtc->config->has_pch_encoder) {
2150 /* if driving the PCH, we need FDI enabled */
2151 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2152 assert_fdi_tx_pll_enabled(dev_priv,
2153 (enum pipe) cpu_transcoder);
2154 }
2155 /* FIXME: assert CPU port conditions for SNB+ */
2156 }
2157
2158 reg = PIPECONF(cpu_transcoder);
2159 val = I915_READ(reg);
2160 if (val & PIPECONF_ENABLE) {
2161 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2162 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2163 return;
2164 }
2165
2166 I915_WRITE(reg, val | PIPECONF_ENABLE);
2167 POSTING_READ(reg);
2168}
2169
2170/**
2171 * intel_disable_pipe - disable a pipe, asserting requirements
2172 * @crtc: crtc whose pipes is to be disabled
2173 *
2174 * Disable the pipe of @crtc, making sure that various hardware
2175 * specific requirements are met, if applicable, e.g. plane
2176 * disabled, panel fitter off, etc.
2177 *
2178 * Will wait until the pipe has shut down before returning.
2179 */
2180static void intel_disable_pipe(struct intel_crtc *crtc)
2181{
2182 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2183 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2184 enum pipe pipe = crtc->pipe;
2185 int reg;
2186 u32 val;
2187
2188 /*
2189 * Make sure planes won't keep trying to pump pixels to us,
2190 * or we might hang the display.
2191 */
2192 assert_planes_disabled(dev_priv, pipe);
2193 assert_cursor_disabled(dev_priv, pipe);
2194 assert_sprites_disabled(dev_priv, pipe);
2195
2196 reg = PIPECONF(cpu_transcoder);
2197 val = I915_READ(reg);
2198 if ((val & PIPECONF_ENABLE) == 0)
2199 return;
2200
2201 /*
2202 * Double wide has implications for planes
2203 * so best keep it disabled when not needed.
2204 */
2205 if (crtc->config->double_wide)
2206 val &= ~PIPECONF_DOUBLE_WIDE;
2207
2208 /* Don't disable pipe or pipe PLLs if needed */
2209 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2210 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2211 val &= ~PIPECONF_ENABLE;
2212
2213 I915_WRITE(reg, val);
2214 if ((val & PIPECONF_ENABLE) == 0)
2215 intel_wait_for_pipe_off(crtc);
2216}
2217
2218/**
2219 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2220 * @plane: plane to be enabled
2221 * @crtc: crtc for the plane
2222 *
2223 * Enable @plane on @crtc, making sure that the pipe is running first.
2224 */
2225static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2226 struct drm_crtc *crtc)
2227{
2228 struct drm_device *dev = plane->dev;
2229 struct drm_i915_private *dev_priv = dev->dev_private;
2230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2231
2232 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2233 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2234 to_intel_plane_state(plane->state)->visible = true;
2235
2236 dev_priv->display.update_primary_plane(crtc, plane->fb,
2237 crtc->x, crtc->y);
2238}
2239
2240static bool need_vtd_wa(struct drm_device *dev)
2241{
2242#ifdef CONFIG_INTEL_IOMMU
2243 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2244 return true;
2245#endif
2246 return false;
2247}
2248
2249unsigned int
2250intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2251 uint64_t fb_format_modifier)
2252{
2253 unsigned int tile_height;
2254 uint32_t pixel_bytes;
2255
2256 switch (fb_format_modifier) {
2257 case DRM_FORMAT_MOD_NONE:
2258 tile_height = 1;
2259 break;
2260 case I915_FORMAT_MOD_X_TILED:
2261 tile_height = IS_GEN2(dev) ? 16 : 8;
2262 break;
2263 case I915_FORMAT_MOD_Y_TILED:
2264 tile_height = 32;
2265 break;
2266 case I915_FORMAT_MOD_Yf_TILED:
2267 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2268 switch (pixel_bytes) {
2269 default:
2270 case 1:
2271 tile_height = 64;
2272 break;
2273 case 2:
2274 case 4:
2275 tile_height = 32;
2276 break;
2277 case 8:
2278 tile_height = 16;
2279 break;
2280 case 16:
2281 WARN_ONCE(1,
2282 "128-bit pixels are not supported for display!");
2283 tile_height = 16;
2284 break;
2285 }
2286 break;
2287 default:
2288 MISSING_CASE(fb_format_modifier);
2289 tile_height = 1;
2290 break;
2291 }
2292
2293 return tile_height;
2294}
2295
2296unsigned int
2297intel_fb_align_height(struct drm_device *dev, unsigned int height,
2298 uint32_t pixel_format, uint64_t fb_format_modifier)
2299{
2300 return ALIGN(height, intel_tile_height(dev, pixel_format,
2301 fb_format_modifier));
2302}
2303
2304static int
2305intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2306 const struct drm_plane_state *plane_state)
2307{
2308 struct intel_rotation_info *info = &view->rotation_info;
2309
2310 *view = i915_ggtt_view_normal;
2311
2312 if (!plane_state)
2313 return 0;
2314
2315 if (!intel_rotation_90_or_270(plane_state->rotation))
2316 return 0;
2317
2318 *view = i915_ggtt_view_rotated;
2319
2320 info->height = fb->height;
2321 info->pixel_format = fb->pixel_format;
2322 info->pitch = fb->pitches[0];
2323 info->fb_modifier = fb->modifier[0];
2324
2325 return 0;
2326}
2327
2328int
2329intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2330 struct drm_framebuffer *fb,
2331 const struct drm_plane_state *plane_state,
2332 struct intel_engine_cs *pipelined)
2333{
2334 struct drm_device *dev = fb->dev;
2335 struct drm_i915_private *dev_priv = dev->dev_private;
2336 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2337 struct i915_ggtt_view view;
2338 u32 alignment;
2339 int ret;
2340
2341 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2342
2343 switch (fb->modifier[0]) {
2344 case DRM_FORMAT_MOD_NONE:
2345 if (INTEL_INFO(dev)->gen >= 9)
2346 alignment = 256 * 1024;
2347 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2348 alignment = 128 * 1024;
2349 else if (INTEL_INFO(dev)->gen >= 4)
2350 alignment = 4 * 1024;
2351 else
2352 alignment = 64 * 1024;
2353 break;
2354 case I915_FORMAT_MOD_X_TILED:
2355 if (INTEL_INFO(dev)->gen >= 9)
2356 alignment = 256 * 1024;
2357 else {
2358 /* pin() will align the object as required by fence */
2359 alignment = 0;
2360 }
2361 break;
2362 case I915_FORMAT_MOD_Y_TILED:
2363 case I915_FORMAT_MOD_Yf_TILED:
2364 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2365 "Y tiling bo slipped through, driver bug!\n"))
2366 return -EINVAL;
2367 alignment = 1 * 1024 * 1024;
2368 break;
2369 default:
2370 MISSING_CASE(fb->modifier[0]);
2371 return -EINVAL;
2372 }
2373
2374 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2375 if (ret)
2376 return ret;
2377
2378 /* Note that the w/a also requires 64 PTE of padding following the
2379 * bo. We currently fill all unused PTE with the shadow page and so
2380 * we should always have valid PTE following the scanout preventing
2381 * the VT-d warning.
2382 */
2383 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2384 alignment = 256 * 1024;
2385
2386 /*
2387 * Global gtt pte registers are special registers which actually forward
2388 * writes to a chunk of system memory. Which means that there is no risk
2389 * that the register values disappear as soon as we call
2390 * intel_runtime_pm_put(), so it is correct to wrap only the
2391 * pin/unpin/fence and not more.
2392 */
2393 intel_runtime_pm_get(dev_priv);
2394
2395 dev_priv->mm.interruptible = false;
2396 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2397 &view);
2398 if (ret)
2399 goto err_interruptible;
2400
2401 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2402 * fence, whereas 965+ only requires a fence if using
2403 * framebuffer compression. For simplicity, we always install
2404 * a fence as the cost is not that onerous.
2405 */
2406 ret = i915_gem_object_get_fence(obj);
2407 if (ret)
2408 goto err_unpin;
2409
2410 i915_gem_object_pin_fence(obj);
2411
2412 dev_priv->mm.interruptible = true;
2413 intel_runtime_pm_put(dev_priv);
2414 return 0;
2415
2416err_unpin:
2417 i915_gem_object_unpin_from_display_plane(obj, &view);
2418err_interruptible:
2419 dev_priv->mm.interruptible = true;
2420 intel_runtime_pm_put(dev_priv);
2421 return ret;
2422}
2423
2424static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2425 const struct drm_plane_state *plane_state)
2426{
2427 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2428 struct i915_ggtt_view view;
2429 int ret;
2430
2431 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2432
2433 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2434 WARN_ONCE(ret, "Couldn't get view from plane state!");
2435
2436 i915_gem_object_unpin_fence(obj);
2437 i915_gem_object_unpin_from_display_plane(obj, &view);
2438}
2439
2440/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2441 * is assumed to be a power-of-two. */
2442unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2443 unsigned int tiling_mode,
2444 unsigned int cpp,
2445 unsigned int pitch)
2446{
2447 if (tiling_mode != I915_TILING_NONE) {
2448 unsigned int tile_rows, tiles;
2449
2450 tile_rows = *y / 8;
2451 *y %= 8;
2452
2453 tiles = *x / (512/cpp);
2454 *x %= 512/cpp;
2455
2456 return tile_rows * pitch * 8 + tiles * 4096;
2457 } else {
2458 unsigned int offset;
2459
2460 offset = *y * pitch + *x * cpp;
2461 *y = 0;
2462 *x = (offset & 4095) / cpp;
2463 return offset & -4096;
2464 }
2465}
2466
2467static int i9xx_format_to_fourcc(int format)
2468{
2469 switch (format) {
2470 case DISPPLANE_8BPP:
2471 return DRM_FORMAT_C8;
2472 case DISPPLANE_BGRX555:
2473 return DRM_FORMAT_XRGB1555;
2474 case DISPPLANE_BGRX565:
2475 return DRM_FORMAT_RGB565;
2476 default:
2477 case DISPPLANE_BGRX888:
2478 return DRM_FORMAT_XRGB8888;
2479 case DISPPLANE_RGBX888:
2480 return DRM_FORMAT_XBGR8888;
2481 case DISPPLANE_BGRX101010:
2482 return DRM_FORMAT_XRGB2101010;
2483 case DISPPLANE_RGBX101010:
2484 return DRM_FORMAT_XBGR2101010;
2485 }
2486}
2487
2488static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2489{
2490 switch (format) {
2491 case PLANE_CTL_FORMAT_RGB_565:
2492 return DRM_FORMAT_RGB565;
2493 default:
2494 case PLANE_CTL_FORMAT_XRGB_8888:
2495 if (rgb_order) {
2496 if (alpha)
2497 return DRM_FORMAT_ABGR8888;
2498 else
2499 return DRM_FORMAT_XBGR8888;
2500 } else {
2501 if (alpha)
2502 return DRM_FORMAT_ARGB8888;
2503 else
2504 return DRM_FORMAT_XRGB8888;
2505 }
2506 case PLANE_CTL_FORMAT_XRGB_2101010:
2507 if (rgb_order)
2508 return DRM_FORMAT_XBGR2101010;
2509 else
2510 return DRM_FORMAT_XRGB2101010;
2511 }
2512}
2513
2514static bool
2515intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2516 struct intel_initial_plane_config *plane_config)
2517{
2518 struct drm_device *dev = crtc->base.dev;
2519 struct drm_i915_gem_object *obj = NULL;
2520 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2521 struct drm_framebuffer *fb = &plane_config->fb->base;
2522 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2523 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2524 PAGE_SIZE);
2525
2526 size_aligned -= base_aligned;
2527
2528 if (plane_config->size == 0)
2529 return false;
2530
2531 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2532 base_aligned,
2533 base_aligned,
2534 size_aligned);
2535 if (!obj)
2536 return false;
2537
2538 obj->tiling_mode = plane_config->tiling;
2539 if (obj->tiling_mode == I915_TILING_X)
2540 obj->stride = fb->pitches[0];
2541
2542 mode_cmd.pixel_format = fb->pixel_format;
2543 mode_cmd.width = fb->width;
2544 mode_cmd.height = fb->height;
2545 mode_cmd.pitches[0] = fb->pitches[0];
2546 mode_cmd.modifier[0] = fb->modifier[0];
2547 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2548
2549 mutex_lock(&dev->struct_mutex);
2550 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2551 &mode_cmd, obj)) {
2552 DRM_DEBUG_KMS("intel fb init failed\n");
2553 goto out_unref_obj;
2554 }
2555 mutex_unlock(&dev->struct_mutex);
2556
2557 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2558 return true;
2559
2560out_unref_obj:
2561 drm_gem_object_unreference(&obj->base);
2562 mutex_unlock(&dev->struct_mutex);
2563 return false;
2564}
2565
2566/* Update plane->state->fb to match plane->fb after driver-internal updates */
2567static void
2568update_state_fb(struct drm_plane *plane)
2569{
2570 if (plane->fb == plane->state->fb)
2571 return;
2572
2573 if (plane->state->fb)
2574 drm_framebuffer_unreference(plane->state->fb);
2575 plane->state->fb = plane->fb;
2576 if (plane->state->fb)
2577 drm_framebuffer_reference(plane->state->fb);
2578}
2579
2580static void
2581intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2582 struct intel_initial_plane_config *plane_config)
2583{
2584 struct drm_device *dev = intel_crtc->base.dev;
2585 struct drm_i915_private *dev_priv = dev->dev_private;
2586 struct drm_crtc *c;
2587 struct intel_crtc *i;
2588 struct drm_i915_gem_object *obj;
2589 struct drm_plane *primary = intel_crtc->base.primary;
2590 struct drm_framebuffer *fb;
2591
2592 if (!plane_config->fb)
2593 return;
2594
2595 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2596 fb = &plane_config->fb->base;
2597 goto valid_fb;
2598 }
2599
2600 kfree(plane_config->fb);
2601
2602 /*
2603 * Failed to alloc the obj, check to see if we should share
2604 * an fb with another CRTC instead
2605 */
2606 for_each_crtc(dev, c) {
2607 i = to_intel_crtc(c);
2608
2609 if (c == &intel_crtc->base)
2610 continue;
2611
2612 if (!i->active)
2613 continue;
2614
2615 fb = c->primary->fb;
2616 if (!fb)
2617 continue;
2618
2619 obj = intel_fb_obj(fb);
2620 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2621 drm_framebuffer_reference(fb);
2622 goto valid_fb;
2623 }
2624 }
2625
2626 return;
2627
2628valid_fb:
2629 obj = intel_fb_obj(fb);
2630 if (obj->tiling_mode != I915_TILING_NONE)
2631 dev_priv->preserve_bios_swizzle = true;
2632
2633 primary->fb = fb;
2634 primary->crtc = primary->state->crtc = &intel_crtc->base;
2635 update_state_fb(primary);
2636 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2637 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2638}
2639
2640static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2641 struct drm_framebuffer *fb,
2642 int x, int y)
2643{
2644 struct drm_device *dev = crtc->dev;
2645 struct drm_i915_private *dev_priv = dev->dev_private;
2646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2647 struct drm_plane *primary = crtc->primary;
2648 bool visible = to_intel_plane_state(primary->state)->visible;
2649 struct drm_i915_gem_object *obj;
2650 int plane = intel_crtc->plane;
2651 unsigned long linear_offset;
2652 u32 dspcntr;
2653 u32 reg = DSPCNTR(plane);
2654 int pixel_size;
2655
2656 if (!visible || !fb) {
2657 I915_WRITE(reg, 0);
2658 if (INTEL_INFO(dev)->gen >= 4)
2659 I915_WRITE(DSPSURF(plane), 0);
2660 else
2661 I915_WRITE(DSPADDR(plane), 0);
2662 POSTING_READ(reg);
2663 return;
2664 }
2665
2666 obj = intel_fb_obj(fb);
2667 if (WARN_ON(obj == NULL))
2668 return;
2669
2670 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2671
2672 dspcntr = DISPPLANE_GAMMA_ENABLE;
2673
2674 dspcntr |= DISPLAY_PLANE_ENABLE;
2675
2676 if (INTEL_INFO(dev)->gen < 4) {
2677 if (intel_crtc->pipe == PIPE_B)
2678 dspcntr |= DISPPLANE_SEL_PIPE_B;
2679
2680 /* pipesrc and dspsize control the size that is scaled from,
2681 * which should always be the user's requested size.
2682 */
2683 I915_WRITE(DSPSIZE(plane),
2684 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2685 (intel_crtc->config->pipe_src_w - 1));
2686 I915_WRITE(DSPPOS(plane), 0);
2687 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2688 I915_WRITE(PRIMSIZE(plane),
2689 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2690 (intel_crtc->config->pipe_src_w - 1));
2691 I915_WRITE(PRIMPOS(plane), 0);
2692 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2693 }
2694
2695 switch (fb->pixel_format) {
2696 case DRM_FORMAT_C8:
2697 dspcntr |= DISPPLANE_8BPP;
2698 break;
2699 case DRM_FORMAT_XRGB1555:
2700 dspcntr |= DISPPLANE_BGRX555;
2701 break;
2702 case DRM_FORMAT_RGB565:
2703 dspcntr |= DISPPLANE_BGRX565;
2704 break;
2705 case DRM_FORMAT_XRGB8888:
2706 dspcntr |= DISPPLANE_BGRX888;
2707 break;
2708 case DRM_FORMAT_XBGR8888:
2709 dspcntr |= DISPPLANE_RGBX888;
2710 break;
2711 case DRM_FORMAT_XRGB2101010:
2712 dspcntr |= DISPPLANE_BGRX101010;
2713 break;
2714 case DRM_FORMAT_XBGR2101010:
2715 dspcntr |= DISPPLANE_RGBX101010;
2716 break;
2717 default:
2718 BUG();
2719 }
2720
2721 if (INTEL_INFO(dev)->gen >= 4 &&
2722 obj->tiling_mode != I915_TILING_NONE)
2723 dspcntr |= DISPPLANE_TILED;
2724
2725 if (IS_G4X(dev))
2726 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2727
2728 linear_offset = y * fb->pitches[0] + x * pixel_size;
2729
2730 if (INTEL_INFO(dev)->gen >= 4) {
2731 intel_crtc->dspaddr_offset =
2732 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2733 pixel_size,
2734 fb->pitches[0]);
2735 linear_offset -= intel_crtc->dspaddr_offset;
2736 } else {
2737 intel_crtc->dspaddr_offset = linear_offset;
2738 }
2739
2740 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2741 dspcntr |= DISPPLANE_ROTATE_180;
2742
2743 x += (intel_crtc->config->pipe_src_w - 1);
2744 y += (intel_crtc->config->pipe_src_h - 1);
2745
2746 /* Finding the last pixel of the last line of the display
2747 data and adding to linear_offset*/
2748 linear_offset +=
2749 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2750 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2751 }
2752
2753 I915_WRITE(reg, dspcntr);
2754
2755 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2756 if (INTEL_INFO(dev)->gen >= 4) {
2757 I915_WRITE(DSPSURF(plane),
2758 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2759 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2760 I915_WRITE(DSPLINOFF(plane), linear_offset);
2761 } else
2762 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2763 POSTING_READ(reg);
2764}
2765
2766static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2767 struct drm_framebuffer *fb,
2768 int x, int y)
2769{
2770 struct drm_device *dev = crtc->dev;
2771 struct drm_i915_private *dev_priv = dev->dev_private;
2772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2773 struct drm_plane *primary = crtc->primary;
2774 bool visible = to_intel_plane_state(primary->state)->visible;
2775 struct drm_i915_gem_object *obj;
2776 int plane = intel_crtc->plane;
2777 unsigned long linear_offset;
2778 u32 dspcntr;
2779 u32 reg = DSPCNTR(plane);
2780 int pixel_size;
2781
2782 if (!visible || !fb) {
2783 I915_WRITE(reg, 0);
2784 I915_WRITE(DSPSURF(plane), 0);
2785 POSTING_READ(reg);
2786 return;
2787 }
2788
2789 obj = intel_fb_obj(fb);
2790 if (WARN_ON(obj == NULL))
2791 return;
2792
2793 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2794
2795 dspcntr = DISPPLANE_GAMMA_ENABLE;
2796
2797 dspcntr |= DISPLAY_PLANE_ENABLE;
2798
2799 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2800 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2801
2802 switch (fb->pixel_format) {
2803 case DRM_FORMAT_C8:
2804 dspcntr |= DISPPLANE_8BPP;
2805 break;
2806 case DRM_FORMAT_RGB565:
2807 dspcntr |= DISPPLANE_BGRX565;
2808 break;
2809 case DRM_FORMAT_XRGB8888:
2810 dspcntr |= DISPPLANE_BGRX888;
2811 break;
2812 case DRM_FORMAT_XBGR8888:
2813 dspcntr |= DISPPLANE_RGBX888;
2814 break;
2815 case DRM_FORMAT_XRGB2101010:
2816 dspcntr |= DISPPLANE_BGRX101010;
2817 break;
2818 case DRM_FORMAT_XBGR2101010:
2819 dspcntr |= DISPPLANE_RGBX101010;
2820 break;
2821 default:
2822 BUG();
2823 }
2824
2825 if (obj->tiling_mode != I915_TILING_NONE)
2826 dspcntr |= DISPPLANE_TILED;
2827
2828 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2829 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2830
2831 linear_offset = y * fb->pitches[0] + x * pixel_size;
2832 intel_crtc->dspaddr_offset =
2833 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2834 pixel_size,
2835 fb->pitches[0]);
2836 linear_offset -= intel_crtc->dspaddr_offset;
2837 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2838 dspcntr |= DISPPLANE_ROTATE_180;
2839
2840 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2841 x += (intel_crtc->config->pipe_src_w - 1);
2842 y += (intel_crtc->config->pipe_src_h - 1);
2843
2844 /* Finding the last pixel of the last line of the display
2845 data and adding to linear_offset*/
2846 linear_offset +=
2847 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2848 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2849 }
2850 }
2851
2852 I915_WRITE(reg, dspcntr);
2853
2854 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2855 I915_WRITE(DSPSURF(plane),
2856 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2857 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2858 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2859 } else {
2860 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2861 I915_WRITE(DSPLINOFF(plane), linear_offset);
2862 }
2863 POSTING_READ(reg);
2864}
2865
2866u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2867 uint32_t pixel_format)
2868{
2869 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2870
2871 /*
2872 * The stride is either expressed as a multiple of 64 bytes
2873 * chunks for linear buffers or in number of tiles for tiled
2874 * buffers.
2875 */
2876 switch (fb_modifier) {
2877 case DRM_FORMAT_MOD_NONE:
2878 return 64;
2879 case I915_FORMAT_MOD_X_TILED:
2880 if (INTEL_INFO(dev)->gen == 2)
2881 return 128;
2882 return 512;
2883 case I915_FORMAT_MOD_Y_TILED:
2884 /* No need to check for old gens and Y tiling since this is
2885 * about the display engine and those will be blocked before
2886 * we get here.
2887 */
2888 return 128;
2889 case I915_FORMAT_MOD_Yf_TILED:
2890 if (bits_per_pixel == 8)
2891 return 64;
2892 else
2893 return 128;
2894 default:
2895 MISSING_CASE(fb_modifier);
2896 return 64;
2897 }
2898}
2899
2900unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2901 struct drm_i915_gem_object *obj)
2902{
2903 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2904
2905 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2906 view = &i915_ggtt_view_rotated;
2907
2908 return i915_gem_obj_ggtt_offset_view(obj, view);
2909}
2910
2911/*
2912 * This function detaches (aka. unbinds) unused scalers in hardware
2913 */
2914void skl_detach_scalers(struct intel_crtc *intel_crtc)
2915{
2916 struct drm_device *dev;
2917 struct drm_i915_private *dev_priv;
2918 struct intel_crtc_scaler_state *scaler_state;
2919 int i;
2920
2921 if (!intel_crtc || !intel_crtc->config)
2922 return;
2923
2924 dev = intel_crtc->base.dev;
2925 dev_priv = dev->dev_private;
2926 scaler_state = &intel_crtc->config->scaler_state;
2927
2928 /* loop through and disable scalers that aren't in use */
2929 for (i = 0; i < intel_crtc->num_scalers; i++) {
2930 if (!scaler_state->scalers[i].in_use) {
2931 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2932 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2933 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2934 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2935 intel_crtc->base.base.id, intel_crtc->pipe, i);
2936 }
2937 }
2938}
2939
2940u32 skl_plane_ctl_format(uint32_t pixel_format)
2941{
2942 switch (pixel_format) {
2943 case DRM_FORMAT_C8:
2944 return PLANE_CTL_FORMAT_INDEXED;
2945 case DRM_FORMAT_RGB565:
2946 return PLANE_CTL_FORMAT_RGB_565;
2947 case DRM_FORMAT_XBGR8888:
2948 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2949 case DRM_FORMAT_XRGB8888:
2950 return PLANE_CTL_FORMAT_XRGB_8888;
2951 /*
2952 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2953 * to be already pre-multiplied. We need to add a knob (or a different
2954 * DRM_FORMAT) for user-space to configure that.
2955 */
2956 case DRM_FORMAT_ABGR8888:
2957 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2958 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2959 case DRM_FORMAT_ARGB8888:
2960 return PLANE_CTL_FORMAT_XRGB_8888 |
2961 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2962 case DRM_FORMAT_XRGB2101010:
2963 return PLANE_CTL_FORMAT_XRGB_2101010;
2964 case DRM_FORMAT_XBGR2101010:
2965 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2966 case DRM_FORMAT_YUYV:
2967 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2968 case DRM_FORMAT_YVYU:
2969 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2970 case DRM_FORMAT_UYVY:
2971 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2972 case DRM_FORMAT_VYUY:
2973 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2974 default:
2975 MISSING_CASE(pixel_format);
2976 }
2977
2978 return 0;
2979}
2980
2981u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2982{
2983 switch (fb_modifier) {
2984 case DRM_FORMAT_MOD_NONE:
2985 break;
2986 case I915_FORMAT_MOD_X_TILED:
2987 return PLANE_CTL_TILED_X;
2988 case I915_FORMAT_MOD_Y_TILED:
2989 return PLANE_CTL_TILED_Y;
2990 case I915_FORMAT_MOD_Yf_TILED:
2991 return PLANE_CTL_TILED_YF;
2992 default:
2993 MISSING_CASE(fb_modifier);
2994 }
2995
2996 return 0;
2997}
2998
2999u32 skl_plane_ctl_rotation(unsigned int rotation)
3000{
3001 switch (rotation) {
3002 case BIT(DRM_ROTATE_0):
3003 break;
3004 /*
3005 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3006 * while i915 HW rotation is clockwise, thats why this swapping.
3007 */
3008 case BIT(DRM_ROTATE_90):
3009 return PLANE_CTL_ROTATE_270;
3010 case BIT(DRM_ROTATE_180):
3011 return PLANE_CTL_ROTATE_180;
3012 case BIT(DRM_ROTATE_270):
3013 return PLANE_CTL_ROTATE_90;
3014 default:
3015 MISSING_CASE(rotation);
3016 }
3017
3018 return 0;
3019}
3020
3021static void skylake_update_primary_plane(struct drm_crtc *crtc,
3022 struct drm_framebuffer *fb,
3023 int x, int y)
3024{
3025 struct drm_device *dev = crtc->dev;
3026 struct drm_i915_private *dev_priv = dev->dev_private;
3027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3028 struct drm_plane *plane = crtc->primary;
3029 bool visible = to_intel_plane_state(plane->state)->visible;
3030 struct drm_i915_gem_object *obj;
3031 int pipe = intel_crtc->pipe;
3032 u32 plane_ctl, stride_div, stride;
3033 u32 tile_height, plane_offset, plane_size;
3034 unsigned int rotation;
3035 int x_offset, y_offset;
3036 unsigned long surf_addr;
3037 struct intel_crtc_state *crtc_state = intel_crtc->config;
3038 struct intel_plane_state *plane_state;
3039 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3040 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3041 int scaler_id = -1;
3042
3043 plane_state = to_intel_plane_state(plane->state);
3044
3045 if (!visible || !fb) {
3046 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3047 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3048 POSTING_READ(PLANE_CTL(pipe, 0));
3049 return;
3050 }
3051
3052 plane_ctl = PLANE_CTL_ENABLE |
3053 PLANE_CTL_PIPE_GAMMA_ENABLE |
3054 PLANE_CTL_PIPE_CSC_ENABLE;
3055
3056 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3057 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3058 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3059
3060 rotation = plane->state->rotation;
3061 plane_ctl |= skl_plane_ctl_rotation(rotation);
3062
3063 obj = intel_fb_obj(fb);
3064 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3065 fb->pixel_format);
3066 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3067
3068 /*
3069 * FIXME: intel_plane_state->src, dst aren't set when transitional
3070 * update_plane helpers are called from legacy paths.
3071 * Once full atomic crtc is available, below check can be avoided.
3072 */
3073 if (drm_rect_width(&plane_state->src)) {
3074 scaler_id = plane_state->scaler_id;
3075 src_x = plane_state->src.x1 >> 16;
3076 src_y = plane_state->src.y1 >> 16;
3077 src_w = drm_rect_width(&plane_state->src) >> 16;
3078 src_h = drm_rect_height(&plane_state->src) >> 16;
3079 dst_x = plane_state->dst.x1;
3080 dst_y = plane_state->dst.y1;
3081 dst_w = drm_rect_width(&plane_state->dst);
3082 dst_h = drm_rect_height(&plane_state->dst);
3083
3084 WARN_ON(x != src_x || y != src_y);
3085 } else {
3086 src_w = intel_crtc->config->pipe_src_w;
3087 src_h = intel_crtc->config->pipe_src_h;
3088 }
3089
3090 if (intel_rotation_90_or_270(rotation)) {
3091 /* stride = Surface height in tiles */
3092 tile_height = intel_tile_height(dev, fb->pixel_format,
3093 fb->modifier[0]);
3094 stride = DIV_ROUND_UP(fb->height, tile_height);
3095 x_offset = stride * tile_height - y - src_h;
3096 y_offset = x;
3097 plane_size = (src_w - 1) << 16 | (src_h - 1);
3098 } else {
3099 stride = fb->pitches[0] / stride_div;
3100 x_offset = x;
3101 y_offset = y;
3102 plane_size = (src_h - 1) << 16 | (src_w - 1);
3103 }
3104 plane_offset = y_offset << 16 | x_offset;
3105
3106 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3107 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3108 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3109 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3110
3111 if (scaler_id >= 0) {
3112 uint32_t ps_ctrl = 0;
3113
3114 WARN_ON(!dst_w || !dst_h);
3115 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3116 crtc_state->scaler_state.scalers[scaler_id].mode;
3117 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3118 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3119 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3120 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3121 I915_WRITE(PLANE_POS(pipe, 0), 0);
3122 } else {
3123 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3124 }
3125
3126 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3127
3128 POSTING_READ(PLANE_SURF(pipe, 0));
3129}
3130
3131/* Assume fb object is pinned & idle & fenced and just update base pointers */
3132static int
3133intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3134 int x, int y, enum mode_set_atomic state)
3135{
3136 struct drm_device *dev = crtc->dev;
3137 struct drm_i915_private *dev_priv = dev->dev_private;
3138
3139 if (dev_priv->display.disable_fbc)
3140 dev_priv->display.disable_fbc(dev);
3141
3142 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3143
3144 return 0;
3145}
3146
3147static void intel_complete_page_flips(struct drm_device *dev)
3148{
3149 struct drm_crtc *crtc;
3150
3151 for_each_crtc(dev, crtc) {
3152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3153 enum plane plane = intel_crtc->plane;
3154
3155 intel_prepare_page_flip(dev, plane);
3156 intel_finish_page_flip_plane(dev, plane);
3157 }
3158}
3159
3160static void intel_update_primary_planes(struct drm_device *dev)
3161{
3162 struct drm_i915_private *dev_priv = dev->dev_private;
3163 struct drm_crtc *crtc;
3164
3165 for_each_crtc(dev, crtc) {
3166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3167
3168 drm_modeset_lock(&crtc->mutex, NULL);
3169 /*
3170 * FIXME: Once we have proper support for primary planes (and
3171 * disabling them without disabling the entire crtc) allow again
3172 * a NULL crtc->primary->fb.
3173 */
3174 if (intel_crtc->active && crtc->primary->fb)
3175 dev_priv->display.update_primary_plane(crtc,
3176 crtc->primary->fb,
3177 crtc->x,
3178 crtc->y);
3179 drm_modeset_unlock(&crtc->mutex);
3180 }
3181}
3182
3183void intel_prepare_reset(struct drm_device *dev)
3184{
3185 /* no reset support for gen2 */
3186 if (IS_GEN2(dev))
3187 return;
3188
3189 /* reset doesn't touch the display */
3190 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3191 return;
3192
3193 drm_modeset_lock_all(dev);
3194 /*
3195 * Disabling the crtcs gracefully seems nicer. Also the
3196 * g33 docs say we should at least disable all the planes.
3197 */
3198 intel_display_suspend(dev);
3199}
3200
3201void intel_finish_reset(struct drm_device *dev)
3202{
3203 struct drm_i915_private *dev_priv = to_i915(dev);
3204
3205 /*
3206 * Flips in the rings will be nuked by the reset,
3207 * so complete all pending flips so that user space
3208 * will get its events and not get stuck.
3209 */
3210 intel_complete_page_flips(dev);
3211
3212 /* no reset support for gen2 */
3213 if (IS_GEN2(dev))
3214 return;
3215
3216 /* reset doesn't touch the display */
3217 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3218 /*
3219 * Flips in the rings have been nuked by the reset,
3220 * so update the base address of all primary
3221 * planes to the the last fb to make sure we're
3222 * showing the correct fb after a reset.
3223 */
3224 intel_update_primary_planes(dev);
3225 return;
3226 }
3227
3228 /*
3229 * The display has been reset as well,
3230 * so need a full re-initialization.
3231 */
3232 intel_runtime_pm_disable_interrupts(dev_priv);
3233 intel_runtime_pm_enable_interrupts(dev_priv);
3234
3235 intel_modeset_init_hw(dev);
3236
3237 spin_lock_irq(&dev_priv->irq_lock);
3238 if (dev_priv->display.hpd_irq_setup)
3239 dev_priv->display.hpd_irq_setup(dev);
3240 spin_unlock_irq(&dev_priv->irq_lock);
3241
3242 intel_modeset_setup_hw_state(dev, true);
3243
3244 intel_hpd_init(dev_priv);
3245
3246 drm_modeset_unlock_all(dev);
3247}
3248
3249static void
3250intel_finish_fb(struct drm_framebuffer *old_fb)
3251{
3252 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3253 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3254 bool was_interruptible = dev_priv->mm.interruptible;
3255 int ret;
3256
3257 /* Big Hammer, we also need to ensure that any pending
3258 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3259 * current scanout is retired before unpinning the old
3260 * framebuffer. Note that we rely on userspace rendering
3261 * into the buffer attached to the pipe they are waiting
3262 * on. If not, userspace generates a GPU hang with IPEHR
3263 * point to the MI_WAIT_FOR_EVENT.
3264 *
3265 * This should only fail upon a hung GPU, in which case we
3266 * can safely continue.
3267 */
3268 dev_priv->mm.interruptible = false;
3269 ret = i915_gem_object_wait_rendering(obj, true);
3270 dev_priv->mm.interruptible = was_interruptible;
3271
3272 WARN_ON(ret);
3273}
3274
3275static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3276{
3277 struct drm_device *dev = crtc->dev;
3278 struct drm_i915_private *dev_priv = dev->dev_private;
3279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3280 bool pending;
3281
3282 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3283 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3284 return false;
3285
3286 spin_lock_irq(&dev->event_lock);
3287 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3288 spin_unlock_irq(&dev->event_lock);
3289
3290 return pending;
3291}
3292
3293static void intel_update_pipe_size(struct intel_crtc *crtc)
3294{
3295 struct drm_device *dev = crtc->base.dev;
3296 struct drm_i915_private *dev_priv = dev->dev_private;
3297 const struct drm_display_mode *adjusted_mode;
3298
3299 if (!i915.fastboot)
3300 return;
3301
3302 /*
3303 * Update pipe size and adjust fitter if needed: the reason for this is
3304 * that in compute_mode_changes we check the native mode (not the pfit
3305 * mode) to see if we can flip rather than do a full mode set. In the
3306 * fastboot case, we'll flip, but if we don't update the pipesrc and
3307 * pfit state, we'll end up with a big fb scanned out into the wrong
3308 * sized surface.
3309 *
3310 * To fix this properly, we need to hoist the checks up into
3311 * compute_mode_changes (or above), check the actual pfit state and
3312 * whether the platform allows pfit disable with pipe active, and only
3313 * then update the pipesrc and pfit state, even on the flip path.
3314 */
3315
3316 adjusted_mode = &crtc->config->base.adjusted_mode;
3317
3318 I915_WRITE(PIPESRC(crtc->pipe),
3319 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3320 (adjusted_mode->crtc_vdisplay - 1));
3321 if (!crtc->config->pch_pfit.enabled &&
3322 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3323 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3324 I915_WRITE(PF_CTL(crtc->pipe), 0);
3325 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3326 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3327 }
3328 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3329 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3330}
3331
3332static void intel_fdi_normal_train(struct drm_crtc *crtc)
3333{
3334 struct drm_device *dev = crtc->dev;
3335 struct drm_i915_private *dev_priv = dev->dev_private;
3336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3337 int pipe = intel_crtc->pipe;
3338 u32 reg, temp;
3339
3340 /* enable normal train */
3341 reg = FDI_TX_CTL(pipe);
3342 temp = I915_READ(reg);
3343 if (IS_IVYBRIDGE(dev)) {
3344 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3345 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3346 } else {
3347 temp &= ~FDI_LINK_TRAIN_NONE;
3348 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3349 }
3350 I915_WRITE(reg, temp);
3351
3352 reg = FDI_RX_CTL(pipe);
3353 temp = I915_READ(reg);
3354 if (HAS_PCH_CPT(dev)) {
3355 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3356 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3357 } else {
3358 temp &= ~FDI_LINK_TRAIN_NONE;
3359 temp |= FDI_LINK_TRAIN_NONE;
3360 }
3361 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3362
3363 /* wait one idle pattern time */
3364 POSTING_READ(reg);
3365 udelay(1000);
3366
3367 /* IVB wants error correction enabled */
3368 if (IS_IVYBRIDGE(dev))
3369 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3370 FDI_FE_ERRC_ENABLE);
3371}
3372
3373/* The FDI link training functions for ILK/Ibexpeak. */
3374static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3375{
3376 struct drm_device *dev = crtc->dev;
3377 struct drm_i915_private *dev_priv = dev->dev_private;
3378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3379 int pipe = intel_crtc->pipe;
3380 u32 reg, temp, tries;
3381
3382 /* FDI needs bits from pipe first */
3383 assert_pipe_enabled(dev_priv, pipe);
3384
3385 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3386 for train result */
3387 reg = FDI_RX_IMR(pipe);
3388 temp = I915_READ(reg);
3389 temp &= ~FDI_RX_SYMBOL_LOCK;
3390 temp &= ~FDI_RX_BIT_LOCK;
3391 I915_WRITE(reg, temp);
3392 I915_READ(reg);
3393 udelay(150);
3394
3395 /* enable CPU FDI TX and PCH FDI RX */
3396 reg = FDI_TX_CTL(pipe);
3397 temp = I915_READ(reg);
3398 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3399 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3400 temp &= ~FDI_LINK_TRAIN_NONE;
3401 temp |= FDI_LINK_TRAIN_PATTERN_1;
3402 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3403
3404 reg = FDI_RX_CTL(pipe);
3405 temp = I915_READ(reg);
3406 temp &= ~FDI_LINK_TRAIN_NONE;
3407 temp |= FDI_LINK_TRAIN_PATTERN_1;
3408 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3409
3410 POSTING_READ(reg);
3411 udelay(150);
3412
3413 /* Ironlake workaround, enable clock pointer after FDI enable*/
3414 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3415 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3416 FDI_RX_PHASE_SYNC_POINTER_EN);
3417
3418 reg = FDI_RX_IIR(pipe);
3419 for (tries = 0; tries < 5; tries++) {
3420 temp = I915_READ(reg);
3421 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3422
3423 if ((temp & FDI_RX_BIT_LOCK)) {
3424 DRM_DEBUG_KMS("FDI train 1 done.\n");
3425 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3426 break;
3427 }
3428 }
3429 if (tries == 5)
3430 DRM_ERROR("FDI train 1 fail!\n");
3431
3432 /* Train 2 */
3433 reg = FDI_TX_CTL(pipe);
3434 temp = I915_READ(reg);
3435 temp &= ~FDI_LINK_TRAIN_NONE;
3436 temp |= FDI_LINK_TRAIN_PATTERN_2;
3437 I915_WRITE(reg, temp);
3438
3439 reg = FDI_RX_CTL(pipe);
3440 temp = I915_READ(reg);
3441 temp &= ~FDI_LINK_TRAIN_NONE;
3442 temp |= FDI_LINK_TRAIN_PATTERN_2;
3443 I915_WRITE(reg, temp);
3444
3445 POSTING_READ(reg);
3446 udelay(150);
3447
3448 reg = FDI_RX_IIR(pipe);
3449 for (tries = 0; tries < 5; tries++) {
3450 temp = I915_READ(reg);
3451 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3452
3453 if (temp & FDI_RX_SYMBOL_LOCK) {
3454 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3455 DRM_DEBUG_KMS("FDI train 2 done.\n");
3456 break;
3457 }
3458 }
3459 if (tries == 5)
3460 DRM_ERROR("FDI train 2 fail!\n");
3461
3462 DRM_DEBUG_KMS("FDI train done\n");
3463
3464}
3465
3466static const int snb_b_fdi_train_param[] = {
3467 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3468 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3469 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3470 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3471};
3472
3473/* The FDI link training functions for SNB/Cougarpoint. */
3474static void gen6_fdi_link_train(struct drm_crtc *crtc)
3475{
3476 struct drm_device *dev = crtc->dev;
3477 struct drm_i915_private *dev_priv = dev->dev_private;
3478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3479 int pipe = intel_crtc->pipe;
3480 u32 reg, temp, i, retry;
3481
3482 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3483 for train result */
3484 reg = FDI_RX_IMR(pipe);
3485 temp = I915_READ(reg);
3486 temp &= ~FDI_RX_SYMBOL_LOCK;
3487 temp &= ~FDI_RX_BIT_LOCK;
3488 I915_WRITE(reg, temp);
3489
3490 POSTING_READ(reg);
3491 udelay(150);
3492
3493 /* enable CPU FDI TX and PCH FDI RX */
3494 reg = FDI_TX_CTL(pipe);
3495 temp = I915_READ(reg);
3496 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3497 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3498 temp &= ~FDI_LINK_TRAIN_NONE;
3499 temp |= FDI_LINK_TRAIN_PATTERN_1;
3500 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3501 /* SNB-B */
3502 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3503 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3504
3505 I915_WRITE(FDI_RX_MISC(pipe),
3506 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3507
3508 reg = FDI_RX_CTL(pipe);
3509 temp = I915_READ(reg);
3510 if (HAS_PCH_CPT(dev)) {
3511 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3512 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3513 } else {
3514 temp &= ~FDI_LINK_TRAIN_NONE;
3515 temp |= FDI_LINK_TRAIN_PATTERN_1;
3516 }
3517 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3518
3519 POSTING_READ(reg);
3520 udelay(150);
3521
3522 for (i = 0; i < 4; i++) {
3523 reg = FDI_TX_CTL(pipe);
3524 temp = I915_READ(reg);
3525 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3526 temp |= snb_b_fdi_train_param[i];
3527 I915_WRITE(reg, temp);
3528
3529 POSTING_READ(reg);
3530 udelay(500);
3531
3532 for (retry = 0; retry < 5; retry++) {
3533 reg = FDI_RX_IIR(pipe);
3534 temp = I915_READ(reg);
3535 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3536 if (temp & FDI_RX_BIT_LOCK) {
3537 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3538 DRM_DEBUG_KMS("FDI train 1 done.\n");
3539 break;
3540 }
3541 udelay(50);
3542 }
3543 if (retry < 5)
3544 break;
3545 }
3546 if (i == 4)
3547 DRM_ERROR("FDI train 1 fail!\n");
3548
3549 /* Train 2 */
3550 reg = FDI_TX_CTL(pipe);
3551 temp = I915_READ(reg);
3552 temp &= ~FDI_LINK_TRAIN_NONE;
3553 temp |= FDI_LINK_TRAIN_PATTERN_2;
3554 if (IS_GEN6(dev)) {
3555 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3556 /* SNB-B */
3557 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3558 }
3559 I915_WRITE(reg, temp);
3560
3561 reg = FDI_RX_CTL(pipe);
3562 temp = I915_READ(reg);
3563 if (HAS_PCH_CPT(dev)) {
3564 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3565 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3566 } else {
3567 temp &= ~FDI_LINK_TRAIN_NONE;
3568 temp |= FDI_LINK_TRAIN_PATTERN_2;
3569 }
3570 I915_WRITE(reg, temp);
3571
3572 POSTING_READ(reg);
3573 udelay(150);
3574
3575 for (i = 0; i < 4; i++) {
3576 reg = FDI_TX_CTL(pipe);
3577 temp = I915_READ(reg);
3578 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3579 temp |= snb_b_fdi_train_param[i];
3580 I915_WRITE(reg, temp);
3581
3582 POSTING_READ(reg);
3583 udelay(500);
3584
3585 for (retry = 0; retry < 5; retry++) {
3586 reg = FDI_RX_IIR(pipe);
3587 temp = I915_READ(reg);
3588 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3589 if (temp & FDI_RX_SYMBOL_LOCK) {
3590 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3591 DRM_DEBUG_KMS("FDI train 2 done.\n");
3592 break;
3593 }
3594 udelay(50);
3595 }
3596 if (retry < 5)
3597 break;
3598 }
3599 if (i == 4)
3600 DRM_ERROR("FDI train 2 fail!\n");
3601
3602 DRM_DEBUG_KMS("FDI train done.\n");
3603}
3604
3605/* Manual link training for Ivy Bridge A0 parts */
3606static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3607{
3608 struct drm_device *dev = crtc->dev;
3609 struct drm_i915_private *dev_priv = dev->dev_private;
3610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3611 int pipe = intel_crtc->pipe;
3612 u32 reg, temp, i, j;
3613
3614 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3615 for train result */
3616 reg = FDI_RX_IMR(pipe);
3617 temp = I915_READ(reg);
3618 temp &= ~FDI_RX_SYMBOL_LOCK;
3619 temp &= ~FDI_RX_BIT_LOCK;
3620 I915_WRITE(reg, temp);
3621
3622 POSTING_READ(reg);
3623 udelay(150);
3624
3625 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3626 I915_READ(FDI_RX_IIR(pipe)));
3627
3628 /* Try each vswing and preemphasis setting twice before moving on */
3629 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3630 /* disable first in case we need to retry */
3631 reg = FDI_TX_CTL(pipe);
3632 temp = I915_READ(reg);
3633 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3634 temp &= ~FDI_TX_ENABLE;
3635 I915_WRITE(reg, temp);
3636
3637 reg = FDI_RX_CTL(pipe);
3638 temp = I915_READ(reg);
3639 temp &= ~FDI_LINK_TRAIN_AUTO;
3640 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3641 temp &= ~FDI_RX_ENABLE;
3642 I915_WRITE(reg, temp);
3643
3644 /* enable CPU FDI TX and PCH FDI RX */
3645 reg = FDI_TX_CTL(pipe);
3646 temp = I915_READ(reg);
3647 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3648 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3649 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3650 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3651 temp |= snb_b_fdi_train_param[j/2];
3652 temp |= FDI_COMPOSITE_SYNC;
3653 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3654
3655 I915_WRITE(FDI_RX_MISC(pipe),
3656 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3657
3658 reg = FDI_RX_CTL(pipe);
3659 temp = I915_READ(reg);
3660 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3661 temp |= FDI_COMPOSITE_SYNC;
3662 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3663
3664 POSTING_READ(reg);
3665 udelay(1); /* should be 0.5us */
3666
3667 for (i = 0; i < 4; i++) {
3668 reg = FDI_RX_IIR(pipe);
3669 temp = I915_READ(reg);
3670 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3671
3672 if (temp & FDI_RX_BIT_LOCK ||
3673 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3674 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3675 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3676 i);
3677 break;
3678 }
3679 udelay(1); /* should be 0.5us */
3680 }
3681 if (i == 4) {
3682 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3683 continue;
3684 }
3685
3686 /* Train 2 */
3687 reg = FDI_TX_CTL(pipe);
3688 temp = I915_READ(reg);
3689 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3690 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3691 I915_WRITE(reg, temp);
3692
3693 reg = FDI_RX_CTL(pipe);
3694 temp = I915_READ(reg);
3695 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3696 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3697 I915_WRITE(reg, temp);
3698
3699 POSTING_READ(reg);
3700 udelay(2); /* should be 1.5us */
3701
3702 for (i = 0; i < 4; i++) {
3703 reg = FDI_RX_IIR(pipe);
3704 temp = I915_READ(reg);
3705 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3706
3707 if (temp & FDI_RX_SYMBOL_LOCK ||
3708 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3709 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3710 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3711 i);
3712 goto train_done;
3713 }
3714 udelay(2); /* should be 1.5us */
3715 }
3716 if (i == 4)
3717 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3718 }
3719
3720train_done:
3721 DRM_DEBUG_KMS("FDI train done.\n");
3722}
3723
3724static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3725{
3726 struct drm_device *dev = intel_crtc->base.dev;
3727 struct drm_i915_private *dev_priv = dev->dev_private;
3728 int pipe = intel_crtc->pipe;
3729 u32 reg, temp;
3730
3731
3732 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3733 reg = FDI_RX_CTL(pipe);
3734 temp = I915_READ(reg);
3735 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3736 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3737 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3738 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3739
3740 POSTING_READ(reg);
3741 udelay(200);
3742
3743 /* Switch from Rawclk to PCDclk */
3744 temp = I915_READ(reg);
3745 I915_WRITE(reg, temp | FDI_PCDCLK);
3746
3747 POSTING_READ(reg);
3748 udelay(200);
3749
3750 /* Enable CPU FDI TX PLL, always on for Ironlake */
3751 reg = FDI_TX_CTL(pipe);
3752 temp = I915_READ(reg);
3753 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3754 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3755
3756 POSTING_READ(reg);
3757 udelay(100);
3758 }
3759}
3760
3761static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3762{
3763 struct drm_device *dev = intel_crtc->base.dev;
3764 struct drm_i915_private *dev_priv = dev->dev_private;
3765 int pipe = intel_crtc->pipe;
3766 u32 reg, temp;
3767
3768 /* Switch from PCDclk to Rawclk */
3769 reg = FDI_RX_CTL(pipe);
3770 temp = I915_READ(reg);
3771 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3772
3773 /* Disable CPU FDI TX PLL */
3774 reg = FDI_TX_CTL(pipe);
3775 temp = I915_READ(reg);
3776 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3777
3778 POSTING_READ(reg);
3779 udelay(100);
3780
3781 reg = FDI_RX_CTL(pipe);
3782 temp = I915_READ(reg);
3783 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3784
3785 /* Wait for the clocks to turn off. */
3786 POSTING_READ(reg);
3787 udelay(100);
3788}
3789
3790static void ironlake_fdi_disable(struct drm_crtc *crtc)
3791{
3792 struct drm_device *dev = crtc->dev;
3793 struct drm_i915_private *dev_priv = dev->dev_private;
3794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3795 int pipe = intel_crtc->pipe;
3796 u32 reg, temp;
3797
3798 /* disable CPU FDI tx and PCH FDI rx */
3799 reg = FDI_TX_CTL(pipe);
3800 temp = I915_READ(reg);
3801 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3802 POSTING_READ(reg);
3803
3804 reg = FDI_RX_CTL(pipe);
3805 temp = I915_READ(reg);
3806 temp &= ~(0x7 << 16);
3807 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3808 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3809
3810 POSTING_READ(reg);
3811 udelay(100);
3812
3813 /* Ironlake workaround, disable clock pointer after downing FDI */
3814 if (HAS_PCH_IBX(dev))
3815 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3816
3817 /* still set train pattern 1 */
3818 reg = FDI_TX_CTL(pipe);
3819 temp = I915_READ(reg);
3820 temp &= ~FDI_LINK_TRAIN_NONE;
3821 temp |= FDI_LINK_TRAIN_PATTERN_1;
3822 I915_WRITE(reg, temp);
3823
3824 reg = FDI_RX_CTL(pipe);
3825 temp = I915_READ(reg);
3826 if (HAS_PCH_CPT(dev)) {
3827 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3828 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3829 } else {
3830 temp &= ~FDI_LINK_TRAIN_NONE;
3831 temp |= FDI_LINK_TRAIN_PATTERN_1;
3832 }
3833 /* BPC in FDI rx is consistent with that in PIPECONF */
3834 temp &= ~(0x07 << 16);
3835 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3836 I915_WRITE(reg, temp);
3837
3838 POSTING_READ(reg);
3839 udelay(100);
3840}
3841
3842bool intel_has_pending_fb_unpin(struct drm_device *dev)
3843{
3844 struct intel_crtc *crtc;
3845
3846 /* Note that we don't need to be called with mode_config.lock here
3847 * as our list of CRTC objects is static for the lifetime of the
3848 * device and so cannot disappear as we iterate. Similarly, we can
3849 * happily treat the predicates as racy, atomic checks as userspace
3850 * cannot claim and pin a new fb without at least acquring the
3851 * struct_mutex and so serialising with us.
3852 */
3853 for_each_intel_crtc(dev, crtc) {
3854 if (atomic_read(&crtc->unpin_work_count) == 0)
3855 continue;
3856
3857 if (crtc->unpin_work)
3858 intel_wait_for_vblank(dev, crtc->pipe);
3859
3860 return true;
3861 }
3862
3863 return false;
3864}
3865
3866static void page_flip_completed(struct intel_crtc *intel_crtc)
3867{
3868 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3869 struct intel_unpin_work *work = intel_crtc->unpin_work;
3870
3871 /* ensure that the unpin work is consistent wrt ->pending. */
3872 smp_rmb();
3873 intel_crtc->unpin_work = NULL;
3874
3875 if (work->event)
3876 drm_send_vblank_event(intel_crtc->base.dev,
3877 intel_crtc->pipe,
3878 work->event);
3879
3880 drm_crtc_vblank_put(&intel_crtc->base);
3881
3882 wake_up_all(&dev_priv->pending_flip_queue);
3883 queue_work(dev_priv->wq, &work->work);
3884
3885 trace_i915_flip_complete(intel_crtc->plane,
3886 work->pending_flip_obj);
3887}
3888
3889void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3890{
3891 struct drm_device *dev = crtc->dev;
3892 struct drm_i915_private *dev_priv = dev->dev_private;
3893
3894 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3895 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3896 !intel_crtc_has_pending_flip(crtc),
3897 60*HZ) == 0)) {
3898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3899
3900 spin_lock_irq(&dev->event_lock);
3901 if (intel_crtc->unpin_work) {
3902 WARN_ONCE(1, "Removing stuck page flip\n");
3903 page_flip_completed(intel_crtc);
3904 }
3905 spin_unlock_irq(&dev->event_lock);
3906 }
3907
3908 if (crtc->primary->fb) {
3909 mutex_lock(&dev->struct_mutex);
3910 intel_finish_fb(crtc->primary->fb);
3911 mutex_unlock(&dev->struct_mutex);
3912 }
3913}
3914
3915/* Program iCLKIP clock to the desired frequency */
3916static void lpt_program_iclkip(struct drm_crtc *crtc)
3917{
3918 struct drm_device *dev = crtc->dev;
3919 struct drm_i915_private *dev_priv = dev->dev_private;
3920 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3921 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3922 u32 temp;
3923
3924 mutex_lock(&dev_priv->sb_lock);
3925
3926 /* It is necessary to ungate the pixclk gate prior to programming
3927 * the divisors, and gate it back when it is done.
3928 */
3929 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3930
3931 /* Disable SSCCTL */
3932 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3933 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3934 SBI_SSCCTL_DISABLE,
3935 SBI_ICLK);
3936
3937 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3938 if (clock == 20000) {
3939 auxdiv = 1;
3940 divsel = 0x41;
3941 phaseinc = 0x20;
3942 } else {
3943 /* The iCLK virtual clock root frequency is in MHz,
3944 * but the adjusted_mode->crtc_clock in in KHz. To get the
3945 * divisors, it is necessary to divide one by another, so we
3946 * convert the virtual clock precision to KHz here for higher
3947 * precision.
3948 */
3949 u32 iclk_virtual_root_freq = 172800 * 1000;
3950 u32 iclk_pi_range = 64;
3951 u32 desired_divisor, msb_divisor_value, pi_value;
3952
3953 desired_divisor = (iclk_virtual_root_freq / clock);
3954 msb_divisor_value = desired_divisor / iclk_pi_range;
3955 pi_value = desired_divisor % iclk_pi_range;
3956
3957 auxdiv = 0;
3958 divsel = msb_divisor_value - 2;
3959 phaseinc = pi_value;
3960 }
3961
3962 /* This should not happen with any sane values */
3963 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3964 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3965 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3966 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3967
3968 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3969 clock,
3970 auxdiv,
3971 divsel,
3972 phasedir,
3973 phaseinc);
3974
3975 /* Program SSCDIVINTPHASE6 */
3976 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3977 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3978 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3979 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3980 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3981 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3982 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3983 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3984
3985 /* Program SSCAUXDIV */
3986 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3987 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3988 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3989 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3990
3991 /* Enable modulator and associated divider */
3992 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3993 temp &= ~SBI_SSCCTL_DISABLE;
3994 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3995
3996 /* Wait for initialization time */
3997 udelay(24);
3998
3999 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4000
4001 mutex_unlock(&dev_priv->sb_lock);
4002}
4003
4004static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4005 enum pipe pch_transcoder)
4006{
4007 struct drm_device *dev = crtc->base.dev;
4008 struct drm_i915_private *dev_priv = dev->dev_private;
4009 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4010
4011 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4012 I915_READ(HTOTAL(cpu_transcoder)));
4013 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4014 I915_READ(HBLANK(cpu_transcoder)));
4015 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4016 I915_READ(HSYNC(cpu_transcoder)));
4017
4018 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4019 I915_READ(VTOTAL(cpu_transcoder)));
4020 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4021 I915_READ(VBLANK(cpu_transcoder)));
4022 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4023 I915_READ(VSYNC(cpu_transcoder)));
4024 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4025 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4026}
4027
4028static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4029{
4030 struct drm_i915_private *dev_priv = dev->dev_private;
4031 uint32_t temp;
4032
4033 temp = I915_READ(SOUTH_CHICKEN1);
4034 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4035 return;
4036
4037 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4038 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4039
4040 temp &= ~FDI_BC_BIFURCATION_SELECT;
4041 if (enable)
4042 temp |= FDI_BC_BIFURCATION_SELECT;
4043
4044 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4045 I915_WRITE(SOUTH_CHICKEN1, temp);
4046 POSTING_READ(SOUTH_CHICKEN1);
4047}
4048
4049static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4050{
4051 struct drm_device *dev = intel_crtc->base.dev;
4052
4053 switch (intel_crtc->pipe) {
4054 case PIPE_A:
4055 break;
4056 case PIPE_B:
4057 if (intel_crtc->config->fdi_lanes > 2)
4058 cpt_set_fdi_bc_bifurcation(dev, false);
4059 else
4060 cpt_set_fdi_bc_bifurcation(dev, true);
4061
4062 break;
4063 case PIPE_C:
4064 cpt_set_fdi_bc_bifurcation(dev, true);
4065
4066 break;
4067 default:
4068 BUG();
4069 }
4070}
4071
4072/*
4073 * Enable PCH resources required for PCH ports:
4074 * - PCH PLLs
4075 * - FDI training & RX/TX
4076 * - update transcoder timings
4077 * - DP transcoding bits
4078 * - transcoder
4079 */
4080static void ironlake_pch_enable(struct drm_crtc *crtc)
4081{
4082 struct drm_device *dev = crtc->dev;
4083 struct drm_i915_private *dev_priv = dev->dev_private;
4084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4085 int pipe = intel_crtc->pipe;
4086 u32 reg, temp;
4087
4088 assert_pch_transcoder_disabled(dev_priv, pipe);
4089
4090 if (IS_IVYBRIDGE(dev))
4091 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4092
4093 /* Write the TU size bits before fdi link training, so that error
4094 * detection works. */
4095 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4096 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4097
4098 /* For PCH output, training FDI link */
4099 dev_priv->display.fdi_link_train(crtc);
4100
4101 /* We need to program the right clock selection before writing the pixel
4102 * mutliplier into the DPLL. */
4103 if (HAS_PCH_CPT(dev)) {
4104 u32 sel;
4105
4106 temp = I915_READ(PCH_DPLL_SEL);
4107 temp |= TRANS_DPLL_ENABLE(pipe);
4108 sel = TRANS_DPLLB_SEL(pipe);
4109 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4110 temp |= sel;
4111 else
4112 temp &= ~sel;
4113 I915_WRITE(PCH_DPLL_SEL, temp);
4114 }
4115
4116 /* XXX: pch pll's can be enabled any time before we enable the PCH
4117 * transcoder, and we actually should do this to not upset any PCH
4118 * transcoder that already use the clock when we share it.
4119 *
4120 * Note that enable_shared_dpll tries to do the right thing, but
4121 * get_shared_dpll unconditionally resets the pll - we need that to have
4122 * the right LVDS enable sequence. */
4123 intel_enable_shared_dpll(intel_crtc);
4124
4125 /* set transcoder timing, panel must allow it */
4126 assert_panel_unlocked(dev_priv, pipe);
4127 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4128
4129 intel_fdi_normal_train(crtc);
4130
4131 /* For PCH DP, enable TRANS_DP_CTL */
4132 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4133 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4134 reg = TRANS_DP_CTL(pipe);
4135 temp = I915_READ(reg);
4136 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4137 TRANS_DP_SYNC_MASK |
4138 TRANS_DP_BPC_MASK);
4139 temp |= TRANS_DP_OUTPUT_ENABLE;
4140 temp |= bpc << 9; /* same format but at 11:9 */
4141
4142 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4143 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4144 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4145 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4146
4147 switch (intel_trans_dp_port_sel(crtc)) {
4148 case PCH_DP_B:
4149 temp |= TRANS_DP_PORT_SEL_B;
4150 break;
4151 case PCH_DP_C:
4152 temp |= TRANS_DP_PORT_SEL_C;
4153 break;
4154 case PCH_DP_D:
4155 temp |= TRANS_DP_PORT_SEL_D;
4156 break;
4157 default:
4158 BUG();
4159 }
4160
4161 I915_WRITE(reg, temp);
4162 }
4163
4164 ironlake_enable_pch_transcoder(dev_priv, pipe);
4165}
4166
4167static void lpt_pch_enable(struct drm_crtc *crtc)
4168{
4169 struct drm_device *dev = crtc->dev;
4170 struct drm_i915_private *dev_priv = dev->dev_private;
4171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4172 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4173
4174 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4175
4176 lpt_program_iclkip(crtc);
4177
4178 /* Set transcoder timing. */
4179 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4180
4181 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4182}
4183
4184struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4185 struct intel_crtc_state *crtc_state)
4186{
4187 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4188 struct intel_shared_dpll *pll;
4189 enum intel_dpll_id i;
4190
4191 if (HAS_PCH_IBX(dev_priv->dev)) {
4192 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4193 i = (enum intel_dpll_id) crtc->pipe;
4194 pll = &dev_priv->shared_dplls[i];
4195
4196 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4197 crtc->base.base.id, pll->name);
4198
4199 WARN_ON(pll->new_config->crtc_mask);
4200
4201 goto found;
4202 }
4203
4204 if (IS_BROXTON(dev_priv->dev)) {
4205 /* PLL is attached to port in bxt */
4206 struct intel_encoder *encoder;
4207 struct intel_digital_port *intel_dig_port;
4208
4209 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4210 if (WARN_ON(!encoder))
4211 return NULL;
4212
4213 intel_dig_port = enc_to_dig_port(&encoder->base);
4214 /* 1:1 mapping between ports and PLLs */
4215 i = (enum intel_dpll_id)intel_dig_port->port;
4216 pll = &dev_priv->shared_dplls[i];
4217 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4218 crtc->base.base.id, pll->name);
4219 WARN_ON(pll->new_config->crtc_mask);
4220
4221 goto found;
4222 }
4223
4224 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4225 pll = &dev_priv->shared_dplls[i];
4226
4227 /* Only want to check enabled timings first */
4228 if (pll->new_config->crtc_mask == 0)
4229 continue;
4230
4231 if (memcmp(&crtc_state->dpll_hw_state,
4232 &pll->new_config->hw_state,
4233 sizeof(pll->new_config->hw_state)) == 0) {
4234 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4235 crtc->base.base.id, pll->name,
4236 pll->new_config->crtc_mask,
4237 pll->active);
4238 goto found;
4239 }
4240 }
4241
4242 /* Ok no matching timings, maybe there's a free one? */
4243 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4244 pll = &dev_priv->shared_dplls[i];
4245 if (pll->new_config->crtc_mask == 0) {
4246 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4247 crtc->base.base.id, pll->name);
4248 goto found;
4249 }
4250 }
4251
4252 return NULL;
4253
4254found:
4255 if (pll->new_config->crtc_mask == 0)
4256 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4257
4258 crtc_state->shared_dpll = i;
4259 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4260 pipe_name(crtc->pipe));
4261
4262 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4263
4264 return pll;
4265}
4266
4267/**
4268 * intel_shared_dpll_start_config - start a new PLL staged config
4269 * @dev_priv: DRM device
4270 * @clear_pipes: mask of pipes that will have their PLLs freed
4271 *
4272 * Starts a new PLL staged config, copying the current config but
4273 * releasing the references of pipes specified in clear_pipes.
4274 */
4275static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4276 unsigned clear_pipes)
4277{
4278 struct intel_shared_dpll *pll;
4279 enum intel_dpll_id i;
4280
4281 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4282 pll = &dev_priv->shared_dplls[i];
4283
4284 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4285 GFP_KERNEL);
4286 if (!pll->new_config)
4287 goto cleanup;
4288
4289 pll->new_config->crtc_mask &= ~clear_pipes;
4290 }
4291
4292 return 0;
4293
4294cleanup:
4295 while (--i >= 0) {
4296 pll = &dev_priv->shared_dplls[i];
4297 kfree(pll->new_config);
4298 pll->new_config = NULL;
4299 }
4300
4301 return -ENOMEM;
4302}
4303
4304static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4305{
4306 struct intel_shared_dpll *pll;
4307 enum intel_dpll_id i;
4308
4309 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4310 pll = &dev_priv->shared_dplls[i];
4311
4312 WARN_ON(pll->new_config == &pll->config);
4313
4314 pll->config = *pll->new_config;
4315 kfree(pll->new_config);
4316 pll->new_config = NULL;
4317 }
4318}
4319
4320static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4321{
4322 struct intel_shared_dpll *pll;
4323 enum intel_dpll_id i;
4324
4325 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4326 pll = &dev_priv->shared_dplls[i];
4327
4328 WARN_ON(pll->new_config == &pll->config);
4329
4330 kfree(pll->new_config);
4331 pll->new_config = NULL;
4332 }
4333}
4334
4335static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4336{
4337 struct drm_i915_private *dev_priv = dev->dev_private;
4338 int dslreg = PIPEDSL(pipe);
4339 u32 temp;
4340
4341 temp = I915_READ(dslreg);
4342 udelay(500);
4343 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4344 if (wait_for(I915_READ(dslreg) != temp, 5))
4345 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4346 }
4347}
4348
4349/**
4350 * skl_update_scaler_users - Stages update to crtc's scaler state
4351 * @intel_crtc: crtc
4352 * @crtc_state: crtc_state
4353 * @plane: plane (NULL indicates crtc is requesting update)
4354 * @plane_state: plane's state
4355 * @force_detach: request unconditional detachment of scaler
4356 *
4357 * This function updates scaler state for requested plane or crtc.
4358 * To request scaler usage update for a plane, caller shall pass plane pointer.
4359 * To request scaler usage update for crtc, caller shall pass plane pointer
4360 * as NULL.
4361 *
4362 * Return
4363 * 0 - scaler_usage updated successfully
4364 * error - requested scaling cannot be supported or other error condition
4365 */
4366int
4367skl_update_scaler_users(
4368 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4369 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4370 int force_detach)
4371{
4372 int need_scaling;
4373 int idx;
4374 int src_w, src_h, dst_w, dst_h;
4375 int *scaler_id;
4376 struct drm_framebuffer *fb;
4377 struct intel_crtc_scaler_state *scaler_state;
4378 unsigned int rotation;
4379
4380 if (!intel_crtc || !crtc_state)
4381 return 0;
4382
4383 scaler_state = &crtc_state->scaler_state;
4384
4385 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4386 fb = intel_plane ? plane_state->base.fb : NULL;
4387
4388 if (intel_plane) {
4389 src_w = drm_rect_width(&plane_state->src) >> 16;
4390 src_h = drm_rect_height(&plane_state->src) >> 16;
4391 dst_w = drm_rect_width(&plane_state->dst);
4392 dst_h = drm_rect_height(&plane_state->dst);
4393 scaler_id = &plane_state->scaler_id;
4394 rotation = plane_state->base.rotation;
4395 } else {
4396 struct drm_display_mode *adjusted_mode =
4397 &crtc_state->base.adjusted_mode;
4398 src_w = crtc_state->pipe_src_w;
4399 src_h = crtc_state->pipe_src_h;
4400 dst_w = adjusted_mode->hdisplay;
4401 dst_h = adjusted_mode->vdisplay;
4402 scaler_id = &scaler_state->scaler_id;
4403 rotation = DRM_ROTATE_0;
4404 }
4405
4406 need_scaling = intel_rotation_90_or_270(rotation) ?
4407 (src_h != dst_w || src_w != dst_h):
4408 (src_w != dst_w || src_h != dst_h);
4409
4410 /*
4411 * if plane is being disabled or scaler is no more required or force detach
4412 * - free scaler binded to this plane/crtc
4413 * - in order to do this, update crtc->scaler_usage
4414 *
4415 * Here scaler state in crtc_state is set free so that
4416 * scaler can be assigned to other user. Actual register
4417 * update to free the scaler is done in plane/panel-fit programming.
4418 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4419 */
4420 if (force_detach || !need_scaling || (intel_plane &&
4421 (!fb || !plane_state->visible))) {
4422 if (*scaler_id >= 0) {
4423 scaler_state->scaler_users &= ~(1 << idx);
4424 scaler_state->scalers[*scaler_id].in_use = 0;
4425
4426 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4427 "crtc_state = %p scaler_users = 0x%x\n",
4428 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4429 intel_plane ? intel_plane->base.base.id :
4430 intel_crtc->base.base.id, crtc_state,
4431 scaler_state->scaler_users);
4432 *scaler_id = -1;
4433 }
4434 return 0;
4435 }
4436
4437 /* range checks */
4438 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4439 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4440
4441 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4442 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4443 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4444 "size is out of scaler range\n",
4445 intel_plane ? "PLANE" : "CRTC",
4446 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4447 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4448 return -EINVAL;
4449 }
4450
4451 /* check colorkey */
4452 if (WARN_ON(intel_plane &&
4453 intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) {
4454 DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey",
4455 intel_plane->base.base.id, src_w, src_h, dst_w, dst_h);
4456 return -EINVAL;
4457 }
4458
4459 /* Check src format */
4460 if (intel_plane) {
4461 switch (fb->pixel_format) {
4462 case DRM_FORMAT_RGB565:
4463 case DRM_FORMAT_XBGR8888:
4464 case DRM_FORMAT_XRGB8888:
4465 case DRM_FORMAT_ABGR8888:
4466 case DRM_FORMAT_ARGB8888:
4467 case DRM_FORMAT_XRGB2101010:
4468 case DRM_FORMAT_XBGR2101010:
4469 case DRM_FORMAT_YUYV:
4470 case DRM_FORMAT_YVYU:
4471 case DRM_FORMAT_UYVY:
4472 case DRM_FORMAT_VYUY:
4473 break;
4474 default:
4475 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4476 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4477 return -EINVAL;
4478 }
4479 }
4480
4481 /* mark this plane as a scaler user in crtc_state */
4482 scaler_state->scaler_users |= (1 << idx);
4483 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4484 "crtc_state = %p scaler_users = 0x%x\n",
4485 intel_plane ? "PLANE" : "CRTC",
4486 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4487 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4488 return 0;
4489}
4490
4491static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4492{
4493 struct drm_device *dev = crtc->base.dev;
4494 struct drm_i915_private *dev_priv = dev->dev_private;
4495 int pipe = crtc->pipe;
4496 struct intel_crtc_scaler_state *scaler_state =
4497 &crtc->config->scaler_state;
4498
4499 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4500
4501 /* To update pfit, first update scaler state */
4502 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4503 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4504 skl_detach_scalers(crtc);
4505 if (!enable)
4506 return;
4507
4508 if (crtc->config->pch_pfit.enabled) {
4509 int id;
4510
4511 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4512 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4513 return;
4514 }
4515
4516 id = scaler_state->scaler_id;
4517 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4518 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4519 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4520 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4521
4522 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4523 }
4524}
4525
4526static void ironlake_pfit_enable(struct intel_crtc *crtc)
4527{
4528 struct drm_device *dev = crtc->base.dev;
4529 struct drm_i915_private *dev_priv = dev->dev_private;
4530 int pipe = crtc->pipe;
4531
4532 if (crtc->config->pch_pfit.enabled) {
4533 /* Force use of hard-coded filter coefficients
4534 * as some pre-programmed values are broken,
4535 * e.g. x201.
4536 */
4537 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4538 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4539 PF_PIPE_SEL_IVB(pipe));
4540 else
4541 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4542 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4543 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4544 }
4545}
4546
4547static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4548{
4549 struct drm_device *dev = crtc->dev;
4550 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4551 struct drm_plane *plane;
4552 struct intel_plane *intel_plane;
4553
4554 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4555 intel_plane = to_intel_plane(plane);
4556 if (intel_plane->pipe == pipe)
4557 intel_plane_restore(&intel_plane->base);
4558 }
4559}
4560
4561void hsw_enable_ips(struct intel_crtc *crtc)
4562{
4563 struct drm_device *dev = crtc->base.dev;
4564 struct drm_i915_private *dev_priv = dev->dev_private;
4565
4566 if (!crtc->config->ips_enabled)
4567 return;
4568
4569 /* We can only enable IPS after we enable a plane and wait for a vblank */
4570 intel_wait_for_vblank(dev, crtc->pipe);
4571
4572 assert_plane_enabled(dev_priv, crtc->plane);
4573 if (IS_BROADWELL(dev)) {
4574 mutex_lock(&dev_priv->rps.hw_lock);
4575 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4576 mutex_unlock(&dev_priv->rps.hw_lock);
4577 /* Quoting Art Runyan: "its not safe to expect any particular
4578 * value in IPS_CTL bit 31 after enabling IPS through the
4579 * mailbox." Moreover, the mailbox may return a bogus state,
4580 * so we need to just enable it and continue on.
4581 */
4582 } else {
4583 I915_WRITE(IPS_CTL, IPS_ENABLE);
4584 /* The bit only becomes 1 in the next vblank, so this wait here
4585 * is essentially intel_wait_for_vblank. If we don't have this
4586 * and don't wait for vblanks until the end of crtc_enable, then
4587 * the HW state readout code will complain that the expected
4588 * IPS_CTL value is not the one we read. */
4589 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4590 DRM_ERROR("Timed out waiting for IPS enable\n");
4591 }
4592}
4593
4594void hsw_disable_ips(struct intel_crtc *crtc)
4595{
4596 struct drm_device *dev = crtc->base.dev;
4597 struct drm_i915_private *dev_priv = dev->dev_private;
4598
4599 if (!crtc->config->ips_enabled)
4600 return;
4601
4602 assert_plane_enabled(dev_priv, crtc->plane);
4603 if (IS_BROADWELL(dev)) {
4604 mutex_lock(&dev_priv->rps.hw_lock);
4605 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4606 mutex_unlock(&dev_priv->rps.hw_lock);
4607 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4608 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4609 DRM_ERROR("Timed out waiting for IPS disable\n");
4610 } else {
4611 I915_WRITE(IPS_CTL, 0);
4612 POSTING_READ(IPS_CTL);
4613 }
4614
4615 /* We need to wait for a vblank before we can disable the plane. */
4616 intel_wait_for_vblank(dev, crtc->pipe);
4617}
4618
4619/** Loads the palette/gamma unit for the CRTC with the prepared values */
4620static void intel_crtc_load_lut(struct drm_crtc *crtc)
4621{
4622 struct drm_device *dev = crtc->dev;
4623 struct drm_i915_private *dev_priv = dev->dev_private;
4624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4625 enum pipe pipe = intel_crtc->pipe;
4626 int palreg = PALETTE(pipe);
4627 int i;
4628 bool reenable_ips = false;
4629
4630 /* The clocks have to be on to load the palette. */
4631 if (!crtc->state->active)
4632 return;
4633
4634 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4635 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4636 assert_dsi_pll_enabled(dev_priv);
4637 else
4638 assert_pll_enabled(dev_priv, pipe);
4639 }
4640
4641 /* use legacy palette for Ironlake */
4642 if (!HAS_GMCH_DISPLAY(dev))
4643 palreg = LGC_PALETTE(pipe);
4644
4645 /* Workaround : Do not read or write the pipe palette/gamma data while
4646 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4647 */
4648 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4649 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4650 GAMMA_MODE_MODE_SPLIT)) {
4651 hsw_disable_ips(intel_crtc);
4652 reenable_ips = true;
4653 }
4654
4655 for (i = 0; i < 256; i++) {
4656 I915_WRITE(palreg + 4 * i,
4657 (intel_crtc->lut_r[i] << 16) |
4658 (intel_crtc->lut_g[i] << 8) |
4659 intel_crtc->lut_b[i]);
4660 }
4661
4662 if (reenable_ips)
4663 hsw_enable_ips(intel_crtc);
4664}
4665
4666static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4667{
4668 if (intel_crtc->overlay) {
4669 struct drm_device *dev = intel_crtc->base.dev;
4670 struct drm_i915_private *dev_priv = dev->dev_private;
4671
4672 mutex_lock(&dev->struct_mutex);
4673 dev_priv->mm.interruptible = false;
4674 (void) intel_overlay_switch_off(intel_crtc->overlay);
4675 dev_priv->mm.interruptible = true;
4676 mutex_unlock(&dev->struct_mutex);
4677 }
4678
4679 /* Let userspace switch the overlay on again. In most cases userspace
4680 * has to recompute where to put it anyway.
4681 */
4682}
4683
4684/**
4685 * intel_post_enable_primary - Perform operations after enabling primary plane
4686 * @crtc: the CRTC whose primary plane was just enabled
4687 *
4688 * Performs potentially sleeping operations that must be done after the primary
4689 * plane is enabled, such as updating FBC and IPS. Note that this may be
4690 * called due to an explicit primary plane update, or due to an implicit
4691 * re-enable that is caused when a sprite plane is updated to no longer
4692 * completely hide the primary plane.
4693 */
4694static void
4695intel_post_enable_primary(struct drm_crtc *crtc)
4696{
4697 struct drm_device *dev = crtc->dev;
4698 struct drm_i915_private *dev_priv = dev->dev_private;
4699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4700 int pipe = intel_crtc->pipe;
4701
4702 /*
4703 * BDW signals flip done immediately if the plane
4704 * is disabled, even if the plane enable is already
4705 * armed to occur at the next vblank :(
4706 */
4707 if (IS_BROADWELL(dev))
4708 intel_wait_for_vblank(dev, pipe);
4709
4710 /*
4711 * FIXME IPS should be fine as long as one plane is
4712 * enabled, but in practice it seems to have problems
4713 * when going from primary only to sprite only and vice
4714 * versa.
4715 */
4716 hsw_enable_ips(intel_crtc);
4717
4718 mutex_lock(&dev->struct_mutex);
4719 intel_fbc_update(dev);
4720 mutex_unlock(&dev->struct_mutex);
4721
4722 /*
4723 * Gen2 reports pipe underruns whenever all planes are disabled.
4724 * So don't enable underrun reporting before at least some planes
4725 * are enabled.
4726 * FIXME: Need to fix the logic to work when we turn off all planes
4727 * but leave the pipe running.
4728 */
4729 if (IS_GEN2(dev))
4730 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4731
4732 /* Underruns don't raise interrupts, so check manually. */
4733 if (HAS_GMCH_DISPLAY(dev))
4734 i9xx_check_fifo_underruns(dev_priv);
4735}
4736
4737/**
4738 * intel_pre_disable_primary - Perform operations before disabling primary plane
4739 * @crtc: the CRTC whose primary plane is to be disabled
4740 *
4741 * Performs potentially sleeping operations that must be done before the
4742 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4743 * be called due to an explicit primary plane update, or due to an implicit
4744 * disable that is caused when a sprite plane completely hides the primary
4745 * plane.
4746 */
4747static void
4748intel_pre_disable_primary(struct drm_crtc *crtc)
4749{
4750 struct drm_device *dev = crtc->dev;
4751 struct drm_i915_private *dev_priv = dev->dev_private;
4752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4753 int pipe = intel_crtc->pipe;
4754
4755 /*
4756 * Gen2 reports pipe underruns whenever all planes are disabled.
4757 * So diasble underrun reporting before all the planes get disabled.
4758 * FIXME: Need to fix the logic to work when we turn off all planes
4759 * but leave the pipe running.
4760 */
4761 if (IS_GEN2(dev))
4762 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4763
4764 /*
4765 * Vblank time updates from the shadow to live plane control register
4766 * are blocked if the memory self-refresh mode is active at that
4767 * moment. So to make sure the plane gets truly disabled, disable
4768 * first the self-refresh mode. The self-refresh enable bit in turn
4769 * will be checked/applied by the HW only at the next frame start
4770 * event which is after the vblank start event, so we need to have a
4771 * wait-for-vblank between disabling the plane and the pipe.
4772 */
4773 if (HAS_GMCH_DISPLAY(dev))
4774 intel_set_memory_cxsr(dev_priv, false);
4775
4776 mutex_lock(&dev->struct_mutex);
4777 if (dev_priv->fbc.crtc == intel_crtc)
4778 intel_fbc_disable(dev);
4779 mutex_unlock(&dev->struct_mutex);
4780
4781 /*
4782 * FIXME IPS should be fine as long as one plane is
4783 * enabled, but in practice it seems to have problems
4784 * when going from primary only to sprite only and vice
4785 * versa.
4786 */
4787 hsw_disable_ips(intel_crtc);
4788}
4789
4790static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4791{
4792 struct drm_device *dev = crtc->dev;
4793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4794 int pipe = intel_crtc->pipe;
4795
4796 intel_enable_primary_hw_plane(crtc->primary, crtc);
4797 intel_enable_sprite_planes(crtc);
4798 intel_crtc_update_cursor(crtc, true);
4799
4800 intel_post_enable_primary(crtc);
4801
4802 /*
4803 * FIXME: Once we grow proper nuclear flip support out of this we need
4804 * to compute the mask of flip planes precisely. For the time being
4805 * consider this a flip to a NULL plane.
4806 */
4807 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4808}
4809
4810static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4811{
4812 struct drm_device *dev = crtc->dev;
4813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4814 struct intel_plane *intel_plane;
4815 int pipe = intel_crtc->pipe;
4816
4817 intel_crtc_wait_for_pending_flips(crtc);
4818
4819 intel_pre_disable_primary(crtc);
4820
4821 intel_crtc_dpms_overlay_disable(intel_crtc);
4822 for_each_intel_plane(dev, intel_plane) {
4823 if (intel_plane->pipe == pipe) {
4824 struct drm_crtc *from = intel_plane->base.crtc;
4825
4826 intel_plane->disable_plane(&intel_plane->base,
4827 from ?: crtc, true);
4828 }
4829 }
4830
4831 /*
4832 * FIXME: Once we grow proper nuclear flip support out of this we need
4833 * to compute the mask of flip planes precisely. For the time being
4834 * consider this a flip to a NULL plane.
4835 */
4836 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4837}
4838
4839static void ironlake_crtc_enable(struct drm_crtc *crtc)
4840{
4841 struct drm_device *dev = crtc->dev;
4842 struct drm_i915_private *dev_priv = dev->dev_private;
4843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4844 struct intel_encoder *encoder;
4845 int pipe = intel_crtc->pipe;
4846
4847 if (WARN_ON(intel_crtc->active))
4848 return;
4849
4850 if (intel_crtc->config->has_pch_encoder)
4851 intel_prepare_shared_dpll(intel_crtc);
4852
4853 if (intel_crtc->config->has_dp_encoder)
4854 intel_dp_set_m_n(intel_crtc, M1_N1);
4855
4856 intel_set_pipe_timings(intel_crtc);
4857
4858 if (intel_crtc->config->has_pch_encoder) {
4859 intel_cpu_transcoder_set_m_n(intel_crtc,
4860 &intel_crtc->config->fdi_m_n, NULL);
4861 }
4862
4863 ironlake_set_pipeconf(crtc);
4864
4865 intel_crtc->active = true;
4866
4867 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4868 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4869
4870 for_each_encoder_on_crtc(dev, crtc, encoder)
4871 if (encoder->pre_enable)
4872 encoder->pre_enable(encoder);
4873
4874 if (intel_crtc->config->has_pch_encoder) {
4875 /* Note: FDI PLL enabling _must_ be done before we enable the
4876 * cpu pipes, hence this is separate from all the other fdi/pch
4877 * enabling. */
4878 ironlake_fdi_pll_enable(intel_crtc);
4879 } else {
4880 assert_fdi_tx_disabled(dev_priv, pipe);
4881 assert_fdi_rx_disabled(dev_priv, pipe);
4882 }
4883
4884 ironlake_pfit_enable(intel_crtc);
4885
4886 /*
4887 * On ILK+ LUT must be loaded before the pipe is running but with
4888 * clocks enabled
4889 */
4890 intel_crtc_load_lut(crtc);
4891
4892 intel_update_watermarks(crtc);
4893 intel_enable_pipe(intel_crtc);
4894
4895 if (intel_crtc->config->has_pch_encoder)
4896 ironlake_pch_enable(crtc);
4897
4898 assert_vblank_disabled(crtc);
4899 drm_crtc_vblank_on(crtc);
4900
4901 for_each_encoder_on_crtc(dev, crtc, encoder)
4902 encoder->enable(encoder);
4903
4904 if (HAS_PCH_CPT(dev))
4905 cpt_verify_modeset(dev, intel_crtc->pipe);
4906}
4907
4908/* IPS only exists on ULT machines and is tied to pipe A. */
4909static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4910{
4911 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4912}
4913
4914/*
4915 * This implements the workaround described in the "notes" section of the mode
4916 * set sequence documentation. When going from no pipes or single pipe to
4917 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4918 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4919 */
4920static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4921{
4922 struct drm_device *dev = crtc->base.dev;
4923 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4924
4925 /* We want to get the other_active_crtc only if there's only 1 other
4926 * active crtc. */
4927 for_each_intel_crtc(dev, crtc_it) {
4928 if (!crtc_it->active || crtc_it == crtc)
4929 continue;
4930
4931 if (other_active_crtc)
4932 return;
4933
4934 other_active_crtc = crtc_it;
4935 }
4936 if (!other_active_crtc)
4937 return;
4938
4939 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4940 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4941}
4942
4943static void haswell_crtc_enable(struct drm_crtc *crtc)
4944{
4945 struct drm_device *dev = crtc->dev;
4946 struct drm_i915_private *dev_priv = dev->dev_private;
4947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4948 struct intel_encoder *encoder;
4949 int pipe = intel_crtc->pipe;
4950
4951 if (WARN_ON(intel_crtc->active))
4952 return;
4953
4954 if (intel_crtc_to_shared_dpll(intel_crtc))
4955 intel_enable_shared_dpll(intel_crtc);
4956
4957 if (intel_crtc->config->has_dp_encoder)
4958 intel_dp_set_m_n(intel_crtc, M1_N1);
4959
4960 intel_set_pipe_timings(intel_crtc);
4961
4962 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4963 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4964 intel_crtc->config->pixel_multiplier - 1);
4965 }
4966
4967 if (intel_crtc->config->has_pch_encoder) {
4968 intel_cpu_transcoder_set_m_n(intel_crtc,
4969 &intel_crtc->config->fdi_m_n, NULL);
4970 }
4971
4972 haswell_set_pipeconf(crtc);
4973
4974 intel_set_pipe_csc(crtc);
4975
4976 intel_crtc->active = true;
4977
4978 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4979 for_each_encoder_on_crtc(dev, crtc, encoder)
4980 if (encoder->pre_enable)
4981 encoder->pre_enable(encoder);
4982
4983 if (intel_crtc->config->has_pch_encoder) {
4984 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4985 true);
4986 dev_priv->display.fdi_link_train(crtc);
4987 }
4988
4989 intel_ddi_enable_pipe_clock(intel_crtc);
4990
4991 if (INTEL_INFO(dev)->gen == 9)
4992 skylake_pfit_update(intel_crtc, 1);
4993 else if (INTEL_INFO(dev)->gen < 9)
4994 ironlake_pfit_enable(intel_crtc);
4995 else
4996 MISSING_CASE(INTEL_INFO(dev)->gen);
4997
4998 /*
4999 * On ILK+ LUT must be loaded before the pipe is running but with
5000 * clocks enabled
5001 */
5002 intel_crtc_load_lut(crtc);
5003
5004 intel_ddi_set_pipe_settings(crtc);
5005 intel_ddi_enable_transcoder_func(crtc);
5006
5007 intel_update_watermarks(crtc);
5008 intel_enable_pipe(intel_crtc);
5009
5010 if (intel_crtc->config->has_pch_encoder)
5011 lpt_pch_enable(crtc);
5012
5013 if (intel_crtc->config->dp_encoder_is_mst)
5014 intel_ddi_set_vc_payload_alloc(crtc, true);
5015
5016 assert_vblank_disabled(crtc);
5017 drm_crtc_vblank_on(crtc);
5018
5019 for_each_encoder_on_crtc(dev, crtc, encoder) {
5020 encoder->enable(encoder);
5021 intel_opregion_notify_encoder(encoder, true);
5022 }
5023
5024 /* If we change the relative order between pipe/planes enabling, we need
5025 * to change the workaround. */
5026 haswell_mode_set_planes_workaround(intel_crtc);
5027}
5028
5029static void ironlake_pfit_disable(struct intel_crtc *crtc)
5030{
5031 struct drm_device *dev = crtc->base.dev;
5032 struct drm_i915_private *dev_priv = dev->dev_private;
5033 int pipe = crtc->pipe;
5034
5035 /* To avoid upsetting the power well on haswell only disable the pfit if
5036 * it's in use. The hw state code will make sure we get this right. */
5037 if (crtc->config->pch_pfit.enabled) {
5038 I915_WRITE(PF_CTL(pipe), 0);
5039 I915_WRITE(PF_WIN_POS(pipe), 0);
5040 I915_WRITE(PF_WIN_SZ(pipe), 0);
5041 }
5042}
5043
5044static void ironlake_crtc_disable(struct drm_crtc *crtc)
5045{
5046 struct drm_device *dev = crtc->dev;
5047 struct drm_i915_private *dev_priv = dev->dev_private;
5048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5049 struct intel_encoder *encoder;
5050 int pipe = intel_crtc->pipe;
5051 u32 reg, temp;
5052
5053 if (WARN_ON(!intel_crtc->active))
5054 return;
5055
5056 for_each_encoder_on_crtc(dev, crtc, encoder)
5057 encoder->disable(encoder);
5058
5059 drm_crtc_vblank_off(crtc);
5060 assert_vblank_disabled(crtc);
5061
5062 if (intel_crtc->config->has_pch_encoder)
5063 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5064
5065 intel_disable_pipe(intel_crtc);
5066
5067 ironlake_pfit_disable(intel_crtc);
5068
5069 if (intel_crtc->config->has_pch_encoder)
5070 ironlake_fdi_disable(crtc);
5071
5072 for_each_encoder_on_crtc(dev, crtc, encoder)
5073 if (encoder->post_disable)
5074 encoder->post_disable(encoder);
5075
5076 if (intel_crtc->config->has_pch_encoder) {
5077 ironlake_disable_pch_transcoder(dev_priv, pipe);
5078
5079 if (HAS_PCH_CPT(dev)) {
5080 /* disable TRANS_DP_CTL */
5081 reg = TRANS_DP_CTL(pipe);
5082 temp = I915_READ(reg);
5083 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5084 TRANS_DP_PORT_SEL_MASK);
5085 temp |= TRANS_DP_PORT_SEL_NONE;
5086 I915_WRITE(reg, temp);
5087
5088 /* disable DPLL_SEL */
5089 temp = I915_READ(PCH_DPLL_SEL);
5090 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5091 I915_WRITE(PCH_DPLL_SEL, temp);
5092 }
5093
5094 /* disable PCH DPLL */
5095 intel_disable_shared_dpll(intel_crtc);
5096
5097 ironlake_fdi_pll_disable(intel_crtc);
5098 }
5099
5100 intel_crtc->active = false;
5101 intel_update_watermarks(crtc);
5102
5103 mutex_lock(&dev->struct_mutex);
5104 intel_fbc_update(dev);
5105 mutex_unlock(&dev->struct_mutex);
5106}
5107
5108static void haswell_crtc_disable(struct drm_crtc *crtc)
5109{
5110 struct drm_device *dev = crtc->dev;
5111 struct drm_i915_private *dev_priv = dev->dev_private;
5112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5113 struct intel_encoder *encoder;
5114 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5115
5116 if (WARN_ON(!intel_crtc->active))
5117 return;
5118
5119 for_each_encoder_on_crtc(dev, crtc, encoder) {
5120 intel_opregion_notify_encoder(encoder, false);
5121 encoder->disable(encoder);
5122 }
5123
5124 drm_crtc_vblank_off(crtc);
5125 assert_vblank_disabled(crtc);
5126
5127 if (intel_crtc->config->has_pch_encoder)
5128 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5129 false);
5130 intel_disable_pipe(intel_crtc);
5131
5132 if (intel_crtc->config->dp_encoder_is_mst)
5133 intel_ddi_set_vc_payload_alloc(crtc, false);
5134
5135 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5136
5137 if (INTEL_INFO(dev)->gen == 9)
5138 skylake_pfit_update(intel_crtc, 0);
5139 else if (INTEL_INFO(dev)->gen < 9)
5140 ironlake_pfit_disable(intel_crtc);
5141 else
5142 MISSING_CASE(INTEL_INFO(dev)->gen);
5143
5144 intel_ddi_disable_pipe_clock(intel_crtc);
5145
5146 if (intel_crtc->config->has_pch_encoder) {
5147 lpt_disable_pch_transcoder(dev_priv);
5148 intel_ddi_fdi_disable(crtc);
5149 }
5150
5151 for_each_encoder_on_crtc(dev, crtc, encoder)
5152 if (encoder->post_disable)
5153 encoder->post_disable(encoder);
5154
5155 intel_crtc->active = false;
5156 intel_update_watermarks(crtc);
5157
5158 mutex_lock(&dev->struct_mutex);
5159 intel_fbc_update(dev);
5160 mutex_unlock(&dev->struct_mutex);
5161
5162 if (intel_crtc_to_shared_dpll(intel_crtc))
5163 intel_disable_shared_dpll(intel_crtc);
5164}
5165
5166static void i9xx_pfit_enable(struct intel_crtc *crtc)
5167{
5168 struct drm_device *dev = crtc->base.dev;
5169 struct drm_i915_private *dev_priv = dev->dev_private;
5170 struct intel_crtc_state *pipe_config = crtc->config;
5171
5172 if (!pipe_config->gmch_pfit.control)
5173 return;
5174
5175 /*
5176 * The panel fitter should only be adjusted whilst the pipe is disabled,
5177 * according to register description and PRM.
5178 */
5179 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5180 assert_pipe_disabled(dev_priv, crtc->pipe);
5181
5182 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5183 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5184
5185 /* Border color in case we don't scale up to the full screen. Black by
5186 * default, change to something else for debugging. */
5187 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5188}
5189
5190static enum intel_display_power_domain port_to_power_domain(enum port port)
5191{
5192 switch (port) {
5193 case PORT_A:
5194 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5195 case PORT_B:
5196 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5197 case PORT_C:
5198 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5199 case PORT_D:
5200 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5201 default:
5202 WARN_ON_ONCE(1);
5203 return POWER_DOMAIN_PORT_OTHER;
5204 }
5205}
5206
5207#define for_each_power_domain(domain, mask) \
5208 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5209 if ((1 << (domain)) & (mask))
5210
5211enum intel_display_power_domain
5212intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5213{
5214 struct drm_device *dev = intel_encoder->base.dev;
5215 struct intel_digital_port *intel_dig_port;
5216
5217 switch (intel_encoder->type) {
5218 case INTEL_OUTPUT_UNKNOWN:
5219 /* Only DDI platforms should ever use this output type */
5220 WARN_ON_ONCE(!HAS_DDI(dev));
5221 case INTEL_OUTPUT_DISPLAYPORT:
5222 case INTEL_OUTPUT_HDMI:
5223 case INTEL_OUTPUT_EDP:
5224 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5225 return port_to_power_domain(intel_dig_port->port);
5226 case INTEL_OUTPUT_DP_MST:
5227 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5228 return port_to_power_domain(intel_dig_port->port);
5229 case INTEL_OUTPUT_ANALOG:
5230 return POWER_DOMAIN_PORT_CRT;
5231 case INTEL_OUTPUT_DSI:
5232 return POWER_DOMAIN_PORT_DSI;
5233 default:
5234 return POWER_DOMAIN_PORT_OTHER;
5235 }
5236}
5237
5238static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5239{
5240 struct drm_device *dev = crtc->dev;
5241 struct intel_encoder *intel_encoder;
5242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5243 enum pipe pipe = intel_crtc->pipe;
5244 unsigned long mask;
5245 enum transcoder transcoder;
5246
5247 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5248
5249 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5250 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5251 if (intel_crtc->config->pch_pfit.enabled ||
5252 intel_crtc->config->pch_pfit.force_thru)
5253 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5254
5255 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5256 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5257
5258 return mask;
5259}
5260
5261static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5262{
5263 struct drm_device *dev = state->dev;
5264 struct drm_i915_private *dev_priv = dev->dev_private;
5265 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5266 struct intel_crtc *crtc;
5267
5268 /*
5269 * First get all needed power domains, then put all unneeded, to avoid
5270 * any unnecessary toggling of the power wells.
5271 */
5272 for_each_intel_crtc(dev, crtc) {
5273 enum intel_display_power_domain domain;
5274
5275 if (!crtc->base.state->enable)
5276 continue;
5277
5278 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5279
5280 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5281 intel_display_power_get(dev_priv, domain);
5282 }
5283
5284 if (dev_priv->display.modeset_global_resources)
5285 dev_priv->display.modeset_global_resources(state);
5286
5287 for_each_intel_crtc(dev, crtc) {
5288 enum intel_display_power_domain domain;
5289
5290 for_each_power_domain(domain, crtc->enabled_power_domains)
5291 intel_display_power_put(dev_priv, domain);
5292
5293 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5294 }
5295
5296 intel_display_set_init_power(dev_priv, false);
5297}
5298
5299static void intel_update_max_cdclk(struct drm_device *dev)
5300{
5301 struct drm_i915_private *dev_priv = dev->dev_private;
5302
5303 if (IS_SKYLAKE(dev)) {
5304 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5305
5306 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5307 dev_priv->max_cdclk_freq = 675000;
5308 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5309 dev_priv->max_cdclk_freq = 540000;
5310 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5311 dev_priv->max_cdclk_freq = 450000;
5312 else
5313 dev_priv->max_cdclk_freq = 337500;
5314 } else if (IS_BROADWELL(dev)) {
5315 /*
5316 * FIXME with extra cooling we can allow
5317 * 540 MHz for ULX and 675 Mhz for ULT.
5318 * How can we know if extra cooling is
5319 * available? PCI ID, VTB, something else?
5320 */
5321 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5322 dev_priv->max_cdclk_freq = 450000;
5323 else if (IS_BDW_ULX(dev))
5324 dev_priv->max_cdclk_freq = 450000;
5325 else if (IS_BDW_ULT(dev))
5326 dev_priv->max_cdclk_freq = 540000;
5327 else
5328 dev_priv->max_cdclk_freq = 675000;
5329 } else if (IS_VALLEYVIEW(dev)) {
5330 dev_priv->max_cdclk_freq = 400000;
5331 } else {
5332 /* otherwise assume cdclk is fixed */
5333 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5334 }
5335
5336 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5337 dev_priv->max_cdclk_freq);
5338}
5339
5340static void intel_update_cdclk(struct drm_device *dev)
5341{
5342 struct drm_i915_private *dev_priv = dev->dev_private;
5343
5344 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5345 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5346 dev_priv->cdclk_freq);
5347
5348 /*
5349 * Program the gmbus_freq based on the cdclk frequency.
5350 * BSpec erroneously claims we should aim for 4MHz, but
5351 * in fact 1MHz is the correct frequency.
5352 */
5353 if (IS_VALLEYVIEW(dev)) {
5354 /*
5355 * Program the gmbus_freq based on the cdclk frequency.
5356 * BSpec erroneously claims we should aim for 4MHz, but
5357 * in fact 1MHz is the correct frequency.
5358 */
5359 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5360 }
5361
5362 if (dev_priv->max_cdclk_freq == 0)
5363 intel_update_max_cdclk(dev);
5364}
5365
5366static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5367{
5368 struct drm_i915_private *dev_priv = dev->dev_private;
5369 uint32_t divider;
5370 uint32_t ratio;
5371 uint32_t current_freq;
5372 int ret;
5373
5374 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5375 switch (frequency) {
5376 case 144000:
5377 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5378 ratio = BXT_DE_PLL_RATIO(60);
5379 break;
5380 case 288000:
5381 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5382 ratio = BXT_DE_PLL_RATIO(60);
5383 break;
5384 case 384000:
5385 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5386 ratio = BXT_DE_PLL_RATIO(60);
5387 break;
5388 case 576000:
5389 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5390 ratio = BXT_DE_PLL_RATIO(60);
5391 break;
5392 case 624000:
5393 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5394 ratio = BXT_DE_PLL_RATIO(65);
5395 break;
5396 case 19200:
5397 /*
5398 * Bypass frequency with DE PLL disabled. Init ratio, divider
5399 * to suppress GCC warning.
5400 */
5401 ratio = 0;
5402 divider = 0;
5403 break;
5404 default:
5405 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5406
5407 return;
5408 }
5409
5410 mutex_lock(&dev_priv->rps.hw_lock);
5411 /* Inform power controller of upcoming frequency change */
5412 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5413 0x80000000);
5414 mutex_unlock(&dev_priv->rps.hw_lock);
5415
5416 if (ret) {
5417 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5418 ret, frequency);
5419 return;
5420 }
5421
5422 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5423 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5424 current_freq = current_freq * 500 + 1000;
5425
5426 /*
5427 * DE PLL has to be disabled when
5428 * - setting to 19.2MHz (bypass, PLL isn't used)
5429 * - before setting to 624MHz (PLL needs toggling)
5430 * - before setting to any frequency from 624MHz (PLL needs toggling)
5431 */
5432 if (frequency == 19200 || frequency == 624000 ||
5433 current_freq == 624000) {
5434 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5435 /* Timeout 200us */
5436 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5437 1))
5438 DRM_ERROR("timout waiting for DE PLL unlock\n");
5439 }
5440
5441 if (frequency != 19200) {
5442 uint32_t val;
5443
5444 val = I915_READ(BXT_DE_PLL_CTL);
5445 val &= ~BXT_DE_PLL_RATIO_MASK;
5446 val |= ratio;
5447 I915_WRITE(BXT_DE_PLL_CTL, val);
5448
5449 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5450 /* Timeout 200us */
5451 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5452 DRM_ERROR("timeout waiting for DE PLL lock\n");
5453
5454 val = I915_READ(CDCLK_CTL);
5455 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5456 val |= divider;
5457 /*
5458 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5459 * enable otherwise.
5460 */
5461 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5462 if (frequency >= 500000)
5463 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5464
5465 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5466 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5467 val |= (frequency - 1000) / 500;
5468 I915_WRITE(CDCLK_CTL, val);
5469 }
5470
5471 mutex_lock(&dev_priv->rps.hw_lock);
5472 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5473 DIV_ROUND_UP(frequency, 25000));
5474 mutex_unlock(&dev_priv->rps.hw_lock);
5475
5476 if (ret) {
5477 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5478 ret, frequency);
5479 return;
5480 }
5481
5482 intel_update_cdclk(dev);
5483}
5484
5485void broxton_init_cdclk(struct drm_device *dev)
5486{
5487 struct drm_i915_private *dev_priv = dev->dev_private;
5488 uint32_t val;
5489
5490 /*
5491 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5492 * or else the reset will hang because there is no PCH to respond.
5493 * Move the handshake programming to initialization sequence.
5494 * Previously was left up to BIOS.
5495 */
5496 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5497 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5498 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5499
5500 /* Enable PG1 for cdclk */
5501 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5502
5503 /* check if cd clock is enabled */
5504 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5505 DRM_DEBUG_KMS("Display already initialized\n");
5506 return;
5507 }
5508
5509 /*
5510 * FIXME:
5511 * - The initial CDCLK needs to be read from VBT.
5512 * Need to make this change after VBT has changes for BXT.
5513 * - check if setting the max (or any) cdclk freq is really necessary
5514 * here, it belongs to modeset time
5515 */
5516 broxton_set_cdclk(dev, 624000);
5517
5518 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5519 POSTING_READ(DBUF_CTL);
5520
5521 udelay(10);
5522
5523 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5524 DRM_ERROR("DBuf power enable timeout!\n");
5525}
5526
5527void broxton_uninit_cdclk(struct drm_device *dev)
5528{
5529 struct drm_i915_private *dev_priv = dev->dev_private;
5530
5531 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5532 POSTING_READ(DBUF_CTL);
5533
5534 udelay(10);
5535
5536 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5537 DRM_ERROR("DBuf power disable timeout!\n");
5538
5539 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5540 broxton_set_cdclk(dev, 19200);
5541
5542 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5543}
5544
5545static const struct skl_cdclk_entry {
5546 unsigned int freq;
5547 unsigned int vco;
5548} skl_cdclk_frequencies[] = {
5549 { .freq = 308570, .vco = 8640 },
5550 { .freq = 337500, .vco = 8100 },
5551 { .freq = 432000, .vco = 8640 },
5552 { .freq = 450000, .vco = 8100 },
5553 { .freq = 540000, .vco = 8100 },
5554 { .freq = 617140, .vco = 8640 },
5555 { .freq = 675000, .vco = 8100 },
5556};
5557
5558static unsigned int skl_cdclk_decimal(unsigned int freq)
5559{
5560 return (freq - 1000) / 500;
5561}
5562
5563static unsigned int skl_cdclk_get_vco(unsigned int freq)
5564{
5565 unsigned int i;
5566
5567 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5568 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5569
5570 if (e->freq == freq)
5571 return e->vco;
5572 }
5573
5574 return 8100;
5575}
5576
5577static void
5578skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5579{
5580 unsigned int min_freq;
5581 u32 val;
5582
5583 /* select the minimum CDCLK before enabling DPLL 0 */
5584 val = I915_READ(CDCLK_CTL);
5585 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5586 val |= CDCLK_FREQ_337_308;
5587
5588 if (required_vco == 8640)
5589 min_freq = 308570;
5590 else
5591 min_freq = 337500;
5592
5593 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5594
5595 I915_WRITE(CDCLK_CTL, val);
5596 POSTING_READ(CDCLK_CTL);
5597
5598 /*
5599 * We always enable DPLL0 with the lowest link rate possible, but still
5600 * taking into account the VCO required to operate the eDP panel at the
5601 * desired frequency. The usual DP link rates operate with a VCO of
5602 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5603 * The modeset code is responsible for the selection of the exact link
5604 * rate later on, with the constraint of choosing a frequency that
5605 * works with required_vco.
5606 */
5607 val = I915_READ(DPLL_CTRL1);
5608
5609 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5610 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5611 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5612 if (required_vco == 8640)
5613 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5614 SKL_DPLL0);
5615 else
5616 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5617 SKL_DPLL0);
5618
5619 I915_WRITE(DPLL_CTRL1, val);
5620 POSTING_READ(DPLL_CTRL1);
5621
5622 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5623
5624 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5625 DRM_ERROR("DPLL0 not locked\n");
5626}
5627
5628static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5629{
5630 int ret;
5631 u32 val;
5632
5633 /* inform PCU we want to change CDCLK */
5634 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5635 mutex_lock(&dev_priv->rps.hw_lock);
5636 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5637 mutex_unlock(&dev_priv->rps.hw_lock);
5638
5639 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5640}
5641
5642static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5643{
5644 unsigned int i;
5645
5646 for (i = 0; i < 15; i++) {
5647 if (skl_cdclk_pcu_ready(dev_priv))
5648 return true;
5649 udelay(10);
5650 }
5651
5652 return false;
5653}
5654
5655static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5656{
5657 struct drm_device *dev = dev_priv->dev;
5658 u32 freq_select, pcu_ack;
5659
5660 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5661
5662 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5663 DRM_ERROR("failed to inform PCU about cdclk change\n");
5664 return;
5665 }
5666
5667 /* set CDCLK_CTL */
5668 switch(freq) {
5669 case 450000:
5670 case 432000:
5671 freq_select = CDCLK_FREQ_450_432;
5672 pcu_ack = 1;
5673 break;
5674 case 540000:
5675 freq_select = CDCLK_FREQ_540;
5676 pcu_ack = 2;
5677 break;
5678 case 308570:
5679 case 337500:
5680 default:
5681 freq_select = CDCLK_FREQ_337_308;
5682 pcu_ack = 0;
5683 break;
5684 case 617140:
5685 case 675000:
5686 freq_select = CDCLK_FREQ_675_617;
5687 pcu_ack = 3;
5688 break;
5689 }
5690
5691 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5692 POSTING_READ(CDCLK_CTL);
5693
5694 /* inform PCU of the change */
5695 mutex_lock(&dev_priv->rps.hw_lock);
5696 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5697 mutex_unlock(&dev_priv->rps.hw_lock);
5698
5699 intel_update_cdclk(dev);
5700}
5701
5702void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5703{
5704 /* disable DBUF power */
5705 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5706 POSTING_READ(DBUF_CTL);
5707
5708 udelay(10);
5709
5710 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5711 DRM_ERROR("DBuf power disable timeout\n");
5712
5713 /* disable DPLL0 */
5714 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5715 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5716 DRM_ERROR("Couldn't disable DPLL0\n");
5717
5718 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5719}
5720
5721void skl_init_cdclk(struct drm_i915_private *dev_priv)
5722{
5723 u32 val;
5724 unsigned int required_vco;
5725
5726 /* enable PCH reset handshake */
5727 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5728 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5729
5730 /* enable PG1 and Misc I/O */
5731 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5732
5733 /* DPLL0 already enabed !? */
5734 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5735 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5736 return;
5737 }
5738
5739 /* enable DPLL0 */
5740 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5741 skl_dpll0_enable(dev_priv, required_vco);
5742
5743 /* set CDCLK to the frequency the BIOS chose */
5744 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5745
5746 /* enable DBUF power */
5747 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5748 POSTING_READ(DBUF_CTL);
5749
5750 udelay(10);
5751
5752 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5753 DRM_ERROR("DBuf power enable timeout\n");
5754}
5755
5756/* returns HPLL frequency in kHz */
5757static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5758{
5759 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5760
5761 /* Obtain SKU information */
5762 mutex_lock(&dev_priv->sb_lock);
5763 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5764 CCK_FUSE_HPLL_FREQ_MASK;
5765 mutex_unlock(&dev_priv->sb_lock);
5766
5767 return vco_freq[hpll_freq] * 1000;
5768}
5769
5770/* Adjust CDclk dividers to allow high res or save power if possible */
5771static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5772{
5773 struct drm_i915_private *dev_priv = dev->dev_private;
5774 u32 val, cmd;
5775
5776 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5777 != dev_priv->cdclk_freq);
5778
5779 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5780 cmd = 2;
5781 else if (cdclk == 266667)
5782 cmd = 1;
5783 else
5784 cmd = 0;
5785
5786 mutex_lock(&dev_priv->rps.hw_lock);
5787 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5788 val &= ~DSPFREQGUAR_MASK;
5789 val |= (cmd << DSPFREQGUAR_SHIFT);
5790 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5791 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5792 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5793 50)) {
5794 DRM_ERROR("timed out waiting for CDclk change\n");
5795 }
5796 mutex_unlock(&dev_priv->rps.hw_lock);
5797
5798 mutex_lock(&dev_priv->sb_lock);
5799
5800 if (cdclk == 400000) {
5801 u32 divider;
5802
5803 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5804
5805 /* adjust cdclk divider */
5806 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5807 val &= ~DISPLAY_FREQUENCY_VALUES;
5808 val |= divider;
5809 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5810
5811 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5812 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5813 50))
5814 DRM_ERROR("timed out waiting for CDclk change\n");
5815 }
5816
5817 /* adjust self-refresh exit latency value */
5818 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5819 val &= ~0x7f;
5820
5821 /*
5822 * For high bandwidth configs, we set a higher latency in the bunit
5823 * so that the core display fetch happens in time to avoid underruns.
5824 */
5825 if (cdclk == 400000)
5826 val |= 4500 / 250; /* 4.5 usec */
5827 else
5828 val |= 3000 / 250; /* 3.0 usec */
5829 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5830
5831 mutex_unlock(&dev_priv->sb_lock);
5832
5833 intel_update_cdclk(dev);
5834}
5835
5836static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5837{
5838 struct drm_i915_private *dev_priv = dev->dev_private;
5839 u32 val, cmd;
5840
5841 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5842 != dev_priv->cdclk_freq);
5843
5844 switch (cdclk) {
5845 case 333333:
5846 case 320000:
5847 case 266667:
5848 case 200000:
5849 break;
5850 default:
5851 MISSING_CASE(cdclk);
5852 return;
5853 }
5854
5855 /*
5856 * Specs are full of misinformation, but testing on actual
5857 * hardware has shown that we just need to write the desired
5858 * CCK divider into the Punit register.
5859 */
5860 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5861
5862 mutex_lock(&dev_priv->rps.hw_lock);
5863 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5864 val &= ~DSPFREQGUAR_MASK_CHV;
5865 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5866 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5867 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5868 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5869 50)) {
5870 DRM_ERROR("timed out waiting for CDclk change\n");
5871 }
5872 mutex_unlock(&dev_priv->rps.hw_lock);
5873
5874 intel_update_cdclk(dev);
5875}
5876
5877static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5878 int max_pixclk)
5879{
5880 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5881 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5882
5883 /*
5884 * Really only a few cases to deal with, as only 4 CDclks are supported:
5885 * 200MHz
5886 * 267MHz
5887 * 320/333MHz (depends on HPLL freq)
5888 * 400MHz (VLV only)
5889 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5890 * of the lower bin and adjust if needed.
5891 *
5892 * We seem to get an unstable or solid color picture at 200MHz.
5893 * Not sure what's wrong. For now use 200MHz only when all pipes
5894 * are off.
5895 */
5896 if (!IS_CHERRYVIEW(dev_priv) &&
5897 max_pixclk > freq_320*limit/100)
5898 return 400000;
5899 else if (max_pixclk > 266667*limit/100)
5900 return freq_320;
5901 else if (max_pixclk > 0)
5902 return 266667;
5903 else
5904 return 200000;
5905}
5906
5907static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5908 int max_pixclk)
5909{
5910 /*
5911 * FIXME:
5912 * - remove the guardband, it's not needed on BXT
5913 * - set 19.2MHz bypass frequency if there are no active pipes
5914 */
5915 if (max_pixclk > 576000*9/10)
5916 return 624000;
5917 else if (max_pixclk > 384000*9/10)
5918 return 576000;
5919 else if (max_pixclk > 288000*9/10)
5920 return 384000;
5921 else if (max_pixclk > 144000*9/10)
5922 return 288000;
5923 else
5924 return 144000;
5925}
5926
5927/* Compute the max pixel clock for new configuration. Uses atomic state if
5928 * that's non-NULL, look at current state otherwise. */
5929static int intel_mode_max_pixclk(struct drm_device *dev,
5930 struct drm_atomic_state *state)
5931{
5932 struct intel_crtc *intel_crtc;
5933 struct intel_crtc_state *crtc_state;
5934 int max_pixclk = 0;
5935
5936 for_each_intel_crtc(dev, intel_crtc) {
5937 if (state)
5938 crtc_state =
5939 intel_atomic_get_crtc_state(state, intel_crtc);
5940 else
5941 crtc_state = intel_crtc->config;
5942 if (IS_ERR(crtc_state))
5943 return PTR_ERR(crtc_state);
5944
5945 if (!crtc_state->base.enable)
5946 continue;
5947
5948 max_pixclk = max(max_pixclk,
5949 crtc_state->base.adjusted_mode.crtc_clock);
5950 }
5951
5952 return max_pixclk;
5953}
5954
5955static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
5956{
5957 struct drm_i915_private *dev_priv = to_i915(state->dev);
5958 struct drm_crtc *crtc;
5959 struct drm_crtc_state *crtc_state;
5960 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
5961 int cdclk, ret = 0;
5962
5963 if (max_pixclk < 0)
5964 return max_pixclk;
5965
5966 if (IS_VALLEYVIEW(dev_priv))
5967 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5968 else
5969 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5970
5971 if (cdclk == dev_priv->cdclk_freq)
5972 return 0;
5973
5974 /* add all active pipes to the state */
5975 for_each_crtc(state->dev, crtc) {
5976 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5977 if (IS_ERR(crtc_state))
5978 return PTR_ERR(crtc_state);
5979
5980 if (!crtc_state->active || needs_modeset(crtc_state))
5981 continue;
5982
5983 crtc_state->mode_changed = true;
5984
5985 ret = drm_atomic_add_affected_connectors(state, crtc);
5986 if (ret)
5987 break;
5988
5989 ret = drm_atomic_add_affected_planes(state, crtc);
5990 if (ret)
5991 break;
5992 }
5993
5994 return ret;
5995}
5996
5997static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5998{
5999 unsigned int credits, default_credits;
6000
6001 if (IS_CHERRYVIEW(dev_priv))
6002 default_credits = PFI_CREDIT(12);
6003 else
6004 default_credits = PFI_CREDIT(8);
6005
6006 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
6007 /* CHV suggested value is 31 or 63 */
6008 if (IS_CHERRYVIEW(dev_priv))
6009 credits = PFI_CREDIT_31;
6010 else
6011 credits = PFI_CREDIT(15);
6012 } else {
6013 credits = default_credits;
6014 }
6015
6016 /*
6017 * WA - write default credits before re-programming
6018 * FIXME: should we also set the resend bit here?
6019 */
6020 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6021 default_credits);
6022
6023 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6024 credits | PFI_CREDIT_RESEND);
6025
6026 /*
6027 * FIXME is this guaranteed to clear
6028 * immediately or should we poll for it?
6029 */
6030 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6031}
6032
6033static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
6034{
6035 struct drm_device *dev = old_state->dev;
6036 struct drm_i915_private *dev_priv = dev->dev_private;
6037 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
6038 int req_cdclk;
6039
6040 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
6041 * never fail. */
6042 if (WARN_ON(max_pixclk < 0))
6043 return;
6044
6045 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
6046
6047 if (req_cdclk != dev_priv->cdclk_freq) {
6048 /*
6049 * FIXME: We can end up here with all power domains off, yet
6050 * with a CDCLK frequency other than the minimum. To account
6051 * for this take the PIPE-A power domain, which covers the HW
6052 * blocks needed for the following programming. This can be
6053 * removed once it's guaranteed that we get here either with
6054 * the minimum CDCLK set, or the required power domains
6055 * enabled.
6056 */
6057 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6058
6059 if (IS_CHERRYVIEW(dev))
6060 cherryview_set_cdclk(dev, req_cdclk);
6061 else
6062 valleyview_set_cdclk(dev, req_cdclk);
6063
6064 vlv_program_pfi_credits(dev_priv);
6065
6066 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6067 }
6068}
6069
6070static void valleyview_crtc_enable(struct drm_crtc *crtc)
6071{
6072 struct drm_device *dev = crtc->dev;
6073 struct drm_i915_private *dev_priv = to_i915(dev);
6074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6075 struct intel_encoder *encoder;
6076 int pipe = intel_crtc->pipe;
6077 bool is_dsi;
6078
6079 if (WARN_ON(intel_crtc->active))
6080 return;
6081
6082 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6083
6084 if (!is_dsi) {
6085 if (IS_CHERRYVIEW(dev))
6086 chv_prepare_pll(intel_crtc, intel_crtc->config);
6087 else
6088 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6089 }
6090
6091 if (intel_crtc->config->has_dp_encoder)
6092 intel_dp_set_m_n(intel_crtc, M1_N1);
6093
6094 intel_set_pipe_timings(intel_crtc);
6095
6096 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6097 struct drm_i915_private *dev_priv = dev->dev_private;
6098
6099 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6100 I915_WRITE(CHV_CANVAS(pipe), 0);
6101 }
6102
6103 i9xx_set_pipeconf(intel_crtc);
6104
6105 intel_crtc->active = true;
6106
6107 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6108
6109 for_each_encoder_on_crtc(dev, crtc, encoder)
6110 if (encoder->pre_pll_enable)
6111 encoder->pre_pll_enable(encoder);
6112
6113 if (!is_dsi) {
6114 if (IS_CHERRYVIEW(dev))
6115 chv_enable_pll(intel_crtc, intel_crtc->config);
6116 else
6117 vlv_enable_pll(intel_crtc, intel_crtc->config);
6118 }
6119
6120 for_each_encoder_on_crtc(dev, crtc, encoder)
6121 if (encoder->pre_enable)
6122 encoder->pre_enable(encoder);
6123
6124 i9xx_pfit_enable(intel_crtc);
6125
6126 intel_crtc_load_lut(crtc);
6127
6128 intel_update_watermarks(crtc);
6129 intel_enable_pipe(intel_crtc);
6130
6131 assert_vblank_disabled(crtc);
6132 drm_crtc_vblank_on(crtc);
6133
6134 for_each_encoder_on_crtc(dev, crtc, encoder)
6135 encoder->enable(encoder);
6136}
6137
6138static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6139{
6140 struct drm_device *dev = crtc->base.dev;
6141 struct drm_i915_private *dev_priv = dev->dev_private;
6142
6143 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6144 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6145}
6146
6147static void i9xx_crtc_enable(struct drm_crtc *crtc)
6148{
6149 struct drm_device *dev = crtc->dev;
6150 struct drm_i915_private *dev_priv = to_i915(dev);
6151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6152 struct intel_encoder *encoder;
6153 int pipe = intel_crtc->pipe;
6154
6155 if (WARN_ON(intel_crtc->active))
6156 return;
6157
6158 i9xx_set_pll_dividers(intel_crtc);
6159
6160 if (intel_crtc->config->has_dp_encoder)
6161 intel_dp_set_m_n(intel_crtc, M1_N1);
6162
6163 intel_set_pipe_timings(intel_crtc);
6164
6165 i9xx_set_pipeconf(intel_crtc);
6166
6167 intel_crtc->active = true;
6168
6169 if (!IS_GEN2(dev))
6170 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6171
6172 for_each_encoder_on_crtc(dev, crtc, encoder)
6173 if (encoder->pre_enable)
6174 encoder->pre_enable(encoder);
6175
6176 i9xx_enable_pll(intel_crtc);
6177
6178 i9xx_pfit_enable(intel_crtc);
6179
6180 intel_crtc_load_lut(crtc);
6181
6182 intel_update_watermarks(crtc);
6183 intel_enable_pipe(intel_crtc);
6184
6185 assert_vblank_disabled(crtc);
6186 drm_crtc_vblank_on(crtc);
6187
6188 for_each_encoder_on_crtc(dev, crtc, encoder)
6189 encoder->enable(encoder);
6190}
6191
6192static void i9xx_pfit_disable(struct intel_crtc *crtc)
6193{
6194 struct drm_device *dev = crtc->base.dev;
6195 struct drm_i915_private *dev_priv = dev->dev_private;
6196
6197 if (!crtc->config->gmch_pfit.control)
6198 return;
6199
6200 assert_pipe_disabled(dev_priv, crtc->pipe);
6201
6202 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6203 I915_READ(PFIT_CONTROL));
6204 I915_WRITE(PFIT_CONTROL, 0);
6205}
6206
6207static void i9xx_crtc_disable(struct drm_crtc *crtc)
6208{
6209 struct drm_device *dev = crtc->dev;
6210 struct drm_i915_private *dev_priv = dev->dev_private;
6211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6212 struct intel_encoder *encoder;
6213 int pipe = intel_crtc->pipe;
6214
6215 if (WARN_ON(!intel_crtc->active))
6216 return;
6217
6218 /*
6219 * On gen2 planes are double buffered but the pipe isn't, so we must
6220 * wait for planes to fully turn off before disabling the pipe.
6221 * We also need to wait on all gmch platforms because of the
6222 * self-refresh mode constraint explained above.
6223 */
6224 intel_wait_for_vblank(dev, pipe);
6225
6226 for_each_encoder_on_crtc(dev, crtc, encoder)
6227 encoder->disable(encoder);
6228
6229 drm_crtc_vblank_off(crtc);
6230 assert_vblank_disabled(crtc);
6231
6232 intel_disable_pipe(intel_crtc);
6233
6234 i9xx_pfit_disable(intel_crtc);
6235
6236 for_each_encoder_on_crtc(dev, crtc, encoder)
6237 if (encoder->post_disable)
6238 encoder->post_disable(encoder);
6239
6240 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6241 if (IS_CHERRYVIEW(dev))
6242 chv_disable_pll(dev_priv, pipe);
6243 else if (IS_VALLEYVIEW(dev))
6244 vlv_disable_pll(dev_priv, pipe);
6245 else
6246 i9xx_disable_pll(intel_crtc);
6247 }
6248
6249 if (!IS_GEN2(dev))
6250 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6251
6252 intel_crtc->active = false;
6253 intel_update_watermarks(crtc);
6254
6255 mutex_lock(&dev->struct_mutex);
6256 intel_fbc_update(dev);
6257 mutex_unlock(&dev->struct_mutex);
6258}
6259
6260/*
6261 * turn all crtc's off, but do not adjust state
6262 * This has to be paired with a call to intel_modeset_setup_hw_state.
6263 */
6264void intel_display_suspend(struct drm_device *dev)
6265{
6266 struct drm_i915_private *dev_priv = to_i915(dev);
6267 struct drm_crtc *crtc;
6268
6269 for_each_crtc(dev, crtc) {
6270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6271 enum intel_display_power_domain domain;
6272 unsigned long domains;
6273
6274 if (!intel_crtc->active)
6275 continue;
6276
6277 intel_crtc_disable_planes(crtc);
6278 dev_priv->display.crtc_disable(crtc);
6279
6280 domains = intel_crtc->enabled_power_domains;
6281 for_each_power_domain(domain, domains)
6282 intel_display_power_put(dev_priv, domain);
6283 intel_crtc->enabled_power_domains = 0;
6284 }
6285}
6286
6287/* Master function to enable/disable CRTC and corresponding power wells */
6288void intel_crtc_control(struct drm_crtc *crtc, bool enable)
6289{
6290 struct drm_device *dev = crtc->dev;
6291 struct drm_i915_private *dev_priv = dev->dev_private;
6292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6293 enum intel_display_power_domain domain;
6294 unsigned long domains;
6295
6296 if (enable == intel_crtc->active)
6297 return;
6298
6299 if (enable && !crtc->state->enable)
6300 return;
6301
6302 crtc->state->active = enable;
6303 if (enable) {
6304 domains = get_crtc_power_domains(crtc);
6305 for_each_power_domain(domain, domains)
6306 intel_display_power_get(dev_priv, domain);
6307 intel_crtc->enabled_power_domains = domains;
6308
6309 dev_priv->display.crtc_enable(crtc);
6310 intel_crtc_enable_planes(crtc);
6311 } else {
6312 intel_crtc_disable_planes(crtc);
6313 dev_priv->display.crtc_disable(crtc);
6314
6315 domains = intel_crtc->enabled_power_domains;
6316 for_each_power_domain(domain, domains)
6317 intel_display_power_put(dev_priv, domain);
6318 intel_crtc->enabled_power_domains = 0;
6319 }
6320}
6321
6322/**
6323 * Sets the power management mode of the pipe and plane.
6324 */
6325void intel_crtc_update_dpms(struct drm_crtc *crtc)
6326{
6327 struct drm_device *dev = crtc->dev;
6328 struct intel_encoder *intel_encoder;
6329 bool enable = false;
6330
6331 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6332 enable |= intel_encoder->connectors_active;
6333
6334 intel_crtc_control(crtc, enable);
6335}
6336
6337void intel_encoder_destroy(struct drm_encoder *encoder)
6338{
6339 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6340
6341 drm_encoder_cleanup(encoder);
6342 kfree(intel_encoder);
6343}
6344
6345/* Simple dpms helper for encoders with just one connector, no cloning and only
6346 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6347 * state of the entire output pipe. */
6348static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6349{
6350 if (mode == DRM_MODE_DPMS_ON) {
6351 encoder->connectors_active = true;
6352
6353 intel_crtc_update_dpms(encoder->base.crtc);
6354 } else {
6355 encoder->connectors_active = false;
6356
6357 intel_crtc_update_dpms(encoder->base.crtc);
6358 }
6359}
6360
6361/* Cross check the actual hw state with our own modeset state tracking (and it's
6362 * internal consistency). */
6363static void intel_connector_check_state(struct intel_connector *connector)
6364{
6365 if (connector->get_hw_state(connector)) {
6366 struct intel_encoder *encoder = connector->encoder;
6367 struct drm_crtc *crtc;
6368 bool encoder_enabled;
6369 enum pipe pipe;
6370
6371 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6372 connector->base.base.id,
6373 connector->base.name);
6374
6375 /* there is no real hw state for MST connectors */
6376 if (connector->mst_port)
6377 return;
6378
6379 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6380 "wrong connector dpms state\n");
6381 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6382 "active connector not linked to encoder\n");
6383
6384 if (encoder) {
6385 I915_STATE_WARN(!encoder->connectors_active,
6386 "encoder->connectors_active not set\n");
6387
6388 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6389 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6390 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6391 return;
6392
6393 crtc = encoder->base.crtc;
6394
6395 I915_STATE_WARN(!crtc->state->enable,
6396 "crtc not enabled\n");
6397 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6398 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6399 "encoder active on the wrong pipe\n");
6400 }
6401 }
6402}
6403
6404int intel_connector_init(struct intel_connector *connector)
6405{
6406 struct drm_connector_state *connector_state;
6407
6408 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6409 if (!connector_state)
6410 return -ENOMEM;
6411
6412 connector->base.state = connector_state;
6413 return 0;
6414}
6415
6416struct intel_connector *intel_connector_alloc(void)
6417{
6418 struct intel_connector *connector;
6419
6420 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6421 if (!connector)
6422 return NULL;
6423
6424 if (intel_connector_init(connector) < 0) {
6425 kfree(connector);
6426 return NULL;
6427 }
6428
6429 return connector;
6430}
6431
6432/* Even simpler default implementation, if there's really no special case to
6433 * consider. */
6434void intel_connector_dpms(struct drm_connector *connector, int mode)
6435{
6436 /* All the simple cases only support two dpms states. */
6437 if (mode != DRM_MODE_DPMS_ON)
6438 mode = DRM_MODE_DPMS_OFF;
6439
6440 if (mode == connector->dpms)
6441 return;
6442
6443 connector->dpms = mode;
6444
6445 /* Only need to change hw state when actually enabled */
6446 if (connector->encoder)
6447 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6448
6449 intel_modeset_check_state(connector->dev);
6450}
6451
6452/* Simple connector->get_hw_state implementation for encoders that support only
6453 * one connector and no cloning and hence the encoder state determines the state
6454 * of the connector. */
6455bool intel_connector_get_hw_state(struct intel_connector *connector)
6456{
6457 enum pipe pipe = 0;
6458 struct intel_encoder *encoder = connector->encoder;
6459
6460 return encoder->get_hw_state(encoder, &pipe);
6461}
6462
6463static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6464{
6465 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6466 return crtc_state->fdi_lanes;
6467
6468 return 0;
6469}
6470
6471static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6472 struct intel_crtc_state *pipe_config)
6473{
6474 struct drm_atomic_state *state = pipe_config->base.state;
6475 struct intel_crtc *other_crtc;
6476 struct intel_crtc_state *other_crtc_state;
6477
6478 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6479 pipe_name(pipe), pipe_config->fdi_lanes);
6480 if (pipe_config->fdi_lanes > 4) {
6481 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6482 pipe_name(pipe), pipe_config->fdi_lanes);
6483 return -EINVAL;
6484 }
6485
6486 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6487 if (pipe_config->fdi_lanes > 2) {
6488 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6489 pipe_config->fdi_lanes);
6490 return -EINVAL;
6491 } else {
6492 return 0;
6493 }
6494 }
6495
6496 if (INTEL_INFO(dev)->num_pipes == 2)
6497 return 0;
6498
6499 /* Ivybridge 3 pipe is really complicated */
6500 switch (pipe) {
6501 case PIPE_A:
6502 return 0;
6503 case PIPE_B:
6504 if (pipe_config->fdi_lanes <= 2)
6505 return 0;
6506
6507 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6508 other_crtc_state =
6509 intel_atomic_get_crtc_state(state, other_crtc);
6510 if (IS_ERR(other_crtc_state))
6511 return PTR_ERR(other_crtc_state);
6512
6513 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6514 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6515 pipe_name(pipe), pipe_config->fdi_lanes);
6516 return -EINVAL;
6517 }
6518 return 0;
6519 case PIPE_C:
6520 if (pipe_config->fdi_lanes > 2) {
6521 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6522 pipe_name(pipe), pipe_config->fdi_lanes);
6523 return -EINVAL;
6524 }
6525
6526 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6527 other_crtc_state =
6528 intel_atomic_get_crtc_state(state, other_crtc);
6529 if (IS_ERR(other_crtc_state))
6530 return PTR_ERR(other_crtc_state);
6531
6532 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6533 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6534 return -EINVAL;
6535 }
6536 return 0;
6537 default:
6538 BUG();
6539 }
6540}
6541
6542#define RETRY 1
6543static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6544 struct intel_crtc_state *pipe_config)
6545{
6546 struct drm_device *dev = intel_crtc->base.dev;
6547 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6548 int lane, link_bw, fdi_dotclock, ret;
6549 bool needs_recompute = false;
6550
6551retry:
6552 /* FDI is a binary signal running at ~2.7GHz, encoding
6553 * each output octet as 10 bits. The actual frequency
6554 * is stored as a divider into a 100MHz clock, and the
6555 * mode pixel clock is stored in units of 1KHz.
6556 * Hence the bw of each lane in terms of the mode signal
6557 * is:
6558 */
6559 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6560
6561 fdi_dotclock = adjusted_mode->crtc_clock;
6562
6563 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6564 pipe_config->pipe_bpp);
6565
6566 pipe_config->fdi_lanes = lane;
6567
6568 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6569 link_bw, &pipe_config->fdi_m_n);
6570
6571 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6572 intel_crtc->pipe, pipe_config);
6573 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6574 pipe_config->pipe_bpp -= 2*3;
6575 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6576 pipe_config->pipe_bpp);
6577 needs_recompute = true;
6578 pipe_config->bw_constrained = true;
6579
6580 goto retry;
6581 }
6582
6583 if (needs_recompute)
6584 return RETRY;
6585
6586 return ret;
6587}
6588
6589static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6590 struct intel_crtc_state *pipe_config)
6591{
6592 if (pipe_config->pipe_bpp > 24)
6593 return false;
6594
6595 /* HSW can handle pixel rate up to cdclk? */
6596 if (IS_HASWELL(dev_priv->dev))
6597 return true;
6598
6599 /*
6600 * We compare against max which means we must take
6601 * the increased cdclk requirement into account when
6602 * calculating the new cdclk.
6603 *
6604 * Should measure whether using a lower cdclk w/o IPS
6605 */
6606 return ilk_pipe_pixel_rate(pipe_config) <=
6607 dev_priv->max_cdclk_freq * 95 / 100;
6608}
6609
6610static void hsw_compute_ips_config(struct intel_crtc *crtc,
6611 struct intel_crtc_state *pipe_config)
6612{
6613 struct drm_device *dev = crtc->base.dev;
6614 struct drm_i915_private *dev_priv = dev->dev_private;
6615
6616 pipe_config->ips_enabled = i915.enable_ips &&
6617 hsw_crtc_supports_ips(crtc) &&
6618 pipe_config_supports_ips(dev_priv, pipe_config);
6619}
6620
6621static int intel_crtc_compute_config(struct intel_crtc *crtc,
6622 struct intel_crtc_state *pipe_config)
6623{
6624 struct drm_device *dev = crtc->base.dev;
6625 struct drm_i915_private *dev_priv = dev->dev_private;
6626 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6627 int ret;
6628
6629 /* FIXME should check pixel clock limits on all platforms */
6630 if (INTEL_INFO(dev)->gen < 4) {
6631 int clock_limit = dev_priv->max_cdclk_freq;
6632
6633 /*
6634 * Enable pixel doubling when the dot clock
6635 * is > 90% of the (display) core speed.
6636 *
6637 * GDG double wide on either pipe,
6638 * otherwise pipe A only.
6639 */
6640 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6641 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6642 clock_limit *= 2;
6643 pipe_config->double_wide = true;
6644 }
6645
6646 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6647 return -EINVAL;
6648 }
6649
6650 /*
6651 * Pipe horizontal size must be even in:
6652 * - DVO ganged mode
6653 * - LVDS dual channel mode
6654 * - Double wide pipe
6655 */
6656 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6657 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6658 pipe_config->pipe_src_w &= ~1;
6659
6660 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6661 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6662 */
6663 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6664 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6665 return -EINVAL;
6666
6667 if (HAS_IPS(dev))
6668 hsw_compute_ips_config(crtc, pipe_config);
6669
6670 if (pipe_config->has_pch_encoder)
6671 return ironlake_fdi_compute_config(crtc, pipe_config);
6672
6673 /* FIXME: remove below call once atomic mode set is place and all crtc
6674 * related checks called from atomic_crtc_check function */
6675 ret = 0;
6676 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6677 crtc, pipe_config->base.state);
6678 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6679
6680 return ret;
6681}
6682
6683static int skylake_get_display_clock_speed(struct drm_device *dev)
6684{
6685 struct drm_i915_private *dev_priv = to_i915(dev);
6686 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6687 uint32_t cdctl = I915_READ(CDCLK_CTL);
6688 uint32_t linkrate;
6689
6690 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6691 return 24000; /* 24MHz is the cd freq with NSSC ref */
6692
6693 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6694 return 540000;
6695
6696 linkrate = (I915_READ(DPLL_CTRL1) &
6697 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6698
6699 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6700 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6701 /* vco 8640 */
6702 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6703 case CDCLK_FREQ_450_432:
6704 return 432000;
6705 case CDCLK_FREQ_337_308:
6706 return 308570;
6707 case CDCLK_FREQ_675_617:
6708 return 617140;
6709 default:
6710 WARN(1, "Unknown cd freq selection\n");
6711 }
6712 } else {
6713 /* vco 8100 */
6714 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6715 case CDCLK_FREQ_450_432:
6716 return 450000;
6717 case CDCLK_FREQ_337_308:
6718 return 337500;
6719 case CDCLK_FREQ_675_617:
6720 return 675000;
6721 default:
6722 WARN(1, "Unknown cd freq selection\n");
6723 }
6724 }
6725
6726 /* error case, do as if DPLL0 isn't enabled */
6727 return 24000;
6728}
6729
6730static int broadwell_get_display_clock_speed(struct drm_device *dev)
6731{
6732 struct drm_i915_private *dev_priv = dev->dev_private;
6733 uint32_t lcpll = I915_READ(LCPLL_CTL);
6734 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6735
6736 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6737 return 800000;
6738 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6739 return 450000;
6740 else if (freq == LCPLL_CLK_FREQ_450)
6741 return 450000;
6742 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6743 return 540000;
6744 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6745 return 337500;
6746 else
6747 return 675000;
6748}
6749
6750static int haswell_get_display_clock_speed(struct drm_device *dev)
6751{
6752 struct drm_i915_private *dev_priv = dev->dev_private;
6753 uint32_t lcpll = I915_READ(LCPLL_CTL);
6754 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6755
6756 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6757 return 800000;
6758 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6759 return 450000;
6760 else if (freq == LCPLL_CLK_FREQ_450)
6761 return 450000;
6762 else if (IS_HSW_ULT(dev))
6763 return 337500;
6764 else
6765 return 540000;
6766}
6767
6768static int valleyview_get_display_clock_speed(struct drm_device *dev)
6769{
6770 struct drm_i915_private *dev_priv = dev->dev_private;
6771 u32 val;
6772 int divider;
6773
6774 if (dev_priv->hpll_freq == 0)
6775 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6776
6777 mutex_lock(&dev_priv->sb_lock);
6778 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6779 mutex_unlock(&dev_priv->sb_lock);
6780
6781 divider = val & DISPLAY_FREQUENCY_VALUES;
6782
6783 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6784 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6785 "cdclk change in progress\n");
6786
6787 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6788}
6789
6790static int ilk_get_display_clock_speed(struct drm_device *dev)
6791{
6792 return 450000;
6793}
6794
6795static int i945_get_display_clock_speed(struct drm_device *dev)
6796{
6797 return 400000;
6798}
6799
6800static int i915_get_display_clock_speed(struct drm_device *dev)
6801{
6802 return 333333;
6803}
6804
6805static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6806{
6807 return 200000;
6808}
6809
6810static int pnv_get_display_clock_speed(struct drm_device *dev)
6811{
6812 u16 gcfgc = 0;
6813
6814 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6815
6816 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6817 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6818 return 266667;
6819 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6820 return 333333;
6821 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6822 return 444444;
6823 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6824 return 200000;
6825 default:
6826 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6827 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6828 return 133333;
6829 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6830 return 166667;
6831 }
6832}
6833
6834static int i915gm_get_display_clock_speed(struct drm_device *dev)
6835{
6836 u16 gcfgc = 0;
6837
6838 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6839
6840 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6841 return 133333;
6842 else {
6843 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6844 case GC_DISPLAY_CLOCK_333_MHZ:
6845 return 333333;
6846 default:
6847 case GC_DISPLAY_CLOCK_190_200_MHZ:
6848 return 190000;
6849 }
6850 }
6851}
6852
6853static int i865_get_display_clock_speed(struct drm_device *dev)
6854{
6855 return 266667;
6856}
6857
6858static int i85x_get_display_clock_speed(struct drm_device *dev)
6859{
6860 u16 hpllcc = 0;
6861
6862 /*
6863 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6864 * encoding is different :(
6865 * FIXME is this the right way to detect 852GM/852GMV?
6866 */
6867 if (dev->pdev->revision == 0x1)
6868 return 133333;
6869
6870 pci_bus_read_config_word(dev->pdev->bus,
6871 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6872
6873 /* Assume that the hardware is in the high speed state. This
6874 * should be the default.
6875 */
6876 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6877 case GC_CLOCK_133_200:
6878 case GC_CLOCK_133_200_2:
6879 case GC_CLOCK_100_200:
6880 return 200000;
6881 case GC_CLOCK_166_250:
6882 return 250000;
6883 case GC_CLOCK_100_133:
6884 return 133333;
6885 case GC_CLOCK_133_266:
6886 case GC_CLOCK_133_266_2:
6887 case GC_CLOCK_166_266:
6888 return 266667;
6889 }
6890
6891 /* Shouldn't happen */
6892 return 0;
6893}
6894
6895static int i830_get_display_clock_speed(struct drm_device *dev)
6896{
6897 return 133333;
6898}
6899
6900static unsigned int intel_hpll_vco(struct drm_device *dev)
6901{
6902 struct drm_i915_private *dev_priv = dev->dev_private;
6903 static const unsigned int blb_vco[8] = {
6904 [0] = 3200000,
6905 [1] = 4000000,
6906 [2] = 5333333,
6907 [3] = 4800000,
6908 [4] = 6400000,
6909 };
6910 static const unsigned int pnv_vco[8] = {
6911 [0] = 3200000,
6912 [1] = 4000000,
6913 [2] = 5333333,
6914 [3] = 4800000,
6915 [4] = 2666667,
6916 };
6917 static const unsigned int cl_vco[8] = {
6918 [0] = 3200000,
6919 [1] = 4000000,
6920 [2] = 5333333,
6921 [3] = 6400000,
6922 [4] = 3333333,
6923 [5] = 3566667,
6924 [6] = 4266667,
6925 };
6926 static const unsigned int elk_vco[8] = {
6927 [0] = 3200000,
6928 [1] = 4000000,
6929 [2] = 5333333,
6930 [3] = 4800000,
6931 };
6932 static const unsigned int ctg_vco[8] = {
6933 [0] = 3200000,
6934 [1] = 4000000,
6935 [2] = 5333333,
6936 [3] = 6400000,
6937 [4] = 2666667,
6938 [5] = 4266667,
6939 };
6940 const unsigned int *vco_table;
6941 unsigned int vco;
6942 uint8_t tmp = 0;
6943
6944 /* FIXME other chipsets? */
6945 if (IS_GM45(dev))
6946 vco_table = ctg_vco;
6947 else if (IS_G4X(dev))
6948 vco_table = elk_vco;
6949 else if (IS_CRESTLINE(dev))
6950 vco_table = cl_vco;
6951 else if (IS_PINEVIEW(dev))
6952 vco_table = pnv_vco;
6953 else if (IS_G33(dev))
6954 vco_table = blb_vco;
6955 else
6956 return 0;
6957
6958 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6959
6960 vco = vco_table[tmp & 0x7];
6961 if (vco == 0)
6962 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6963 else
6964 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6965
6966 return vco;
6967}
6968
6969static int gm45_get_display_clock_speed(struct drm_device *dev)
6970{
6971 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6972 uint16_t tmp = 0;
6973
6974 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6975
6976 cdclk_sel = (tmp >> 12) & 0x1;
6977
6978 switch (vco) {
6979 case 2666667:
6980 case 4000000:
6981 case 5333333:
6982 return cdclk_sel ? 333333 : 222222;
6983 case 3200000:
6984 return cdclk_sel ? 320000 : 228571;
6985 default:
6986 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6987 return 222222;
6988 }
6989}
6990
6991static int i965gm_get_display_clock_speed(struct drm_device *dev)
6992{
6993 static const uint8_t div_3200[] = { 16, 10, 8 };
6994 static const uint8_t div_4000[] = { 20, 12, 10 };
6995 static const uint8_t div_5333[] = { 24, 16, 14 };
6996 const uint8_t *div_table;
6997 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6998 uint16_t tmp = 0;
6999
7000 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7001
7002 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7003
7004 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7005 goto fail;
7006
7007 switch (vco) {
7008 case 3200000:
7009 div_table = div_3200;
7010 break;
7011 case 4000000:
7012 div_table = div_4000;
7013 break;
7014 case 5333333:
7015 div_table = div_5333;
7016 break;
7017 default:
7018 goto fail;
7019 }
7020
7021 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7022
7023 fail:
7024 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7025 return 200000;
7026}
7027
7028static int g33_get_display_clock_speed(struct drm_device *dev)
7029{
7030 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7031 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7032 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7033 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7034 const uint8_t *div_table;
7035 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7036 uint16_t tmp = 0;
7037
7038 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7039
7040 cdclk_sel = (tmp >> 4) & 0x7;
7041
7042 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7043 goto fail;
7044
7045 switch (vco) {
7046 case 3200000:
7047 div_table = div_3200;
7048 break;
7049 case 4000000:
7050 div_table = div_4000;
7051 break;
7052 case 4800000:
7053 div_table = div_4800;
7054 break;
7055 case 5333333:
7056 div_table = div_5333;
7057 break;
7058 default:
7059 goto fail;
7060 }
7061
7062 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7063
7064 fail:
7065 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7066 return 190476;
7067}
7068
7069static void
7070intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7071{
7072 while (*num > DATA_LINK_M_N_MASK ||
7073 *den > DATA_LINK_M_N_MASK) {
7074 *num >>= 1;
7075 *den >>= 1;
7076 }
7077}
7078
7079static void compute_m_n(unsigned int m, unsigned int n,
7080 uint32_t *ret_m, uint32_t *ret_n)
7081{
7082 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7083 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7084 intel_reduce_m_n_ratio(ret_m, ret_n);
7085}
7086
7087void
7088intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7089 int pixel_clock, int link_clock,
7090 struct intel_link_m_n *m_n)
7091{
7092 m_n->tu = 64;
7093
7094 compute_m_n(bits_per_pixel * pixel_clock,
7095 link_clock * nlanes * 8,
7096 &m_n->gmch_m, &m_n->gmch_n);
7097
7098 compute_m_n(pixel_clock, link_clock,
7099 &m_n->link_m, &m_n->link_n);
7100}
7101
7102static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7103{
7104 if (i915.panel_use_ssc >= 0)
7105 return i915.panel_use_ssc != 0;
7106 return dev_priv->vbt.lvds_use_ssc
7107 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7108}
7109
7110static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7111 int num_connectors)
7112{
7113 struct drm_device *dev = crtc_state->base.crtc->dev;
7114 struct drm_i915_private *dev_priv = dev->dev_private;
7115 int refclk;
7116
7117 WARN_ON(!crtc_state->base.state);
7118
7119 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7120 refclk = 100000;
7121 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7122 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7123 refclk = dev_priv->vbt.lvds_ssc_freq;
7124 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7125 } else if (!IS_GEN2(dev)) {
7126 refclk = 96000;
7127 } else {
7128 refclk = 48000;
7129 }
7130
7131 return refclk;
7132}
7133
7134static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7135{
7136 return (1 << dpll->n) << 16 | dpll->m2;
7137}
7138
7139static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7140{
7141 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7142}
7143
7144static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7145 struct intel_crtc_state *crtc_state,
7146 intel_clock_t *reduced_clock)
7147{
7148 struct drm_device *dev = crtc->base.dev;
7149 u32 fp, fp2 = 0;
7150
7151 if (IS_PINEVIEW(dev)) {
7152 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7153 if (reduced_clock)
7154 fp2 = pnv_dpll_compute_fp(reduced_clock);
7155 } else {
7156 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7157 if (reduced_clock)
7158 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7159 }
7160
7161 crtc_state->dpll_hw_state.fp0 = fp;
7162
7163 crtc->lowfreq_avail = false;
7164 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7165 reduced_clock) {
7166 crtc_state->dpll_hw_state.fp1 = fp2;
7167 crtc->lowfreq_avail = true;
7168 } else {
7169 crtc_state->dpll_hw_state.fp1 = fp;
7170 }
7171}
7172
7173static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7174 pipe)
7175{
7176 u32 reg_val;
7177
7178 /*
7179 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7180 * and set it to a reasonable value instead.
7181 */
7182 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7183 reg_val &= 0xffffff00;
7184 reg_val |= 0x00000030;
7185 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7186
7187 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7188 reg_val &= 0x8cffffff;
7189 reg_val = 0x8c000000;
7190 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7191
7192 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7193 reg_val &= 0xffffff00;
7194 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7195
7196 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7197 reg_val &= 0x00ffffff;
7198 reg_val |= 0xb0000000;
7199 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7200}
7201
7202static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7203 struct intel_link_m_n *m_n)
7204{
7205 struct drm_device *dev = crtc->base.dev;
7206 struct drm_i915_private *dev_priv = dev->dev_private;
7207 int pipe = crtc->pipe;
7208
7209 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7210 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7211 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7212 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7213}
7214
7215static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7216 struct intel_link_m_n *m_n,
7217 struct intel_link_m_n *m2_n2)
7218{
7219 struct drm_device *dev = crtc->base.dev;
7220 struct drm_i915_private *dev_priv = dev->dev_private;
7221 int pipe = crtc->pipe;
7222 enum transcoder transcoder = crtc->config->cpu_transcoder;
7223
7224 if (INTEL_INFO(dev)->gen >= 5) {
7225 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7226 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7227 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7228 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7229 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7230 * for gen < 8) and if DRRS is supported (to make sure the
7231 * registers are not unnecessarily accessed).
7232 */
7233 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7234 crtc->config->has_drrs) {
7235 I915_WRITE(PIPE_DATA_M2(transcoder),
7236 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7237 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7238 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7239 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7240 }
7241 } else {
7242 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7243 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7244 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7245 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7246 }
7247}
7248
7249void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7250{
7251 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7252
7253 if (m_n == M1_N1) {
7254 dp_m_n = &crtc->config->dp_m_n;
7255 dp_m2_n2 = &crtc->config->dp_m2_n2;
7256 } else if (m_n == M2_N2) {
7257
7258 /*
7259 * M2_N2 registers are not supported. Hence m2_n2 divider value
7260 * needs to be programmed into M1_N1.
7261 */
7262 dp_m_n = &crtc->config->dp_m2_n2;
7263 } else {
7264 DRM_ERROR("Unsupported divider value\n");
7265 return;
7266 }
7267
7268 if (crtc->config->has_pch_encoder)
7269 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7270 else
7271 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7272}
7273
7274static void vlv_update_pll(struct intel_crtc *crtc,
7275 struct intel_crtc_state *pipe_config)
7276{
7277 u32 dpll, dpll_md;
7278
7279 /*
7280 * Enable DPIO clock input. We should never disable the reference
7281 * clock for pipe B, since VGA hotplug / manual detection depends
7282 * on it.
7283 */
7284 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7285 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7286 /* We should never disable this, set it here for state tracking */
7287 if (crtc->pipe == PIPE_B)
7288 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7289 dpll |= DPLL_VCO_ENABLE;
7290 pipe_config->dpll_hw_state.dpll = dpll;
7291
7292 dpll_md = (pipe_config->pixel_multiplier - 1)
7293 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7294 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7295}
7296
7297static void vlv_prepare_pll(struct intel_crtc *crtc,
7298 const struct intel_crtc_state *pipe_config)
7299{
7300 struct drm_device *dev = crtc->base.dev;
7301 struct drm_i915_private *dev_priv = dev->dev_private;
7302 int pipe = crtc->pipe;
7303 u32 mdiv;
7304 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7305 u32 coreclk, reg_val;
7306
7307 mutex_lock(&dev_priv->sb_lock);
7308
7309 bestn = pipe_config->dpll.n;
7310 bestm1 = pipe_config->dpll.m1;
7311 bestm2 = pipe_config->dpll.m2;
7312 bestp1 = pipe_config->dpll.p1;
7313 bestp2 = pipe_config->dpll.p2;
7314
7315 /* See eDP HDMI DPIO driver vbios notes doc */
7316
7317 /* PLL B needs special handling */
7318 if (pipe == PIPE_B)
7319 vlv_pllb_recal_opamp(dev_priv, pipe);
7320
7321 /* Set up Tx target for periodic Rcomp update */
7322 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7323
7324 /* Disable target IRef on PLL */
7325 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7326 reg_val &= 0x00ffffff;
7327 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7328
7329 /* Disable fast lock */
7330 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7331
7332 /* Set idtafcrecal before PLL is enabled */
7333 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7334 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7335 mdiv |= ((bestn << DPIO_N_SHIFT));
7336 mdiv |= (1 << DPIO_K_SHIFT);
7337
7338 /*
7339 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7340 * but we don't support that).
7341 * Note: don't use the DAC post divider as it seems unstable.
7342 */
7343 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7344 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7345
7346 mdiv |= DPIO_ENABLE_CALIBRATION;
7347 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7348
7349 /* Set HBR and RBR LPF coefficients */
7350 if (pipe_config->port_clock == 162000 ||
7351 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7352 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7353 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7354 0x009f0003);
7355 else
7356 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7357 0x00d0000f);
7358
7359 if (pipe_config->has_dp_encoder) {
7360 /* Use SSC source */
7361 if (pipe == PIPE_A)
7362 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7363 0x0df40000);
7364 else
7365 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7366 0x0df70000);
7367 } else { /* HDMI or VGA */
7368 /* Use bend source */
7369 if (pipe == PIPE_A)
7370 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7371 0x0df70000);
7372 else
7373 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7374 0x0df40000);
7375 }
7376
7377 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7378 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7379 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7380 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7381 coreclk |= 0x01000000;
7382 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7383
7384 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7385 mutex_unlock(&dev_priv->sb_lock);
7386}
7387
7388static void chv_update_pll(struct intel_crtc *crtc,
7389 struct intel_crtc_state *pipe_config)
7390{
7391 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
7392 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7393 DPLL_VCO_ENABLE;
7394 if (crtc->pipe != PIPE_A)
7395 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7396
7397 pipe_config->dpll_hw_state.dpll_md =
7398 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7399}
7400
7401static void chv_prepare_pll(struct intel_crtc *crtc,
7402 const struct intel_crtc_state *pipe_config)
7403{
7404 struct drm_device *dev = crtc->base.dev;
7405 struct drm_i915_private *dev_priv = dev->dev_private;
7406 int pipe = crtc->pipe;
7407 int dpll_reg = DPLL(crtc->pipe);
7408 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7409 u32 loopfilter, tribuf_calcntr;
7410 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7411 u32 dpio_val;
7412 int vco;
7413
7414 bestn = pipe_config->dpll.n;
7415 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7416 bestm1 = pipe_config->dpll.m1;
7417 bestm2 = pipe_config->dpll.m2 >> 22;
7418 bestp1 = pipe_config->dpll.p1;
7419 bestp2 = pipe_config->dpll.p2;
7420 vco = pipe_config->dpll.vco;
7421 dpio_val = 0;
7422 loopfilter = 0;
7423
7424 /*
7425 * Enable Refclk and SSC
7426 */
7427 I915_WRITE(dpll_reg,
7428 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7429
7430 mutex_lock(&dev_priv->sb_lock);
7431
7432 /* p1 and p2 divider */
7433 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7434 5 << DPIO_CHV_S1_DIV_SHIFT |
7435 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7436 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7437 1 << DPIO_CHV_K_DIV_SHIFT);
7438
7439 /* Feedback post-divider - m2 */
7440 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7441
7442 /* Feedback refclk divider - n and m1 */
7443 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7444 DPIO_CHV_M1_DIV_BY_2 |
7445 1 << DPIO_CHV_N_DIV_SHIFT);
7446
7447 /* M2 fraction division */
7448 if (bestm2_frac)
7449 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7450
7451 /* M2 fraction division enable */
7452 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7453 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7454 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7455 if (bestm2_frac)
7456 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7457 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7458
7459 /* Program digital lock detect threshold */
7460 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7461 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7462 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7463 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7464 if (!bestm2_frac)
7465 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7466 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7467
7468 /* Loop filter */
7469 if (vco == 5400000) {
7470 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7471 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7472 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7473 tribuf_calcntr = 0x9;
7474 } else if (vco <= 6200000) {
7475 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7476 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7477 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7478 tribuf_calcntr = 0x9;
7479 } else if (vco <= 6480000) {
7480 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7481 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7482 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7483 tribuf_calcntr = 0x8;
7484 } else {
7485 /* Not supported. Apply the same limits as in the max case */
7486 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7487 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7488 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7489 tribuf_calcntr = 0;
7490 }
7491 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7492
7493 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7494 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7495 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7496 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7497
7498 /* AFC Recal */
7499 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7500 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7501 DPIO_AFC_RECAL);
7502
7503 mutex_unlock(&dev_priv->sb_lock);
7504}
7505
7506/**
7507 * vlv_force_pll_on - forcibly enable just the PLL
7508 * @dev_priv: i915 private structure
7509 * @pipe: pipe PLL to enable
7510 * @dpll: PLL configuration
7511 *
7512 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7513 * in cases where we need the PLL enabled even when @pipe is not going to
7514 * be enabled.
7515 */
7516void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7517 const struct dpll *dpll)
7518{
7519 struct intel_crtc *crtc =
7520 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7521 struct intel_crtc_state pipe_config = {
7522 .base.crtc = &crtc->base,
7523 .pixel_multiplier = 1,
7524 .dpll = *dpll,
7525 };
7526
7527 if (IS_CHERRYVIEW(dev)) {
7528 chv_update_pll(crtc, &pipe_config);
7529 chv_prepare_pll(crtc, &pipe_config);
7530 chv_enable_pll(crtc, &pipe_config);
7531 } else {
7532 vlv_update_pll(crtc, &pipe_config);
7533 vlv_prepare_pll(crtc, &pipe_config);
7534 vlv_enable_pll(crtc, &pipe_config);
7535 }
7536}
7537
7538/**
7539 * vlv_force_pll_off - forcibly disable just the PLL
7540 * @dev_priv: i915 private structure
7541 * @pipe: pipe PLL to disable
7542 *
7543 * Disable the PLL for @pipe. To be used in cases where we need
7544 * the PLL enabled even when @pipe is not going to be enabled.
7545 */
7546void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7547{
7548 if (IS_CHERRYVIEW(dev))
7549 chv_disable_pll(to_i915(dev), pipe);
7550 else
7551 vlv_disable_pll(to_i915(dev), pipe);
7552}
7553
7554static void i9xx_update_pll(struct intel_crtc *crtc,
7555 struct intel_crtc_state *crtc_state,
7556 intel_clock_t *reduced_clock,
7557 int num_connectors)
7558{
7559 struct drm_device *dev = crtc->base.dev;
7560 struct drm_i915_private *dev_priv = dev->dev_private;
7561 u32 dpll;
7562 bool is_sdvo;
7563 struct dpll *clock = &crtc_state->dpll;
7564
7565 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7566
7567 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7568 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7569
7570 dpll = DPLL_VGA_MODE_DIS;
7571
7572 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7573 dpll |= DPLLB_MODE_LVDS;
7574 else
7575 dpll |= DPLLB_MODE_DAC_SERIAL;
7576
7577 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7578 dpll |= (crtc_state->pixel_multiplier - 1)
7579 << SDVO_MULTIPLIER_SHIFT_HIRES;
7580 }
7581
7582 if (is_sdvo)
7583 dpll |= DPLL_SDVO_HIGH_SPEED;
7584
7585 if (crtc_state->has_dp_encoder)
7586 dpll |= DPLL_SDVO_HIGH_SPEED;
7587
7588 /* compute bitmask from p1 value */
7589 if (IS_PINEVIEW(dev))
7590 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7591 else {
7592 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7593 if (IS_G4X(dev) && reduced_clock)
7594 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7595 }
7596 switch (clock->p2) {
7597 case 5:
7598 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7599 break;
7600 case 7:
7601 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7602 break;
7603 case 10:
7604 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7605 break;
7606 case 14:
7607 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7608 break;
7609 }
7610 if (INTEL_INFO(dev)->gen >= 4)
7611 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7612
7613 if (crtc_state->sdvo_tv_clock)
7614 dpll |= PLL_REF_INPUT_TVCLKINBC;
7615 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7616 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7617 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7618 else
7619 dpll |= PLL_REF_INPUT_DREFCLK;
7620
7621 dpll |= DPLL_VCO_ENABLE;
7622 crtc_state->dpll_hw_state.dpll = dpll;
7623
7624 if (INTEL_INFO(dev)->gen >= 4) {
7625 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7626 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7627 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7628 }
7629}
7630
7631static void i8xx_update_pll(struct intel_crtc *crtc,
7632 struct intel_crtc_state *crtc_state,
7633 intel_clock_t *reduced_clock,
7634 int num_connectors)
7635{
7636 struct drm_device *dev = crtc->base.dev;
7637 struct drm_i915_private *dev_priv = dev->dev_private;
7638 u32 dpll;
7639 struct dpll *clock = &crtc_state->dpll;
7640
7641 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7642
7643 dpll = DPLL_VGA_MODE_DIS;
7644
7645 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7646 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7647 } else {
7648 if (clock->p1 == 2)
7649 dpll |= PLL_P1_DIVIDE_BY_TWO;
7650 else
7651 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7652 if (clock->p2 == 4)
7653 dpll |= PLL_P2_DIVIDE_BY_4;
7654 }
7655
7656 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7657 dpll |= DPLL_DVO_2X_MODE;
7658
7659 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7660 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7661 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7662 else
7663 dpll |= PLL_REF_INPUT_DREFCLK;
7664
7665 dpll |= DPLL_VCO_ENABLE;
7666 crtc_state->dpll_hw_state.dpll = dpll;
7667}
7668
7669static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7670{
7671 struct drm_device *dev = intel_crtc->base.dev;
7672 struct drm_i915_private *dev_priv = dev->dev_private;
7673 enum pipe pipe = intel_crtc->pipe;
7674 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7675 struct drm_display_mode *adjusted_mode =
7676 &intel_crtc->config->base.adjusted_mode;
7677 uint32_t crtc_vtotal, crtc_vblank_end;
7678 int vsyncshift = 0;
7679
7680 /* We need to be careful not to changed the adjusted mode, for otherwise
7681 * the hw state checker will get angry at the mismatch. */
7682 crtc_vtotal = adjusted_mode->crtc_vtotal;
7683 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7684
7685 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7686 /* the chip adds 2 halflines automatically */
7687 crtc_vtotal -= 1;
7688 crtc_vblank_end -= 1;
7689
7690 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7691 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7692 else
7693 vsyncshift = adjusted_mode->crtc_hsync_start -
7694 adjusted_mode->crtc_htotal / 2;
7695 if (vsyncshift < 0)
7696 vsyncshift += adjusted_mode->crtc_htotal;
7697 }
7698
7699 if (INTEL_INFO(dev)->gen > 3)
7700 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7701
7702 I915_WRITE(HTOTAL(cpu_transcoder),
7703 (adjusted_mode->crtc_hdisplay - 1) |
7704 ((adjusted_mode->crtc_htotal - 1) << 16));
7705 I915_WRITE(HBLANK(cpu_transcoder),
7706 (adjusted_mode->crtc_hblank_start - 1) |
7707 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7708 I915_WRITE(HSYNC(cpu_transcoder),
7709 (adjusted_mode->crtc_hsync_start - 1) |
7710 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7711
7712 I915_WRITE(VTOTAL(cpu_transcoder),
7713 (adjusted_mode->crtc_vdisplay - 1) |
7714 ((crtc_vtotal - 1) << 16));
7715 I915_WRITE(VBLANK(cpu_transcoder),
7716 (adjusted_mode->crtc_vblank_start - 1) |
7717 ((crtc_vblank_end - 1) << 16));
7718 I915_WRITE(VSYNC(cpu_transcoder),
7719 (adjusted_mode->crtc_vsync_start - 1) |
7720 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7721
7722 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7723 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7724 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7725 * bits. */
7726 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7727 (pipe == PIPE_B || pipe == PIPE_C))
7728 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7729
7730 /* pipesrc controls the size that is scaled from, which should
7731 * always be the user's requested size.
7732 */
7733 I915_WRITE(PIPESRC(pipe),
7734 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7735 (intel_crtc->config->pipe_src_h - 1));
7736}
7737
7738static void intel_get_pipe_timings(struct intel_crtc *crtc,
7739 struct intel_crtc_state *pipe_config)
7740{
7741 struct drm_device *dev = crtc->base.dev;
7742 struct drm_i915_private *dev_priv = dev->dev_private;
7743 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7744 uint32_t tmp;
7745
7746 tmp = I915_READ(HTOTAL(cpu_transcoder));
7747 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7748 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7749 tmp = I915_READ(HBLANK(cpu_transcoder));
7750 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7751 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7752 tmp = I915_READ(HSYNC(cpu_transcoder));
7753 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7754 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7755
7756 tmp = I915_READ(VTOTAL(cpu_transcoder));
7757 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7758 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7759 tmp = I915_READ(VBLANK(cpu_transcoder));
7760 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7761 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7762 tmp = I915_READ(VSYNC(cpu_transcoder));
7763 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7764 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7765
7766 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7767 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7768 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7769 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7770 }
7771
7772 tmp = I915_READ(PIPESRC(crtc->pipe));
7773 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7774 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7775
7776 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7777 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7778}
7779
7780void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7781 struct intel_crtc_state *pipe_config)
7782{
7783 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7784 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7785 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7786 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7787
7788 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7789 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7790 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7791 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7792
7793 mode->flags = pipe_config->base.adjusted_mode.flags;
7794
7795 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7796 mode->flags |= pipe_config->base.adjusted_mode.flags;
7797}
7798
7799static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7800{
7801 struct drm_device *dev = intel_crtc->base.dev;
7802 struct drm_i915_private *dev_priv = dev->dev_private;
7803 uint32_t pipeconf;
7804
7805 pipeconf = 0;
7806
7807 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7808 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7809 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7810
7811 if (intel_crtc->config->double_wide)
7812 pipeconf |= PIPECONF_DOUBLE_WIDE;
7813
7814 /* only g4x and later have fancy bpc/dither controls */
7815 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7816 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7817 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7818 pipeconf |= PIPECONF_DITHER_EN |
7819 PIPECONF_DITHER_TYPE_SP;
7820
7821 switch (intel_crtc->config->pipe_bpp) {
7822 case 18:
7823 pipeconf |= PIPECONF_6BPC;
7824 break;
7825 case 24:
7826 pipeconf |= PIPECONF_8BPC;
7827 break;
7828 case 30:
7829 pipeconf |= PIPECONF_10BPC;
7830 break;
7831 default:
7832 /* Case prevented by intel_choose_pipe_bpp_dither. */
7833 BUG();
7834 }
7835 }
7836
7837 if (HAS_PIPE_CXSR(dev)) {
7838 if (intel_crtc->lowfreq_avail) {
7839 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7840 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7841 } else {
7842 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7843 }
7844 }
7845
7846 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7847 if (INTEL_INFO(dev)->gen < 4 ||
7848 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7849 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7850 else
7851 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7852 } else
7853 pipeconf |= PIPECONF_PROGRESSIVE;
7854
7855 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7856 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7857
7858 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7859 POSTING_READ(PIPECONF(intel_crtc->pipe));
7860}
7861
7862static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7863 struct intel_crtc_state *crtc_state)
7864{
7865 struct drm_device *dev = crtc->base.dev;
7866 struct drm_i915_private *dev_priv = dev->dev_private;
7867 int refclk, num_connectors = 0;
7868 intel_clock_t clock, reduced_clock;
7869 bool ok, has_reduced_clock = false;
7870 bool is_lvds = false, is_dsi = false;
7871 struct intel_encoder *encoder;
7872 const intel_limit_t *limit;
7873 struct drm_atomic_state *state = crtc_state->base.state;
7874 struct drm_connector *connector;
7875 struct drm_connector_state *connector_state;
7876 int i;
7877
7878 memset(&crtc_state->dpll_hw_state, 0,
7879 sizeof(crtc_state->dpll_hw_state));
7880
7881 for_each_connector_in_state(state, connector, connector_state, i) {
7882 if (connector_state->crtc != &crtc->base)
7883 continue;
7884
7885 encoder = to_intel_encoder(connector_state->best_encoder);
7886
7887 switch (encoder->type) {
7888 case INTEL_OUTPUT_LVDS:
7889 is_lvds = true;
7890 break;
7891 case INTEL_OUTPUT_DSI:
7892 is_dsi = true;
7893 break;
7894 default:
7895 break;
7896 }
7897
7898 num_connectors++;
7899 }
7900
7901 if (is_dsi)
7902 return 0;
7903
7904 if (!crtc_state->clock_set) {
7905 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7906
7907 /*
7908 * Returns a set of divisors for the desired target clock with
7909 * the given refclk, or FALSE. The returned values represent
7910 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7911 * 2) / p1 / p2.
7912 */
7913 limit = intel_limit(crtc_state, refclk);
7914 ok = dev_priv->display.find_dpll(limit, crtc_state,
7915 crtc_state->port_clock,
7916 refclk, NULL, &clock);
7917 if (!ok) {
7918 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7919 return -EINVAL;
7920 }
7921
7922 if (is_lvds && dev_priv->lvds_downclock_avail) {
7923 /*
7924 * Ensure we match the reduced clock's P to the target
7925 * clock. If the clocks don't match, we can't switch
7926 * the display clock by using the FP0/FP1. In such case
7927 * we will disable the LVDS downclock feature.
7928 */
7929 has_reduced_clock =
7930 dev_priv->display.find_dpll(limit, crtc_state,
7931 dev_priv->lvds_downclock,
7932 refclk, &clock,
7933 &reduced_clock);
7934 }
7935 /* Compat-code for transition, will disappear. */
7936 crtc_state->dpll.n = clock.n;
7937 crtc_state->dpll.m1 = clock.m1;
7938 crtc_state->dpll.m2 = clock.m2;
7939 crtc_state->dpll.p1 = clock.p1;
7940 crtc_state->dpll.p2 = clock.p2;
7941 }
7942
7943 if (IS_GEN2(dev)) {
7944 i8xx_update_pll(crtc, crtc_state,
7945 has_reduced_clock ? &reduced_clock : NULL,
7946 num_connectors);
7947 } else if (IS_CHERRYVIEW(dev)) {
7948 chv_update_pll(crtc, crtc_state);
7949 } else if (IS_VALLEYVIEW(dev)) {
7950 vlv_update_pll(crtc, crtc_state);
7951 } else {
7952 i9xx_update_pll(crtc, crtc_state,
7953 has_reduced_clock ? &reduced_clock : NULL,
7954 num_connectors);
7955 }
7956
7957 return 0;
7958}
7959
7960static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7961 struct intel_crtc_state *pipe_config)
7962{
7963 struct drm_device *dev = crtc->base.dev;
7964 struct drm_i915_private *dev_priv = dev->dev_private;
7965 uint32_t tmp;
7966
7967 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7968 return;
7969
7970 tmp = I915_READ(PFIT_CONTROL);
7971 if (!(tmp & PFIT_ENABLE))
7972 return;
7973
7974 /* Check whether the pfit is attached to our pipe. */
7975 if (INTEL_INFO(dev)->gen < 4) {
7976 if (crtc->pipe != PIPE_B)
7977 return;
7978 } else {
7979 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7980 return;
7981 }
7982
7983 pipe_config->gmch_pfit.control = tmp;
7984 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7985 if (INTEL_INFO(dev)->gen < 5)
7986 pipe_config->gmch_pfit.lvds_border_bits =
7987 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7988}
7989
7990static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7991 struct intel_crtc_state *pipe_config)
7992{
7993 struct drm_device *dev = crtc->base.dev;
7994 struct drm_i915_private *dev_priv = dev->dev_private;
7995 int pipe = pipe_config->cpu_transcoder;
7996 intel_clock_t clock;
7997 u32 mdiv;
7998 int refclk = 100000;
7999
8000 /* In case of MIPI DPLL will not even be used */
8001 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8002 return;
8003
8004 mutex_lock(&dev_priv->sb_lock);
8005 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8006 mutex_unlock(&dev_priv->sb_lock);
8007
8008 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8009 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8010 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8011 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8012 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8013
8014 vlv_clock(refclk, &clock);
8015
8016 /* clock.dot is the fast clock */
8017 pipe_config->port_clock = clock.dot / 5;
8018}
8019
8020static void
8021i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8022 struct intel_initial_plane_config *plane_config)
8023{
8024 struct drm_device *dev = crtc->base.dev;
8025 struct drm_i915_private *dev_priv = dev->dev_private;
8026 u32 val, base, offset;
8027 int pipe = crtc->pipe, plane = crtc->plane;
8028 int fourcc, pixel_format;
8029 unsigned int aligned_height;
8030 struct drm_framebuffer *fb;
8031 struct intel_framebuffer *intel_fb;
8032
8033 val = I915_READ(DSPCNTR(plane));
8034 if (!(val & DISPLAY_PLANE_ENABLE))
8035 return;
8036
8037 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8038 if (!intel_fb) {
8039 DRM_DEBUG_KMS("failed to alloc fb\n");
8040 return;
8041 }
8042
8043 fb = &intel_fb->base;
8044
8045 if (INTEL_INFO(dev)->gen >= 4) {
8046 if (val & DISPPLANE_TILED) {
8047 plane_config->tiling = I915_TILING_X;
8048 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8049 }
8050 }
8051
8052 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8053 fourcc = i9xx_format_to_fourcc(pixel_format);
8054 fb->pixel_format = fourcc;
8055 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8056
8057 if (INTEL_INFO(dev)->gen >= 4) {
8058 if (plane_config->tiling)
8059 offset = I915_READ(DSPTILEOFF(plane));
8060 else
8061 offset = I915_READ(DSPLINOFF(plane));
8062 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8063 } else {
8064 base = I915_READ(DSPADDR(plane));
8065 }
8066 plane_config->base = base;
8067
8068 val = I915_READ(PIPESRC(pipe));
8069 fb->width = ((val >> 16) & 0xfff) + 1;
8070 fb->height = ((val >> 0) & 0xfff) + 1;
8071
8072 val = I915_READ(DSPSTRIDE(pipe));
8073 fb->pitches[0] = val & 0xffffffc0;
8074
8075 aligned_height = intel_fb_align_height(dev, fb->height,
8076 fb->pixel_format,
8077 fb->modifier[0]);
8078
8079 plane_config->size = fb->pitches[0] * aligned_height;
8080
8081 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8082 pipe_name(pipe), plane, fb->width, fb->height,
8083 fb->bits_per_pixel, base, fb->pitches[0],
8084 plane_config->size);
8085
8086 plane_config->fb = intel_fb;
8087}
8088
8089static void chv_crtc_clock_get(struct intel_crtc *crtc,
8090 struct intel_crtc_state *pipe_config)
8091{
8092 struct drm_device *dev = crtc->base.dev;
8093 struct drm_i915_private *dev_priv = dev->dev_private;
8094 int pipe = pipe_config->cpu_transcoder;
8095 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8096 intel_clock_t clock;
8097 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8098 int refclk = 100000;
8099
8100 mutex_lock(&dev_priv->sb_lock);
8101 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8102 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8103 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8104 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8105 mutex_unlock(&dev_priv->sb_lock);
8106
8107 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8108 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8109 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8110 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8111 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8112
8113 chv_clock(refclk, &clock);
8114
8115 /* clock.dot is the fast clock */
8116 pipe_config->port_clock = clock.dot / 5;
8117}
8118
8119static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8120 struct intel_crtc_state *pipe_config)
8121{
8122 struct drm_device *dev = crtc->base.dev;
8123 struct drm_i915_private *dev_priv = dev->dev_private;
8124 uint32_t tmp;
8125
8126 if (!intel_display_power_is_enabled(dev_priv,
8127 POWER_DOMAIN_PIPE(crtc->pipe)))
8128 return false;
8129
8130 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8131 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8132
8133 tmp = I915_READ(PIPECONF(crtc->pipe));
8134 if (!(tmp & PIPECONF_ENABLE))
8135 return false;
8136
8137 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8138 switch (tmp & PIPECONF_BPC_MASK) {
8139 case PIPECONF_6BPC:
8140 pipe_config->pipe_bpp = 18;
8141 break;
8142 case PIPECONF_8BPC:
8143 pipe_config->pipe_bpp = 24;
8144 break;
8145 case PIPECONF_10BPC:
8146 pipe_config->pipe_bpp = 30;
8147 break;
8148 default:
8149 break;
8150 }
8151 }
8152
8153 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8154 pipe_config->limited_color_range = true;
8155
8156 if (INTEL_INFO(dev)->gen < 4)
8157 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8158
8159 intel_get_pipe_timings(crtc, pipe_config);
8160
8161 i9xx_get_pfit_config(crtc, pipe_config);
8162
8163 if (INTEL_INFO(dev)->gen >= 4) {
8164 tmp = I915_READ(DPLL_MD(crtc->pipe));
8165 pipe_config->pixel_multiplier =
8166 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8167 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8168 pipe_config->dpll_hw_state.dpll_md = tmp;
8169 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8170 tmp = I915_READ(DPLL(crtc->pipe));
8171 pipe_config->pixel_multiplier =
8172 ((tmp & SDVO_MULTIPLIER_MASK)
8173 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8174 } else {
8175 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8176 * port and will be fixed up in the encoder->get_config
8177 * function. */
8178 pipe_config->pixel_multiplier = 1;
8179 }
8180 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8181 if (!IS_VALLEYVIEW(dev)) {
8182 /*
8183 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8184 * on 830. Filter it out here so that we don't
8185 * report errors due to that.
8186 */
8187 if (IS_I830(dev))
8188 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8189
8190 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8191 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8192 } else {
8193 /* Mask out read-only status bits. */
8194 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8195 DPLL_PORTC_READY_MASK |
8196 DPLL_PORTB_READY_MASK);
8197 }
8198
8199 if (IS_CHERRYVIEW(dev))
8200 chv_crtc_clock_get(crtc, pipe_config);
8201 else if (IS_VALLEYVIEW(dev))
8202 vlv_crtc_clock_get(crtc, pipe_config);
8203 else
8204 i9xx_crtc_clock_get(crtc, pipe_config);
8205
8206 return true;
8207}
8208
8209static void ironlake_init_pch_refclk(struct drm_device *dev)
8210{
8211 struct drm_i915_private *dev_priv = dev->dev_private;
8212 struct intel_encoder *encoder;
8213 u32 val, final;
8214 bool has_lvds = false;
8215 bool has_cpu_edp = false;
8216 bool has_panel = false;
8217 bool has_ck505 = false;
8218 bool can_ssc = false;
8219
8220 /* We need to take the global config into account */
8221 for_each_intel_encoder(dev, encoder) {
8222 switch (encoder->type) {
8223 case INTEL_OUTPUT_LVDS:
8224 has_panel = true;
8225 has_lvds = true;
8226 break;
8227 case INTEL_OUTPUT_EDP:
8228 has_panel = true;
8229 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8230 has_cpu_edp = true;
8231 break;
8232 default:
8233 break;
8234 }
8235 }
8236
8237 if (HAS_PCH_IBX(dev)) {
8238 has_ck505 = dev_priv->vbt.display_clock_mode;
8239 can_ssc = has_ck505;
8240 } else {
8241 has_ck505 = false;
8242 can_ssc = true;
8243 }
8244
8245 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8246 has_panel, has_lvds, has_ck505);
8247
8248 /* Ironlake: try to setup display ref clock before DPLL
8249 * enabling. This is only under driver's control after
8250 * PCH B stepping, previous chipset stepping should be
8251 * ignoring this setting.
8252 */
8253 val = I915_READ(PCH_DREF_CONTROL);
8254
8255 /* As we must carefully and slowly disable/enable each source in turn,
8256 * compute the final state we want first and check if we need to
8257 * make any changes at all.
8258 */
8259 final = val;
8260 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8261 if (has_ck505)
8262 final |= DREF_NONSPREAD_CK505_ENABLE;
8263 else
8264 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8265
8266 final &= ~DREF_SSC_SOURCE_MASK;
8267 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8268 final &= ~DREF_SSC1_ENABLE;
8269
8270 if (has_panel) {
8271 final |= DREF_SSC_SOURCE_ENABLE;
8272
8273 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8274 final |= DREF_SSC1_ENABLE;
8275
8276 if (has_cpu_edp) {
8277 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8278 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8279 else
8280 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8281 } else
8282 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8283 } else {
8284 final |= DREF_SSC_SOURCE_DISABLE;
8285 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8286 }
8287
8288 if (final == val)
8289 return;
8290
8291 /* Always enable nonspread source */
8292 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8293
8294 if (has_ck505)
8295 val |= DREF_NONSPREAD_CK505_ENABLE;
8296 else
8297 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8298
8299 if (has_panel) {
8300 val &= ~DREF_SSC_SOURCE_MASK;
8301 val |= DREF_SSC_SOURCE_ENABLE;
8302
8303 /* SSC must be turned on before enabling the CPU output */
8304 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8305 DRM_DEBUG_KMS("Using SSC on panel\n");
8306 val |= DREF_SSC1_ENABLE;
8307 } else
8308 val &= ~DREF_SSC1_ENABLE;
8309
8310 /* Get SSC going before enabling the outputs */
8311 I915_WRITE(PCH_DREF_CONTROL, val);
8312 POSTING_READ(PCH_DREF_CONTROL);
8313 udelay(200);
8314
8315 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8316
8317 /* Enable CPU source on CPU attached eDP */
8318 if (has_cpu_edp) {
8319 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8320 DRM_DEBUG_KMS("Using SSC on eDP\n");
8321 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8322 } else
8323 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8324 } else
8325 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8326
8327 I915_WRITE(PCH_DREF_CONTROL, val);
8328 POSTING_READ(PCH_DREF_CONTROL);
8329 udelay(200);
8330 } else {
8331 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8332
8333 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8334
8335 /* Turn off CPU output */
8336 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8337
8338 I915_WRITE(PCH_DREF_CONTROL, val);
8339 POSTING_READ(PCH_DREF_CONTROL);
8340 udelay(200);
8341
8342 /* Turn off the SSC source */
8343 val &= ~DREF_SSC_SOURCE_MASK;
8344 val |= DREF_SSC_SOURCE_DISABLE;
8345
8346 /* Turn off SSC1 */
8347 val &= ~DREF_SSC1_ENABLE;
8348
8349 I915_WRITE(PCH_DREF_CONTROL, val);
8350 POSTING_READ(PCH_DREF_CONTROL);
8351 udelay(200);
8352 }
8353
8354 BUG_ON(val != final);
8355}
8356
8357static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8358{
8359 uint32_t tmp;
8360
8361 tmp = I915_READ(SOUTH_CHICKEN2);
8362 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8363 I915_WRITE(SOUTH_CHICKEN2, tmp);
8364
8365 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8366 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8367 DRM_ERROR("FDI mPHY reset assert timeout\n");
8368
8369 tmp = I915_READ(SOUTH_CHICKEN2);
8370 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8371 I915_WRITE(SOUTH_CHICKEN2, tmp);
8372
8373 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8374 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8375 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8376}
8377
8378/* WaMPhyProgramming:hsw */
8379static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8380{
8381 uint32_t tmp;
8382
8383 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8384 tmp &= ~(0xFF << 24);
8385 tmp |= (0x12 << 24);
8386 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8387
8388 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8389 tmp |= (1 << 11);
8390 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8391
8392 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8393 tmp |= (1 << 11);
8394 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8395
8396 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8397 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8398 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8399
8400 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8401 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8402 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8403
8404 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8405 tmp &= ~(7 << 13);
8406 tmp |= (5 << 13);
8407 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8408
8409 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8410 tmp &= ~(7 << 13);
8411 tmp |= (5 << 13);
8412 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8413
8414 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8415 tmp &= ~0xFF;
8416 tmp |= 0x1C;
8417 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8418
8419 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8420 tmp &= ~0xFF;
8421 tmp |= 0x1C;
8422 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8423
8424 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8425 tmp &= ~(0xFF << 16);
8426 tmp |= (0x1C << 16);
8427 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8428
8429 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8430 tmp &= ~(0xFF << 16);
8431 tmp |= (0x1C << 16);
8432 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8433
8434 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8435 tmp |= (1 << 27);
8436 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8437
8438 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8439 tmp |= (1 << 27);
8440 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8441
8442 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8443 tmp &= ~(0xF << 28);
8444 tmp |= (4 << 28);
8445 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8446
8447 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8448 tmp &= ~(0xF << 28);
8449 tmp |= (4 << 28);
8450 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8451}
8452
8453/* Implements 3 different sequences from BSpec chapter "Display iCLK
8454 * Programming" based on the parameters passed:
8455 * - Sequence to enable CLKOUT_DP
8456 * - Sequence to enable CLKOUT_DP without spread
8457 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8458 */
8459static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8460 bool with_fdi)
8461{
8462 struct drm_i915_private *dev_priv = dev->dev_private;
8463 uint32_t reg, tmp;
8464
8465 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8466 with_spread = true;
8467 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8468 with_fdi, "LP PCH doesn't have FDI\n"))
8469 with_fdi = false;
8470
8471 mutex_lock(&dev_priv->sb_lock);
8472
8473 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8474 tmp &= ~SBI_SSCCTL_DISABLE;
8475 tmp |= SBI_SSCCTL_PATHALT;
8476 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8477
8478 udelay(24);
8479
8480 if (with_spread) {
8481 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8482 tmp &= ~SBI_SSCCTL_PATHALT;
8483 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8484
8485 if (with_fdi) {
8486 lpt_reset_fdi_mphy(dev_priv);
8487 lpt_program_fdi_mphy(dev_priv);
8488 }
8489 }
8490
8491 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8492 SBI_GEN0 : SBI_DBUFF0;
8493 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8494 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8495 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8496
8497 mutex_unlock(&dev_priv->sb_lock);
8498}
8499
8500/* Sequence to disable CLKOUT_DP */
8501static void lpt_disable_clkout_dp(struct drm_device *dev)
8502{
8503 struct drm_i915_private *dev_priv = dev->dev_private;
8504 uint32_t reg, tmp;
8505
8506 mutex_lock(&dev_priv->sb_lock);
8507
8508 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8509 SBI_GEN0 : SBI_DBUFF0;
8510 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8511 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8512 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8513
8514 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8515 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8516 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8517 tmp |= SBI_SSCCTL_PATHALT;
8518 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8519 udelay(32);
8520 }
8521 tmp |= SBI_SSCCTL_DISABLE;
8522 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8523 }
8524
8525 mutex_unlock(&dev_priv->sb_lock);
8526}
8527
8528static void lpt_init_pch_refclk(struct drm_device *dev)
8529{
8530 struct intel_encoder *encoder;
8531 bool has_vga = false;
8532
8533 for_each_intel_encoder(dev, encoder) {
8534 switch (encoder->type) {
8535 case INTEL_OUTPUT_ANALOG:
8536 has_vga = true;
8537 break;
8538 default:
8539 break;
8540 }
8541 }
8542
8543 if (has_vga)
8544 lpt_enable_clkout_dp(dev, true, true);
8545 else
8546 lpt_disable_clkout_dp(dev);
8547}
8548
8549/*
8550 * Initialize reference clocks when the driver loads
8551 */
8552void intel_init_pch_refclk(struct drm_device *dev)
8553{
8554 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8555 ironlake_init_pch_refclk(dev);
8556 else if (HAS_PCH_LPT(dev))
8557 lpt_init_pch_refclk(dev);
8558}
8559
8560static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8561{
8562 struct drm_device *dev = crtc_state->base.crtc->dev;
8563 struct drm_i915_private *dev_priv = dev->dev_private;
8564 struct drm_atomic_state *state = crtc_state->base.state;
8565 struct drm_connector *connector;
8566 struct drm_connector_state *connector_state;
8567 struct intel_encoder *encoder;
8568 int num_connectors = 0, i;
8569 bool is_lvds = false;
8570
8571 for_each_connector_in_state(state, connector, connector_state, i) {
8572 if (connector_state->crtc != crtc_state->base.crtc)
8573 continue;
8574
8575 encoder = to_intel_encoder(connector_state->best_encoder);
8576
8577 switch (encoder->type) {
8578 case INTEL_OUTPUT_LVDS:
8579 is_lvds = true;
8580 break;
8581 default:
8582 break;
8583 }
8584 num_connectors++;
8585 }
8586
8587 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8588 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8589 dev_priv->vbt.lvds_ssc_freq);
8590 return dev_priv->vbt.lvds_ssc_freq;
8591 }
8592
8593 return 120000;
8594}
8595
8596static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8597{
8598 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8600 int pipe = intel_crtc->pipe;
8601 uint32_t val;
8602
8603 val = 0;
8604
8605 switch (intel_crtc->config->pipe_bpp) {
8606 case 18:
8607 val |= PIPECONF_6BPC;
8608 break;
8609 case 24:
8610 val |= PIPECONF_8BPC;
8611 break;
8612 case 30:
8613 val |= PIPECONF_10BPC;
8614 break;
8615 case 36:
8616 val |= PIPECONF_12BPC;
8617 break;
8618 default:
8619 /* Case prevented by intel_choose_pipe_bpp_dither. */
8620 BUG();
8621 }
8622
8623 if (intel_crtc->config->dither)
8624 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8625
8626 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8627 val |= PIPECONF_INTERLACED_ILK;
8628 else
8629 val |= PIPECONF_PROGRESSIVE;
8630
8631 if (intel_crtc->config->limited_color_range)
8632 val |= PIPECONF_COLOR_RANGE_SELECT;
8633
8634 I915_WRITE(PIPECONF(pipe), val);
8635 POSTING_READ(PIPECONF(pipe));
8636}
8637
8638/*
8639 * Set up the pipe CSC unit.
8640 *
8641 * Currently only full range RGB to limited range RGB conversion
8642 * is supported, but eventually this should handle various
8643 * RGB<->YCbCr scenarios as well.
8644 */
8645static void intel_set_pipe_csc(struct drm_crtc *crtc)
8646{
8647 struct drm_device *dev = crtc->dev;
8648 struct drm_i915_private *dev_priv = dev->dev_private;
8649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8650 int pipe = intel_crtc->pipe;
8651 uint16_t coeff = 0x7800; /* 1.0 */
8652
8653 /*
8654 * TODO: Check what kind of values actually come out of the pipe
8655 * with these coeff/postoff values and adjust to get the best
8656 * accuracy. Perhaps we even need to take the bpc value into
8657 * consideration.
8658 */
8659
8660 if (intel_crtc->config->limited_color_range)
8661 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8662
8663 /*
8664 * GY/GU and RY/RU should be the other way around according
8665 * to BSpec, but reality doesn't agree. Just set them up in
8666 * a way that results in the correct picture.
8667 */
8668 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8669 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8670
8671 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8672 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8673
8674 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8675 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8676
8677 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8678 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8679 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8680
8681 if (INTEL_INFO(dev)->gen > 6) {
8682 uint16_t postoff = 0;
8683
8684 if (intel_crtc->config->limited_color_range)
8685 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8686
8687 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8688 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8689 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8690
8691 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8692 } else {
8693 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8694
8695 if (intel_crtc->config->limited_color_range)
8696 mode |= CSC_BLACK_SCREEN_OFFSET;
8697
8698 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8699 }
8700}
8701
8702static void haswell_set_pipeconf(struct drm_crtc *crtc)
8703{
8704 struct drm_device *dev = crtc->dev;
8705 struct drm_i915_private *dev_priv = dev->dev_private;
8706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8707 enum pipe pipe = intel_crtc->pipe;
8708 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8709 uint32_t val;
8710
8711 val = 0;
8712
8713 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8714 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8715
8716 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8717 val |= PIPECONF_INTERLACED_ILK;
8718 else
8719 val |= PIPECONF_PROGRESSIVE;
8720
8721 I915_WRITE(PIPECONF(cpu_transcoder), val);
8722 POSTING_READ(PIPECONF(cpu_transcoder));
8723
8724 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8725 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8726
8727 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8728 val = 0;
8729
8730 switch (intel_crtc->config->pipe_bpp) {
8731 case 18:
8732 val |= PIPEMISC_DITHER_6_BPC;
8733 break;
8734 case 24:
8735 val |= PIPEMISC_DITHER_8_BPC;
8736 break;
8737 case 30:
8738 val |= PIPEMISC_DITHER_10_BPC;
8739 break;
8740 case 36:
8741 val |= PIPEMISC_DITHER_12_BPC;
8742 break;
8743 default:
8744 /* Case prevented by pipe_config_set_bpp. */
8745 BUG();
8746 }
8747
8748 if (intel_crtc->config->dither)
8749 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8750
8751 I915_WRITE(PIPEMISC(pipe), val);
8752 }
8753}
8754
8755static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8756 struct intel_crtc_state *crtc_state,
8757 intel_clock_t *clock,
8758 bool *has_reduced_clock,
8759 intel_clock_t *reduced_clock)
8760{
8761 struct drm_device *dev = crtc->dev;
8762 struct drm_i915_private *dev_priv = dev->dev_private;
8763 int refclk;
8764 const intel_limit_t *limit;
8765 bool ret, is_lvds = false;
8766
8767 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8768
8769 refclk = ironlake_get_refclk(crtc_state);
8770
8771 /*
8772 * Returns a set of divisors for the desired target clock with the given
8773 * refclk, or FALSE. The returned values represent the clock equation:
8774 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8775 */
8776 limit = intel_limit(crtc_state, refclk);
8777 ret = dev_priv->display.find_dpll(limit, crtc_state,
8778 crtc_state->port_clock,
8779 refclk, NULL, clock);
8780 if (!ret)
8781 return false;
8782
8783 if (is_lvds && dev_priv->lvds_downclock_avail) {
8784 /*
8785 * Ensure we match the reduced clock's P to the target clock.
8786 * If the clocks don't match, we can't switch the display clock
8787 * by using the FP0/FP1. In such case we will disable the LVDS
8788 * downclock feature.
8789 */
8790 *has_reduced_clock =
8791 dev_priv->display.find_dpll(limit, crtc_state,
8792 dev_priv->lvds_downclock,
8793 refclk, clock,
8794 reduced_clock);
8795 }
8796
8797 return true;
8798}
8799
8800int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8801{
8802 /*
8803 * Account for spread spectrum to avoid
8804 * oversubscribing the link. Max center spread
8805 * is 2.5%; use 5% for safety's sake.
8806 */
8807 u32 bps = target_clock * bpp * 21 / 20;
8808 return DIV_ROUND_UP(bps, link_bw * 8);
8809}
8810
8811static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8812{
8813 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8814}
8815
8816static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8817 struct intel_crtc_state *crtc_state,
8818 u32 *fp,
8819 intel_clock_t *reduced_clock, u32 *fp2)
8820{
8821 struct drm_crtc *crtc = &intel_crtc->base;
8822 struct drm_device *dev = crtc->dev;
8823 struct drm_i915_private *dev_priv = dev->dev_private;
8824 struct drm_atomic_state *state = crtc_state->base.state;
8825 struct drm_connector *connector;
8826 struct drm_connector_state *connector_state;
8827 struct intel_encoder *encoder;
8828 uint32_t dpll;
8829 int factor, num_connectors = 0, i;
8830 bool is_lvds = false, is_sdvo = false;
8831
8832 for_each_connector_in_state(state, connector, connector_state, i) {
8833 if (connector_state->crtc != crtc_state->base.crtc)
8834 continue;
8835
8836 encoder = to_intel_encoder(connector_state->best_encoder);
8837
8838 switch (encoder->type) {
8839 case INTEL_OUTPUT_LVDS:
8840 is_lvds = true;
8841 break;
8842 case INTEL_OUTPUT_SDVO:
8843 case INTEL_OUTPUT_HDMI:
8844 is_sdvo = true;
8845 break;
8846 default:
8847 break;
8848 }
8849
8850 num_connectors++;
8851 }
8852
8853 /* Enable autotuning of the PLL clock (if permissible) */
8854 factor = 21;
8855 if (is_lvds) {
8856 if ((intel_panel_use_ssc(dev_priv) &&
8857 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8858 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8859 factor = 25;
8860 } else if (crtc_state->sdvo_tv_clock)
8861 factor = 20;
8862
8863 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8864 *fp |= FP_CB_TUNE;
8865
8866 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8867 *fp2 |= FP_CB_TUNE;
8868
8869 dpll = 0;
8870
8871 if (is_lvds)
8872 dpll |= DPLLB_MODE_LVDS;
8873 else
8874 dpll |= DPLLB_MODE_DAC_SERIAL;
8875
8876 dpll |= (crtc_state->pixel_multiplier - 1)
8877 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8878
8879 if (is_sdvo)
8880 dpll |= DPLL_SDVO_HIGH_SPEED;
8881 if (crtc_state->has_dp_encoder)
8882 dpll |= DPLL_SDVO_HIGH_SPEED;
8883
8884 /* compute bitmask from p1 value */
8885 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8886 /* also FPA1 */
8887 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8888
8889 switch (crtc_state->dpll.p2) {
8890 case 5:
8891 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8892 break;
8893 case 7:
8894 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8895 break;
8896 case 10:
8897 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8898 break;
8899 case 14:
8900 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8901 break;
8902 }
8903
8904 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8905 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8906 else
8907 dpll |= PLL_REF_INPUT_DREFCLK;
8908
8909 return dpll | DPLL_VCO_ENABLE;
8910}
8911
8912static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8913 struct intel_crtc_state *crtc_state)
8914{
8915 struct drm_device *dev = crtc->base.dev;
8916 intel_clock_t clock, reduced_clock;
8917 u32 dpll = 0, fp = 0, fp2 = 0;
8918 bool ok, has_reduced_clock = false;
8919 bool is_lvds = false;
8920 struct intel_shared_dpll *pll;
8921
8922 memset(&crtc_state->dpll_hw_state, 0,
8923 sizeof(crtc_state->dpll_hw_state));
8924
8925 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8926
8927 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8928 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8929
8930 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8931 &has_reduced_clock, &reduced_clock);
8932 if (!ok && !crtc_state->clock_set) {
8933 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8934 return -EINVAL;
8935 }
8936 /* Compat-code for transition, will disappear. */
8937 if (!crtc_state->clock_set) {
8938 crtc_state->dpll.n = clock.n;
8939 crtc_state->dpll.m1 = clock.m1;
8940 crtc_state->dpll.m2 = clock.m2;
8941 crtc_state->dpll.p1 = clock.p1;
8942 crtc_state->dpll.p2 = clock.p2;
8943 }
8944
8945 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8946 if (crtc_state->has_pch_encoder) {
8947 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8948 if (has_reduced_clock)
8949 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8950
8951 dpll = ironlake_compute_dpll(crtc, crtc_state,
8952 &fp, &reduced_clock,
8953 has_reduced_clock ? &fp2 : NULL);
8954
8955 crtc_state->dpll_hw_state.dpll = dpll;
8956 crtc_state->dpll_hw_state.fp0 = fp;
8957 if (has_reduced_clock)
8958 crtc_state->dpll_hw_state.fp1 = fp2;
8959 else
8960 crtc_state->dpll_hw_state.fp1 = fp;
8961
8962 pll = intel_get_shared_dpll(crtc, crtc_state);
8963 if (pll == NULL) {
8964 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8965 pipe_name(crtc->pipe));
8966 return -EINVAL;
8967 }
8968 }
8969
8970 if (is_lvds && has_reduced_clock)
8971 crtc->lowfreq_avail = true;
8972 else
8973 crtc->lowfreq_avail = false;
8974
8975 return 0;
8976}
8977
8978static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8979 struct intel_link_m_n *m_n)
8980{
8981 struct drm_device *dev = crtc->base.dev;
8982 struct drm_i915_private *dev_priv = dev->dev_private;
8983 enum pipe pipe = crtc->pipe;
8984
8985 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8986 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8987 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8988 & ~TU_SIZE_MASK;
8989 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8990 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8991 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8992}
8993
8994static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8995 enum transcoder transcoder,
8996 struct intel_link_m_n *m_n,
8997 struct intel_link_m_n *m2_n2)
8998{
8999 struct drm_device *dev = crtc->base.dev;
9000 struct drm_i915_private *dev_priv = dev->dev_private;
9001 enum pipe pipe = crtc->pipe;
9002
9003 if (INTEL_INFO(dev)->gen >= 5) {
9004 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9005 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9006 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9007 & ~TU_SIZE_MASK;
9008 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9009 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9010 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9011 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9012 * gen < 8) and if DRRS is supported (to make sure the
9013 * registers are not unnecessarily read).
9014 */
9015 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9016 crtc->config->has_drrs) {
9017 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9018 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9019 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9020 & ~TU_SIZE_MASK;
9021 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9022 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9023 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9024 }
9025 } else {
9026 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9027 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9028 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9029 & ~TU_SIZE_MASK;
9030 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9031 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9032 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9033 }
9034}
9035
9036void intel_dp_get_m_n(struct intel_crtc *crtc,
9037 struct intel_crtc_state *pipe_config)
9038{
9039 if (pipe_config->has_pch_encoder)
9040 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9041 else
9042 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9043 &pipe_config->dp_m_n,
9044 &pipe_config->dp_m2_n2);
9045}
9046
9047static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9048 struct intel_crtc_state *pipe_config)
9049{
9050 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9051 &pipe_config->fdi_m_n, NULL);
9052}
9053
9054static void skylake_get_pfit_config(struct intel_crtc *crtc,
9055 struct intel_crtc_state *pipe_config)
9056{
9057 struct drm_device *dev = crtc->base.dev;
9058 struct drm_i915_private *dev_priv = dev->dev_private;
9059 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9060 uint32_t ps_ctrl = 0;
9061 int id = -1;
9062 int i;
9063
9064 /* find scaler attached to this pipe */
9065 for (i = 0; i < crtc->num_scalers; i++) {
9066 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9067 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9068 id = i;
9069 pipe_config->pch_pfit.enabled = true;
9070 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9071 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9072 break;
9073 }
9074 }
9075
9076 scaler_state->scaler_id = id;
9077 if (id >= 0) {
9078 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9079 } else {
9080 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9081 }
9082}
9083
9084static void
9085skylake_get_initial_plane_config(struct intel_crtc *crtc,
9086 struct intel_initial_plane_config *plane_config)
9087{
9088 struct drm_device *dev = crtc->base.dev;
9089 struct drm_i915_private *dev_priv = dev->dev_private;
9090 u32 val, base, offset, stride_mult, tiling;
9091 int pipe = crtc->pipe;
9092 int fourcc, pixel_format;
9093 unsigned int aligned_height;
9094 struct drm_framebuffer *fb;
9095 struct intel_framebuffer *intel_fb;
9096
9097 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9098 if (!intel_fb) {
9099 DRM_DEBUG_KMS("failed to alloc fb\n");
9100 return;
9101 }
9102
9103 fb = &intel_fb->base;
9104
9105 val = I915_READ(PLANE_CTL(pipe, 0));
9106 if (!(val & PLANE_CTL_ENABLE))
9107 goto error;
9108
9109 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9110 fourcc = skl_format_to_fourcc(pixel_format,
9111 val & PLANE_CTL_ORDER_RGBX,
9112 val & PLANE_CTL_ALPHA_MASK);
9113 fb->pixel_format = fourcc;
9114 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9115
9116 tiling = val & PLANE_CTL_TILED_MASK;
9117 switch (tiling) {
9118 case PLANE_CTL_TILED_LINEAR:
9119 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9120 break;
9121 case PLANE_CTL_TILED_X:
9122 plane_config->tiling = I915_TILING_X;
9123 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9124 break;
9125 case PLANE_CTL_TILED_Y:
9126 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9127 break;
9128 case PLANE_CTL_TILED_YF:
9129 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9130 break;
9131 default:
9132 MISSING_CASE(tiling);
9133 goto error;
9134 }
9135
9136 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9137 plane_config->base = base;
9138
9139 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9140
9141 val = I915_READ(PLANE_SIZE(pipe, 0));
9142 fb->height = ((val >> 16) & 0xfff) + 1;
9143 fb->width = ((val >> 0) & 0x1fff) + 1;
9144
9145 val = I915_READ(PLANE_STRIDE(pipe, 0));
9146 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9147 fb->pixel_format);
9148 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9149
9150 aligned_height = intel_fb_align_height(dev, fb->height,
9151 fb->pixel_format,
9152 fb->modifier[0]);
9153
9154 plane_config->size = fb->pitches[0] * aligned_height;
9155
9156 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9157 pipe_name(pipe), fb->width, fb->height,
9158 fb->bits_per_pixel, base, fb->pitches[0],
9159 plane_config->size);
9160
9161 plane_config->fb = intel_fb;
9162 return;
9163
9164error:
9165 kfree(fb);
9166}
9167
9168static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9169 struct intel_crtc_state *pipe_config)
9170{
9171 struct drm_device *dev = crtc->base.dev;
9172 struct drm_i915_private *dev_priv = dev->dev_private;
9173 uint32_t tmp;
9174
9175 tmp = I915_READ(PF_CTL(crtc->pipe));
9176
9177 if (tmp & PF_ENABLE) {
9178 pipe_config->pch_pfit.enabled = true;
9179 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9180 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9181
9182 /* We currently do not free assignements of panel fitters on
9183 * ivb/hsw (since we don't use the higher upscaling modes which
9184 * differentiates them) so just WARN about this case for now. */
9185 if (IS_GEN7(dev)) {
9186 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9187 PF_PIPE_SEL_IVB(crtc->pipe));
9188 }
9189 }
9190}
9191
9192static void
9193ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9194 struct intel_initial_plane_config *plane_config)
9195{
9196 struct drm_device *dev = crtc->base.dev;
9197 struct drm_i915_private *dev_priv = dev->dev_private;
9198 u32 val, base, offset;
9199 int pipe = crtc->pipe;
9200 int fourcc, pixel_format;
9201 unsigned int aligned_height;
9202 struct drm_framebuffer *fb;
9203 struct intel_framebuffer *intel_fb;
9204
9205 val = I915_READ(DSPCNTR(pipe));
9206 if (!(val & DISPLAY_PLANE_ENABLE))
9207 return;
9208
9209 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9210 if (!intel_fb) {
9211 DRM_DEBUG_KMS("failed to alloc fb\n");
9212 return;
9213 }
9214
9215 fb = &intel_fb->base;
9216
9217 if (INTEL_INFO(dev)->gen >= 4) {
9218 if (val & DISPPLANE_TILED) {
9219 plane_config->tiling = I915_TILING_X;
9220 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9221 }
9222 }
9223
9224 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9225 fourcc = i9xx_format_to_fourcc(pixel_format);
9226 fb->pixel_format = fourcc;
9227 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9228
9229 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9230 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9231 offset = I915_READ(DSPOFFSET(pipe));
9232 } else {
9233 if (plane_config->tiling)
9234 offset = I915_READ(DSPTILEOFF(pipe));
9235 else
9236 offset = I915_READ(DSPLINOFF(pipe));
9237 }
9238 plane_config->base = base;
9239
9240 val = I915_READ(PIPESRC(pipe));
9241 fb->width = ((val >> 16) & 0xfff) + 1;
9242 fb->height = ((val >> 0) & 0xfff) + 1;
9243
9244 val = I915_READ(DSPSTRIDE(pipe));
9245 fb->pitches[0] = val & 0xffffffc0;
9246
9247 aligned_height = intel_fb_align_height(dev, fb->height,
9248 fb->pixel_format,
9249 fb->modifier[0]);
9250
9251 plane_config->size = fb->pitches[0] * aligned_height;
9252
9253 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9254 pipe_name(pipe), fb->width, fb->height,
9255 fb->bits_per_pixel, base, fb->pitches[0],
9256 plane_config->size);
9257
9258 plane_config->fb = intel_fb;
9259}
9260
9261static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9262 struct intel_crtc_state *pipe_config)
9263{
9264 struct drm_device *dev = crtc->base.dev;
9265 struct drm_i915_private *dev_priv = dev->dev_private;
9266 uint32_t tmp;
9267
9268 if (!intel_display_power_is_enabled(dev_priv,
9269 POWER_DOMAIN_PIPE(crtc->pipe)))
9270 return false;
9271
9272 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9273 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9274
9275 tmp = I915_READ(PIPECONF(crtc->pipe));
9276 if (!(tmp & PIPECONF_ENABLE))
9277 return false;
9278
9279 switch (tmp & PIPECONF_BPC_MASK) {
9280 case PIPECONF_6BPC:
9281 pipe_config->pipe_bpp = 18;
9282 break;
9283 case PIPECONF_8BPC:
9284 pipe_config->pipe_bpp = 24;
9285 break;
9286 case PIPECONF_10BPC:
9287 pipe_config->pipe_bpp = 30;
9288 break;
9289 case PIPECONF_12BPC:
9290 pipe_config->pipe_bpp = 36;
9291 break;
9292 default:
9293 break;
9294 }
9295
9296 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9297 pipe_config->limited_color_range = true;
9298
9299 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9300 struct intel_shared_dpll *pll;
9301
9302 pipe_config->has_pch_encoder = true;
9303
9304 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9305 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9306 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9307
9308 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9309
9310 if (HAS_PCH_IBX(dev_priv->dev)) {
9311 pipe_config->shared_dpll =
9312 (enum intel_dpll_id) crtc->pipe;
9313 } else {
9314 tmp = I915_READ(PCH_DPLL_SEL);
9315 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9316 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9317 else
9318 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9319 }
9320
9321 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9322
9323 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9324 &pipe_config->dpll_hw_state));
9325
9326 tmp = pipe_config->dpll_hw_state.dpll;
9327 pipe_config->pixel_multiplier =
9328 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9329 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9330
9331 ironlake_pch_clock_get(crtc, pipe_config);
9332 } else {
9333 pipe_config->pixel_multiplier = 1;
9334 }
9335
9336 intel_get_pipe_timings(crtc, pipe_config);
9337
9338 ironlake_get_pfit_config(crtc, pipe_config);
9339
9340 return true;
9341}
9342
9343static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9344{
9345 struct drm_device *dev = dev_priv->dev;
9346 struct intel_crtc *crtc;
9347
9348 for_each_intel_crtc(dev, crtc)
9349 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9350 pipe_name(crtc->pipe));
9351
9352 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9353 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9354 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9355 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9356 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9357 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9358 "CPU PWM1 enabled\n");
9359 if (IS_HASWELL(dev))
9360 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9361 "CPU PWM2 enabled\n");
9362 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9363 "PCH PWM1 enabled\n");
9364 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9365 "Utility pin enabled\n");
9366 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9367
9368 /*
9369 * In theory we can still leave IRQs enabled, as long as only the HPD
9370 * interrupts remain enabled. We used to check for that, but since it's
9371 * gen-specific and since we only disable LCPLL after we fully disable
9372 * the interrupts, the check below should be enough.
9373 */
9374 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9375}
9376
9377static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9378{
9379 struct drm_device *dev = dev_priv->dev;
9380
9381 if (IS_HASWELL(dev))
9382 return I915_READ(D_COMP_HSW);
9383 else
9384 return I915_READ(D_COMP_BDW);
9385}
9386
9387static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9388{
9389 struct drm_device *dev = dev_priv->dev;
9390
9391 if (IS_HASWELL(dev)) {
9392 mutex_lock(&dev_priv->rps.hw_lock);
9393 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9394 val))
9395 DRM_ERROR("Failed to write to D_COMP\n");
9396 mutex_unlock(&dev_priv->rps.hw_lock);
9397 } else {
9398 I915_WRITE(D_COMP_BDW, val);
9399 POSTING_READ(D_COMP_BDW);
9400 }
9401}
9402
9403/*
9404 * This function implements pieces of two sequences from BSpec:
9405 * - Sequence for display software to disable LCPLL
9406 * - Sequence for display software to allow package C8+
9407 * The steps implemented here are just the steps that actually touch the LCPLL
9408 * register. Callers should take care of disabling all the display engine
9409 * functions, doing the mode unset, fixing interrupts, etc.
9410 */
9411static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9412 bool switch_to_fclk, bool allow_power_down)
9413{
9414 uint32_t val;
9415
9416 assert_can_disable_lcpll(dev_priv);
9417
9418 val = I915_READ(LCPLL_CTL);
9419
9420 if (switch_to_fclk) {
9421 val |= LCPLL_CD_SOURCE_FCLK;
9422 I915_WRITE(LCPLL_CTL, val);
9423
9424 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9425 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9426 DRM_ERROR("Switching to FCLK failed\n");
9427
9428 val = I915_READ(LCPLL_CTL);
9429 }
9430
9431 val |= LCPLL_PLL_DISABLE;
9432 I915_WRITE(LCPLL_CTL, val);
9433 POSTING_READ(LCPLL_CTL);
9434
9435 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9436 DRM_ERROR("LCPLL still locked\n");
9437
9438 val = hsw_read_dcomp(dev_priv);
9439 val |= D_COMP_COMP_DISABLE;
9440 hsw_write_dcomp(dev_priv, val);
9441 ndelay(100);
9442
9443 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9444 1))
9445 DRM_ERROR("D_COMP RCOMP still in progress\n");
9446
9447 if (allow_power_down) {
9448 val = I915_READ(LCPLL_CTL);
9449 val |= LCPLL_POWER_DOWN_ALLOW;
9450 I915_WRITE(LCPLL_CTL, val);
9451 POSTING_READ(LCPLL_CTL);
9452 }
9453}
9454
9455/*
9456 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9457 * source.
9458 */
9459static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9460{
9461 uint32_t val;
9462
9463 val = I915_READ(LCPLL_CTL);
9464
9465 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9466 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9467 return;
9468
9469 /*
9470 * Make sure we're not on PC8 state before disabling PC8, otherwise
9471 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9472 */
9473 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9474
9475 if (val & LCPLL_POWER_DOWN_ALLOW) {
9476 val &= ~LCPLL_POWER_DOWN_ALLOW;
9477 I915_WRITE(LCPLL_CTL, val);
9478 POSTING_READ(LCPLL_CTL);
9479 }
9480
9481 val = hsw_read_dcomp(dev_priv);
9482 val |= D_COMP_COMP_FORCE;
9483 val &= ~D_COMP_COMP_DISABLE;
9484 hsw_write_dcomp(dev_priv, val);
9485
9486 val = I915_READ(LCPLL_CTL);
9487 val &= ~LCPLL_PLL_DISABLE;
9488 I915_WRITE(LCPLL_CTL, val);
9489
9490 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9491 DRM_ERROR("LCPLL not locked yet\n");
9492
9493 if (val & LCPLL_CD_SOURCE_FCLK) {
9494 val = I915_READ(LCPLL_CTL);
9495 val &= ~LCPLL_CD_SOURCE_FCLK;
9496 I915_WRITE(LCPLL_CTL, val);
9497
9498 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9499 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9500 DRM_ERROR("Switching back to LCPLL failed\n");
9501 }
9502
9503 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9504 intel_update_cdclk(dev_priv->dev);
9505}
9506
9507/*
9508 * Package states C8 and deeper are really deep PC states that can only be
9509 * reached when all the devices on the system allow it, so even if the graphics
9510 * device allows PC8+, it doesn't mean the system will actually get to these
9511 * states. Our driver only allows PC8+ when going into runtime PM.
9512 *
9513 * The requirements for PC8+ are that all the outputs are disabled, the power
9514 * well is disabled and most interrupts are disabled, and these are also
9515 * requirements for runtime PM. When these conditions are met, we manually do
9516 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9517 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9518 * hang the machine.
9519 *
9520 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9521 * the state of some registers, so when we come back from PC8+ we need to
9522 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9523 * need to take care of the registers kept by RC6. Notice that this happens even
9524 * if we don't put the device in PCI D3 state (which is what currently happens
9525 * because of the runtime PM support).
9526 *
9527 * For more, read "Display Sequences for Package C8" on the hardware
9528 * documentation.
9529 */
9530void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9531{
9532 struct drm_device *dev = dev_priv->dev;
9533 uint32_t val;
9534
9535 DRM_DEBUG_KMS("Enabling package C8+\n");
9536
9537 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9538 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9539 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9540 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9541 }
9542
9543 lpt_disable_clkout_dp(dev);
9544 hsw_disable_lcpll(dev_priv, true, true);
9545}
9546
9547void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9548{
9549 struct drm_device *dev = dev_priv->dev;
9550 uint32_t val;
9551
9552 DRM_DEBUG_KMS("Disabling package C8+\n");
9553
9554 hsw_restore_lcpll(dev_priv);
9555 lpt_init_pch_refclk(dev);
9556
9557 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9558 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9559 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9560 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9561 }
9562
9563 intel_prepare_ddi(dev);
9564}
9565
9566static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
9567{
9568 struct drm_device *dev = old_state->dev;
9569 struct drm_i915_private *dev_priv = dev->dev_private;
9570 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
9571 int req_cdclk;
9572
9573 /* see the comment in valleyview_modeset_global_resources */
9574 if (WARN_ON(max_pixclk < 0))
9575 return;
9576
9577 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9578
9579 if (req_cdclk != dev_priv->cdclk_freq)
9580 broxton_set_cdclk(dev, req_cdclk);
9581}
9582
9583/* compute the max rate for new configuration */
9584static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv)
9585{
9586 struct drm_device *dev = dev_priv->dev;
9587 struct intel_crtc *intel_crtc;
9588 struct drm_crtc *crtc;
9589 int max_pixel_rate = 0;
9590 int pixel_rate;
9591
9592 for_each_crtc(dev, crtc) {
9593 if (!crtc->state->enable)
9594 continue;
9595
9596 intel_crtc = to_intel_crtc(crtc);
9597 pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
9598
9599 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9600 if (IS_BROADWELL(dev) && intel_crtc->config->ips_enabled)
9601 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9602
9603 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9604 }
9605
9606 return max_pixel_rate;
9607}
9608
9609static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9610{
9611 struct drm_i915_private *dev_priv = dev->dev_private;
9612 uint32_t val, data;
9613 int ret;
9614
9615 if (WARN((I915_READ(LCPLL_CTL) &
9616 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9617 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9618 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9619 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9620 "trying to change cdclk frequency with cdclk not enabled\n"))
9621 return;
9622
9623 mutex_lock(&dev_priv->rps.hw_lock);
9624 ret = sandybridge_pcode_write(dev_priv,
9625 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9626 mutex_unlock(&dev_priv->rps.hw_lock);
9627 if (ret) {
9628 DRM_ERROR("failed to inform pcode about cdclk change\n");
9629 return;
9630 }
9631
9632 val = I915_READ(LCPLL_CTL);
9633 val |= LCPLL_CD_SOURCE_FCLK;
9634 I915_WRITE(LCPLL_CTL, val);
9635
9636 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9637 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9638 DRM_ERROR("Switching to FCLK failed\n");
9639
9640 val = I915_READ(LCPLL_CTL);
9641 val &= ~LCPLL_CLK_FREQ_MASK;
9642
9643 switch (cdclk) {
9644 case 450000:
9645 val |= LCPLL_CLK_FREQ_450;
9646 data = 0;
9647 break;
9648 case 540000:
9649 val |= LCPLL_CLK_FREQ_54O_BDW;
9650 data = 1;
9651 break;
9652 case 337500:
9653 val |= LCPLL_CLK_FREQ_337_5_BDW;
9654 data = 2;
9655 break;
9656 case 675000:
9657 val |= LCPLL_CLK_FREQ_675_BDW;
9658 data = 3;
9659 break;
9660 default:
9661 WARN(1, "invalid cdclk frequency\n");
9662 return;
9663 }
9664
9665 I915_WRITE(LCPLL_CTL, val);
9666
9667 val = I915_READ(LCPLL_CTL);
9668 val &= ~LCPLL_CD_SOURCE_FCLK;
9669 I915_WRITE(LCPLL_CTL, val);
9670
9671 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9672 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9673 DRM_ERROR("Switching back to LCPLL failed\n");
9674
9675 mutex_lock(&dev_priv->rps.hw_lock);
9676 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9677 mutex_unlock(&dev_priv->rps.hw_lock);
9678
9679 intel_update_cdclk(dev);
9680
9681 WARN(cdclk != dev_priv->cdclk_freq,
9682 "cdclk requested %d kHz but got %d kHz\n",
9683 cdclk, dev_priv->cdclk_freq);
9684}
9685
9686static int broadwell_calc_cdclk(struct drm_i915_private *dev_priv,
9687 int max_pixel_rate)
9688{
9689 int cdclk;
9690
9691 /*
9692 * FIXME should also account for plane ratio
9693 * once 64bpp pixel formats are supported.
9694 */
9695 if (max_pixel_rate > 540000)
9696 cdclk = 675000;
9697 else if (max_pixel_rate > 450000)
9698 cdclk = 540000;
9699 else if (max_pixel_rate > 337500)
9700 cdclk = 450000;
9701 else
9702 cdclk = 337500;
9703
9704 /*
9705 * FIXME move the cdclk caclulation to
9706 * compute_config() so we can fail gracegully.
9707 */
9708 if (cdclk > dev_priv->max_cdclk_freq) {
9709 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9710 cdclk, dev_priv->max_cdclk_freq);
9711 cdclk = dev_priv->max_cdclk_freq;
9712 }
9713
9714 return cdclk;
9715}
9716
9717static int broadwell_modeset_global_pipes(struct drm_atomic_state *state)
9718{
9719 struct drm_i915_private *dev_priv = to_i915(state->dev);
9720 struct drm_crtc *crtc;
9721 struct drm_crtc_state *crtc_state;
9722 int max_pixclk = ilk_max_pixel_rate(dev_priv);
9723 int cdclk, i;
9724
9725 cdclk = broadwell_calc_cdclk(dev_priv, max_pixclk);
9726
9727 if (cdclk == dev_priv->cdclk_freq)
9728 return 0;
9729
9730 /* add all active pipes to the state */
9731 for_each_crtc(state->dev, crtc) {
9732 if (!crtc->state->enable)
9733 continue;
9734
9735 crtc_state = drm_atomic_get_crtc_state(state, crtc);
9736 if (IS_ERR(crtc_state))
9737 return PTR_ERR(crtc_state);
9738 }
9739
9740 /* disable/enable all currently active pipes while we change cdclk */
9741 for_each_crtc_in_state(state, crtc, crtc_state, i)
9742 if (crtc_state->enable)
9743 crtc_state->mode_changed = true;
9744
9745 return 0;
9746}
9747
9748static void broadwell_modeset_global_resources(struct drm_atomic_state *state)
9749{
9750 struct drm_device *dev = state->dev;
9751 struct drm_i915_private *dev_priv = dev->dev_private;
9752 int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
9753 int req_cdclk = broadwell_calc_cdclk(dev_priv, max_pixel_rate);
9754
9755 if (req_cdclk != dev_priv->cdclk_freq)
9756 broadwell_set_cdclk(dev, req_cdclk);
9757}
9758
9759static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9760 struct intel_crtc_state *crtc_state)
9761{
9762 if (!intel_ddi_pll_select(crtc, crtc_state))
9763 return -EINVAL;
9764
9765 crtc->lowfreq_avail = false;
9766
9767 return 0;
9768}
9769
9770static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9771 enum port port,
9772 struct intel_crtc_state *pipe_config)
9773{
9774 switch (port) {
9775 case PORT_A:
9776 pipe_config->ddi_pll_sel = SKL_DPLL0;
9777 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9778 break;
9779 case PORT_B:
9780 pipe_config->ddi_pll_sel = SKL_DPLL1;
9781 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9782 break;
9783 case PORT_C:
9784 pipe_config->ddi_pll_sel = SKL_DPLL2;
9785 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9786 break;
9787 default:
9788 DRM_ERROR("Incorrect port type\n");
9789 }
9790}
9791
9792static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9793 enum port port,
9794 struct intel_crtc_state *pipe_config)
9795{
9796 u32 temp, dpll_ctl1;
9797
9798 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9799 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9800
9801 switch (pipe_config->ddi_pll_sel) {
9802 case SKL_DPLL0:
9803 /*
9804 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9805 * of the shared DPLL framework and thus needs to be read out
9806 * separately
9807 */
9808 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9809 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9810 break;
9811 case SKL_DPLL1:
9812 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9813 break;
9814 case SKL_DPLL2:
9815 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9816 break;
9817 case SKL_DPLL3:
9818 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9819 break;
9820 }
9821}
9822
9823static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9824 enum port port,
9825 struct intel_crtc_state *pipe_config)
9826{
9827 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9828
9829 switch (pipe_config->ddi_pll_sel) {
9830 case PORT_CLK_SEL_WRPLL1:
9831 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9832 break;
9833 case PORT_CLK_SEL_WRPLL2:
9834 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9835 break;
9836 }
9837}
9838
9839static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9840 struct intel_crtc_state *pipe_config)
9841{
9842 struct drm_device *dev = crtc->base.dev;
9843 struct drm_i915_private *dev_priv = dev->dev_private;
9844 struct intel_shared_dpll *pll;
9845 enum port port;
9846 uint32_t tmp;
9847
9848 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9849
9850 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9851
9852 if (IS_SKYLAKE(dev))
9853 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9854 else if (IS_BROXTON(dev))
9855 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9856 else
9857 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9858
9859 if (pipe_config->shared_dpll >= 0) {
9860 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9861
9862 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9863 &pipe_config->dpll_hw_state));
9864 }
9865
9866 /*
9867 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9868 * DDI E. So just check whether this pipe is wired to DDI E and whether
9869 * the PCH transcoder is on.
9870 */
9871 if (INTEL_INFO(dev)->gen < 9 &&
9872 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9873 pipe_config->has_pch_encoder = true;
9874
9875 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9876 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9877 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9878
9879 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9880 }
9881}
9882
9883static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9884 struct intel_crtc_state *pipe_config)
9885{
9886 struct drm_device *dev = crtc->base.dev;
9887 struct drm_i915_private *dev_priv = dev->dev_private;
9888 enum intel_display_power_domain pfit_domain;
9889 uint32_t tmp;
9890
9891 if (!intel_display_power_is_enabled(dev_priv,
9892 POWER_DOMAIN_PIPE(crtc->pipe)))
9893 return false;
9894
9895 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9896 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9897
9898 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9899 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9900 enum pipe trans_edp_pipe;
9901 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9902 default:
9903 WARN(1, "unknown pipe linked to edp transcoder\n");
9904 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9905 case TRANS_DDI_EDP_INPUT_A_ON:
9906 trans_edp_pipe = PIPE_A;
9907 break;
9908 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9909 trans_edp_pipe = PIPE_B;
9910 break;
9911 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9912 trans_edp_pipe = PIPE_C;
9913 break;
9914 }
9915
9916 if (trans_edp_pipe == crtc->pipe)
9917 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9918 }
9919
9920 if (!intel_display_power_is_enabled(dev_priv,
9921 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9922 return false;
9923
9924 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9925 if (!(tmp & PIPECONF_ENABLE))
9926 return false;
9927
9928 haswell_get_ddi_port_state(crtc, pipe_config);
9929
9930 intel_get_pipe_timings(crtc, pipe_config);
9931
9932 if (INTEL_INFO(dev)->gen >= 9) {
9933 skl_init_scalers(dev, crtc, pipe_config);
9934 }
9935
9936 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9937
9938 if (INTEL_INFO(dev)->gen >= 9) {
9939 pipe_config->scaler_state.scaler_id = -1;
9940 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9941 }
9942
9943 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9944 if (INTEL_INFO(dev)->gen == 9)
9945 skylake_get_pfit_config(crtc, pipe_config);
9946 else if (INTEL_INFO(dev)->gen < 9)
9947 ironlake_get_pfit_config(crtc, pipe_config);
9948 else
9949 MISSING_CASE(INTEL_INFO(dev)->gen);
9950 }
9951
9952 if (IS_HASWELL(dev))
9953 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9954 (I915_READ(IPS_CTL) & IPS_ENABLE);
9955
9956 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9957 pipe_config->pixel_multiplier =
9958 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9959 } else {
9960 pipe_config->pixel_multiplier = 1;
9961 }
9962
9963 return true;
9964}
9965
9966static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9967{
9968 struct drm_device *dev = crtc->dev;
9969 struct drm_i915_private *dev_priv = dev->dev_private;
9970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9971 uint32_t cntl = 0, size = 0;
9972
9973 if (base) {
9974 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9975 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9976 unsigned int stride = roundup_pow_of_two(width) * 4;
9977
9978 switch (stride) {
9979 default:
9980 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9981 width, stride);
9982 stride = 256;
9983 /* fallthrough */
9984 case 256:
9985 case 512:
9986 case 1024:
9987 case 2048:
9988 break;
9989 }
9990
9991 cntl |= CURSOR_ENABLE |
9992 CURSOR_GAMMA_ENABLE |
9993 CURSOR_FORMAT_ARGB |
9994 CURSOR_STRIDE(stride);
9995
9996 size = (height << 12) | width;
9997 }
9998
9999 if (intel_crtc->cursor_cntl != 0 &&
10000 (intel_crtc->cursor_base != base ||
10001 intel_crtc->cursor_size != size ||
10002 intel_crtc->cursor_cntl != cntl)) {
10003 /* On these chipsets we can only modify the base/size/stride
10004 * whilst the cursor is disabled.
10005 */
10006 I915_WRITE(_CURACNTR, 0);
10007 POSTING_READ(_CURACNTR);
10008 intel_crtc->cursor_cntl = 0;
10009 }
10010
10011 if (intel_crtc->cursor_base != base) {
10012 I915_WRITE(_CURABASE, base);
10013 intel_crtc->cursor_base = base;
10014 }
10015
10016 if (intel_crtc->cursor_size != size) {
10017 I915_WRITE(CURSIZE, size);
10018 intel_crtc->cursor_size = size;
10019 }
10020
10021 if (intel_crtc->cursor_cntl != cntl) {
10022 I915_WRITE(_CURACNTR, cntl);
10023 POSTING_READ(_CURACNTR);
10024 intel_crtc->cursor_cntl = cntl;
10025 }
10026}
10027
10028static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
10029{
10030 struct drm_device *dev = crtc->dev;
10031 struct drm_i915_private *dev_priv = dev->dev_private;
10032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10033 int pipe = intel_crtc->pipe;
10034 uint32_t cntl;
10035
10036 cntl = 0;
10037 if (base) {
10038 cntl = MCURSOR_GAMMA_ENABLE;
10039 switch (intel_crtc->base.cursor->state->crtc_w) {
10040 case 64:
10041 cntl |= CURSOR_MODE_64_ARGB_AX;
10042 break;
10043 case 128:
10044 cntl |= CURSOR_MODE_128_ARGB_AX;
10045 break;
10046 case 256:
10047 cntl |= CURSOR_MODE_256_ARGB_AX;
10048 break;
10049 default:
10050 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
10051 return;
10052 }
10053 cntl |= pipe << 28; /* Connect to correct pipe */
10054
10055 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
10056 cntl |= CURSOR_PIPE_CSC_ENABLE;
10057 }
10058
10059 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
10060 cntl |= CURSOR_ROTATE_180;
10061
10062 if (intel_crtc->cursor_cntl != cntl) {
10063 I915_WRITE(CURCNTR(pipe), cntl);
10064 POSTING_READ(CURCNTR(pipe));
10065 intel_crtc->cursor_cntl = cntl;
10066 }
10067
10068 /* and commit changes on next vblank */
10069 I915_WRITE(CURBASE(pipe), base);
10070 POSTING_READ(CURBASE(pipe));
10071
10072 intel_crtc->cursor_base = base;
10073}
10074
10075/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10076static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10077 bool on)
10078{
10079 struct drm_device *dev = crtc->dev;
10080 struct drm_i915_private *dev_priv = dev->dev_private;
10081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10082 int pipe = intel_crtc->pipe;
10083 int x = crtc->cursor_x;
10084 int y = crtc->cursor_y;
10085 u32 base = 0, pos = 0;
10086
10087 if (on)
10088 base = intel_crtc->cursor_addr;
10089
10090 if (x >= intel_crtc->config->pipe_src_w)
10091 base = 0;
10092
10093 if (y >= intel_crtc->config->pipe_src_h)
10094 base = 0;
10095
10096 if (x < 0) {
10097 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
10098 base = 0;
10099
10100 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10101 x = -x;
10102 }
10103 pos |= x << CURSOR_X_SHIFT;
10104
10105 if (y < 0) {
10106 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
10107 base = 0;
10108
10109 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10110 y = -y;
10111 }
10112 pos |= y << CURSOR_Y_SHIFT;
10113
10114 if (base == 0 && intel_crtc->cursor_base == 0)
10115 return;
10116
10117 I915_WRITE(CURPOS(pipe), pos);
10118
10119 /* ILK+ do this automagically */
10120 if (HAS_GMCH_DISPLAY(dev) &&
10121 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10122 base += (intel_crtc->base.cursor->state->crtc_h *
10123 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
10124 }
10125
10126 if (IS_845G(dev) || IS_I865G(dev))
10127 i845_update_cursor(crtc, base);
10128 else
10129 i9xx_update_cursor(crtc, base);
10130}
10131
10132static bool cursor_size_ok(struct drm_device *dev,
10133 uint32_t width, uint32_t height)
10134{
10135 if (width == 0 || height == 0)
10136 return false;
10137
10138 /*
10139 * 845g/865g are special in that they are only limited by
10140 * the width of their cursors, the height is arbitrary up to
10141 * the precision of the register. Everything else requires
10142 * square cursors, limited to a few power-of-two sizes.
10143 */
10144 if (IS_845G(dev) || IS_I865G(dev)) {
10145 if ((width & 63) != 0)
10146 return false;
10147
10148 if (width > (IS_845G(dev) ? 64 : 512))
10149 return false;
10150
10151 if (height > 1023)
10152 return false;
10153 } else {
10154 switch (width | height) {
10155 case 256:
10156 case 128:
10157 if (IS_GEN2(dev))
10158 return false;
10159 case 64:
10160 break;
10161 default:
10162 return false;
10163 }
10164 }
10165
10166 return true;
10167}
10168
10169static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10170 u16 *blue, uint32_t start, uint32_t size)
10171{
10172 int end = (start + size > 256) ? 256 : start + size, i;
10173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10174
10175 for (i = start; i < end; i++) {
10176 intel_crtc->lut_r[i] = red[i] >> 8;
10177 intel_crtc->lut_g[i] = green[i] >> 8;
10178 intel_crtc->lut_b[i] = blue[i] >> 8;
10179 }
10180
10181 intel_crtc_load_lut(crtc);
10182}
10183
10184/* VESA 640x480x72Hz mode to set on the pipe */
10185static struct drm_display_mode load_detect_mode = {
10186 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10187 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10188};
10189
10190struct drm_framebuffer *
10191__intel_framebuffer_create(struct drm_device *dev,
10192 struct drm_mode_fb_cmd2 *mode_cmd,
10193 struct drm_i915_gem_object *obj)
10194{
10195 struct intel_framebuffer *intel_fb;
10196 int ret;
10197
10198 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10199 if (!intel_fb) {
10200 drm_gem_object_unreference(&obj->base);
10201 return ERR_PTR(-ENOMEM);
10202 }
10203
10204 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10205 if (ret)
10206 goto err;
10207
10208 return &intel_fb->base;
10209err:
10210 drm_gem_object_unreference(&obj->base);
10211 kfree(intel_fb);
10212
10213 return ERR_PTR(ret);
10214}
10215
10216static struct drm_framebuffer *
10217intel_framebuffer_create(struct drm_device *dev,
10218 struct drm_mode_fb_cmd2 *mode_cmd,
10219 struct drm_i915_gem_object *obj)
10220{
10221 struct drm_framebuffer *fb;
10222 int ret;
10223
10224 ret = i915_mutex_lock_interruptible(dev);
10225 if (ret)
10226 return ERR_PTR(ret);
10227 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10228 mutex_unlock(&dev->struct_mutex);
10229
10230 return fb;
10231}
10232
10233static u32
10234intel_framebuffer_pitch_for_width(int width, int bpp)
10235{
10236 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10237 return ALIGN(pitch, 64);
10238}
10239
10240static u32
10241intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10242{
10243 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10244 return PAGE_ALIGN(pitch * mode->vdisplay);
10245}
10246
10247static struct drm_framebuffer *
10248intel_framebuffer_create_for_mode(struct drm_device *dev,
10249 struct drm_display_mode *mode,
10250 int depth, int bpp)
10251{
10252 struct drm_i915_gem_object *obj;
10253 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10254
10255 obj = i915_gem_alloc_object(dev,
10256 intel_framebuffer_size_for_mode(mode, bpp));
10257 if (obj == NULL)
10258 return ERR_PTR(-ENOMEM);
10259
10260 mode_cmd.width = mode->hdisplay;
10261 mode_cmd.height = mode->vdisplay;
10262 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10263 bpp);
10264 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10265
10266 return intel_framebuffer_create(dev, &mode_cmd, obj);
10267}
10268
10269static struct drm_framebuffer *
10270mode_fits_in_fbdev(struct drm_device *dev,
10271 struct drm_display_mode *mode)
10272{
10273#ifdef CONFIG_DRM_I915_FBDEV
10274 struct drm_i915_private *dev_priv = dev->dev_private;
10275 struct drm_i915_gem_object *obj;
10276 struct drm_framebuffer *fb;
10277
10278 if (!dev_priv->fbdev)
10279 return NULL;
10280
10281 if (!dev_priv->fbdev->fb)
10282 return NULL;
10283
10284 obj = dev_priv->fbdev->fb->obj;
10285 BUG_ON(!obj);
10286
10287 fb = &dev_priv->fbdev->fb->base;
10288 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10289 fb->bits_per_pixel))
10290 return NULL;
10291
10292 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10293 return NULL;
10294
10295 return fb;
10296#else
10297 return NULL;
10298#endif
10299}
10300
10301static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10302 struct drm_crtc *crtc,
10303 struct drm_display_mode *mode,
10304 struct drm_framebuffer *fb,
10305 int x, int y)
10306{
10307 struct drm_plane_state *plane_state;
10308 int hdisplay, vdisplay;
10309 int ret;
10310
10311 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10312 if (IS_ERR(plane_state))
10313 return PTR_ERR(plane_state);
10314
10315 if (mode)
10316 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10317 else
10318 hdisplay = vdisplay = 0;
10319
10320 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10321 if (ret)
10322 return ret;
10323 drm_atomic_set_fb_for_plane(plane_state, fb);
10324 plane_state->crtc_x = 0;
10325 plane_state->crtc_y = 0;
10326 plane_state->crtc_w = hdisplay;
10327 plane_state->crtc_h = vdisplay;
10328 plane_state->src_x = x << 16;
10329 plane_state->src_y = y << 16;
10330 plane_state->src_w = hdisplay << 16;
10331 plane_state->src_h = vdisplay << 16;
10332
10333 return 0;
10334}
10335
10336bool intel_get_load_detect_pipe(struct drm_connector *connector,
10337 struct drm_display_mode *mode,
10338 struct intel_load_detect_pipe *old,
10339 struct drm_modeset_acquire_ctx *ctx)
10340{
10341 struct intel_crtc *intel_crtc;
10342 struct intel_encoder *intel_encoder =
10343 intel_attached_encoder(connector);
10344 struct drm_crtc *possible_crtc;
10345 struct drm_encoder *encoder = &intel_encoder->base;
10346 struct drm_crtc *crtc = NULL;
10347 struct drm_device *dev = encoder->dev;
10348 struct drm_framebuffer *fb;
10349 struct drm_mode_config *config = &dev->mode_config;
10350 struct drm_atomic_state *state = NULL;
10351 struct drm_connector_state *connector_state;
10352 struct intel_crtc_state *crtc_state;
10353 int ret, i = -1;
10354
10355 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10356 connector->base.id, connector->name,
10357 encoder->base.id, encoder->name);
10358
10359retry:
10360 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10361 if (ret)
10362 goto fail_unlock;
10363
10364 /*
10365 * Algorithm gets a little messy:
10366 *
10367 * - if the connector already has an assigned crtc, use it (but make
10368 * sure it's on first)
10369 *
10370 * - try to find the first unused crtc that can drive this connector,
10371 * and use that if we find one
10372 */
10373
10374 /* See if we already have a CRTC for this connector */
10375 if (encoder->crtc) {
10376 crtc = encoder->crtc;
10377
10378 ret = drm_modeset_lock(&crtc->mutex, ctx);
10379 if (ret)
10380 goto fail_unlock;
10381 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10382 if (ret)
10383 goto fail_unlock;
10384
10385 old->dpms_mode = connector->dpms;
10386 old->load_detect_temp = false;
10387
10388 /* Make sure the crtc and connector are running */
10389 if (connector->dpms != DRM_MODE_DPMS_ON)
10390 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10391
10392 return true;
10393 }
10394
10395 /* Find an unused one (if possible) */
10396 for_each_crtc(dev, possible_crtc) {
10397 i++;
10398 if (!(encoder->possible_crtcs & (1 << i)))
10399 continue;
10400 if (possible_crtc->state->enable)
10401 continue;
10402 /* This can occur when applying the pipe A quirk on resume. */
10403 if (to_intel_crtc(possible_crtc)->new_enabled)
10404 continue;
10405
10406 crtc = possible_crtc;
10407 break;
10408 }
10409
10410 /*
10411 * If we didn't find an unused CRTC, don't use any.
10412 */
10413 if (!crtc) {
10414 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10415 goto fail_unlock;
10416 }
10417
10418 ret = drm_modeset_lock(&crtc->mutex, ctx);
10419 if (ret)
10420 goto fail_unlock;
10421 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10422 if (ret)
10423 goto fail_unlock;
10424 intel_encoder->new_crtc = to_intel_crtc(crtc);
10425 to_intel_connector(connector)->new_encoder = intel_encoder;
10426
10427 intel_crtc = to_intel_crtc(crtc);
10428 intel_crtc->new_enabled = true;
10429 old->dpms_mode = connector->dpms;
10430 old->load_detect_temp = true;
10431 old->release_fb = NULL;
10432
10433 state = drm_atomic_state_alloc(dev);
10434 if (!state)
10435 return false;
10436
10437 state->acquire_ctx = ctx;
10438
10439 connector_state = drm_atomic_get_connector_state(state, connector);
10440 if (IS_ERR(connector_state)) {
10441 ret = PTR_ERR(connector_state);
10442 goto fail;
10443 }
10444
10445 connector_state->crtc = crtc;
10446 connector_state->best_encoder = &intel_encoder->base;
10447
10448 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10449 if (IS_ERR(crtc_state)) {
10450 ret = PTR_ERR(crtc_state);
10451 goto fail;
10452 }
10453
10454 crtc_state->base.active = crtc_state->base.enable = true;
10455
10456 if (!mode)
10457 mode = &load_detect_mode;
10458
10459 /* We need a framebuffer large enough to accommodate all accesses
10460 * that the plane may generate whilst we perform load detection.
10461 * We can not rely on the fbcon either being present (we get called
10462 * during its initialisation to detect all boot displays, or it may
10463 * not even exist) or that it is large enough to satisfy the
10464 * requested mode.
10465 */
10466 fb = mode_fits_in_fbdev(dev, mode);
10467 if (fb == NULL) {
10468 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10469 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10470 old->release_fb = fb;
10471 } else
10472 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10473 if (IS_ERR(fb)) {
10474 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10475 goto fail;
10476 }
10477
10478 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10479 if (ret)
10480 goto fail;
10481
10482 drm_mode_copy(&crtc_state->base.mode, mode);
10483
10484 if (intel_set_mode(state)) {
10485 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10486 if (old->release_fb)
10487 old->release_fb->funcs->destroy(old->release_fb);
10488 goto fail;
10489 }
10490 crtc->primary->crtc = crtc;
10491
10492 /* let the connector get through one full cycle before testing */
10493 intel_wait_for_vblank(dev, intel_crtc->pipe);
10494 return true;
10495
10496 fail:
10497 intel_crtc->new_enabled = crtc->state->enable;
10498fail_unlock:
10499 drm_atomic_state_free(state);
10500 state = NULL;
10501
10502 if (ret == -EDEADLK) {
10503 drm_modeset_backoff(ctx);
10504 goto retry;
10505 }
10506
10507 return false;
10508}
10509
10510void intel_release_load_detect_pipe(struct drm_connector *connector,
10511 struct intel_load_detect_pipe *old,
10512 struct drm_modeset_acquire_ctx *ctx)
10513{
10514 struct drm_device *dev = connector->dev;
10515 struct intel_encoder *intel_encoder =
10516 intel_attached_encoder(connector);
10517 struct drm_encoder *encoder = &intel_encoder->base;
10518 struct drm_crtc *crtc = encoder->crtc;
10519 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10520 struct drm_atomic_state *state;
10521 struct drm_connector_state *connector_state;
10522 struct intel_crtc_state *crtc_state;
10523 int ret;
10524
10525 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10526 connector->base.id, connector->name,
10527 encoder->base.id, encoder->name);
10528
10529 if (old->load_detect_temp) {
10530 state = drm_atomic_state_alloc(dev);
10531 if (!state)
10532 goto fail;
10533
10534 state->acquire_ctx = ctx;
10535
10536 connector_state = drm_atomic_get_connector_state(state, connector);
10537 if (IS_ERR(connector_state))
10538 goto fail;
10539
10540 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10541 if (IS_ERR(crtc_state))
10542 goto fail;
10543
10544 to_intel_connector(connector)->new_encoder = NULL;
10545 intel_encoder->new_crtc = NULL;
10546 intel_crtc->new_enabled = false;
10547
10548 connector_state->best_encoder = NULL;
10549 connector_state->crtc = NULL;
10550
10551 crtc_state->base.enable = crtc_state->base.active = false;
10552
10553 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10554 0, 0);
10555 if (ret)
10556 goto fail;
10557
10558 ret = intel_set_mode(state);
10559 if (ret)
10560 goto fail;
10561
10562 if (old->release_fb) {
10563 drm_framebuffer_unregister_private(old->release_fb);
10564 drm_framebuffer_unreference(old->release_fb);
10565 }
10566
10567 return;
10568 }
10569
10570 /* Switch crtc and encoder back off if necessary */
10571 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10572 connector->funcs->dpms(connector, old->dpms_mode);
10573
10574 return;
10575fail:
10576 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10577 drm_atomic_state_free(state);
10578}
10579
10580static int i9xx_pll_refclk(struct drm_device *dev,
10581 const struct intel_crtc_state *pipe_config)
10582{
10583 struct drm_i915_private *dev_priv = dev->dev_private;
10584 u32 dpll = pipe_config->dpll_hw_state.dpll;
10585
10586 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10587 return dev_priv->vbt.lvds_ssc_freq;
10588 else if (HAS_PCH_SPLIT(dev))
10589 return 120000;
10590 else if (!IS_GEN2(dev))
10591 return 96000;
10592 else
10593 return 48000;
10594}
10595
10596/* Returns the clock of the currently programmed mode of the given pipe. */
10597static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10598 struct intel_crtc_state *pipe_config)
10599{
10600 struct drm_device *dev = crtc->base.dev;
10601 struct drm_i915_private *dev_priv = dev->dev_private;
10602 int pipe = pipe_config->cpu_transcoder;
10603 u32 dpll = pipe_config->dpll_hw_state.dpll;
10604 u32 fp;
10605 intel_clock_t clock;
10606 int refclk = i9xx_pll_refclk(dev, pipe_config);
10607
10608 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10609 fp = pipe_config->dpll_hw_state.fp0;
10610 else
10611 fp = pipe_config->dpll_hw_state.fp1;
10612
10613 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10614 if (IS_PINEVIEW(dev)) {
10615 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10616 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10617 } else {
10618 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10619 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10620 }
10621
10622 if (!IS_GEN2(dev)) {
10623 if (IS_PINEVIEW(dev))
10624 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10625 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10626 else
10627 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10628 DPLL_FPA01_P1_POST_DIV_SHIFT);
10629
10630 switch (dpll & DPLL_MODE_MASK) {
10631 case DPLLB_MODE_DAC_SERIAL:
10632 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10633 5 : 10;
10634 break;
10635 case DPLLB_MODE_LVDS:
10636 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10637 7 : 14;
10638 break;
10639 default:
10640 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10641 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10642 return;
10643 }
10644
10645 if (IS_PINEVIEW(dev))
10646 pineview_clock(refclk, &clock);
10647 else
10648 i9xx_clock(refclk, &clock);
10649 } else {
10650 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10651 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10652
10653 if (is_lvds) {
10654 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10655 DPLL_FPA01_P1_POST_DIV_SHIFT);
10656
10657 if (lvds & LVDS_CLKB_POWER_UP)
10658 clock.p2 = 7;
10659 else
10660 clock.p2 = 14;
10661 } else {
10662 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10663 clock.p1 = 2;
10664 else {
10665 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10666 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10667 }
10668 if (dpll & PLL_P2_DIVIDE_BY_4)
10669 clock.p2 = 4;
10670 else
10671 clock.p2 = 2;
10672 }
10673
10674 i9xx_clock(refclk, &clock);
10675 }
10676
10677 /*
10678 * This value includes pixel_multiplier. We will use
10679 * port_clock to compute adjusted_mode.crtc_clock in the
10680 * encoder's get_config() function.
10681 */
10682 pipe_config->port_clock = clock.dot;
10683}
10684
10685int intel_dotclock_calculate(int link_freq,
10686 const struct intel_link_m_n *m_n)
10687{
10688 /*
10689 * The calculation for the data clock is:
10690 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10691 * But we want to avoid losing precison if possible, so:
10692 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10693 *
10694 * and the link clock is simpler:
10695 * link_clock = (m * link_clock) / n
10696 */
10697
10698 if (!m_n->link_n)
10699 return 0;
10700
10701 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10702}
10703
10704static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10705 struct intel_crtc_state *pipe_config)
10706{
10707 struct drm_device *dev = crtc->base.dev;
10708
10709 /* read out port_clock from the DPLL */
10710 i9xx_crtc_clock_get(crtc, pipe_config);
10711
10712 /*
10713 * This value does not include pixel_multiplier.
10714 * We will check that port_clock and adjusted_mode.crtc_clock
10715 * agree once we know their relationship in the encoder's
10716 * get_config() function.
10717 */
10718 pipe_config->base.adjusted_mode.crtc_clock =
10719 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10720 &pipe_config->fdi_m_n);
10721}
10722
10723/** Returns the currently programmed mode of the given pipe. */
10724struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10725 struct drm_crtc *crtc)
10726{
10727 struct drm_i915_private *dev_priv = dev->dev_private;
10728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10729 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10730 struct drm_display_mode *mode;
10731 struct intel_crtc_state pipe_config;
10732 int htot = I915_READ(HTOTAL(cpu_transcoder));
10733 int hsync = I915_READ(HSYNC(cpu_transcoder));
10734 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10735 int vsync = I915_READ(VSYNC(cpu_transcoder));
10736 enum pipe pipe = intel_crtc->pipe;
10737
10738 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10739 if (!mode)
10740 return NULL;
10741
10742 /*
10743 * Construct a pipe_config sufficient for getting the clock info
10744 * back out of crtc_clock_get.
10745 *
10746 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10747 * to use a real value here instead.
10748 */
10749 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10750 pipe_config.pixel_multiplier = 1;
10751 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10752 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10753 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10754 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10755
10756 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10757 mode->hdisplay = (htot & 0xffff) + 1;
10758 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10759 mode->hsync_start = (hsync & 0xffff) + 1;
10760 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10761 mode->vdisplay = (vtot & 0xffff) + 1;
10762 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10763 mode->vsync_start = (vsync & 0xffff) + 1;
10764 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10765
10766 drm_mode_set_name(mode);
10767
10768 return mode;
10769}
10770
10771static void intel_decrease_pllclock(struct drm_crtc *crtc)
10772{
10773 struct drm_device *dev = crtc->dev;
10774 struct drm_i915_private *dev_priv = dev->dev_private;
10775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10776
10777 if (!HAS_GMCH_DISPLAY(dev))
10778 return;
10779
10780 if (!dev_priv->lvds_downclock_avail)
10781 return;
10782
10783 /*
10784 * Since this is called by a timer, we should never get here in
10785 * the manual case.
10786 */
10787 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
10788 int pipe = intel_crtc->pipe;
10789 int dpll_reg = DPLL(pipe);
10790 int dpll;
10791
10792 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10793
10794 assert_panel_unlocked(dev_priv, pipe);
10795
10796 dpll = I915_READ(dpll_reg);
10797 dpll |= DISPLAY_RATE_SELECT_FPA1;
10798 I915_WRITE(dpll_reg, dpll);
10799 intel_wait_for_vblank(dev, pipe);
10800 dpll = I915_READ(dpll_reg);
10801 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
10802 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10803 }
10804
10805}
10806
10807void intel_mark_busy(struct drm_device *dev)
10808{
10809 struct drm_i915_private *dev_priv = dev->dev_private;
10810
10811 if (dev_priv->mm.busy)
10812 return;
10813
10814 intel_runtime_pm_get(dev_priv);
10815 i915_update_gfx_val(dev_priv);
10816 if (INTEL_INFO(dev)->gen >= 6)
10817 gen6_rps_busy(dev_priv);
10818 dev_priv->mm.busy = true;
10819}
10820
10821void intel_mark_idle(struct drm_device *dev)
10822{
10823 struct drm_i915_private *dev_priv = dev->dev_private;
10824 struct drm_crtc *crtc;
10825
10826 if (!dev_priv->mm.busy)
10827 return;
10828
10829 dev_priv->mm.busy = false;
10830
10831 for_each_crtc(dev, crtc) {
10832 if (!crtc->primary->fb)
10833 continue;
10834
10835 intel_decrease_pllclock(crtc);
10836 }
10837
10838 if (INTEL_INFO(dev)->gen >= 6)
10839 gen6_rps_idle(dev->dev_private);
10840
10841 intel_runtime_pm_put(dev_priv);
10842}
10843
10844static void intel_crtc_destroy(struct drm_crtc *crtc)
10845{
10846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10847 struct drm_device *dev = crtc->dev;
10848 struct intel_unpin_work *work;
10849
10850 spin_lock_irq(&dev->event_lock);
10851 work = intel_crtc->unpin_work;
10852 intel_crtc->unpin_work = NULL;
10853 spin_unlock_irq(&dev->event_lock);
10854
10855 if (work) {
10856 cancel_work_sync(&work->work);
10857 kfree(work);
10858 }
10859
10860 drm_crtc_cleanup(crtc);
10861
10862 kfree(intel_crtc);
10863}
10864
10865static void intel_unpin_work_fn(struct work_struct *__work)
10866{
10867 struct intel_unpin_work *work =
10868 container_of(__work, struct intel_unpin_work, work);
10869 struct drm_device *dev = work->crtc->dev;
10870 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10871
10872 mutex_lock(&dev->struct_mutex);
10873 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
10874 drm_gem_object_unreference(&work->pending_flip_obj->base);
10875
10876 intel_fbc_update(dev);
10877
10878 if (work->flip_queued_req)
10879 i915_gem_request_assign(&work->flip_queued_req, NULL);
10880 mutex_unlock(&dev->struct_mutex);
10881
10882 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10883 drm_framebuffer_unreference(work->old_fb);
10884
10885 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10886 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10887
10888 kfree(work);
10889}
10890
10891static void do_intel_finish_page_flip(struct drm_device *dev,
10892 struct drm_crtc *crtc)
10893{
10894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10895 struct intel_unpin_work *work;
10896 unsigned long flags;
10897
10898 /* Ignore early vblank irqs */
10899 if (intel_crtc == NULL)
10900 return;
10901
10902 /*
10903 * This is called both by irq handlers and the reset code (to complete
10904 * lost pageflips) so needs the full irqsave spinlocks.
10905 */
10906 spin_lock_irqsave(&dev->event_lock, flags);
10907 work = intel_crtc->unpin_work;
10908
10909 /* Ensure we don't miss a work->pending update ... */
10910 smp_rmb();
10911
10912 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10913 spin_unlock_irqrestore(&dev->event_lock, flags);
10914 return;
10915 }
10916
10917 page_flip_completed(intel_crtc);
10918
10919 spin_unlock_irqrestore(&dev->event_lock, flags);
10920}
10921
10922void intel_finish_page_flip(struct drm_device *dev, int pipe)
10923{
10924 struct drm_i915_private *dev_priv = dev->dev_private;
10925 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10926
10927 do_intel_finish_page_flip(dev, crtc);
10928}
10929
10930void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10931{
10932 struct drm_i915_private *dev_priv = dev->dev_private;
10933 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10934
10935 do_intel_finish_page_flip(dev, crtc);
10936}
10937
10938/* Is 'a' after or equal to 'b'? */
10939static bool g4x_flip_count_after_eq(u32 a, u32 b)
10940{
10941 return !((a - b) & 0x80000000);
10942}
10943
10944static bool page_flip_finished(struct intel_crtc *crtc)
10945{
10946 struct drm_device *dev = crtc->base.dev;
10947 struct drm_i915_private *dev_priv = dev->dev_private;
10948
10949 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10950 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10951 return true;
10952
10953 /*
10954 * The relevant registers doen't exist on pre-ctg.
10955 * As the flip done interrupt doesn't trigger for mmio
10956 * flips on gmch platforms, a flip count check isn't
10957 * really needed there. But since ctg has the registers,
10958 * include it in the check anyway.
10959 */
10960 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10961 return true;
10962
10963 /*
10964 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10965 * used the same base address. In that case the mmio flip might
10966 * have completed, but the CS hasn't even executed the flip yet.
10967 *
10968 * A flip count check isn't enough as the CS might have updated
10969 * the base address just after start of vblank, but before we
10970 * managed to process the interrupt. This means we'd complete the
10971 * CS flip too soon.
10972 *
10973 * Combining both checks should get us a good enough result. It may
10974 * still happen that the CS flip has been executed, but has not
10975 * yet actually completed. But in case the base address is the same
10976 * anyway, we don't really care.
10977 */
10978 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10979 crtc->unpin_work->gtt_offset &&
10980 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10981 crtc->unpin_work->flip_count);
10982}
10983
10984void intel_prepare_page_flip(struct drm_device *dev, int plane)
10985{
10986 struct drm_i915_private *dev_priv = dev->dev_private;
10987 struct intel_crtc *intel_crtc =
10988 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10989 unsigned long flags;
10990
10991
10992 /*
10993 * This is called both by irq handlers and the reset code (to complete
10994 * lost pageflips) so needs the full irqsave spinlocks.
10995 *
10996 * NB: An MMIO update of the plane base pointer will also
10997 * generate a page-flip completion irq, i.e. every modeset
10998 * is also accompanied by a spurious intel_prepare_page_flip().
10999 */
11000 spin_lock_irqsave(&dev->event_lock, flags);
11001 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
11002 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
11003 spin_unlock_irqrestore(&dev->event_lock, flags);
11004}
11005
11006static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
11007{
11008 /* Ensure that the work item is consistent when activating it ... */
11009 smp_wmb();
11010 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
11011 /* and that it is marked active as soon as the irq could fire. */
11012 smp_wmb();
11013}
11014
11015static int intel_gen2_queue_flip(struct drm_device *dev,
11016 struct drm_crtc *crtc,
11017 struct drm_framebuffer *fb,
11018 struct drm_i915_gem_object *obj,
11019 struct intel_engine_cs *ring,
11020 uint32_t flags)
11021{
11022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11023 u32 flip_mask;
11024 int ret;
11025
11026 ret = intel_ring_begin(ring, 6);
11027 if (ret)
11028 return ret;
11029
11030 /* Can't queue multiple flips, so wait for the previous
11031 * one to finish before executing the next.
11032 */
11033 if (intel_crtc->plane)
11034 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11035 else
11036 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11037 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11038 intel_ring_emit(ring, MI_NOOP);
11039 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11040 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11041 intel_ring_emit(ring, fb->pitches[0]);
11042 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11043 intel_ring_emit(ring, 0); /* aux display base address, unused */
11044
11045 intel_mark_page_flip_active(intel_crtc);
11046 __intel_ring_advance(ring);
11047 return 0;
11048}
11049
11050static int intel_gen3_queue_flip(struct drm_device *dev,
11051 struct drm_crtc *crtc,
11052 struct drm_framebuffer *fb,
11053 struct drm_i915_gem_object *obj,
11054 struct intel_engine_cs *ring,
11055 uint32_t flags)
11056{
11057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11058 u32 flip_mask;
11059 int ret;
11060
11061 ret = intel_ring_begin(ring, 6);
11062 if (ret)
11063 return ret;
11064
11065 if (intel_crtc->plane)
11066 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11067 else
11068 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11069 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11070 intel_ring_emit(ring, MI_NOOP);
11071 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11072 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11073 intel_ring_emit(ring, fb->pitches[0]);
11074 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11075 intel_ring_emit(ring, MI_NOOP);
11076
11077 intel_mark_page_flip_active(intel_crtc);
11078 __intel_ring_advance(ring);
11079 return 0;
11080}
11081
11082static int intel_gen4_queue_flip(struct drm_device *dev,
11083 struct drm_crtc *crtc,
11084 struct drm_framebuffer *fb,
11085 struct drm_i915_gem_object *obj,
11086 struct intel_engine_cs *ring,
11087 uint32_t flags)
11088{
11089 struct drm_i915_private *dev_priv = dev->dev_private;
11090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11091 uint32_t pf, pipesrc;
11092 int ret;
11093
11094 ret = intel_ring_begin(ring, 4);
11095 if (ret)
11096 return ret;
11097
11098 /* i965+ uses the linear or tiled offsets from the
11099 * Display Registers (which do not change across a page-flip)
11100 * so we need only reprogram the base address.
11101 */
11102 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11103 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11104 intel_ring_emit(ring, fb->pitches[0]);
11105 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11106 obj->tiling_mode);
11107
11108 /* XXX Enabling the panel-fitter across page-flip is so far
11109 * untested on non-native modes, so ignore it for now.
11110 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11111 */
11112 pf = 0;
11113 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11114 intel_ring_emit(ring, pf | pipesrc);
11115
11116 intel_mark_page_flip_active(intel_crtc);
11117 __intel_ring_advance(ring);
11118 return 0;
11119}
11120
11121static int intel_gen6_queue_flip(struct drm_device *dev,
11122 struct drm_crtc *crtc,
11123 struct drm_framebuffer *fb,
11124 struct drm_i915_gem_object *obj,
11125 struct intel_engine_cs *ring,
11126 uint32_t flags)
11127{
11128 struct drm_i915_private *dev_priv = dev->dev_private;
11129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11130 uint32_t pf, pipesrc;
11131 int ret;
11132
11133 ret = intel_ring_begin(ring, 4);
11134 if (ret)
11135 return ret;
11136
11137 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11138 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11139 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11140 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11141
11142 /* Contrary to the suggestions in the documentation,
11143 * "Enable Panel Fitter" does not seem to be required when page
11144 * flipping with a non-native mode, and worse causes a normal
11145 * modeset to fail.
11146 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11147 */
11148 pf = 0;
11149 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11150 intel_ring_emit(ring, pf | pipesrc);
11151
11152 intel_mark_page_flip_active(intel_crtc);
11153 __intel_ring_advance(ring);
11154 return 0;
11155}
11156
11157static int intel_gen7_queue_flip(struct drm_device *dev,
11158 struct drm_crtc *crtc,
11159 struct drm_framebuffer *fb,
11160 struct drm_i915_gem_object *obj,
11161 struct intel_engine_cs *ring,
11162 uint32_t flags)
11163{
11164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11165 uint32_t plane_bit = 0;
11166 int len, ret;
11167
11168 switch (intel_crtc->plane) {
11169 case PLANE_A:
11170 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11171 break;
11172 case PLANE_B:
11173 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11174 break;
11175 case PLANE_C:
11176 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11177 break;
11178 default:
11179 WARN_ONCE(1, "unknown plane in flip command\n");
11180 return -ENODEV;
11181 }
11182
11183 len = 4;
11184 if (ring->id == RCS) {
11185 len += 6;
11186 /*
11187 * On Gen 8, SRM is now taking an extra dword to accommodate
11188 * 48bits addresses, and we need a NOOP for the batch size to
11189 * stay even.
11190 */
11191 if (IS_GEN8(dev))
11192 len += 2;
11193 }
11194
11195 /*
11196 * BSpec MI_DISPLAY_FLIP for IVB:
11197 * "The full packet must be contained within the same cache line."
11198 *
11199 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11200 * cacheline, if we ever start emitting more commands before
11201 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11202 * then do the cacheline alignment, and finally emit the
11203 * MI_DISPLAY_FLIP.
11204 */
11205 ret = intel_ring_cacheline_align(ring);
11206 if (ret)
11207 return ret;
11208
11209 ret = intel_ring_begin(ring, len);
11210 if (ret)
11211 return ret;
11212
11213 /* Unmask the flip-done completion message. Note that the bspec says that
11214 * we should do this for both the BCS and RCS, and that we must not unmask
11215 * more than one flip event at any time (or ensure that one flip message
11216 * can be sent by waiting for flip-done prior to queueing new flips).
11217 * Experimentation says that BCS works despite DERRMR masking all
11218 * flip-done completion events and that unmasking all planes at once
11219 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11220 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11221 */
11222 if (ring->id == RCS) {
11223 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11224 intel_ring_emit(ring, DERRMR);
11225 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11226 DERRMR_PIPEB_PRI_FLIP_DONE |
11227 DERRMR_PIPEC_PRI_FLIP_DONE));
11228 if (IS_GEN8(dev))
11229 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11230 MI_SRM_LRM_GLOBAL_GTT);
11231 else
11232 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11233 MI_SRM_LRM_GLOBAL_GTT);
11234 intel_ring_emit(ring, DERRMR);
11235 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11236 if (IS_GEN8(dev)) {
11237 intel_ring_emit(ring, 0);
11238 intel_ring_emit(ring, MI_NOOP);
11239 }
11240 }
11241
11242 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11243 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11244 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11245 intel_ring_emit(ring, (MI_NOOP));
11246
11247 intel_mark_page_flip_active(intel_crtc);
11248 __intel_ring_advance(ring);
11249 return 0;
11250}
11251
11252static bool use_mmio_flip(struct intel_engine_cs *ring,
11253 struct drm_i915_gem_object *obj)
11254{
11255 /*
11256 * This is not being used for older platforms, because
11257 * non-availability of flip done interrupt forces us to use
11258 * CS flips. Older platforms derive flip done using some clever
11259 * tricks involving the flip_pending status bits and vblank irqs.
11260 * So using MMIO flips there would disrupt this mechanism.
11261 */
11262
11263 if (ring == NULL)
11264 return true;
11265
11266 if (INTEL_INFO(ring->dev)->gen < 5)
11267 return false;
11268
11269 if (i915.use_mmio_flip < 0)
11270 return false;
11271 else if (i915.use_mmio_flip > 0)
11272 return true;
11273 else if (i915.enable_execlists)
11274 return true;
11275 else
11276 return ring != i915_gem_request_get_ring(obj->last_write_req);
11277}
11278
11279static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11280{
11281 struct drm_device *dev = intel_crtc->base.dev;
11282 struct drm_i915_private *dev_priv = dev->dev_private;
11283 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11284 const enum pipe pipe = intel_crtc->pipe;
11285 u32 ctl, stride;
11286
11287 ctl = I915_READ(PLANE_CTL(pipe, 0));
11288 ctl &= ~PLANE_CTL_TILED_MASK;
11289 switch (fb->modifier[0]) {
11290 case DRM_FORMAT_MOD_NONE:
11291 break;
11292 case I915_FORMAT_MOD_X_TILED:
11293 ctl |= PLANE_CTL_TILED_X;
11294 break;
11295 case I915_FORMAT_MOD_Y_TILED:
11296 ctl |= PLANE_CTL_TILED_Y;
11297 break;
11298 case I915_FORMAT_MOD_Yf_TILED:
11299 ctl |= PLANE_CTL_TILED_YF;
11300 break;
11301 default:
11302 MISSING_CASE(fb->modifier[0]);
11303 }
11304
11305 /*
11306 * The stride is either expressed as a multiple of 64 bytes chunks for
11307 * linear buffers or in number of tiles for tiled buffers.
11308 */
11309 stride = fb->pitches[0] /
11310 intel_fb_stride_alignment(dev, fb->modifier[0],
11311 fb->pixel_format);
11312
11313 /*
11314 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11315 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11316 */
11317 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11318 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11319
11320 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11321 POSTING_READ(PLANE_SURF(pipe, 0));
11322}
11323
11324static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11325{
11326 struct drm_device *dev = intel_crtc->base.dev;
11327 struct drm_i915_private *dev_priv = dev->dev_private;
11328 struct intel_framebuffer *intel_fb =
11329 to_intel_framebuffer(intel_crtc->base.primary->fb);
11330 struct drm_i915_gem_object *obj = intel_fb->obj;
11331 u32 dspcntr;
11332 u32 reg;
11333
11334 reg = DSPCNTR(intel_crtc->plane);
11335 dspcntr = I915_READ(reg);
11336
11337 if (obj->tiling_mode != I915_TILING_NONE)
11338 dspcntr |= DISPPLANE_TILED;
11339 else
11340 dspcntr &= ~DISPPLANE_TILED;
11341
11342 I915_WRITE(reg, dspcntr);
11343
11344 I915_WRITE(DSPSURF(intel_crtc->plane),
11345 intel_crtc->unpin_work->gtt_offset);
11346 POSTING_READ(DSPSURF(intel_crtc->plane));
11347
11348}
11349
11350/*
11351 * XXX: This is the temporary way to update the plane registers until we get
11352 * around to using the usual plane update functions for MMIO flips
11353 */
11354static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11355{
11356 struct drm_device *dev = intel_crtc->base.dev;
11357 bool atomic_update;
11358 u32 start_vbl_count;
11359
11360 intel_mark_page_flip_active(intel_crtc);
11361
11362 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11363
11364 if (INTEL_INFO(dev)->gen >= 9)
11365 skl_do_mmio_flip(intel_crtc);
11366 else
11367 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11368 ilk_do_mmio_flip(intel_crtc);
11369
11370 if (atomic_update)
11371 intel_pipe_update_end(intel_crtc, start_vbl_count);
11372}
11373
11374static void intel_mmio_flip_work_func(struct work_struct *work)
11375{
11376 struct intel_mmio_flip *mmio_flip =
11377 container_of(work, struct intel_mmio_flip, work);
11378
11379 if (mmio_flip->req)
11380 WARN_ON(__i915_wait_request(mmio_flip->req,
11381 mmio_flip->crtc->reset_counter,
11382 false, NULL,
11383 &mmio_flip->i915->rps.mmioflips));
11384
11385 intel_do_mmio_flip(mmio_flip->crtc);
11386
11387 i915_gem_request_unreference__unlocked(mmio_flip->req);
11388 kfree(mmio_flip);
11389}
11390
11391static int intel_queue_mmio_flip(struct drm_device *dev,
11392 struct drm_crtc *crtc,
11393 struct drm_framebuffer *fb,
11394 struct drm_i915_gem_object *obj,
11395 struct intel_engine_cs *ring,
11396 uint32_t flags)
11397{
11398 struct intel_mmio_flip *mmio_flip;
11399
11400 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11401 if (mmio_flip == NULL)
11402 return -ENOMEM;
11403
11404 mmio_flip->i915 = to_i915(dev);
11405 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11406 mmio_flip->crtc = to_intel_crtc(crtc);
11407
11408 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11409 schedule_work(&mmio_flip->work);
11410
11411 return 0;
11412}
11413
11414static int intel_default_queue_flip(struct drm_device *dev,
11415 struct drm_crtc *crtc,
11416 struct drm_framebuffer *fb,
11417 struct drm_i915_gem_object *obj,
11418 struct intel_engine_cs *ring,
11419 uint32_t flags)
11420{
11421 return -ENODEV;
11422}
11423
11424static bool __intel_pageflip_stall_check(struct drm_device *dev,
11425 struct drm_crtc *crtc)
11426{
11427 struct drm_i915_private *dev_priv = dev->dev_private;
11428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11429 struct intel_unpin_work *work = intel_crtc->unpin_work;
11430 u32 addr;
11431
11432 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11433 return true;
11434
11435 if (!work->enable_stall_check)
11436 return false;
11437
11438 if (work->flip_ready_vblank == 0) {
11439 if (work->flip_queued_req &&
11440 !i915_gem_request_completed(work->flip_queued_req, true))
11441 return false;
11442
11443 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11444 }
11445
11446 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11447 return false;
11448
11449 /* Potential stall - if we see that the flip has happened,
11450 * assume a missed interrupt. */
11451 if (INTEL_INFO(dev)->gen >= 4)
11452 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11453 else
11454 addr = I915_READ(DSPADDR(intel_crtc->plane));
11455
11456 /* There is a potential issue here with a false positive after a flip
11457 * to the same address. We could address this by checking for a
11458 * non-incrementing frame counter.
11459 */
11460 return addr == work->gtt_offset;
11461}
11462
11463void intel_check_page_flip(struct drm_device *dev, int pipe)
11464{
11465 struct drm_i915_private *dev_priv = dev->dev_private;
11466 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11467 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11468 struct intel_unpin_work *work;
11469
11470 WARN_ON(!in_interrupt());
11471
11472 if (crtc == NULL)
11473 return;
11474
11475 spin_lock(&dev->event_lock);
11476 work = intel_crtc->unpin_work;
11477 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11478 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11479 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11480 page_flip_completed(intel_crtc);
11481 work = NULL;
11482 }
11483 if (work != NULL &&
11484 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11485 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11486 spin_unlock(&dev->event_lock);
11487}
11488
11489static int intel_crtc_page_flip(struct drm_crtc *crtc,
11490 struct drm_framebuffer *fb,
11491 struct drm_pending_vblank_event *event,
11492 uint32_t page_flip_flags)
11493{
11494 struct drm_device *dev = crtc->dev;
11495 struct drm_i915_private *dev_priv = dev->dev_private;
11496 struct drm_framebuffer *old_fb = crtc->primary->fb;
11497 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11499 struct drm_plane *primary = crtc->primary;
11500 enum pipe pipe = intel_crtc->pipe;
11501 struct intel_unpin_work *work;
11502 struct intel_engine_cs *ring;
11503 bool mmio_flip;
11504 int ret;
11505
11506 /*
11507 * drm_mode_page_flip_ioctl() should already catch this, but double
11508 * check to be safe. In the future we may enable pageflipping from
11509 * a disabled primary plane.
11510 */
11511 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11512 return -EBUSY;
11513
11514 /* Can't change pixel format via MI display flips. */
11515 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11516 return -EINVAL;
11517
11518 /*
11519 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11520 * Note that pitch changes could also affect these register.
11521 */
11522 if (INTEL_INFO(dev)->gen > 3 &&
11523 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11524 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11525 return -EINVAL;
11526
11527 if (i915_terminally_wedged(&dev_priv->gpu_error))
11528 goto out_hang;
11529
11530 work = kzalloc(sizeof(*work), GFP_KERNEL);
11531 if (work == NULL)
11532 return -ENOMEM;
11533
11534 work->event = event;
11535 work->crtc = crtc;
11536 work->old_fb = old_fb;
11537 INIT_WORK(&work->work, intel_unpin_work_fn);
11538
11539 ret = drm_crtc_vblank_get(crtc);
11540 if (ret)
11541 goto free_work;
11542
11543 /* We borrow the event spin lock for protecting unpin_work */
11544 spin_lock_irq(&dev->event_lock);
11545 if (intel_crtc->unpin_work) {
11546 /* Before declaring the flip queue wedged, check if
11547 * the hardware completed the operation behind our backs.
11548 */
11549 if (__intel_pageflip_stall_check(dev, crtc)) {
11550 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11551 page_flip_completed(intel_crtc);
11552 } else {
11553 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11554 spin_unlock_irq(&dev->event_lock);
11555
11556 drm_crtc_vblank_put(crtc);
11557 kfree(work);
11558 return -EBUSY;
11559 }
11560 }
11561 intel_crtc->unpin_work = work;
11562 spin_unlock_irq(&dev->event_lock);
11563
11564 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11565 flush_workqueue(dev_priv->wq);
11566
11567 /* Reference the objects for the scheduled work. */
11568 drm_framebuffer_reference(work->old_fb);
11569 drm_gem_object_reference(&obj->base);
11570
11571 crtc->primary->fb = fb;
11572 update_state_fb(crtc->primary);
11573
11574 work->pending_flip_obj = obj;
11575
11576 ret = i915_mutex_lock_interruptible(dev);
11577 if (ret)
11578 goto cleanup;
11579
11580 atomic_inc(&intel_crtc->unpin_work_count);
11581 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11582
11583 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11584 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11585
11586 if (IS_VALLEYVIEW(dev)) {
11587 ring = &dev_priv->ring[BCS];
11588 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11589 /* vlv: DISPLAY_FLIP fails to change tiling */
11590 ring = NULL;
11591 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11592 ring = &dev_priv->ring[BCS];
11593 } else if (INTEL_INFO(dev)->gen >= 7) {
11594 ring = i915_gem_request_get_ring(obj->last_write_req);
11595 if (ring == NULL || ring->id != RCS)
11596 ring = &dev_priv->ring[BCS];
11597 } else {
11598 ring = &dev_priv->ring[RCS];
11599 }
11600
11601 mmio_flip = use_mmio_flip(ring, obj);
11602
11603 /* When using CS flips, we want to emit semaphores between rings.
11604 * However, when using mmio flips we will create a task to do the
11605 * synchronisation, so all we want here is to pin the framebuffer
11606 * into the display plane and skip any waits.
11607 */
11608 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11609 crtc->primary->state,
11610 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
11611 if (ret)
11612 goto cleanup_pending;
11613
11614 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11615 + intel_crtc->dspaddr_offset;
11616
11617 if (mmio_flip) {
11618 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11619 page_flip_flags);
11620 if (ret)
11621 goto cleanup_unpin;
11622
11623 i915_gem_request_assign(&work->flip_queued_req,
11624 obj->last_write_req);
11625 } else {
11626 if (obj->last_write_req) {
11627 ret = i915_gem_check_olr(obj->last_write_req);
11628 if (ret)
11629 goto cleanup_unpin;
11630 }
11631
11632 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
11633 page_flip_flags);
11634 if (ret)
11635 goto cleanup_unpin;
11636
11637 i915_gem_request_assign(&work->flip_queued_req,
11638 intel_ring_get_request(ring));
11639 }
11640
11641 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11642 work->enable_stall_check = true;
11643
11644 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11645 INTEL_FRONTBUFFER_PRIMARY(pipe));
11646
11647 intel_fbc_disable(dev);
11648 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11649 mutex_unlock(&dev->struct_mutex);
11650
11651 trace_i915_flip_request(intel_crtc->plane, obj);
11652
11653 return 0;
11654
11655cleanup_unpin:
11656 intel_unpin_fb_obj(fb, crtc->primary->state);
11657cleanup_pending:
11658 atomic_dec(&intel_crtc->unpin_work_count);
11659 mutex_unlock(&dev->struct_mutex);
11660cleanup:
11661 crtc->primary->fb = old_fb;
11662 update_state_fb(crtc->primary);
11663
11664 drm_gem_object_unreference_unlocked(&obj->base);
11665 drm_framebuffer_unreference(work->old_fb);
11666
11667 spin_lock_irq(&dev->event_lock);
11668 intel_crtc->unpin_work = NULL;
11669 spin_unlock_irq(&dev->event_lock);
11670
11671 drm_crtc_vblank_put(crtc);
11672free_work:
11673 kfree(work);
11674
11675 if (ret == -EIO) {
11676out_hang:
11677 ret = intel_plane_restore(primary);
11678 if (ret == 0 && event) {
11679 spin_lock_irq(&dev->event_lock);
11680 drm_send_vblank_event(dev, pipe, event);
11681 spin_unlock_irq(&dev->event_lock);
11682 }
11683 }
11684 return ret;
11685}
11686
11687static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11688 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11689 .load_lut = intel_crtc_load_lut,
11690 .atomic_begin = intel_begin_crtc_commit,
11691 .atomic_flush = intel_finish_crtc_commit,
11692};
11693
11694/**
11695 * intel_modeset_update_staged_output_state
11696 *
11697 * Updates the staged output configuration state, e.g. after we've read out the
11698 * current hw state.
11699 */
11700static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11701{
11702 struct intel_crtc *crtc;
11703 struct intel_encoder *encoder;
11704 struct intel_connector *connector;
11705
11706 for_each_intel_connector(dev, connector) {
11707 connector->new_encoder =
11708 to_intel_encoder(connector->base.encoder);
11709 }
11710
11711 for_each_intel_encoder(dev, encoder) {
11712 encoder->new_crtc =
11713 to_intel_crtc(encoder->base.crtc);
11714 }
11715
11716 for_each_intel_crtc(dev, crtc) {
11717 crtc->new_enabled = crtc->base.state->enable;
11718 }
11719}
11720
11721/* Transitional helper to copy current connector/encoder state to
11722 * connector->state. This is needed so that code that is partially
11723 * converted to atomic does the right thing.
11724 */
11725static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11726{
11727 struct intel_connector *connector;
11728
11729 for_each_intel_connector(dev, connector) {
11730 if (connector->base.encoder) {
11731 connector->base.state->best_encoder =
11732 connector->base.encoder;
11733 connector->base.state->crtc =
11734 connector->base.encoder->crtc;
11735 } else {
11736 connector->base.state->best_encoder = NULL;
11737 connector->base.state->crtc = NULL;
11738 }
11739 }
11740}
11741
11742static void
11743connected_sink_compute_bpp(struct intel_connector *connector,
11744 struct intel_crtc_state *pipe_config)
11745{
11746 int bpp = pipe_config->pipe_bpp;
11747
11748 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11749 connector->base.base.id,
11750 connector->base.name);
11751
11752 /* Don't use an invalid EDID bpc value */
11753 if (connector->base.display_info.bpc &&
11754 connector->base.display_info.bpc * 3 < bpp) {
11755 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11756 bpp, connector->base.display_info.bpc*3);
11757 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11758 }
11759
11760 /* Clamp bpp to 8 on screens without EDID 1.4 */
11761 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11762 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11763 bpp);
11764 pipe_config->pipe_bpp = 24;
11765 }
11766}
11767
11768static int
11769compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11770 struct intel_crtc_state *pipe_config)
11771{
11772 struct drm_device *dev = crtc->base.dev;
11773 struct drm_atomic_state *state;
11774 struct drm_connector *connector;
11775 struct drm_connector_state *connector_state;
11776 int bpp, i;
11777
11778 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11779 bpp = 10*3;
11780 else if (INTEL_INFO(dev)->gen >= 5)
11781 bpp = 12*3;
11782 else
11783 bpp = 8*3;
11784
11785
11786 pipe_config->pipe_bpp = bpp;
11787
11788 state = pipe_config->base.state;
11789
11790 /* Clamp display bpp to EDID value */
11791 for_each_connector_in_state(state, connector, connector_state, i) {
11792 if (connector_state->crtc != &crtc->base)
11793 continue;
11794
11795 connected_sink_compute_bpp(to_intel_connector(connector),
11796 pipe_config);
11797 }
11798
11799 return bpp;
11800}
11801
11802static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11803{
11804 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11805 "type: 0x%x flags: 0x%x\n",
11806 mode->crtc_clock,
11807 mode->crtc_hdisplay, mode->crtc_hsync_start,
11808 mode->crtc_hsync_end, mode->crtc_htotal,
11809 mode->crtc_vdisplay, mode->crtc_vsync_start,
11810 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11811}
11812
11813static void intel_dump_pipe_config(struct intel_crtc *crtc,
11814 struct intel_crtc_state *pipe_config,
11815 const char *context)
11816{
11817 struct drm_device *dev = crtc->base.dev;
11818 struct drm_plane *plane;
11819 struct intel_plane *intel_plane;
11820 struct intel_plane_state *state;
11821 struct drm_framebuffer *fb;
11822
11823 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11824 context, pipe_config, pipe_name(crtc->pipe));
11825
11826 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11827 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11828 pipe_config->pipe_bpp, pipe_config->dither);
11829 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11830 pipe_config->has_pch_encoder,
11831 pipe_config->fdi_lanes,
11832 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11833 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11834 pipe_config->fdi_m_n.tu);
11835 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11836 pipe_config->has_dp_encoder,
11837 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11838 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11839 pipe_config->dp_m_n.tu);
11840
11841 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11842 pipe_config->has_dp_encoder,
11843 pipe_config->dp_m2_n2.gmch_m,
11844 pipe_config->dp_m2_n2.gmch_n,
11845 pipe_config->dp_m2_n2.link_m,
11846 pipe_config->dp_m2_n2.link_n,
11847 pipe_config->dp_m2_n2.tu);
11848
11849 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11850 pipe_config->has_audio,
11851 pipe_config->has_infoframe);
11852
11853 DRM_DEBUG_KMS("requested mode:\n");
11854 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11855 DRM_DEBUG_KMS("adjusted mode:\n");
11856 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11857 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11858 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11859 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11860 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11861 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11862 crtc->num_scalers,
11863 pipe_config->scaler_state.scaler_users,
11864 pipe_config->scaler_state.scaler_id);
11865 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11866 pipe_config->gmch_pfit.control,
11867 pipe_config->gmch_pfit.pgm_ratios,
11868 pipe_config->gmch_pfit.lvds_border_bits);
11869 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11870 pipe_config->pch_pfit.pos,
11871 pipe_config->pch_pfit.size,
11872 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11873 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11874 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11875
11876 if (IS_BROXTON(dev)) {
11877 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11878 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11879 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11880 pipe_config->ddi_pll_sel,
11881 pipe_config->dpll_hw_state.ebb0,
11882 pipe_config->dpll_hw_state.pll0,
11883 pipe_config->dpll_hw_state.pll1,
11884 pipe_config->dpll_hw_state.pll2,
11885 pipe_config->dpll_hw_state.pll3,
11886 pipe_config->dpll_hw_state.pll6,
11887 pipe_config->dpll_hw_state.pll8,
11888 pipe_config->dpll_hw_state.pcsdw12);
11889 } else if (IS_SKYLAKE(dev)) {
11890 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11891 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11892 pipe_config->ddi_pll_sel,
11893 pipe_config->dpll_hw_state.ctrl1,
11894 pipe_config->dpll_hw_state.cfgcr1,
11895 pipe_config->dpll_hw_state.cfgcr2);
11896 } else if (HAS_DDI(dev)) {
11897 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11898 pipe_config->ddi_pll_sel,
11899 pipe_config->dpll_hw_state.wrpll);
11900 } else {
11901 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11902 "fp0: 0x%x, fp1: 0x%x\n",
11903 pipe_config->dpll_hw_state.dpll,
11904 pipe_config->dpll_hw_state.dpll_md,
11905 pipe_config->dpll_hw_state.fp0,
11906 pipe_config->dpll_hw_state.fp1);
11907 }
11908
11909 DRM_DEBUG_KMS("planes on this crtc\n");
11910 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11911 intel_plane = to_intel_plane(plane);
11912 if (intel_plane->pipe != crtc->pipe)
11913 continue;
11914
11915 state = to_intel_plane_state(plane->state);
11916 fb = state->base.fb;
11917 if (!fb) {
11918 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11919 "disabled, scaler_id = %d\n",
11920 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11921 plane->base.id, intel_plane->pipe,
11922 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11923 drm_plane_index(plane), state->scaler_id);
11924 continue;
11925 }
11926
11927 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11928 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11929 plane->base.id, intel_plane->pipe,
11930 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11931 drm_plane_index(plane));
11932 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11933 fb->base.id, fb->width, fb->height, fb->pixel_format);
11934 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11935 state->scaler_id,
11936 state->src.x1 >> 16, state->src.y1 >> 16,
11937 drm_rect_width(&state->src) >> 16,
11938 drm_rect_height(&state->src) >> 16,
11939 state->dst.x1, state->dst.y1,
11940 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11941 }
11942}
11943
11944static bool encoders_cloneable(const struct intel_encoder *a,
11945 const struct intel_encoder *b)
11946{
11947 /* masks could be asymmetric, so check both ways */
11948 return a == b || (a->cloneable & (1 << b->type) &&
11949 b->cloneable & (1 << a->type));
11950}
11951
11952static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11953 struct intel_crtc *crtc,
11954 struct intel_encoder *encoder)
11955{
11956 struct intel_encoder *source_encoder;
11957 struct drm_connector *connector;
11958 struct drm_connector_state *connector_state;
11959 int i;
11960
11961 for_each_connector_in_state(state, connector, connector_state, i) {
11962 if (connector_state->crtc != &crtc->base)
11963 continue;
11964
11965 source_encoder =
11966 to_intel_encoder(connector_state->best_encoder);
11967 if (!encoders_cloneable(encoder, source_encoder))
11968 return false;
11969 }
11970
11971 return true;
11972}
11973
11974static bool check_encoder_cloning(struct drm_atomic_state *state,
11975 struct intel_crtc *crtc)
11976{
11977 struct intel_encoder *encoder;
11978 struct drm_connector *connector;
11979 struct drm_connector_state *connector_state;
11980 int i;
11981
11982 for_each_connector_in_state(state, connector, connector_state, i) {
11983 if (connector_state->crtc != &crtc->base)
11984 continue;
11985
11986 encoder = to_intel_encoder(connector_state->best_encoder);
11987 if (!check_single_encoder_cloning(state, crtc, encoder))
11988 return false;
11989 }
11990
11991 return true;
11992}
11993
11994static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11995{
11996 struct drm_device *dev = state->dev;
11997 struct intel_encoder *encoder;
11998 struct drm_connector *connector;
11999 struct drm_connector_state *connector_state;
12000 unsigned int used_ports = 0;
12001 int i;
12002
12003 /*
12004 * Walk the connector list instead of the encoder
12005 * list to detect the problem on ddi platforms
12006 * where there's just one encoder per digital port.
12007 */
12008 for_each_connector_in_state(state, connector, connector_state, i) {
12009 if (!connector_state->best_encoder)
12010 continue;
12011
12012 encoder = to_intel_encoder(connector_state->best_encoder);
12013
12014 WARN_ON(!connector_state->crtc);
12015
12016 switch (encoder->type) {
12017 unsigned int port_mask;
12018 case INTEL_OUTPUT_UNKNOWN:
12019 if (WARN_ON(!HAS_DDI(dev)))
12020 break;
12021 case INTEL_OUTPUT_DISPLAYPORT:
12022 case INTEL_OUTPUT_HDMI:
12023 case INTEL_OUTPUT_EDP:
12024 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12025
12026 /* the same port mustn't appear more than once */
12027 if (used_ports & port_mask)
12028 return false;
12029
12030 used_ports |= port_mask;
12031 default:
12032 break;
12033 }
12034 }
12035
12036 return true;
12037}
12038
12039static void
12040clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12041{
12042 struct drm_crtc_state tmp_state;
12043 struct intel_crtc_scaler_state scaler_state;
12044 struct intel_dpll_hw_state dpll_hw_state;
12045 enum intel_dpll_id shared_dpll;
12046 uint32_t ddi_pll_sel;
12047
12048 /* FIXME: before the switch to atomic started, a new pipe_config was
12049 * kzalloc'd. Code that depends on any field being zero should be
12050 * fixed, so that the crtc_state can be safely duplicated. For now,
12051 * only fields that are know to not cause problems are preserved. */
12052
12053 tmp_state = crtc_state->base;
12054 scaler_state = crtc_state->scaler_state;
12055 shared_dpll = crtc_state->shared_dpll;
12056 dpll_hw_state = crtc_state->dpll_hw_state;
12057 ddi_pll_sel = crtc_state->ddi_pll_sel;
12058
12059 memset(crtc_state, 0, sizeof *crtc_state);
12060
12061 crtc_state->base = tmp_state;
12062 crtc_state->scaler_state = scaler_state;
12063 crtc_state->shared_dpll = shared_dpll;
12064 crtc_state->dpll_hw_state = dpll_hw_state;
12065 crtc_state->ddi_pll_sel = ddi_pll_sel;
12066}
12067
12068static int
12069intel_modeset_pipe_config(struct drm_crtc *crtc,
12070 struct drm_atomic_state *state)
12071{
12072 struct drm_crtc_state *crtc_state;
12073 struct intel_crtc_state *pipe_config;
12074 struct intel_encoder *encoder;
12075 struct drm_connector *connector;
12076 struct drm_connector_state *connector_state;
12077 int base_bpp, ret = -EINVAL;
12078 int i;
12079 bool retry = true;
12080
12081 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
12082 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12083 return -EINVAL;
12084 }
12085
12086 if (!check_digital_port_conflicts(state)) {
12087 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12088 return -EINVAL;
12089 }
12090
12091 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12092 if (WARN_ON(!crtc_state))
12093 return -EINVAL;
12094
12095 pipe_config = to_intel_crtc_state(crtc_state);
12096
12097 /*
12098 * XXX: Add all connectors to make the crtc state match the encoders.
12099 */
12100 if (!needs_modeset(&pipe_config->base)) {
12101 ret = drm_atomic_add_affected_connectors(state, crtc);
12102 if (ret)
12103 return ret;
12104 }
12105
12106 clear_intel_crtc_state(pipe_config);
12107
12108 pipe_config->cpu_transcoder =
12109 (enum transcoder) to_intel_crtc(crtc)->pipe;
12110
12111 /*
12112 * Sanitize sync polarity flags based on requested ones. If neither
12113 * positive or negative polarity is requested, treat this as meaning
12114 * negative polarity.
12115 */
12116 if (!(pipe_config->base.adjusted_mode.flags &
12117 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12118 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12119
12120 if (!(pipe_config->base.adjusted_mode.flags &
12121 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12122 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12123
12124 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12125 * plane pixel format and any sink constraints into account. Returns the
12126 * source plane bpp so that dithering can be selected on mismatches
12127 * after encoders and crtc also have had their say. */
12128 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12129 pipe_config);
12130 if (base_bpp < 0)
12131 goto fail;
12132
12133 /*
12134 * Determine the real pipe dimensions. Note that stereo modes can
12135 * increase the actual pipe size due to the frame doubling and
12136 * insertion of additional space for blanks between the frame. This
12137 * is stored in the crtc timings. We use the requested mode to do this
12138 * computation to clearly distinguish it from the adjusted mode, which
12139 * can be changed by the connectors in the below retry loop.
12140 */
12141 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12142 &pipe_config->pipe_src_w,
12143 &pipe_config->pipe_src_h);
12144
12145encoder_retry:
12146 /* Ensure the port clock defaults are reset when retrying. */
12147 pipe_config->port_clock = 0;
12148 pipe_config->pixel_multiplier = 1;
12149
12150 /* Fill in default crtc timings, allow encoders to overwrite them. */
12151 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12152 CRTC_STEREO_DOUBLE);
12153
12154 /* Pass our mode to the connectors and the CRTC to give them a chance to
12155 * adjust it according to limitations or connector properties, and also
12156 * a chance to reject the mode entirely.
12157 */
12158 for_each_connector_in_state(state, connector, connector_state, i) {
12159 if (connector_state->crtc != crtc)
12160 continue;
12161
12162 encoder = to_intel_encoder(connector_state->best_encoder);
12163
12164 if (!(encoder->compute_config(encoder, pipe_config))) {
12165 DRM_DEBUG_KMS("Encoder config failure\n");
12166 goto fail;
12167 }
12168 }
12169
12170 /* Set default port clock if not overwritten by the encoder. Needs to be
12171 * done afterwards in case the encoder adjusts the mode. */
12172 if (!pipe_config->port_clock)
12173 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12174 * pipe_config->pixel_multiplier;
12175
12176 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12177 if (ret < 0) {
12178 DRM_DEBUG_KMS("CRTC fixup failed\n");
12179 goto fail;
12180 }
12181
12182 if (ret == RETRY) {
12183 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12184 ret = -EINVAL;
12185 goto fail;
12186 }
12187
12188 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12189 retry = false;
12190 goto encoder_retry;
12191 }
12192
12193 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
12194 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12195 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12196
12197 /* Check if we need to force a modeset */
12198 if (pipe_config->has_audio !=
12199 to_intel_crtc_state(crtc->state)->has_audio) {
12200 pipe_config->base.mode_changed = true;
12201 ret = drm_atomic_add_affected_planes(state, crtc);
12202 }
12203
12204 /*
12205 * Note we have an issue here with infoframes: current code
12206 * only updates them on the full mode set path per hw
12207 * requirements. So here we should be checking for any
12208 * required changes and forcing a mode set.
12209 */
12210fail:
12211 return ret;
12212}
12213
12214static bool intel_crtc_in_use(struct drm_crtc *crtc)
12215{
12216 struct drm_encoder *encoder;
12217 struct drm_device *dev = crtc->dev;
12218
12219 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12220 if (encoder->crtc == crtc)
12221 return true;
12222
12223 return false;
12224}
12225
12226static void
12227intel_modeset_update_state(struct drm_atomic_state *state)
12228{
12229 struct drm_device *dev = state->dev;
12230 struct drm_i915_private *dev_priv = dev->dev_private;
12231 struct intel_encoder *intel_encoder;
12232 struct drm_crtc *crtc;
12233 struct drm_crtc_state *crtc_state;
12234 struct drm_connector *connector;
12235
12236 intel_shared_dpll_commit(dev_priv);
12237 drm_atomic_helper_swap_state(state->dev, state);
12238
12239 for_each_intel_encoder(dev, intel_encoder) {
12240 if (!intel_encoder->base.crtc)
12241 continue;
12242
12243 crtc = intel_encoder->base.crtc;
12244 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12245 if (!crtc_state || !needs_modeset(crtc->state))
12246 continue;
12247
12248 intel_encoder->connectors_active = false;
12249 }
12250
12251 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12252 intel_modeset_update_staged_output_state(state->dev);
12253
12254 /* Double check state. */
12255 for_each_crtc(dev, crtc) {
12256 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
12257
12258 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12259 }
12260
12261 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12262 if (!connector->encoder || !connector->encoder->crtc)
12263 continue;
12264
12265 crtc = connector->encoder->crtc;
12266 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12267 if (!crtc_state || !needs_modeset(crtc->state))
12268 continue;
12269
12270 if (crtc->state->active) {
12271 struct drm_property *dpms_property =
12272 dev->mode_config.dpms_property;
12273
12274 connector->dpms = DRM_MODE_DPMS_ON;
12275 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
12276
12277 intel_encoder = to_intel_encoder(connector->encoder);
12278 intel_encoder->connectors_active = true;
12279 } else
12280 connector->dpms = DRM_MODE_DPMS_OFF;
12281 }
12282}
12283
12284static bool intel_fuzzy_clock_check(int clock1, int clock2)
12285{
12286 int diff;
12287
12288 if (clock1 == clock2)
12289 return true;
12290
12291 if (!clock1 || !clock2)
12292 return false;
12293
12294 diff = abs(clock1 - clock2);
12295
12296 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12297 return true;
12298
12299 return false;
12300}
12301
12302#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12303 list_for_each_entry((intel_crtc), \
12304 &(dev)->mode_config.crtc_list, \
12305 base.head) \
12306 if (mask & (1 <<(intel_crtc)->pipe))
12307
12308static bool
12309intel_pipe_config_compare(struct drm_device *dev,
12310 struct intel_crtc_state *current_config,
12311 struct intel_crtc_state *pipe_config)
12312{
12313#define PIPE_CONF_CHECK_X(name) \
12314 if (current_config->name != pipe_config->name) { \
12315 DRM_ERROR("mismatch in " #name " " \
12316 "(expected 0x%08x, found 0x%08x)\n", \
12317 current_config->name, \
12318 pipe_config->name); \
12319 return false; \
12320 }
12321
12322#define PIPE_CONF_CHECK_I(name) \
12323 if (current_config->name != pipe_config->name) { \
12324 DRM_ERROR("mismatch in " #name " " \
12325 "(expected %i, found %i)\n", \
12326 current_config->name, \
12327 pipe_config->name); \
12328 return false; \
12329 }
12330
12331/* This is required for BDW+ where there is only one set of registers for
12332 * switching between high and low RR.
12333 * This macro can be used whenever a comparison has to be made between one
12334 * hw state and multiple sw state variables.
12335 */
12336#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12337 if ((current_config->name != pipe_config->name) && \
12338 (current_config->alt_name != pipe_config->name)) { \
12339 DRM_ERROR("mismatch in " #name " " \
12340 "(expected %i or %i, found %i)\n", \
12341 current_config->name, \
12342 current_config->alt_name, \
12343 pipe_config->name); \
12344 return false; \
12345 }
12346
12347#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12348 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12349 DRM_ERROR("mismatch in " #name "(" #mask ") " \
12350 "(expected %i, found %i)\n", \
12351 current_config->name & (mask), \
12352 pipe_config->name & (mask)); \
12353 return false; \
12354 }
12355
12356#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12357 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12358 DRM_ERROR("mismatch in " #name " " \
12359 "(expected %i, found %i)\n", \
12360 current_config->name, \
12361 pipe_config->name); \
12362 return false; \
12363 }
12364
12365#define PIPE_CONF_QUIRK(quirk) \
12366 ((current_config->quirks | pipe_config->quirks) & (quirk))
12367
12368 PIPE_CONF_CHECK_I(cpu_transcoder);
12369
12370 PIPE_CONF_CHECK_I(has_pch_encoder);
12371 PIPE_CONF_CHECK_I(fdi_lanes);
12372 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12373 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12374 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12375 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12376 PIPE_CONF_CHECK_I(fdi_m_n.tu);
12377
12378 PIPE_CONF_CHECK_I(has_dp_encoder);
12379
12380 if (INTEL_INFO(dev)->gen < 8) {
12381 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12382 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12383 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12384 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12385 PIPE_CONF_CHECK_I(dp_m_n.tu);
12386
12387 if (current_config->has_drrs) {
12388 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12389 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12390 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12391 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12392 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12393 }
12394 } else {
12395 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12396 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12397 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12398 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12399 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12400 }
12401
12402 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12403 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12404 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12405 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12406 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12407 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12408
12409 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12410 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12411 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12412 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12413 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12414 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12415
12416 PIPE_CONF_CHECK_I(pixel_multiplier);
12417 PIPE_CONF_CHECK_I(has_hdmi_sink);
12418 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12419 IS_VALLEYVIEW(dev))
12420 PIPE_CONF_CHECK_I(limited_color_range);
12421 PIPE_CONF_CHECK_I(has_infoframe);
12422
12423 PIPE_CONF_CHECK_I(has_audio);
12424
12425 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12426 DRM_MODE_FLAG_INTERLACE);
12427
12428 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12429 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12430 DRM_MODE_FLAG_PHSYNC);
12431 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12432 DRM_MODE_FLAG_NHSYNC);
12433 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12434 DRM_MODE_FLAG_PVSYNC);
12435 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12436 DRM_MODE_FLAG_NVSYNC);
12437 }
12438
12439 PIPE_CONF_CHECK_I(pipe_src_w);
12440 PIPE_CONF_CHECK_I(pipe_src_h);
12441
12442 /*
12443 * FIXME: BIOS likes to set up a cloned config with lvds+external
12444 * screen. Since we don't yet re-compute the pipe config when moving
12445 * just the lvds port away to another pipe the sw tracking won't match.
12446 *
12447 * Proper atomic modesets with recomputed global state will fix this.
12448 * Until then just don't check gmch state for inherited modes.
12449 */
12450 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12451 PIPE_CONF_CHECK_I(gmch_pfit.control);
12452 /* pfit ratios are autocomputed by the hw on gen4+ */
12453 if (INTEL_INFO(dev)->gen < 4)
12454 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12455 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12456 }
12457
12458 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12459 if (current_config->pch_pfit.enabled) {
12460 PIPE_CONF_CHECK_I(pch_pfit.pos);
12461 PIPE_CONF_CHECK_I(pch_pfit.size);
12462 }
12463
12464 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12465
12466 /* BDW+ don't expose a synchronous way to read the state */
12467 if (IS_HASWELL(dev))
12468 PIPE_CONF_CHECK_I(ips_enabled);
12469
12470 PIPE_CONF_CHECK_I(double_wide);
12471
12472 PIPE_CONF_CHECK_X(ddi_pll_sel);
12473
12474 PIPE_CONF_CHECK_I(shared_dpll);
12475 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12476 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12477 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12478 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12479 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12480 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12481 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12482 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12483
12484 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12485 PIPE_CONF_CHECK_I(pipe_bpp);
12486
12487 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12488 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12489
12490#undef PIPE_CONF_CHECK_X
12491#undef PIPE_CONF_CHECK_I
12492#undef PIPE_CONF_CHECK_I_ALT
12493#undef PIPE_CONF_CHECK_FLAGS
12494#undef PIPE_CONF_CHECK_CLOCK_FUZZY
12495#undef PIPE_CONF_QUIRK
12496
12497 return true;
12498}
12499
12500static void check_wm_state(struct drm_device *dev)
12501{
12502 struct drm_i915_private *dev_priv = dev->dev_private;
12503 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12504 struct intel_crtc *intel_crtc;
12505 int plane;
12506
12507 if (INTEL_INFO(dev)->gen < 9)
12508 return;
12509
12510 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12511 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12512
12513 for_each_intel_crtc(dev, intel_crtc) {
12514 struct skl_ddb_entry *hw_entry, *sw_entry;
12515 const enum pipe pipe = intel_crtc->pipe;
12516
12517 if (!intel_crtc->active)
12518 continue;
12519
12520 /* planes */
12521 for_each_plane(dev_priv, pipe, plane) {
12522 hw_entry = &hw_ddb.plane[pipe][plane];
12523 sw_entry = &sw_ddb->plane[pipe][plane];
12524
12525 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12526 continue;
12527
12528 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12529 "(expected (%u,%u), found (%u,%u))\n",
12530 pipe_name(pipe), plane + 1,
12531 sw_entry->start, sw_entry->end,
12532 hw_entry->start, hw_entry->end);
12533 }
12534
12535 /* cursor */
12536 hw_entry = &hw_ddb.cursor[pipe];
12537 sw_entry = &sw_ddb->cursor[pipe];
12538
12539 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12540 continue;
12541
12542 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12543 "(expected (%u,%u), found (%u,%u))\n",
12544 pipe_name(pipe),
12545 sw_entry->start, sw_entry->end,
12546 hw_entry->start, hw_entry->end);
12547 }
12548}
12549
12550static void
12551check_connector_state(struct drm_device *dev)
12552{
12553 struct intel_connector *connector;
12554
12555 for_each_intel_connector(dev, connector) {
12556 /* This also checks the encoder/connector hw state with the
12557 * ->get_hw_state callbacks. */
12558 intel_connector_check_state(connector);
12559
12560 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
12561 "connector's staged encoder doesn't match current encoder\n");
12562 }
12563}
12564
12565static void
12566check_encoder_state(struct drm_device *dev)
12567{
12568 struct intel_encoder *encoder;
12569 struct intel_connector *connector;
12570
12571 for_each_intel_encoder(dev, encoder) {
12572 bool enabled = false;
12573 bool active = false;
12574 enum pipe pipe, tracked_pipe;
12575
12576 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12577 encoder->base.base.id,
12578 encoder->base.name);
12579
12580 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
12581 "encoder's stage crtc doesn't match current crtc\n");
12582 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12583 "encoder's active_connectors set, but no crtc\n");
12584
12585 for_each_intel_connector(dev, connector) {
12586 if (connector->base.encoder != &encoder->base)
12587 continue;
12588 enabled = true;
12589 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12590 active = true;
12591 }
12592 /*
12593 * for MST connectors if we unplug the connector is gone
12594 * away but the encoder is still connected to a crtc
12595 * until a modeset happens in response to the hotplug.
12596 */
12597 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12598 continue;
12599
12600 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12601 "encoder's enabled state mismatch "
12602 "(expected %i, found %i)\n",
12603 !!encoder->base.crtc, enabled);
12604 I915_STATE_WARN(active && !encoder->base.crtc,
12605 "active encoder with no crtc\n");
12606
12607 I915_STATE_WARN(encoder->connectors_active != active,
12608 "encoder's computed active state doesn't match tracked active state "
12609 "(expected %i, found %i)\n", active, encoder->connectors_active);
12610
12611 active = encoder->get_hw_state(encoder, &pipe);
12612 I915_STATE_WARN(active != encoder->connectors_active,
12613 "encoder's hw state doesn't match sw tracking "
12614 "(expected %i, found %i)\n",
12615 encoder->connectors_active, active);
12616
12617 if (!encoder->base.crtc)
12618 continue;
12619
12620 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12621 I915_STATE_WARN(active && pipe != tracked_pipe,
12622 "active encoder's pipe doesn't match"
12623 "(expected %i, found %i)\n",
12624 tracked_pipe, pipe);
12625
12626 }
12627}
12628
12629static void
12630check_crtc_state(struct drm_device *dev)
12631{
12632 struct drm_i915_private *dev_priv = dev->dev_private;
12633 struct intel_crtc *crtc;
12634 struct intel_encoder *encoder;
12635 struct intel_crtc_state pipe_config;
12636
12637 for_each_intel_crtc(dev, crtc) {
12638 bool enabled = false;
12639 bool active = false;
12640
12641 memset(&pipe_config, 0, sizeof(pipe_config));
12642
12643 DRM_DEBUG_KMS("[CRTC:%d]\n",
12644 crtc->base.base.id);
12645
12646 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12647 "active crtc, but not enabled in sw tracking\n");
12648
12649 for_each_intel_encoder(dev, encoder) {
12650 if (encoder->base.crtc != &crtc->base)
12651 continue;
12652 enabled = true;
12653 if (encoder->connectors_active)
12654 active = true;
12655 }
12656
12657 I915_STATE_WARN(active != crtc->active,
12658 "crtc's computed active state doesn't match tracked active state "
12659 "(expected %i, found %i)\n", active, crtc->active);
12660 I915_STATE_WARN(enabled != crtc->base.state->enable,
12661 "crtc's computed enabled state doesn't match tracked enabled state "
12662 "(expected %i, found %i)\n", enabled,
12663 crtc->base.state->enable);
12664
12665 active = dev_priv->display.get_pipe_config(crtc,
12666 &pipe_config);
12667
12668 /* hw state is inconsistent with the pipe quirk */
12669 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12670 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12671 active = crtc->active;
12672
12673 for_each_intel_encoder(dev, encoder) {
12674 enum pipe pipe;
12675 if (encoder->base.crtc != &crtc->base)
12676 continue;
12677 if (encoder->get_hw_state(encoder, &pipe))
12678 encoder->get_config(encoder, &pipe_config);
12679 }
12680
12681 I915_STATE_WARN(crtc->active != active,
12682 "crtc active state doesn't match with hw state "
12683 "(expected %i, found %i)\n", crtc->active, active);
12684
12685 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12686 "transitional active state does not match atomic hw state "
12687 "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12688
12689 if (active &&
12690 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12691 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12692 intel_dump_pipe_config(crtc, &pipe_config,
12693 "[hw state]");
12694 intel_dump_pipe_config(crtc, crtc->config,
12695 "[sw state]");
12696 }
12697 }
12698}
12699
12700static void
12701check_shared_dpll_state(struct drm_device *dev)
12702{
12703 struct drm_i915_private *dev_priv = dev->dev_private;
12704 struct intel_crtc *crtc;
12705 struct intel_dpll_hw_state dpll_hw_state;
12706 int i;
12707
12708 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12709 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12710 int enabled_crtcs = 0, active_crtcs = 0;
12711 bool active;
12712
12713 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12714
12715 DRM_DEBUG_KMS("%s\n", pll->name);
12716
12717 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12718
12719 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12720 "more active pll users than references: %i vs %i\n",
12721 pll->active, hweight32(pll->config.crtc_mask));
12722 I915_STATE_WARN(pll->active && !pll->on,
12723 "pll in active use but not on in sw tracking\n");
12724 I915_STATE_WARN(pll->on && !pll->active,
12725 "pll in on but not on in use in sw tracking\n");
12726 I915_STATE_WARN(pll->on != active,
12727 "pll on state mismatch (expected %i, found %i)\n",
12728 pll->on, active);
12729
12730 for_each_intel_crtc(dev, crtc) {
12731 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12732 enabled_crtcs++;
12733 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12734 active_crtcs++;
12735 }
12736 I915_STATE_WARN(pll->active != active_crtcs,
12737 "pll active crtcs mismatch (expected %i, found %i)\n",
12738 pll->active, active_crtcs);
12739 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12740 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12741 hweight32(pll->config.crtc_mask), enabled_crtcs);
12742
12743 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12744 sizeof(dpll_hw_state)),
12745 "pll hw state mismatch\n");
12746 }
12747}
12748
12749void
12750intel_modeset_check_state(struct drm_device *dev)
12751{
12752 check_wm_state(dev);
12753 check_connector_state(dev);
12754 check_encoder_state(dev);
12755 check_crtc_state(dev);
12756 check_shared_dpll_state(dev);
12757}
12758
12759void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12760 int dotclock)
12761{
12762 /*
12763 * FDI already provided one idea for the dotclock.
12764 * Yell if the encoder disagrees.
12765 */
12766 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12767 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12768 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12769}
12770
12771static void update_scanline_offset(struct intel_crtc *crtc)
12772{
12773 struct drm_device *dev = crtc->base.dev;
12774
12775 /*
12776 * The scanline counter increments at the leading edge of hsync.
12777 *
12778 * On most platforms it starts counting from vtotal-1 on the
12779 * first active line. That means the scanline counter value is
12780 * always one less than what we would expect. Ie. just after
12781 * start of vblank, which also occurs at start of hsync (on the
12782 * last active line), the scanline counter will read vblank_start-1.
12783 *
12784 * On gen2 the scanline counter starts counting from 1 instead
12785 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12786 * to keep the value positive), instead of adding one.
12787 *
12788 * On HSW+ the behaviour of the scanline counter depends on the output
12789 * type. For DP ports it behaves like most other platforms, but on HDMI
12790 * there's an extra 1 line difference. So we need to add two instead of
12791 * one to the value.
12792 */
12793 if (IS_GEN2(dev)) {
12794 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12795 int vtotal;
12796
12797 vtotal = mode->crtc_vtotal;
12798 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12799 vtotal /= 2;
12800
12801 crtc->scanline_offset = vtotal - 1;
12802 } else if (HAS_DDI(dev) &&
12803 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12804 crtc->scanline_offset = 2;
12805 } else
12806 crtc->scanline_offset = 1;
12807}
12808
12809static int
12810intel_modeset_compute_config(struct drm_atomic_state *state)
12811{
12812 struct drm_crtc *crtc;
12813 struct drm_crtc_state *crtc_state;
12814 int ret, i;
12815
12816 ret = drm_atomic_helper_check_modeset(state->dev, state);
12817 if (ret)
12818 return ret;
12819
12820 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12821 if (!crtc_state->enable &&
12822 WARN_ON(crtc_state->active))
12823 crtc_state->active = false;
12824
12825 if (!crtc_state->enable)
12826 continue;
12827
12828 ret = intel_modeset_pipe_config(crtc, state);
12829 if (ret)
12830 return ret;
12831
12832 intel_dump_pipe_config(to_intel_crtc(crtc),
12833 to_intel_crtc_state(crtc_state),
12834 "[modeset]");
12835 }
12836
12837 return drm_atomic_helper_check_planes(state->dev, state);
12838}
12839
12840static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
12841{
12842 struct drm_device *dev = state->dev;
12843 struct drm_i915_private *dev_priv = to_i915(dev);
12844 unsigned clear_pipes = 0;
12845 struct intel_crtc *intel_crtc;
12846 struct intel_crtc_state *intel_crtc_state;
12847 struct drm_crtc *crtc;
12848 struct drm_crtc_state *crtc_state;
12849 int ret = 0;
12850 int i;
12851
12852 if (!dev_priv->display.crtc_compute_clock)
12853 return 0;
12854
12855 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12856 intel_crtc = to_intel_crtc(crtc);
12857 intel_crtc_state = to_intel_crtc_state(crtc_state);
12858
12859 if (needs_modeset(crtc_state)) {
12860 clear_pipes |= 1 << intel_crtc->pipe;
12861 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12862 }
12863 }
12864
12865 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12866 if (ret)
12867 goto done;
12868
12869 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12870 if (!needs_modeset(crtc_state) || !crtc_state->enable)
12871 continue;
12872
12873 intel_crtc = to_intel_crtc(crtc);
12874 intel_crtc_state = to_intel_crtc_state(crtc_state);
12875
12876 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12877 intel_crtc_state);
12878 if (ret) {
12879 intel_shared_dpll_abort_config(dev_priv);
12880 goto done;
12881 }
12882 }
12883
12884done:
12885 return ret;
12886}
12887
12888/* Code that should eventually be part of atomic_check() */
12889static int __intel_set_mode_checks(struct drm_atomic_state *state)
12890{
12891 struct drm_device *dev = state->dev;
12892 int ret;
12893
12894 /*
12895 * See if the config requires any additional preparation, e.g.
12896 * to adjust global state with pipes off. We need to do this
12897 * here so we can get the modeset_pipe updated config for the new
12898 * mode set on this crtc. For other crtcs we need to use the
12899 * adjusted_mode bits in the crtc directly.
12900 */
12901 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev) || IS_BROADWELL(dev)) {
12902 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev))
12903 ret = valleyview_modeset_global_pipes(state);
12904 else
12905 ret = broadwell_modeset_global_pipes(state);
12906
12907 if (ret)
12908 return ret;
12909 }
12910
12911 ret = __intel_set_mode_setup_plls(state);
12912 if (ret)
12913 return ret;
12914
12915 return 0;
12916}
12917
12918static int __intel_set_mode(struct drm_atomic_state *state)
12919{
12920 struct drm_device *dev = state->dev;
12921 struct drm_i915_private *dev_priv = dev->dev_private;
12922 struct drm_crtc *crtc;
12923 struct drm_crtc_state *crtc_state;
12924 int ret = 0;
12925 int i;
12926
12927 ret = __intel_set_mode_checks(state);
12928 if (ret < 0)
12929 return ret;
12930
12931 ret = drm_atomic_helper_prepare_planes(dev, state);
12932 if (ret)
12933 return ret;
12934
12935 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12936 if (!needs_modeset(crtc_state) || !crtc->state->active)
12937 continue;
12938
12939 intel_crtc_disable_planes(crtc);
12940 dev_priv->display.crtc_disable(crtc);
12941 }
12942
12943 /* Only after disabling all output pipelines that will be changed can we
12944 * update the the output configuration. */
12945 intel_modeset_update_state(state);
12946
12947 /* The state has been swaped above, so state actually contains the
12948 * old state now. */
12949
12950 modeset_update_crtc_power_domains(state);
12951
12952 drm_atomic_helper_commit_planes(dev, state);
12953
12954 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12955 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12956 if (!needs_modeset(crtc->state) || !crtc->state->active)
12957 continue;
12958
12959 update_scanline_offset(to_intel_crtc(crtc));
12960
12961 dev_priv->display.crtc_enable(crtc);
12962 intel_crtc_enable_planes(crtc);
12963 }
12964
12965 /* FIXME: add subpixel order */
12966
12967 drm_atomic_helper_cleanup_planes(dev, state);
12968
12969 drm_atomic_state_free(state);
12970
12971 return 0;
12972}
12973
12974static int intel_set_mode_checked(struct drm_atomic_state *state)
12975{
12976 struct drm_device *dev = state->dev;
12977 int ret;
12978
12979 ret = __intel_set_mode(state);
12980 if (ret == 0)
12981 intel_modeset_check_state(dev);
12982
12983 return ret;
12984}
12985
12986static int intel_set_mode(struct drm_atomic_state *state)
12987{
12988 int ret;
12989
12990 ret = intel_modeset_compute_config(state);
12991 if (ret)
12992 return ret;
12993
12994 return intel_set_mode_checked(state);
12995}
12996
12997void intel_crtc_restore_mode(struct drm_crtc *crtc)
12998{
12999 struct drm_device *dev = crtc->dev;
13000 struct drm_atomic_state *state;
13001 struct intel_crtc *intel_crtc;
13002 struct intel_encoder *encoder;
13003 struct intel_connector *connector;
13004 struct drm_connector_state *connector_state;
13005 struct intel_crtc_state *crtc_state;
13006 int ret;
13007
13008 state = drm_atomic_state_alloc(dev);
13009 if (!state) {
13010 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13011 crtc->base.id);
13012 return;
13013 }
13014
13015 state->acquire_ctx = dev->mode_config.acquire_ctx;
13016
13017 /* The force restore path in the HW readout code relies on the staged
13018 * config still keeping the user requested config while the actual
13019 * state has been overwritten by the configuration read from HW. We
13020 * need to copy the staged config to the atomic state, otherwise the
13021 * mode set will just reapply the state the HW is already in. */
13022 for_each_intel_encoder(dev, encoder) {
13023 if (&encoder->new_crtc->base != crtc)
13024 continue;
13025
13026 for_each_intel_connector(dev, connector) {
13027 if (connector->new_encoder != encoder)
13028 continue;
13029
13030 connector_state = drm_atomic_get_connector_state(state, &connector->base);
13031 if (IS_ERR(connector_state)) {
13032 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13033 connector->base.base.id,
13034 connector->base.name,
13035 PTR_ERR(connector_state));
13036 continue;
13037 }
13038
13039 connector_state->crtc = crtc;
13040 connector_state->best_encoder = &encoder->base;
13041 }
13042 }
13043
13044 for_each_intel_crtc(dev, intel_crtc) {
13045 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
13046 continue;
13047
13048 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
13049 if (IS_ERR(crtc_state)) {
13050 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13051 intel_crtc->base.base.id,
13052 PTR_ERR(crtc_state));
13053 continue;
13054 }
13055
13056 crtc_state->base.active = crtc_state->base.enable =
13057 intel_crtc->new_enabled;
13058
13059 if (&intel_crtc->base == crtc)
13060 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
13061 }
13062
13063 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13064 crtc->primary->fb, crtc->x, crtc->y);
13065
13066 ret = intel_set_mode(state);
13067 if (ret)
13068 drm_atomic_state_free(state);
13069}
13070
13071#undef for_each_intel_crtc_masked
13072
13073static bool intel_connector_in_mode_set(struct intel_connector *connector,
13074 struct drm_mode_set *set)
13075{
13076 int ro;
13077
13078 for (ro = 0; ro < set->num_connectors; ro++)
13079 if (set->connectors[ro] == &connector->base)
13080 return true;
13081
13082 return false;
13083}
13084
13085static int
13086intel_modeset_stage_output_state(struct drm_device *dev,
13087 struct drm_mode_set *set,
13088 struct drm_atomic_state *state)
13089{
13090 struct intel_connector *connector;
13091 struct drm_connector *drm_connector;
13092 struct drm_connector_state *connector_state;
13093 struct drm_crtc *crtc;
13094 struct drm_crtc_state *crtc_state;
13095 int i, ret;
13096
13097 /* The upper layers ensure that we either disable a crtc or have a list
13098 * of connectors. For paranoia, double-check this. */
13099 WARN_ON(!set->fb && (set->num_connectors != 0));
13100 WARN_ON(set->fb && (set->num_connectors == 0));
13101
13102 for_each_intel_connector(dev, connector) {
13103 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13104
13105 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13106 continue;
13107
13108 connector_state =
13109 drm_atomic_get_connector_state(state, &connector->base);
13110 if (IS_ERR(connector_state))
13111 return PTR_ERR(connector_state);
13112
13113 if (in_mode_set) {
13114 int pipe = to_intel_crtc(set->crtc)->pipe;
13115 connector_state->best_encoder =
13116 &intel_find_encoder(connector, pipe)->base;
13117 }
13118
13119 if (connector->base.state->crtc != set->crtc)
13120 continue;
13121
13122 /* If we disable the crtc, disable all its connectors. Also, if
13123 * the connector is on the changing crtc but not on the new
13124 * connector list, disable it. */
13125 if (!set->fb || !in_mode_set) {
13126 connector_state->best_encoder = NULL;
13127
13128 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13129 connector->base.base.id,
13130 connector->base.name);
13131 }
13132 }
13133 /* connector->new_encoder is now updated for all connectors. */
13134
13135 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13136 connector = to_intel_connector(drm_connector);
13137
13138 if (!connector_state->best_encoder) {
13139 ret = drm_atomic_set_crtc_for_connector(connector_state,
13140 NULL);
13141 if (ret)
13142 return ret;
13143
13144 continue;
13145 }
13146
13147 if (intel_connector_in_mode_set(connector, set)) {
13148 struct drm_crtc *crtc = connector->base.state->crtc;
13149
13150 /* If this connector was in a previous crtc, add it
13151 * to the state. We might need to disable it. */
13152 if (crtc) {
13153 crtc_state =
13154 drm_atomic_get_crtc_state(state, crtc);
13155 if (IS_ERR(crtc_state))
13156 return PTR_ERR(crtc_state);
13157 }
13158
13159 ret = drm_atomic_set_crtc_for_connector(connector_state,
13160 set->crtc);
13161 if (ret)
13162 return ret;
13163 }
13164
13165 /* Make sure the new CRTC will work with the encoder */
13166 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13167 connector_state->crtc)) {
13168 return -EINVAL;
13169 }
13170
13171 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13172 connector->base.base.id,
13173 connector->base.name,
13174 connector_state->crtc->base.id);
13175
13176 if (connector_state->best_encoder != &connector->encoder->base)
13177 connector->encoder =
13178 to_intel_encoder(connector_state->best_encoder);
13179 }
13180
13181 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13182 bool has_connectors;
13183
13184 ret = drm_atomic_add_affected_connectors(state, crtc);
13185 if (ret)
13186 return ret;
13187
13188 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13189 if (has_connectors != crtc_state->enable)
13190 crtc_state->enable =
13191 crtc_state->active = has_connectors;
13192 }
13193
13194 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13195 set->fb, set->x, set->y);
13196 if (ret)
13197 return ret;
13198
13199 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13200 if (IS_ERR(crtc_state))
13201 return PTR_ERR(crtc_state);
13202
13203 if (set->mode)
13204 drm_mode_copy(&crtc_state->mode, set->mode);
13205
13206 if (set->num_connectors)
13207 crtc_state->active = true;
13208
13209 return 0;
13210}
13211
13212static int intel_crtc_set_config(struct drm_mode_set *set)
13213{
13214 struct drm_device *dev;
13215 struct drm_atomic_state *state = NULL;
13216 int ret;
13217
13218 BUG_ON(!set);
13219 BUG_ON(!set->crtc);
13220 BUG_ON(!set->crtc->helper_private);
13221
13222 /* Enforce sane interface api - has been abused by the fb helper. */
13223 BUG_ON(!set->mode && set->fb);
13224 BUG_ON(set->fb && set->num_connectors == 0);
13225
13226 if (set->fb) {
13227 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13228 set->crtc->base.id, set->fb->base.id,
13229 (int)set->num_connectors, set->x, set->y);
13230 } else {
13231 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
13232 }
13233
13234 dev = set->crtc->dev;
13235
13236 state = drm_atomic_state_alloc(dev);
13237 if (!state)
13238 return -ENOMEM;
13239
13240 state->acquire_ctx = dev->mode_config.acquire_ctx;
13241
13242 ret = intel_modeset_stage_output_state(dev, set, state);
13243 if (ret)
13244 goto out;
13245
13246 ret = intel_modeset_compute_config(state);
13247 if (ret)
13248 goto out;
13249
13250 intel_update_pipe_size(to_intel_crtc(set->crtc));
13251
13252 ret = intel_set_mode_checked(state);
13253 if (ret) {
13254 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13255 set->crtc->base.id, ret);
13256 }
13257
13258out:
13259 if (ret)
13260 drm_atomic_state_free(state);
13261 return ret;
13262}
13263
13264static const struct drm_crtc_funcs intel_crtc_funcs = {
13265 .gamma_set = intel_crtc_gamma_set,
13266 .set_config = intel_crtc_set_config,
13267 .destroy = intel_crtc_destroy,
13268 .page_flip = intel_crtc_page_flip,
13269 .atomic_duplicate_state = intel_crtc_duplicate_state,
13270 .atomic_destroy_state = intel_crtc_destroy_state,
13271};
13272
13273static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13274 struct intel_shared_dpll *pll,
13275 struct intel_dpll_hw_state *hw_state)
13276{
13277 uint32_t val;
13278
13279 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13280 return false;
13281
13282 val = I915_READ(PCH_DPLL(pll->id));
13283 hw_state->dpll = val;
13284 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13285 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13286
13287 return val & DPLL_VCO_ENABLE;
13288}
13289
13290static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13291 struct intel_shared_dpll *pll)
13292{
13293 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13294 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13295}
13296
13297static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13298 struct intel_shared_dpll *pll)
13299{
13300 /* PCH refclock must be enabled first */
13301 ibx_assert_pch_refclk_enabled(dev_priv);
13302
13303 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13304
13305 /* Wait for the clocks to stabilize. */
13306 POSTING_READ(PCH_DPLL(pll->id));
13307 udelay(150);
13308
13309 /* The pixel multiplier can only be updated once the
13310 * DPLL is enabled and the clocks are stable.
13311 *
13312 * So write it again.
13313 */
13314 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13315 POSTING_READ(PCH_DPLL(pll->id));
13316 udelay(200);
13317}
13318
13319static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13320 struct intel_shared_dpll *pll)
13321{
13322 struct drm_device *dev = dev_priv->dev;
13323 struct intel_crtc *crtc;
13324
13325 /* Make sure no transcoder isn't still depending on us. */
13326 for_each_intel_crtc(dev, crtc) {
13327 if (intel_crtc_to_shared_dpll(crtc) == pll)
13328 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13329 }
13330
13331 I915_WRITE(PCH_DPLL(pll->id), 0);
13332 POSTING_READ(PCH_DPLL(pll->id));
13333 udelay(200);
13334}
13335
13336static char *ibx_pch_dpll_names[] = {
13337 "PCH DPLL A",
13338 "PCH DPLL B",
13339};
13340
13341static void ibx_pch_dpll_init(struct drm_device *dev)
13342{
13343 struct drm_i915_private *dev_priv = dev->dev_private;
13344 int i;
13345
13346 dev_priv->num_shared_dpll = 2;
13347
13348 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13349 dev_priv->shared_dplls[i].id = i;
13350 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13351 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13352 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13353 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13354 dev_priv->shared_dplls[i].get_hw_state =
13355 ibx_pch_dpll_get_hw_state;
13356 }
13357}
13358
13359static void intel_shared_dpll_init(struct drm_device *dev)
13360{
13361 struct drm_i915_private *dev_priv = dev->dev_private;
13362
13363 intel_update_cdclk(dev);
13364
13365 if (HAS_DDI(dev))
13366 intel_ddi_pll_init(dev);
13367 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13368 ibx_pch_dpll_init(dev);
13369 else
13370 dev_priv->num_shared_dpll = 0;
13371
13372 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13373}
13374
13375/**
13376 * intel_wm_need_update - Check whether watermarks need updating
13377 * @plane: drm plane
13378 * @state: new plane state
13379 *
13380 * Check current plane state versus the new one to determine whether
13381 * watermarks need to be recalculated.
13382 *
13383 * Returns true or false.
13384 */
13385bool intel_wm_need_update(struct drm_plane *plane,
13386 struct drm_plane_state *state)
13387{
13388 /* Update watermarks on tiling changes. */
13389 if (!plane->state->fb || !state->fb ||
13390 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13391 plane->state->rotation != state->rotation)
13392 return true;
13393
13394 return false;
13395}
13396
13397/**
13398 * intel_prepare_plane_fb - Prepare fb for usage on plane
13399 * @plane: drm plane to prepare for
13400 * @fb: framebuffer to prepare for presentation
13401 *
13402 * Prepares a framebuffer for usage on a display plane. Generally this
13403 * involves pinning the underlying object and updating the frontbuffer tracking
13404 * bits. Some older platforms need special physical address handling for
13405 * cursor planes.
13406 *
13407 * Returns 0 on success, negative error code on failure.
13408 */
13409int
13410intel_prepare_plane_fb(struct drm_plane *plane,
13411 struct drm_framebuffer *fb,
13412 const struct drm_plane_state *new_state)
13413{
13414 struct drm_device *dev = plane->dev;
13415 struct intel_plane *intel_plane = to_intel_plane(plane);
13416 enum pipe pipe = intel_plane->pipe;
13417 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13418 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13419 unsigned frontbuffer_bits = 0;
13420 int ret = 0;
13421
13422 if (!obj)
13423 return 0;
13424
13425 switch (plane->type) {
13426 case DRM_PLANE_TYPE_PRIMARY:
13427 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13428 break;
13429 case DRM_PLANE_TYPE_CURSOR:
13430 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13431 break;
13432 case DRM_PLANE_TYPE_OVERLAY:
13433 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13434 break;
13435 }
13436
13437 mutex_lock(&dev->struct_mutex);
13438
13439 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13440 INTEL_INFO(dev)->cursor_needs_physical) {
13441 int align = IS_I830(dev) ? 16 * 1024 : 256;
13442 ret = i915_gem_object_attach_phys(obj, align);
13443 if (ret)
13444 DRM_DEBUG_KMS("failed to attach phys object\n");
13445 } else {
13446 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
13447 }
13448
13449 if (ret == 0)
13450 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
13451
13452 mutex_unlock(&dev->struct_mutex);
13453
13454 return ret;
13455}
13456
13457/**
13458 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13459 * @plane: drm plane to clean up for
13460 * @fb: old framebuffer that was on plane
13461 *
13462 * Cleans up a framebuffer that has just been removed from a plane.
13463 */
13464void
13465intel_cleanup_plane_fb(struct drm_plane *plane,
13466 struct drm_framebuffer *fb,
13467 const struct drm_plane_state *old_state)
13468{
13469 struct drm_device *dev = plane->dev;
13470 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13471
13472 if (WARN_ON(!obj))
13473 return;
13474
13475 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13476 !INTEL_INFO(dev)->cursor_needs_physical) {
13477 mutex_lock(&dev->struct_mutex);
13478 intel_unpin_fb_obj(fb, old_state);
13479 mutex_unlock(&dev->struct_mutex);
13480 }
13481}
13482
13483int
13484skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13485{
13486 int max_scale;
13487 struct drm_device *dev;
13488 struct drm_i915_private *dev_priv;
13489 int crtc_clock, cdclk;
13490
13491 if (!intel_crtc || !crtc_state)
13492 return DRM_PLANE_HELPER_NO_SCALING;
13493
13494 dev = intel_crtc->base.dev;
13495 dev_priv = dev->dev_private;
13496 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13497 cdclk = dev_priv->display.get_display_clock_speed(dev);
13498
13499 if (!crtc_clock || !cdclk)
13500 return DRM_PLANE_HELPER_NO_SCALING;
13501
13502 /*
13503 * skl max scale is lower of:
13504 * close to 3 but not 3, -1 is for that purpose
13505 * or
13506 * cdclk/crtc_clock
13507 */
13508 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13509
13510 return max_scale;
13511}
13512
13513static int
13514intel_check_primary_plane(struct drm_plane *plane,
13515 struct intel_plane_state *state)
13516{
13517 struct drm_device *dev = plane->dev;
13518 struct drm_i915_private *dev_priv = dev->dev_private;
13519 struct drm_crtc *crtc = state->base.crtc;
13520 struct intel_crtc *intel_crtc;
13521 struct intel_crtc_state *crtc_state;
13522 struct drm_framebuffer *fb = state->base.fb;
13523 struct drm_rect *dest = &state->dst;
13524 struct drm_rect *src = &state->src;
13525 const struct drm_rect *clip = &state->clip;
13526 bool can_position = false;
13527 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13528 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13529 int ret;
13530
13531 crtc = crtc ? crtc : plane->crtc;
13532 intel_crtc = to_intel_crtc(crtc);
13533 crtc_state = state->base.state ?
13534 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
13535
13536 if (INTEL_INFO(dev)->gen >= 9) {
13537 /* use scaler when colorkey is not required */
13538 if (to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) {
13539 min_scale = 1;
13540 max_scale = skl_max_scale(intel_crtc, crtc_state);
13541 }
13542 can_position = true;
13543 }
13544
13545 ret = drm_plane_helper_check_update(plane, crtc, fb,
13546 src, dest, clip,
13547 min_scale,
13548 max_scale,
13549 can_position, true,
13550 &state->visible);
13551 if (ret)
13552 return ret;
13553
13554 if (intel_crtc->active) {
13555 struct intel_plane_state *old_state =
13556 to_intel_plane_state(plane->state);
13557
13558 intel_crtc->atomic.wait_for_flips = true;
13559
13560 /*
13561 * FBC does not work on some platforms for rotated
13562 * planes, so disable it when rotation is not 0 and
13563 * update it when rotation is set back to 0.
13564 *
13565 * FIXME: This is redundant with the fbc update done in
13566 * the primary plane enable function except that that
13567 * one is done too late. We eventually need to unify
13568 * this.
13569 */
13570 if (state->visible &&
13571 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
13572 dev_priv->fbc.crtc == intel_crtc &&
13573 state->base.rotation != BIT(DRM_ROTATE_0)) {
13574 intel_crtc->atomic.disable_fbc = true;
13575 }
13576
13577 if (state->visible && !old_state->visible) {
13578 /*
13579 * BDW signals flip done immediately if the plane
13580 * is disabled, even if the plane enable is already
13581 * armed to occur at the next vblank :(
13582 */
13583 if (IS_BROADWELL(dev))
13584 intel_crtc->atomic.wait_vblank = true;
13585
13586 if (crtc_state && !needs_modeset(&crtc_state->base))
13587 intel_crtc->atomic.post_enable_primary = true;
13588 }
13589
13590 if (!state->visible && old_state->visible &&
13591 crtc_state && !needs_modeset(&crtc_state->base))
13592 intel_crtc->atomic.pre_disable_primary = true;
13593
13594 intel_crtc->atomic.fb_bits |=
13595 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13596
13597 intel_crtc->atomic.update_fbc = true;
13598
13599 if (intel_wm_need_update(plane, &state->base))
13600 intel_crtc->atomic.update_wm = true;
13601 }
13602
13603 if (INTEL_INFO(dev)->gen >= 9) {
13604 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13605 to_intel_plane(plane), state, 0);
13606 if (ret)
13607 return ret;
13608 }
13609
13610 return 0;
13611}
13612
13613static void
13614intel_commit_primary_plane(struct drm_plane *plane,
13615 struct intel_plane_state *state)
13616{
13617 struct drm_crtc *crtc = state->base.crtc;
13618 struct drm_framebuffer *fb = state->base.fb;
13619 struct drm_device *dev = plane->dev;
13620 struct drm_i915_private *dev_priv = dev->dev_private;
13621 struct intel_crtc *intel_crtc;
13622 struct drm_rect *src = &state->src;
13623
13624 crtc = crtc ? crtc : plane->crtc;
13625 intel_crtc = to_intel_crtc(crtc);
13626
13627 plane->fb = fb;
13628 crtc->x = src->x1 >> 16;
13629 crtc->y = src->y1 >> 16;
13630
13631 if (intel_crtc->active) {
13632 if (state->visible)
13633 /* FIXME: kill this fastboot hack */
13634 intel_update_pipe_size(intel_crtc);
13635
13636 dev_priv->display.update_primary_plane(crtc, plane->fb,
13637 crtc->x, crtc->y);
13638 }
13639}
13640
13641static void
13642intel_disable_primary_plane(struct drm_plane *plane,
13643 struct drm_crtc *crtc,
13644 bool force)
13645{
13646 struct drm_device *dev = plane->dev;
13647 struct drm_i915_private *dev_priv = dev->dev_private;
13648
13649 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13650}
13651
13652static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13653{
13654 struct drm_device *dev = crtc->dev;
13655 struct drm_i915_private *dev_priv = dev->dev_private;
13656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13657 struct intel_plane *intel_plane;
13658 struct drm_plane *p;
13659 unsigned fb_bits = 0;
13660
13661 /* Track fb's for any planes being disabled */
13662 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13663 intel_plane = to_intel_plane(p);
13664
13665 if (intel_crtc->atomic.disabled_planes &
13666 (1 << drm_plane_index(p))) {
13667 switch (p->type) {
13668 case DRM_PLANE_TYPE_PRIMARY:
13669 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13670 break;
13671 case DRM_PLANE_TYPE_CURSOR:
13672 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13673 break;
13674 case DRM_PLANE_TYPE_OVERLAY:
13675 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13676 break;
13677 }
13678
13679 mutex_lock(&dev->struct_mutex);
13680 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13681 mutex_unlock(&dev->struct_mutex);
13682 }
13683 }
13684
13685 if (intel_crtc->atomic.wait_for_flips)
13686 intel_crtc_wait_for_pending_flips(crtc);
13687
13688 if (intel_crtc->atomic.disable_fbc)
13689 intel_fbc_disable(dev);
13690
13691 if (intel_crtc->atomic.pre_disable_primary)
13692 intel_pre_disable_primary(crtc);
13693
13694 if (intel_crtc->atomic.update_wm)
13695 intel_update_watermarks(crtc);
13696
13697 intel_runtime_pm_get(dev_priv);
13698
13699 /* Perform vblank evasion around commit operation */
13700 if (intel_crtc->active)
13701 intel_crtc->atomic.evade =
13702 intel_pipe_update_start(intel_crtc,
13703 &intel_crtc->atomic.start_vbl_count);
13704}
13705
13706static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13707{
13708 struct drm_device *dev = crtc->dev;
13709 struct drm_i915_private *dev_priv = dev->dev_private;
13710 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13711 struct drm_plane *p;
13712
13713 if (intel_crtc->atomic.evade)
13714 intel_pipe_update_end(intel_crtc,
13715 intel_crtc->atomic.start_vbl_count);
13716
13717 intel_runtime_pm_put(dev_priv);
13718
13719 if (intel_crtc->atomic.wait_vblank && intel_crtc->active)
13720 intel_wait_for_vblank(dev, intel_crtc->pipe);
13721
13722 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13723
13724 if (intel_crtc->atomic.update_fbc) {
13725 mutex_lock(&dev->struct_mutex);
13726 intel_fbc_update(dev);
13727 mutex_unlock(&dev->struct_mutex);
13728 }
13729
13730 if (intel_crtc->atomic.post_enable_primary)
13731 intel_post_enable_primary(crtc);
13732
13733 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13734 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13735 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13736 false, false);
13737
13738 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
13739}
13740
13741/**
13742 * intel_plane_destroy - destroy a plane
13743 * @plane: plane to destroy
13744 *
13745 * Common destruction function for all types of planes (primary, cursor,
13746 * sprite).
13747 */
13748void intel_plane_destroy(struct drm_plane *plane)
13749{
13750 struct intel_plane *intel_plane = to_intel_plane(plane);
13751 drm_plane_cleanup(plane);
13752 kfree(intel_plane);
13753}
13754
13755const struct drm_plane_funcs intel_plane_funcs = {
13756 .update_plane = drm_atomic_helper_update_plane,
13757 .disable_plane = drm_atomic_helper_disable_plane,
13758 .destroy = intel_plane_destroy,
13759 .set_property = drm_atomic_helper_plane_set_property,
13760 .atomic_get_property = intel_plane_atomic_get_property,
13761 .atomic_set_property = intel_plane_atomic_set_property,
13762 .atomic_duplicate_state = intel_plane_duplicate_state,
13763 .atomic_destroy_state = intel_plane_destroy_state,
13764
13765};
13766
13767static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13768 int pipe)
13769{
13770 struct intel_plane *primary;
13771 struct intel_plane_state *state;
13772 const uint32_t *intel_primary_formats;
13773 int num_formats;
13774
13775 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13776 if (primary == NULL)
13777 return NULL;
13778
13779 state = intel_create_plane_state(&primary->base);
13780 if (!state) {
13781 kfree(primary);
13782 return NULL;
13783 }
13784 primary->base.state = &state->base;
13785
13786 primary->can_scale = false;
13787 primary->max_downscale = 1;
13788 if (INTEL_INFO(dev)->gen >= 9) {
13789 primary->can_scale = true;
13790 state->scaler_id = -1;
13791 }
13792 primary->pipe = pipe;
13793 primary->plane = pipe;
13794 primary->check_plane = intel_check_primary_plane;
13795 primary->commit_plane = intel_commit_primary_plane;
13796 primary->disable_plane = intel_disable_primary_plane;
13797 primary->ckey.flags = I915_SET_COLORKEY_NONE;
13798 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13799 primary->plane = !pipe;
13800
13801 if (INTEL_INFO(dev)->gen >= 9) {
13802 intel_primary_formats = skl_primary_formats;
13803 num_formats = ARRAY_SIZE(skl_primary_formats);
13804 } else if (INTEL_INFO(dev)->gen >= 4) {
13805 intel_primary_formats = i965_primary_formats;
13806 num_formats = ARRAY_SIZE(i965_primary_formats);
13807 } else {
13808 intel_primary_formats = i8xx_primary_formats;
13809 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13810 }
13811
13812 drm_universal_plane_init(dev, &primary->base, 0,
13813 &intel_plane_funcs,
13814 intel_primary_formats, num_formats,
13815 DRM_PLANE_TYPE_PRIMARY);
13816
13817 if (INTEL_INFO(dev)->gen >= 4)
13818 intel_create_rotation_property(dev, primary);
13819
13820 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13821
13822 return &primary->base;
13823}
13824
13825void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13826{
13827 if (!dev->mode_config.rotation_property) {
13828 unsigned long flags = BIT(DRM_ROTATE_0) |
13829 BIT(DRM_ROTATE_180);
13830
13831 if (INTEL_INFO(dev)->gen >= 9)
13832 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13833
13834 dev->mode_config.rotation_property =
13835 drm_mode_create_rotation_property(dev, flags);
13836 }
13837 if (dev->mode_config.rotation_property)
13838 drm_object_attach_property(&plane->base.base,
13839 dev->mode_config.rotation_property,
13840 plane->base.state->rotation);
13841}
13842
13843static int
13844intel_check_cursor_plane(struct drm_plane *plane,
13845 struct intel_plane_state *state)
13846{
13847 struct drm_crtc *crtc = state->base.crtc;
13848 struct drm_device *dev = plane->dev;
13849 struct drm_framebuffer *fb = state->base.fb;
13850 struct drm_rect *dest = &state->dst;
13851 struct drm_rect *src = &state->src;
13852 const struct drm_rect *clip = &state->clip;
13853 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13854 struct intel_crtc *intel_crtc;
13855 unsigned stride;
13856 int ret;
13857
13858 crtc = crtc ? crtc : plane->crtc;
13859 intel_crtc = to_intel_crtc(crtc);
13860
13861 ret = drm_plane_helper_check_update(plane, crtc, fb,
13862 src, dest, clip,
13863 DRM_PLANE_HELPER_NO_SCALING,
13864 DRM_PLANE_HELPER_NO_SCALING,
13865 true, true, &state->visible);
13866 if (ret)
13867 return ret;
13868
13869
13870 /* if we want to turn off the cursor ignore width and height */
13871 if (!obj)
13872 goto finish;
13873
13874 /* Check for which cursor types we support */
13875 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13876 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13877 state->base.crtc_w, state->base.crtc_h);
13878 return -EINVAL;
13879 }
13880
13881 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13882 if (obj->base.size < stride * state->base.crtc_h) {
13883 DRM_DEBUG_KMS("buffer is too small\n");
13884 return -ENOMEM;
13885 }
13886
13887 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13888 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13889 ret = -EINVAL;
13890 }
13891
13892finish:
13893 if (intel_crtc->active) {
13894 if (plane->state->crtc_w != state->base.crtc_w)
13895 intel_crtc->atomic.update_wm = true;
13896
13897 intel_crtc->atomic.fb_bits |=
13898 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13899 }
13900
13901 return ret;
13902}
13903
13904static void
13905intel_disable_cursor_plane(struct drm_plane *plane,
13906 struct drm_crtc *crtc,
13907 bool force)
13908{
13909 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13910
13911 if (!force) {
13912 plane->fb = NULL;
13913 intel_crtc->cursor_bo = NULL;
13914 intel_crtc->cursor_addr = 0;
13915 }
13916
13917 intel_crtc_update_cursor(crtc, false);
13918}
13919
13920static void
13921intel_commit_cursor_plane(struct drm_plane *plane,
13922 struct intel_plane_state *state)
13923{
13924 struct drm_crtc *crtc = state->base.crtc;
13925 struct drm_device *dev = plane->dev;
13926 struct intel_crtc *intel_crtc;
13927 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13928 uint32_t addr;
13929
13930 crtc = crtc ? crtc : plane->crtc;
13931 intel_crtc = to_intel_crtc(crtc);
13932
13933 plane->fb = state->base.fb;
13934 crtc->cursor_x = state->base.crtc_x;
13935 crtc->cursor_y = state->base.crtc_y;
13936
13937 if (intel_crtc->cursor_bo == obj)
13938 goto update;
13939
13940 if (!obj)
13941 addr = 0;
13942 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13943 addr = i915_gem_obj_ggtt_offset(obj);
13944 else
13945 addr = obj->phys_handle->busaddr;
13946
13947 intel_crtc->cursor_addr = addr;
13948 intel_crtc->cursor_bo = obj;
13949update:
13950
13951 if (intel_crtc->active)
13952 intel_crtc_update_cursor(crtc, state->visible);
13953}
13954
13955static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13956 int pipe)
13957{
13958 struct intel_plane *cursor;
13959 struct intel_plane_state *state;
13960
13961 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13962 if (cursor == NULL)
13963 return NULL;
13964
13965 state = intel_create_plane_state(&cursor->base);
13966 if (!state) {
13967 kfree(cursor);
13968 return NULL;
13969 }
13970 cursor->base.state = &state->base;
13971
13972 cursor->can_scale = false;
13973 cursor->max_downscale = 1;
13974 cursor->pipe = pipe;
13975 cursor->plane = pipe;
13976 cursor->check_plane = intel_check_cursor_plane;
13977 cursor->commit_plane = intel_commit_cursor_plane;
13978 cursor->disable_plane = intel_disable_cursor_plane;
13979
13980 drm_universal_plane_init(dev, &cursor->base, 0,
13981 &intel_plane_funcs,
13982 intel_cursor_formats,
13983 ARRAY_SIZE(intel_cursor_formats),
13984 DRM_PLANE_TYPE_CURSOR);
13985
13986 if (INTEL_INFO(dev)->gen >= 4) {
13987 if (!dev->mode_config.rotation_property)
13988 dev->mode_config.rotation_property =
13989 drm_mode_create_rotation_property(dev,
13990 BIT(DRM_ROTATE_0) |
13991 BIT(DRM_ROTATE_180));
13992 if (dev->mode_config.rotation_property)
13993 drm_object_attach_property(&cursor->base.base,
13994 dev->mode_config.rotation_property,
13995 state->base.rotation);
13996 }
13997
13998 if (INTEL_INFO(dev)->gen >=9)
13999 state->scaler_id = -1;
14000
14001 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14002
14003 return &cursor->base;
14004}
14005
14006static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14007 struct intel_crtc_state *crtc_state)
14008{
14009 int i;
14010 struct intel_scaler *intel_scaler;
14011 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14012
14013 for (i = 0; i < intel_crtc->num_scalers; i++) {
14014 intel_scaler = &scaler_state->scalers[i];
14015 intel_scaler->in_use = 0;
14016 intel_scaler->id = i;
14017
14018 intel_scaler->mode = PS_SCALER_MODE_DYN;
14019 }
14020
14021 scaler_state->scaler_id = -1;
14022}
14023
14024static void intel_crtc_init(struct drm_device *dev, int pipe)
14025{
14026 struct drm_i915_private *dev_priv = dev->dev_private;
14027 struct intel_crtc *intel_crtc;
14028 struct intel_crtc_state *crtc_state = NULL;
14029 struct drm_plane *primary = NULL;
14030 struct drm_plane *cursor = NULL;
14031 int i, ret;
14032
14033 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14034 if (intel_crtc == NULL)
14035 return;
14036
14037 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14038 if (!crtc_state)
14039 goto fail;
14040 intel_crtc->config = crtc_state;
14041 intel_crtc->base.state = &crtc_state->base;
14042 crtc_state->base.crtc = &intel_crtc->base;
14043
14044 /* initialize shared scalers */
14045 if (INTEL_INFO(dev)->gen >= 9) {
14046 if (pipe == PIPE_C)
14047 intel_crtc->num_scalers = 1;
14048 else
14049 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14050
14051 skl_init_scalers(dev, intel_crtc, crtc_state);
14052 }
14053
14054 primary = intel_primary_plane_create(dev, pipe);
14055 if (!primary)
14056 goto fail;
14057
14058 cursor = intel_cursor_plane_create(dev, pipe);
14059 if (!cursor)
14060 goto fail;
14061
14062 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14063 cursor, &intel_crtc_funcs);
14064 if (ret)
14065 goto fail;
14066
14067 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14068 for (i = 0; i < 256; i++) {
14069 intel_crtc->lut_r[i] = i;
14070 intel_crtc->lut_g[i] = i;
14071 intel_crtc->lut_b[i] = i;
14072 }
14073
14074 /*
14075 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14076 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14077 */
14078 intel_crtc->pipe = pipe;
14079 intel_crtc->plane = pipe;
14080 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14081 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14082 intel_crtc->plane = !pipe;
14083 }
14084
14085 intel_crtc->cursor_base = ~0;
14086 intel_crtc->cursor_cntl = ~0;
14087 intel_crtc->cursor_size = ~0;
14088
14089 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14090 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14091 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14092 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14093
14094 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14095
14096 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14097 return;
14098
14099fail:
14100 if (primary)
14101 drm_plane_cleanup(primary);
14102 if (cursor)
14103 drm_plane_cleanup(cursor);
14104 kfree(crtc_state);
14105 kfree(intel_crtc);
14106}
14107
14108enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14109{
14110 struct drm_encoder *encoder = connector->base.encoder;
14111 struct drm_device *dev = connector->base.dev;
14112
14113 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14114
14115 if (!encoder || WARN_ON(!encoder->crtc))
14116 return INVALID_PIPE;
14117
14118 return to_intel_crtc(encoder->crtc)->pipe;
14119}
14120
14121int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14122 struct drm_file *file)
14123{
14124 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14125 struct drm_crtc *drmmode_crtc;
14126 struct intel_crtc *crtc;
14127
14128 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14129
14130 if (!drmmode_crtc) {
14131 DRM_ERROR("no such CRTC id\n");
14132 return -ENOENT;
14133 }
14134
14135 crtc = to_intel_crtc(drmmode_crtc);
14136 pipe_from_crtc_id->pipe = crtc->pipe;
14137
14138 return 0;
14139}
14140
14141static int intel_encoder_clones(struct intel_encoder *encoder)
14142{
14143 struct drm_device *dev = encoder->base.dev;
14144 struct intel_encoder *source_encoder;
14145 int index_mask = 0;
14146 int entry = 0;
14147
14148 for_each_intel_encoder(dev, source_encoder) {
14149 if (encoders_cloneable(encoder, source_encoder))
14150 index_mask |= (1 << entry);
14151
14152 entry++;
14153 }
14154
14155 return index_mask;
14156}
14157
14158static bool has_edp_a(struct drm_device *dev)
14159{
14160 struct drm_i915_private *dev_priv = dev->dev_private;
14161
14162 if (!IS_MOBILE(dev))
14163 return false;
14164
14165 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14166 return false;
14167
14168 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14169 return false;
14170
14171 return true;
14172}
14173
14174static bool intel_crt_present(struct drm_device *dev)
14175{
14176 struct drm_i915_private *dev_priv = dev->dev_private;
14177
14178 if (INTEL_INFO(dev)->gen >= 9)
14179 return false;
14180
14181 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14182 return false;
14183
14184 if (IS_CHERRYVIEW(dev))
14185 return false;
14186
14187 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14188 return false;
14189
14190 return true;
14191}
14192
14193static void intel_setup_outputs(struct drm_device *dev)
14194{
14195 struct drm_i915_private *dev_priv = dev->dev_private;
14196 struct intel_encoder *encoder;
14197 bool dpd_is_edp = false;
14198
14199 intel_lvds_init(dev);
14200
14201 if (intel_crt_present(dev))
14202 intel_crt_init(dev);
14203
14204 if (IS_BROXTON(dev)) {
14205 /*
14206 * FIXME: Broxton doesn't support port detection via the
14207 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14208 * detect the ports.
14209 */
14210 intel_ddi_init(dev, PORT_A);
14211 intel_ddi_init(dev, PORT_B);
14212 intel_ddi_init(dev, PORT_C);
14213 } else if (HAS_DDI(dev)) {
14214 int found;
14215
14216 /*
14217 * Haswell uses DDI functions to detect digital outputs.
14218 * On SKL pre-D0 the strap isn't connected, so we assume
14219 * it's there.
14220 */
14221 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
14222 /* WaIgnoreDDIAStrap: skl */
14223 if (found ||
14224 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
14225 intel_ddi_init(dev, PORT_A);
14226
14227 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14228 * register */
14229 found = I915_READ(SFUSE_STRAP);
14230
14231 if (found & SFUSE_STRAP_DDIB_DETECTED)
14232 intel_ddi_init(dev, PORT_B);
14233 if (found & SFUSE_STRAP_DDIC_DETECTED)
14234 intel_ddi_init(dev, PORT_C);
14235 if (found & SFUSE_STRAP_DDID_DETECTED)
14236 intel_ddi_init(dev, PORT_D);
14237 } else if (HAS_PCH_SPLIT(dev)) {
14238 int found;
14239 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14240
14241 if (has_edp_a(dev))
14242 intel_dp_init(dev, DP_A, PORT_A);
14243
14244 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14245 /* PCH SDVOB multiplex with HDMIB */
14246 found = intel_sdvo_init(dev, PCH_SDVOB, true);
14247 if (!found)
14248 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14249 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14250 intel_dp_init(dev, PCH_DP_B, PORT_B);
14251 }
14252
14253 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14254 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14255
14256 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14257 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14258
14259 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14260 intel_dp_init(dev, PCH_DP_C, PORT_C);
14261
14262 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14263 intel_dp_init(dev, PCH_DP_D, PORT_D);
14264 } else if (IS_VALLEYVIEW(dev)) {
14265 /*
14266 * The DP_DETECTED bit is the latched state of the DDC
14267 * SDA pin at boot. However since eDP doesn't require DDC
14268 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14269 * eDP ports may have been muxed to an alternate function.
14270 * Thus we can't rely on the DP_DETECTED bit alone to detect
14271 * eDP ports. Consult the VBT as well as DP_DETECTED to
14272 * detect eDP ports.
14273 */
14274 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14275 !intel_dp_is_edp(dev, PORT_B))
14276 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14277 PORT_B);
14278 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14279 intel_dp_is_edp(dev, PORT_B))
14280 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14281
14282 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14283 !intel_dp_is_edp(dev, PORT_C))
14284 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14285 PORT_C);
14286 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14287 intel_dp_is_edp(dev, PORT_C))
14288 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14289
14290 if (IS_CHERRYVIEW(dev)) {
14291 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14292 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14293 PORT_D);
14294 /* eDP not supported on port D, so don't check VBT */
14295 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14296 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14297 }
14298
14299 intel_dsi_init(dev);
14300 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
14301 bool found = false;
14302
14303 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14304 DRM_DEBUG_KMS("probing SDVOB\n");
14305 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14306 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14307 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14308 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14309 }
14310
14311 if (!found && SUPPORTS_INTEGRATED_DP(dev))
14312 intel_dp_init(dev, DP_B, PORT_B);
14313 }
14314
14315 /* Before G4X SDVOC doesn't have its own detect register */
14316
14317 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14318 DRM_DEBUG_KMS("probing SDVOC\n");
14319 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14320 }
14321
14322 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14323
14324 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14325 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14326 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14327 }
14328 if (SUPPORTS_INTEGRATED_DP(dev))
14329 intel_dp_init(dev, DP_C, PORT_C);
14330 }
14331
14332 if (SUPPORTS_INTEGRATED_DP(dev) &&
14333 (I915_READ(DP_D) & DP_DETECTED))
14334 intel_dp_init(dev, DP_D, PORT_D);
14335 } else if (IS_GEN2(dev))
14336 intel_dvo_init(dev);
14337
14338 if (SUPPORTS_TV(dev))
14339 intel_tv_init(dev);
14340
14341 intel_psr_init(dev);
14342
14343 for_each_intel_encoder(dev, encoder) {
14344 encoder->base.possible_crtcs = encoder->crtc_mask;
14345 encoder->base.possible_clones =
14346 intel_encoder_clones(encoder);
14347 }
14348
14349 intel_init_pch_refclk(dev);
14350
14351 drm_helper_move_panel_connectors_to_head(dev);
14352}
14353
14354static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14355{
14356 struct drm_device *dev = fb->dev;
14357 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14358
14359 drm_framebuffer_cleanup(fb);
14360 mutex_lock(&dev->struct_mutex);
14361 WARN_ON(!intel_fb->obj->framebuffer_references--);
14362 drm_gem_object_unreference(&intel_fb->obj->base);
14363 mutex_unlock(&dev->struct_mutex);
14364 kfree(intel_fb);
14365}
14366
14367static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14368 struct drm_file *file,
14369 unsigned int *handle)
14370{
14371 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14372 struct drm_i915_gem_object *obj = intel_fb->obj;
14373
14374 return drm_gem_handle_create(file, &obj->base, handle);
14375}
14376
14377static const struct drm_framebuffer_funcs intel_fb_funcs = {
14378 .destroy = intel_user_framebuffer_destroy,
14379 .create_handle = intel_user_framebuffer_create_handle,
14380};
14381
14382static
14383u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14384 uint32_t pixel_format)
14385{
14386 u32 gen = INTEL_INFO(dev)->gen;
14387
14388 if (gen >= 9) {
14389 /* "The stride in bytes must not exceed the of the size of 8K
14390 * pixels and 32K bytes."
14391 */
14392 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14393 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14394 return 32*1024;
14395 } else if (gen >= 4) {
14396 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14397 return 16*1024;
14398 else
14399 return 32*1024;
14400 } else if (gen >= 3) {
14401 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14402 return 8*1024;
14403 else
14404 return 16*1024;
14405 } else {
14406 /* XXX DSPC is limited to 4k tiled */
14407 return 8*1024;
14408 }
14409}
14410
14411static int intel_framebuffer_init(struct drm_device *dev,
14412 struct intel_framebuffer *intel_fb,
14413 struct drm_mode_fb_cmd2 *mode_cmd,
14414 struct drm_i915_gem_object *obj)
14415{
14416 unsigned int aligned_height;
14417 int ret;
14418 u32 pitch_limit, stride_alignment;
14419
14420 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14421
14422 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14423 /* Enforce that fb modifier and tiling mode match, but only for
14424 * X-tiled. This is needed for FBC. */
14425 if (!!(obj->tiling_mode == I915_TILING_X) !=
14426 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14427 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14428 return -EINVAL;
14429 }
14430 } else {
14431 if (obj->tiling_mode == I915_TILING_X)
14432 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14433 else if (obj->tiling_mode == I915_TILING_Y) {
14434 DRM_DEBUG("No Y tiling for legacy addfb\n");
14435 return -EINVAL;
14436 }
14437 }
14438
14439 /* Passed in modifier sanity checking. */
14440 switch (mode_cmd->modifier[0]) {
14441 case I915_FORMAT_MOD_Y_TILED:
14442 case I915_FORMAT_MOD_Yf_TILED:
14443 if (INTEL_INFO(dev)->gen < 9) {
14444 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14445 mode_cmd->modifier[0]);
14446 return -EINVAL;
14447 }
14448 case DRM_FORMAT_MOD_NONE:
14449 case I915_FORMAT_MOD_X_TILED:
14450 break;
14451 default:
14452 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14453 mode_cmd->modifier[0]);
14454 return -EINVAL;
14455 }
14456
14457 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14458 mode_cmd->pixel_format);
14459 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14460 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14461 mode_cmd->pitches[0], stride_alignment);
14462 return -EINVAL;
14463 }
14464
14465 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14466 mode_cmd->pixel_format);
14467 if (mode_cmd->pitches[0] > pitch_limit) {
14468 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14469 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14470 "tiled" : "linear",
14471 mode_cmd->pitches[0], pitch_limit);
14472 return -EINVAL;
14473 }
14474
14475 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14476 mode_cmd->pitches[0] != obj->stride) {
14477 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14478 mode_cmd->pitches[0], obj->stride);
14479 return -EINVAL;
14480 }
14481
14482 /* Reject formats not supported by any plane early. */
14483 switch (mode_cmd->pixel_format) {
14484 case DRM_FORMAT_C8:
14485 case DRM_FORMAT_RGB565:
14486 case DRM_FORMAT_XRGB8888:
14487 case DRM_FORMAT_ARGB8888:
14488 break;
14489 case DRM_FORMAT_XRGB1555:
14490 if (INTEL_INFO(dev)->gen > 3) {
14491 DRM_DEBUG("unsupported pixel format: %s\n",
14492 drm_get_format_name(mode_cmd->pixel_format));
14493 return -EINVAL;
14494 }
14495 break;
14496 case DRM_FORMAT_ABGR8888:
14497 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14498 DRM_DEBUG("unsupported pixel format: %s\n",
14499 drm_get_format_name(mode_cmd->pixel_format));
14500 return -EINVAL;
14501 }
14502 break;
14503 case DRM_FORMAT_XBGR8888:
14504 case DRM_FORMAT_XRGB2101010:
14505 case DRM_FORMAT_XBGR2101010:
14506 if (INTEL_INFO(dev)->gen < 4) {
14507 DRM_DEBUG("unsupported pixel format: %s\n",
14508 drm_get_format_name(mode_cmd->pixel_format));
14509 return -EINVAL;
14510 }
14511 break;
14512 case DRM_FORMAT_ABGR2101010:
14513 if (!IS_VALLEYVIEW(dev)) {
14514 DRM_DEBUG("unsupported pixel format: %s\n",
14515 drm_get_format_name(mode_cmd->pixel_format));
14516 return -EINVAL;
14517 }
14518 break;
14519 case DRM_FORMAT_YUYV:
14520 case DRM_FORMAT_UYVY:
14521 case DRM_FORMAT_YVYU:
14522 case DRM_FORMAT_VYUY:
14523 if (INTEL_INFO(dev)->gen < 5) {
14524 DRM_DEBUG("unsupported pixel format: %s\n",
14525 drm_get_format_name(mode_cmd->pixel_format));
14526 return -EINVAL;
14527 }
14528 break;
14529 default:
14530 DRM_DEBUG("unsupported pixel format: %s\n",
14531 drm_get_format_name(mode_cmd->pixel_format));
14532 return -EINVAL;
14533 }
14534
14535 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14536 if (mode_cmd->offsets[0] != 0)
14537 return -EINVAL;
14538
14539 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14540 mode_cmd->pixel_format,
14541 mode_cmd->modifier[0]);
14542 /* FIXME drm helper for size checks (especially planar formats)? */
14543 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14544 return -EINVAL;
14545
14546 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14547 intel_fb->obj = obj;
14548 intel_fb->obj->framebuffer_references++;
14549
14550 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14551 if (ret) {
14552 DRM_ERROR("framebuffer init failed %d\n", ret);
14553 return ret;
14554 }
14555
14556 return 0;
14557}
14558
14559static struct drm_framebuffer *
14560intel_user_framebuffer_create(struct drm_device *dev,
14561 struct drm_file *filp,
14562 struct drm_mode_fb_cmd2 *mode_cmd)
14563{
14564 struct drm_i915_gem_object *obj;
14565
14566 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14567 mode_cmd->handles[0]));
14568 if (&obj->base == NULL)
14569 return ERR_PTR(-ENOENT);
14570
14571 return intel_framebuffer_create(dev, mode_cmd, obj);
14572}
14573
14574#ifndef CONFIG_DRM_I915_FBDEV
14575static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14576{
14577}
14578#endif
14579
14580static const struct drm_mode_config_funcs intel_mode_funcs = {
14581 .fb_create = intel_user_framebuffer_create,
14582 .output_poll_changed = intel_fbdev_output_poll_changed,
14583 .atomic_check = intel_atomic_check,
14584 .atomic_commit = intel_atomic_commit,
14585};
14586
14587/* Set up chip specific display functions */
14588static void intel_init_display(struct drm_device *dev)
14589{
14590 struct drm_i915_private *dev_priv = dev->dev_private;
14591
14592 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14593 dev_priv->display.find_dpll = g4x_find_best_dpll;
14594 else if (IS_CHERRYVIEW(dev))
14595 dev_priv->display.find_dpll = chv_find_best_dpll;
14596 else if (IS_VALLEYVIEW(dev))
14597 dev_priv->display.find_dpll = vlv_find_best_dpll;
14598 else if (IS_PINEVIEW(dev))
14599 dev_priv->display.find_dpll = pnv_find_best_dpll;
14600 else
14601 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14602
14603 if (INTEL_INFO(dev)->gen >= 9) {
14604 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14605 dev_priv->display.get_initial_plane_config =
14606 skylake_get_initial_plane_config;
14607 dev_priv->display.crtc_compute_clock =
14608 haswell_crtc_compute_clock;
14609 dev_priv->display.crtc_enable = haswell_crtc_enable;
14610 dev_priv->display.crtc_disable = haswell_crtc_disable;
14611 dev_priv->display.update_primary_plane =
14612 skylake_update_primary_plane;
14613 } else if (HAS_DDI(dev)) {
14614 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14615 dev_priv->display.get_initial_plane_config =
14616 ironlake_get_initial_plane_config;
14617 dev_priv->display.crtc_compute_clock =
14618 haswell_crtc_compute_clock;
14619 dev_priv->display.crtc_enable = haswell_crtc_enable;
14620 dev_priv->display.crtc_disable = haswell_crtc_disable;
14621 dev_priv->display.update_primary_plane =
14622 ironlake_update_primary_plane;
14623 } else if (HAS_PCH_SPLIT(dev)) {
14624 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14625 dev_priv->display.get_initial_plane_config =
14626 ironlake_get_initial_plane_config;
14627 dev_priv->display.crtc_compute_clock =
14628 ironlake_crtc_compute_clock;
14629 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14630 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14631 dev_priv->display.update_primary_plane =
14632 ironlake_update_primary_plane;
14633 } else if (IS_VALLEYVIEW(dev)) {
14634 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14635 dev_priv->display.get_initial_plane_config =
14636 i9xx_get_initial_plane_config;
14637 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14638 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14639 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14640 dev_priv->display.update_primary_plane =
14641 i9xx_update_primary_plane;
14642 } else {
14643 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14644 dev_priv->display.get_initial_plane_config =
14645 i9xx_get_initial_plane_config;
14646 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14647 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14648 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14649 dev_priv->display.update_primary_plane =
14650 i9xx_update_primary_plane;
14651 }
14652
14653 /* Returns the core display clock speed */
14654 if (IS_SKYLAKE(dev))
14655 dev_priv->display.get_display_clock_speed =
14656 skylake_get_display_clock_speed;
14657 else if (IS_BROADWELL(dev))
14658 dev_priv->display.get_display_clock_speed =
14659 broadwell_get_display_clock_speed;
14660 else if (IS_HASWELL(dev))
14661 dev_priv->display.get_display_clock_speed =
14662 haswell_get_display_clock_speed;
14663 else if (IS_VALLEYVIEW(dev))
14664 dev_priv->display.get_display_clock_speed =
14665 valleyview_get_display_clock_speed;
14666 else if (IS_GEN5(dev))
14667 dev_priv->display.get_display_clock_speed =
14668 ilk_get_display_clock_speed;
14669 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14670 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14671 dev_priv->display.get_display_clock_speed =
14672 i945_get_display_clock_speed;
14673 else if (IS_GM45(dev))
14674 dev_priv->display.get_display_clock_speed =
14675 gm45_get_display_clock_speed;
14676 else if (IS_CRESTLINE(dev))
14677 dev_priv->display.get_display_clock_speed =
14678 i965gm_get_display_clock_speed;
14679 else if (IS_PINEVIEW(dev))
14680 dev_priv->display.get_display_clock_speed =
14681 pnv_get_display_clock_speed;
14682 else if (IS_G33(dev) || IS_G4X(dev))
14683 dev_priv->display.get_display_clock_speed =
14684 g33_get_display_clock_speed;
14685 else if (IS_I915G(dev))
14686 dev_priv->display.get_display_clock_speed =
14687 i915_get_display_clock_speed;
14688 else if (IS_I945GM(dev) || IS_845G(dev))
14689 dev_priv->display.get_display_clock_speed =
14690 i9xx_misc_get_display_clock_speed;
14691 else if (IS_PINEVIEW(dev))
14692 dev_priv->display.get_display_clock_speed =
14693 pnv_get_display_clock_speed;
14694 else if (IS_I915GM(dev))
14695 dev_priv->display.get_display_clock_speed =
14696 i915gm_get_display_clock_speed;
14697 else if (IS_I865G(dev))
14698 dev_priv->display.get_display_clock_speed =
14699 i865_get_display_clock_speed;
14700 else if (IS_I85X(dev))
14701 dev_priv->display.get_display_clock_speed =
14702 i85x_get_display_clock_speed;
14703 else { /* 830 */
14704 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14705 dev_priv->display.get_display_clock_speed =
14706 i830_get_display_clock_speed;
14707 }
14708
14709 if (IS_GEN5(dev)) {
14710 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14711 } else if (IS_GEN6(dev)) {
14712 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14713 } else if (IS_IVYBRIDGE(dev)) {
14714 /* FIXME: detect B0+ stepping and use auto training */
14715 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14716 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14717 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14718 if (IS_BROADWELL(dev))
14719 dev_priv->display.modeset_global_resources =
14720 broadwell_modeset_global_resources;
14721 } else if (IS_VALLEYVIEW(dev)) {
14722 dev_priv->display.modeset_global_resources =
14723 valleyview_modeset_global_resources;
14724 } else if (IS_BROXTON(dev)) {
14725 dev_priv->display.modeset_global_resources =
14726 broxton_modeset_global_resources;
14727 }
14728
14729 switch (INTEL_INFO(dev)->gen) {
14730 case 2:
14731 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14732 break;
14733
14734 case 3:
14735 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14736 break;
14737
14738 case 4:
14739 case 5:
14740 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14741 break;
14742
14743 case 6:
14744 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14745 break;
14746 case 7:
14747 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14748 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14749 break;
14750 case 9:
14751 /* Drop through - unsupported since execlist only. */
14752 default:
14753 /* Default just returns -ENODEV to indicate unsupported */
14754 dev_priv->display.queue_flip = intel_default_queue_flip;
14755 }
14756
14757 intel_panel_init_backlight_funcs(dev);
14758
14759 mutex_init(&dev_priv->pps_mutex);
14760}
14761
14762/*
14763 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14764 * resume, or other times. This quirk makes sure that's the case for
14765 * affected systems.
14766 */
14767static void quirk_pipea_force(struct drm_device *dev)
14768{
14769 struct drm_i915_private *dev_priv = dev->dev_private;
14770
14771 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14772 DRM_INFO("applying pipe a force quirk\n");
14773}
14774
14775static void quirk_pipeb_force(struct drm_device *dev)
14776{
14777 struct drm_i915_private *dev_priv = dev->dev_private;
14778
14779 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14780 DRM_INFO("applying pipe b force quirk\n");
14781}
14782
14783/*
14784 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14785 */
14786static void quirk_ssc_force_disable(struct drm_device *dev)
14787{
14788 struct drm_i915_private *dev_priv = dev->dev_private;
14789 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14790 DRM_INFO("applying lvds SSC disable quirk\n");
14791}
14792
14793/*
14794 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14795 * brightness value
14796 */
14797static void quirk_invert_brightness(struct drm_device *dev)
14798{
14799 struct drm_i915_private *dev_priv = dev->dev_private;
14800 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14801 DRM_INFO("applying inverted panel brightness quirk\n");
14802}
14803
14804/* Some VBT's incorrectly indicate no backlight is present */
14805static void quirk_backlight_present(struct drm_device *dev)
14806{
14807 struct drm_i915_private *dev_priv = dev->dev_private;
14808 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14809 DRM_INFO("applying backlight present quirk\n");
14810}
14811
14812struct intel_quirk {
14813 int device;
14814 int subsystem_vendor;
14815 int subsystem_device;
14816 void (*hook)(struct drm_device *dev);
14817};
14818
14819/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14820struct intel_dmi_quirk {
14821 void (*hook)(struct drm_device *dev);
14822 const struct dmi_system_id (*dmi_id_list)[];
14823};
14824
14825static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14826{
14827 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14828 return 1;
14829}
14830
14831static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14832 {
14833 .dmi_id_list = &(const struct dmi_system_id[]) {
14834 {
14835 .callback = intel_dmi_reverse_brightness,
14836 .ident = "NCR Corporation",
14837 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14838 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14839 },
14840 },
14841 { } /* terminating entry */
14842 },
14843 .hook = quirk_invert_brightness,
14844 },
14845};
14846
14847static struct intel_quirk intel_quirks[] = {
14848 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14849 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14850
14851 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14852 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14853
14854 /* 830 needs to leave pipe A & dpll A up */
14855 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14856
14857 /* 830 needs to leave pipe B & dpll B up */
14858 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14859
14860 /* Lenovo U160 cannot use SSC on LVDS */
14861 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14862
14863 /* Sony Vaio Y cannot use SSC on LVDS */
14864 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14865
14866 /* Acer Aspire 5734Z must invert backlight brightness */
14867 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14868
14869 /* Acer/eMachines G725 */
14870 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14871
14872 /* Acer/eMachines e725 */
14873 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14874
14875 /* Acer/Packard Bell NCL20 */
14876 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14877
14878 /* Acer Aspire 4736Z */
14879 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14880
14881 /* Acer Aspire 5336 */
14882 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14883
14884 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14885 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14886
14887 /* Acer C720 Chromebook (Core i3 4005U) */
14888 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14889
14890 /* Apple Macbook 2,1 (Core 2 T7400) */
14891 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14892
14893 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14894 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14895
14896 /* HP Chromebook 14 (Celeron 2955U) */
14897 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14898
14899 /* Dell Chromebook 11 */
14900 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14901};
14902
14903static void intel_init_quirks(struct drm_device *dev)
14904{
14905 struct pci_dev *d = dev->pdev;
14906 int i;
14907
14908 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14909 struct intel_quirk *q = &intel_quirks[i];
14910
14911 if (d->device == q->device &&
14912 (d->subsystem_vendor == q->subsystem_vendor ||
14913 q->subsystem_vendor == PCI_ANY_ID) &&
14914 (d->subsystem_device == q->subsystem_device ||
14915 q->subsystem_device == PCI_ANY_ID))
14916 q->hook(dev);
14917 }
14918 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14919 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14920 intel_dmi_quirks[i].hook(dev);
14921 }
14922}
14923
14924/* Disable the VGA plane that we never use */
14925static void i915_disable_vga(struct drm_device *dev)
14926{
14927 struct drm_i915_private *dev_priv = dev->dev_private;
14928 u8 sr1;
14929 u32 vga_reg = i915_vgacntrl_reg(dev);
14930
14931 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14932 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14933 outb(SR01, VGA_SR_INDEX);
14934 sr1 = inb(VGA_SR_DATA);
14935 outb(sr1 | 1<<5, VGA_SR_DATA);
14936 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14937 udelay(300);
14938
14939 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14940 POSTING_READ(vga_reg);
14941}
14942
14943void intel_modeset_init_hw(struct drm_device *dev)
14944{
14945 intel_update_cdclk(dev);
14946 intel_prepare_ddi(dev);
14947 intel_init_clock_gating(dev);
14948 intel_enable_gt_powersave(dev);
14949}
14950
14951void intel_modeset_init(struct drm_device *dev)
14952{
14953 struct drm_i915_private *dev_priv = dev->dev_private;
14954 int sprite, ret;
14955 enum pipe pipe;
14956 struct intel_crtc *crtc;
14957
14958 drm_mode_config_init(dev);
14959
14960 dev->mode_config.min_width = 0;
14961 dev->mode_config.min_height = 0;
14962
14963 dev->mode_config.preferred_depth = 24;
14964 dev->mode_config.prefer_shadow = 1;
14965
14966 dev->mode_config.allow_fb_modifiers = true;
14967
14968 dev->mode_config.funcs = &intel_mode_funcs;
14969
14970 intel_init_quirks(dev);
14971
14972 intel_init_pm(dev);
14973
14974 if (INTEL_INFO(dev)->num_pipes == 0)
14975 return;
14976
14977 intel_init_display(dev);
14978 intel_init_audio(dev);
14979
14980 if (IS_GEN2(dev)) {
14981 dev->mode_config.max_width = 2048;
14982 dev->mode_config.max_height = 2048;
14983 } else if (IS_GEN3(dev)) {
14984 dev->mode_config.max_width = 4096;
14985 dev->mode_config.max_height = 4096;
14986 } else {
14987 dev->mode_config.max_width = 8192;
14988 dev->mode_config.max_height = 8192;
14989 }
14990
14991 if (IS_845G(dev) || IS_I865G(dev)) {
14992 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14993 dev->mode_config.cursor_height = 1023;
14994 } else if (IS_GEN2(dev)) {
14995 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14996 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14997 } else {
14998 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14999 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15000 }
15001
15002 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15003
15004 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15005 INTEL_INFO(dev)->num_pipes,
15006 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15007
15008 for_each_pipe(dev_priv, pipe) {
15009 intel_crtc_init(dev, pipe);
15010 for_each_sprite(dev_priv, pipe, sprite) {
15011 ret = intel_plane_init(dev, pipe, sprite);
15012 if (ret)
15013 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15014 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15015 }
15016 }
15017
15018 intel_init_dpio(dev);
15019
15020 intel_shared_dpll_init(dev);
15021
15022 /* Just disable it once at startup */
15023 i915_disable_vga(dev);
15024 intel_setup_outputs(dev);
15025
15026 /* Just in case the BIOS is doing something questionable. */
15027 intel_fbc_disable(dev);
15028
15029 drm_modeset_lock_all(dev);
15030 intel_modeset_setup_hw_state(dev, false);
15031 drm_modeset_unlock_all(dev);
15032
15033 for_each_intel_crtc(dev, crtc) {
15034 if (!crtc->active)
15035 continue;
15036
15037 /*
15038 * Note that reserving the BIOS fb up front prevents us
15039 * from stuffing other stolen allocations like the ring
15040 * on top. This prevents some ugliness at boot time, and
15041 * can even allow for smooth boot transitions if the BIOS
15042 * fb is large enough for the active pipe configuration.
15043 */
15044 if (dev_priv->display.get_initial_plane_config) {
15045 dev_priv->display.get_initial_plane_config(crtc,
15046 &crtc->plane_config);
15047 /*
15048 * If the fb is shared between multiple heads, we'll
15049 * just get the first one.
15050 */
15051 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
15052 }
15053 }
15054}
15055
15056static void intel_enable_pipe_a(struct drm_device *dev)
15057{
15058 struct intel_connector *connector;
15059 struct drm_connector *crt = NULL;
15060 struct intel_load_detect_pipe load_detect_temp;
15061 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15062
15063 /* We can't just switch on the pipe A, we need to set things up with a
15064 * proper mode and output configuration. As a gross hack, enable pipe A
15065 * by enabling the load detect pipe once. */
15066 for_each_intel_connector(dev, connector) {
15067 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15068 crt = &connector->base;
15069 break;
15070 }
15071 }
15072
15073 if (!crt)
15074 return;
15075
15076 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15077 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15078}
15079
15080static bool
15081intel_check_plane_mapping(struct intel_crtc *crtc)
15082{
15083 struct drm_device *dev = crtc->base.dev;
15084 struct drm_i915_private *dev_priv = dev->dev_private;
15085 u32 reg, val;
15086
15087 if (INTEL_INFO(dev)->num_pipes == 1)
15088 return true;
15089
15090 reg = DSPCNTR(!crtc->plane);
15091 val = I915_READ(reg);
15092
15093 if ((val & DISPLAY_PLANE_ENABLE) &&
15094 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15095 return false;
15096
15097 return true;
15098}
15099
15100static void intel_sanitize_crtc(struct intel_crtc *crtc)
15101{
15102 struct drm_device *dev = crtc->base.dev;
15103 struct drm_i915_private *dev_priv = dev->dev_private;
15104 u32 reg;
15105
15106 /* Clear any frame start delays used for debugging left by the BIOS */
15107 reg = PIPECONF(crtc->config->cpu_transcoder);
15108 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15109
15110 /* restore vblank interrupts to correct state */
15111 drm_crtc_vblank_reset(&crtc->base);
15112 if (crtc->active) {
15113 update_scanline_offset(crtc);
15114 drm_crtc_vblank_on(&crtc->base);
15115 }
15116
15117 /* We need to sanitize the plane -> pipe mapping first because this will
15118 * disable the crtc (and hence change the state) if it is wrong. Note
15119 * that gen4+ has a fixed plane -> pipe mapping. */
15120 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15121 struct intel_connector *connector;
15122 bool plane;
15123
15124 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15125 crtc->base.base.id);
15126
15127 /* Pipe has the wrong plane attached and the plane is active.
15128 * Temporarily change the plane mapping and disable everything
15129 * ... */
15130 plane = crtc->plane;
15131 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15132 crtc->plane = !plane;
15133 intel_crtc_control(&crtc->base, false);
15134 crtc->plane = plane;
15135
15136 /* ... and break all links. */
15137 for_each_intel_connector(dev, connector) {
15138 if (connector->encoder->base.crtc != &crtc->base)
15139 continue;
15140
15141 connector->base.dpms = DRM_MODE_DPMS_OFF;
15142 connector->base.encoder = NULL;
15143 }
15144 /* multiple connectors may have the same encoder:
15145 * handle them and break crtc link separately */
15146 for_each_intel_connector(dev, connector)
15147 if (connector->encoder->base.crtc == &crtc->base) {
15148 connector->encoder->base.crtc = NULL;
15149 connector->encoder->connectors_active = false;
15150 }
15151
15152 WARN_ON(crtc->active);
15153 crtc->base.state->enable = false;
15154 crtc->base.state->active = false;
15155 crtc->base.enabled = false;
15156 }
15157
15158 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15159 crtc->pipe == PIPE_A && !crtc->active) {
15160 /* BIOS forgot to enable pipe A, this mostly happens after
15161 * resume. Force-enable the pipe to fix this, the update_dpms
15162 * call below we restore the pipe to the right state, but leave
15163 * the required bits on. */
15164 intel_enable_pipe_a(dev);
15165 }
15166
15167 /* Adjust the state of the output pipe according to whether we
15168 * have active connectors/encoders. */
15169 intel_crtc_update_dpms(&crtc->base);
15170
15171 if (crtc->active != crtc->base.state->active) {
15172 struct intel_encoder *encoder;
15173
15174 /* This can happen either due to bugs in the get_hw_state
15175 * functions or because the pipe is force-enabled due to the
15176 * pipe A quirk. */
15177 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15178 crtc->base.base.id,
15179 crtc->base.state->enable ? "enabled" : "disabled",
15180 crtc->active ? "enabled" : "disabled");
15181
15182 crtc->base.state->enable = crtc->active;
15183 crtc->base.state->active = crtc->active;
15184 crtc->base.enabled = crtc->active;
15185
15186 /* Because we only establish the connector -> encoder ->
15187 * crtc links if something is active, this means the
15188 * crtc is now deactivated. Break the links. connector
15189 * -> encoder links are only establish when things are
15190 * actually up, hence no need to break them. */
15191 WARN_ON(crtc->active);
15192
15193 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15194 WARN_ON(encoder->connectors_active);
15195 encoder->base.crtc = NULL;
15196 }
15197 }
15198
15199 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15200 /*
15201 * We start out with underrun reporting disabled to avoid races.
15202 * For correct bookkeeping mark this on active crtcs.
15203 *
15204 * Also on gmch platforms we dont have any hardware bits to
15205 * disable the underrun reporting. Which means we need to start
15206 * out with underrun reporting disabled also on inactive pipes,
15207 * since otherwise we'll complain about the garbage we read when
15208 * e.g. coming up after runtime pm.
15209 *
15210 * No protection against concurrent access is required - at
15211 * worst a fifo underrun happens which also sets this to false.
15212 */
15213 crtc->cpu_fifo_underrun_disabled = true;
15214 crtc->pch_fifo_underrun_disabled = true;
15215 }
15216}
15217
15218static void intel_sanitize_encoder(struct intel_encoder *encoder)
15219{
15220 struct intel_connector *connector;
15221 struct drm_device *dev = encoder->base.dev;
15222
15223 /* We need to check both for a crtc link (meaning that the
15224 * encoder is active and trying to read from a pipe) and the
15225 * pipe itself being active. */
15226 bool has_active_crtc = encoder->base.crtc &&
15227 to_intel_crtc(encoder->base.crtc)->active;
15228
15229 if (encoder->connectors_active && !has_active_crtc) {
15230 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15231 encoder->base.base.id,
15232 encoder->base.name);
15233
15234 /* Connector is active, but has no active pipe. This is
15235 * fallout from our resume register restoring. Disable
15236 * the encoder manually again. */
15237 if (encoder->base.crtc) {
15238 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15239 encoder->base.base.id,
15240 encoder->base.name);
15241 encoder->disable(encoder);
15242 if (encoder->post_disable)
15243 encoder->post_disable(encoder);
15244 }
15245 encoder->base.crtc = NULL;
15246 encoder->connectors_active = false;
15247
15248 /* Inconsistent output/port/pipe state happens presumably due to
15249 * a bug in one of the get_hw_state functions. Or someplace else
15250 * in our code, like the register restore mess on resume. Clamp
15251 * things to off as a safer default. */
15252 for_each_intel_connector(dev, connector) {
15253 if (connector->encoder != encoder)
15254 continue;
15255 connector->base.dpms = DRM_MODE_DPMS_OFF;
15256 connector->base.encoder = NULL;
15257 }
15258 }
15259 /* Enabled encoders without active connectors will be fixed in
15260 * the crtc fixup. */
15261}
15262
15263void i915_redisable_vga_power_on(struct drm_device *dev)
15264{
15265 struct drm_i915_private *dev_priv = dev->dev_private;
15266 u32 vga_reg = i915_vgacntrl_reg(dev);
15267
15268 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15269 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15270 i915_disable_vga(dev);
15271 }
15272}
15273
15274void i915_redisable_vga(struct drm_device *dev)
15275{
15276 struct drm_i915_private *dev_priv = dev->dev_private;
15277
15278 /* This function can be called both from intel_modeset_setup_hw_state or
15279 * at a very early point in our resume sequence, where the power well
15280 * structures are not yet restored. Since this function is at a very
15281 * paranoid "someone might have enabled VGA while we were not looking"
15282 * level, just check if the power well is enabled instead of trying to
15283 * follow the "don't touch the power well if we don't need it" policy
15284 * the rest of the driver uses. */
15285 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15286 return;
15287
15288 i915_redisable_vga_power_on(dev);
15289}
15290
15291static bool primary_get_hw_state(struct intel_crtc *crtc)
15292{
15293 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15294
15295 if (!crtc->active)
15296 return false;
15297
15298 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15299}
15300
15301static void intel_modeset_readout_hw_state(struct drm_device *dev)
15302{
15303 struct drm_i915_private *dev_priv = dev->dev_private;
15304 enum pipe pipe;
15305 struct intel_crtc *crtc;
15306 struct intel_encoder *encoder;
15307 struct intel_connector *connector;
15308 int i;
15309
15310 for_each_intel_crtc(dev, crtc) {
15311 struct drm_plane *primary = crtc->base.primary;
15312 struct intel_plane_state *plane_state;
15313
15314 memset(crtc->config, 0, sizeof(*crtc->config));
15315
15316 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
15317
15318 crtc->active = dev_priv->display.get_pipe_config(crtc,
15319 crtc->config);
15320
15321 crtc->base.state->enable = crtc->active;
15322 crtc->base.state->active = crtc->active;
15323 crtc->base.enabled = crtc->active;
15324
15325 plane_state = to_intel_plane_state(primary->state);
15326 plane_state->visible = primary_get_hw_state(crtc);
15327
15328 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15329 crtc->base.base.id,
15330 crtc->active ? "enabled" : "disabled");
15331 }
15332
15333 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15334 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15335
15336 pll->on = pll->get_hw_state(dev_priv, pll,
15337 &pll->config.hw_state);
15338 pll->active = 0;
15339 pll->config.crtc_mask = 0;
15340 for_each_intel_crtc(dev, crtc) {
15341 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15342 pll->active++;
15343 pll->config.crtc_mask |= 1 << crtc->pipe;
15344 }
15345 }
15346
15347 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15348 pll->name, pll->config.crtc_mask, pll->on);
15349
15350 if (pll->config.crtc_mask)
15351 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15352 }
15353
15354 for_each_intel_encoder(dev, encoder) {
15355 pipe = 0;
15356
15357 if (encoder->get_hw_state(encoder, &pipe)) {
15358 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15359 encoder->base.crtc = &crtc->base;
15360 encoder->get_config(encoder, crtc->config);
15361 } else {
15362 encoder->base.crtc = NULL;
15363 }
15364
15365 encoder->connectors_active = false;
15366 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15367 encoder->base.base.id,
15368 encoder->base.name,
15369 encoder->base.crtc ? "enabled" : "disabled",
15370 pipe_name(pipe));
15371 }
15372
15373 for_each_intel_connector(dev, connector) {
15374 if (connector->get_hw_state(connector)) {
15375 connector->base.dpms = DRM_MODE_DPMS_ON;
15376 connector->encoder->connectors_active = true;
15377 connector->base.encoder = &connector->encoder->base;
15378 } else {
15379 connector->base.dpms = DRM_MODE_DPMS_OFF;
15380 connector->base.encoder = NULL;
15381 }
15382 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15383 connector->base.base.id,
15384 connector->base.name,
15385 connector->base.encoder ? "enabled" : "disabled");
15386 }
15387}
15388
15389/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15390 * and i915 state tracking structures. */
15391void intel_modeset_setup_hw_state(struct drm_device *dev,
15392 bool force_restore)
15393{
15394 struct drm_i915_private *dev_priv = dev->dev_private;
15395 enum pipe pipe;
15396 struct intel_crtc *crtc;
15397 struct intel_encoder *encoder;
15398 int i;
15399
15400 intel_modeset_readout_hw_state(dev);
15401
15402 /*
15403 * Now that we have the config, copy it to each CRTC struct
15404 * Note that this could go away if we move to using crtc_config
15405 * checking everywhere.
15406 */
15407 for_each_intel_crtc(dev, crtc) {
15408 if (crtc->active && i915.fastboot) {
15409 intel_mode_from_pipe_config(&crtc->base.mode,
15410 crtc->config);
15411 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15412 crtc->base.base.id);
15413 drm_mode_debug_printmodeline(&crtc->base.mode);
15414 }
15415 }
15416
15417 /* HW state is read out, now we need to sanitize this mess. */
15418 for_each_intel_encoder(dev, encoder) {
15419 intel_sanitize_encoder(encoder);
15420 }
15421
15422 for_each_pipe(dev_priv, pipe) {
15423 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15424 intel_sanitize_crtc(crtc);
15425 intel_dump_pipe_config(crtc, crtc->config,
15426 "[setup_hw_state]");
15427 }
15428
15429 intel_modeset_update_connector_atomic_state(dev);
15430
15431 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15432 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15433
15434 if (!pll->on || pll->active)
15435 continue;
15436
15437 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15438
15439 pll->disable(dev_priv, pll);
15440 pll->on = false;
15441 }
15442
15443 if (IS_GEN9(dev))
15444 skl_wm_get_hw_state(dev);
15445 else if (HAS_PCH_SPLIT(dev))
15446 ilk_wm_get_hw_state(dev);
15447
15448 if (force_restore) {
15449 i915_redisable_vga(dev);
15450
15451 /*
15452 * We need to use raw interfaces for restoring state to avoid
15453 * checking (bogus) intermediate states.
15454 */
15455 for_each_pipe(dev_priv, pipe) {
15456 struct drm_crtc *crtc =
15457 dev_priv->pipe_to_crtc_mapping[pipe];
15458
15459 intel_crtc_restore_mode(crtc);
15460 }
15461 } else {
15462 intel_modeset_update_staged_output_state(dev);
15463 }
15464
15465 intel_modeset_check_state(dev);
15466}
15467
15468void intel_modeset_gem_init(struct drm_device *dev)
15469{
15470 struct drm_i915_private *dev_priv = dev->dev_private;
15471 struct drm_crtc *c;
15472 struct drm_i915_gem_object *obj;
15473 int ret;
15474
15475 mutex_lock(&dev->struct_mutex);
15476 intel_init_gt_powersave(dev);
15477 mutex_unlock(&dev->struct_mutex);
15478
15479 /*
15480 * There may be no VBT; and if the BIOS enabled SSC we can
15481 * just keep using it to avoid unnecessary flicker. Whereas if the
15482 * BIOS isn't using it, don't assume it will work even if the VBT
15483 * indicates as much.
15484 */
15485 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15486 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15487 DREF_SSC1_ENABLE);
15488
15489 intel_modeset_init_hw(dev);
15490
15491 intel_setup_overlay(dev);
15492
15493 /*
15494 * Make sure any fbs we allocated at startup are properly
15495 * pinned & fenced. When we do the allocation it's too early
15496 * for this.
15497 */
15498 for_each_crtc(dev, c) {
15499 obj = intel_fb_obj(c->primary->fb);
15500 if (obj == NULL)
15501 continue;
15502
15503 mutex_lock(&dev->struct_mutex);
15504 ret = intel_pin_and_fence_fb_obj(c->primary,
15505 c->primary->fb,
15506 c->primary->state,
15507 NULL);
15508 mutex_unlock(&dev->struct_mutex);
15509 if (ret) {
15510 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15511 to_intel_crtc(c)->pipe);
15512 drm_framebuffer_unreference(c->primary->fb);
15513 c->primary->fb = NULL;
15514 c->primary->crtc = c->primary->state->crtc = NULL;
15515 update_state_fb(c->primary);
15516 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15517 }
15518 }
15519
15520 intel_backlight_register(dev);
15521}
15522
15523void intel_connector_unregister(struct intel_connector *intel_connector)
15524{
15525 struct drm_connector *connector = &intel_connector->base;
15526
15527 intel_panel_destroy_backlight(connector);
15528 drm_connector_unregister(connector);
15529}
15530
15531void intel_modeset_cleanup(struct drm_device *dev)
15532{
15533 struct drm_i915_private *dev_priv = dev->dev_private;
15534 struct drm_connector *connector;
15535
15536 intel_disable_gt_powersave(dev);
15537
15538 intel_backlight_unregister(dev);
15539
15540 /*
15541 * Interrupts and polling as the first thing to avoid creating havoc.
15542 * Too much stuff here (turning of connectors, ...) would
15543 * experience fancy races otherwise.
15544 */
15545 intel_irq_uninstall(dev_priv);
15546
15547 /*
15548 * Due to the hpd irq storm handling the hotplug work can re-arm the
15549 * poll handlers. Hence disable polling after hpd handling is shut down.
15550 */
15551 drm_kms_helper_poll_fini(dev);
15552
15553 mutex_lock(&dev->struct_mutex);
15554
15555 intel_unregister_dsm_handler();
15556
15557 intel_fbc_disable(dev);
15558
15559 mutex_unlock(&dev->struct_mutex);
15560
15561 /* flush any delayed tasks or pending work */
15562 flush_scheduled_work();
15563
15564 /* destroy the backlight and sysfs files before encoders/connectors */
15565 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15566 struct intel_connector *intel_connector;
15567
15568 intel_connector = to_intel_connector(connector);
15569 intel_connector->unregister(intel_connector);
15570 }
15571
15572 drm_mode_config_cleanup(dev);
15573
15574 intel_cleanup_overlay(dev);
15575
15576 mutex_lock(&dev->struct_mutex);
15577 intel_cleanup_gt_powersave(dev);
15578 mutex_unlock(&dev->struct_mutex);
15579}
15580
15581/*
15582 * Return which encoder is currently attached for connector.
15583 */
15584struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15585{
15586 return &intel_attached_encoder(connector)->base;
15587}
15588
15589void intel_connector_attach_encoder(struct intel_connector *connector,
15590 struct intel_encoder *encoder)
15591{
15592 connector->encoder = encoder;
15593 drm_mode_connector_attach_encoder(&connector->base,
15594 &encoder->base);
15595}
15596
15597/*
15598 * set vga decode state - true == enable VGA decode
15599 */
15600int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15601{
15602 struct drm_i915_private *dev_priv = dev->dev_private;
15603 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15604 u16 gmch_ctrl;
15605
15606 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15607 DRM_ERROR("failed to read control word\n");
15608 return -EIO;
15609 }
15610
15611 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15612 return 0;
15613
15614 if (state)
15615 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15616 else
15617 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15618
15619 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15620 DRM_ERROR("failed to write control word\n");
15621 return -EIO;
15622 }
15623
15624 return 0;
15625}
15626
15627struct intel_display_error_state {
15628
15629 u32 power_well_driver;
15630
15631 int num_transcoders;
15632
15633 struct intel_cursor_error_state {
15634 u32 control;
15635 u32 position;
15636 u32 base;
15637 u32 size;
15638 } cursor[I915_MAX_PIPES];
15639
15640 struct intel_pipe_error_state {
15641 bool power_domain_on;
15642 u32 source;
15643 u32 stat;
15644 } pipe[I915_MAX_PIPES];
15645
15646 struct intel_plane_error_state {
15647 u32 control;
15648 u32 stride;
15649 u32 size;
15650 u32 pos;
15651 u32 addr;
15652 u32 surface;
15653 u32 tile_offset;
15654 } plane[I915_MAX_PIPES];
15655
15656 struct intel_transcoder_error_state {
15657 bool power_domain_on;
15658 enum transcoder cpu_transcoder;
15659
15660 u32 conf;
15661
15662 u32 htotal;
15663 u32 hblank;
15664 u32 hsync;
15665 u32 vtotal;
15666 u32 vblank;
15667 u32 vsync;
15668 } transcoder[4];
15669};
15670
15671struct intel_display_error_state *
15672intel_display_capture_error_state(struct drm_device *dev)
15673{
15674 struct drm_i915_private *dev_priv = dev->dev_private;
15675 struct intel_display_error_state *error;
15676 int transcoders[] = {
15677 TRANSCODER_A,
15678 TRANSCODER_B,
15679 TRANSCODER_C,
15680 TRANSCODER_EDP,
15681 };
15682 int i;
15683
15684 if (INTEL_INFO(dev)->num_pipes == 0)
15685 return NULL;
15686
15687 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15688 if (error == NULL)
15689 return NULL;
15690
15691 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15692 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15693
15694 for_each_pipe(dev_priv, i) {
15695 error->pipe[i].power_domain_on =
15696 __intel_display_power_is_enabled(dev_priv,
15697 POWER_DOMAIN_PIPE(i));
15698 if (!error->pipe[i].power_domain_on)
15699 continue;
15700
15701 error->cursor[i].control = I915_READ(CURCNTR(i));
15702 error->cursor[i].position = I915_READ(CURPOS(i));
15703 error->cursor[i].base = I915_READ(CURBASE(i));
15704
15705 error->plane[i].control = I915_READ(DSPCNTR(i));
15706 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15707 if (INTEL_INFO(dev)->gen <= 3) {
15708 error->plane[i].size = I915_READ(DSPSIZE(i));
15709 error->plane[i].pos = I915_READ(DSPPOS(i));
15710 }
15711 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15712 error->plane[i].addr = I915_READ(DSPADDR(i));
15713 if (INTEL_INFO(dev)->gen >= 4) {
15714 error->plane[i].surface = I915_READ(DSPSURF(i));
15715 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15716 }
15717
15718 error->pipe[i].source = I915_READ(PIPESRC(i));
15719
15720 if (HAS_GMCH_DISPLAY(dev))
15721 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15722 }
15723
15724 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15725 if (HAS_DDI(dev_priv->dev))
15726 error->num_transcoders++; /* Account for eDP. */
15727
15728 for (i = 0; i < error->num_transcoders; i++) {
15729 enum transcoder cpu_transcoder = transcoders[i];
15730
15731 error->transcoder[i].power_domain_on =
15732 __intel_display_power_is_enabled(dev_priv,
15733 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15734 if (!error->transcoder[i].power_domain_on)
15735 continue;
15736
15737 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15738
15739 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15740 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15741 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15742 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15743 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15744 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15745 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15746 }
15747
15748 return error;
15749}
15750
15751#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15752
15753void
15754intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15755 struct drm_device *dev,
15756 struct intel_display_error_state *error)
15757{
15758 struct drm_i915_private *dev_priv = dev->dev_private;
15759 int i;
15760
15761 if (!error)
15762 return;
15763
15764 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15765 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15766 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15767 error->power_well_driver);
15768 for_each_pipe(dev_priv, i) {
15769 err_printf(m, "Pipe [%d]:\n", i);
15770 err_printf(m, " Power: %s\n",
15771 error->pipe[i].power_domain_on ? "on" : "off");
15772 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15773 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15774
15775 err_printf(m, "Plane [%d]:\n", i);
15776 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15777 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15778 if (INTEL_INFO(dev)->gen <= 3) {
15779 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15780 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15781 }
15782 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15783 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15784 if (INTEL_INFO(dev)->gen >= 4) {
15785 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15786 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15787 }
15788
15789 err_printf(m, "Cursor [%d]:\n", i);
15790 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15791 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15792 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15793 }
15794
15795 for (i = 0; i < error->num_transcoders; i++) {
15796 err_printf(m, "CPU transcoder: %c\n",
15797 transcoder_name(error->transcoder[i].cpu_transcoder));
15798 err_printf(m, " Power: %s\n",
15799 error->transcoder[i].power_domain_on ? "on" : "off");
15800 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15801 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15802 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15803 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15804 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15805 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15806 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15807 }
15808}
15809
15810void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15811{
15812 struct intel_crtc *crtc;
15813
15814 for_each_intel_crtc(dev, crtc) {
15815 struct intel_unpin_work *work;
15816
15817 spin_lock_irq(&dev->event_lock);
15818
15819 work = crtc->unpin_work;
15820
15821 if (work && work->event &&
15822 work->event->base.file_priv == file) {
15823 kfree(work->event);
15824 work->event = NULL;
15825 }
15826
15827 spin_unlock_irq(&dev->event_lock);
15828 }
15829}
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