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drm/i915/ddi: write ELD where it's supposed to be done
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
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1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
29#include <linux/slab.h>
30#include <linux/export.h>
31#include <linux/notifier.h>
32#include <linux/reboot.h>
33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
37#include "intel_drv.h"
38#include <drm/i915_drm.h>
39#include "i915_drv.h"
40
41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
99}
100
101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
102{
103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
106}
107
108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
111}
112
113static void intel_dp_link_down(struct intel_dp *intel_dp);
114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
116static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
117static void vlv_steal_power_sequencer(struct drm_device *dev,
118 enum pipe pipe);
119
120int
121intel_dp_max_link_bw(struct intel_dp *intel_dp)
122{
123 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
124 struct drm_device *dev = intel_dp->attached_connector->base.dev;
125
126 switch (max_link_bw) {
127 case DP_LINK_BW_1_62:
128 case DP_LINK_BW_2_7:
129 break;
130 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
131 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
132 INTEL_INFO(dev)->gen >= 8) &&
133 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
134 max_link_bw = DP_LINK_BW_5_4;
135 else
136 max_link_bw = DP_LINK_BW_2_7;
137 break;
138 default:
139 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
140 max_link_bw);
141 max_link_bw = DP_LINK_BW_1_62;
142 break;
143 }
144 return max_link_bw;
145}
146
147static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
148{
149 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
150 struct drm_device *dev = intel_dig_port->base.base.dev;
151 u8 source_max, sink_max;
152
153 source_max = 4;
154 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
155 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
156 source_max = 2;
157
158 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
159
160 return min(source_max, sink_max);
161}
162
163/*
164 * The units on the numbers in the next two are... bizarre. Examples will
165 * make it clearer; this one parallels an example in the eDP spec.
166 *
167 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
168 *
169 * 270000 * 1 * 8 / 10 == 216000
170 *
171 * The actual data capacity of that configuration is 2.16Gbit/s, so the
172 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
173 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
174 * 119000. At 18bpp that's 2142000 kilobits per second.
175 *
176 * Thus the strange-looking division by 10 in intel_dp_link_required, to
177 * get the result in decakilobits instead of kilobits.
178 */
179
180static int
181intel_dp_link_required(int pixel_clock, int bpp)
182{
183 return (pixel_clock * bpp + 9) / 10;
184}
185
186static int
187intel_dp_max_data_rate(int max_link_clock, int max_lanes)
188{
189 return (max_link_clock * max_lanes * 8) / 10;
190}
191
192static enum drm_mode_status
193intel_dp_mode_valid(struct drm_connector *connector,
194 struct drm_display_mode *mode)
195{
196 struct intel_dp *intel_dp = intel_attached_dp(connector);
197 struct intel_connector *intel_connector = to_intel_connector(connector);
198 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
199 int target_clock = mode->clock;
200 int max_rate, mode_rate, max_lanes, max_link_clock;
201
202 if (is_edp(intel_dp) && fixed_mode) {
203 if (mode->hdisplay > fixed_mode->hdisplay)
204 return MODE_PANEL;
205
206 if (mode->vdisplay > fixed_mode->vdisplay)
207 return MODE_PANEL;
208
209 target_clock = fixed_mode->clock;
210 }
211
212 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
213 max_lanes = intel_dp_max_lane_count(intel_dp);
214
215 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
216 mode_rate = intel_dp_link_required(target_clock, 18);
217
218 if (mode_rate > max_rate)
219 return MODE_CLOCK_HIGH;
220
221 if (mode->clock < 10000)
222 return MODE_CLOCK_LOW;
223
224 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
225 return MODE_H_ILLEGAL;
226
227 return MODE_OK;
228}
229
230static uint32_t
231pack_aux(const uint8_t *src, int src_bytes)
232{
233 int i;
234 uint32_t v = 0;
235
236 if (src_bytes > 4)
237 src_bytes = 4;
238 for (i = 0; i < src_bytes; i++)
239 v |= ((uint32_t) src[i]) << ((3-i) * 8);
240 return v;
241}
242
243static void
244unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
245{
246 int i;
247 if (dst_bytes > 4)
248 dst_bytes = 4;
249 for (i = 0; i < dst_bytes; i++)
250 dst[i] = src >> ((3-i) * 8);
251}
252
253/* hrawclock is 1/4 the FSB frequency */
254static int
255intel_hrawclk(struct drm_device *dev)
256{
257 struct drm_i915_private *dev_priv = dev->dev_private;
258 uint32_t clkcfg;
259
260 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
261 if (IS_VALLEYVIEW(dev))
262 return 200;
263
264 clkcfg = I915_READ(CLKCFG);
265 switch (clkcfg & CLKCFG_FSB_MASK) {
266 case CLKCFG_FSB_400:
267 return 100;
268 case CLKCFG_FSB_533:
269 return 133;
270 case CLKCFG_FSB_667:
271 return 166;
272 case CLKCFG_FSB_800:
273 return 200;
274 case CLKCFG_FSB_1067:
275 return 266;
276 case CLKCFG_FSB_1333:
277 return 333;
278 /* these two are just a guess; one of them might be right */
279 case CLKCFG_FSB_1600:
280 case CLKCFG_FSB_1600_ALT:
281 return 400;
282 default:
283 return 133;
284 }
285}
286
287static void
288intel_dp_init_panel_power_sequencer(struct drm_device *dev,
289 struct intel_dp *intel_dp);
290static void
291intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
292 struct intel_dp *intel_dp);
293
294static void pps_lock(struct intel_dp *intel_dp)
295{
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
297 struct intel_encoder *encoder = &intel_dig_port->base;
298 struct drm_device *dev = encoder->base.dev;
299 struct drm_i915_private *dev_priv = dev->dev_private;
300 enum intel_display_power_domain power_domain;
301
302 /*
303 * See vlv_power_sequencer_reset() why we need
304 * a power domain reference here.
305 */
306 power_domain = intel_display_port_power_domain(encoder);
307 intel_display_power_get(dev_priv, power_domain);
308
309 mutex_lock(&dev_priv->pps_mutex);
310}
311
312static void pps_unlock(struct intel_dp *intel_dp)
313{
314 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
315 struct intel_encoder *encoder = &intel_dig_port->base;
316 struct drm_device *dev = encoder->base.dev;
317 struct drm_i915_private *dev_priv = dev->dev_private;
318 enum intel_display_power_domain power_domain;
319
320 mutex_unlock(&dev_priv->pps_mutex);
321
322 power_domain = intel_display_port_power_domain(encoder);
323 intel_display_power_put(dev_priv, power_domain);
324}
325
326static void
327vlv_power_sequencer_kick(struct intel_dp *intel_dp)
328{
329 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
330 struct drm_device *dev = intel_dig_port->base.base.dev;
331 struct drm_i915_private *dev_priv = dev->dev_private;
332 enum pipe pipe = intel_dp->pps_pipe;
333 bool pll_enabled;
334 uint32_t DP;
335
336 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
337 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
338 pipe_name(pipe), port_name(intel_dig_port->port)))
339 return;
340
341 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
342 pipe_name(pipe), port_name(intel_dig_port->port));
343
344 /* Preserve the BIOS-computed detected bit. This is
345 * supposed to be read-only.
346 */
347 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
348 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
349 DP |= DP_PORT_WIDTH(1);
350 DP |= DP_LINK_TRAIN_PAT_1;
351
352 if (IS_CHERRYVIEW(dev))
353 DP |= DP_PIPE_SELECT_CHV(pipe);
354 else if (pipe == PIPE_B)
355 DP |= DP_PIPEB_SELECT;
356
357 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
358
359 /*
360 * The DPLL for the pipe must be enabled for this to work.
361 * So enable temporarily it if it's not already enabled.
362 */
363 if (!pll_enabled)
364 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
365 &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
366
367 /*
368 * Similar magic as in intel_dp_enable_port().
369 * We _must_ do this port enable + disable trick
370 * to make this power seqeuencer lock onto the port.
371 * Otherwise even VDD force bit won't work.
372 */
373 I915_WRITE(intel_dp->output_reg, DP);
374 POSTING_READ(intel_dp->output_reg);
375
376 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
377 POSTING_READ(intel_dp->output_reg);
378
379 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
380 POSTING_READ(intel_dp->output_reg);
381
382 if (!pll_enabled)
383 vlv_force_pll_off(dev, pipe);
384}
385
386static enum pipe
387vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
388{
389 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
390 struct drm_device *dev = intel_dig_port->base.base.dev;
391 struct drm_i915_private *dev_priv = dev->dev_private;
392 struct intel_encoder *encoder;
393 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
394 enum pipe pipe;
395
396 lockdep_assert_held(&dev_priv->pps_mutex);
397
398 /* We should never land here with regular DP ports */
399 WARN_ON(!is_edp(intel_dp));
400
401 if (intel_dp->pps_pipe != INVALID_PIPE)
402 return intel_dp->pps_pipe;
403
404 /*
405 * We don't have power sequencer currently.
406 * Pick one that's not used by other ports.
407 */
408 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
409 base.head) {
410 struct intel_dp *tmp;
411
412 if (encoder->type != INTEL_OUTPUT_EDP)
413 continue;
414
415 tmp = enc_to_intel_dp(&encoder->base);
416
417 if (tmp->pps_pipe != INVALID_PIPE)
418 pipes &= ~(1 << tmp->pps_pipe);
419 }
420
421 /*
422 * Didn't find one. This should not happen since there
423 * are two power sequencers and up to two eDP ports.
424 */
425 if (WARN_ON(pipes == 0))
426 pipe = PIPE_A;
427 else
428 pipe = ffs(pipes) - 1;
429
430 vlv_steal_power_sequencer(dev, pipe);
431 intel_dp->pps_pipe = pipe;
432
433 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
434 pipe_name(intel_dp->pps_pipe),
435 port_name(intel_dig_port->port));
436
437 /* init power sequencer on this pipe and port */
438 intel_dp_init_panel_power_sequencer(dev, intel_dp);
439 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
440
441 /*
442 * Even vdd force doesn't work until we've made
443 * the power sequencer lock in on the port.
444 */
445 vlv_power_sequencer_kick(intel_dp);
446
447 return intel_dp->pps_pipe;
448}
449
450typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
451 enum pipe pipe);
452
453static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
454 enum pipe pipe)
455{
456 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
457}
458
459static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
460 enum pipe pipe)
461{
462 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
463}
464
465static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
466 enum pipe pipe)
467{
468 return true;
469}
470
471static enum pipe
472vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
473 enum port port,
474 vlv_pipe_check pipe_check)
475{
476 enum pipe pipe;
477
478 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
479 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
480 PANEL_PORT_SELECT_MASK;
481
482 if (port_sel != PANEL_PORT_SELECT_VLV(port))
483 continue;
484
485 if (!pipe_check(dev_priv, pipe))
486 continue;
487
488 return pipe;
489 }
490
491 return INVALID_PIPE;
492}
493
494static void
495vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
496{
497 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
498 struct drm_device *dev = intel_dig_port->base.base.dev;
499 struct drm_i915_private *dev_priv = dev->dev_private;
500 enum port port = intel_dig_port->port;
501
502 lockdep_assert_held(&dev_priv->pps_mutex);
503
504 /* try to find a pipe with this port selected */
505 /* first pick one where the panel is on */
506 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
507 vlv_pipe_has_pp_on);
508 /* didn't find one? pick one where vdd is on */
509 if (intel_dp->pps_pipe == INVALID_PIPE)
510 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
511 vlv_pipe_has_vdd_on);
512 /* didn't find one? pick one with just the correct port */
513 if (intel_dp->pps_pipe == INVALID_PIPE)
514 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
515 vlv_pipe_any);
516
517 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
518 if (intel_dp->pps_pipe == INVALID_PIPE) {
519 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
520 port_name(port));
521 return;
522 }
523
524 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
525 port_name(port), pipe_name(intel_dp->pps_pipe));
526
527 intel_dp_init_panel_power_sequencer(dev, intel_dp);
528 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
529}
530
531void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
532{
533 struct drm_device *dev = dev_priv->dev;
534 struct intel_encoder *encoder;
535
536 if (WARN_ON(!IS_VALLEYVIEW(dev)))
537 return;
538
539 /*
540 * We can't grab pps_mutex here due to deadlock with power_domain
541 * mutex when power_domain functions are called while holding pps_mutex.
542 * That also means that in order to use pps_pipe the code needs to
543 * hold both a power domain reference and pps_mutex, and the power domain
544 * reference get/put must be done while _not_ holding pps_mutex.
545 * pps_{lock,unlock}() do these steps in the correct order, so one
546 * should use them always.
547 */
548
549 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
550 struct intel_dp *intel_dp;
551
552 if (encoder->type != INTEL_OUTPUT_EDP)
553 continue;
554
555 intel_dp = enc_to_intel_dp(&encoder->base);
556 intel_dp->pps_pipe = INVALID_PIPE;
557 }
558}
559
560static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
561{
562 struct drm_device *dev = intel_dp_to_dev(intel_dp);
563
564 if (HAS_PCH_SPLIT(dev))
565 return PCH_PP_CONTROL;
566 else
567 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
568}
569
570static u32 _pp_stat_reg(struct intel_dp *intel_dp)
571{
572 struct drm_device *dev = intel_dp_to_dev(intel_dp);
573
574 if (HAS_PCH_SPLIT(dev))
575 return PCH_PP_STATUS;
576 else
577 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
578}
579
580/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
581 This function only applicable when panel PM state is not to be tracked */
582static int edp_notify_handler(struct notifier_block *this, unsigned long code,
583 void *unused)
584{
585 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
586 edp_notifier);
587 struct drm_device *dev = intel_dp_to_dev(intel_dp);
588 struct drm_i915_private *dev_priv = dev->dev_private;
589 u32 pp_div;
590 u32 pp_ctrl_reg, pp_div_reg;
591
592 if (!is_edp(intel_dp) || code != SYS_RESTART)
593 return 0;
594
595 pps_lock(intel_dp);
596
597 if (IS_VALLEYVIEW(dev)) {
598 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
599
600 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
601 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
602 pp_div = I915_READ(pp_div_reg);
603 pp_div &= PP_REFERENCE_DIVIDER_MASK;
604
605 /* 0x1F write to PP_DIV_REG sets max cycle delay */
606 I915_WRITE(pp_div_reg, pp_div | 0x1F);
607 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
608 msleep(intel_dp->panel_power_cycle_delay);
609 }
610
611 pps_unlock(intel_dp);
612
613 return 0;
614}
615
616static bool edp_have_panel_power(struct intel_dp *intel_dp)
617{
618 struct drm_device *dev = intel_dp_to_dev(intel_dp);
619 struct drm_i915_private *dev_priv = dev->dev_private;
620
621 lockdep_assert_held(&dev_priv->pps_mutex);
622
623 if (IS_VALLEYVIEW(dev) &&
624 intel_dp->pps_pipe == INVALID_PIPE)
625 return false;
626
627 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
628}
629
630static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
631{
632 struct drm_device *dev = intel_dp_to_dev(intel_dp);
633 struct drm_i915_private *dev_priv = dev->dev_private;
634
635 lockdep_assert_held(&dev_priv->pps_mutex);
636
637 if (IS_VALLEYVIEW(dev) &&
638 intel_dp->pps_pipe == INVALID_PIPE)
639 return false;
640
641 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
642}
643
644static void
645intel_dp_check_edp(struct intel_dp *intel_dp)
646{
647 struct drm_device *dev = intel_dp_to_dev(intel_dp);
648 struct drm_i915_private *dev_priv = dev->dev_private;
649
650 if (!is_edp(intel_dp))
651 return;
652
653 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
654 WARN(1, "eDP powered off while attempting aux channel communication.\n");
655 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
656 I915_READ(_pp_stat_reg(intel_dp)),
657 I915_READ(_pp_ctrl_reg(intel_dp)));
658 }
659}
660
661static uint32_t
662intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
663{
664 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
665 struct drm_device *dev = intel_dig_port->base.base.dev;
666 struct drm_i915_private *dev_priv = dev->dev_private;
667 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
668 uint32_t status;
669 bool done;
670
671#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
672 if (has_aux_irq)
673 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
674 msecs_to_jiffies_timeout(10));
675 else
676 done = wait_for_atomic(C, 10) == 0;
677 if (!done)
678 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
679 has_aux_irq);
680#undef C
681
682 return status;
683}
684
685static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
686{
687 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
688 struct drm_device *dev = intel_dig_port->base.base.dev;
689
690 /*
691 * The clock divider is based off the hrawclk, and would like to run at
692 * 2MHz. So, take the hrawclk value and divide by 2 and use that
693 */
694 return index ? 0 : intel_hrawclk(dev) / 2;
695}
696
697static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
698{
699 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
700 struct drm_device *dev = intel_dig_port->base.base.dev;
701
702 if (index)
703 return 0;
704
705 if (intel_dig_port->port == PORT_A) {
706 if (IS_GEN6(dev) || IS_GEN7(dev))
707 return 200; /* SNB & IVB eDP input clock at 400Mhz */
708 else
709 return 225; /* eDP input clock at 450Mhz */
710 } else {
711 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
712 }
713}
714
715static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
716{
717 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
718 struct drm_device *dev = intel_dig_port->base.base.dev;
719 struct drm_i915_private *dev_priv = dev->dev_private;
720
721 if (intel_dig_port->port == PORT_A) {
722 if (index)
723 return 0;
724 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
725 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
726 /* Workaround for non-ULT HSW */
727 switch (index) {
728 case 0: return 63;
729 case 1: return 72;
730 default: return 0;
731 }
732 } else {
733 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
734 }
735}
736
737static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
738{
739 return index ? 0 : 100;
740}
741
742static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
743{
744 /*
745 * SKL doesn't need us to program the AUX clock divider (Hardware will
746 * derive the clock from CDCLK automatically). We still implement the
747 * get_aux_clock_divider vfunc to plug-in into the existing code.
748 */
749 return index ? 0 : 1;
750}
751
752static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
753 bool has_aux_irq,
754 int send_bytes,
755 uint32_t aux_clock_divider)
756{
757 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
758 struct drm_device *dev = intel_dig_port->base.base.dev;
759 uint32_t precharge, timeout;
760
761 if (IS_GEN6(dev))
762 precharge = 3;
763 else
764 precharge = 5;
765
766 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
767 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
768 else
769 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
770
771 return DP_AUX_CH_CTL_SEND_BUSY |
772 DP_AUX_CH_CTL_DONE |
773 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
774 DP_AUX_CH_CTL_TIME_OUT_ERROR |
775 timeout |
776 DP_AUX_CH_CTL_RECEIVE_ERROR |
777 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
778 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
779 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
780}
781
782static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
783 bool has_aux_irq,
784 int send_bytes,
785 uint32_t unused)
786{
787 return DP_AUX_CH_CTL_SEND_BUSY |
788 DP_AUX_CH_CTL_DONE |
789 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
790 DP_AUX_CH_CTL_TIME_OUT_ERROR |
791 DP_AUX_CH_CTL_TIME_OUT_1600us |
792 DP_AUX_CH_CTL_RECEIVE_ERROR |
793 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
794 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
795}
796
797static int
798intel_dp_aux_ch(struct intel_dp *intel_dp,
799 const uint8_t *send, int send_bytes,
800 uint8_t *recv, int recv_size)
801{
802 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
803 struct drm_device *dev = intel_dig_port->base.base.dev;
804 struct drm_i915_private *dev_priv = dev->dev_private;
805 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
806 uint32_t ch_data = ch_ctl + 4;
807 uint32_t aux_clock_divider;
808 int i, ret, recv_bytes;
809 uint32_t status;
810 int try, clock = 0;
811 bool has_aux_irq = HAS_AUX_IRQ(dev);
812 bool vdd;
813
814 pps_lock(intel_dp);
815
816 /*
817 * We will be called with VDD already enabled for dpcd/edid/oui reads.
818 * In such cases we want to leave VDD enabled and it's up to upper layers
819 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
820 * ourselves.
821 */
822 vdd = edp_panel_vdd_on(intel_dp);
823
824 /* dp aux is extremely sensitive to irq latency, hence request the
825 * lowest possible wakeup latency and so prevent the cpu from going into
826 * deep sleep states.
827 */
828 pm_qos_update_request(&dev_priv->pm_qos, 0);
829
830 intel_dp_check_edp(intel_dp);
831
832 intel_aux_display_runtime_get(dev_priv);
833
834 /* Try to wait for any previous AUX channel activity */
835 for (try = 0; try < 3; try++) {
836 status = I915_READ_NOTRACE(ch_ctl);
837 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
838 break;
839 msleep(1);
840 }
841
842 if (try == 3) {
843 WARN(1, "dp_aux_ch not started status 0x%08x\n",
844 I915_READ(ch_ctl));
845 ret = -EBUSY;
846 goto out;
847 }
848
849 /* Only 5 data registers! */
850 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
851 ret = -E2BIG;
852 goto out;
853 }
854
855 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
856 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
857 has_aux_irq,
858 send_bytes,
859 aux_clock_divider);
860
861 /* Must try at least 3 times according to DP spec */
862 for (try = 0; try < 5; try++) {
863 /* Load the send data into the aux channel data registers */
864 for (i = 0; i < send_bytes; i += 4)
865 I915_WRITE(ch_data + i,
866 pack_aux(send + i, send_bytes - i));
867
868 /* Send the command and wait for it to complete */
869 I915_WRITE(ch_ctl, send_ctl);
870
871 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
872
873 /* Clear done status and any errors */
874 I915_WRITE(ch_ctl,
875 status |
876 DP_AUX_CH_CTL_DONE |
877 DP_AUX_CH_CTL_TIME_OUT_ERROR |
878 DP_AUX_CH_CTL_RECEIVE_ERROR);
879
880 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
881 DP_AUX_CH_CTL_RECEIVE_ERROR))
882 continue;
883 if (status & DP_AUX_CH_CTL_DONE)
884 break;
885 }
886 if (status & DP_AUX_CH_CTL_DONE)
887 break;
888 }
889
890 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
891 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
892 ret = -EBUSY;
893 goto out;
894 }
895
896 /* Check for timeout or receive error.
897 * Timeouts occur when the sink is not connected
898 */
899 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
900 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
901 ret = -EIO;
902 goto out;
903 }
904
905 /* Timeouts occur when the device isn't connected, so they're
906 * "normal" -- don't fill the kernel log with these */
907 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
908 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
909 ret = -ETIMEDOUT;
910 goto out;
911 }
912
913 /* Unload any bytes sent back from the other side */
914 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
915 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
916 if (recv_bytes > recv_size)
917 recv_bytes = recv_size;
918
919 for (i = 0; i < recv_bytes; i += 4)
920 unpack_aux(I915_READ(ch_data + i),
921 recv + i, recv_bytes - i);
922
923 ret = recv_bytes;
924out:
925 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
926 intel_aux_display_runtime_put(dev_priv);
927
928 if (vdd)
929 edp_panel_vdd_off(intel_dp, false);
930
931 pps_unlock(intel_dp);
932
933 return ret;
934}
935
936#define BARE_ADDRESS_SIZE 3
937#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
938static ssize_t
939intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
940{
941 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
942 uint8_t txbuf[20], rxbuf[20];
943 size_t txsize, rxsize;
944 int ret;
945
946 txbuf[0] = msg->request << 4;
947 txbuf[1] = msg->address >> 8;
948 txbuf[2] = msg->address & 0xff;
949 txbuf[3] = msg->size - 1;
950
951 switch (msg->request & ~DP_AUX_I2C_MOT) {
952 case DP_AUX_NATIVE_WRITE:
953 case DP_AUX_I2C_WRITE:
954 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
955 rxsize = 1;
956
957 if (WARN_ON(txsize > 20))
958 return -E2BIG;
959
960 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
961
962 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
963 if (ret > 0) {
964 msg->reply = rxbuf[0] >> 4;
965
966 /* Return payload size. */
967 ret = msg->size;
968 }
969 break;
970
971 case DP_AUX_NATIVE_READ:
972 case DP_AUX_I2C_READ:
973 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
974 rxsize = msg->size + 1;
975
976 if (WARN_ON(rxsize > 20))
977 return -E2BIG;
978
979 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
980 if (ret > 0) {
981 msg->reply = rxbuf[0] >> 4;
982 /*
983 * Assume happy day, and copy the data. The caller is
984 * expected to check msg->reply before touching it.
985 *
986 * Return payload size.
987 */
988 ret--;
989 memcpy(msg->buffer, rxbuf + 1, ret);
990 }
991 break;
992
993 default:
994 ret = -EINVAL;
995 break;
996 }
997
998 return ret;
999}
1000
1001static void
1002intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1003{
1004 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1005 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1006 enum port port = intel_dig_port->port;
1007 const char *name = NULL;
1008 int ret;
1009
1010 switch (port) {
1011 case PORT_A:
1012 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
1013 name = "DPDDC-A";
1014 break;
1015 case PORT_B:
1016 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
1017 name = "DPDDC-B";
1018 break;
1019 case PORT_C:
1020 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
1021 name = "DPDDC-C";
1022 break;
1023 case PORT_D:
1024 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
1025 name = "DPDDC-D";
1026 break;
1027 default:
1028 BUG();
1029 }
1030
1031 /*
1032 * The AUX_CTL register is usually DP_CTL + 0x10.
1033 *
1034 * On Haswell and Broadwell though:
1035 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1036 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1037 *
1038 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1039 */
1040 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1041 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
1042
1043 intel_dp->aux.name = name;
1044 intel_dp->aux.dev = dev->dev;
1045 intel_dp->aux.transfer = intel_dp_aux_transfer;
1046
1047 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1048 connector->base.kdev->kobj.name);
1049
1050 ret = drm_dp_aux_register(&intel_dp->aux);
1051 if (ret < 0) {
1052 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1053 name, ret);
1054 return;
1055 }
1056
1057 ret = sysfs_create_link(&connector->base.kdev->kobj,
1058 &intel_dp->aux.ddc.dev.kobj,
1059 intel_dp->aux.ddc.dev.kobj.name);
1060 if (ret < 0) {
1061 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
1062 drm_dp_aux_unregister(&intel_dp->aux);
1063 }
1064}
1065
1066static void
1067intel_dp_connector_unregister(struct intel_connector *intel_connector)
1068{
1069 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1070
1071 if (!intel_connector->mst_port)
1072 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1073 intel_dp->aux.ddc.dev.kobj.name);
1074 intel_connector_unregister(intel_connector);
1075}
1076
1077static void
1078hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
1079{
1080 switch (link_bw) {
1081 case DP_LINK_BW_1_62:
1082 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1083 break;
1084 case DP_LINK_BW_2_7:
1085 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1086 break;
1087 case DP_LINK_BW_5_4:
1088 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1089 break;
1090 }
1091}
1092
1093static void
1094intel_dp_set_clock(struct intel_encoder *encoder,
1095 struct intel_crtc_config *pipe_config, int link_bw)
1096{
1097 struct drm_device *dev = encoder->base.dev;
1098 const struct dp_link_dpll *divisor = NULL;
1099 int i, count = 0;
1100
1101 if (IS_G4X(dev)) {
1102 divisor = gen4_dpll;
1103 count = ARRAY_SIZE(gen4_dpll);
1104 } else if (HAS_PCH_SPLIT(dev)) {
1105 divisor = pch_dpll;
1106 count = ARRAY_SIZE(pch_dpll);
1107 } else if (IS_CHERRYVIEW(dev)) {
1108 divisor = chv_dpll;
1109 count = ARRAY_SIZE(chv_dpll);
1110 } else if (IS_VALLEYVIEW(dev)) {
1111 divisor = vlv_dpll;
1112 count = ARRAY_SIZE(vlv_dpll);
1113 }
1114
1115 if (divisor && count) {
1116 for (i = 0; i < count; i++) {
1117 if (link_bw == divisor[i].link_bw) {
1118 pipe_config->dpll = divisor[i].dpll;
1119 pipe_config->clock_set = true;
1120 break;
1121 }
1122 }
1123 }
1124}
1125
1126bool
1127intel_dp_compute_config(struct intel_encoder *encoder,
1128 struct intel_crtc_config *pipe_config)
1129{
1130 struct drm_device *dev = encoder->base.dev;
1131 struct drm_i915_private *dev_priv = dev->dev_private;
1132 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
1133 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1134 enum port port = dp_to_dig_port(intel_dp)->port;
1135 struct intel_crtc *intel_crtc = encoder->new_crtc;
1136 struct intel_connector *intel_connector = intel_dp->attached_connector;
1137 int lane_count, clock;
1138 int min_lane_count = 1;
1139 int max_lane_count = intel_dp_max_lane_count(intel_dp);
1140 /* Conveniently, the link BW constants become indices with a shift...*/
1141 int min_clock = 0;
1142 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
1143 int bpp, mode_rate;
1144 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
1145 int link_avail, link_clock;
1146
1147 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1148 pipe_config->has_pch_encoder = true;
1149
1150 pipe_config->has_dp_encoder = true;
1151 pipe_config->has_drrs = false;
1152 pipe_config->has_audio = intel_dp->has_audio;
1153
1154 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1155 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1156 adjusted_mode);
1157 if (!HAS_PCH_SPLIT(dev))
1158 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1159 intel_connector->panel.fitting_mode);
1160 else
1161 intel_pch_panel_fitting(intel_crtc, pipe_config,
1162 intel_connector->panel.fitting_mode);
1163 }
1164
1165 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1166 return false;
1167
1168 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1169 "max bw %02x pixel clock %iKHz\n",
1170 max_lane_count, bws[max_clock],
1171 adjusted_mode->crtc_clock);
1172
1173 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1174 * bpc in between. */
1175 bpp = pipe_config->pipe_bpp;
1176 if (is_edp(intel_dp)) {
1177 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1178 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1179 dev_priv->vbt.edp_bpp);
1180 bpp = dev_priv->vbt.edp_bpp;
1181 }
1182
1183 /*
1184 * Use the maximum clock and number of lanes the eDP panel
1185 * advertizes being capable of. The panels are generally
1186 * designed to support only a single clock and lane
1187 * configuration, and typically these values correspond to the
1188 * native resolution of the panel.
1189 */
1190 min_lane_count = max_lane_count;
1191 min_clock = max_clock;
1192 }
1193
1194 for (; bpp >= 6*3; bpp -= 2*3) {
1195 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1196 bpp);
1197
1198 for (clock = min_clock; clock <= max_clock; clock++) {
1199 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
1200 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1201 link_avail = intel_dp_max_data_rate(link_clock,
1202 lane_count);
1203
1204 if (mode_rate <= link_avail) {
1205 goto found;
1206 }
1207 }
1208 }
1209 }
1210
1211 return false;
1212
1213found:
1214 if (intel_dp->color_range_auto) {
1215 /*
1216 * See:
1217 * CEA-861-E - 5.1 Default Encoding Parameters
1218 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1219 */
1220 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
1221 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1222 else
1223 intel_dp->color_range = 0;
1224 }
1225
1226 if (intel_dp->color_range)
1227 pipe_config->limited_color_range = true;
1228
1229 intel_dp->link_bw = bws[clock];
1230 intel_dp->lane_count = lane_count;
1231 pipe_config->pipe_bpp = bpp;
1232 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
1233
1234 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1235 intel_dp->link_bw, intel_dp->lane_count,
1236 pipe_config->port_clock, bpp);
1237 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1238 mode_rate, link_avail);
1239
1240 intel_link_compute_m_n(bpp, lane_count,
1241 adjusted_mode->crtc_clock,
1242 pipe_config->port_clock,
1243 &pipe_config->dp_m_n);
1244
1245 if (intel_connector->panel.downclock_mode != NULL &&
1246 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
1247 pipe_config->has_drrs = true;
1248 intel_link_compute_m_n(bpp, lane_count,
1249 intel_connector->panel.downclock_mode->clock,
1250 pipe_config->port_clock,
1251 &pipe_config->dp_m2_n2);
1252 }
1253
1254 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1255 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1256 else
1257 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
1258
1259 return true;
1260}
1261
1262static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
1263{
1264 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1265 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1266 struct drm_device *dev = crtc->base.dev;
1267 struct drm_i915_private *dev_priv = dev->dev_private;
1268 u32 dpa_ctl;
1269
1270 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
1271 dpa_ctl = I915_READ(DP_A);
1272 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1273
1274 if (crtc->config.port_clock == 162000) {
1275 /* For a long time we've carried around a ILK-DevA w/a for the
1276 * 160MHz clock. If we're really unlucky, it's still required.
1277 */
1278 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1279 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1280 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1281 } else {
1282 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1283 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1284 }
1285
1286 I915_WRITE(DP_A, dpa_ctl);
1287
1288 POSTING_READ(DP_A);
1289 udelay(500);
1290}
1291
1292static void intel_dp_prepare(struct intel_encoder *encoder)
1293{
1294 struct drm_device *dev = encoder->base.dev;
1295 struct drm_i915_private *dev_priv = dev->dev_private;
1296 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1297 enum port port = dp_to_dig_port(intel_dp)->port;
1298 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1299 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
1300
1301 /*
1302 * There are four kinds of DP registers:
1303 *
1304 * IBX PCH
1305 * SNB CPU
1306 * IVB CPU
1307 * CPT PCH
1308 *
1309 * IBX PCH and CPU are the same for almost everything,
1310 * except that the CPU DP PLL is configured in this
1311 * register
1312 *
1313 * CPT PCH is quite different, having many bits moved
1314 * to the TRANS_DP_CTL register instead. That
1315 * configuration happens (oddly) in ironlake_pch_enable
1316 */
1317
1318 /* Preserve the BIOS-computed detected bit. This is
1319 * supposed to be read-only.
1320 */
1321 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1322
1323 /* Handle DP bits in common between all three register formats */
1324 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1325 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1326
1327 if (crtc->config.has_audio) {
1328 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1329 pipe_name(crtc->pipe));
1330 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1331 intel_write_eld(encoder);
1332 }
1333
1334 /* Split out the IBX/CPU vs CPT settings */
1335
1336 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1337 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1338 intel_dp->DP |= DP_SYNC_HS_HIGH;
1339 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1340 intel_dp->DP |= DP_SYNC_VS_HIGH;
1341 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1342
1343 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1344 intel_dp->DP |= DP_ENHANCED_FRAMING;
1345
1346 intel_dp->DP |= crtc->pipe << 29;
1347 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1348 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1349 intel_dp->DP |= intel_dp->color_range;
1350
1351 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1352 intel_dp->DP |= DP_SYNC_HS_HIGH;
1353 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1354 intel_dp->DP |= DP_SYNC_VS_HIGH;
1355 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1356
1357 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1358 intel_dp->DP |= DP_ENHANCED_FRAMING;
1359
1360 if (!IS_CHERRYVIEW(dev)) {
1361 if (crtc->pipe == 1)
1362 intel_dp->DP |= DP_PIPEB_SELECT;
1363 } else {
1364 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1365 }
1366 } else {
1367 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1368 }
1369}
1370
1371#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1372#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1373
1374#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1375#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1376
1377#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1378#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1379
1380static void wait_panel_status(struct intel_dp *intel_dp,
1381 u32 mask,
1382 u32 value)
1383{
1384 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1385 struct drm_i915_private *dev_priv = dev->dev_private;
1386 u32 pp_stat_reg, pp_ctrl_reg;
1387
1388 lockdep_assert_held(&dev_priv->pps_mutex);
1389
1390 pp_stat_reg = _pp_stat_reg(intel_dp);
1391 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1392
1393 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1394 mask, value,
1395 I915_READ(pp_stat_reg),
1396 I915_READ(pp_ctrl_reg));
1397
1398 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1399 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1400 I915_READ(pp_stat_reg),
1401 I915_READ(pp_ctrl_reg));
1402 }
1403
1404 DRM_DEBUG_KMS("Wait complete\n");
1405}
1406
1407static void wait_panel_on(struct intel_dp *intel_dp)
1408{
1409 DRM_DEBUG_KMS("Wait for panel power on\n");
1410 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1411}
1412
1413static void wait_panel_off(struct intel_dp *intel_dp)
1414{
1415 DRM_DEBUG_KMS("Wait for panel power off time\n");
1416 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1417}
1418
1419static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1420{
1421 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1422
1423 /* When we disable the VDD override bit last we have to do the manual
1424 * wait. */
1425 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1426 intel_dp->panel_power_cycle_delay);
1427
1428 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1429}
1430
1431static void wait_backlight_on(struct intel_dp *intel_dp)
1432{
1433 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1434 intel_dp->backlight_on_delay);
1435}
1436
1437static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1438{
1439 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1440 intel_dp->backlight_off_delay);
1441}
1442
1443/* Read the current pp_control value, unlocking the register if it
1444 * is locked
1445 */
1446
1447static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1448{
1449 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1450 struct drm_i915_private *dev_priv = dev->dev_private;
1451 u32 control;
1452
1453 lockdep_assert_held(&dev_priv->pps_mutex);
1454
1455 control = I915_READ(_pp_ctrl_reg(intel_dp));
1456 control &= ~PANEL_UNLOCK_MASK;
1457 control |= PANEL_UNLOCK_REGS;
1458 return control;
1459}
1460
1461/*
1462 * Must be paired with edp_panel_vdd_off().
1463 * Must hold pps_mutex around the whole on/off sequence.
1464 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1465 */
1466static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1467{
1468 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1469 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1470 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1471 struct drm_i915_private *dev_priv = dev->dev_private;
1472 enum intel_display_power_domain power_domain;
1473 u32 pp;
1474 u32 pp_stat_reg, pp_ctrl_reg;
1475 bool need_to_disable = !intel_dp->want_panel_vdd;
1476
1477 lockdep_assert_held(&dev_priv->pps_mutex);
1478
1479 if (!is_edp(intel_dp))
1480 return false;
1481
1482 intel_dp->want_panel_vdd = true;
1483
1484 if (edp_have_panel_vdd(intel_dp))
1485 return need_to_disable;
1486
1487 power_domain = intel_display_port_power_domain(intel_encoder);
1488 intel_display_power_get(dev_priv, power_domain);
1489
1490 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1491 port_name(intel_dig_port->port));
1492
1493 if (!edp_have_panel_power(intel_dp))
1494 wait_panel_power_cycle(intel_dp);
1495
1496 pp = ironlake_get_pp_control(intel_dp);
1497 pp |= EDP_FORCE_VDD;
1498
1499 pp_stat_reg = _pp_stat_reg(intel_dp);
1500 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1501
1502 I915_WRITE(pp_ctrl_reg, pp);
1503 POSTING_READ(pp_ctrl_reg);
1504 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1505 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1506 /*
1507 * If the panel wasn't on, delay before accessing aux channel
1508 */
1509 if (!edp_have_panel_power(intel_dp)) {
1510 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1511 port_name(intel_dig_port->port));
1512 msleep(intel_dp->panel_power_up_delay);
1513 }
1514
1515 return need_to_disable;
1516}
1517
1518/*
1519 * Must be paired with intel_edp_panel_vdd_off() or
1520 * intel_edp_panel_off().
1521 * Nested calls to these functions are not allowed since
1522 * we drop the lock. Caller must use some higher level
1523 * locking to prevent nested calls from other threads.
1524 */
1525void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1526{
1527 bool vdd;
1528
1529 if (!is_edp(intel_dp))
1530 return;
1531
1532 pps_lock(intel_dp);
1533 vdd = edp_panel_vdd_on(intel_dp);
1534 pps_unlock(intel_dp);
1535
1536 WARN(!vdd, "eDP port %c VDD already requested on\n",
1537 port_name(dp_to_dig_port(intel_dp)->port));
1538}
1539
1540static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1541{
1542 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1543 struct drm_i915_private *dev_priv = dev->dev_private;
1544 struct intel_digital_port *intel_dig_port =
1545 dp_to_dig_port(intel_dp);
1546 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1547 enum intel_display_power_domain power_domain;
1548 u32 pp;
1549 u32 pp_stat_reg, pp_ctrl_reg;
1550
1551 lockdep_assert_held(&dev_priv->pps_mutex);
1552
1553 WARN_ON(intel_dp->want_panel_vdd);
1554
1555 if (!edp_have_panel_vdd(intel_dp))
1556 return;
1557
1558 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1559 port_name(intel_dig_port->port));
1560
1561 pp = ironlake_get_pp_control(intel_dp);
1562 pp &= ~EDP_FORCE_VDD;
1563
1564 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1565 pp_stat_reg = _pp_stat_reg(intel_dp);
1566
1567 I915_WRITE(pp_ctrl_reg, pp);
1568 POSTING_READ(pp_ctrl_reg);
1569
1570 /* Make sure sequencer is idle before allowing subsequent activity */
1571 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1572 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1573
1574 if ((pp & POWER_TARGET_ON) == 0)
1575 intel_dp->last_power_cycle = jiffies;
1576
1577 power_domain = intel_display_port_power_domain(intel_encoder);
1578 intel_display_power_put(dev_priv, power_domain);
1579}
1580
1581static void edp_panel_vdd_work(struct work_struct *__work)
1582{
1583 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1584 struct intel_dp, panel_vdd_work);
1585
1586 pps_lock(intel_dp);
1587 if (!intel_dp->want_panel_vdd)
1588 edp_panel_vdd_off_sync(intel_dp);
1589 pps_unlock(intel_dp);
1590}
1591
1592static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1593{
1594 unsigned long delay;
1595
1596 /*
1597 * Queue the timer to fire a long time from now (relative to the power
1598 * down delay) to keep the panel power up across a sequence of
1599 * operations.
1600 */
1601 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1602 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1603}
1604
1605/*
1606 * Must be paired with edp_panel_vdd_on().
1607 * Must hold pps_mutex around the whole on/off sequence.
1608 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1609 */
1610static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1611{
1612 struct drm_i915_private *dev_priv =
1613 intel_dp_to_dev(intel_dp)->dev_private;
1614
1615 lockdep_assert_held(&dev_priv->pps_mutex);
1616
1617 if (!is_edp(intel_dp))
1618 return;
1619
1620 WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
1621 port_name(dp_to_dig_port(intel_dp)->port));
1622
1623 intel_dp->want_panel_vdd = false;
1624
1625 if (sync)
1626 edp_panel_vdd_off_sync(intel_dp);
1627 else
1628 edp_panel_vdd_schedule_off(intel_dp);
1629}
1630
1631static void edp_panel_on(struct intel_dp *intel_dp)
1632{
1633 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1634 struct drm_i915_private *dev_priv = dev->dev_private;
1635 u32 pp;
1636 u32 pp_ctrl_reg;
1637
1638 lockdep_assert_held(&dev_priv->pps_mutex);
1639
1640 if (!is_edp(intel_dp))
1641 return;
1642
1643 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1644 port_name(dp_to_dig_port(intel_dp)->port));
1645
1646 if (WARN(edp_have_panel_power(intel_dp),
1647 "eDP port %c panel power already on\n",
1648 port_name(dp_to_dig_port(intel_dp)->port)))
1649 return;
1650
1651 wait_panel_power_cycle(intel_dp);
1652
1653 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1654 pp = ironlake_get_pp_control(intel_dp);
1655 if (IS_GEN5(dev)) {
1656 /* ILK workaround: disable reset around power sequence */
1657 pp &= ~PANEL_POWER_RESET;
1658 I915_WRITE(pp_ctrl_reg, pp);
1659 POSTING_READ(pp_ctrl_reg);
1660 }
1661
1662 pp |= POWER_TARGET_ON;
1663 if (!IS_GEN5(dev))
1664 pp |= PANEL_POWER_RESET;
1665
1666 I915_WRITE(pp_ctrl_reg, pp);
1667 POSTING_READ(pp_ctrl_reg);
1668
1669 wait_panel_on(intel_dp);
1670 intel_dp->last_power_on = jiffies;
1671
1672 if (IS_GEN5(dev)) {
1673 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1674 I915_WRITE(pp_ctrl_reg, pp);
1675 POSTING_READ(pp_ctrl_reg);
1676 }
1677}
1678
1679void intel_edp_panel_on(struct intel_dp *intel_dp)
1680{
1681 if (!is_edp(intel_dp))
1682 return;
1683
1684 pps_lock(intel_dp);
1685 edp_panel_on(intel_dp);
1686 pps_unlock(intel_dp);
1687}
1688
1689
1690static void edp_panel_off(struct intel_dp *intel_dp)
1691{
1692 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1693 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1694 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1695 struct drm_i915_private *dev_priv = dev->dev_private;
1696 enum intel_display_power_domain power_domain;
1697 u32 pp;
1698 u32 pp_ctrl_reg;
1699
1700 lockdep_assert_held(&dev_priv->pps_mutex);
1701
1702 if (!is_edp(intel_dp))
1703 return;
1704
1705 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1706 port_name(dp_to_dig_port(intel_dp)->port));
1707
1708 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
1709 port_name(dp_to_dig_port(intel_dp)->port));
1710
1711 pp = ironlake_get_pp_control(intel_dp);
1712 /* We need to switch off panel power _and_ force vdd, for otherwise some
1713 * panels get very unhappy and cease to work. */
1714 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1715 EDP_BLC_ENABLE);
1716
1717 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1718
1719 intel_dp->want_panel_vdd = false;
1720
1721 I915_WRITE(pp_ctrl_reg, pp);
1722 POSTING_READ(pp_ctrl_reg);
1723
1724 intel_dp->last_power_cycle = jiffies;
1725 wait_panel_off(intel_dp);
1726
1727 /* We got a reference when we enabled the VDD. */
1728 power_domain = intel_display_port_power_domain(intel_encoder);
1729 intel_display_power_put(dev_priv, power_domain);
1730}
1731
1732void intel_edp_panel_off(struct intel_dp *intel_dp)
1733{
1734 if (!is_edp(intel_dp))
1735 return;
1736
1737 pps_lock(intel_dp);
1738 edp_panel_off(intel_dp);
1739 pps_unlock(intel_dp);
1740}
1741
1742/* Enable backlight in the panel power control. */
1743static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
1744{
1745 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1746 struct drm_device *dev = intel_dig_port->base.base.dev;
1747 struct drm_i915_private *dev_priv = dev->dev_private;
1748 u32 pp;
1749 u32 pp_ctrl_reg;
1750
1751 /*
1752 * If we enable the backlight right away following a panel power
1753 * on, we may see slight flicker as the panel syncs with the eDP
1754 * link. So delay a bit to make sure the image is solid before
1755 * allowing it to appear.
1756 */
1757 wait_backlight_on(intel_dp);
1758
1759 pps_lock(intel_dp);
1760
1761 pp = ironlake_get_pp_control(intel_dp);
1762 pp |= EDP_BLC_ENABLE;
1763
1764 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1765
1766 I915_WRITE(pp_ctrl_reg, pp);
1767 POSTING_READ(pp_ctrl_reg);
1768
1769 pps_unlock(intel_dp);
1770}
1771
1772/* Enable backlight PWM and backlight PP control. */
1773void intel_edp_backlight_on(struct intel_dp *intel_dp)
1774{
1775 if (!is_edp(intel_dp))
1776 return;
1777
1778 DRM_DEBUG_KMS("\n");
1779
1780 intel_panel_enable_backlight(intel_dp->attached_connector);
1781 _intel_edp_backlight_on(intel_dp);
1782}
1783
1784/* Disable backlight in the panel power control. */
1785static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
1786{
1787 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1788 struct drm_i915_private *dev_priv = dev->dev_private;
1789 u32 pp;
1790 u32 pp_ctrl_reg;
1791
1792 if (!is_edp(intel_dp))
1793 return;
1794
1795 pps_lock(intel_dp);
1796
1797 pp = ironlake_get_pp_control(intel_dp);
1798 pp &= ~EDP_BLC_ENABLE;
1799
1800 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1801
1802 I915_WRITE(pp_ctrl_reg, pp);
1803 POSTING_READ(pp_ctrl_reg);
1804
1805 pps_unlock(intel_dp);
1806
1807 intel_dp->last_backlight_off = jiffies;
1808 edp_wait_backlight_off(intel_dp);
1809}
1810
1811/* Disable backlight PP control and backlight PWM. */
1812void intel_edp_backlight_off(struct intel_dp *intel_dp)
1813{
1814 if (!is_edp(intel_dp))
1815 return;
1816
1817 DRM_DEBUG_KMS("\n");
1818
1819 _intel_edp_backlight_off(intel_dp);
1820 intel_panel_disable_backlight(intel_dp->attached_connector);
1821}
1822
1823/*
1824 * Hook for controlling the panel power control backlight through the bl_power
1825 * sysfs attribute. Take care to handle multiple calls.
1826 */
1827static void intel_edp_backlight_power(struct intel_connector *connector,
1828 bool enable)
1829{
1830 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
1831 bool is_enabled;
1832
1833 pps_lock(intel_dp);
1834 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1835 pps_unlock(intel_dp);
1836
1837 if (is_enabled == enable)
1838 return;
1839
1840 DRM_DEBUG_KMS("panel power control backlight %s\n",
1841 enable ? "enable" : "disable");
1842
1843 if (enable)
1844 _intel_edp_backlight_on(intel_dp);
1845 else
1846 _intel_edp_backlight_off(intel_dp);
1847}
1848
1849static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1850{
1851 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1852 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1853 struct drm_device *dev = crtc->dev;
1854 struct drm_i915_private *dev_priv = dev->dev_private;
1855 u32 dpa_ctl;
1856
1857 assert_pipe_disabled(dev_priv,
1858 to_intel_crtc(crtc)->pipe);
1859
1860 DRM_DEBUG_KMS("\n");
1861 dpa_ctl = I915_READ(DP_A);
1862 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1863 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1864
1865 /* We don't adjust intel_dp->DP while tearing down the link, to
1866 * facilitate link retraining (e.g. after hotplug). Hence clear all
1867 * enable bits here to ensure that we don't enable too much. */
1868 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1869 intel_dp->DP |= DP_PLL_ENABLE;
1870 I915_WRITE(DP_A, intel_dp->DP);
1871 POSTING_READ(DP_A);
1872 udelay(200);
1873}
1874
1875static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1876{
1877 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1878 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1879 struct drm_device *dev = crtc->dev;
1880 struct drm_i915_private *dev_priv = dev->dev_private;
1881 u32 dpa_ctl;
1882
1883 assert_pipe_disabled(dev_priv,
1884 to_intel_crtc(crtc)->pipe);
1885
1886 dpa_ctl = I915_READ(DP_A);
1887 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1888 "dp pll off, should be on\n");
1889 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1890
1891 /* We can't rely on the value tracked for the DP register in
1892 * intel_dp->DP because link_down must not change that (otherwise link
1893 * re-training will fail. */
1894 dpa_ctl &= ~DP_PLL_ENABLE;
1895 I915_WRITE(DP_A, dpa_ctl);
1896 POSTING_READ(DP_A);
1897 udelay(200);
1898}
1899
1900/* If the sink supports it, try to set the power state appropriately */
1901void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1902{
1903 int ret, i;
1904
1905 /* Should have a valid DPCD by this point */
1906 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1907 return;
1908
1909 if (mode != DRM_MODE_DPMS_ON) {
1910 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1911 DP_SET_POWER_D3);
1912 } else {
1913 /*
1914 * When turning on, we need to retry for 1ms to give the sink
1915 * time to wake up.
1916 */
1917 for (i = 0; i < 3; i++) {
1918 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1919 DP_SET_POWER_D0);
1920 if (ret == 1)
1921 break;
1922 msleep(1);
1923 }
1924 }
1925
1926 if (ret != 1)
1927 DRM_DEBUG_KMS("failed to %s sink power state\n",
1928 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
1929}
1930
1931static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1932 enum pipe *pipe)
1933{
1934 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1935 enum port port = dp_to_dig_port(intel_dp)->port;
1936 struct drm_device *dev = encoder->base.dev;
1937 struct drm_i915_private *dev_priv = dev->dev_private;
1938 enum intel_display_power_domain power_domain;
1939 u32 tmp;
1940
1941 power_domain = intel_display_port_power_domain(encoder);
1942 if (!intel_display_power_is_enabled(dev_priv, power_domain))
1943 return false;
1944
1945 tmp = I915_READ(intel_dp->output_reg);
1946
1947 if (!(tmp & DP_PORT_EN))
1948 return false;
1949
1950 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1951 *pipe = PORT_TO_PIPE_CPT(tmp);
1952 } else if (IS_CHERRYVIEW(dev)) {
1953 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
1954 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1955 *pipe = PORT_TO_PIPE(tmp);
1956 } else {
1957 u32 trans_sel;
1958 u32 trans_dp;
1959 int i;
1960
1961 switch (intel_dp->output_reg) {
1962 case PCH_DP_B:
1963 trans_sel = TRANS_DP_PORT_SEL_B;
1964 break;
1965 case PCH_DP_C:
1966 trans_sel = TRANS_DP_PORT_SEL_C;
1967 break;
1968 case PCH_DP_D:
1969 trans_sel = TRANS_DP_PORT_SEL_D;
1970 break;
1971 default:
1972 return true;
1973 }
1974
1975 for_each_pipe(dev_priv, i) {
1976 trans_dp = I915_READ(TRANS_DP_CTL(i));
1977 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1978 *pipe = i;
1979 return true;
1980 }
1981 }
1982
1983 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1984 intel_dp->output_reg);
1985 }
1986
1987 return true;
1988}
1989
1990static void intel_dp_get_config(struct intel_encoder *encoder,
1991 struct intel_crtc_config *pipe_config)
1992{
1993 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1994 u32 tmp, flags = 0;
1995 struct drm_device *dev = encoder->base.dev;
1996 struct drm_i915_private *dev_priv = dev->dev_private;
1997 enum port port = dp_to_dig_port(intel_dp)->port;
1998 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1999 int dotclock;
2000
2001 tmp = I915_READ(intel_dp->output_reg);
2002 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
2003 pipe_config->has_audio = true;
2004
2005 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
2006 if (tmp & DP_SYNC_HS_HIGH)
2007 flags |= DRM_MODE_FLAG_PHSYNC;
2008 else
2009 flags |= DRM_MODE_FLAG_NHSYNC;
2010
2011 if (tmp & DP_SYNC_VS_HIGH)
2012 flags |= DRM_MODE_FLAG_PVSYNC;
2013 else
2014 flags |= DRM_MODE_FLAG_NVSYNC;
2015 } else {
2016 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2017 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2018 flags |= DRM_MODE_FLAG_PHSYNC;
2019 else
2020 flags |= DRM_MODE_FLAG_NHSYNC;
2021
2022 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2023 flags |= DRM_MODE_FLAG_PVSYNC;
2024 else
2025 flags |= DRM_MODE_FLAG_NVSYNC;
2026 }
2027
2028 pipe_config->adjusted_mode.flags |= flags;
2029
2030 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2031 tmp & DP_COLOR_RANGE_16_235)
2032 pipe_config->limited_color_range = true;
2033
2034 pipe_config->has_dp_encoder = true;
2035
2036 intel_dp_get_m_n(crtc, pipe_config);
2037
2038 if (port == PORT_A) {
2039 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2040 pipe_config->port_clock = 162000;
2041 else
2042 pipe_config->port_clock = 270000;
2043 }
2044
2045 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2046 &pipe_config->dp_m_n);
2047
2048 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2049 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2050
2051 pipe_config->adjusted_mode.crtc_clock = dotclock;
2052
2053 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2054 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2055 /*
2056 * This is a big fat ugly hack.
2057 *
2058 * Some machines in UEFI boot mode provide us a VBT that has 18
2059 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2060 * unknown we fail to light up. Yet the same BIOS boots up with
2061 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2062 * max, not what it tells us to use.
2063 *
2064 * Note: This will still be broken if the eDP panel is not lit
2065 * up by the BIOS, and thus we can't get the mode at module
2066 * load.
2067 */
2068 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2069 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2070 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2071 }
2072}
2073
2074static bool is_edp_psr(struct intel_dp *intel_dp)
2075{
2076 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2077}
2078
2079static bool intel_edp_is_psr_enabled(struct drm_device *dev)
2080{
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082
2083 if (!HAS_PSR(dev))
2084 return false;
2085
2086 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2087}
2088
2089static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
2090 struct edp_vsc_psr *vsc_psr)
2091{
2092 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2093 struct drm_device *dev = dig_port->base.base.dev;
2094 struct drm_i915_private *dev_priv = dev->dev_private;
2095 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
2096 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
2097 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
2098 uint32_t *data = (uint32_t *) vsc_psr;
2099 unsigned int i;
2100
2101 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
2102 the video DIP being updated before program video DIP data buffer
2103 registers for DIP being updated. */
2104 I915_WRITE(ctl_reg, 0);
2105 POSTING_READ(ctl_reg);
2106
2107 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
2108 if (i < sizeof(struct edp_vsc_psr))
2109 I915_WRITE(data_reg + i, *data++);
2110 else
2111 I915_WRITE(data_reg + i, 0);
2112 }
2113
2114 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
2115 POSTING_READ(ctl_reg);
2116}
2117
2118static void intel_edp_psr_setup_vsc(struct intel_dp *intel_dp)
2119{
2120 struct edp_vsc_psr psr_vsc;
2121
2122 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2123 memset(&psr_vsc, 0, sizeof(psr_vsc));
2124 psr_vsc.sdp_header.HB0 = 0;
2125 psr_vsc.sdp_header.HB1 = 0x7;
2126 psr_vsc.sdp_header.HB2 = 0x2;
2127 psr_vsc.sdp_header.HB3 = 0x8;
2128 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
2129}
2130
2131static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
2132{
2133 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2134 struct drm_device *dev = dig_port->base.base.dev;
2135 struct drm_i915_private *dev_priv = dev->dev_private;
2136 uint32_t aux_clock_divider;
2137 int precharge = 0x3;
2138 bool only_standby = false;
2139 static const uint8_t aux_msg[] = {
2140 [0] = DP_AUX_NATIVE_WRITE << 4,
2141 [1] = DP_SET_POWER >> 8,
2142 [2] = DP_SET_POWER & 0xff,
2143 [3] = 1 - 1,
2144 [4] = DP_SET_POWER_D0,
2145 };
2146 int i;
2147
2148 BUILD_BUG_ON(sizeof(aux_msg) > 20);
2149
2150 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
2151
2152 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2153 only_standby = true;
2154
2155 /* Enable PSR in sink */
2156 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
2157 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2158 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2159 else
2160 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2161 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2162
2163 /* Setup AUX registers */
2164 for (i = 0; i < sizeof(aux_msg); i += 4)
2165 I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,
2166 pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
2167
2168 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2169 DP_AUX_CH_CTL_TIME_OUT_400us |
2170 (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
2171 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
2172 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
2173}
2174
2175static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
2176{
2177 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2178 struct drm_device *dev = dig_port->base.base.dev;
2179 struct drm_i915_private *dev_priv = dev->dev_private;
2180 uint32_t max_sleep_time = 0x1f;
2181 uint32_t idle_frames = 1;
2182 uint32_t val = 0x0;
2183 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2184 bool only_standby = false;
2185
2186 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2187 only_standby = true;
2188
2189 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2190 val |= EDP_PSR_LINK_STANDBY;
2191 val |= EDP_PSR_TP2_TP3_TIME_0us;
2192 val |= EDP_PSR_TP1_TIME_0us;
2193 val |= EDP_PSR_SKIP_AUX_EXIT;
2194 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2195 } else
2196 val |= EDP_PSR_LINK_DISABLE;
2197
2198 I915_WRITE(EDP_PSR_CTL(dev), val |
2199 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2200 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
2201 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
2202 EDP_PSR_ENABLE);
2203}
2204
2205static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
2206{
2207 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2208 struct drm_device *dev = dig_port->base.base.dev;
2209 struct drm_i915_private *dev_priv = dev->dev_private;
2210 struct drm_crtc *crtc = dig_port->base.base.crtc;
2211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2212
2213 lockdep_assert_held(&dev_priv->psr.lock);
2214 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
2215 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
2216
2217 dev_priv->psr.source_ok = false;
2218
2219 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
2220 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
2221 return false;
2222 }
2223
2224 if (!i915.enable_psr) {
2225 DRM_DEBUG_KMS("PSR disable by flag\n");
2226 return false;
2227 }
2228
2229 /* Below limitations aren't valid for Broadwell */
2230 if (IS_BROADWELL(dev))
2231 goto out;
2232
2233 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
2234 S3D_ENABLE) {
2235 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
2236 return false;
2237 }
2238
2239 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
2240 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
2241 return false;
2242 }
2243
2244 out:
2245 dev_priv->psr.source_ok = true;
2246 return true;
2247}
2248
2249static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2250{
2251 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2252 struct drm_device *dev = intel_dig_port->base.base.dev;
2253 struct drm_i915_private *dev_priv = dev->dev_private;
2254
2255 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2256 WARN_ON(dev_priv->psr.active);
2257 lockdep_assert_held(&dev_priv->psr.lock);
2258
2259 /* Enable/Re-enable PSR on the host */
2260 intel_edp_psr_enable_source(intel_dp);
2261
2262 dev_priv->psr.active = true;
2263}
2264
2265void intel_edp_psr_enable(struct intel_dp *intel_dp)
2266{
2267 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2268 struct drm_i915_private *dev_priv = dev->dev_private;
2269
2270 if (!HAS_PSR(dev)) {
2271 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2272 return;
2273 }
2274
2275 if (!is_edp_psr(intel_dp)) {
2276 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2277 return;
2278 }
2279
2280 mutex_lock(&dev_priv->psr.lock);
2281 if (dev_priv->psr.enabled) {
2282 DRM_DEBUG_KMS("PSR already in use\n");
2283 goto unlock;
2284 }
2285
2286 if (!intel_edp_psr_match_conditions(intel_dp))
2287 goto unlock;
2288
2289 dev_priv->psr.busy_frontbuffer_bits = 0;
2290
2291 intel_edp_psr_setup_vsc(intel_dp);
2292
2293 /* Avoid continuous PSR exit by masking memup and hpd */
2294 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
2295 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2296
2297 /* Enable PSR on the panel */
2298 intel_edp_psr_enable_sink(intel_dp);
2299
2300 dev_priv->psr.enabled = intel_dp;
2301unlock:
2302 mutex_unlock(&dev_priv->psr.lock);
2303}
2304
2305void intel_edp_psr_disable(struct intel_dp *intel_dp)
2306{
2307 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2308 struct drm_i915_private *dev_priv = dev->dev_private;
2309
2310 mutex_lock(&dev_priv->psr.lock);
2311 if (!dev_priv->psr.enabled) {
2312 mutex_unlock(&dev_priv->psr.lock);
2313 return;
2314 }
2315
2316 if (dev_priv->psr.active) {
2317 I915_WRITE(EDP_PSR_CTL(dev),
2318 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2319
2320 /* Wait till PSR is idle */
2321 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2322 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2323 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2324
2325 dev_priv->psr.active = false;
2326 } else {
2327 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2328 }
2329
2330 dev_priv->psr.enabled = NULL;
2331 mutex_unlock(&dev_priv->psr.lock);
2332
2333 cancel_delayed_work_sync(&dev_priv->psr.work);
2334}
2335
2336static void intel_edp_psr_work(struct work_struct *work)
2337{
2338 struct drm_i915_private *dev_priv =
2339 container_of(work, typeof(*dev_priv), psr.work.work);
2340 struct intel_dp *intel_dp = dev_priv->psr.enabled;
2341
2342 /* We have to make sure PSR is ready for re-enable
2343 * otherwise it keeps disabled until next full enable/disable cycle.
2344 * PSR might take some time to get fully disabled
2345 * and be ready for re-enable.
2346 */
2347 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
2348 EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
2349 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
2350 return;
2351 }
2352
2353 mutex_lock(&dev_priv->psr.lock);
2354 intel_dp = dev_priv->psr.enabled;
2355
2356 if (!intel_dp)
2357 goto unlock;
2358
2359 /*
2360 * The delayed work can race with an invalidate hence we need to
2361 * recheck. Since psr_flush first clears this and then reschedules we
2362 * won't ever miss a flush when bailing out here.
2363 */
2364 if (dev_priv->psr.busy_frontbuffer_bits)
2365 goto unlock;
2366
2367 intel_edp_psr_do_enable(intel_dp);
2368unlock:
2369 mutex_unlock(&dev_priv->psr.lock);
2370}
2371
2372static void intel_edp_psr_do_exit(struct drm_device *dev)
2373{
2374 struct drm_i915_private *dev_priv = dev->dev_private;
2375
2376 if (dev_priv->psr.active) {
2377 u32 val = I915_READ(EDP_PSR_CTL(dev));
2378
2379 WARN_ON(!(val & EDP_PSR_ENABLE));
2380
2381 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2382
2383 dev_priv->psr.active = false;
2384 }
2385
2386}
2387
2388void intel_edp_psr_invalidate(struct drm_device *dev,
2389 unsigned frontbuffer_bits)
2390{
2391 struct drm_i915_private *dev_priv = dev->dev_private;
2392 struct drm_crtc *crtc;
2393 enum pipe pipe;
2394
2395 mutex_lock(&dev_priv->psr.lock);
2396 if (!dev_priv->psr.enabled) {
2397 mutex_unlock(&dev_priv->psr.lock);
2398 return;
2399 }
2400
2401 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2402 pipe = to_intel_crtc(crtc)->pipe;
2403
2404 intel_edp_psr_do_exit(dev);
2405
2406 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2407
2408 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2409 mutex_unlock(&dev_priv->psr.lock);
2410}
2411
2412void intel_edp_psr_flush(struct drm_device *dev,
2413 unsigned frontbuffer_bits)
2414{
2415 struct drm_i915_private *dev_priv = dev->dev_private;
2416 struct drm_crtc *crtc;
2417 enum pipe pipe;
2418
2419 mutex_lock(&dev_priv->psr.lock);
2420 if (!dev_priv->psr.enabled) {
2421 mutex_unlock(&dev_priv->psr.lock);
2422 return;
2423 }
2424
2425 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2426 pipe = to_intel_crtc(crtc)->pipe;
2427 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2428
2429 /*
2430 * On Haswell sprite plane updates don't result in a psr invalidating
2431 * signal in the hardware. Which means we need to manually fake this in
2432 * software for all flushes, not just when we've seen a preceding
2433 * invalidation through frontbuffer rendering.
2434 */
2435 if (IS_HASWELL(dev) &&
2436 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2437 intel_edp_psr_do_exit(dev);
2438
2439 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2440 schedule_delayed_work(&dev_priv->psr.work,
2441 msecs_to_jiffies(100));
2442 mutex_unlock(&dev_priv->psr.lock);
2443}
2444
2445void intel_edp_psr_init(struct drm_device *dev)
2446{
2447 struct drm_i915_private *dev_priv = dev->dev_private;
2448
2449 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
2450 mutex_init(&dev_priv->psr.lock);
2451}
2452
2453static void intel_disable_dp(struct intel_encoder *encoder)
2454{
2455 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2456 struct drm_device *dev = encoder->base.dev;
2457
2458 /* Make sure the panel is off before trying to change the mode. But also
2459 * ensure that we have vdd while we switch off the panel. */
2460 intel_edp_panel_vdd_on(intel_dp);
2461 intel_edp_backlight_off(intel_dp);
2462 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2463 intel_edp_panel_off(intel_dp);
2464
2465 /* disable the port before the pipe on g4x */
2466 if (INTEL_INFO(dev)->gen < 5)
2467 intel_dp_link_down(intel_dp);
2468}
2469
2470static void ilk_post_disable_dp(struct intel_encoder *encoder)
2471{
2472 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2473 enum port port = dp_to_dig_port(intel_dp)->port;
2474
2475 intel_dp_link_down(intel_dp);
2476 if (port == PORT_A)
2477 ironlake_edp_pll_off(intel_dp);
2478}
2479
2480static void vlv_post_disable_dp(struct intel_encoder *encoder)
2481{
2482 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2483
2484 intel_dp_link_down(intel_dp);
2485}
2486
2487static void chv_post_disable_dp(struct intel_encoder *encoder)
2488{
2489 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2490 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2491 struct drm_device *dev = encoder->base.dev;
2492 struct drm_i915_private *dev_priv = dev->dev_private;
2493 struct intel_crtc *intel_crtc =
2494 to_intel_crtc(encoder->base.crtc);
2495 enum dpio_channel ch = vlv_dport_to_channel(dport);
2496 enum pipe pipe = intel_crtc->pipe;
2497 u32 val;
2498
2499 intel_dp_link_down(intel_dp);
2500
2501 mutex_lock(&dev_priv->dpio_lock);
2502
2503 /* Propagate soft reset to data lane reset */
2504 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2505 val |= CHV_PCS_REQ_SOFTRESET_EN;
2506 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2507
2508 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2509 val |= CHV_PCS_REQ_SOFTRESET_EN;
2510 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2511
2512 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2513 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2514 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2515
2516 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2517 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2518 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2519
2520 mutex_unlock(&dev_priv->dpio_lock);
2521}
2522
2523static void
2524_intel_dp_set_link_train(struct intel_dp *intel_dp,
2525 uint32_t *DP,
2526 uint8_t dp_train_pat)
2527{
2528 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2529 struct drm_device *dev = intel_dig_port->base.base.dev;
2530 struct drm_i915_private *dev_priv = dev->dev_private;
2531 enum port port = intel_dig_port->port;
2532
2533 if (HAS_DDI(dev)) {
2534 uint32_t temp = I915_READ(DP_TP_CTL(port));
2535
2536 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2537 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2538 else
2539 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2540
2541 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2542 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2543 case DP_TRAINING_PATTERN_DISABLE:
2544 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2545
2546 break;
2547 case DP_TRAINING_PATTERN_1:
2548 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2549 break;
2550 case DP_TRAINING_PATTERN_2:
2551 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2552 break;
2553 case DP_TRAINING_PATTERN_3:
2554 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2555 break;
2556 }
2557 I915_WRITE(DP_TP_CTL(port), temp);
2558
2559 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2560 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2561
2562 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2563 case DP_TRAINING_PATTERN_DISABLE:
2564 *DP |= DP_LINK_TRAIN_OFF_CPT;
2565 break;
2566 case DP_TRAINING_PATTERN_1:
2567 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2568 break;
2569 case DP_TRAINING_PATTERN_2:
2570 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2571 break;
2572 case DP_TRAINING_PATTERN_3:
2573 DRM_ERROR("DP training pattern 3 not supported\n");
2574 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2575 break;
2576 }
2577
2578 } else {
2579 if (IS_CHERRYVIEW(dev))
2580 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2581 else
2582 *DP &= ~DP_LINK_TRAIN_MASK;
2583
2584 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2585 case DP_TRAINING_PATTERN_DISABLE:
2586 *DP |= DP_LINK_TRAIN_OFF;
2587 break;
2588 case DP_TRAINING_PATTERN_1:
2589 *DP |= DP_LINK_TRAIN_PAT_1;
2590 break;
2591 case DP_TRAINING_PATTERN_2:
2592 *DP |= DP_LINK_TRAIN_PAT_2;
2593 break;
2594 case DP_TRAINING_PATTERN_3:
2595 if (IS_CHERRYVIEW(dev)) {
2596 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2597 } else {
2598 DRM_ERROR("DP training pattern 3 not supported\n");
2599 *DP |= DP_LINK_TRAIN_PAT_2;
2600 }
2601 break;
2602 }
2603 }
2604}
2605
2606static void intel_dp_enable_port(struct intel_dp *intel_dp)
2607{
2608 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2609 struct drm_i915_private *dev_priv = dev->dev_private;
2610
2611 /* enable with pattern 1 (as per spec) */
2612 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2613 DP_TRAINING_PATTERN_1);
2614
2615 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2616 POSTING_READ(intel_dp->output_reg);
2617
2618 /*
2619 * Magic for VLV/CHV. We _must_ first set up the register
2620 * without actually enabling the port, and then do another
2621 * write to enable the port. Otherwise link training will
2622 * fail when the power sequencer is freshly used for this port.
2623 */
2624 intel_dp->DP |= DP_PORT_EN;
2625
2626 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2627 POSTING_READ(intel_dp->output_reg);
2628}
2629
2630static void intel_enable_dp(struct intel_encoder *encoder)
2631{
2632 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2633 struct drm_device *dev = encoder->base.dev;
2634 struct drm_i915_private *dev_priv = dev->dev_private;
2635 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2636
2637 if (WARN_ON(dp_reg & DP_PORT_EN))
2638 return;
2639
2640 pps_lock(intel_dp);
2641
2642 if (IS_VALLEYVIEW(dev))
2643 vlv_init_panel_power_sequencer(intel_dp);
2644
2645 intel_dp_enable_port(intel_dp);
2646
2647 edp_panel_vdd_on(intel_dp);
2648 edp_panel_on(intel_dp);
2649 edp_panel_vdd_off(intel_dp, true);
2650
2651 pps_unlock(intel_dp);
2652
2653 if (IS_VALLEYVIEW(dev))
2654 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));
2655
2656 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2657 intel_dp_start_link_train(intel_dp);
2658 intel_dp_complete_link_train(intel_dp);
2659 intel_dp_stop_link_train(intel_dp);
2660}
2661
2662static void g4x_enable_dp(struct intel_encoder *encoder)
2663{
2664 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2665
2666 intel_enable_dp(encoder);
2667 intel_edp_backlight_on(intel_dp);
2668}
2669
2670static void vlv_enable_dp(struct intel_encoder *encoder)
2671{
2672 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2673
2674 intel_edp_backlight_on(intel_dp);
2675}
2676
2677static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2678{
2679 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2680 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2681
2682 intel_dp_prepare(encoder);
2683
2684 /* Only ilk+ has port A */
2685 if (dport->port == PORT_A) {
2686 ironlake_set_pll_cpu_edp(intel_dp);
2687 ironlake_edp_pll_on(intel_dp);
2688 }
2689}
2690
2691static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2692{
2693 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2694 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2695 enum pipe pipe = intel_dp->pps_pipe;
2696 int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2697
2698 edp_panel_vdd_off_sync(intel_dp);
2699
2700 /*
2701 * VLV seems to get confused when multiple power seqeuencers
2702 * have the same port selected (even if only one has power/vdd
2703 * enabled). The failure manifests as vlv_wait_port_ready() failing
2704 * CHV on the other hand doesn't seem to mind having the same port
2705 * selected in multiple power seqeuencers, but let's clear the
2706 * port select always when logically disconnecting a power sequencer
2707 * from a port.
2708 */
2709 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2710 pipe_name(pipe), port_name(intel_dig_port->port));
2711 I915_WRITE(pp_on_reg, 0);
2712 POSTING_READ(pp_on_reg);
2713
2714 intel_dp->pps_pipe = INVALID_PIPE;
2715}
2716
2717static void vlv_steal_power_sequencer(struct drm_device *dev,
2718 enum pipe pipe)
2719{
2720 struct drm_i915_private *dev_priv = dev->dev_private;
2721 struct intel_encoder *encoder;
2722
2723 lockdep_assert_held(&dev_priv->pps_mutex);
2724
2725 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2726 return;
2727
2728 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2729 base.head) {
2730 struct intel_dp *intel_dp;
2731 enum port port;
2732
2733 if (encoder->type != INTEL_OUTPUT_EDP)
2734 continue;
2735
2736 intel_dp = enc_to_intel_dp(&encoder->base);
2737 port = dp_to_dig_port(intel_dp)->port;
2738
2739 if (intel_dp->pps_pipe != pipe)
2740 continue;
2741
2742 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2743 pipe_name(pipe), port_name(port));
2744
2745 WARN(encoder->connectors_active,
2746 "stealing pipe %c power sequencer from active eDP port %c\n",
2747 pipe_name(pipe), port_name(port));
2748
2749 /* make sure vdd is off before we steal it */
2750 vlv_detach_power_sequencer(intel_dp);
2751 }
2752}
2753
2754static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2755{
2756 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2757 struct intel_encoder *encoder = &intel_dig_port->base;
2758 struct drm_device *dev = encoder->base.dev;
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2761
2762 lockdep_assert_held(&dev_priv->pps_mutex);
2763
2764 if (!is_edp(intel_dp))
2765 return;
2766
2767 if (intel_dp->pps_pipe == crtc->pipe)
2768 return;
2769
2770 /*
2771 * If another power sequencer was being used on this
2772 * port previously make sure to turn off vdd there while
2773 * we still have control of it.
2774 */
2775 if (intel_dp->pps_pipe != INVALID_PIPE)
2776 vlv_detach_power_sequencer(intel_dp);
2777
2778 /*
2779 * We may be stealing the power
2780 * sequencer from another port.
2781 */
2782 vlv_steal_power_sequencer(dev, crtc->pipe);
2783
2784 /* now it's all ours */
2785 intel_dp->pps_pipe = crtc->pipe;
2786
2787 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2788 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2789
2790 /* init power sequencer on this pipe and port */
2791 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2792 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2793}
2794
2795static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2796{
2797 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2798 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2799 struct drm_device *dev = encoder->base.dev;
2800 struct drm_i915_private *dev_priv = dev->dev_private;
2801 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2802 enum dpio_channel port = vlv_dport_to_channel(dport);
2803 int pipe = intel_crtc->pipe;
2804 u32 val;
2805
2806 mutex_lock(&dev_priv->dpio_lock);
2807
2808 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2809 val = 0;
2810 if (pipe)
2811 val |= (1<<21);
2812 else
2813 val &= ~(1<<21);
2814 val |= 0x001000c4;
2815 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2816 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2817 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2818
2819 mutex_unlock(&dev_priv->dpio_lock);
2820
2821 intel_enable_dp(encoder);
2822}
2823
2824static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2825{
2826 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2827 struct drm_device *dev = encoder->base.dev;
2828 struct drm_i915_private *dev_priv = dev->dev_private;
2829 struct intel_crtc *intel_crtc =
2830 to_intel_crtc(encoder->base.crtc);
2831 enum dpio_channel port = vlv_dport_to_channel(dport);
2832 int pipe = intel_crtc->pipe;
2833
2834 intel_dp_prepare(encoder);
2835
2836 /* Program Tx lane resets to default */
2837 mutex_lock(&dev_priv->dpio_lock);
2838 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2839 DPIO_PCS_TX_LANE2_RESET |
2840 DPIO_PCS_TX_LANE1_RESET);
2841 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2842 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2843 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2844 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2845 DPIO_PCS_CLK_SOFT_RESET);
2846
2847 /* Fix up inter-pair skew failure */
2848 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2849 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2850 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2851 mutex_unlock(&dev_priv->dpio_lock);
2852}
2853
2854static void chv_pre_enable_dp(struct intel_encoder *encoder)
2855{
2856 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2857 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2858 struct drm_device *dev = encoder->base.dev;
2859 struct drm_i915_private *dev_priv = dev->dev_private;
2860 struct intel_crtc *intel_crtc =
2861 to_intel_crtc(encoder->base.crtc);
2862 enum dpio_channel ch = vlv_dport_to_channel(dport);
2863 int pipe = intel_crtc->pipe;
2864 int data, i;
2865 u32 val;
2866
2867 mutex_lock(&dev_priv->dpio_lock);
2868
2869 /* allow hardware to manage TX FIFO reset source */
2870 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2871 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2872 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2873
2874 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2875 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2876 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2877
2878 /* Deassert soft data lane reset*/
2879 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2880 val |= CHV_PCS_REQ_SOFTRESET_EN;
2881 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2882
2883 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2884 val |= CHV_PCS_REQ_SOFTRESET_EN;
2885 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2886
2887 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2888 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2889 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2890
2891 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2892 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2893 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2894
2895 /* Program Tx lane latency optimal setting*/
2896 for (i = 0; i < 4; i++) {
2897 /* Set the latency optimal bit */
2898 data = (i == 1) ? 0x0 : 0x6;
2899 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2900 data << DPIO_FRC_LATENCY_SHFIT);
2901
2902 /* Set the upar bit */
2903 data = (i == 1) ? 0x0 : 0x1;
2904 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2905 data << DPIO_UPAR_SHIFT);
2906 }
2907
2908 /* Data lane stagger programming */
2909 /* FIXME: Fix up value only after power analysis */
2910
2911 mutex_unlock(&dev_priv->dpio_lock);
2912
2913 intel_enable_dp(encoder);
2914}
2915
2916static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2917{
2918 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2919 struct drm_device *dev = encoder->base.dev;
2920 struct drm_i915_private *dev_priv = dev->dev_private;
2921 struct intel_crtc *intel_crtc =
2922 to_intel_crtc(encoder->base.crtc);
2923 enum dpio_channel ch = vlv_dport_to_channel(dport);
2924 enum pipe pipe = intel_crtc->pipe;
2925 u32 val;
2926
2927 intel_dp_prepare(encoder);
2928
2929 mutex_lock(&dev_priv->dpio_lock);
2930
2931 /* program left/right clock distribution */
2932 if (pipe != PIPE_B) {
2933 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2934 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2935 if (ch == DPIO_CH0)
2936 val |= CHV_BUFLEFTENA1_FORCE;
2937 if (ch == DPIO_CH1)
2938 val |= CHV_BUFRIGHTENA1_FORCE;
2939 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2940 } else {
2941 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2942 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2943 if (ch == DPIO_CH0)
2944 val |= CHV_BUFLEFTENA2_FORCE;
2945 if (ch == DPIO_CH1)
2946 val |= CHV_BUFRIGHTENA2_FORCE;
2947 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2948 }
2949
2950 /* program clock channel usage */
2951 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2952 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2953 if (pipe != PIPE_B)
2954 val &= ~CHV_PCS_USEDCLKCHANNEL;
2955 else
2956 val |= CHV_PCS_USEDCLKCHANNEL;
2957 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2958
2959 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2960 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2961 if (pipe != PIPE_B)
2962 val &= ~CHV_PCS_USEDCLKCHANNEL;
2963 else
2964 val |= CHV_PCS_USEDCLKCHANNEL;
2965 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2966
2967 /*
2968 * This a a bit weird since generally CL
2969 * matches the pipe, but here we need to
2970 * pick the CL based on the port.
2971 */
2972 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2973 if (pipe != PIPE_B)
2974 val &= ~CHV_CMN_USEDCLKCHANNEL;
2975 else
2976 val |= CHV_CMN_USEDCLKCHANNEL;
2977 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2978
2979 mutex_unlock(&dev_priv->dpio_lock);
2980}
2981
2982/*
2983 * Native read with retry for link status and receiver capability reads for
2984 * cases where the sink may still be asleep.
2985 *
2986 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2987 * supposed to retry 3 times per the spec.
2988 */
2989static ssize_t
2990intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2991 void *buffer, size_t size)
2992{
2993 ssize_t ret;
2994 int i;
2995
2996 for (i = 0; i < 3; i++) {
2997 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2998 if (ret == size)
2999 return ret;
3000 msleep(1);
3001 }
3002
3003 return ret;
3004}
3005
3006/*
3007 * Fetch AUX CH registers 0x202 - 0x207 which contain
3008 * link status information
3009 */
3010static bool
3011intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3012{
3013 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3014 DP_LANE0_1_STATUS,
3015 link_status,
3016 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3017}
3018
3019/* These are source-specific values. */
3020static uint8_t
3021intel_dp_voltage_max(struct intel_dp *intel_dp)
3022{
3023 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3024 enum port port = dp_to_dig_port(intel_dp)->port;
3025
3026 if (INTEL_INFO(dev)->gen >= 9)
3027 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3028 else if (IS_VALLEYVIEW(dev))
3029 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3030 else if (IS_GEN7(dev) && port == PORT_A)
3031 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3032 else if (HAS_PCH_CPT(dev) && port != PORT_A)
3033 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3034 else
3035 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3036}
3037
3038static uint8_t
3039intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3040{
3041 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3042 enum port port = dp_to_dig_port(intel_dp)->port;
3043
3044 if (INTEL_INFO(dev)->gen >= 9) {
3045 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3047 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3048 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3049 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3050 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3051 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3052 default:
3053 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3054 }
3055 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3056 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3057 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3058 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3059 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3060 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3061 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3062 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3063 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3064 default:
3065 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3066 }
3067 } else if (IS_VALLEYVIEW(dev)) {
3068 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3069 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3070 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3071 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3072 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3073 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3074 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3075 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3076 default:
3077 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3078 }
3079 } else if (IS_GEN7(dev) && port == PORT_A) {
3080 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3081 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3082 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3083 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3084 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3085 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3086 default:
3087 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3088 }
3089 } else {
3090 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3091 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3092 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3093 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3094 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3095 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3096 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3097 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3098 default:
3099 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3100 }
3101 }
3102}
3103
3104static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
3105{
3106 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3107 struct drm_i915_private *dev_priv = dev->dev_private;
3108 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3109 struct intel_crtc *intel_crtc =
3110 to_intel_crtc(dport->base.base.crtc);
3111 unsigned long demph_reg_value, preemph_reg_value,
3112 uniqtranscale_reg_value;
3113 uint8_t train_set = intel_dp->train_set[0];
3114 enum dpio_channel port = vlv_dport_to_channel(dport);
3115 int pipe = intel_crtc->pipe;
3116
3117 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3118 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3119 preemph_reg_value = 0x0004000;
3120 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3121 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3122 demph_reg_value = 0x2B405555;
3123 uniqtranscale_reg_value = 0x552AB83A;
3124 break;
3125 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3126 demph_reg_value = 0x2B404040;
3127 uniqtranscale_reg_value = 0x5548B83A;
3128 break;
3129 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3130 demph_reg_value = 0x2B245555;
3131 uniqtranscale_reg_value = 0x5560B83A;
3132 break;
3133 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3134 demph_reg_value = 0x2B405555;
3135 uniqtranscale_reg_value = 0x5598DA3A;
3136 break;
3137 default:
3138 return 0;
3139 }
3140 break;
3141 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3142 preemph_reg_value = 0x0002000;
3143 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3144 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3145 demph_reg_value = 0x2B404040;
3146 uniqtranscale_reg_value = 0x5552B83A;
3147 break;
3148 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3149 demph_reg_value = 0x2B404848;
3150 uniqtranscale_reg_value = 0x5580B83A;
3151 break;
3152 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3153 demph_reg_value = 0x2B404040;
3154 uniqtranscale_reg_value = 0x55ADDA3A;
3155 break;
3156 default:
3157 return 0;
3158 }
3159 break;
3160 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3161 preemph_reg_value = 0x0000000;
3162 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3163 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3164 demph_reg_value = 0x2B305555;
3165 uniqtranscale_reg_value = 0x5570B83A;
3166 break;
3167 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3168 demph_reg_value = 0x2B2B4040;
3169 uniqtranscale_reg_value = 0x55ADDA3A;
3170 break;
3171 default:
3172 return 0;
3173 }
3174 break;
3175 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3176 preemph_reg_value = 0x0006000;
3177 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3178 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3179 demph_reg_value = 0x1B405555;
3180 uniqtranscale_reg_value = 0x55ADDA3A;
3181 break;
3182 default:
3183 return 0;
3184 }
3185 break;
3186 default:
3187 return 0;
3188 }
3189
3190 mutex_lock(&dev_priv->dpio_lock);
3191 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3192 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3193 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
3194 uniqtranscale_reg_value);
3195 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3196 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3197 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3198 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
3199 mutex_unlock(&dev_priv->dpio_lock);
3200
3201 return 0;
3202}
3203
3204static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
3205{
3206 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3207 struct drm_i915_private *dev_priv = dev->dev_private;
3208 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3209 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
3210 u32 deemph_reg_value, margin_reg_value, val;
3211 uint8_t train_set = intel_dp->train_set[0];
3212 enum dpio_channel ch = vlv_dport_to_channel(dport);
3213 enum pipe pipe = intel_crtc->pipe;
3214 int i;
3215
3216 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3217 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3218 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3220 deemph_reg_value = 128;
3221 margin_reg_value = 52;
3222 break;
3223 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3224 deemph_reg_value = 128;
3225 margin_reg_value = 77;
3226 break;
3227 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3228 deemph_reg_value = 128;
3229 margin_reg_value = 102;
3230 break;
3231 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3232 deemph_reg_value = 128;
3233 margin_reg_value = 154;
3234 /* FIXME extra to set for 1200 */
3235 break;
3236 default:
3237 return 0;
3238 }
3239 break;
3240 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3241 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3242 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3243 deemph_reg_value = 85;
3244 margin_reg_value = 78;
3245 break;
3246 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3247 deemph_reg_value = 85;
3248 margin_reg_value = 116;
3249 break;
3250 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3251 deemph_reg_value = 85;
3252 margin_reg_value = 154;
3253 break;
3254 default:
3255 return 0;
3256 }
3257 break;
3258 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3259 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3260 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3261 deemph_reg_value = 64;
3262 margin_reg_value = 104;
3263 break;
3264 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3265 deemph_reg_value = 64;
3266 margin_reg_value = 154;
3267 break;
3268 default:
3269 return 0;
3270 }
3271 break;
3272 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3273 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3274 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3275 deemph_reg_value = 43;
3276 margin_reg_value = 154;
3277 break;
3278 default:
3279 return 0;
3280 }
3281 break;
3282 default:
3283 return 0;
3284 }
3285
3286 mutex_lock(&dev_priv->dpio_lock);
3287
3288 /* Clear calc init */
3289 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3290 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3291 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3292 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3293 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3294
3295 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3296 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3297 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3298 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3299 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3300
3301 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3302 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3303 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3304 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3305
3306 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3307 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3308 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3309 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3310
3311 /* Program swing deemph */
3312 for (i = 0; i < 4; i++) {
3313 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3314 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3315 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3316 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3317 }
3318
3319 /* Program swing margin */
3320 for (i = 0; i < 4; i++) {
3321 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3322 val &= ~DPIO_SWING_MARGIN000_MASK;
3323 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
3324 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3325 }
3326
3327 /* Disable unique transition scale */
3328 for (i = 0; i < 4; i++) {
3329 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3330 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3331 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3332 }
3333
3334 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
3335 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
3336 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
3337 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
3338
3339 /*
3340 * The document said it needs to set bit 27 for ch0 and bit 26
3341 * for ch1. Might be a typo in the doc.
3342 * For now, for this unique transition scale selection, set bit
3343 * 27 for ch0 and ch1.
3344 */
3345 for (i = 0; i < 4; i++) {
3346 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3347 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3348 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3349 }
3350
3351 for (i = 0; i < 4; i++) {
3352 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3353 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3354 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3355 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3356 }
3357 }
3358
3359 /* Start swing calculation */
3360 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3361 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3362 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3363
3364 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3365 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3366 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3367
3368 /* LRC Bypass */
3369 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3370 val |= DPIO_LRC_BYPASS;
3371 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3372
3373 mutex_unlock(&dev_priv->dpio_lock);
3374
3375 return 0;
3376}
3377
3378static void
3379intel_get_adjust_train(struct intel_dp *intel_dp,
3380 const uint8_t link_status[DP_LINK_STATUS_SIZE])
3381{
3382 uint8_t v = 0;
3383 uint8_t p = 0;
3384 int lane;
3385 uint8_t voltage_max;
3386 uint8_t preemph_max;
3387
3388 for (lane = 0; lane < intel_dp->lane_count; lane++) {
3389 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3390 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
3391
3392 if (this_v > v)
3393 v = this_v;
3394 if (this_p > p)
3395 p = this_p;
3396 }
3397
3398 voltage_max = intel_dp_voltage_max(intel_dp);
3399 if (v >= voltage_max)
3400 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
3401
3402 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3403 if (p >= preemph_max)
3404 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
3405
3406 for (lane = 0; lane < 4; lane++)
3407 intel_dp->train_set[lane] = v | p;
3408}
3409
3410static uint32_t
3411intel_gen4_signal_levels(uint8_t train_set)
3412{
3413 uint32_t signal_levels = 0;
3414
3415 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3416 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3417 default:
3418 signal_levels |= DP_VOLTAGE_0_4;
3419 break;
3420 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3421 signal_levels |= DP_VOLTAGE_0_6;
3422 break;
3423 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3424 signal_levels |= DP_VOLTAGE_0_8;
3425 break;
3426 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3427 signal_levels |= DP_VOLTAGE_1_2;
3428 break;
3429 }
3430 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3431 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3432 default:
3433 signal_levels |= DP_PRE_EMPHASIS_0;
3434 break;
3435 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3436 signal_levels |= DP_PRE_EMPHASIS_3_5;
3437 break;
3438 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3439 signal_levels |= DP_PRE_EMPHASIS_6;
3440 break;
3441 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3442 signal_levels |= DP_PRE_EMPHASIS_9_5;
3443 break;
3444 }
3445 return signal_levels;
3446}
3447
3448/* Gen6's DP voltage swing and pre-emphasis control */
3449static uint32_t
3450intel_gen6_edp_signal_levels(uint8_t train_set)
3451{
3452 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3453 DP_TRAIN_PRE_EMPHASIS_MASK);
3454 switch (signal_levels) {
3455 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3456 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3457 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3458 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3459 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3460 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3461 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3462 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3463 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3464 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3465 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3466 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3467 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3468 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3469 default:
3470 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3471 "0x%x\n", signal_levels);
3472 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3473 }
3474}
3475
3476/* Gen7's DP voltage swing and pre-emphasis control */
3477static uint32_t
3478intel_gen7_edp_signal_levels(uint8_t train_set)
3479{
3480 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3481 DP_TRAIN_PRE_EMPHASIS_MASK);
3482 switch (signal_levels) {
3483 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3484 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3485 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3486 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3487 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3488 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3489
3490 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3491 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3492 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3493 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3494
3495 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3496 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3497 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3498 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3499
3500 default:
3501 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3502 "0x%x\n", signal_levels);
3503 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3504 }
3505}
3506
3507/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3508static uint32_t
3509intel_hsw_signal_levels(uint8_t train_set)
3510{
3511 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3512 DP_TRAIN_PRE_EMPHASIS_MASK);
3513 switch (signal_levels) {
3514 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3515 return DDI_BUF_TRANS_SELECT(0);
3516 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3517 return DDI_BUF_TRANS_SELECT(1);
3518 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3519 return DDI_BUF_TRANS_SELECT(2);
3520 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
3521 return DDI_BUF_TRANS_SELECT(3);
3522
3523 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3524 return DDI_BUF_TRANS_SELECT(4);
3525 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3526 return DDI_BUF_TRANS_SELECT(5);
3527 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3528 return DDI_BUF_TRANS_SELECT(6);
3529
3530 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3531 return DDI_BUF_TRANS_SELECT(7);
3532 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3533 return DDI_BUF_TRANS_SELECT(8);
3534 default:
3535 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3536 "0x%x\n", signal_levels);
3537 return DDI_BUF_TRANS_SELECT(0);
3538 }
3539}
3540
3541/* Properly updates "DP" with the correct signal levels. */
3542static void
3543intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3544{
3545 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3546 enum port port = intel_dig_port->port;
3547 struct drm_device *dev = intel_dig_port->base.base.dev;
3548 uint32_t signal_levels, mask;
3549 uint8_t train_set = intel_dp->train_set[0];
3550
3551 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
3552 signal_levels = intel_hsw_signal_levels(train_set);
3553 mask = DDI_BUF_EMP_MASK;
3554 } else if (IS_CHERRYVIEW(dev)) {
3555 signal_levels = intel_chv_signal_levels(intel_dp);
3556 mask = 0;
3557 } else if (IS_VALLEYVIEW(dev)) {
3558 signal_levels = intel_vlv_signal_levels(intel_dp);
3559 mask = 0;
3560 } else if (IS_GEN7(dev) && port == PORT_A) {
3561 signal_levels = intel_gen7_edp_signal_levels(train_set);
3562 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3563 } else if (IS_GEN6(dev) && port == PORT_A) {
3564 signal_levels = intel_gen6_edp_signal_levels(train_set);
3565 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3566 } else {
3567 signal_levels = intel_gen4_signal_levels(train_set);
3568 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3569 }
3570
3571 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3572
3573 *DP = (*DP & ~mask) | signal_levels;
3574}
3575
3576static bool
3577intel_dp_set_link_train(struct intel_dp *intel_dp,
3578 uint32_t *DP,
3579 uint8_t dp_train_pat)
3580{
3581 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3582 struct drm_device *dev = intel_dig_port->base.base.dev;
3583 struct drm_i915_private *dev_priv = dev->dev_private;
3584 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3585 int ret, len;
3586
3587 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3588
3589 I915_WRITE(intel_dp->output_reg, *DP);
3590 POSTING_READ(intel_dp->output_reg);
3591
3592 buf[0] = dp_train_pat;
3593 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3594 DP_TRAINING_PATTERN_DISABLE) {
3595 /* don't write DP_TRAINING_LANEx_SET on disable */
3596 len = 1;
3597 } else {
3598 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3599 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3600 len = intel_dp->lane_count + 1;
3601 }
3602
3603 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3604 buf, len);
3605
3606 return ret == len;
3607}
3608
3609static bool
3610intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3611 uint8_t dp_train_pat)
3612{
3613 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3614 intel_dp_set_signal_levels(intel_dp, DP);
3615 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3616}
3617
3618static bool
3619intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3620 const uint8_t link_status[DP_LINK_STATUS_SIZE])
3621{
3622 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3623 struct drm_device *dev = intel_dig_port->base.base.dev;
3624 struct drm_i915_private *dev_priv = dev->dev_private;
3625 int ret;
3626
3627 intel_get_adjust_train(intel_dp, link_status);
3628 intel_dp_set_signal_levels(intel_dp, DP);
3629
3630 I915_WRITE(intel_dp->output_reg, *DP);
3631 POSTING_READ(intel_dp->output_reg);
3632
3633 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3634 intel_dp->train_set, intel_dp->lane_count);
3635
3636 return ret == intel_dp->lane_count;
3637}
3638
3639static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3640{
3641 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3642 struct drm_device *dev = intel_dig_port->base.base.dev;
3643 struct drm_i915_private *dev_priv = dev->dev_private;
3644 enum port port = intel_dig_port->port;
3645 uint32_t val;
3646
3647 if (!HAS_DDI(dev))
3648 return;
3649
3650 val = I915_READ(DP_TP_CTL(port));
3651 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3652 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3653 I915_WRITE(DP_TP_CTL(port), val);
3654
3655 /*
3656 * On PORT_A we can have only eDP in SST mode. There the only reason
3657 * we need to set idle transmission mode is to work around a HW issue
3658 * where we enable the pipe while not in idle link-training mode.
3659 * In this case there is requirement to wait for a minimum number of
3660 * idle patterns to be sent.
3661 */
3662 if (port == PORT_A)
3663 return;
3664
3665 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3666 1))
3667 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3668}
3669
3670/* Enable corresponding port and start training pattern 1 */
3671void
3672intel_dp_start_link_train(struct intel_dp *intel_dp)
3673{
3674 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3675 struct drm_device *dev = encoder->dev;
3676 int i;
3677 uint8_t voltage;
3678 int voltage_tries, loop_tries;
3679 uint32_t DP = intel_dp->DP;
3680 uint8_t link_config[2];
3681
3682 if (HAS_DDI(dev))
3683 intel_ddi_prepare_link_retrain(encoder);
3684
3685 /* Write the link configuration data */
3686 link_config[0] = intel_dp->link_bw;
3687 link_config[1] = intel_dp->lane_count;
3688 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3689 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3690 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3691
3692 link_config[0] = 0;
3693 link_config[1] = DP_SET_ANSI_8B10B;
3694 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3695
3696 DP |= DP_PORT_EN;
3697
3698 /* clock recovery */
3699 if (!intel_dp_reset_link_train(intel_dp, &DP,
3700 DP_TRAINING_PATTERN_1 |
3701 DP_LINK_SCRAMBLING_DISABLE)) {
3702 DRM_ERROR("failed to enable link training\n");
3703 return;
3704 }
3705
3706 voltage = 0xff;
3707 voltage_tries = 0;
3708 loop_tries = 0;
3709 for (;;) {
3710 uint8_t link_status[DP_LINK_STATUS_SIZE];
3711
3712 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3713 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3714 DRM_ERROR("failed to get link status\n");
3715 break;
3716 }
3717
3718 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3719 DRM_DEBUG_KMS("clock recovery OK\n");
3720 break;
3721 }
3722
3723 /* Check to see if we've tried the max voltage */
3724 for (i = 0; i < intel_dp->lane_count; i++)
3725 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3726 break;
3727 if (i == intel_dp->lane_count) {
3728 ++loop_tries;
3729 if (loop_tries == 5) {
3730 DRM_ERROR("too many full retries, give up\n");
3731 break;
3732 }
3733 intel_dp_reset_link_train(intel_dp, &DP,
3734 DP_TRAINING_PATTERN_1 |
3735 DP_LINK_SCRAMBLING_DISABLE);
3736 voltage_tries = 0;
3737 continue;
3738 }
3739
3740 /* Check to see if we've tried the same voltage 5 times */
3741 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3742 ++voltage_tries;
3743 if (voltage_tries == 5) {
3744 DRM_ERROR("too many voltage retries, give up\n");
3745 break;
3746 }
3747 } else
3748 voltage_tries = 0;
3749 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3750
3751 /* Update training set as requested by target */
3752 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3753 DRM_ERROR("failed to update link training\n");
3754 break;
3755 }
3756 }
3757
3758 intel_dp->DP = DP;
3759}
3760
3761void
3762intel_dp_complete_link_train(struct intel_dp *intel_dp)
3763{
3764 bool channel_eq = false;
3765 int tries, cr_tries;
3766 uint32_t DP = intel_dp->DP;
3767 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3768
3769 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3770 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3771 training_pattern = DP_TRAINING_PATTERN_3;
3772
3773 /* channel equalization */
3774 if (!intel_dp_set_link_train(intel_dp, &DP,
3775 training_pattern |
3776 DP_LINK_SCRAMBLING_DISABLE)) {
3777 DRM_ERROR("failed to start channel equalization\n");
3778 return;
3779 }
3780
3781 tries = 0;
3782 cr_tries = 0;
3783 channel_eq = false;
3784 for (;;) {
3785 uint8_t link_status[DP_LINK_STATUS_SIZE];
3786
3787 if (cr_tries > 5) {
3788 DRM_ERROR("failed to train DP, aborting\n");
3789 break;
3790 }
3791
3792 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3793 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3794 DRM_ERROR("failed to get link status\n");
3795 break;
3796 }
3797
3798 /* Make sure clock is still ok */
3799 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3800 intel_dp_start_link_train(intel_dp);
3801 intel_dp_set_link_train(intel_dp, &DP,
3802 training_pattern |
3803 DP_LINK_SCRAMBLING_DISABLE);
3804 cr_tries++;
3805 continue;
3806 }
3807
3808 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3809 channel_eq = true;
3810 break;
3811 }
3812
3813 /* Try 5 times, then try clock recovery if that fails */
3814 if (tries > 5) {
3815 intel_dp_link_down(intel_dp);
3816 intel_dp_start_link_train(intel_dp);
3817 intel_dp_set_link_train(intel_dp, &DP,
3818 training_pattern |
3819 DP_LINK_SCRAMBLING_DISABLE);
3820 tries = 0;
3821 cr_tries++;
3822 continue;
3823 }
3824
3825 /* Update training set as requested by target */
3826 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3827 DRM_ERROR("failed to update link training\n");
3828 break;
3829 }
3830 ++tries;
3831 }
3832
3833 intel_dp_set_idle_link_train(intel_dp);
3834
3835 intel_dp->DP = DP;
3836
3837 if (channel_eq)
3838 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3839
3840}
3841
3842void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3843{
3844 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3845 DP_TRAINING_PATTERN_DISABLE);
3846}
3847
3848static void
3849intel_dp_link_down(struct intel_dp *intel_dp)
3850{
3851 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3852 enum port port = intel_dig_port->port;
3853 struct drm_device *dev = intel_dig_port->base.base.dev;
3854 struct drm_i915_private *dev_priv = dev->dev_private;
3855 struct intel_crtc *intel_crtc =
3856 to_intel_crtc(intel_dig_port->base.base.crtc);
3857 uint32_t DP = intel_dp->DP;
3858
3859 if (WARN_ON(HAS_DDI(dev)))
3860 return;
3861
3862 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3863 return;
3864
3865 DRM_DEBUG_KMS("\n");
3866
3867 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3868 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3869 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3870 } else {
3871 if (IS_CHERRYVIEW(dev))
3872 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3873 else
3874 DP &= ~DP_LINK_TRAIN_MASK;
3875 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3876 }
3877 POSTING_READ(intel_dp->output_reg);
3878
3879 if (HAS_PCH_IBX(dev) &&
3880 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3881 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
3882
3883 /* Hardware workaround: leaving our transcoder select
3884 * set to transcoder B while it's off will prevent the
3885 * corresponding HDMI output on transcoder A.
3886 *
3887 * Combine this with another hardware workaround:
3888 * transcoder select bit can only be cleared while the
3889 * port is enabled.
3890 */
3891 DP &= ~DP_PIPEB_SELECT;
3892 I915_WRITE(intel_dp->output_reg, DP);
3893
3894 /* Changes to enable or select take place the vblank
3895 * after being written.
3896 */
3897 if (WARN_ON(crtc == NULL)) {
3898 /* We should never try to disable a port without a crtc
3899 * attached. For paranoia keep the code around for a
3900 * bit. */
3901 POSTING_READ(intel_dp->output_reg);
3902 msleep(50);
3903 } else
3904 intel_wait_for_vblank(dev, intel_crtc->pipe);
3905 }
3906
3907 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
3908 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3909 POSTING_READ(intel_dp->output_reg);
3910 msleep(intel_dp->panel_power_down_delay);
3911}
3912
3913static bool
3914intel_dp_get_dpcd(struct intel_dp *intel_dp)
3915{
3916 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3917 struct drm_device *dev = dig_port->base.base.dev;
3918 struct drm_i915_private *dev_priv = dev->dev_private;
3919
3920 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3921 sizeof(intel_dp->dpcd)) < 0)
3922 return false; /* aux transfer failed */
3923
3924 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3925
3926 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3927 return false; /* DPCD not present */
3928
3929 /* Check if the panel supports PSR */
3930 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3931 if (is_edp(intel_dp)) {
3932 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3933 intel_dp->psr_dpcd,
3934 sizeof(intel_dp->psr_dpcd));
3935 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3936 dev_priv->psr.sink_support = true;
3937 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3938 }
3939 }
3940
3941 /* Training Pattern 3 support */
3942 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3943 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3944 intel_dp->use_tps3 = true;
3945 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3946 } else
3947 intel_dp->use_tps3 = false;
3948
3949 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3950 DP_DWN_STRM_PORT_PRESENT))
3951 return true; /* native DP sink */
3952
3953 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3954 return true; /* no per-port downstream info */
3955
3956 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3957 intel_dp->downstream_ports,
3958 DP_MAX_DOWNSTREAM_PORTS) < 0)
3959 return false; /* downstream port status fetch failed */
3960
3961 return true;
3962}
3963
3964static void
3965intel_dp_probe_oui(struct intel_dp *intel_dp)
3966{
3967 u8 buf[3];
3968
3969 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3970 return;
3971
3972 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3973 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3974 buf[0], buf[1], buf[2]);
3975
3976 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3977 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3978 buf[0], buf[1], buf[2]);
3979}
3980
3981static bool
3982intel_dp_probe_mst(struct intel_dp *intel_dp)
3983{
3984 u8 buf[1];
3985
3986 if (!intel_dp->can_mst)
3987 return false;
3988
3989 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3990 return false;
3991
3992 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3993 if (buf[0] & DP_MST_CAP) {
3994 DRM_DEBUG_KMS("Sink is MST capable\n");
3995 intel_dp->is_mst = true;
3996 } else {
3997 DRM_DEBUG_KMS("Sink is not MST capable\n");
3998 intel_dp->is_mst = false;
3999 }
4000 }
4001
4002 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4003 return intel_dp->is_mst;
4004}
4005
4006int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
4007{
4008 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4009 struct drm_device *dev = intel_dig_port->base.base.dev;
4010 struct intel_crtc *intel_crtc =
4011 to_intel_crtc(intel_dig_port->base.base.crtc);
4012 u8 buf;
4013 int test_crc_count;
4014 int attempts = 6;
4015
4016 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
4017 return -EIO;
4018
4019 if (!(buf & DP_TEST_CRC_SUPPORTED))
4020 return -ENOTTY;
4021
4022 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
4023 return -EIO;
4024
4025 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4026 buf | DP_TEST_SINK_START) < 0)
4027 return -EIO;
4028
4029 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
4030 return -EIO;
4031 test_crc_count = buf & DP_TEST_COUNT_MASK;
4032
4033 do {
4034 if (drm_dp_dpcd_readb(&intel_dp->aux,
4035 DP_TEST_SINK_MISC, &buf) < 0)
4036 return -EIO;
4037 intel_wait_for_vblank(dev, intel_crtc->pipe);
4038 } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
4039
4040 if (attempts == 0) {
4041 DRM_ERROR("Panel is unable to calculate CRC after 6 vblanks\n");
4042 return -EIO;
4043 }
4044
4045 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
4046 return -EIO;
4047
4048 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
4049 return -EIO;
4050 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4051 buf & ~DP_TEST_SINK_START) < 0)
4052 return -EIO;
4053
4054 return 0;
4055}
4056
4057static bool
4058intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4059{
4060 return intel_dp_dpcd_read_wake(&intel_dp->aux,
4061 DP_DEVICE_SERVICE_IRQ_VECTOR,
4062 sink_irq_vector, 1) == 1;
4063}
4064
4065static bool
4066intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4067{
4068 int ret;
4069
4070 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
4071 DP_SINK_COUNT_ESI,
4072 sink_irq_vector, 14);
4073 if (ret != 14)
4074 return false;
4075
4076 return true;
4077}
4078
4079static void
4080intel_dp_handle_test_request(struct intel_dp *intel_dp)
4081{
4082 /* NAK by default */
4083 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
4084}
4085
4086static int
4087intel_dp_check_mst_status(struct intel_dp *intel_dp)
4088{
4089 bool bret;
4090
4091 if (intel_dp->is_mst) {
4092 u8 esi[16] = { 0 };
4093 int ret = 0;
4094 int retry;
4095 bool handled;
4096 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4097go_again:
4098 if (bret == true) {
4099
4100 /* check link status - esi[10] = 0x200c */
4101 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4102 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4103 intel_dp_start_link_train(intel_dp);
4104 intel_dp_complete_link_train(intel_dp);
4105 intel_dp_stop_link_train(intel_dp);
4106 }
4107
4108 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4109 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4110
4111 if (handled) {
4112 for (retry = 0; retry < 3; retry++) {
4113 int wret;
4114 wret = drm_dp_dpcd_write(&intel_dp->aux,
4115 DP_SINK_COUNT_ESI+1,
4116 &esi[1], 3);
4117 if (wret == 3) {
4118 break;
4119 }
4120 }
4121
4122 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4123 if (bret == true) {
4124 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4125 goto go_again;
4126 }
4127 } else
4128 ret = 0;
4129
4130 return ret;
4131 } else {
4132 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4133 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4134 intel_dp->is_mst = false;
4135 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4136 /* send a hotplug event */
4137 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4138 }
4139 }
4140 return -EINVAL;
4141}
4142
4143/*
4144 * According to DP spec
4145 * 5.1.2:
4146 * 1. Read DPCD
4147 * 2. Configure link according to Receiver Capabilities
4148 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4149 * 4. Check link status on receipt of hot-plug interrupt
4150 */
4151void
4152intel_dp_check_link_status(struct intel_dp *intel_dp)
4153{
4154 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4155 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4156 u8 sink_irq_vector;
4157 u8 link_status[DP_LINK_STATUS_SIZE];
4158
4159 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4160
4161 if (!intel_encoder->connectors_active)
4162 return;
4163
4164 if (WARN_ON(!intel_encoder->base.crtc))
4165 return;
4166
4167 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4168 return;
4169
4170 /* Try to read receiver status if the link appears to be up */
4171 if (!intel_dp_get_link_status(intel_dp, link_status)) {
4172 return;
4173 }
4174
4175 /* Now read the DPCD to see if it's actually running */
4176 if (!intel_dp_get_dpcd(intel_dp)) {
4177 return;
4178 }
4179
4180 /* Try to read the source of the interrupt */
4181 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4182 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4183 /* Clear interrupt source */
4184 drm_dp_dpcd_writeb(&intel_dp->aux,
4185 DP_DEVICE_SERVICE_IRQ_VECTOR,
4186 sink_irq_vector);
4187
4188 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4189 intel_dp_handle_test_request(intel_dp);
4190 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4191 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4192 }
4193
4194 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4195 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4196 intel_encoder->base.name);
4197 intel_dp_start_link_train(intel_dp);
4198 intel_dp_complete_link_train(intel_dp);
4199 intel_dp_stop_link_train(intel_dp);
4200 }
4201}
4202
4203/* XXX this is probably wrong for multiple downstream ports */
4204static enum drm_connector_status
4205intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4206{
4207 uint8_t *dpcd = intel_dp->dpcd;
4208 uint8_t type;
4209
4210 if (!intel_dp_get_dpcd(intel_dp))
4211 return connector_status_disconnected;
4212
4213 /* if there's no downstream port, we're done */
4214 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
4215 return connector_status_connected;
4216
4217 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4218 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4219 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4220 uint8_t reg;
4221
4222 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4223 &reg, 1) < 0)
4224 return connector_status_unknown;
4225
4226 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4227 : connector_status_disconnected;
4228 }
4229
4230 /* If no HPD, poke DDC gently */
4231 if (drm_probe_ddc(&intel_dp->aux.ddc))
4232 return connector_status_connected;
4233
4234 /* Well we tried, say unknown for unreliable port types */
4235 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4236 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4237 if (type == DP_DS_PORT_TYPE_VGA ||
4238 type == DP_DS_PORT_TYPE_NON_EDID)
4239 return connector_status_unknown;
4240 } else {
4241 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4242 DP_DWN_STRM_PORT_TYPE_MASK;
4243 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4244 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4245 return connector_status_unknown;
4246 }
4247
4248 /* Anything else is out of spec, warn and ignore */
4249 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4250 return connector_status_disconnected;
4251}
4252
4253static enum drm_connector_status
4254edp_detect(struct intel_dp *intel_dp)
4255{
4256 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4257 enum drm_connector_status status;
4258
4259 status = intel_panel_detect(dev);
4260 if (status == connector_status_unknown)
4261 status = connector_status_connected;
4262
4263 return status;
4264}
4265
4266static enum drm_connector_status
4267ironlake_dp_detect(struct intel_dp *intel_dp)
4268{
4269 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4270 struct drm_i915_private *dev_priv = dev->dev_private;
4271 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4272
4273 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4274 return connector_status_disconnected;
4275
4276 return intel_dp_detect_dpcd(intel_dp);
4277}
4278
4279static int g4x_digital_port_connected(struct drm_device *dev,
4280 struct intel_digital_port *intel_dig_port)
4281{
4282 struct drm_i915_private *dev_priv = dev->dev_private;
4283 uint32_t bit;
4284
4285 if (IS_VALLEYVIEW(dev)) {
4286 switch (intel_dig_port->port) {
4287 case PORT_B:
4288 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4289 break;
4290 case PORT_C:
4291 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4292 break;
4293 case PORT_D:
4294 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4295 break;
4296 default:
4297 return -EINVAL;
4298 }
4299 } else {
4300 switch (intel_dig_port->port) {
4301 case PORT_B:
4302 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4303 break;
4304 case PORT_C:
4305 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4306 break;
4307 case PORT_D:
4308 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4309 break;
4310 default:
4311 return -EINVAL;
4312 }
4313 }
4314
4315 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
4316 return 0;
4317 return 1;
4318}
4319
4320static enum drm_connector_status
4321g4x_dp_detect(struct intel_dp *intel_dp)
4322{
4323 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4324 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4325 int ret;
4326
4327 /* Can't disconnect eDP, but you can close the lid... */
4328 if (is_edp(intel_dp)) {
4329 enum drm_connector_status status;
4330
4331 status = intel_panel_detect(dev);
4332 if (status == connector_status_unknown)
4333 status = connector_status_connected;
4334 return status;
4335 }
4336
4337 ret = g4x_digital_port_connected(dev, intel_dig_port);
4338 if (ret == -EINVAL)
4339 return connector_status_unknown;
4340 else if (ret == 0)
4341 return connector_status_disconnected;
4342
4343 return intel_dp_detect_dpcd(intel_dp);
4344}
4345
4346static struct edid *
4347intel_dp_get_edid(struct intel_dp *intel_dp)
4348{
4349 struct intel_connector *intel_connector = intel_dp->attached_connector;
4350
4351 /* use cached edid if we have one */
4352 if (intel_connector->edid) {
4353 /* invalid edid */
4354 if (IS_ERR(intel_connector->edid))
4355 return NULL;
4356
4357 return drm_edid_duplicate(intel_connector->edid);
4358 } else
4359 return drm_get_edid(&intel_connector->base,
4360 &intel_dp->aux.ddc);
4361}
4362
4363static void
4364intel_dp_set_edid(struct intel_dp *intel_dp)
4365{
4366 struct intel_connector *intel_connector = intel_dp->attached_connector;
4367 struct edid *edid;
4368
4369 edid = intel_dp_get_edid(intel_dp);
4370 intel_connector->detect_edid = edid;
4371
4372 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4373 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4374 else
4375 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4376}
4377
4378static void
4379intel_dp_unset_edid(struct intel_dp *intel_dp)
4380{
4381 struct intel_connector *intel_connector = intel_dp->attached_connector;
4382
4383 kfree(intel_connector->detect_edid);
4384 intel_connector->detect_edid = NULL;
4385
4386 intel_dp->has_audio = false;
4387}
4388
4389static enum intel_display_power_domain
4390intel_dp_power_get(struct intel_dp *dp)
4391{
4392 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4393 enum intel_display_power_domain power_domain;
4394
4395 power_domain = intel_display_port_power_domain(encoder);
4396 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4397
4398 return power_domain;
4399}
4400
4401static void
4402intel_dp_power_put(struct intel_dp *dp,
4403 enum intel_display_power_domain power_domain)
4404{
4405 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4406 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
4407}
4408
4409static enum drm_connector_status
4410intel_dp_detect(struct drm_connector *connector, bool force)
4411{
4412 struct intel_dp *intel_dp = intel_attached_dp(connector);
4413 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4414 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4415 struct drm_device *dev = connector->dev;
4416 enum drm_connector_status status;
4417 enum intel_display_power_domain power_domain;
4418 bool ret;
4419
4420 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4421 connector->base.id, connector->name);
4422 intel_dp_unset_edid(intel_dp);
4423
4424 if (intel_dp->is_mst) {
4425 /* MST devices are disconnected from a monitor POV */
4426 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4427 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4428 return connector_status_disconnected;
4429 }
4430
4431 power_domain = intel_dp_power_get(intel_dp);
4432
4433 /* Can't disconnect eDP, but you can close the lid... */
4434 if (is_edp(intel_dp))
4435 status = edp_detect(intel_dp);
4436 else if (HAS_PCH_SPLIT(dev))
4437 status = ironlake_dp_detect(intel_dp);
4438 else
4439 status = g4x_dp_detect(intel_dp);
4440 if (status != connector_status_connected)
4441 goto out;
4442
4443 intel_dp_probe_oui(intel_dp);
4444
4445 ret = intel_dp_probe_mst(intel_dp);
4446 if (ret) {
4447 /* if we are in MST mode then this connector
4448 won't appear connected or have anything with EDID on it */
4449 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4450 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4451 status = connector_status_disconnected;
4452 goto out;
4453 }
4454
4455 intel_dp_set_edid(intel_dp);
4456
4457 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4458 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4459 status = connector_status_connected;
4460
4461out:
4462 intel_dp_power_put(intel_dp, power_domain);
4463 return status;
4464}
4465
4466static void
4467intel_dp_force(struct drm_connector *connector)
4468{
4469 struct intel_dp *intel_dp = intel_attached_dp(connector);
4470 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4471 enum intel_display_power_domain power_domain;
4472
4473 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4474 connector->base.id, connector->name);
4475 intel_dp_unset_edid(intel_dp);
4476
4477 if (connector->status != connector_status_connected)
4478 return;
4479
4480 power_domain = intel_dp_power_get(intel_dp);
4481
4482 intel_dp_set_edid(intel_dp);
4483
4484 intel_dp_power_put(intel_dp, power_domain);
4485
4486 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4487 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4488}
4489
4490static int intel_dp_get_modes(struct drm_connector *connector)
4491{
4492 struct intel_connector *intel_connector = to_intel_connector(connector);
4493 struct edid *edid;
4494
4495 edid = intel_connector->detect_edid;
4496 if (edid) {
4497 int ret = intel_connector_update_modes(connector, edid);
4498 if (ret)
4499 return ret;
4500 }
4501
4502 /* if eDP has no EDID, fall back to fixed mode */
4503 if (is_edp(intel_attached_dp(connector)) &&
4504 intel_connector->panel.fixed_mode) {
4505 struct drm_display_mode *mode;
4506
4507 mode = drm_mode_duplicate(connector->dev,
4508 intel_connector->panel.fixed_mode);
4509 if (mode) {
4510 drm_mode_probed_add(connector, mode);
4511 return 1;
4512 }
4513 }
4514
4515 return 0;
4516}
4517
4518static bool
4519intel_dp_detect_audio(struct drm_connector *connector)
4520{
4521 bool has_audio = false;
4522 struct edid *edid;
4523
4524 edid = to_intel_connector(connector)->detect_edid;
4525 if (edid)
4526 has_audio = drm_detect_monitor_audio(edid);
4527
4528 return has_audio;
4529}
4530
4531static int
4532intel_dp_set_property(struct drm_connector *connector,
4533 struct drm_property *property,
4534 uint64_t val)
4535{
4536 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4537 struct intel_connector *intel_connector = to_intel_connector(connector);
4538 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4539 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4540 int ret;
4541
4542 ret = drm_object_property_set_value(&connector->base, property, val);
4543 if (ret)
4544 return ret;
4545
4546 if (property == dev_priv->force_audio_property) {
4547 int i = val;
4548 bool has_audio;
4549
4550 if (i == intel_dp->force_audio)
4551 return 0;
4552
4553 intel_dp->force_audio = i;
4554
4555 if (i == HDMI_AUDIO_AUTO)
4556 has_audio = intel_dp_detect_audio(connector);
4557 else
4558 has_audio = (i == HDMI_AUDIO_ON);
4559
4560 if (has_audio == intel_dp->has_audio)
4561 return 0;
4562
4563 intel_dp->has_audio = has_audio;
4564 goto done;
4565 }
4566
4567 if (property == dev_priv->broadcast_rgb_property) {
4568 bool old_auto = intel_dp->color_range_auto;
4569 uint32_t old_range = intel_dp->color_range;
4570
4571 switch (val) {
4572 case INTEL_BROADCAST_RGB_AUTO:
4573 intel_dp->color_range_auto = true;
4574 break;
4575 case INTEL_BROADCAST_RGB_FULL:
4576 intel_dp->color_range_auto = false;
4577 intel_dp->color_range = 0;
4578 break;
4579 case INTEL_BROADCAST_RGB_LIMITED:
4580 intel_dp->color_range_auto = false;
4581 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4582 break;
4583 default:
4584 return -EINVAL;
4585 }
4586
4587 if (old_auto == intel_dp->color_range_auto &&
4588 old_range == intel_dp->color_range)
4589 return 0;
4590
4591 goto done;
4592 }
4593
4594 if (is_edp(intel_dp) &&
4595 property == connector->dev->mode_config.scaling_mode_property) {
4596 if (val == DRM_MODE_SCALE_NONE) {
4597 DRM_DEBUG_KMS("no scaling not supported\n");
4598 return -EINVAL;
4599 }
4600
4601 if (intel_connector->panel.fitting_mode == val) {
4602 /* the eDP scaling property is not changed */
4603 return 0;
4604 }
4605 intel_connector->panel.fitting_mode = val;
4606
4607 goto done;
4608 }
4609
4610 return -EINVAL;
4611
4612done:
4613 if (intel_encoder->base.crtc)
4614 intel_crtc_restore_mode(intel_encoder->base.crtc);
4615
4616 return 0;
4617}
4618
4619static void
4620intel_dp_connector_destroy(struct drm_connector *connector)
4621{
4622 struct intel_connector *intel_connector = to_intel_connector(connector);
4623
4624 kfree(intel_connector->detect_edid);
4625
4626 if (!IS_ERR_OR_NULL(intel_connector->edid))
4627 kfree(intel_connector->edid);
4628
4629 /* Can't call is_edp() since the encoder may have been destroyed
4630 * already. */
4631 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4632 intel_panel_fini(&intel_connector->panel);
4633
4634 drm_connector_cleanup(connector);
4635 kfree(connector);
4636}
4637
4638void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4639{
4640 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4641 struct intel_dp *intel_dp = &intel_dig_port->dp;
4642
4643 drm_dp_aux_unregister(&intel_dp->aux);
4644 intel_dp_mst_encoder_cleanup(intel_dig_port);
4645 drm_encoder_cleanup(encoder);
4646 if (is_edp(intel_dp)) {
4647 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4648 /*
4649 * vdd might still be enabled do to the delayed vdd off.
4650 * Make sure vdd is actually turned off here.
4651 */
4652 pps_lock(intel_dp);
4653 edp_panel_vdd_off_sync(intel_dp);
4654 pps_unlock(intel_dp);
4655
4656 if (intel_dp->edp_notifier.notifier_call) {
4657 unregister_reboot_notifier(&intel_dp->edp_notifier);
4658 intel_dp->edp_notifier.notifier_call = NULL;
4659 }
4660 }
4661 kfree(intel_dig_port);
4662}
4663
4664static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4665{
4666 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4667
4668 if (!is_edp(intel_dp))
4669 return;
4670
4671 /*
4672 * vdd might still be enabled do to the delayed vdd off.
4673 * Make sure vdd is actually turned off here.
4674 */
4675 pps_lock(intel_dp);
4676 edp_panel_vdd_off_sync(intel_dp);
4677 pps_unlock(intel_dp);
4678}
4679
4680static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4681{
4682 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4683}
4684
4685static const struct drm_connector_funcs intel_dp_connector_funcs = {
4686 .dpms = intel_connector_dpms,
4687 .detect = intel_dp_detect,
4688 .force = intel_dp_force,
4689 .fill_modes = drm_helper_probe_single_connector_modes,
4690 .set_property = intel_dp_set_property,
4691 .destroy = intel_dp_connector_destroy,
4692};
4693
4694static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4695 .get_modes = intel_dp_get_modes,
4696 .mode_valid = intel_dp_mode_valid,
4697 .best_encoder = intel_best_encoder,
4698};
4699
4700static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4701 .reset = intel_dp_encoder_reset,
4702 .destroy = intel_dp_encoder_destroy,
4703};
4704
4705void
4706intel_dp_hot_plug(struct intel_encoder *intel_encoder)
4707{
4708 return;
4709}
4710
4711bool
4712intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4713{
4714 struct intel_dp *intel_dp = &intel_dig_port->dp;
4715 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4716 struct drm_device *dev = intel_dig_port->base.base.dev;
4717 struct drm_i915_private *dev_priv = dev->dev_private;
4718 enum intel_display_power_domain power_domain;
4719 bool ret = true;
4720
4721 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4722 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4723
4724 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4725 port_name(intel_dig_port->port),
4726 long_hpd ? "long" : "short");
4727
4728 power_domain = intel_display_port_power_domain(intel_encoder);
4729 intel_display_power_get(dev_priv, power_domain);
4730
4731 if (long_hpd) {
4732
4733 if (HAS_PCH_SPLIT(dev)) {
4734 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4735 goto mst_fail;
4736 } else {
4737 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4738 goto mst_fail;
4739 }
4740
4741 if (!intel_dp_get_dpcd(intel_dp)) {
4742 goto mst_fail;
4743 }
4744
4745 intel_dp_probe_oui(intel_dp);
4746
4747 if (!intel_dp_probe_mst(intel_dp))
4748 goto mst_fail;
4749
4750 } else {
4751 if (intel_dp->is_mst) {
4752 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
4753 goto mst_fail;
4754 }
4755
4756 if (!intel_dp->is_mst) {
4757 /*
4758 * we'll check the link status via the normal hot plug path later -
4759 * but for short hpds we should check it now
4760 */
4761 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4762 intel_dp_check_link_status(intel_dp);
4763 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4764 }
4765 }
4766 ret = false;
4767 goto put_power;
4768mst_fail:
4769 /* if we were in MST mode, and device is not there get out of MST mode */
4770 if (intel_dp->is_mst) {
4771 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4772 intel_dp->is_mst = false;
4773 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4774 }
4775put_power:
4776 intel_display_power_put(dev_priv, power_domain);
4777
4778 return ret;
4779}
4780
4781/* Return which DP Port should be selected for Transcoder DP control */
4782int
4783intel_trans_dp_port_sel(struct drm_crtc *crtc)
4784{
4785 struct drm_device *dev = crtc->dev;
4786 struct intel_encoder *intel_encoder;
4787 struct intel_dp *intel_dp;
4788
4789 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4790 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4791
4792 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4793 intel_encoder->type == INTEL_OUTPUT_EDP)
4794 return intel_dp->output_reg;
4795 }
4796
4797 return -1;
4798}
4799
4800/* check the VBT to see whether the eDP is on DP-D port */
4801bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4802{
4803 struct drm_i915_private *dev_priv = dev->dev_private;
4804 union child_device_config *p_child;
4805 int i;
4806 static const short port_mapping[] = {
4807 [PORT_B] = PORT_IDPB,
4808 [PORT_C] = PORT_IDPC,
4809 [PORT_D] = PORT_IDPD,
4810 };
4811
4812 if (port == PORT_A)
4813 return true;
4814
4815 if (!dev_priv->vbt.child_dev_num)
4816 return false;
4817
4818 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4819 p_child = dev_priv->vbt.child_dev + i;
4820
4821 if (p_child->common.dvo_port == port_mapping[port] &&
4822 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4823 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
4824 return true;
4825 }
4826 return false;
4827}
4828
4829void
4830intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4831{
4832 struct intel_connector *intel_connector = to_intel_connector(connector);
4833
4834 intel_attach_force_audio_property(connector);
4835 intel_attach_broadcast_rgb_property(connector);
4836 intel_dp->color_range_auto = true;
4837
4838 if (is_edp(intel_dp)) {
4839 drm_mode_create_scaling_mode_property(connector->dev);
4840 drm_object_attach_property(
4841 &connector->base,
4842 connector->dev->mode_config.scaling_mode_property,
4843 DRM_MODE_SCALE_ASPECT);
4844 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4845 }
4846}
4847
4848static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4849{
4850 intel_dp->last_power_cycle = jiffies;
4851 intel_dp->last_power_on = jiffies;
4852 intel_dp->last_backlight_off = jiffies;
4853}
4854
4855static void
4856intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4857 struct intel_dp *intel_dp)
4858{
4859 struct drm_i915_private *dev_priv = dev->dev_private;
4860 struct edp_power_seq cur, vbt, spec,
4861 *final = &intel_dp->pps_delays;
4862 u32 pp_on, pp_off, pp_div, pp;
4863 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
4864
4865 lockdep_assert_held(&dev_priv->pps_mutex);
4866
4867 /* already initialized? */
4868 if (final->t11_t12 != 0)
4869 return;
4870
4871 if (HAS_PCH_SPLIT(dev)) {
4872 pp_ctrl_reg = PCH_PP_CONTROL;
4873 pp_on_reg = PCH_PP_ON_DELAYS;
4874 pp_off_reg = PCH_PP_OFF_DELAYS;
4875 pp_div_reg = PCH_PP_DIVISOR;
4876 } else {
4877 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4878
4879 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4880 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4881 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4882 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4883 }
4884
4885 /* Workaround: Need to write PP_CONTROL with the unlock key as
4886 * the very first thing. */
4887 pp = ironlake_get_pp_control(intel_dp);
4888 I915_WRITE(pp_ctrl_reg, pp);
4889
4890 pp_on = I915_READ(pp_on_reg);
4891 pp_off = I915_READ(pp_off_reg);
4892 pp_div = I915_READ(pp_div_reg);
4893
4894 /* Pull timing values out of registers */
4895 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4896 PANEL_POWER_UP_DELAY_SHIFT;
4897
4898 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4899 PANEL_LIGHT_ON_DELAY_SHIFT;
4900
4901 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4902 PANEL_LIGHT_OFF_DELAY_SHIFT;
4903
4904 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4905 PANEL_POWER_DOWN_DELAY_SHIFT;
4906
4907 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4908 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4909
4910 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4911 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4912
4913 vbt = dev_priv->vbt.edp_pps;
4914
4915 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4916 * our hw here, which are all in 100usec. */
4917 spec.t1_t3 = 210 * 10;
4918 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4919 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4920 spec.t10 = 500 * 10;
4921 /* This one is special and actually in units of 100ms, but zero
4922 * based in the hw (so we need to add 100 ms). But the sw vbt
4923 * table multiplies it with 1000 to make it in units of 100usec,
4924 * too. */
4925 spec.t11_t12 = (510 + 100) * 10;
4926
4927 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4928 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4929
4930 /* Use the max of the register settings and vbt. If both are
4931 * unset, fall back to the spec limits. */
4932#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
4933 spec.field : \
4934 max(cur.field, vbt.field))
4935 assign_final(t1_t3);
4936 assign_final(t8);
4937 assign_final(t9);
4938 assign_final(t10);
4939 assign_final(t11_t12);
4940#undef assign_final
4941
4942#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
4943 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4944 intel_dp->backlight_on_delay = get_delay(t8);
4945 intel_dp->backlight_off_delay = get_delay(t9);
4946 intel_dp->panel_power_down_delay = get_delay(t10);
4947 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4948#undef get_delay
4949
4950 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4951 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4952 intel_dp->panel_power_cycle_delay);
4953
4954 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4955 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4956}
4957
4958static void
4959intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4960 struct intel_dp *intel_dp)
4961{
4962 struct drm_i915_private *dev_priv = dev->dev_private;
4963 u32 pp_on, pp_off, pp_div, port_sel = 0;
4964 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4965 int pp_on_reg, pp_off_reg, pp_div_reg;
4966 enum port port = dp_to_dig_port(intel_dp)->port;
4967 const struct edp_power_seq *seq = &intel_dp->pps_delays;
4968
4969 lockdep_assert_held(&dev_priv->pps_mutex);
4970
4971 if (HAS_PCH_SPLIT(dev)) {
4972 pp_on_reg = PCH_PP_ON_DELAYS;
4973 pp_off_reg = PCH_PP_OFF_DELAYS;
4974 pp_div_reg = PCH_PP_DIVISOR;
4975 } else {
4976 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4977
4978 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4979 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4980 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4981 }
4982
4983 /*
4984 * And finally store the new values in the power sequencer. The
4985 * backlight delays are set to 1 because we do manual waits on them. For
4986 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4987 * we'll end up waiting for the backlight off delay twice: once when we
4988 * do the manual sleep, and once when we disable the panel and wait for
4989 * the PP_STATUS bit to become zero.
4990 */
4991 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4992 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4993 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4994 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4995 /* Compute the divisor for the pp clock, simply match the Bspec
4996 * formula. */
4997 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4998 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4999 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5000
5001 /* Haswell doesn't have any port selection bits for the panel
5002 * power sequencer any more. */
5003 if (IS_VALLEYVIEW(dev)) {
5004 port_sel = PANEL_PORT_SELECT_VLV(port);
5005 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5006 if (port == PORT_A)
5007 port_sel = PANEL_PORT_SELECT_DPA;
5008 else
5009 port_sel = PANEL_PORT_SELECT_DPD;
5010 }
5011
5012 pp_on |= port_sel;
5013
5014 I915_WRITE(pp_on_reg, pp_on);
5015 I915_WRITE(pp_off_reg, pp_off);
5016 I915_WRITE(pp_div_reg, pp_div);
5017
5018 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5019 I915_READ(pp_on_reg),
5020 I915_READ(pp_off_reg),
5021 I915_READ(pp_div_reg));
5022}
5023
5024void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
5025{
5026 struct drm_i915_private *dev_priv = dev->dev_private;
5027 struct intel_encoder *encoder;
5028 struct intel_dp *intel_dp = NULL;
5029 struct intel_crtc_config *config = NULL;
5030 struct intel_crtc *intel_crtc = NULL;
5031 struct intel_connector *intel_connector = dev_priv->drrs.connector;
5032 u32 reg, val;
5033 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
5034
5035 if (refresh_rate <= 0) {
5036 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5037 return;
5038 }
5039
5040 if (intel_connector == NULL) {
5041 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
5042 return;
5043 }
5044
5045 /*
5046 * FIXME: This needs proper synchronization with psr state. But really
5047 * hard to tell without seeing the user of this function of this code.
5048 * Check locking and ordering once that lands.
5049 */
5050 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
5051 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
5052 return;
5053 }
5054
5055 encoder = intel_attached_encoder(&intel_connector->base);
5056 intel_dp = enc_to_intel_dp(&encoder->base);
5057 intel_crtc = encoder->new_crtc;
5058
5059 if (!intel_crtc) {
5060 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5061 return;
5062 }
5063
5064 config = &intel_crtc->config;
5065
5066 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
5067 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5068 return;
5069 }
5070
5071 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
5072 index = DRRS_LOW_RR;
5073
5074 if (index == intel_dp->drrs_state.refresh_rate_type) {
5075 DRM_DEBUG_KMS(
5076 "DRRS requested for previously set RR...ignoring\n");
5077 return;
5078 }
5079
5080 if (!intel_crtc->active) {
5081 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5082 return;
5083 }
5084
5085 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
5086 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
5087 val = I915_READ(reg);
5088 if (index > DRRS_HIGH_RR) {
5089 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5090 intel_dp_set_m_n(intel_crtc);
5091 } else {
5092 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5093 }
5094 I915_WRITE(reg, val);
5095 }
5096
5097 /*
5098 * mutex taken to ensure that there is no race between differnt
5099 * drrs calls trying to update refresh rate. This scenario may occur
5100 * in future when idleness detection based DRRS in kernel and
5101 * possible calls from user space to set differnt RR are made.
5102 */
5103
5104 mutex_lock(&intel_dp->drrs_state.mutex);
5105
5106 intel_dp->drrs_state.refresh_rate_type = index;
5107
5108 mutex_unlock(&intel_dp->drrs_state.mutex);
5109
5110 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5111}
5112
5113static struct drm_display_mode *
5114intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
5115 struct intel_connector *intel_connector,
5116 struct drm_display_mode *fixed_mode)
5117{
5118 struct drm_connector *connector = &intel_connector->base;
5119 struct intel_dp *intel_dp = &intel_dig_port->dp;
5120 struct drm_device *dev = intel_dig_port->base.base.dev;
5121 struct drm_i915_private *dev_priv = dev->dev_private;
5122 struct drm_display_mode *downclock_mode = NULL;
5123
5124 if (INTEL_INFO(dev)->gen <= 6) {
5125 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5126 return NULL;
5127 }
5128
5129 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5130 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5131 return NULL;
5132 }
5133
5134 downclock_mode = intel_find_panel_downclock
5135 (dev, fixed_mode, connector);
5136
5137 if (!downclock_mode) {
5138 DRM_DEBUG_KMS("DRRS not supported\n");
5139 return NULL;
5140 }
5141
5142 dev_priv->drrs.connector = intel_connector;
5143
5144 mutex_init(&intel_dp->drrs_state.mutex);
5145
5146 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
5147
5148 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
5149 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5150 return downclock_mode;
5151}
5152
5153void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
5154{
5155 struct drm_device *dev = intel_encoder->base.dev;
5156 struct drm_i915_private *dev_priv = dev->dev_private;
5157 struct intel_dp *intel_dp;
5158 enum intel_display_power_domain power_domain;
5159
5160 if (intel_encoder->type != INTEL_OUTPUT_EDP)
5161 return;
5162
5163 intel_dp = enc_to_intel_dp(&intel_encoder->base);
5164
5165 pps_lock(intel_dp);
5166
5167 if (!edp_have_panel_vdd(intel_dp))
5168 goto out;
5169 /*
5170 * The VDD bit needs a power domain reference, so if the bit is
5171 * already enabled when we boot or resume, grab this reference and
5172 * schedule a vdd off, so we don't hold on to the reference
5173 * indefinitely.
5174 */
5175 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5176 power_domain = intel_display_port_power_domain(intel_encoder);
5177 intel_display_power_get(dev_priv, power_domain);
5178
5179 edp_panel_vdd_schedule_off(intel_dp);
5180 out:
5181 pps_unlock(intel_dp);
5182}
5183
5184static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5185 struct intel_connector *intel_connector)
5186{
5187 struct drm_connector *connector = &intel_connector->base;
5188 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5189 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5190 struct drm_device *dev = intel_encoder->base.dev;
5191 struct drm_i915_private *dev_priv = dev->dev_private;
5192 struct drm_display_mode *fixed_mode = NULL;
5193 struct drm_display_mode *downclock_mode = NULL;
5194 bool has_dpcd;
5195 struct drm_display_mode *scan;
5196 struct edid *edid;
5197
5198 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
5199
5200 if (!is_edp(intel_dp))
5201 return true;
5202
5203 intel_edp_panel_vdd_sanitize(intel_encoder);
5204
5205 /* Cache DPCD and EDID for edp. */
5206 has_dpcd = intel_dp_get_dpcd(intel_dp);
5207
5208 if (has_dpcd) {
5209 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5210 dev_priv->no_aux_handshake =
5211 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5212 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5213 } else {
5214 /* if this fails, presume the device is a ghost */
5215 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5216 return false;
5217 }
5218
5219 /* We now know it's not a ghost, init power sequence regs. */
5220 pps_lock(intel_dp);
5221 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5222 pps_unlock(intel_dp);
5223
5224 mutex_lock(&dev->mode_config.mutex);
5225 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5226 if (edid) {
5227 if (drm_add_edid_modes(connector, edid)) {
5228 drm_mode_connector_update_edid_property(connector,
5229 edid);
5230 drm_edid_to_eld(connector, edid);
5231 } else {
5232 kfree(edid);
5233 edid = ERR_PTR(-EINVAL);
5234 }
5235 } else {
5236 edid = ERR_PTR(-ENOENT);
5237 }
5238 intel_connector->edid = edid;
5239
5240 /* prefer fixed mode from EDID if available */
5241 list_for_each_entry(scan, &connector->probed_modes, head) {
5242 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5243 fixed_mode = drm_mode_duplicate(dev, scan);
5244 downclock_mode = intel_dp_drrs_init(
5245 intel_dig_port,
5246 intel_connector, fixed_mode);
5247 break;
5248 }
5249 }
5250
5251 /* fallback to VBT if available for eDP */
5252 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5253 fixed_mode = drm_mode_duplicate(dev,
5254 dev_priv->vbt.lfp_lvds_vbt_mode);
5255 if (fixed_mode)
5256 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5257 }
5258 mutex_unlock(&dev->mode_config.mutex);
5259
5260 if (IS_VALLEYVIEW(dev)) {
5261 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5262 register_reboot_notifier(&intel_dp->edp_notifier);
5263 }
5264
5265 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5266 intel_connector->panel.backlight_power = intel_edp_backlight_power;
5267 intel_panel_setup_backlight(connector);
5268
5269 return true;
5270}
5271
5272bool
5273intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5274 struct intel_connector *intel_connector)
5275{
5276 struct drm_connector *connector = &intel_connector->base;
5277 struct intel_dp *intel_dp = &intel_dig_port->dp;
5278 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5279 struct drm_device *dev = intel_encoder->base.dev;
5280 struct drm_i915_private *dev_priv = dev->dev_private;
5281 enum port port = intel_dig_port->port;
5282 int type;
5283
5284 intel_dp->pps_pipe = INVALID_PIPE;
5285
5286 /* intel_dp vfuncs */
5287 if (INTEL_INFO(dev)->gen >= 9)
5288 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5289 else if (IS_VALLEYVIEW(dev))
5290 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5291 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5292 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5293 else if (HAS_PCH_SPLIT(dev))
5294 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5295 else
5296 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5297
5298 if (INTEL_INFO(dev)->gen >= 9)
5299 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5300 else
5301 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
5302
5303 /* Preserve the current hw state. */
5304 intel_dp->DP = I915_READ(intel_dp->output_reg);
5305 intel_dp->attached_connector = intel_connector;
5306
5307 if (intel_dp_is_edp(dev, port))
5308 type = DRM_MODE_CONNECTOR_eDP;
5309 else
5310 type = DRM_MODE_CONNECTOR_DisplayPort;
5311
5312 /*
5313 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5314 * for DP the encoder type can be set by the caller to
5315 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5316 */
5317 if (type == DRM_MODE_CONNECTOR_eDP)
5318 intel_encoder->type = INTEL_OUTPUT_EDP;
5319
5320 /* eDP only on port B and/or C on vlv/chv */
5321 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5322 port != PORT_B && port != PORT_C))
5323 return false;
5324
5325 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5326 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5327 port_name(port));
5328
5329 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5330 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5331
5332 connector->interlace_allowed = true;
5333 connector->doublescan_allowed = 0;
5334
5335 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5336 edp_panel_vdd_work);
5337
5338 intel_connector_attach_encoder(intel_connector, intel_encoder);
5339 drm_connector_register(connector);
5340
5341 if (HAS_DDI(dev))
5342 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5343 else
5344 intel_connector->get_hw_state = intel_connector_get_hw_state;
5345 intel_connector->unregister = intel_dp_connector_unregister;
5346
5347 /* Set up the hotplug pin. */
5348 switch (port) {
5349 case PORT_A:
5350 intel_encoder->hpd_pin = HPD_PORT_A;
5351 break;
5352 case PORT_B:
5353 intel_encoder->hpd_pin = HPD_PORT_B;
5354 break;
5355 case PORT_C:
5356 intel_encoder->hpd_pin = HPD_PORT_C;
5357 break;
5358 case PORT_D:
5359 intel_encoder->hpd_pin = HPD_PORT_D;
5360 break;
5361 default:
5362 BUG();
5363 }
5364
5365 if (is_edp(intel_dp)) {
5366 pps_lock(intel_dp);
5367 if (IS_VALLEYVIEW(dev)) {
5368 vlv_initial_power_sequencer_setup(intel_dp);
5369 } else {
5370 intel_dp_init_panel_power_timestamps(intel_dp);
5371 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5372 }
5373 pps_unlock(intel_dp);
5374 }
5375
5376 intel_dp_aux_init(intel_dp, intel_connector);
5377
5378 /* init MST on ports that can support it */
5379 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5380 if (port == PORT_B || port == PORT_C || port == PORT_D) {
5381 intel_dp_mst_encoder_init(intel_dig_port,
5382 intel_connector->base.base.id);
5383 }
5384 }
5385
5386 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5387 drm_dp_aux_unregister(&intel_dp->aux);
5388 if (is_edp(intel_dp)) {
5389 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5390 /*
5391 * vdd might still be enabled do to the delayed vdd off.
5392 * Make sure vdd is actually turned off here.
5393 */
5394 pps_lock(intel_dp);
5395 edp_panel_vdd_off_sync(intel_dp);
5396 pps_unlock(intel_dp);
5397 }
5398 drm_connector_unregister(connector);
5399 drm_connector_cleanup(connector);
5400 return false;
5401 }
5402
5403 intel_dp_add_properties(intel_dp, connector);
5404
5405 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5406 * 0xd. Failure to do so will result in spurious interrupts being
5407 * generated on the port when a cable is not attached.
5408 */
5409 if (IS_G4X(dev) && !IS_GM45(dev)) {
5410 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5411 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5412 }
5413
5414 return true;
5415}
5416
5417void
5418intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5419{
5420 struct drm_i915_private *dev_priv = dev->dev_private;
5421 struct intel_digital_port *intel_dig_port;
5422 struct intel_encoder *intel_encoder;
5423 struct drm_encoder *encoder;
5424 struct intel_connector *intel_connector;
5425
5426 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5427 if (!intel_dig_port)
5428 return;
5429
5430 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
5431 if (!intel_connector) {
5432 kfree(intel_dig_port);
5433 return;
5434 }
5435
5436 intel_encoder = &intel_dig_port->base;
5437 encoder = &intel_encoder->base;
5438
5439 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5440 DRM_MODE_ENCODER_TMDS);
5441
5442 intel_encoder->compute_config = intel_dp_compute_config;
5443 intel_encoder->disable = intel_disable_dp;
5444 intel_encoder->get_hw_state = intel_dp_get_hw_state;
5445 intel_encoder->get_config = intel_dp_get_config;
5446 intel_encoder->suspend = intel_dp_encoder_suspend;
5447 if (IS_CHERRYVIEW(dev)) {
5448 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5449 intel_encoder->pre_enable = chv_pre_enable_dp;
5450 intel_encoder->enable = vlv_enable_dp;
5451 intel_encoder->post_disable = chv_post_disable_dp;
5452 } else if (IS_VALLEYVIEW(dev)) {
5453 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5454 intel_encoder->pre_enable = vlv_pre_enable_dp;
5455 intel_encoder->enable = vlv_enable_dp;
5456 intel_encoder->post_disable = vlv_post_disable_dp;
5457 } else {
5458 intel_encoder->pre_enable = g4x_pre_enable_dp;
5459 intel_encoder->enable = g4x_enable_dp;
5460 if (INTEL_INFO(dev)->gen >= 5)
5461 intel_encoder->post_disable = ilk_post_disable_dp;
5462 }
5463
5464 intel_dig_port->port = port;
5465 intel_dig_port->dp.output_reg = output_reg;
5466
5467 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
5468 if (IS_CHERRYVIEW(dev)) {
5469 if (port == PORT_D)
5470 intel_encoder->crtc_mask = 1 << 2;
5471 else
5472 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5473 } else {
5474 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5475 }
5476 intel_encoder->cloneable = 0;
5477 intel_encoder->hot_plug = intel_dp_hot_plug;
5478
5479 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5480 dev_priv->hpd_irq_port[port] = intel_dig_port;
5481
5482 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5483 drm_encoder_cleanup(encoder);
5484 kfree(intel_dig_port);
5485 kfree(intel_connector);
5486 }
5487}
5488
5489void intel_dp_mst_suspend(struct drm_device *dev)
5490{
5491 struct drm_i915_private *dev_priv = dev->dev_private;
5492 int i;
5493
5494 /* disable MST */
5495 for (i = 0; i < I915_MAX_PORTS; i++) {
5496 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5497 if (!intel_dig_port)
5498 continue;
5499
5500 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5501 if (!intel_dig_port->dp.can_mst)
5502 continue;
5503 if (intel_dig_port->dp.is_mst)
5504 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5505 }
5506 }
5507}
5508
5509void intel_dp_mst_resume(struct drm_device *dev)
5510{
5511 struct drm_i915_private *dev_priv = dev->dev_private;
5512 int i;
5513
5514 for (i = 0; i < I915_MAX_PORTS; i++) {
5515 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5516 if (!intel_dig_port)
5517 continue;
5518 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5519 int ret;
5520
5521 if (!intel_dig_port->dp.can_mst)
5522 continue;
5523
5524 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5525 if (ret != 0) {
5526 intel_dp_check_mst_status(&intel_dig_port->dp);
5527 }
5528 }
5529 }
5530}
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