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drm/i915: enable IPS for bpp <= 24
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
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1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
29#include <linux/slab.h>
30#include <linux/export.h>
31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
35#include "intel_drv.h"
36#include <drm/i915_drm.h>
37#include "i915_drv.h"
38
39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
53}
54
55static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
56{
57 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
58
59 return intel_dig_port->base.base.dev;
60}
61
62static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
63{
64 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
65}
66
67static void intel_dp_link_down(struct intel_dp *intel_dp);
68
69static int
70intel_dp_max_link_bw(struct intel_dp *intel_dp)
71{
72 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
73
74 switch (max_link_bw) {
75 case DP_LINK_BW_1_62:
76 case DP_LINK_BW_2_7:
77 break;
78 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
79 max_link_bw = DP_LINK_BW_2_7;
80 break;
81 default:
82 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
83 max_link_bw);
84 max_link_bw = DP_LINK_BW_1_62;
85 break;
86 }
87 return max_link_bw;
88}
89
90/*
91 * The units on the numbers in the next two are... bizarre. Examples will
92 * make it clearer; this one parallels an example in the eDP spec.
93 *
94 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
95 *
96 * 270000 * 1 * 8 / 10 == 216000
97 *
98 * The actual data capacity of that configuration is 2.16Gbit/s, so the
99 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
100 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
101 * 119000. At 18bpp that's 2142000 kilobits per second.
102 *
103 * Thus the strange-looking division by 10 in intel_dp_link_required, to
104 * get the result in decakilobits instead of kilobits.
105 */
106
107static int
108intel_dp_link_required(int pixel_clock, int bpp)
109{
110 return (pixel_clock * bpp + 9) / 10;
111}
112
113static int
114intel_dp_max_data_rate(int max_link_clock, int max_lanes)
115{
116 return (max_link_clock * max_lanes * 8) / 10;
117}
118
119static int
120intel_dp_mode_valid(struct drm_connector *connector,
121 struct drm_display_mode *mode)
122{
123 struct intel_dp *intel_dp = intel_attached_dp(connector);
124 struct intel_connector *intel_connector = to_intel_connector(connector);
125 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
126 int target_clock = mode->clock;
127 int max_rate, mode_rate, max_lanes, max_link_clock;
128
129 if (is_edp(intel_dp) && fixed_mode) {
130 if (mode->hdisplay > fixed_mode->hdisplay)
131 return MODE_PANEL;
132
133 if (mode->vdisplay > fixed_mode->vdisplay)
134 return MODE_PANEL;
135
136 target_clock = fixed_mode->clock;
137 }
138
139 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
140 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
141
142 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
143 mode_rate = intel_dp_link_required(target_clock, 18);
144
145 if (mode_rate > max_rate)
146 return MODE_CLOCK_HIGH;
147
148 if (mode->clock < 10000)
149 return MODE_CLOCK_LOW;
150
151 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
152 return MODE_H_ILLEGAL;
153
154 return MODE_OK;
155}
156
157static uint32_t
158pack_aux(uint8_t *src, int src_bytes)
159{
160 int i;
161 uint32_t v = 0;
162
163 if (src_bytes > 4)
164 src_bytes = 4;
165 for (i = 0; i < src_bytes; i++)
166 v |= ((uint32_t) src[i]) << ((3-i) * 8);
167 return v;
168}
169
170static void
171unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
172{
173 int i;
174 if (dst_bytes > 4)
175 dst_bytes = 4;
176 for (i = 0; i < dst_bytes; i++)
177 dst[i] = src >> ((3-i) * 8);
178}
179
180/* hrawclock is 1/4 the FSB frequency */
181static int
182intel_hrawclk(struct drm_device *dev)
183{
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 uint32_t clkcfg;
186
187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev))
189 return 200;
190
191 clkcfg = I915_READ(CLKCFG);
192 switch (clkcfg & CLKCFG_FSB_MASK) {
193 case CLKCFG_FSB_400:
194 return 100;
195 case CLKCFG_FSB_533:
196 return 133;
197 case CLKCFG_FSB_667:
198 return 166;
199 case CLKCFG_FSB_800:
200 return 200;
201 case CLKCFG_FSB_1067:
202 return 266;
203 case CLKCFG_FSB_1333:
204 return 333;
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600:
207 case CLKCFG_FSB_1600_ALT:
208 return 400;
209 default:
210 return 133;
211 }
212}
213
214static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
215{
216 struct drm_device *dev = intel_dp_to_dev(intel_dp);
217 struct drm_i915_private *dev_priv = dev->dev_private;
218 u32 pp_stat_reg;
219
220 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
221 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
222}
223
224static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
225{
226 struct drm_device *dev = intel_dp_to_dev(intel_dp);
227 struct drm_i915_private *dev_priv = dev->dev_private;
228 u32 pp_ctrl_reg;
229
230 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
231 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
232}
233
234static void
235intel_dp_check_edp(struct intel_dp *intel_dp)
236{
237 struct drm_device *dev = intel_dp_to_dev(intel_dp);
238 struct drm_i915_private *dev_priv = dev->dev_private;
239 u32 pp_stat_reg, pp_ctrl_reg;
240
241 if (!is_edp(intel_dp))
242 return;
243
244 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
245 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
246
247 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
248 WARN(1, "eDP powered off while attempting aux channel communication.\n");
249 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
250 I915_READ(pp_stat_reg),
251 I915_READ(pp_ctrl_reg));
252 }
253}
254
255static uint32_t
256intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
257{
258 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
259 struct drm_device *dev = intel_dig_port->base.base.dev;
260 struct drm_i915_private *dev_priv = dev->dev_private;
261 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
262 uint32_t status;
263 bool done;
264
265#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
266 if (has_aux_irq)
267 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
268 msecs_to_jiffies_timeout(10));
269 else
270 done = wait_for_atomic(C, 10) == 0;
271 if (!done)
272 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
273 has_aux_irq);
274#undef C
275
276 return status;
277}
278
279static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
280 int index)
281{
282 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
283 struct drm_device *dev = intel_dig_port->base.base.dev;
284 struct drm_i915_private *dev_priv = dev->dev_private;
285
286 /* The clock divider is based off the hrawclk,
287 * and would like to run at 2MHz. So, take the
288 * hrawclk value and divide by 2 and use that
289 *
290 * Note that PCH attached eDP panels should use a 125MHz input
291 * clock divider.
292 */
293 if (IS_VALLEYVIEW(dev)) {
294 return index ? 0 : 100;
295 } else if (intel_dig_port->port == PORT_A) {
296 if (index)
297 return 0;
298 if (HAS_DDI(dev))
299 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
300 else if (IS_GEN6(dev) || IS_GEN7(dev))
301 return 200; /* SNB & IVB eDP input clock at 400Mhz */
302 else
303 return 225; /* eDP input clock at 450Mhz */
304 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
305 /* Workaround for non-ULT HSW */
306 switch (index) {
307 case 0: return 63;
308 case 1: return 72;
309 default: return 0;
310 }
311 } else if (HAS_PCH_SPLIT(dev)) {
312 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
313 } else {
314 return index ? 0 :intel_hrawclk(dev) / 2;
315 }
316}
317
318static int
319intel_dp_aux_ch(struct intel_dp *intel_dp,
320 uint8_t *send, int send_bytes,
321 uint8_t *recv, int recv_size)
322{
323 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
324 struct drm_device *dev = intel_dig_port->base.base.dev;
325 struct drm_i915_private *dev_priv = dev->dev_private;
326 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
327 uint32_t ch_data = ch_ctl + 4;
328 uint32_t aux_clock_divider;
329 int i, ret, recv_bytes;
330 uint32_t status;
331 int try, precharge, clock = 0;
332 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
333
334 /* dp aux is extremely sensitive to irq latency, hence request the
335 * lowest possible wakeup latency and so prevent the cpu from going into
336 * deep sleep states.
337 */
338 pm_qos_update_request(&dev_priv->pm_qos, 0);
339
340 intel_dp_check_edp(intel_dp);
341
342 if (IS_GEN6(dev))
343 precharge = 3;
344 else
345 precharge = 5;
346
347 /* Try to wait for any previous AUX channel activity */
348 for (try = 0; try < 3; try++) {
349 status = I915_READ_NOTRACE(ch_ctl);
350 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
351 break;
352 msleep(1);
353 }
354
355 if (try == 3) {
356 WARN(1, "dp_aux_ch not started status 0x%08x\n",
357 I915_READ(ch_ctl));
358 ret = -EBUSY;
359 goto out;
360 }
361
362 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
363 /* Must try at least 3 times according to DP spec */
364 for (try = 0; try < 5; try++) {
365 /* Load the send data into the aux channel data registers */
366 for (i = 0; i < send_bytes; i += 4)
367 I915_WRITE(ch_data + i,
368 pack_aux(send + i, send_bytes - i));
369
370 /* Send the command and wait for it to complete */
371 I915_WRITE(ch_ctl,
372 DP_AUX_CH_CTL_SEND_BUSY |
373 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
374 DP_AUX_CH_CTL_TIME_OUT_400us |
375 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
376 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
377 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
378 DP_AUX_CH_CTL_DONE |
379 DP_AUX_CH_CTL_TIME_OUT_ERROR |
380 DP_AUX_CH_CTL_RECEIVE_ERROR);
381
382 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
383
384 /* Clear done status and any errors */
385 I915_WRITE(ch_ctl,
386 status |
387 DP_AUX_CH_CTL_DONE |
388 DP_AUX_CH_CTL_TIME_OUT_ERROR |
389 DP_AUX_CH_CTL_RECEIVE_ERROR);
390
391 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
392 DP_AUX_CH_CTL_RECEIVE_ERROR))
393 continue;
394 if (status & DP_AUX_CH_CTL_DONE)
395 break;
396 }
397 if (status & DP_AUX_CH_CTL_DONE)
398 break;
399 }
400
401 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
402 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
403 ret = -EBUSY;
404 goto out;
405 }
406
407 /* Check for timeout or receive error.
408 * Timeouts occur when the sink is not connected
409 */
410 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
411 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
412 ret = -EIO;
413 goto out;
414 }
415
416 /* Timeouts occur when the device isn't connected, so they're
417 * "normal" -- don't fill the kernel log with these */
418 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
419 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
420 ret = -ETIMEDOUT;
421 goto out;
422 }
423
424 /* Unload any bytes sent back from the other side */
425 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
426 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
427 if (recv_bytes > recv_size)
428 recv_bytes = recv_size;
429
430 for (i = 0; i < recv_bytes; i += 4)
431 unpack_aux(I915_READ(ch_data + i),
432 recv + i, recv_bytes - i);
433
434 ret = recv_bytes;
435out:
436 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
437
438 return ret;
439}
440
441/* Write data to the aux channel in native mode */
442static int
443intel_dp_aux_native_write(struct intel_dp *intel_dp,
444 uint16_t address, uint8_t *send, int send_bytes)
445{
446 int ret;
447 uint8_t msg[20];
448 int msg_bytes;
449 uint8_t ack;
450
451 intel_dp_check_edp(intel_dp);
452 if (send_bytes > 16)
453 return -1;
454 msg[0] = AUX_NATIVE_WRITE << 4;
455 msg[1] = address >> 8;
456 msg[2] = address & 0xff;
457 msg[3] = send_bytes - 1;
458 memcpy(&msg[4], send, send_bytes);
459 msg_bytes = send_bytes + 4;
460 for (;;) {
461 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
462 if (ret < 0)
463 return ret;
464 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
465 break;
466 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
467 udelay(100);
468 else
469 return -EIO;
470 }
471 return send_bytes;
472}
473
474/* Write a single byte to the aux channel in native mode */
475static int
476intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
477 uint16_t address, uint8_t byte)
478{
479 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
480}
481
482/* read bytes from a native aux channel */
483static int
484intel_dp_aux_native_read(struct intel_dp *intel_dp,
485 uint16_t address, uint8_t *recv, int recv_bytes)
486{
487 uint8_t msg[4];
488 int msg_bytes;
489 uint8_t reply[20];
490 int reply_bytes;
491 uint8_t ack;
492 int ret;
493
494 intel_dp_check_edp(intel_dp);
495 msg[0] = AUX_NATIVE_READ << 4;
496 msg[1] = address >> 8;
497 msg[2] = address & 0xff;
498 msg[3] = recv_bytes - 1;
499
500 msg_bytes = 4;
501 reply_bytes = recv_bytes + 1;
502
503 for (;;) {
504 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
505 reply, reply_bytes);
506 if (ret == 0)
507 return -EPROTO;
508 if (ret < 0)
509 return ret;
510 ack = reply[0];
511 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
512 memcpy(recv, reply + 1, ret - 1);
513 return ret - 1;
514 }
515 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
516 udelay(100);
517 else
518 return -EIO;
519 }
520}
521
522static int
523intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
524 uint8_t write_byte, uint8_t *read_byte)
525{
526 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
527 struct intel_dp *intel_dp = container_of(adapter,
528 struct intel_dp,
529 adapter);
530 uint16_t address = algo_data->address;
531 uint8_t msg[5];
532 uint8_t reply[2];
533 unsigned retry;
534 int msg_bytes;
535 int reply_bytes;
536 int ret;
537
538 intel_dp_check_edp(intel_dp);
539 /* Set up the command byte */
540 if (mode & MODE_I2C_READ)
541 msg[0] = AUX_I2C_READ << 4;
542 else
543 msg[0] = AUX_I2C_WRITE << 4;
544
545 if (!(mode & MODE_I2C_STOP))
546 msg[0] |= AUX_I2C_MOT << 4;
547
548 msg[1] = address >> 8;
549 msg[2] = address;
550
551 switch (mode) {
552 case MODE_I2C_WRITE:
553 msg[3] = 0;
554 msg[4] = write_byte;
555 msg_bytes = 5;
556 reply_bytes = 1;
557 break;
558 case MODE_I2C_READ:
559 msg[3] = 0;
560 msg_bytes = 4;
561 reply_bytes = 2;
562 break;
563 default:
564 msg_bytes = 3;
565 reply_bytes = 1;
566 break;
567 }
568
569 for (retry = 0; retry < 5; retry++) {
570 ret = intel_dp_aux_ch(intel_dp,
571 msg, msg_bytes,
572 reply, reply_bytes);
573 if (ret < 0) {
574 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
575 return ret;
576 }
577
578 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
579 case AUX_NATIVE_REPLY_ACK:
580 /* I2C-over-AUX Reply field is only valid
581 * when paired with AUX ACK.
582 */
583 break;
584 case AUX_NATIVE_REPLY_NACK:
585 DRM_DEBUG_KMS("aux_ch native nack\n");
586 return -EREMOTEIO;
587 case AUX_NATIVE_REPLY_DEFER:
588 udelay(100);
589 continue;
590 default:
591 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
592 reply[0]);
593 return -EREMOTEIO;
594 }
595
596 switch (reply[0] & AUX_I2C_REPLY_MASK) {
597 case AUX_I2C_REPLY_ACK:
598 if (mode == MODE_I2C_READ) {
599 *read_byte = reply[1];
600 }
601 return reply_bytes - 1;
602 case AUX_I2C_REPLY_NACK:
603 DRM_DEBUG_KMS("aux_i2c nack\n");
604 return -EREMOTEIO;
605 case AUX_I2C_REPLY_DEFER:
606 DRM_DEBUG_KMS("aux_i2c defer\n");
607 udelay(100);
608 break;
609 default:
610 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
611 return -EREMOTEIO;
612 }
613 }
614
615 DRM_ERROR("too many retries, giving up\n");
616 return -EREMOTEIO;
617}
618
619static int
620intel_dp_i2c_init(struct intel_dp *intel_dp,
621 struct intel_connector *intel_connector, const char *name)
622{
623 int ret;
624
625 DRM_DEBUG_KMS("i2c_init %s\n", name);
626 intel_dp->algo.running = false;
627 intel_dp->algo.address = 0;
628 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
629
630 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
631 intel_dp->adapter.owner = THIS_MODULE;
632 intel_dp->adapter.class = I2C_CLASS_DDC;
633 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
634 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
635 intel_dp->adapter.algo_data = &intel_dp->algo;
636 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
637
638 ironlake_edp_panel_vdd_on(intel_dp);
639 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
640 ironlake_edp_panel_vdd_off(intel_dp, false);
641 return ret;
642}
643
644static void
645intel_dp_set_clock(struct intel_encoder *encoder,
646 struct intel_crtc_config *pipe_config, int link_bw)
647{
648 struct drm_device *dev = encoder->base.dev;
649
650 if (IS_G4X(dev)) {
651 if (link_bw == DP_LINK_BW_1_62) {
652 pipe_config->dpll.p1 = 2;
653 pipe_config->dpll.p2 = 10;
654 pipe_config->dpll.n = 2;
655 pipe_config->dpll.m1 = 23;
656 pipe_config->dpll.m2 = 8;
657 } else {
658 pipe_config->dpll.p1 = 1;
659 pipe_config->dpll.p2 = 10;
660 pipe_config->dpll.n = 1;
661 pipe_config->dpll.m1 = 14;
662 pipe_config->dpll.m2 = 2;
663 }
664 pipe_config->clock_set = true;
665 } else if (IS_HASWELL(dev)) {
666 /* Haswell has special-purpose DP DDI clocks. */
667 } else if (HAS_PCH_SPLIT(dev)) {
668 if (link_bw == DP_LINK_BW_1_62) {
669 pipe_config->dpll.n = 1;
670 pipe_config->dpll.p1 = 2;
671 pipe_config->dpll.p2 = 10;
672 pipe_config->dpll.m1 = 12;
673 pipe_config->dpll.m2 = 9;
674 } else {
675 pipe_config->dpll.n = 2;
676 pipe_config->dpll.p1 = 1;
677 pipe_config->dpll.p2 = 10;
678 pipe_config->dpll.m1 = 14;
679 pipe_config->dpll.m2 = 8;
680 }
681 pipe_config->clock_set = true;
682 } else if (IS_VALLEYVIEW(dev)) {
683 /* FIXME: Need to figure out optimized DP clocks for vlv. */
684 }
685}
686
687bool
688intel_dp_compute_config(struct intel_encoder *encoder,
689 struct intel_crtc_config *pipe_config)
690{
691 struct drm_device *dev = encoder->base.dev;
692 struct drm_i915_private *dev_priv = dev->dev_private;
693 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
694 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
695 enum port port = dp_to_dig_port(intel_dp)->port;
696 struct intel_crtc *intel_crtc = encoder->new_crtc;
697 struct intel_connector *intel_connector = intel_dp->attached_connector;
698 int lane_count, clock;
699 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
700 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
701 int bpp, mode_rate;
702 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
703 int link_avail, link_clock;
704
705 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
706 pipe_config->has_pch_encoder = true;
707
708 pipe_config->has_dp_encoder = true;
709
710 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
711 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
712 adjusted_mode);
713 if (!HAS_PCH_SPLIT(dev))
714 intel_gmch_panel_fitting(intel_crtc, pipe_config,
715 intel_connector->panel.fitting_mode);
716 else
717 intel_pch_panel_fitting(intel_crtc, pipe_config,
718 intel_connector->panel.fitting_mode);
719 }
720
721 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
722 return false;
723
724 DRM_DEBUG_KMS("DP link computation with max lane count %i "
725 "max bw %02x pixel clock %iKHz\n",
726 max_lane_count, bws[max_clock], adjusted_mode->clock);
727
728 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
729 * bpc in between. */
730 bpp = pipe_config->pipe_bpp;
731 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) {
732 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
733 dev_priv->vbt.edp_bpp);
734 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
735 }
736
737 for (; bpp >= 6*3; bpp -= 2*3) {
738 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
739
740 for (clock = 0; clock <= max_clock; clock++) {
741 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
742 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
743 link_avail = intel_dp_max_data_rate(link_clock,
744 lane_count);
745
746 if (mode_rate <= link_avail) {
747 goto found;
748 }
749 }
750 }
751 }
752
753 return false;
754
755found:
756 if (intel_dp->color_range_auto) {
757 /*
758 * See:
759 * CEA-861-E - 5.1 Default Encoding Parameters
760 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
761 */
762 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
763 intel_dp->color_range = DP_COLOR_RANGE_16_235;
764 else
765 intel_dp->color_range = 0;
766 }
767
768 if (intel_dp->color_range)
769 pipe_config->limited_color_range = true;
770
771 intel_dp->link_bw = bws[clock];
772 intel_dp->lane_count = lane_count;
773 pipe_config->pipe_bpp = bpp;
774 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
775
776 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
777 intel_dp->link_bw, intel_dp->lane_count,
778 pipe_config->port_clock, bpp);
779 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
780 mode_rate, link_avail);
781
782 intel_link_compute_m_n(bpp, lane_count,
783 adjusted_mode->clock, pipe_config->port_clock,
784 &pipe_config->dp_m_n);
785
786 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
787
788 return true;
789}
790
791void intel_dp_init_link_config(struct intel_dp *intel_dp)
792{
793 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
794 intel_dp->link_configuration[0] = intel_dp->link_bw;
795 intel_dp->link_configuration[1] = intel_dp->lane_count;
796 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
797 /*
798 * Check for DPCD version > 1.1 and enhanced framing support
799 */
800 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
801 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
802 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
803 }
804}
805
806static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
807{
808 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
809 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
810 struct drm_device *dev = crtc->base.dev;
811 struct drm_i915_private *dev_priv = dev->dev_private;
812 u32 dpa_ctl;
813
814 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
815 dpa_ctl = I915_READ(DP_A);
816 dpa_ctl &= ~DP_PLL_FREQ_MASK;
817
818 if (crtc->config.port_clock == 162000) {
819 /* For a long time we've carried around a ILK-DevA w/a for the
820 * 160MHz clock. If we're really unlucky, it's still required.
821 */
822 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
823 dpa_ctl |= DP_PLL_FREQ_160MHZ;
824 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
825 } else {
826 dpa_ctl |= DP_PLL_FREQ_270MHZ;
827 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
828 }
829
830 I915_WRITE(DP_A, dpa_ctl);
831
832 POSTING_READ(DP_A);
833 udelay(500);
834}
835
836static void intel_dp_mode_set(struct intel_encoder *encoder)
837{
838 struct drm_device *dev = encoder->base.dev;
839 struct drm_i915_private *dev_priv = dev->dev_private;
840 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
841 enum port port = dp_to_dig_port(intel_dp)->port;
842 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
843 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
844
845 /*
846 * There are four kinds of DP registers:
847 *
848 * IBX PCH
849 * SNB CPU
850 * IVB CPU
851 * CPT PCH
852 *
853 * IBX PCH and CPU are the same for almost everything,
854 * except that the CPU DP PLL is configured in this
855 * register
856 *
857 * CPT PCH is quite different, having many bits moved
858 * to the TRANS_DP_CTL register instead. That
859 * configuration happens (oddly) in ironlake_pch_enable
860 */
861
862 /* Preserve the BIOS-computed detected bit. This is
863 * supposed to be read-only.
864 */
865 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
866
867 /* Handle DP bits in common between all three register formats */
868 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
869 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
870
871 if (intel_dp->has_audio) {
872 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
873 pipe_name(crtc->pipe));
874 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
875 intel_write_eld(&encoder->base, adjusted_mode);
876 }
877
878 intel_dp_init_link_config(intel_dp);
879
880 /* Split out the IBX/CPU vs CPT settings */
881
882 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
883 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
884 intel_dp->DP |= DP_SYNC_HS_HIGH;
885 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
886 intel_dp->DP |= DP_SYNC_VS_HIGH;
887 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
888
889 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
890 intel_dp->DP |= DP_ENHANCED_FRAMING;
891
892 intel_dp->DP |= crtc->pipe << 29;
893 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
894 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
895 intel_dp->DP |= intel_dp->color_range;
896
897 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
898 intel_dp->DP |= DP_SYNC_HS_HIGH;
899 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
900 intel_dp->DP |= DP_SYNC_VS_HIGH;
901 intel_dp->DP |= DP_LINK_TRAIN_OFF;
902
903 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
904 intel_dp->DP |= DP_ENHANCED_FRAMING;
905
906 if (crtc->pipe == 1)
907 intel_dp->DP |= DP_PIPEB_SELECT;
908 } else {
909 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
910 }
911
912 if (port == PORT_A && !IS_VALLEYVIEW(dev))
913 ironlake_set_pll_cpu_edp(intel_dp);
914}
915
916#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
917#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
918
919#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
920#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
921
922#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
923#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
924
925static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
926 u32 mask,
927 u32 value)
928{
929 struct drm_device *dev = intel_dp_to_dev(intel_dp);
930 struct drm_i915_private *dev_priv = dev->dev_private;
931 u32 pp_stat_reg, pp_ctrl_reg;
932
933 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
934 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
935
936 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
937 mask, value,
938 I915_READ(pp_stat_reg),
939 I915_READ(pp_ctrl_reg));
940
941 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
942 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
943 I915_READ(pp_stat_reg),
944 I915_READ(pp_ctrl_reg));
945 }
946}
947
948static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
949{
950 DRM_DEBUG_KMS("Wait for panel power on\n");
951 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
952}
953
954static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
955{
956 DRM_DEBUG_KMS("Wait for panel power off time\n");
957 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
958}
959
960static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
961{
962 DRM_DEBUG_KMS("Wait for panel power cycle\n");
963 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
964}
965
966
967/* Read the current pp_control value, unlocking the register if it
968 * is locked
969 */
970
971static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
972{
973 struct drm_device *dev = intel_dp_to_dev(intel_dp);
974 struct drm_i915_private *dev_priv = dev->dev_private;
975 u32 control;
976 u32 pp_ctrl_reg;
977
978 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
979 control = I915_READ(pp_ctrl_reg);
980
981 control &= ~PANEL_UNLOCK_MASK;
982 control |= PANEL_UNLOCK_REGS;
983 return control;
984}
985
986void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
987{
988 struct drm_device *dev = intel_dp_to_dev(intel_dp);
989 struct drm_i915_private *dev_priv = dev->dev_private;
990 u32 pp;
991 u32 pp_stat_reg, pp_ctrl_reg;
992
993 if (!is_edp(intel_dp))
994 return;
995 DRM_DEBUG_KMS("Turn eDP VDD on\n");
996
997 WARN(intel_dp->want_panel_vdd,
998 "eDP VDD already requested on\n");
999
1000 intel_dp->want_panel_vdd = true;
1001
1002 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1003 DRM_DEBUG_KMS("eDP VDD already on\n");
1004 return;
1005 }
1006
1007 if (!ironlake_edp_have_panel_power(intel_dp))
1008 ironlake_wait_panel_power_cycle(intel_dp);
1009
1010 pp = ironlake_get_pp_control(intel_dp);
1011 pp |= EDP_FORCE_VDD;
1012
1013 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1014 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1015
1016 I915_WRITE(pp_ctrl_reg, pp);
1017 POSTING_READ(pp_ctrl_reg);
1018 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1019 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1020 /*
1021 * If the panel wasn't on, delay before accessing aux channel
1022 */
1023 if (!ironlake_edp_have_panel_power(intel_dp)) {
1024 DRM_DEBUG_KMS("eDP was not running\n");
1025 msleep(intel_dp->panel_power_up_delay);
1026 }
1027}
1028
1029static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1030{
1031 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1032 struct drm_i915_private *dev_priv = dev->dev_private;
1033 u32 pp;
1034 u32 pp_stat_reg, pp_ctrl_reg;
1035
1036 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1037
1038 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1039 pp = ironlake_get_pp_control(intel_dp);
1040 pp &= ~EDP_FORCE_VDD;
1041
1042 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1043 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1044
1045 I915_WRITE(pp_ctrl_reg, pp);
1046 POSTING_READ(pp_ctrl_reg);
1047
1048 /* Make sure sequencer is idle before allowing subsequent activity */
1049 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1050 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1051 msleep(intel_dp->panel_power_down_delay);
1052 }
1053}
1054
1055static void ironlake_panel_vdd_work(struct work_struct *__work)
1056{
1057 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1058 struct intel_dp, panel_vdd_work);
1059 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1060
1061 mutex_lock(&dev->mode_config.mutex);
1062 ironlake_panel_vdd_off_sync(intel_dp);
1063 mutex_unlock(&dev->mode_config.mutex);
1064}
1065
1066void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1067{
1068 if (!is_edp(intel_dp))
1069 return;
1070
1071 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1072 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1073
1074 intel_dp->want_panel_vdd = false;
1075
1076 if (sync) {
1077 ironlake_panel_vdd_off_sync(intel_dp);
1078 } else {
1079 /*
1080 * Queue the timer to fire a long
1081 * time from now (relative to the power down delay)
1082 * to keep the panel power up across a sequence of operations
1083 */
1084 schedule_delayed_work(&intel_dp->panel_vdd_work,
1085 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1086 }
1087}
1088
1089void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1090{
1091 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1092 struct drm_i915_private *dev_priv = dev->dev_private;
1093 u32 pp;
1094 u32 pp_ctrl_reg;
1095
1096 if (!is_edp(intel_dp))
1097 return;
1098
1099 DRM_DEBUG_KMS("Turn eDP power on\n");
1100
1101 if (ironlake_edp_have_panel_power(intel_dp)) {
1102 DRM_DEBUG_KMS("eDP power already on\n");
1103 return;
1104 }
1105
1106 ironlake_wait_panel_power_cycle(intel_dp);
1107
1108 pp = ironlake_get_pp_control(intel_dp);
1109 if (IS_GEN5(dev)) {
1110 /* ILK workaround: disable reset around power sequence */
1111 pp &= ~PANEL_POWER_RESET;
1112 I915_WRITE(PCH_PP_CONTROL, pp);
1113 POSTING_READ(PCH_PP_CONTROL);
1114 }
1115
1116 pp |= POWER_TARGET_ON;
1117 if (!IS_GEN5(dev))
1118 pp |= PANEL_POWER_RESET;
1119
1120 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1121
1122 I915_WRITE(pp_ctrl_reg, pp);
1123 POSTING_READ(pp_ctrl_reg);
1124
1125 ironlake_wait_panel_on(intel_dp);
1126
1127 if (IS_GEN5(dev)) {
1128 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1129 I915_WRITE(PCH_PP_CONTROL, pp);
1130 POSTING_READ(PCH_PP_CONTROL);
1131 }
1132}
1133
1134void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1135{
1136 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1137 struct drm_i915_private *dev_priv = dev->dev_private;
1138 u32 pp;
1139 u32 pp_ctrl_reg;
1140
1141 if (!is_edp(intel_dp))
1142 return;
1143
1144 DRM_DEBUG_KMS("Turn eDP power off\n");
1145
1146 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1147
1148 pp = ironlake_get_pp_control(intel_dp);
1149 /* We need to switch off panel power _and_ force vdd, for otherwise some
1150 * panels get very unhappy and cease to work. */
1151 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1152
1153 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1154
1155 I915_WRITE(pp_ctrl_reg, pp);
1156 POSTING_READ(pp_ctrl_reg);
1157
1158 intel_dp->want_panel_vdd = false;
1159
1160 ironlake_wait_panel_off(intel_dp);
1161}
1162
1163void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1164{
1165 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1166 struct drm_device *dev = intel_dig_port->base.base.dev;
1167 struct drm_i915_private *dev_priv = dev->dev_private;
1168 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1169 u32 pp;
1170 u32 pp_ctrl_reg;
1171
1172 if (!is_edp(intel_dp))
1173 return;
1174
1175 DRM_DEBUG_KMS("\n");
1176 /*
1177 * If we enable the backlight right away following a panel power
1178 * on, we may see slight flicker as the panel syncs with the eDP
1179 * link. So delay a bit to make sure the image is solid before
1180 * allowing it to appear.
1181 */
1182 msleep(intel_dp->backlight_on_delay);
1183 pp = ironlake_get_pp_control(intel_dp);
1184 pp |= EDP_BLC_ENABLE;
1185
1186 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1187
1188 I915_WRITE(pp_ctrl_reg, pp);
1189 POSTING_READ(pp_ctrl_reg);
1190
1191 intel_panel_enable_backlight(dev, pipe);
1192}
1193
1194void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1195{
1196 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1197 struct drm_i915_private *dev_priv = dev->dev_private;
1198 u32 pp;
1199 u32 pp_ctrl_reg;
1200
1201 if (!is_edp(intel_dp))
1202 return;
1203
1204 intel_panel_disable_backlight(dev);
1205
1206 DRM_DEBUG_KMS("\n");
1207 pp = ironlake_get_pp_control(intel_dp);
1208 pp &= ~EDP_BLC_ENABLE;
1209
1210 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1211
1212 I915_WRITE(pp_ctrl_reg, pp);
1213 POSTING_READ(pp_ctrl_reg);
1214 msleep(intel_dp->backlight_off_delay);
1215}
1216
1217static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1218{
1219 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1220 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1221 struct drm_device *dev = crtc->dev;
1222 struct drm_i915_private *dev_priv = dev->dev_private;
1223 u32 dpa_ctl;
1224
1225 assert_pipe_disabled(dev_priv,
1226 to_intel_crtc(crtc)->pipe);
1227
1228 DRM_DEBUG_KMS("\n");
1229 dpa_ctl = I915_READ(DP_A);
1230 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1231 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1232
1233 /* We don't adjust intel_dp->DP while tearing down the link, to
1234 * facilitate link retraining (e.g. after hotplug). Hence clear all
1235 * enable bits here to ensure that we don't enable too much. */
1236 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1237 intel_dp->DP |= DP_PLL_ENABLE;
1238 I915_WRITE(DP_A, intel_dp->DP);
1239 POSTING_READ(DP_A);
1240 udelay(200);
1241}
1242
1243static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1244{
1245 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1246 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1247 struct drm_device *dev = crtc->dev;
1248 struct drm_i915_private *dev_priv = dev->dev_private;
1249 u32 dpa_ctl;
1250
1251 assert_pipe_disabled(dev_priv,
1252 to_intel_crtc(crtc)->pipe);
1253
1254 dpa_ctl = I915_READ(DP_A);
1255 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1256 "dp pll off, should be on\n");
1257 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1258
1259 /* We can't rely on the value tracked for the DP register in
1260 * intel_dp->DP because link_down must not change that (otherwise link
1261 * re-training will fail. */
1262 dpa_ctl &= ~DP_PLL_ENABLE;
1263 I915_WRITE(DP_A, dpa_ctl);
1264 POSTING_READ(DP_A);
1265 udelay(200);
1266}
1267
1268/* If the sink supports it, try to set the power state appropriately */
1269void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1270{
1271 int ret, i;
1272
1273 /* Should have a valid DPCD by this point */
1274 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1275 return;
1276
1277 if (mode != DRM_MODE_DPMS_ON) {
1278 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1279 DP_SET_POWER_D3);
1280 if (ret != 1)
1281 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1282 } else {
1283 /*
1284 * When turning on, we need to retry for 1ms to give the sink
1285 * time to wake up.
1286 */
1287 for (i = 0; i < 3; i++) {
1288 ret = intel_dp_aux_native_write_1(intel_dp,
1289 DP_SET_POWER,
1290 DP_SET_POWER_D0);
1291 if (ret == 1)
1292 break;
1293 msleep(1);
1294 }
1295 }
1296}
1297
1298static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1299 enum pipe *pipe)
1300{
1301 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1302 enum port port = dp_to_dig_port(intel_dp)->port;
1303 struct drm_device *dev = encoder->base.dev;
1304 struct drm_i915_private *dev_priv = dev->dev_private;
1305 u32 tmp = I915_READ(intel_dp->output_reg);
1306
1307 if (!(tmp & DP_PORT_EN))
1308 return false;
1309
1310 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1311 *pipe = PORT_TO_PIPE_CPT(tmp);
1312 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1313 *pipe = PORT_TO_PIPE(tmp);
1314 } else {
1315 u32 trans_sel;
1316 u32 trans_dp;
1317 int i;
1318
1319 switch (intel_dp->output_reg) {
1320 case PCH_DP_B:
1321 trans_sel = TRANS_DP_PORT_SEL_B;
1322 break;
1323 case PCH_DP_C:
1324 trans_sel = TRANS_DP_PORT_SEL_C;
1325 break;
1326 case PCH_DP_D:
1327 trans_sel = TRANS_DP_PORT_SEL_D;
1328 break;
1329 default:
1330 return true;
1331 }
1332
1333 for_each_pipe(i) {
1334 trans_dp = I915_READ(TRANS_DP_CTL(i));
1335 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1336 *pipe = i;
1337 return true;
1338 }
1339 }
1340
1341 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1342 intel_dp->output_reg);
1343 }
1344
1345 return true;
1346}
1347
1348static void intel_dp_get_config(struct intel_encoder *encoder,
1349 struct intel_crtc_config *pipe_config)
1350{
1351 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1352 u32 tmp, flags = 0;
1353 struct drm_device *dev = encoder->base.dev;
1354 struct drm_i915_private *dev_priv = dev->dev_private;
1355 enum port port = dp_to_dig_port(intel_dp)->port;
1356 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1357
1358 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1359 tmp = I915_READ(intel_dp->output_reg);
1360 if (tmp & DP_SYNC_HS_HIGH)
1361 flags |= DRM_MODE_FLAG_PHSYNC;
1362 else
1363 flags |= DRM_MODE_FLAG_NHSYNC;
1364
1365 if (tmp & DP_SYNC_VS_HIGH)
1366 flags |= DRM_MODE_FLAG_PVSYNC;
1367 else
1368 flags |= DRM_MODE_FLAG_NVSYNC;
1369 } else {
1370 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1371 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1372 flags |= DRM_MODE_FLAG_PHSYNC;
1373 else
1374 flags |= DRM_MODE_FLAG_NHSYNC;
1375
1376 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1377 flags |= DRM_MODE_FLAG_PVSYNC;
1378 else
1379 flags |= DRM_MODE_FLAG_NVSYNC;
1380 }
1381
1382 pipe_config->adjusted_mode.flags |= flags;
1383
1384 if (dp_to_dig_port(intel_dp)->port == PORT_A) {
1385 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1386 pipe_config->port_clock = 162000;
1387 else
1388 pipe_config->port_clock = 270000;
1389 }
1390}
1391
1392static bool is_edp_psr(struct intel_dp *intel_dp)
1393{
1394 return is_edp(intel_dp) &&
1395 intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1396}
1397
1398static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1399{
1400 struct drm_i915_private *dev_priv = dev->dev_private;
1401
1402 if (!IS_HASWELL(dev))
1403 return false;
1404
1405 return I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
1406}
1407
1408static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1409 struct edp_vsc_psr *vsc_psr)
1410{
1411 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1412 struct drm_device *dev = dig_port->base.base.dev;
1413 struct drm_i915_private *dev_priv = dev->dev_private;
1414 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1415 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1416 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1417 uint32_t *data = (uint32_t *) vsc_psr;
1418 unsigned int i;
1419
1420 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1421 the video DIP being updated before program video DIP data buffer
1422 registers for DIP being updated. */
1423 I915_WRITE(ctl_reg, 0);
1424 POSTING_READ(ctl_reg);
1425
1426 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1427 if (i < sizeof(struct edp_vsc_psr))
1428 I915_WRITE(data_reg + i, *data++);
1429 else
1430 I915_WRITE(data_reg + i, 0);
1431 }
1432
1433 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1434 POSTING_READ(ctl_reg);
1435}
1436
1437static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1438{
1439 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1440 struct drm_i915_private *dev_priv = dev->dev_private;
1441 struct edp_vsc_psr psr_vsc;
1442
1443 if (intel_dp->psr_setup_done)
1444 return;
1445
1446 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1447 memset(&psr_vsc, 0, sizeof(psr_vsc));
1448 psr_vsc.sdp_header.HB0 = 0;
1449 psr_vsc.sdp_header.HB1 = 0x7;
1450 psr_vsc.sdp_header.HB2 = 0x2;
1451 psr_vsc.sdp_header.HB3 = 0x8;
1452 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1453
1454 /* Avoid continuous PSR exit by masking memup and hpd */
1455 I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
1456 EDP_PSR_DEBUG_MASK_HPD);
1457
1458 intel_dp->psr_setup_done = true;
1459}
1460
1461static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1462{
1463 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1464 struct drm_i915_private *dev_priv = dev->dev_private;
1465 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
1466 int precharge = 0x3;
1467 int msg_size = 5; /* Header(4) + Message(1) */
1468
1469 /* Enable PSR in sink */
1470 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1471 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1472 DP_PSR_ENABLE &
1473 ~DP_PSR_MAIN_LINK_ACTIVE);
1474 else
1475 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1476 DP_PSR_ENABLE |
1477 DP_PSR_MAIN_LINK_ACTIVE);
1478
1479 /* Setup AUX registers */
1480 I915_WRITE(EDP_PSR_AUX_DATA1, EDP_PSR_DPCD_COMMAND);
1481 I915_WRITE(EDP_PSR_AUX_DATA2, EDP_PSR_DPCD_NORMAL_OPERATION);
1482 I915_WRITE(EDP_PSR_AUX_CTL,
1483 DP_AUX_CH_CTL_TIME_OUT_400us |
1484 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1485 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1486 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1487}
1488
1489static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1490{
1491 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1492 struct drm_i915_private *dev_priv = dev->dev_private;
1493 uint32_t max_sleep_time = 0x1f;
1494 uint32_t idle_frames = 1;
1495 uint32_t val = 0x0;
1496
1497 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1498 val |= EDP_PSR_LINK_STANDBY;
1499 val |= EDP_PSR_TP2_TP3_TIME_0us;
1500 val |= EDP_PSR_TP1_TIME_0us;
1501 val |= EDP_PSR_SKIP_AUX_EXIT;
1502 } else
1503 val |= EDP_PSR_LINK_DISABLE;
1504
1505 I915_WRITE(EDP_PSR_CTL, val |
1506 EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
1507 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1508 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1509 EDP_PSR_ENABLE);
1510}
1511
1512static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1513{
1514 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1515 struct drm_device *dev = dig_port->base.base.dev;
1516 struct drm_i915_private *dev_priv = dev->dev_private;
1517 struct drm_crtc *crtc = dig_port->base.base.crtc;
1518 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1519 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1520 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1521
1522 if (!IS_HASWELL(dev)) {
1523 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1524 dev_priv->no_psr_reason = PSR_NO_SOURCE;
1525 return false;
1526 }
1527
1528 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1529 (dig_port->port != PORT_A)) {
1530 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1531 dev_priv->no_psr_reason = PSR_HSW_NOT_DDIA;
1532 return false;
1533 }
1534
1535 if (!is_edp_psr(intel_dp)) {
1536 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1537 dev_priv->no_psr_reason = PSR_NO_SINK;
1538 return false;
1539 }
1540
1541 if (!i915_enable_psr) {
1542 DRM_DEBUG_KMS("PSR disable by flag\n");
1543 dev_priv->no_psr_reason = PSR_MODULE_PARAM;
1544 return false;
1545 }
1546
1547 crtc = dig_port->base.base.crtc;
1548 if (crtc == NULL) {
1549 DRM_DEBUG_KMS("crtc not active for PSR\n");
1550 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1551 return false;
1552 }
1553
1554 intel_crtc = to_intel_crtc(crtc);
1555 if (!intel_crtc->active || !crtc->fb || !crtc->mode.clock) {
1556 DRM_DEBUG_KMS("crtc not active for PSR\n");
1557 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1558 return false;
1559 }
1560
1561 obj = to_intel_framebuffer(crtc->fb)->obj;
1562 if (obj->tiling_mode != I915_TILING_X ||
1563 obj->fence_reg == I915_FENCE_REG_NONE) {
1564 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1565 dev_priv->no_psr_reason = PSR_NOT_TILED;
1566 return false;
1567 }
1568
1569 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1570 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1571 dev_priv->no_psr_reason = PSR_SPRITE_ENABLED;
1572 return false;
1573 }
1574
1575 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1576 S3D_ENABLE) {
1577 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1578 dev_priv->no_psr_reason = PSR_S3D_ENABLED;
1579 return false;
1580 }
1581
1582 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
1583 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1584 dev_priv->no_psr_reason = PSR_INTERLACED_ENABLED;
1585 return false;
1586 }
1587
1588 return true;
1589}
1590
1591static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1592{
1593 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1594
1595 if (!intel_edp_psr_match_conditions(intel_dp) ||
1596 intel_edp_is_psr_enabled(dev))
1597 return;
1598
1599 /* Setup PSR once */
1600 intel_edp_psr_setup(intel_dp);
1601
1602 /* Enable PSR on the panel */
1603 intel_edp_psr_enable_sink(intel_dp);
1604
1605 /* Enable PSR on the host */
1606 intel_edp_psr_enable_source(intel_dp);
1607}
1608
1609void intel_edp_psr_enable(struct intel_dp *intel_dp)
1610{
1611 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1612
1613 if (intel_edp_psr_match_conditions(intel_dp) &&
1614 !intel_edp_is_psr_enabled(dev))
1615 intel_edp_psr_do_enable(intel_dp);
1616}
1617
1618void intel_edp_psr_disable(struct intel_dp *intel_dp)
1619{
1620 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1621 struct drm_i915_private *dev_priv = dev->dev_private;
1622
1623 if (!intel_edp_is_psr_enabled(dev))
1624 return;
1625
1626 I915_WRITE(EDP_PSR_CTL, I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
1627
1628 /* Wait till PSR is idle */
1629 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
1630 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1631 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1632}
1633
1634void intel_edp_psr_update(struct drm_device *dev)
1635{
1636 struct intel_encoder *encoder;
1637 struct intel_dp *intel_dp = NULL;
1638
1639 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1640 if (encoder->type == INTEL_OUTPUT_EDP) {
1641 intel_dp = enc_to_intel_dp(&encoder->base);
1642
1643 if (!is_edp_psr(intel_dp))
1644 return;
1645
1646 if (!intel_edp_psr_match_conditions(intel_dp))
1647 intel_edp_psr_disable(intel_dp);
1648 else
1649 if (!intel_edp_is_psr_enabled(dev))
1650 intel_edp_psr_do_enable(intel_dp);
1651 }
1652}
1653
1654static void intel_disable_dp(struct intel_encoder *encoder)
1655{
1656 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1657 enum port port = dp_to_dig_port(intel_dp)->port;
1658 struct drm_device *dev = encoder->base.dev;
1659
1660 /* Make sure the panel is off before trying to change the mode. But also
1661 * ensure that we have vdd while we switch off the panel. */
1662 ironlake_edp_panel_vdd_on(intel_dp);
1663 ironlake_edp_backlight_off(intel_dp);
1664 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1665 ironlake_edp_panel_off(intel_dp);
1666
1667 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1668 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1669 intel_dp_link_down(intel_dp);
1670}
1671
1672static void intel_post_disable_dp(struct intel_encoder *encoder)
1673{
1674 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1675 enum port port = dp_to_dig_port(intel_dp)->port;
1676 struct drm_device *dev = encoder->base.dev;
1677
1678 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1679 intel_dp_link_down(intel_dp);
1680 if (!IS_VALLEYVIEW(dev))
1681 ironlake_edp_pll_off(intel_dp);
1682 }
1683}
1684
1685static void intel_enable_dp(struct intel_encoder *encoder)
1686{
1687 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1688 struct drm_device *dev = encoder->base.dev;
1689 struct drm_i915_private *dev_priv = dev->dev_private;
1690 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1691
1692 if (WARN_ON(dp_reg & DP_PORT_EN))
1693 return;
1694
1695 ironlake_edp_panel_vdd_on(intel_dp);
1696 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1697 intel_dp_start_link_train(intel_dp);
1698 ironlake_edp_panel_on(intel_dp);
1699 ironlake_edp_panel_vdd_off(intel_dp, true);
1700 intel_dp_complete_link_train(intel_dp);
1701 intel_dp_stop_link_train(intel_dp);
1702 ironlake_edp_backlight_on(intel_dp);
1703
1704 if (IS_VALLEYVIEW(dev)) {
1705 struct intel_digital_port *dport =
1706 enc_to_dig_port(&encoder->base);
1707 int channel = vlv_dport_to_channel(dport);
1708
1709 vlv_wait_port_ready(dev_priv, channel);
1710 }
1711}
1712
1713static void intel_pre_enable_dp(struct intel_encoder *encoder)
1714{
1715 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1716 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1717 struct drm_device *dev = encoder->base.dev;
1718 struct drm_i915_private *dev_priv = dev->dev_private;
1719
1720 if (dport->port == PORT_A && !IS_VALLEYVIEW(dev))
1721 ironlake_edp_pll_on(intel_dp);
1722
1723 if (IS_VALLEYVIEW(dev)) {
1724 struct intel_crtc *intel_crtc =
1725 to_intel_crtc(encoder->base.crtc);
1726 int port = vlv_dport_to_channel(dport);
1727 int pipe = intel_crtc->pipe;
1728 u32 val;
1729
1730 val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1731 val = 0;
1732 if (pipe)
1733 val |= (1<<21);
1734 else
1735 val &= ~(1<<21);
1736 val |= 0x001000c4;
1737 vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1738
1739 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
1740 0x00760018);
1741 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
1742 0x00400888);
1743 }
1744}
1745
1746static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1747{
1748 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1749 struct drm_device *dev = encoder->base.dev;
1750 struct drm_i915_private *dev_priv = dev->dev_private;
1751 int port = vlv_dport_to_channel(dport);
1752
1753 if (!IS_VALLEYVIEW(dev))
1754 return;
1755
1756 /* Program Tx lane resets to default */
1757 vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
1758 DPIO_PCS_TX_LANE2_RESET |
1759 DPIO_PCS_TX_LANE1_RESET);
1760 vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1761 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1762 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1763 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1764 DPIO_PCS_CLK_SOFT_RESET);
1765
1766 /* Fix up inter-pair skew failure */
1767 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1768 vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1769 vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
1770}
1771
1772/*
1773 * Native read with retry for link status and receiver capability reads for
1774 * cases where the sink may still be asleep.
1775 */
1776static bool
1777intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1778 uint8_t *recv, int recv_bytes)
1779{
1780 int ret, i;
1781
1782 /*
1783 * Sinks are *supposed* to come up within 1ms from an off state,
1784 * but we're also supposed to retry 3 times per the spec.
1785 */
1786 for (i = 0; i < 3; i++) {
1787 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1788 recv_bytes);
1789 if (ret == recv_bytes)
1790 return true;
1791 msleep(1);
1792 }
1793
1794 return false;
1795}
1796
1797/*
1798 * Fetch AUX CH registers 0x202 - 0x207 which contain
1799 * link status information
1800 */
1801static bool
1802intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1803{
1804 return intel_dp_aux_native_read_retry(intel_dp,
1805 DP_LANE0_1_STATUS,
1806 link_status,
1807 DP_LINK_STATUS_SIZE);
1808}
1809
1810#if 0
1811static char *voltage_names[] = {
1812 "0.4V", "0.6V", "0.8V", "1.2V"
1813};
1814static char *pre_emph_names[] = {
1815 "0dB", "3.5dB", "6dB", "9.5dB"
1816};
1817static char *link_train_names[] = {
1818 "pattern 1", "pattern 2", "idle", "off"
1819};
1820#endif
1821
1822/*
1823 * These are source-specific values; current Intel hardware supports
1824 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1825 */
1826
1827static uint8_t
1828intel_dp_voltage_max(struct intel_dp *intel_dp)
1829{
1830 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1831 enum port port = dp_to_dig_port(intel_dp)->port;
1832
1833 if (IS_VALLEYVIEW(dev))
1834 return DP_TRAIN_VOLTAGE_SWING_1200;
1835 else if (IS_GEN7(dev) && port == PORT_A)
1836 return DP_TRAIN_VOLTAGE_SWING_800;
1837 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1838 return DP_TRAIN_VOLTAGE_SWING_1200;
1839 else
1840 return DP_TRAIN_VOLTAGE_SWING_800;
1841}
1842
1843static uint8_t
1844intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1845{
1846 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1847 enum port port = dp_to_dig_port(intel_dp)->port;
1848
1849 if (HAS_DDI(dev)) {
1850 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1851 case DP_TRAIN_VOLTAGE_SWING_400:
1852 return DP_TRAIN_PRE_EMPHASIS_9_5;
1853 case DP_TRAIN_VOLTAGE_SWING_600:
1854 return DP_TRAIN_PRE_EMPHASIS_6;
1855 case DP_TRAIN_VOLTAGE_SWING_800:
1856 return DP_TRAIN_PRE_EMPHASIS_3_5;
1857 case DP_TRAIN_VOLTAGE_SWING_1200:
1858 default:
1859 return DP_TRAIN_PRE_EMPHASIS_0;
1860 }
1861 } else if (IS_VALLEYVIEW(dev)) {
1862 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1863 case DP_TRAIN_VOLTAGE_SWING_400:
1864 return DP_TRAIN_PRE_EMPHASIS_9_5;
1865 case DP_TRAIN_VOLTAGE_SWING_600:
1866 return DP_TRAIN_PRE_EMPHASIS_6;
1867 case DP_TRAIN_VOLTAGE_SWING_800:
1868 return DP_TRAIN_PRE_EMPHASIS_3_5;
1869 case DP_TRAIN_VOLTAGE_SWING_1200:
1870 default:
1871 return DP_TRAIN_PRE_EMPHASIS_0;
1872 }
1873 } else if (IS_GEN7(dev) && port == PORT_A) {
1874 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1875 case DP_TRAIN_VOLTAGE_SWING_400:
1876 return DP_TRAIN_PRE_EMPHASIS_6;
1877 case DP_TRAIN_VOLTAGE_SWING_600:
1878 case DP_TRAIN_VOLTAGE_SWING_800:
1879 return DP_TRAIN_PRE_EMPHASIS_3_5;
1880 default:
1881 return DP_TRAIN_PRE_EMPHASIS_0;
1882 }
1883 } else {
1884 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1885 case DP_TRAIN_VOLTAGE_SWING_400:
1886 return DP_TRAIN_PRE_EMPHASIS_6;
1887 case DP_TRAIN_VOLTAGE_SWING_600:
1888 return DP_TRAIN_PRE_EMPHASIS_6;
1889 case DP_TRAIN_VOLTAGE_SWING_800:
1890 return DP_TRAIN_PRE_EMPHASIS_3_5;
1891 case DP_TRAIN_VOLTAGE_SWING_1200:
1892 default:
1893 return DP_TRAIN_PRE_EMPHASIS_0;
1894 }
1895 }
1896}
1897
1898static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1899{
1900 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1901 struct drm_i915_private *dev_priv = dev->dev_private;
1902 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1903 unsigned long demph_reg_value, preemph_reg_value,
1904 uniqtranscale_reg_value;
1905 uint8_t train_set = intel_dp->train_set[0];
1906 int port = vlv_dport_to_channel(dport);
1907
1908 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1909 case DP_TRAIN_PRE_EMPHASIS_0:
1910 preemph_reg_value = 0x0004000;
1911 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1912 case DP_TRAIN_VOLTAGE_SWING_400:
1913 demph_reg_value = 0x2B405555;
1914 uniqtranscale_reg_value = 0x552AB83A;
1915 break;
1916 case DP_TRAIN_VOLTAGE_SWING_600:
1917 demph_reg_value = 0x2B404040;
1918 uniqtranscale_reg_value = 0x5548B83A;
1919 break;
1920 case DP_TRAIN_VOLTAGE_SWING_800:
1921 demph_reg_value = 0x2B245555;
1922 uniqtranscale_reg_value = 0x5560B83A;
1923 break;
1924 case DP_TRAIN_VOLTAGE_SWING_1200:
1925 demph_reg_value = 0x2B405555;
1926 uniqtranscale_reg_value = 0x5598DA3A;
1927 break;
1928 default:
1929 return 0;
1930 }
1931 break;
1932 case DP_TRAIN_PRE_EMPHASIS_3_5:
1933 preemph_reg_value = 0x0002000;
1934 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1935 case DP_TRAIN_VOLTAGE_SWING_400:
1936 demph_reg_value = 0x2B404040;
1937 uniqtranscale_reg_value = 0x5552B83A;
1938 break;
1939 case DP_TRAIN_VOLTAGE_SWING_600:
1940 demph_reg_value = 0x2B404848;
1941 uniqtranscale_reg_value = 0x5580B83A;
1942 break;
1943 case DP_TRAIN_VOLTAGE_SWING_800:
1944 demph_reg_value = 0x2B404040;
1945 uniqtranscale_reg_value = 0x55ADDA3A;
1946 break;
1947 default:
1948 return 0;
1949 }
1950 break;
1951 case DP_TRAIN_PRE_EMPHASIS_6:
1952 preemph_reg_value = 0x0000000;
1953 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1954 case DP_TRAIN_VOLTAGE_SWING_400:
1955 demph_reg_value = 0x2B305555;
1956 uniqtranscale_reg_value = 0x5570B83A;
1957 break;
1958 case DP_TRAIN_VOLTAGE_SWING_600:
1959 demph_reg_value = 0x2B2B4040;
1960 uniqtranscale_reg_value = 0x55ADDA3A;
1961 break;
1962 default:
1963 return 0;
1964 }
1965 break;
1966 case DP_TRAIN_PRE_EMPHASIS_9_5:
1967 preemph_reg_value = 0x0006000;
1968 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1969 case DP_TRAIN_VOLTAGE_SWING_400:
1970 demph_reg_value = 0x1B405555;
1971 uniqtranscale_reg_value = 0x55ADDA3A;
1972 break;
1973 default:
1974 return 0;
1975 }
1976 break;
1977 default:
1978 return 0;
1979 }
1980
1981 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1982 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1983 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
1984 uniqtranscale_reg_value);
1985 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1986 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1987 vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1988 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
1989
1990 return 0;
1991}
1992
1993static void
1994intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1995{
1996 uint8_t v = 0;
1997 uint8_t p = 0;
1998 int lane;
1999 uint8_t voltage_max;
2000 uint8_t preemph_max;
2001
2002 for (lane = 0; lane < intel_dp->lane_count; lane++) {
2003 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2004 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2005
2006 if (this_v > v)
2007 v = this_v;
2008 if (this_p > p)
2009 p = this_p;
2010 }
2011
2012 voltage_max = intel_dp_voltage_max(intel_dp);
2013 if (v >= voltage_max)
2014 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2015
2016 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2017 if (p >= preemph_max)
2018 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2019
2020 for (lane = 0; lane < 4; lane++)
2021 intel_dp->train_set[lane] = v | p;
2022}
2023
2024static uint32_t
2025intel_gen4_signal_levels(uint8_t train_set)
2026{
2027 uint32_t signal_levels = 0;
2028
2029 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2030 case DP_TRAIN_VOLTAGE_SWING_400:
2031 default:
2032 signal_levels |= DP_VOLTAGE_0_4;
2033 break;
2034 case DP_TRAIN_VOLTAGE_SWING_600:
2035 signal_levels |= DP_VOLTAGE_0_6;
2036 break;
2037 case DP_TRAIN_VOLTAGE_SWING_800:
2038 signal_levels |= DP_VOLTAGE_0_8;
2039 break;
2040 case DP_TRAIN_VOLTAGE_SWING_1200:
2041 signal_levels |= DP_VOLTAGE_1_2;
2042 break;
2043 }
2044 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2045 case DP_TRAIN_PRE_EMPHASIS_0:
2046 default:
2047 signal_levels |= DP_PRE_EMPHASIS_0;
2048 break;
2049 case DP_TRAIN_PRE_EMPHASIS_3_5:
2050 signal_levels |= DP_PRE_EMPHASIS_3_5;
2051 break;
2052 case DP_TRAIN_PRE_EMPHASIS_6:
2053 signal_levels |= DP_PRE_EMPHASIS_6;
2054 break;
2055 case DP_TRAIN_PRE_EMPHASIS_9_5:
2056 signal_levels |= DP_PRE_EMPHASIS_9_5;
2057 break;
2058 }
2059 return signal_levels;
2060}
2061
2062/* Gen6's DP voltage swing and pre-emphasis control */
2063static uint32_t
2064intel_gen6_edp_signal_levels(uint8_t train_set)
2065{
2066 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2067 DP_TRAIN_PRE_EMPHASIS_MASK);
2068 switch (signal_levels) {
2069 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2070 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2071 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2072 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2073 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2074 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2075 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2076 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2077 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2078 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2079 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2080 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2081 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2082 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2083 default:
2084 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2085 "0x%x\n", signal_levels);
2086 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2087 }
2088}
2089
2090/* Gen7's DP voltage swing and pre-emphasis control */
2091static uint32_t
2092intel_gen7_edp_signal_levels(uint8_t train_set)
2093{
2094 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2095 DP_TRAIN_PRE_EMPHASIS_MASK);
2096 switch (signal_levels) {
2097 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2098 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2099 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2100 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2101 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2102 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2103
2104 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2105 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2106 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2107 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2108
2109 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2110 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2111 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2112 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2113
2114 default:
2115 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2116 "0x%x\n", signal_levels);
2117 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2118 }
2119}
2120
2121/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2122static uint32_t
2123intel_hsw_signal_levels(uint8_t train_set)
2124{
2125 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2126 DP_TRAIN_PRE_EMPHASIS_MASK);
2127 switch (signal_levels) {
2128 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2129 return DDI_BUF_EMP_400MV_0DB_HSW;
2130 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2131 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2132 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2133 return DDI_BUF_EMP_400MV_6DB_HSW;
2134 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2135 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2136
2137 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2138 return DDI_BUF_EMP_600MV_0DB_HSW;
2139 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2140 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2141 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2142 return DDI_BUF_EMP_600MV_6DB_HSW;
2143
2144 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2145 return DDI_BUF_EMP_800MV_0DB_HSW;
2146 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2147 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2148 default:
2149 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2150 "0x%x\n", signal_levels);
2151 return DDI_BUF_EMP_400MV_0DB_HSW;
2152 }
2153}
2154
2155/* Properly updates "DP" with the correct signal levels. */
2156static void
2157intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2158{
2159 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2160 enum port port = intel_dig_port->port;
2161 struct drm_device *dev = intel_dig_port->base.base.dev;
2162 uint32_t signal_levels, mask;
2163 uint8_t train_set = intel_dp->train_set[0];
2164
2165 if (HAS_DDI(dev)) {
2166 signal_levels = intel_hsw_signal_levels(train_set);
2167 mask = DDI_BUF_EMP_MASK;
2168 } else if (IS_VALLEYVIEW(dev)) {
2169 signal_levels = intel_vlv_signal_levels(intel_dp);
2170 mask = 0;
2171 } else if (IS_GEN7(dev) && port == PORT_A) {
2172 signal_levels = intel_gen7_edp_signal_levels(train_set);
2173 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2174 } else if (IS_GEN6(dev) && port == PORT_A) {
2175 signal_levels = intel_gen6_edp_signal_levels(train_set);
2176 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2177 } else {
2178 signal_levels = intel_gen4_signal_levels(train_set);
2179 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2180 }
2181
2182 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2183
2184 *DP = (*DP & ~mask) | signal_levels;
2185}
2186
2187static bool
2188intel_dp_set_link_train(struct intel_dp *intel_dp,
2189 uint32_t dp_reg_value,
2190 uint8_t dp_train_pat)
2191{
2192 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2193 struct drm_device *dev = intel_dig_port->base.base.dev;
2194 struct drm_i915_private *dev_priv = dev->dev_private;
2195 enum port port = intel_dig_port->port;
2196 int ret;
2197
2198 if (HAS_DDI(dev)) {
2199 uint32_t temp = I915_READ(DP_TP_CTL(port));
2200
2201 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2202 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2203 else
2204 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2205
2206 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2207 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2208 case DP_TRAINING_PATTERN_DISABLE:
2209 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2210
2211 break;
2212 case DP_TRAINING_PATTERN_1:
2213 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2214 break;
2215 case DP_TRAINING_PATTERN_2:
2216 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2217 break;
2218 case DP_TRAINING_PATTERN_3:
2219 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2220 break;
2221 }
2222 I915_WRITE(DP_TP_CTL(port), temp);
2223
2224 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2225 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
2226
2227 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2228 case DP_TRAINING_PATTERN_DISABLE:
2229 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
2230 break;
2231 case DP_TRAINING_PATTERN_1:
2232 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
2233 break;
2234 case DP_TRAINING_PATTERN_2:
2235 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2236 break;
2237 case DP_TRAINING_PATTERN_3:
2238 DRM_ERROR("DP training pattern 3 not supported\n");
2239 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2240 break;
2241 }
2242
2243 } else {
2244 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
2245
2246 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2247 case DP_TRAINING_PATTERN_DISABLE:
2248 dp_reg_value |= DP_LINK_TRAIN_OFF;
2249 break;
2250 case DP_TRAINING_PATTERN_1:
2251 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
2252 break;
2253 case DP_TRAINING_PATTERN_2:
2254 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2255 break;
2256 case DP_TRAINING_PATTERN_3:
2257 DRM_ERROR("DP training pattern 3 not supported\n");
2258 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2259 break;
2260 }
2261 }
2262
2263 I915_WRITE(intel_dp->output_reg, dp_reg_value);
2264 POSTING_READ(intel_dp->output_reg);
2265
2266 intel_dp_aux_native_write_1(intel_dp,
2267 DP_TRAINING_PATTERN_SET,
2268 dp_train_pat);
2269
2270 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
2271 DP_TRAINING_PATTERN_DISABLE) {
2272 ret = intel_dp_aux_native_write(intel_dp,
2273 DP_TRAINING_LANE0_SET,
2274 intel_dp->train_set,
2275 intel_dp->lane_count);
2276 if (ret != intel_dp->lane_count)
2277 return false;
2278 }
2279
2280 return true;
2281}
2282
2283static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2284{
2285 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2286 struct drm_device *dev = intel_dig_port->base.base.dev;
2287 struct drm_i915_private *dev_priv = dev->dev_private;
2288 enum port port = intel_dig_port->port;
2289 uint32_t val;
2290
2291 if (!HAS_DDI(dev))
2292 return;
2293
2294 val = I915_READ(DP_TP_CTL(port));
2295 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2296 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2297 I915_WRITE(DP_TP_CTL(port), val);
2298
2299 /*
2300 * On PORT_A we can have only eDP in SST mode. There the only reason
2301 * we need to set idle transmission mode is to work around a HW issue
2302 * where we enable the pipe while not in idle link-training mode.
2303 * In this case there is requirement to wait for a minimum number of
2304 * idle patterns to be sent.
2305 */
2306 if (port == PORT_A)
2307 return;
2308
2309 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2310 1))
2311 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2312}
2313
2314/* Enable corresponding port and start training pattern 1 */
2315void
2316intel_dp_start_link_train(struct intel_dp *intel_dp)
2317{
2318 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2319 struct drm_device *dev = encoder->dev;
2320 int i;
2321 uint8_t voltage;
2322 bool clock_recovery = false;
2323 int voltage_tries, loop_tries;
2324 uint32_t DP = intel_dp->DP;
2325
2326 if (HAS_DDI(dev))
2327 intel_ddi_prepare_link_retrain(encoder);
2328
2329 /* Write the link configuration data */
2330 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2331 intel_dp->link_configuration,
2332 DP_LINK_CONFIGURATION_SIZE);
2333
2334 DP |= DP_PORT_EN;
2335
2336 memset(intel_dp->train_set, 0, 4);
2337 voltage = 0xff;
2338 voltage_tries = 0;
2339 loop_tries = 0;
2340 clock_recovery = false;
2341 for (;;) {
2342 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2343 uint8_t link_status[DP_LINK_STATUS_SIZE];
2344
2345 intel_dp_set_signal_levels(intel_dp, &DP);
2346
2347 /* Set training pattern 1 */
2348 if (!intel_dp_set_link_train(intel_dp, DP,
2349 DP_TRAINING_PATTERN_1 |
2350 DP_LINK_SCRAMBLING_DISABLE))
2351 break;
2352
2353 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2354 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2355 DRM_ERROR("failed to get link status\n");
2356 break;
2357 }
2358
2359 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2360 DRM_DEBUG_KMS("clock recovery OK\n");
2361 clock_recovery = true;
2362 break;
2363 }
2364
2365 /* Check to see if we've tried the max voltage */
2366 for (i = 0; i < intel_dp->lane_count; i++)
2367 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2368 break;
2369 if (i == intel_dp->lane_count) {
2370 ++loop_tries;
2371 if (loop_tries == 5) {
2372 DRM_DEBUG_KMS("too many full retries, give up\n");
2373 break;
2374 }
2375 memset(intel_dp->train_set, 0, 4);
2376 voltage_tries = 0;
2377 continue;
2378 }
2379
2380 /* Check to see if we've tried the same voltage 5 times */
2381 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2382 ++voltage_tries;
2383 if (voltage_tries == 5) {
2384 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2385 break;
2386 }
2387 } else
2388 voltage_tries = 0;
2389 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2390
2391 /* Compute new intel_dp->train_set as requested by target */
2392 intel_get_adjust_train(intel_dp, link_status);
2393 }
2394
2395 intel_dp->DP = DP;
2396}
2397
2398void
2399intel_dp_complete_link_train(struct intel_dp *intel_dp)
2400{
2401 bool channel_eq = false;
2402 int tries, cr_tries;
2403 uint32_t DP = intel_dp->DP;
2404
2405 /* channel equalization */
2406 tries = 0;
2407 cr_tries = 0;
2408 channel_eq = false;
2409 for (;;) {
2410 uint8_t link_status[DP_LINK_STATUS_SIZE];
2411
2412 if (cr_tries > 5) {
2413 DRM_ERROR("failed to train DP, aborting\n");
2414 intel_dp_link_down(intel_dp);
2415 break;
2416 }
2417
2418 intel_dp_set_signal_levels(intel_dp, &DP);
2419
2420 /* channel eq pattern */
2421 if (!intel_dp_set_link_train(intel_dp, DP,
2422 DP_TRAINING_PATTERN_2 |
2423 DP_LINK_SCRAMBLING_DISABLE))
2424 break;
2425
2426 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2427 if (!intel_dp_get_link_status(intel_dp, link_status))
2428 break;
2429
2430 /* Make sure clock is still ok */
2431 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2432 intel_dp_start_link_train(intel_dp);
2433 cr_tries++;
2434 continue;
2435 }
2436
2437 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2438 channel_eq = true;
2439 break;
2440 }
2441
2442 /* Try 5 times, then try clock recovery if that fails */
2443 if (tries > 5) {
2444 intel_dp_link_down(intel_dp);
2445 intel_dp_start_link_train(intel_dp);
2446 tries = 0;
2447 cr_tries++;
2448 continue;
2449 }
2450
2451 /* Compute new intel_dp->train_set as requested by target */
2452 intel_get_adjust_train(intel_dp, link_status);
2453 ++tries;
2454 }
2455
2456 intel_dp_set_idle_link_train(intel_dp);
2457
2458 intel_dp->DP = DP;
2459
2460 if (channel_eq)
2461 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2462
2463}
2464
2465void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2466{
2467 intel_dp_set_link_train(intel_dp, intel_dp->DP,
2468 DP_TRAINING_PATTERN_DISABLE);
2469}
2470
2471static void
2472intel_dp_link_down(struct intel_dp *intel_dp)
2473{
2474 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2475 enum port port = intel_dig_port->port;
2476 struct drm_device *dev = intel_dig_port->base.base.dev;
2477 struct drm_i915_private *dev_priv = dev->dev_private;
2478 struct intel_crtc *intel_crtc =
2479 to_intel_crtc(intel_dig_port->base.base.crtc);
2480 uint32_t DP = intel_dp->DP;
2481
2482 /*
2483 * DDI code has a strict mode set sequence and we should try to respect
2484 * it, otherwise we might hang the machine in many different ways. So we
2485 * really should be disabling the port only on a complete crtc_disable
2486 * sequence. This function is just called under two conditions on DDI
2487 * code:
2488 * - Link train failed while doing crtc_enable, and on this case we
2489 * really should respect the mode set sequence and wait for a
2490 * crtc_disable.
2491 * - Someone turned the monitor off and intel_dp_check_link_status
2492 * called us. We don't need to disable the whole port on this case, so
2493 * when someone turns the monitor on again,
2494 * intel_ddi_prepare_link_retrain will take care of redoing the link
2495 * train.
2496 */
2497 if (HAS_DDI(dev))
2498 return;
2499
2500 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2501 return;
2502
2503 DRM_DEBUG_KMS("\n");
2504
2505 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2506 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2507 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2508 } else {
2509 DP &= ~DP_LINK_TRAIN_MASK;
2510 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2511 }
2512 POSTING_READ(intel_dp->output_reg);
2513
2514 /* We don't really know why we're doing this */
2515 intel_wait_for_vblank(dev, intel_crtc->pipe);
2516
2517 if (HAS_PCH_IBX(dev) &&
2518 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2519 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2520
2521 /* Hardware workaround: leaving our transcoder select
2522 * set to transcoder B while it's off will prevent the
2523 * corresponding HDMI output on transcoder A.
2524 *
2525 * Combine this with another hardware workaround:
2526 * transcoder select bit can only be cleared while the
2527 * port is enabled.
2528 */
2529 DP &= ~DP_PIPEB_SELECT;
2530 I915_WRITE(intel_dp->output_reg, DP);
2531
2532 /* Changes to enable or select take place the vblank
2533 * after being written.
2534 */
2535 if (WARN_ON(crtc == NULL)) {
2536 /* We should never try to disable a port without a crtc
2537 * attached. For paranoia keep the code around for a
2538 * bit. */
2539 POSTING_READ(intel_dp->output_reg);
2540 msleep(50);
2541 } else
2542 intel_wait_for_vblank(dev, intel_crtc->pipe);
2543 }
2544
2545 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2546 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2547 POSTING_READ(intel_dp->output_reg);
2548 msleep(intel_dp->panel_power_down_delay);
2549}
2550
2551static bool
2552intel_dp_get_dpcd(struct intel_dp *intel_dp)
2553{
2554 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2555
2556 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2557 sizeof(intel_dp->dpcd)) == 0)
2558 return false; /* aux transfer failed */
2559
2560 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2561 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2562 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2563
2564 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2565 return false; /* DPCD not present */
2566
2567 /* Check if the panel supports PSR */
2568 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2569 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2570 intel_dp->psr_dpcd,
2571 sizeof(intel_dp->psr_dpcd));
2572 if (is_edp_psr(intel_dp))
2573 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2574 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2575 DP_DWN_STRM_PORT_PRESENT))
2576 return true; /* native DP sink */
2577
2578 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2579 return true; /* no per-port downstream info */
2580
2581 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2582 intel_dp->downstream_ports,
2583 DP_MAX_DOWNSTREAM_PORTS) == 0)
2584 return false; /* downstream port status fetch failed */
2585
2586 return true;
2587}
2588
2589static void
2590intel_dp_probe_oui(struct intel_dp *intel_dp)
2591{
2592 u8 buf[3];
2593
2594 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2595 return;
2596
2597 ironlake_edp_panel_vdd_on(intel_dp);
2598
2599 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2600 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2601 buf[0], buf[1], buf[2]);
2602
2603 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2604 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2605 buf[0], buf[1], buf[2]);
2606
2607 ironlake_edp_panel_vdd_off(intel_dp, false);
2608}
2609
2610static bool
2611intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2612{
2613 int ret;
2614
2615 ret = intel_dp_aux_native_read_retry(intel_dp,
2616 DP_DEVICE_SERVICE_IRQ_VECTOR,
2617 sink_irq_vector, 1);
2618 if (!ret)
2619 return false;
2620
2621 return true;
2622}
2623
2624static void
2625intel_dp_handle_test_request(struct intel_dp *intel_dp)
2626{
2627 /* NAK by default */
2628 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2629}
2630
2631/*
2632 * According to DP spec
2633 * 5.1.2:
2634 * 1. Read DPCD
2635 * 2. Configure link according to Receiver Capabilities
2636 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2637 * 4. Check link status on receipt of hot-plug interrupt
2638 */
2639
2640void
2641intel_dp_check_link_status(struct intel_dp *intel_dp)
2642{
2643 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2644 u8 sink_irq_vector;
2645 u8 link_status[DP_LINK_STATUS_SIZE];
2646
2647 if (!intel_encoder->connectors_active)
2648 return;
2649
2650 if (WARN_ON(!intel_encoder->base.crtc))
2651 return;
2652
2653 /* Try to read receiver status if the link appears to be up */
2654 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2655 intel_dp_link_down(intel_dp);
2656 return;
2657 }
2658
2659 /* Now read the DPCD to see if it's actually running */
2660 if (!intel_dp_get_dpcd(intel_dp)) {
2661 intel_dp_link_down(intel_dp);
2662 return;
2663 }
2664
2665 /* Try to read the source of the interrupt */
2666 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2667 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2668 /* Clear interrupt source */
2669 intel_dp_aux_native_write_1(intel_dp,
2670 DP_DEVICE_SERVICE_IRQ_VECTOR,
2671 sink_irq_vector);
2672
2673 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2674 intel_dp_handle_test_request(intel_dp);
2675 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2676 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2677 }
2678
2679 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2680 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2681 drm_get_encoder_name(&intel_encoder->base));
2682 intel_dp_start_link_train(intel_dp);
2683 intel_dp_complete_link_train(intel_dp);
2684 intel_dp_stop_link_train(intel_dp);
2685 }
2686}
2687
2688/* XXX this is probably wrong for multiple downstream ports */
2689static enum drm_connector_status
2690intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2691{
2692 uint8_t *dpcd = intel_dp->dpcd;
2693 bool hpd;
2694 uint8_t type;
2695
2696 if (!intel_dp_get_dpcd(intel_dp))
2697 return connector_status_disconnected;
2698
2699 /* if there's no downstream port, we're done */
2700 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2701 return connector_status_connected;
2702
2703 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2704 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2705 if (hpd) {
2706 uint8_t reg;
2707 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2708 &reg, 1))
2709 return connector_status_unknown;
2710 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2711 : connector_status_disconnected;
2712 }
2713
2714 /* If no HPD, poke DDC gently */
2715 if (drm_probe_ddc(&intel_dp->adapter))
2716 return connector_status_connected;
2717
2718 /* Well we tried, say unknown for unreliable port types */
2719 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2720 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2721 return connector_status_unknown;
2722
2723 /* Anything else is out of spec, warn and ignore */
2724 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2725 return connector_status_disconnected;
2726}
2727
2728static enum drm_connector_status
2729ironlake_dp_detect(struct intel_dp *intel_dp)
2730{
2731 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2732 struct drm_i915_private *dev_priv = dev->dev_private;
2733 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2734 enum drm_connector_status status;
2735
2736 /* Can't disconnect eDP, but you can close the lid... */
2737 if (is_edp(intel_dp)) {
2738 status = intel_panel_detect(dev);
2739 if (status == connector_status_unknown)
2740 status = connector_status_connected;
2741 return status;
2742 }
2743
2744 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2745 return connector_status_disconnected;
2746
2747 return intel_dp_detect_dpcd(intel_dp);
2748}
2749
2750static enum drm_connector_status
2751g4x_dp_detect(struct intel_dp *intel_dp)
2752{
2753 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2754 struct drm_i915_private *dev_priv = dev->dev_private;
2755 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2756 uint32_t bit;
2757
2758 /* Can't disconnect eDP, but you can close the lid... */
2759 if (is_edp(intel_dp)) {
2760 enum drm_connector_status status;
2761
2762 status = intel_panel_detect(dev);
2763 if (status == connector_status_unknown)
2764 status = connector_status_connected;
2765 return status;
2766 }
2767
2768 switch (intel_dig_port->port) {
2769 case PORT_B:
2770 bit = PORTB_HOTPLUG_LIVE_STATUS;
2771 break;
2772 case PORT_C:
2773 bit = PORTC_HOTPLUG_LIVE_STATUS;
2774 break;
2775 case PORT_D:
2776 bit = PORTD_HOTPLUG_LIVE_STATUS;
2777 break;
2778 default:
2779 return connector_status_unknown;
2780 }
2781
2782 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2783 return connector_status_disconnected;
2784
2785 return intel_dp_detect_dpcd(intel_dp);
2786}
2787
2788static struct edid *
2789intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2790{
2791 struct intel_connector *intel_connector = to_intel_connector(connector);
2792
2793 /* use cached edid if we have one */
2794 if (intel_connector->edid) {
2795 struct edid *edid;
2796 int size;
2797
2798 /* invalid edid */
2799 if (IS_ERR(intel_connector->edid))
2800 return NULL;
2801
2802 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2803 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
2804 if (!edid)
2805 return NULL;
2806
2807 return edid;
2808 }
2809
2810 return drm_get_edid(connector, adapter);
2811}
2812
2813static int
2814intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2815{
2816 struct intel_connector *intel_connector = to_intel_connector(connector);
2817
2818 /* use cached edid if we have one */
2819 if (intel_connector->edid) {
2820 /* invalid edid */
2821 if (IS_ERR(intel_connector->edid))
2822 return 0;
2823
2824 return intel_connector_update_modes(connector,
2825 intel_connector->edid);
2826 }
2827
2828 return intel_ddc_get_modes(connector, adapter);
2829}
2830
2831static enum drm_connector_status
2832intel_dp_detect(struct drm_connector *connector, bool force)
2833{
2834 struct intel_dp *intel_dp = intel_attached_dp(connector);
2835 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2836 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2837 struct drm_device *dev = connector->dev;
2838 enum drm_connector_status status;
2839 struct edid *edid = NULL;
2840
2841 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2842 connector->base.id, drm_get_connector_name(connector));
2843
2844 intel_dp->has_audio = false;
2845
2846 if (HAS_PCH_SPLIT(dev))
2847 status = ironlake_dp_detect(intel_dp);
2848 else
2849 status = g4x_dp_detect(intel_dp);
2850
2851 if (status != connector_status_connected)
2852 return status;
2853
2854 intel_dp_probe_oui(intel_dp);
2855
2856 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2857 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2858 } else {
2859 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2860 if (edid) {
2861 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2862 kfree(edid);
2863 }
2864 }
2865
2866 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2867 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2868 return connector_status_connected;
2869}
2870
2871static int intel_dp_get_modes(struct drm_connector *connector)
2872{
2873 struct intel_dp *intel_dp = intel_attached_dp(connector);
2874 struct intel_connector *intel_connector = to_intel_connector(connector);
2875 struct drm_device *dev = connector->dev;
2876 int ret;
2877
2878 /* We should parse the EDID data and find out if it has an audio sink
2879 */
2880
2881 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2882 if (ret)
2883 return ret;
2884
2885 /* if eDP has no EDID, fall back to fixed mode */
2886 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2887 struct drm_display_mode *mode;
2888 mode = drm_mode_duplicate(dev,
2889 intel_connector->panel.fixed_mode);
2890 if (mode) {
2891 drm_mode_probed_add(connector, mode);
2892 return 1;
2893 }
2894 }
2895 return 0;
2896}
2897
2898static bool
2899intel_dp_detect_audio(struct drm_connector *connector)
2900{
2901 struct intel_dp *intel_dp = intel_attached_dp(connector);
2902 struct edid *edid;
2903 bool has_audio = false;
2904
2905 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2906 if (edid) {
2907 has_audio = drm_detect_monitor_audio(edid);
2908 kfree(edid);
2909 }
2910
2911 return has_audio;
2912}
2913
2914static int
2915intel_dp_set_property(struct drm_connector *connector,
2916 struct drm_property *property,
2917 uint64_t val)
2918{
2919 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2920 struct intel_connector *intel_connector = to_intel_connector(connector);
2921 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2922 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2923 int ret;
2924
2925 ret = drm_object_property_set_value(&connector->base, property, val);
2926 if (ret)
2927 return ret;
2928
2929 if (property == dev_priv->force_audio_property) {
2930 int i = val;
2931 bool has_audio;
2932
2933 if (i == intel_dp->force_audio)
2934 return 0;
2935
2936 intel_dp->force_audio = i;
2937
2938 if (i == HDMI_AUDIO_AUTO)
2939 has_audio = intel_dp_detect_audio(connector);
2940 else
2941 has_audio = (i == HDMI_AUDIO_ON);
2942
2943 if (has_audio == intel_dp->has_audio)
2944 return 0;
2945
2946 intel_dp->has_audio = has_audio;
2947 goto done;
2948 }
2949
2950 if (property == dev_priv->broadcast_rgb_property) {
2951 bool old_auto = intel_dp->color_range_auto;
2952 uint32_t old_range = intel_dp->color_range;
2953
2954 switch (val) {
2955 case INTEL_BROADCAST_RGB_AUTO:
2956 intel_dp->color_range_auto = true;
2957 break;
2958 case INTEL_BROADCAST_RGB_FULL:
2959 intel_dp->color_range_auto = false;
2960 intel_dp->color_range = 0;
2961 break;
2962 case INTEL_BROADCAST_RGB_LIMITED:
2963 intel_dp->color_range_auto = false;
2964 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2965 break;
2966 default:
2967 return -EINVAL;
2968 }
2969
2970 if (old_auto == intel_dp->color_range_auto &&
2971 old_range == intel_dp->color_range)
2972 return 0;
2973
2974 goto done;
2975 }
2976
2977 if (is_edp(intel_dp) &&
2978 property == connector->dev->mode_config.scaling_mode_property) {
2979 if (val == DRM_MODE_SCALE_NONE) {
2980 DRM_DEBUG_KMS("no scaling not supported\n");
2981 return -EINVAL;
2982 }
2983
2984 if (intel_connector->panel.fitting_mode == val) {
2985 /* the eDP scaling property is not changed */
2986 return 0;
2987 }
2988 intel_connector->panel.fitting_mode = val;
2989
2990 goto done;
2991 }
2992
2993 return -EINVAL;
2994
2995done:
2996 if (intel_encoder->base.crtc)
2997 intel_crtc_restore_mode(intel_encoder->base.crtc);
2998
2999 return 0;
3000}
3001
3002static void
3003intel_dp_connector_destroy(struct drm_connector *connector)
3004{
3005 struct intel_connector *intel_connector = to_intel_connector(connector);
3006
3007 if (!IS_ERR_OR_NULL(intel_connector->edid))
3008 kfree(intel_connector->edid);
3009
3010 /* Can't call is_edp() since the encoder may have been destroyed
3011 * already. */
3012 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3013 intel_panel_fini(&intel_connector->panel);
3014
3015 drm_sysfs_connector_remove(connector);
3016 drm_connector_cleanup(connector);
3017 kfree(connector);
3018}
3019
3020void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3021{
3022 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3023 struct intel_dp *intel_dp = &intel_dig_port->dp;
3024 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3025
3026 i2c_del_adapter(&intel_dp->adapter);
3027 drm_encoder_cleanup(encoder);
3028 if (is_edp(intel_dp)) {
3029 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3030 mutex_lock(&dev->mode_config.mutex);
3031 ironlake_panel_vdd_off_sync(intel_dp);
3032 mutex_unlock(&dev->mode_config.mutex);
3033 }
3034 kfree(intel_dig_port);
3035}
3036
3037static const struct drm_connector_funcs intel_dp_connector_funcs = {
3038 .dpms = intel_connector_dpms,
3039 .detect = intel_dp_detect,
3040 .fill_modes = drm_helper_probe_single_connector_modes,
3041 .set_property = intel_dp_set_property,
3042 .destroy = intel_dp_connector_destroy,
3043};
3044
3045static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3046 .get_modes = intel_dp_get_modes,
3047 .mode_valid = intel_dp_mode_valid,
3048 .best_encoder = intel_best_encoder,
3049};
3050
3051static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3052 .destroy = intel_dp_encoder_destroy,
3053};
3054
3055static void
3056intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3057{
3058 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3059
3060 intel_dp_check_link_status(intel_dp);
3061}
3062
3063/* Return which DP Port should be selected for Transcoder DP control */
3064int
3065intel_trans_dp_port_sel(struct drm_crtc *crtc)
3066{
3067 struct drm_device *dev = crtc->dev;
3068 struct intel_encoder *intel_encoder;
3069 struct intel_dp *intel_dp;
3070
3071 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3072 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3073
3074 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3075 intel_encoder->type == INTEL_OUTPUT_EDP)
3076 return intel_dp->output_reg;
3077 }
3078
3079 return -1;
3080}
3081
3082/* check the VBT to see whether the eDP is on DP-D port */
3083bool intel_dpd_is_edp(struct drm_device *dev)
3084{
3085 struct drm_i915_private *dev_priv = dev->dev_private;
3086 struct child_device_config *p_child;
3087 int i;
3088
3089 if (!dev_priv->vbt.child_dev_num)
3090 return false;
3091
3092 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3093 p_child = dev_priv->vbt.child_dev + i;
3094
3095 if (p_child->dvo_port == PORT_IDPD &&
3096 p_child->device_type == DEVICE_TYPE_eDP)
3097 return true;
3098 }
3099 return false;
3100}
3101
3102static void
3103intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3104{
3105 struct intel_connector *intel_connector = to_intel_connector(connector);
3106
3107 intel_attach_force_audio_property(connector);
3108 intel_attach_broadcast_rgb_property(connector);
3109 intel_dp->color_range_auto = true;
3110
3111 if (is_edp(intel_dp)) {
3112 drm_mode_create_scaling_mode_property(connector->dev);
3113 drm_object_attach_property(
3114 &connector->base,
3115 connector->dev->mode_config.scaling_mode_property,
3116 DRM_MODE_SCALE_ASPECT);
3117 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3118 }
3119}
3120
3121static void
3122intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3123 struct intel_dp *intel_dp,
3124 struct edp_power_seq *out)
3125{
3126 struct drm_i915_private *dev_priv = dev->dev_private;
3127 struct edp_power_seq cur, vbt, spec, final;
3128 u32 pp_on, pp_off, pp_div, pp;
3129 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3130
3131 if (HAS_PCH_SPLIT(dev)) {
3132 pp_control_reg = PCH_PP_CONTROL;
3133 pp_on_reg = PCH_PP_ON_DELAYS;
3134 pp_off_reg = PCH_PP_OFF_DELAYS;
3135 pp_div_reg = PCH_PP_DIVISOR;
3136 } else {
3137 pp_control_reg = PIPEA_PP_CONTROL;
3138 pp_on_reg = PIPEA_PP_ON_DELAYS;
3139 pp_off_reg = PIPEA_PP_OFF_DELAYS;
3140 pp_div_reg = PIPEA_PP_DIVISOR;
3141 }
3142
3143 /* Workaround: Need to write PP_CONTROL with the unlock key as
3144 * the very first thing. */
3145 pp = ironlake_get_pp_control(intel_dp);
3146 I915_WRITE(pp_control_reg, pp);
3147
3148 pp_on = I915_READ(pp_on_reg);
3149 pp_off = I915_READ(pp_off_reg);
3150 pp_div = I915_READ(pp_div_reg);
3151
3152 /* Pull timing values out of registers */
3153 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3154 PANEL_POWER_UP_DELAY_SHIFT;
3155
3156 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3157 PANEL_LIGHT_ON_DELAY_SHIFT;
3158
3159 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3160 PANEL_LIGHT_OFF_DELAY_SHIFT;
3161
3162 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3163 PANEL_POWER_DOWN_DELAY_SHIFT;
3164
3165 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3166 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3167
3168 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3169 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3170
3171 vbt = dev_priv->vbt.edp_pps;
3172
3173 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3174 * our hw here, which are all in 100usec. */
3175 spec.t1_t3 = 210 * 10;
3176 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3177 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3178 spec.t10 = 500 * 10;
3179 /* This one is special and actually in units of 100ms, but zero
3180 * based in the hw (so we need to add 100 ms). But the sw vbt
3181 * table multiplies it with 1000 to make it in units of 100usec,
3182 * too. */
3183 spec.t11_t12 = (510 + 100) * 10;
3184
3185 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3186 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3187
3188 /* Use the max of the register settings and vbt. If both are
3189 * unset, fall back to the spec limits. */
3190#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3191 spec.field : \
3192 max(cur.field, vbt.field))
3193 assign_final(t1_t3);
3194 assign_final(t8);
3195 assign_final(t9);
3196 assign_final(t10);
3197 assign_final(t11_t12);
3198#undef assign_final
3199
3200#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3201 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3202 intel_dp->backlight_on_delay = get_delay(t8);
3203 intel_dp->backlight_off_delay = get_delay(t9);
3204 intel_dp->panel_power_down_delay = get_delay(t10);
3205 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3206#undef get_delay
3207
3208 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3209 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3210 intel_dp->panel_power_cycle_delay);
3211
3212 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3213 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3214
3215 if (out)
3216 *out = final;
3217}
3218
3219static void
3220intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3221 struct intel_dp *intel_dp,
3222 struct edp_power_seq *seq)
3223{
3224 struct drm_i915_private *dev_priv = dev->dev_private;
3225 u32 pp_on, pp_off, pp_div, port_sel = 0;
3226 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3227 int pp_on_reg, pp_off_reg, pp_div_reg;
3228
3229 if (HAS_PCH_SPLIT(dev)) {
3230 pp_on_reg = PCH_PP_ON_DELAYS;
3231 pp_off_reg = PCH_PP_OFF_DELAYS;
3232 pp_div_reg = PCH_PP_DIVISOR;
3233 } else {
3234 pp_on_reg = PIPEA_PP_ON_DELAYS;
3235 pp_off_reg = PIPEA_PP_OFF_DELAYS;
3236 pp_div_reg = PIPEA_PP_DIVISOR;
3237 }
3238
3239 /* And finally store the new values in the power sequencer. */
3240 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3241 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3242 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3243 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3244 /* Compute the divisor for the pp clock, simply match the Bspec
3245 * formula. */
3246 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3247 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3248 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3249
3250 /* Haswell doesn't have any port selection bits for the panel
3251 * power sequencer any more. */
3252 if (IS_VALLEYVIEW(dev)) {
3253 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
3254 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3255 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3256 port_sel = PANEL_POWER_PORT_DP_A;
3257 else
3258 port_sel = PANEL_POWER_PORT_DP_D;
3259 }
3260
3261 pp_on |= port_sel;
3262
3263 I915_WRITE(pp_on_reg, pp_on);
3264 I915_WRITE(pp_off_reg, pp_off);
3265 I915_WRITE(pp_div_reg, pp_div);
3266
3267 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3268 I915_READ(pp_on_reg),
3269 I915_READ(pp_off_reg),
3270 I915_READ(pp_div_reg));
3271}
3272
3273static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3274 struct intel_connector *intel_connector)
3275{
3276 struct drm_connector *connector = &intel_connector->base;
3277 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3278 struct drm_device *dev = intel_dig_port->base.base.dev;
3279 struct drm_i915_private *dev_priv = dev->dev_private;
3280 struct drm_display_mode *fixed_mode = NULL;
3281 struct edp_power_seq power_seq = { 0 };
3282 bool has_dpcd;
3283 struct drm_display_mode *scan;
3284 struct edid *edid;
3285
3286 if (!is_edp(intel_dp))
3287 return true;
3288
3289 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3290
3291 /* Cache DPCD and EDID for edp. */
3292 ironlake_edp_panel_vdd_on(intel_dp);
3293 has_dpcd = intel_dp_get_dpcd(intel_dp);
3294 ironlake_edp_panel_vdd_off(intel_dp, false);
3295
3296 if (has_dpcd) {
3297 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3298 dev_priv->no_aux_handshake =
3299 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3300 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3301 } else {
3302 /* if this fails, presume the device is a ghost */
3303 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3304 return false;
3305 }
3306
3307 /* We now know it's not a ghost, init power sequence regs. */
3308 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3309 &power_seq);
3310
3311 ironlake_edp_panel_vdd_on(intel_dp);
3312 edid = drm_get_edid(connector, &intel_dp->adapter);
3313 if (edid) {
3314 if (drm_add_edid_modes(connector, edid)) {
3315 drm_mode_connector_update_edid_property(connector,
3316 edid);
3317 drm_edid_to_eld(connector, edid);
3318 } else {
3319 kfree(edid);
3320 edid = ERR_PTR(-EINVAL);
3321 }
3322 } else {
3323 edid = ERR_PTR(-ENOENT);
3324 }
3325 intel_connector->edid = edid;
3326
3327 /* prefer fixed mode from EDID if available */
3328 list_for_each_entry(scan, &connector->probed_modes, head) {
3329 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3330 fixed_mode = drm_mode_duplicate(dev, scan);
3331 break;
3332 }
3333 }
3334
3335 /* fallback to VBT if available for eDP */
3336 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3337 fixed_mode = drm_mode_duplicate(dev,
3338 dev_priv->vbt.lfp_lvds_vbt_mode);
3339 if (fixed_mode)
3340 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3341 }
3342
3343 ironlake_edp_panel_vdd_off(intel_dp, false);
3344
3345 intel_panel_init(&intel_connector->panel, fixed_mode);
3346 intel_panel_setup_backlight(connector);
3347
3348 return true;
3349}
3350
3351bool
3352intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3353 struct intel_connector *intel_connector)
3354{
3355 struct drm_connector *connector = &intel_connector->base;
3356 struct intel_dp *intel_dp = &intel_dig_port->dp;
3357 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3358 struct drm_device *dev = intel_encoder->base.dev;
3359 struct drm_i915_private *dev_priv = dev->dev_private;
3360 enum port port = intel_dig_port->port;
3361 const char *name = NULL;
3362 int type, error;
3363
3364 /* Preserve the current hw state. */
3365 intel_dp->DP = I915_READ(intel_dp->output_reg);
3366 intel_dp->attached_connector = intel_connector;
3367
3368 type = DRM_MODE_CONNECTOR_DisplayPort;
3369 /*
3370 * FIXME : We need to initialize built-in panels before external panels.
3371 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3372 */
3373 switch (port) {
3374 case PORT_A:
3375 type = DRM_MODE_CONNECTOR_eDP;
3376 break;
3377 case PORT_C:
3378 if (IS_VALLEYVIEW(dev))
3379 type = DRM_MODE_CONNECTOR_eDP;
3380 break;
3381 case PORT_D:
3382 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3383 type = DRM_MODE_CONNECTOR_eDP;
3384 break;
3385 default: /* silence GCC warning */
3386 break;
3387 }
3388
3389 /*
3390 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3391 * for DP the encoder type can be set by the caller to
3392 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3393 */
3394 if (type == DRM_MODE_CONNECTOR_eDP)
3395 intel_encoder->type = INTEL_OUTPUT_EDP;
3396
3397 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3398 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3399 port_name(port));
3400
3401 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3402 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3403
3404 connector->interlace_allowed = true;
3405 connector->doublescan_allowed = 0;
3406
3407 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3408 ironlake_panel_vdd_work);
3409
3410 intel_connector_attach_encoder(intel_connector, intel_encoder);
3411 drm_sysfs_connector_add(connector);
3412
3413 if (HAS_DDI(dev))
3414 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3415 else
3416 intel_connector->get_hw_state = intel_connector_get_hw_state;
3417
3418 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3419 if (HAS_DDI(dev)) {
3420 switch (intel_dig_port->port) {
3421 case PORT_A:
3422 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3423 break;
3424 case PORT_B:
3425 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3426 break;
3427 case PORT_C:
3428 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3429 break;
3430 case PORT_D:
3431 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3432 break;
3433 default:
3434 BUG();
3435 }
3436 }
3437
3438 /* Set up the DDC bus. */
3439 switch (port) {
3440 case PORT_A:
3441 intel_encoder->hpd_pin = HPD_PORT_A;
3442 name = "DPDDC-A";
3443 break;
3444 case PORT_B:
3445 intel_encoder->hpd_pin = HPD_PORT_B;
3446 name = "DPDDC-B";
3447 break;
3448 case PORT_C:
3449 intel_encoder->hpd_pin = HPD_PORT_C;
3450 name = "DPDDC-C";
3451 break;
3452 case PORT_D:
3453 intel_encoder->hpd_pin = HPD_PORT_D;
3454 name = "DPDDC-D";
3455 break;
3456 default:
3457 BUG();
3458 }
3459
3460 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3461 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3462 error, port_name(port));
3463
3464 intel_dp->psr_setup_done = false;
3465
3466 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
3467 i2c_del_adapter(&intel_dp->adapter);
3468 if (is_edp(intel_dp)) {
3469 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3470 mutex_lock(&dev->mode_config.mutex);
3471 ironlake_panel_vdd_off_sync(intel_dp);
3472 mutex_unlock(&dev->mode_config.mutex);
3473 }
3474 drm_sysfs_connector_remove(connector);
3475 drm_connector_cleanup(connector);
3476 return false;
3477 }
3478
3479 intel_dp_add_properties(intel_dp, connector);
3480
3481 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3482 * 0xd. Failure to do so will result in spurious interrupts being
3483 * generated on the port when a cable is not attached.
3484 */
3485 if (IS_G4X(dev) && !IS_GM45(dev)) {
3486 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3487 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3488 }
3489
3490 return true;
3491}
3492
3493void
3494intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3495{
3496 struct intel_digital_port *intel_dig_port;
3497 struct intel_encoder *intel_encoder;
3498 struct drm_encoder *encoder;
3499 struct intel_connector *intel_connector;
3500
3501 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3502 if (!intel_dig_port)
3503 return;
3504
3505 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3506 if (!intel_connector) {
3507 kfree(intel_dig_port);
3508 return;
3509 }
3510
3511 intel_encoder = &intel_dig_port->base;
3512 encoder = &intel_encoder->base;
3513
3514 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3515 DRM_MODE_ENCODER_TMDS);
3516
3517 intel_encoder->compute_config = intel_dp_compute_config;
3518 intel_encoder->mode_set = intel_dp_mode_set;
3519 intel_encoder->enable = intel_enable_dp;
3520 intel_encoder->pre_enable = intel_pre_enable_dp;
3521 intel_encoder->disable = intel_disable_dp;
3522 intel_encoder->post_disable = intel_post_disable_dp;
3523 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3524 intel_encoder->get_config = intel_dp_get_config;
3525 if (IS_VALLEYVIEW(dev))
3526 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
3527
3528 intel_dig_port->port = port;
3529 intel_dig_port->dp.output_reg = output_reg;
3530
3531 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3532 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3533 intel_encoder->cloneable = false;
3534 intel_encoder->hot_plug = intel_dp_hot_plug;
3535
3536 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3537 drm_encoder_cleanup(encoder);
3538 kfree(intel_dig_port);
3539 kfree(intel_connector);
3540 }
3541}
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