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1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
29#include <linux/slab.h>
30#include <linux/export.h>
31#include <linux/notifier.h>
32#include <linux/reboot.h>
33#include <drm/drmP.h>
34#include <drm/drm_atomic_helper.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
38#include "intel_drv.h"
39#include <drm/i915_drm.h>
40#include "i915_drv.h"
41
42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
44/* Compliance test status bits */
45#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49
50struct dp_link_dpll {
51 int clock;
52 struct dpll dpll;
53};
54
55static const struct dp_link_dpll gen4_dpll[] = {
56 { 162000,
57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
58 { 270000,
59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
60};
61
62static const struct dp_link_dpll pch_dpll[] = {
63 { 162000,
64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
65 { 270000,
66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
67};
68
69static const struct dp_link_dpll vlv_dpll[] = {
70 { 162000,
71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
72 { 270000,
73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
74};
75
76/*
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
79 */
80static const struct dp_link_dpll chv_dpll[] = {
81 /*
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
85 */
86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
88 { 270000, /* m2_int = 27, m2_fraction = 0 */
89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
90 { 540000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
92};
93
94static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
96static const int skl_rates[] = { 162000, 216000, 270000,
97 324000, 432000, 540000 };
98static const int default_rates[] = { 162000, 270000, 540000 };
99
100/**
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
103 *
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
106 */
107static bool is_edp(struct intel_dp *intel_dp)
108{
109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
110
111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
112}
113
114static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
115{
116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
117
118 return intel_dig_port->base.base.dev;
119}
120
121static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
122{
123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
124}
125
126static void intel_dp_link_down(struct intel_dp *intel_dp);
127static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
128static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
129static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
130static void vlv_steal_power_sequencer(struct drm_device *dev,
131 enum pipe pipe);
132
133static unsigned int intel_dp_unused_lane_mask(int lane_count)
134{
135 return ~((1 << lane_count) - 1) & 0xf;
136}
137
138static int
139intel_dp_max_link_bw(struct intel_dp *intel_dp)
140{
141 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
142
143 switch (max_link_bw) {
144 case DP_LINK_BW_1_62:
145 case DP_LINK_BW_2_7:
146 case DP_LINK_BW_5_4:
147 break;
148 default:
149 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
150 max_link_bw);
151 max_link_bw = DP_LINK_BW_1_62;
152 break;
153 }
154 return max_link_bw;
155}
156
157static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
158{
159 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
160 struct drm_device *dev = intel_dig_port->base.base.dev;
161 u8 source_max, sink_max;
162
163 source_max = 4;
164 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
165 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
166 source_max = 2;
167
168 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
169
170 return min(source_max, sink_max);
171}
172
173/*
174 * The units on the numbers in the next two are... bizarre. Examples will
175 * make it clearer; this one parallels an example in the eDP spec.
176 *
177 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
178 *
179 * 270000 * 1 * 8 / 10 == 216000
180 *
181 * The actual data capacity of that configuration is 2.16Gbit/s, so the
182 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
183 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
184 * 119000. At 18bpp that's 2142000 kilobits per second.
185 *
186 * Thus the strange-looking division by 10 in intel_dp_link_required, to
187 * get the result in decakilobits instead of kilobits.
188 */
189
190static int
191intel_dp_link_required(int pixel_clock, int bpp)
192{
193 return (pixel_clock * bpp + 9) / 10;
194}
195
196static int
197intel_dp_max_data_rate(int max_link_clock, int max_lanes)
198{
199 return (max_link_clock * max_lanes * 8) / 10;
200}
201
202static enum drm_mode_status
203intel_dp_mode_valid(struct drm_connector *connector,
204 struct drm_display_mode *mode)
205{
206 struct intel_dp *intel_dp = intel_attached_dp(connector);
207 struct intel_connector *intel_connector = to_intel_connector(connector);
208 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
209 int target_clock = mode->clock;
210 int max_rate, mode_rate, max_lanes, max_link_clock;
211
212 if (is_edp(intel_dp) && fixed_mode) {
213 if (mode->hdisplay > fixed_mode->hdisplay)
214 return MODE_PANEL;
215
216 if (mode->vdisplay > fixed_mode->vdisplay)
217 return MODE_PANEL;
218
219 target_clock = fixed_mode->clock;
220 }
221
222 max_link_clock = intel_dp_max_link_rate(intel_dp);
223 max_lanes = intel_dp_max_lane_count(intel_dp);
224
225 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
226 mode_rate = intel_dp_link_required(target_clock, 18);
227
228 if (mode_rate > max_rate)
229 return MODE_CLOCK_HIGH;
230
231 if (mode->clock < 10000)
232 return MODE_CLOCK_LOW;
233
234 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
235 return MODE_H_ILLEGAL;
236
237 return MODE_OK;
238}
239
240uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
241{
242 int i;
243 uint32_t v = 0;
244
245 if (src_bytes > 4)
246 src_bytes = 4;
247 for (i = 0; i < src_bytes; i++)
248 v |= ((uint32_t) src[i]) << ((3-i) * 8);
249 return v;
250}
251
252static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
253{
254 int i;
255 if (dst_bytes > 4)
256 dst_bytes = 4;
257 for (i = 0; i < dst_bytes; i++)
258 dst[i] = src >> ((3-i) * 8);
259}
260
261static void
262intel_dp_init_panel_power_sequencer(struct drm_device *dev,
263 struct intel_dp *intel_dp);
264static void
265intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
266 struct intel_dp *intel_dp);
267
268static void pps_lock(struct intel_dp *intel_dp)
269{
270 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
271 struct intel_encoder *encoder = &intel_dig_port->base;
272 struct drm_device *dev = encoder->base.dev;
273 struct drm_i915_private *dev_priv = dev->dev_private;
274 enum intel_display_power_domain power_domain;
275
276 /*
277 * See vlv_power_sequencer_reset() why we need
278 * a power domain reference here.
279 */
280 power_domain = intel_display_port_power_domain(encoder);
281 intel_display_power_get(dev_priv, power_domain);
282
283 mutex_lock(&dev_priv->pps_mutex);
284}
285
286static void pps_unlock(struct intel_dp *intel_dp)
287{
288 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
289 struct intel_encoder *encoder = &intel_dig_port->base;
290 struct drm_device *dev = encoder->base.dev;
291 struct drm_i915_private *dev_priv = dev->dev_private;
292 enum intel_display_power_domain power_domain;
293
294 mutex_unlock(&dev_priv->pps_mutex);
295
296 power_domain = intel_display_port_power_domain(encoder);
297 intel_display_power_put(dev_priv, power_domain);
298}
299
300static void
301vlv_power_sequencer_kick(struct intel_dp *intel_dp)
302{
303 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
304 struct drm_device *dev = intel_dig_port->base.base.dev;
305 struct drm_i915_private *dev_priv = dev->dev_private;
306 enum pipe pipe = intel_dp->pps_pipe;
307 bool pll_enabled, release_cl_override = false;
308 enum dpio_phy phy = DPIO_PHY(pipe);
309 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
310 uint32_t DP;
311
312 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
313 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
314 pipe_name(pipe), port_name(intel_dig_port->port)))
315 return;
316
317 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
318 pipe_name(pipe), port_name(intel_dig_port->port));
319
320 /* Preserve the BIOS-computed detected bit. This is
321 * supposed to be read-only.
322 */
323 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
324 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
325 DP |= DP_PORT_WIDTH(1);
326 DP |= DP_LINK_TRAIN_PAT_1;
327
328 if (IS_CHERRYVIEW(dev))
329 DP |= DP_PIPE_SELECT_CHV(pipe);
330 else if (pipe == PIPE_B)
331 DP |= DP_PIPEB_SELECT;
332
333 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
334
335 /*
336 * The DPLL for the pipe must be enabled for this to work.
337 * So enable temporarily it if it's not already enabled.
338 */
339 if (!pll_enabled) {
340 release_cl_override = IS_CHERRYVIEW(dev) &&
341 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
342
343 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
344 &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
345 }
346
347 /*
348 * Similar magic as in intel_dp_enable_port().
349 * We _must_ do this port enable + disable trick
350 * to make this power seqeuencer lock onto the port.
351 * Otherwise even VDD force bit won't work.
352 */
353 I915_WRITE(intel_dp->output_reg, DP);
354 POSTING_READ(intel_dp->output_reg);
355
356 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
357 POSTING_READ(intel_dp->output_reg);
358
359 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
360 POSTING_READ(intel_dp->output_reg);
361
362 if (!pll_enabled) {
363 vlv_force_pll_off(dev, pipe);
364
365 if (release_cl_override)
366 chv_phy_powergate_ch(dev_priv, phy, ch, false);
367 }
368}
369
370static enum pipe
371vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
372{
373 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
374 struct drm_device *dev = intel_dig_port->base.base.dev;
375 struct drm_i915_private *dev_priv = dev->dev_private;
376 struct intel_encoder *encoder;
377 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
378 enum pipe pipe;
379
380 lockdep_assert_held(&dev_priv->pps_mutex);
381
382 /* We should never land here with regular DP ports */
383 WARN_ON(!is_edp(intel_dp));
384
385 if (intel_dp->pps_pipe != INVALID_PIPE)
386 return intel_dp->pps_pipe;
387
388 /*
389 * We don't have power sequencer currently.
390 * Pick one that's not used by other ports.
391 */
392 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
393 base.head) {
394 struct intel_dp *tmp;
395
396 if (encoder->type != INTEL_OUTPUT_EDP)
397 continue;
398
399 tmp = enc_to_intel_dp(&encoder->base);
400
401 if (tmp->pps_pipe != INVALID_PIPE)
402 pipes &= ~(1 << tmp->pps_pipe);
403 }
404
405 /*
406 * Didn't find one. This should not happen since there
407 * are two power sequencers and up to two eDP ports.
408 */
409 if (WARN_ON(pipes == 0))
410 pipe = PIPE_A;
411 else
412 pipe = ffs(pipes) - 1;
413
414 vlv_steal_power_sequencer(dev, pipe);
415 intel_dp->pps_pipe = pipe;
416
417 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
418 pipe_name(intel_dp->pps_pipe),
419 port_name(intel_dig_port->port));
420
421 /* init power sequencer on this pipe and port */
422 intel_dp_init_panel_power_sequencer(dev, intel_dp);
423 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
424
425 /*
426 * Even vdd force doesn't work until we've made
427 * the power sequencer lock in on the port.
428 */
429 vlv_power_sequencer_kick(intel_dp);
430
431 return intel_dp->pps_pipe;
432}
433
434typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
435 enum pipe pipe);
436
437static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
438 enum pipe pipe)
439{
440 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
441}
442
443static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
444 enum pipe pipe)
445{
446 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
447}
448
449static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
450 enum pipe pipe)
451{
452 return true;
453}
454
455static enum pipe
456vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
457 enum port port,
458 vlv_pipe_check pipe_check)
459{
460 enum pipe pipe;
461
462 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
463 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
464 PANEL_PORT_SELECT_MASK;
465
466 if (port_sel != PANEL_PORT_SELECT_VLV(port))
467 continue;
468
469 if (!pipe_check(dev_priv, pipe))
470 continue;
471
472 return pipe;
473 }
474
475 return INVALID_PIPE;
476}
477
478static void
479vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
480{
481 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
482 struct drm_device *dev = intel_dig_port->base.base.dev;
483 struct drm_i915_private *dev_priv = dev->dev_private;
484 enum port port = intel_dig_port->port;
485
486 lockdep_assert_held(&dev_priv->pps_mutex);
487
488 /* try to find a pipe with this port selected */
489 /* first pick one where the panel is on */
490 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
491 vlv_pipe_has_pp_on);
492 /* didn't find one? pick one where vdd is on */
493 if (intel_dp->pps_pipe == INVALID_PIPE)
494 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
495 vlv_pipe_has_vdd_on);
496 /* didn't find one? pick one with just the correct port */
497 if (intel_dp->pps_pipe == INVALID_PIPE)
498 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
499 vlv_pipe_any);
500
501 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
502 if (intel_dp->pps_pipe == INVALID_PIPE) {
503 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
504 port_name(port));
505 return;
506 }
507
508 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
509 port_name(port), pipe_name(intel_dp->pps_pipe));
510
511 intel_dp_init_panel_power_sequencer(dev, intel_dp);
512 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
513}
514
515void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
516{
517 struct drm_device *dev = dev_priv->dev;
518 struct intel_encoder *encoder;
519
520 if (WARN_ON(!IS_VALLEYVIEW(dev)))
521 return;
522
523 /*
524 * We can't grab pps_mutex here due to deadlock with power_domain
525 * mutex when power_domain functions are called while holding pps_mutex.
526 * That also means that in order to use pps_pipe the code needs to
527 * hold both a power domain reference and pps_mutex, and the power domain
528 * reference get/put must be done while _not_ holding pps_mutex.
529 * pps_{lock,unlock}() do these steps in the correct order, so one
530 * should use them always.
531 */
532
533 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
534 struct intel_dp *intel_dp;
535
536 if (encoder->type != INTEL_OUTPUT_EDP)
537 continue;
538
539 intel_dp = enc_to_intel_dp(&encoder->base);
540 intel_dp->pps_pipe = INVALID_PIPE;
541 }
542}
543
544static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
545{
546 struct drm_device *dev = intel_dp_to_dev(intel_dp);
547
548 if (IS_BROXTON(dev))
549 return BXT_PP_CONTROL(0);
550 else if (HAS_PCH_SPLIT(dev))
551 return PCH_PP_CONTROL;
552 else
553 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
554}
555
556static u32 _pp_stat_reg(struct intel_dp *intel_dp)
557{
558 struct drm_device *dev = intel_dp_to_dev(intel_dp);
559
560 if (IS_BROXTON(dev))
561 return BXT_PP_STATUS(0);
562 else if (HAS_PCH_SPLIT(dev))
563 return PCH_PP_STATUS;
564 else
565 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
566}
567
568/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
569 This function only applicable when panel PM state is not to be tracked */
570static int edp_notify_handler(struct notifier_block *this, unsigned long code,
571 void *unused)
572{
573 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
574 edp_notifier);
575 struct drm_device *dev = intel_dp_to_dev(intel_dp);
576 struct drm_i915_private *dev_priv = dev->dev_private;
577
578 if (!is_edp(intel_dp) || code != SYS_RESTART)
579 return 0;
580
581 pps_lock(intel_dp);
582
583 if (IS_VALLEYVIEW(dev)) {
584 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
585 u32 pp_ctrl_reg, pp_div_reg;
586 u32 pp_div;
587
588 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
589 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
590 pp_div = I915_READ(pp_div_reg);
591 pp_div &= PP_REFERENCE_DIVIDER_MASK;
592
593 /* 0x1F write to PP_DIV_REG sets max cycle delay */
594 I915_WRITE(pp_div_reg, pp_div | 0x1F);
595 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
596 msleep(intel_dp->panel_power_cycle_delay);
597 }
598
599 pps_unlock(intel_dp);
600
601 return 0;
602}
603
604static bool edp_have_panel_power(struct intel_dp *intel_dp)
605{
606 struct drm_device *dev = intel_dp_to_dev(intel_dp);
607 struct drm_i915_private *dev_priv = dev->dev_private;
608
609 lockdep_assert_held(&dev_priv->pps_mutex);
610
611 if (IS_VALLEYVIEW(dev) &&
612 intel_dp->pps_pipe == INVALID_PIPE)
613 return false;
614
615 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
616}
617
618static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
619{
620 struct drm_device *dev = intel_dp_to_dev(intel_dp);
621 struct drm_i915_private *dev_priv = dev->dev_private;
622
623 lockdep_assert_held(&dev_priv->pps_mutex);
624
625 if (IS_VALLEYVIEW(dev) &&
626 intel_dp->pps_pipe == INVALID_PIPE)
627 return false;
628
629 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
630}
631
632static void
633intel_dp_check_edp(struct intel_dp *intel_dp)
634{
635 struct drm_device *dev = intel_dp_to_dev(intel_dp);
636 struct drm_i915_private *dev_priv = dev->dev_private;
637
638 if (!is_edp(intel_dp))
639 return;
640
641 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
642 WARN(1, "eDP powered off while attempting aux channel communication.\n");
643 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
644 I915_READ(_pp_stat_reg(intel_dp)),
645 I915_READ(_pp_ctrl_reg(intel_dp)));
646 }
647}
648
649static uint32_t
650intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
651{
652 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
653 struct drm_device *dev = intel_dig_port->base.base.dev;
654 struct drm_i915_private *dev_priv = dev->dev_private;
655 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
656 uint32_t status;
657 bool done;
658
659#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
660 if (has_aux_irq)
661 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
662 msecs_to_jiffies_timeout(10));
663 else
664 done = wait_for_atomic(C, 10) == 0;
665 if (!done)
666 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
667 has_aux_irq);
668#undef C
669
670 return status;
671}
672
673static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
674{
675 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
676 struct drm_device *dev = intel_dig_port->base.base.dev;
677
678 /*
679 * The clock divider is based off the hrawclk, and would like to run at
680 * 2MHz. So, take the hrawclk value and divide by 2 and use that
681 */
682 return index ? 0 : intel_hrawclk(dev) / 2;
683}
684
685static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
686{
687 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
688 struct drm_device *dev = intel_dig_port->base.base.dev;
689 struct drm_i915_private *dev_priv = dev->dev_private;
690
691 if (index)
692 return 0;
693
694 if (intel_dig_port->port == PORT_A) {
695 return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000);
696
697 } else {
698 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
699 }
700}
701
702static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
703{
704 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
705 struct drm_device *dev = intel_dig_port->base.base.dev;
706 struct drm_i915_private *dev_priv = dev->dev_private;
707
708 if (intel_dig_port->port == PORT_A) {
709 if (index)
710 return 0;
711 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
712 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
713 /* Workaround for non-ULT HSW */
714 switch (index) {
715 case 0: return 63;
716 case 1: return 72;
717 default: return 0;
718 }
719 } else {
720 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
721 }
722}
723
724static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
725{
726 return index ? 0 : 100;
727}
728
729static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
730{
731 /*
732 * SKL doesn't need us to program the AUX clock divider (Hardware will
733 * derive the clock from CDCLK automatically). We still implement the
734 * get_aux_clock_divider vfunc to plug-in into the existing code.
735 */
736 return index ? 0 : 1;
737}
738
739static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
740 bool has_aux_irq,
741 int send_bytes,
742 uint32_t aux_clock_divider)
743{
744 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
745 struct drm_device *dev = intel_dig_port->base.base.dev;
746 uint32_t precharge, timeout;
747
748 if (IS_GEN6(dev))
749 precharge = 3;
750 else
751 precharge = 5;
752
753 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
754 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
755 else
756 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
757
758 return DP_AUX_CH_CTL_SEND_BUSY |
759 DP_AUX_CH_CTL_DONE |
760 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
761 DP_AUX_CH_CTL_TIME_OUT_ERROR |
762 timeout |
763 DP_AUX_CH_CTL_RECEIVE_ERROR |
764 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
765 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
766 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
767}
768
769static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
770 bool has_aux_irq,
771 int send_bytes,
772 uint32_t unused)
773{
774 return DP_AUX_CH_CTL_SEND_BUSY |
775 DP_AUX_CH_CTL_DONE |
776 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
777 DP_AUX_CH_CTL_TIME_OUT_ERROR |
778 DP_AUX_CH_CTL_TIME_OUT_1600us |
779 DP_AUX_CH_CTL_RECEIVE_ERROR |
780 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
781 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
782}
783
784static int
785intel_dp_aux_ch(struct intel_dp *intel_dp,
786 const uint8_t *send, int send_bytes,
787 uint8_t *recv, int recv_size)
788{
789 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
790 struct drm_device *dev = intel_dig_port->base.base.dev;
791 struct drm_i915_private *dev_priv = dev->dev_private;
792 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
793 uint32_t ch_data = ch_ctl + 4;
794 uint32_t aux_clock_divider;
795 int i, ret, recv_bytes;
796 uint32_t status;
797 int try, clock = 0;
798 bool has_aux_irq = HAS_AUX_IRQ(dev);
799 bool vdd;
800
801 pps_lock(intel_dp);
802
803 /*
804 * We will be called with VDD already enabled for dpcd/edid/oui reads.
805 * In such cases we want to leave VDD enabled and it's up to upper layers
806 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
807 * ourselves.
808 */
809 vdd = edp_panel_vdd_on(intel_dp);
810
811 /* dp aux is extremely sensitive to irq latency, hence request the
812 * lowest possible wakeup latency and so prevent the cpu from going into
813 * deep sleep states.
814 */
815 pm_qos_update_request(&dev_priv->pm_qos, 0);
816
817 intel_dp_check_edp(intel_dp);
818
819 intel_aux_display_runtime_get(dev_priv);
820
821 /* Try to wait for any previous AUX channel activity */
822 for (try = 0; try < 3; try++) {
823 status = I915_READ_NOTRACE(ch_ctl);
824 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
825 break;
826 msleep(1);
827 }
828
829 if (try == 3) {
830 static u32 last_status = -1;
831 const u32 status = I915_READ(ch_ctl);
832
833 if (status != last_status) {
834 WARN(1, "dp_aux_ch not started status 0x%08x\n",
835 status);
836 last_status = status;
837 }
838
839 ret = -EBUSY;
840 goto out;
841 }
842
843 /* Only 5 data registers! */
844 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
845 ret = -E2BIG;
846 goto out;
847 }
848
849 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
850 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
851 has_aux_irq,
852 send_bytes,
853 aux_clock_divider);
854
855 /* Must try at least 3 times according to DP spec */
856 for (try = 0; try < 5; try++) {
857 /* Load the send data into the aux channel data registers */
858 for (i = 0; i < send_bytes; i += 4)
859 I915_WRITE(ch_data + i,
860 intel_dp_pack_aux(send + i,
861 send_bytes - i));
862
863 /* Send the command and wait for it to complete */
864 I915_WRITE(ch_ctl, send_ctl);
865
866 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
867
868 /* Clear done status and any errors */
869 I915_WRITE(ch_ctl,
870 status |
871 DP_AUX_CH_CTL_DONE |
872 DP_AUX_CH_CTL_TIME_OUT_ERROR |
873 DP_AUX_CH_CTL_RECEIVE_ERROR);
874
875 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
876 continue;
877
878 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
879 * 400us delay required for errors and timeouts
880 * Timeout errors from the HW already meet this
881 * requirement so skip to next iteration
882 */
883 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
884 usleep_range(400, 500);
885 continue;
886 }
887 if (status & DP_AUX_CH_CTL_DONE)
888 goto done;
889 }
890 }
891
892 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
893 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
894 ret = -EBUSY;
895 goto out;
896 }
897
898done:
899 /* Check for timeout or receive error.
900 * Timeouts occur when the sink is not connected
901 */
902 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
903 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
904 ret = -EIO;
905 goto out;
906 }
907
908 /* Timeouts occur when the device isn't connected, so they're
909 * "normal" -- don't fill the kernel log with these */
910 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
911 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
912 ret = -ETIMEDOUT;
913 goto out;
914 }
915
916 /* Unload any bytes sent back from the other side */
917 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
918 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
919 if (recv_bytes > recv_size)
920 recv_bytes = recv_size;
921
922 for (i = 0; i < recv_bytes; i += 4)
923 intel_dp_unpack_aux(I915_READ(ch_data + i),
924 recv + i, recv_bytes - i);
925
926 ret = recv_bytes;
927out:
928 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
929 intel_aux_display_runtime_put(dev_priv);
930
931 if (vdd)
932 edp_panel_vdd_off(intel_dp, false);
933
934 pps_unlock(intel_dp);
935
936 return ret;
937}
938
939#define BARE_ADDRESS_SIZE 3
940#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
941static ssize_t
942intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
943{
944 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
945 uint8_t txbuf[20], rxbuf[20];
946 size_t txsize, rxsize;
947 int ret;
948
949 txbuf[0] = (msg->request << 4) |
950 ((msg->address >> 16) & 0xf);
951 txbuf[1] = (msg->address >> 8) & 0xff;
952 txbuf[2] = msg->address & 0xff;
953 txbuf[3] = msg->size - 1;
954
955 switch (msg->request & ~DP_AUX_I2C_MOT) {
956 case DP_AUX_NATIVE_WRITE:
957 case DP_AUX_I2C_WRITE:
958 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
959 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
960 rxsize = 2; /* 0 or 1 data bytes */
961
962 if (WARN_ON(txsize > 20))
963 return -E2BIG;
964
965 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
966
967 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
968 if (ret > 0) {
969 msg->reply = rxbuf[0] >> 4;
970
971 if (ret > 1) {
972 /* Number of bytes written in a short write. */
973 ret = clamp_t(int, rxbuf[1], 0, msg->size);
974 } else {
975 /* Return payload size. */
976 ret = msg->size;
977 }
978 }
979 break;
980
981 case DP_AUX_NATIVE_READ:
982 case DP_AUX_I2C_READ:
983 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
984 rxsize = msg->size + 1;
985
986 if (WARN_ON(rxsize > 20))
987 return -E2BIG;
988
989 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
990 if (ret > 0) {
991 msg->reply = rxbuf[0] >> 4;
992 /*
993 * Assume happy day, and copy the data. The caller is
994 * expected to check msg->reply before touching it.
995 *
996 * Return payload size.
997 */
998 ret--;
999 memcpy(msg->buffer, rxbuf + 1, ret);
1000 }
1001 break;
1002
1003 default:
1004 ret = -EINVAL;
1005 break;
1006 }
1007
1008 return ret;
1009}
1010
1011static void
1012intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1013{
1014 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1015 struct drm_i915_private *dev_priv = dev->dev_private;
1016 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1017 enum port port = intel_dig_port->port;
1018 struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
1019 const char *name = NULL;
1020 uint32_t porte_aux_ctl_reg = DPA_AUX_CH_CTL;
1021 int ret;
1022
1023 /* On SKL we don't have Aux for port E so we rely on VBT to set
1024 * a proper alternate aux channel.
1025 */
1026 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && port == PORT_E) {
1027 switch (info->alternate_aux_channel) {
1028 case DP_AUX_B:
1029 porte_aux_ctl_reg = DPB_AUX_CH_CTL;
1030 break;
1031 case DP_AUX_C:
1032 porte_aux_ctl_reg = DPC_AUX_CH_CTL;
1033 break;
1034 case DP_AUX_D:
1035 porte_aux_ctl_reg = DPD_AUX_CH_CTL;
1036 break;
1037 case DP_AUX_A:
1038 default:
1039 porte_aux_ctl_reg = DPA_AUX_CH_CTL;
1040 }
1041 }
1042
1043 switch (port) {
1044 case PORT_A:
1045 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
1046 name = "DPDDC-A";
1047 break;
1048 case PORT_B:
1049 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
1050 name = "DPDDC-B";
1051 break;
1052 case PORT_C:
1053 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
1054 name = "DPDDC-C";
1055 break;
1056 case PORT_D:
1057 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
1058 name = "DPDDC-D";
1059 break;
1060 case PORT_E:
1061 intel_dp->aux_ch_ctl_reg = porte_aux_ctl_reg;
1062 name = "DPDDC-E";
1063 break;
1064 default:
1065 BUG();
1066 }
1067
1068 /*
1069 * The AUX_CTL register is usually DP_CTL + 0x10.
1070 *
1071 * On Haswell and Broadwell though:
1072 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1073 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1074 *
1075 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1076 */
1077 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev) && port != PORT_E)
1078 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
1079
1080 intel_dp->aux.name = name;
1081 intel_dp->aux.dev = dev->dev;
1082 intel_dp->aux.transfer = intel_dp_aux_transfer;
1083
1084 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1085 connector->base.kdev->kobj.name);
1086
1087 ret = drm_dp_aux_register(&intel_dp->aux);
1088 if (ret < 0) {
1089 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1090 name, ret);
1091 return;
1092 }
1093
1094 ret = sysfs_create_link(&connector->base.kdev->kobj,
1095 &intel_dp->aux.ddc.dev.kobj,
1096 intel_dp->aux.ddc.dev.kobj.name);
1097 if (ret < 0) {
1098 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
1099 drm_dp_aux_unregister(&intel_dp->aux);
1100 }
1101}
1102
1103static void
1104intel_dp_connector_unregister(struct intel_connector *intel_connector)
1105{
1106 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1107
1108 if (!intel_connector->mst_port)
1109 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1110 intel_dp->aux.ddc.dev.kobj.name);
1111 intel_connector_unregister(intel_connector);
1112}
1113
1114static void
1115skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
1116{
1117 u32 ctrl1;
1118
1119 memset(&pipe_config->dpll_hw_state, 0,
1120 sizeof(pipe_config->dpll_hw_state));
1121
1122 pipe_config->ddi_pll_sel = SKL_DPLL0;
1123 pipe_config->dpll_hw_state.cfgcr1 = 0;
1124 pipe_config->dpll_hw_state.cfgcr2 = 0;
1125
1126 ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
1127 switch (pipe_config->port_clock / 2) {
1128 case 81000:
1129 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
1130 SKL_DPLL0);
1131 break;
1132 case 135000:
1133 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350,
1134 SKL_DPLL0);
1135 break;
1136 case 270000:
1137 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700,
1138 SKL_DPLL0);
1139 break;
1140 case 162000:
1141 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620,
1142 SKL_DPLL0);
1143 break;
1144 /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1145 results in CDCLK change. Need to handle the change of CDCLK by
1146 disabling pipes and re-enabling them */
1147 case 108000:
1148 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
1149 SKL_DPLL0);
1150 break;
1151 case 216000:
1152 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
1153 SKL_DPLL0);
1154 break;
1155
1156 }
1157 pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1158}
1159
1160void
1161hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config)
1162{
1163 memset(&pipe_config->dpll_hw_state, 0,
1164 sizeof(pipe_config->dpll_hw_state));
1165
1166 switch (pipe_config->port_clock / 2) {
1167 case 81000:
1168 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1169 break;
1170 case 135000:
1171 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1172 break;
1173 case 270000:
1174 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1175 break;
1176 }
1177}
1178
1179static int
1180intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
1181{
1182 if (intel_dp->num_sink_rates) {
1183 *sink_rates = intel_dp->sink_rates;
1184 return intel_dp->num_sink_rates;
1185 }
1186
1187 *sink_rates = default_rates;
1188
1189 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
1190}
1191
1192bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1193{
1194 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1195 struct drm_device *dev = dig_port->base.base.dev;
1196
1197 /* WaDisableHBR2:skl */
1198 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
1199 return false;
1200
1201 if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
1202 (INTEL_INFO(dev)->gen >= 9))
1203 return true;
1204 else
1205 return false;
1206}
1207
1208static int
1209intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
1210{
1211 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1212 struct drm_device *dev = dig_port->base.base.dev;
1213 int size;
1214
1215 if (IS_BROXTON(dev)) {
1216 *source_rates = bxt_rates;
1217 size = ARRAY_SIZE(bxt_rates);
1218 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1219 *source_rates = skl_rates;
1220 size = ARRAY_SIZE(skl_rates);
1221 } else {
1222 *source_rates = default_rates;
1223 size = ARRAY_SIZE(default_rates);
1224 }
1225
1226 /* This depends on the fact that 5.4 is last value in the array */
1227 if (!intel_dp_source_supports_hbr2(intel_dp))
1228 size--;
1229
1230 return size;
1231}
1232
1233static void
1234intel_dp_set_clock(struct intel_encoder *encoder,
1235 struct intel_crtc_state *pipe_config)
1236{
1237 struct drm_device *dev = encoder->base.dev;
1238 const struct dp_link_dpll *divisor = NULL;
1239 int i, count = 0;
1240
1241 if (IS_G4X(dev)) {
1242 divisor = gen4_dpll;
1243 count = ARRAY_SIZE(gen4_dpll);
1244 } else if (HAS_PCH_SPLIT(dev)) {
1245 divisor = pch_dpll;
1246 count = ARRAY_SIZE(pch_dpll);
1247 } else if (IS_CHERRYVIEW(dev)) {
1248 divisor = chv_dpll;
1249 count = ARRAY_SIZE(chv_dpll);
1250 } else if (IS_VALLEYVIEW(dev)) {
1251 divisor = vlv_dpll;
1252 count = ARRAY_SIZE(vlv_dpll);
1253 }
1254
1255 if (divisor && count) {
1256 for (i = 0; i < count; i++) {
1257 if (pipe_config->port_clock == divisor[i].clock) {
1258 pipe_config->dpll = divisor[i].dpll;
1259 pipe_config->clock_set = true;
1260 break;
1261 }
1262 }
1263 }
1264}
1265
1266static int intersect_rates(const int *source_rates, int source_len,
1267 const int *sink_rates, int sink_len,
1268 int *common_rates)
1269{
1270 int i = 0, j = 0, k = 0;
1271
1272 while (i < source_len && j < sink_len) {
1273 if (source_rates[i] == sink_rates[j]) {
1274 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1275 return k;
1276 common_rates[k] = source_rates[i];
1277 ++k;
1278 ++i;
1279 ++j;
1280 } else if (source_rates[i] < sink_rates[j]) {
1281 ++i;
1282 } else {
1283 ++j;
1284 }
1285 }
1286 return k;
1287}
1288
1289static int intel_dp_common_rates(struct intel_dp *intel_dp,
1290 int *common_rates)
1291{
1292 const int *source_rates, *sink_rates;
1293 int source_len, sink_len;
1294
1295 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1296 source_len = intel_dp_source_rates(intel_dp, &source_rates);
1297
1298 return intersect_rates(source_rates, source_len,
1299 sink_rates, sink_len,
1300 common_rates);
1301}
1302
1303static void snprintf_int_array(char *str, size_t len,
1304 const int *array, int nelem)
1305{
1306 int i;
1307
1308 str[0] = '\0';
1309
1310 for (i = 0; i < nelem; i++) {
1311 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1312 if (r >= len)
1313 return;
1314 str += r;
1315 len -= r;
1316 }
1317}
1318
1319static void intel_dp_print_rates(struct intel_dp *intel_dp)
1320{
1321 const int *source_rates, *sink_rates;
1322 int source_len, sink_len, common_len;
1323 int common_rates[DP_MAX_SUPPORTED_RATES];
1324 char str[128]; /* FIXME: too big for stack? */
1325
1326 if ((drm_debug & DRM_UT_KMS) == 0)
1327 return;
1328
1329 source_len = intel_dp_source_rates(intel_dp, &source_rates);
1330 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1331 DRM_DEBUG_KMS("source rates: %s\n", str);
1332
1333 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1334 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1335 DRM_DEBUG_KMS("sink rates: %s\n", str);
1336
1337 common_len = intel_dp_common_rates(intel_dp, common_rates);
1338 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1339 DRM_DEBUG_KMS("common rates: %s\n", str);
1340}
1341
1342static int rate_to_index(int find, const int *rates)
1343{
1344 int i = 0;
1345
1346 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1347 if (find == rates[i])
1348 break;
1349
1350 return i;
1351}
1352
1353int
1354intel_dp_max_link_rate(struct intel_dp *intel_dp)
1355{
1356 int rates[DP_MAX_SUPPORTED_RATES] = {};
1357 int len;
1358
1359 len = intel_dp_common_rates(intel_dp, rates);
1360 if (WARN_ON(len <= 0))
1361 return 162000;
1362
1363 return rates[rate_to_index(0, rates) - 1];
1364}
1365
1366int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1367{
1368 return rate_to_index(rate, intel_dp->sink_rates);
1369}
1370
1371void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1372 uint8_t *link_bw, uint8_t *rate_select)
1373{
1374 if (intel_dp->num_sink_rates) {
1375 *link_bw = 0;
1376 *rate_select =
1377 intel_dp_rate_select(intel_dp, port_clock);
1378 } else {
1379 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1380 *rate_select = 0;
1381 }
1382}
1383
1384bool
1385intel_dp_compute_config(struct intel_encoder *encoder,
1386 struct intel_crtc_state *pipe_config)
1387{
1388 struct drm_device *dev = encoder->base.dev;
1389 struct drm_i915_private *dev_priv = dev->dev_private;
1390 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1391 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1392 enum port port = dp_to_dig_port(intel_dp)->port;
1393 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1394 struct intel_connector *intel_connector = intel_dp->attached_connector;
1395 int lane_count, clock;
1396 int min_lane_count = 1;
1397 int max_lane_count = intel_dp_max_lane_count(intel_dp);
1398 /* Conveniently, the link BW constants become indices with a shift...*/
1399 int min_clock = 0;
1400 int max_clock;
1401 int bpp, mode_rate;
1402 int link_avail, link_clock;
1403 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1404 int common_len;
1405 uint8_t link_bw, rate_select;
1406
1407 common_len = intel_dp_common_rates(intel_dp, common_rates);
1408
1409 /* No common link rates between source and sink */
1410 WARN_ON(common_len <= 0);
1411
1412 max_clock = common_len - 1;
1413
1414 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1415 pipe_config->has_pch_encoder = true;
1416
1417 pipe_config->has_dp_encoder = true;
1418 pipe_config->has_drrs = false;
1419 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1420
1421 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1422 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1423 adjusted_mode);
1424
1425 if (INTEL_INFO(dev)->gen >= 9) {
1426 int ret;
1427 ret = skl_update_scaler_crtc(pipe_config);
1428 if (ret)
1429 return ret;
1430 }
1431
1432 if (HAS_GMCH_DISPLAY(dev))
1433 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1434 intel_connector->panel.fitting_mode);
1435 else
1436 intel_pch_panel_fitting(intel_crtc, pipe_config,
1437 intel_connector->panel.fitting_mode);
1438 }
1439
1440 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1441 return false;
1442
1443 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1444 "max bw %d pixel clock %iKHz\n",
1445 max_lane_count, common_rates[max_clock],
1446 adjusted_mode->crtc_clock);
1447
1448 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1449 * bpc in between. */
1450 bpp = pipe_config->pipe_bpp;
1451 if (is_edp(intel_dp)) {
1452
1453 /* Get bpp from vbt only for panels that dont have bpp in edid */
1454 if (intel_connector->base.display_info.bpc == 0 &&
1455 (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp)) {
1456 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1457 dev_priv->vbt.edp_bpp);
1458 bpp = dev_priv->vbt.edp_bpp;
1459 }
1460
1461 /*
1462 * Use the maximum clock and number of lanes the eDP panel
1463 * advertizes being capable of. The panels are generally
1464 * designed to support only a single clock and lane
1465 * configuration, and typically these values correspond to the
1466 * native resolution of the panel.
1467 */
1468 min_lane_count = max_lane_count;
1469 min_clock = max_clock;
1470 }
1471
1472 for (; bpp >= 6*3; bpp -= 2*3) {
1473 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1474 bpp);
1475
1476 for (clock = min_clock; clock <= max_clock; clock++) {
1477 for (lane_count = min_lane_count;
1478 lane_count <= max_lane_count;
1479 lane_count <<= 1) {
1480
1481 link_clock = common_rates[clock];
1482 link_avail = intel_dp_max_data_rate(link_clock,
1483 lane_count);
1484
1485 if (mode_rate <= link_avail) {
1486 goto found;
1487 }
1488 }
1489 }
1490 }
1491
1492 return false;
1493
1494found:
1495 if (intel_dp->color_range_auto) {
1496 /*
1497 * See:
1498 * CEA-861-E - 5.1 Default Encoding Parameters
1499 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1500 */
1501 pipe_config->limited_color_range =
1502 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1503 } else {
1504 pipe_config->limited_color_range =
1505 intel_dp->limited_color_range;
1506 }
1507
1508 pipe_config->lane_count = lane_count;
1509
1510 pipe_config->pipe_bpp = bpp;
1511 pipe_config->port_clock = common_rates[clock];
1512
1513 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1514 &link_bw, &rate_select);
1515
1516 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1517 link_bw, rate_select, pipe_config->lane_count,
1518 pipe_config->port_clock, bpp);
1519 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1520 mode_rate, link_avail);
1521
1522 intel_link_compute_m_n(bpp, lane_count,
1523 adjusted_mode->crtc_clock,
1524 pipe_config->port_clock,
1525 &pipe_config->dp_m_n);
1526
1527 if (intel_connector->panel.downclock_mode != NULL &&
1528 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1529 pipe_config->has_drrs = true;
1530 intel_link_compute_m_n(bpp, lane_count,
1531 intel_connector->panel.downclock_mode->clock,
1532 pipe_config->port_clock,
1533 &pipe_config->dp_m2_n2);
1534 }
1535
1536 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && is_edp(intel_dp))
1537 skl_edp_set_pll_config(pipe_config);
1538 else if (IS_BROXTON(dev))
1539 /* handled in ddi */;
1540 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1541 hsw_dp_set_ddi_pll_sel(pipe_config);
1542 else
1543 intel_dp_set_clock(encoder, pipe_config);
1544
1545 return true;
1546}
1547
1548void intel_dp_set_link_params(struct intel_dp *intel_dp,
1549 const struct intel_crtc_state *pipe_config)
1550{
1551 intel_dp->link_rate = pipe_config->port_clock;
1552 intel_dp->lane_count = pipe_config->lane_count;
1553}
1554
1555static void intel_dp_prepare(struct intel_encoder *encoder)
1556{
1557 struct drm_device *dev = encoder->base.dev;
1558 struct drm_i915_private *dev_priv = dev->dev_private;
1559 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1560 enum port port = dp_to_dig_port(intel_dp)->port;
1561 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1562 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
1563
1564 intel_dp_set_link_params(intel_dp, crtc->config);
1565
1566 /*
1567 * There are four kinds of DP registers:
1568 *
1569 * IBX PCH
1570 * SNB CPU
1571 * IVB CPU
1572 * CPT PCH
1573 *
1574 * IBX PCH and CPU are the same for almost everything,
1575 * except that the CPU DP PLL is configured in this
1576 * register
1577 *
1578 * CPT PCH is quite different, having many bits moved
1579 * to the TRANS_DP_CTL register instead. That
1580 * configuration happens (oddly) in ironlake_pch_enable
1581 */
1582
1583 /* Preserve the BIOS-computed detected bit. This is
1584 * supposed to be read-only.
1585 */
1586 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1587
1588 /* Handle DP bits in common between all three register formats */
1589 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1590 intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
1591
1592 /* Split out the IBX/CPU vs CPT settings */
1593
1594 if (IS_GEN7(dev) && port == PORT_A) {
1595 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1596 intel_dp->DP |= DP_SYNC_HS_HIGH;
1597 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1598 intel_dp->DP |= DP_SYNC_VS_HIGH;
1599 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1600
1601 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1602 intel_dp->DP |= DP_ENHANCED_FRAMING;
1603
1604 intel_dp->DP |= crtc->pipe << 29;
1605 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
1606 u32 trans_dp;
1607
1608 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1609
1610 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1611 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1612 trans_dp |= TRANS_DP_ENH_FRAMING;
1613 else
1614 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1615 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1616 } else {
1617 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1618 crtc->config->limited_color_range)
1619 intel_dp->DP |= DP_COLOR_RANGE_16_235;
1620
1621 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1622 intel_dp->DP |= DP_SYNC_HS_HIGH;
1623 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1624 intel_dp->DP |= DP_SYNC_VS_HIGH;
1625 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1626
1627 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1628 intel_dp->DP |= DP_ENHANCED_FRAMING;
1629
1630 if (IS_CHERRYVIEW(dev))
1631 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1632 else if (crtc->pipe == PIPE_B)
1633 intel_dp->DP |= DP_PIPEB_SELECT;
1634 }
1635}
1636
1637#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1638#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1639
1640#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1641#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1642
1643#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1644#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1645
1646static void wait_panel_status(struct intel_dp *intel_dp,
1647 u32 mask,
1648 u32 value)
1649{
1650 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1651 struct drm_i915_private *dev_priv = dev->dev_private;
1652 u32 pp_stat_reg, pp_ctrl_reg;
1653
1654 lockdep_assert_held(&dev_priv->pps_mutex);
1655
1656 pp_stat_reg = _pp_stat_reg(intel_dp);
1657 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1658
1659 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1660 mask, value,
1661 I915_READ(pp_stat_reg),
1662 I915_READ(pp_ctrl_reg));
1663
1664 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1665 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1666 I915_READ(pp_stat_reg),
1667 I915_READ(pp_ctrl_reg));
1668 }
1669
1670 DRM_DEBUG_KMS("Wait complete\n");
1671}
1672
1673static void wait_panel_on(struct intel_dp *intel_dp)
1674{
1675 DRM_DEBUG_KMS("Wait for panel power on\n");
1676 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1677}
1678
1679static void wait_panel_off(struct intel_dp *intel_dp)
1680{
1681 DRM_DEBUG_KMS("Wait for panel power off time\n");
1682 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1683}
1684
1685static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1686{
1687 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1688
1689 /* When we disable the VDD override bit last we have to do the manual
1690 * wait. */
1691 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1692 intel_dp->panel_power_cycle_delay);
1693
1694 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1695}
1696
1697static void wait_backlight_on(struct intel_dp *intel_dp)
1698{
1699 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1700 intel_dp->backlight_on_delay);
1701}
1702
1703static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1704{
1705 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1706 intel_dp->backlight_off_delay);
1707}
1708
1709/* Read the current pp_control value, unlocking the register if it
1710 * is locked
1711 */
1712
1713static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1714{
1715 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1716 struct drm_i915_private *dev_priv = dev->dev_private;
1717 u32 control;
1718
1719 lockdep_assert_held(&dev_priv->pps_mutex);
1720
1721 control = I915_READ(_pp_ctrl_reg(intel_dp));
1722 if (!IS_BROXTON(dev)) {
1723 control &= ~PANEL_UNLOCK_MASK;
1724 control |= PANEL_UNLOCK_REGS;
1725 }
1726 return control;
1727}
1728
1729/*
1730 * Must be paired with edp_panel_vdd_off().
1731 * Must hold pps_mutex around the whole on/off sequence.
1732 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1733 */
1734static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1735{
1736 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1737 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1738 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1739 struct drm_i915_private *dev_priv = dev->dev_private;
1740 enum intel_display_power_domain power_domain;
1741 u32 pp;
1742 u32 pp_stat_reg, pp_ctrl_reg;
1743 bool need_to_disable = !intel_dp->want_panel_vdd;
1744
1745 lockdep_assert_held(&dev_priv->pps_mutex);
1746
1747 if (!is_edp(intel_dp))
1748 return false;
1749
1750 cancel_delayed_work(&intel_dp->panel_vdd_work);
1751 intel_dp->want_panel_vdd = true;
1752
1753 if (edp_have_panel_vdd(intel_dp))
1754 return need_to_disable;
1755
1756 power_domain = intel_display_port_power_domain(intel_encoder);
1757 intel_display_power_get(dev_priv, power_domain);
1758
1759 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1760 port_name(intel_dig_port->port));
1761
1762 if (!edp_have_panel_power(intel_dp))
1763 wait_panel_power_cycle(intel_dp);
1764
1765 pp = ironlake_get_pp_control(intel_dp);
1766 pp |= EDP_FORCE_VDD;
1767
1768 pp_stat_reg = _pp_stat_reg(intel_dp);
1769 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1770
1771 I915_WRITE(pp_ctrl_reg, pp);
1772 POSTING_READ(pp_ctrl_reg);
1773 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1774 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1775 /*
1776 * If the panel wasn't on, delay before accessing aux channel
1777 */
1778 if (!edp_have_panel_power(intel_dp)) {
1779 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1780 port_name(intel_dig_port->port));
1781 msleep(intel_dp->panel_power_up_delay);
1782 }
1783
1784 return need_to_disable;
1785}
1786
1787/*
1788 * Must be paired with intel_edp_panel_vdd_off() or
1789 * intel_edp_panel_off().
1790 * Nested calls to these functions are not allowed since
1791 * we drop the lock. Caller must use some higher level
1792 * locking to prevent nested calls from other threads.
1793 */
1794void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1795{
1796 bool vdd;
1797
1798 if (!is_edp(intel_dp))
1799 return;
1800
1801 pps_lock(intel_dp);
1802 vdd = edp_panel_vdd_on(intel_dp);
1803 pps_unlock(intel_dp);
1804
1805 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
1806 port_name(dp_to_dig_port(intel_dp)->port));
1807}
1808
1809static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1810{
1811 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1812 struct drm_i915_private *dev_priv = dev->dev_private;
1813 struct intel_digital_port *intel_dig_port =
1814 dp_to_dig_port(intel_dp);
1815 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1816 enum intel_display_power_domain power_domain;
1817 u32 pp;
1818 u32 pp_stat_reg, pp_ctrl_reg;
1819
1820 lockdep_assert_held(&dev_priv->pps_mutex);
1821
1822 WARN_ON(intel_dp->want_panel_vdd);
1823
1824 if (!edp_have_panel_vdd(intel_dp))
1825 return;
1826
1827 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1828 port_name(intel_dig_port->port));
1829
1830 pp = ironlake_get_pp_control(intel_dp);
1831 pp &= ~EDP_FORCE_VDD;
1832
1833 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1834 pp_stat_reg = _pp_stat_reg(intel_dp);
1835
1836 I915_WRITE(pp_ctrl_reg, pp);
1837 POSTING_READ(pp_ctrl_reg);
1838
1839 /* Make sure sequencer is idle before allowing subsequent activity */
1840 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1841 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1842
1843 if ((pp & POWER_TARGET_ON) == 0)
1844 intel_dp->last_power_cycle = jiffies;
1845
1846 power_domain = intel_display_port_power_domain(intel_encoder);
1847 intel_display_power_put(dev_priv, power_domain);
1848}
1849
1850static void edp_panel_vdd_work(struct work_struct *__work)
1851{
1852 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1853 struct intel_dp, panel_vdd_work);
1854
1855 pps_lock(intel_dp);
1856 if (!intel_dp->want_panel_vdd)
1857 edp_panel_vdd_off_sync(intel_dp);
1858 pps_unlock(intel_dp);
1859}
1860
1861static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1862{
1863 unsigned long delay;
1864
1865 /*
1866 * Queue the timer to fire a long time from now (relative to the power
1867 * down delay) to keep the panel power up across a sequence of
1868 * operations.
1869 */
1870 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1871 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1872}
1873
1874/*
1875 * Must be paired with edp_panel_vdd_on().
1876 * Must hold pps_mutex around the whole on/off sequence.
1877 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1878 */
1879static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1880{
1881 struct drm_i915_private *dev_priv =
1882 intel_dp_to_dev(intel_dp)->dev_private;
1883
1884 lockdep_assert_held(&dev_priv->pps_mutex);
1885
1886 if (!is_edp(intel_dp))
1887 return;
1888
1889 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
1890 port_name(dp_to_dig_port(intel_dp)->port));
1891
1892 intel_dp->want_panel_vdd = false;
1893
1894 if (sync)
1895 edp_panel_vdd_off_sync(intel_dp);
1896 else
1897 edp_panel_vdd_schedule_off(intel_dp);
1898}
1899
1900static void edp_panel_on(struct intel_dp *intel_dp)
1901{
1902 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1903 struct drm_i915_private *dev_priv = dev->dev_private;
1904 u32 pp;
1905 u32 pp_ctrl_reg;
1906
1907 lockdep_assert_held(&dev_priv->pps_mutex);
1908
1909 if (!is_edp(intel_dp))
1910 return;
1911
1912 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1913 port_name(dp_to_dig_port(intel_dp)->port));
1914
1915 if (WARN(edp_have_panel_power(intel_dp),
1916 "eDP port %c panel power already on\n",
1917 port_name(dp_to_dig_port(intel_dp)->port)))
1918 return;
1919
1920 wait_panel_power_cycle(intel_dp);
1921
1922 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1923 pp = ironlake_get_pp_control(intel_dp);
1924 if (IS_GEN5(dev)) {
1925 /* ILK workaround: disable reset around power sequence */
1926 pp &= ~PANEL_POWER_RESET;
1927 I915_WRITE(pp_ctrl_reg, pp);
1928 POSTING_READ(pp_ctrl_reg);
1929 }
1930
1931 pp |= POWER_TARGET_ON;
1932 if (!IS_GEN5(dev))
1933 pp |= PANEL_POWER_RESET;
1934
1935 I915_WRITE(pp_ctrl_reg, pp);
1936 POSTING_READ(pp_ctrl_reg);
1937
1938 wait_panel_on(intel_dp);
1939 intel_dp->last_power_on = jiffies;
1940
1941 if (IS_GEN5(dev)) {
1942 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1943 I915_WRITE(pp_ctrl_reg, pp);
1944 POSTING_READ(pp_ctrl_reg);
1945 }
1946}
1947
1948void intel_edp_panel_on(struct intel_dp *intel_dp)
1949{
1950 if (!is_edp(intel_dp))
1951 return;
1952
1953 pps_lock(intel_dp);
1954 edp_panel_on(intel_dp);
1955 pps_unlock(intel_dp);
1956}
1957
1958
1959static void edp_panel_off(struct intel_dp *intel_dp)
1960{
1961 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1962 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1963 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1964 struct drm_i915_private *dev_priv = dev->dev_private;
1965 enum intel_display_power_domain power_domain;
1966 u32 pp;
1967 u32 pp_ctrl_reg;
1968
1969 lockdep_assert_held(&dev_priv->pps_mutex);
1970
1971 if (!is_edp(intel_dp))
1972 return;
1973
1974 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1975 port_name(dp_to_dig_port(intel_dp)->port));
1976
1977 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
1978 port_name(dp_to_dig_port(intel_dp)->port));
1979
1980 pp = ironlake_get_pp_control(intel_dp);
1981 /* We need to switch off panel power _and_ force vdd, for otherwise some
1982 * panels get very unhappy and cease to work. */
1983 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1984 EDP_BLC_ENABLE);
1985
1986 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1987
1988 intel_dp->want_panel_vdd = false;
1989
1990 I915_WRITE(pp_ctrl_reg, pp);
1991 POSTING_READ(pp_ctrl_reg);
1992
1993 intel_dp->last_power_cycle = jiffies;
1994 wait_panel_off(intel_dp);
1995
1996 /* We got a reference when we enabled the VDD. */
1997 power_domain = intel_display_port_power_domain(intel_encoder);
1998 intel_display_power_put(dev_priv, power_domain);
1999}
2000
2001void intel_edp_panel_off(struct intel_dp *intel_dp)
2002{
2003 if (!is_edp(intel_dp))
2004 return;
2005
2006 pps_lock(intel_dp);
2007 edp_panel_off(intel_dp);
2008 pps_unlock(intel_dp);
2009}
2010
2011/* Enable backlight in the panel power control. */
2012static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2013{
2014 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2015 struct drm_device *dev = intel_dig_port->base.base.dev;
2016 struct drm_i915_private *dev_priv = dev->dev_private;
2017 u32 pp;
2018 u32 pp_ctrl_reg;
2019
2020 /*
2021 * If we enable the backlight right away following a panel power
2022 * on, we may see slight flicker as the panel syncs with the eDP
2023 * link. So delay a bit to make sure the image is solid before
2024 * allowing it to appear.
2025 */
2026 wait_backlight_on(intel_dp);
2027
2028 pps_lock(intel_dp);
2029
2030 pp = ironlake_get_pp_control(intel_dp);
2031 pp |= EDP_BLC_ENABLE;
2032
2033 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2034
2035 I915_WRITE(pp_ctrl_reg, pp);
2036 POSTING_READ(pp_ctrl_reg);
2037
2038 pps_unlock(intel_dp);
2039}
2040
2041/* Enable backlight PWM and backlight PP control. */
2042void intel_edp_backlight_on(struct intel_dp *intel_dp)
2043{
2044 if (!is_edp(intel_dp))
2045 return;
2046
2047 DRM_DEBUG_KMS("\n");
2048
2049 intel_panel_enable_backlight(intel_dp->attached_connector);
2050 _intel_edp_backlight_on(intel_dp);
2051}
2052
2053/* Disable backlight in the panel power control. */
2054static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2055{
2056 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2057 struct drm_i915_private *dev_priv = dev->dev_private;
2058 u32 pp;
2059 u32 pp_ctrl_reg;
2060
2061 if (!is_edp(intel_dp))
2062 return;
2063
2064 pps_lock(intel_dp);
2065
2066 pp = ironlake_get_pp_control(intel_dp);
2067 pp &= ~EDP_BLC_ENABLE;
2068
2069 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2070
2071 I915_WRITE(pp_ctrl_reg, pp);
2072 POSTING_READ(pp_ctrl_reg);
2073
2074 pps_unlock(intel_dp);
2075
2076 intel_dp->last_backlight_off = jiffies;
2077 edp_wait_backlight_off(intel_dp);
2078}
2079
2080/* Disable backlight PP control and backlight PWM. */
2081void intel_edp_backlight_off(struct intel_dp *intel_dp)
2082{
2083 if (!is_edp(intel_dp))
2084 return;
2085
2086 DRM_DEBUG_KMS("\n");
2087
2088 _intel_edp_backlight_off(intel_dp);
2089 intel_panel_disable_backlight(intel_dp->attached_connector);
2090}
2091
2092/*
2093 * Hook for controlling the panel power control backlight through the bl_power
2094 * sysfs attribute. Take care to handle multiple calls.
2095 */
2096static void intel_edp_backlight_power(struct intel_connector *connector,
2097 bool enable)
2098{
2099 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2100 bool is_enabled;
2101
2102 pps_lock(intel_dp);
2103 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2104 pps_unlock(intel_dp);
2105
2106 if (is_enabled == enable)
2107 return;
2108
2109 DRM_DEBUG_KMS("panel power control backlight %s\n",
2110 enable ? "enable" : "disable");
2111
2112 if (enable)
2113 _intel_edp_backlight_on(intel_dp);
2114 else
2115 _intel_edp_backlight_off(intel_dp);
2116}
2117
2118static const char *state_string(bool enabled)
2119{
2120 return enabled ? "on" : "off";
2121}
2122
2123static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2124{
2125 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2126 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2127 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2128
2129 I915_STATE_WARN(cur_state != state,
2130 "DP port %c state assertion failure (expected %s, current %s)\n",
2131 port_name(dig_port->port),
2132 state_string(state), state_string(cur_state));
2133}
2134#define assert_dp_port_disabled(d) assert_dp_port((d), false)
2135
2136static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2137{
2138 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2139
2140 I915_STATE_WARN(cur_state != state,
2141 "eDP PLL state assertion failure (expected %s, current %s)\n",
2142 state_string(state), state_string(cur_state));
2143}
2144#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2145#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2146
2147static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
2148{
2149 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2150 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2151 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2152
2153 assert_pipe_disabled(dev_priv, crtc->pipe);
2154 assert_dp_port_disabled(intel_dp);
2155 assert_edp_pll_disabled(dev_priv);
2156
2157 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2158 crtc->config->port_clock);
2159
2160 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2161
2162 if (crtc->config->port_clock == 162000)
2163 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2164 else
2165 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2166
2167 I915_WRITE(DP_A, intel_dp->DP);
2168 POSTING_READ(DP_A);
2169 udelay(500);
2170
2171 intel_dp->DP |= DP_PLL_ENABLE;
2172
2173 I915_WRITE(DP_A, intel_dp->DP);
2174 POSTING_READ(DP_A);
2175 udelay(200);
2176}
2177
2178static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2179{
2180 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2181 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2182 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2183
2184 assert_pipe_disabled(dev_priv, crtc->pipe);
2185 assert_dp_port_disabled(intel_dp);
2186 assert_edp_pll_enabled(dev_priv);
2187
2188 DRM_DEBUG_KMS("disabling eDP PLL\n");
2189
2190 intel_dp->DP &= ~DP_PLL_ENABLE;
2191
2192 I915_WRITE(DP_A, intel_dp->DP);
2193 POSTING_READ(DP_A);
2194 udelay(200);
2195}
2196
2197/* If the sink supports it, try to set the power state appropriately */
2198void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2199{
2200 int ret, i;
2201
2202 /* Should have a valid DPCD by this point */
2203 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2204 return;
2205
2206 if (mode != DRM_MODE_DPMS_ON) {
2207 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2208 DP_SET_POWER_D3);
2209 } else {
2210 /*
2211 * When turning on, we need to retry for 1ms to give the sink
2212 * time to wake up.
2213 */
2214 for (i = 0; i < 3; i++) {
2215 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2216 DP_SET_POWER_D0);
2217 if (ret == 1)
2218 break;
2219 msleep(1);
2220 }
2221 }
2222
2223 if (ret != 1)
2224 DRM_DEBUG_KMS("failed to %s sink power state\n",
2225 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2226}
2227
2228static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2229 enum pipe *pipe)
2230{
2231 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2232 enum port port = dp_to_dig_port(intel_dp)->port;
2233 struct drm_device *dev = encoder->base.dev;
2234 struct drm_i915_private *dev_priv = dev->dev_private;
2235 enum intel_display_power_domain power_domain;
2236 u32 tmp;
2237
2238 power_domain = intel_display_port_power_domain(encoder);
2239 if (!intel_display_power_is_enabled(dev_priv, power_domain))
2240 return false;
2241
2242 tmp = I915_READ(intel_dp->output_reg);
2243
2244 if (!(tmp & DP_PORT_EN))
2245 return false;
2246
2247 if (IS_GEN7(dev) && port == PORT_A) {
2248 *pipe = PORT_TO_PIPE_CPT(tmp);
2249 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
2250 enum pipe p;
2251
2252 for_each_pipe(dev_priv, p) {
2253 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2254 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2255 *pipe = p;
2256 return true;
2257 }
2258 }
2259
2260 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2261 intel_dp->output_reg);
2262 } else if (IS_CHERRYVIEW(dev)) {
2263 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2264 } else {
2265 *pipe = PORT_TO_PIPE(tmp);
2266 }
2267
2268 return true;
2269}
2270
2271static void intel_dp_get_config(struct intel_encoder *encoder,
2272 struct intel_crtc_state *pipe_config)
2273{
2274 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2275 u32 tmp, flags = 0;
2276 struct drm_device *dev = encoder->base.dev;
2277 struct drm_i915_private *dev_priv = dev->dev_private;
2278 enum port port = dp_to_dig_port(intel_dp)->port;
2279 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2280 int dotclock;
2281
2282 tmp = I915_READ(intel_dp->output_reg);
2283
2284 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2285
2286 if (HAS_PCH_CPT(dev) && port != PORT_A) {
2287 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2288
2289 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2290 flags |= DRM_MODE_FLAG_PHSYNC;
2291 else
2292 flags |= DRM_MODE_FLAG_NHSYNC;
2293
2294 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2295 flags |= DRM_MODE_FLAG_PVSYNC;
2296 else
2297 flags |= DRM_MODE_FLAG_NVSYNC;
2298 } else {
2299 if (tmp & DP_SYNC_HS_HIGH)
2300 flags |= DRM_MODE_FLAG_PHSYNC;
2301 else
2302 flags |= DRM_MODE_FLAG_NHSYNC;
2303
2304 if (tmp & DP_SYNC_VS_HIGH)
2305 flags |= DRM_MODE_FLAG_PVSYNC;
2306 else
2307 flags |= DRM_MODE_FLAG_NVSYNC;
2308 }
2309
2310 pipe_config->base.adjusted_mode.flags |= flags;
2311
2312 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2313 tmp & DP_COLOR_RANGE_16_235)
2314 pipe_config->limited_color_range = true;
2315
2316 pipe_config->has_dp_encoder = true;
2317
2318 pipe_config->lane_count =
2319 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2320
2321 intel_dp_get_m_n(crtc, pipe_config);
2322
2323 if (port == PORT_A) {
2324 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2325 pipe_config->port_clock = 162000;
2326 else
2327 pipe_config->port_clock = 270000;
2328 }
2329
2330 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2331 &pipe_config->dp_m_n);
2332
2333 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2334 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2335
2336 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
2337
2338 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2339 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2340 /*
2341 * This is a big fat ugly hack.
2342 *
2343 * Some machines in UEFI boot mode provide us a VBT that has 18
2344 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2345 * unknown we fail to light up. Yet the same BIOS boots up with
2346 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2347 * max, not what it tells us to use.
2348 *
2349 * Note: This will still be broken if the eDP panel is not lit
2350 * up by the BIOS, and thus we can't get the mode at module
2351 * load.
2352 */
2353 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2354 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2355 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2356 }
2357}
2358
2359static void intel_disable_dp(struct intel_encoder *encoder)
2360{
2361 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2362 struct drm_device *dev = encoder->base.dev;
2363 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2364
2365 if (crtc->config->has_audio)
2366 intel_audio_codec_disable(encoder);
2367
2368 if (HAS_PSR(dev) && !HAS_DDI(dev))
2369 intel_psr_disable(intel_dp);
2370
2371 /* Make sure the panel is off before trying to change the mode. But also
2372 * ensure that we have vdd while we switch off the panel. */
2373 intel_edp_panel_vdd_on(intel_dp);
2374 intel_edp_backlight_off(intel_dp);
2375 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2376 intel_edp_panel_off(intel_dp);
2377
2378 /* disable the port before the pipe on g4x */
2379 if (INTEL_INFO(dev)->gen < 5)
2380 intel_dp_link_down(intel_dp);
2381}
2382
2383static void ilk_post_disable_dp(struct intel_encoder *encoder)
2384{
2385 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2386 enum port port = dp_to_dig_port(intel_dp)->port;
2387
2388 intel_dp_link_down(intel_dp);
2389
2390 /* Only ilk+ has port A */
2391 if (port == PORT_A)
2392 ironlake_edp_pll_off(intel_dp);
2393}
2394
2395static void vlv_post_disable_dp(struct intel_encoder *encoder)
2396{
2397 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2398
2399 intel_dp_link_down(intel_dp);
2400}
2401
2402static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
2403 bool reset)
2404{
2405 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2406 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
2407 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2408 enum pipe pipe = crtc->pipe;
2409 uint32_t val;
2410
2411 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2412 if (reset)
2413 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2414 else
2415 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
2416 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2417
2418 if (crtc->config->lane_count > 2) {
2419 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2420 if (reset)
2421 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2422 else
2423 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
2424 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2425 }
2426
2427 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2428 val |= CHV_PCS_REQ_SOFTRESET_EN;
2429 if (reset)
2430 val &= ~DPIO_PCS_CLK_SOFT_RESET;
2431 else
2432 val |= DPIO_PCS_CLK_SOFT_RESET;
2433 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2434
2435 if (crtc->config->lane_count > 2) {
2436 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2437 val |= CHV_PCS_REQ_SOFTRESET_EN;
2438 if (reset)
2439 val &= ~DPIO_PCS_CLK_SOFT_RESET;
2440 else
2441 val |= DPIO_PCS_CLK_SOFT_RESET;
2442 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2443 }
2444}
2445
2446static void chv_post_disable_dp(struct intel_encoder *encoder)
2447{
2448 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2449 struct drm_device *dev = encoder->base.dev;
2450 struct drm_i915_private *dev_priv = dev->dev_private;
2451
2452 intel_dp_link_down(intel_dp);
2453
2454 mutex_lock(&dev_priv->sb_lock);
2455
2456 /* Assert data lane reset */
2457 chv_data_lane_soft_reset(encoder, true);
2458
2459 mutex_unlock(&dev_priv->sb_lock);
2460}
2461
2462static void
2463_intel_dp_set_link_train(struct intel_dp *intel_dp,
2464 uint32_t *DP,
2465 uint8_t dp_train_pat)
2466{
2467 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2468 struct drm_device *dev = intel_dig_port->base.base.dev;
2469 struct drm_i915_private *dev_priv = dev->dev_private;
2470 enum port port = intel_dig_port->port;
2471
2472 if (HAS_DDI(dev)) {
2473 uint32_t temp = I915_READ(DP_TP_CTL(port));
2474
2475 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2476 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2477 else
2478 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2479
2480 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2481 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2482 case DP_TRAINING_PATTERN_DISABLE:
2483 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2484
2485 break;
2486 case DP_TRAINING_PATTERN_1:
2487 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2488 break;
2489 case DP_TRAINING_PATTERN_2:
2490 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2491 break;
2492 case DP_TRAINING_PATTERN_3:
2493 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2494 break;
2495 }
2496 I915_WRITE(DP_TP_CTL(port), temp);
2497
2498 } else if ((IS_GEN7(dev) && port == PORT_A) ||
2499 (HAS_PCH_CPT(dev) && port != PORT_A)) {
2500 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2501
2502 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2503 case DP_TRAINING_PATTERN_DISABLE:
2504 *DP |= DP_LINK_TRAIN_OFF_CPT;
2505 break;
2506 case DP_TRAINING_PATTERN_1:
2507 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2508 break;
2509 case DP_TRAINING_PATTERN_2:
2510 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2511 break;
2512 case DP_TRAINING_PATTERN_3:
2513 DRM_ERROR("DP training pattern 3 not supported\n");
2514 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2515 break;
2516 }
2517
2518 } else {
2519 if (IS_CHERRYVIEW(dev))
2520 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2521 else
2522 *DP &= ~DP_LINK_TRAIN_MASK;
2523
2524 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2525 case DP_TRAINING_PATTERN_DISABLE:
2526 *DP |= DP_LINK_TRAIN_OFF;
2527 break;
2528 case DP_TRAINING_PATTERN_1:
2529 *DP |= DP_LINK_TRAIN_PAT_1;
2530 break;
2531 case DP_TRAINING_PATTERN_2:
2532 *DP |= DP_LINK_TRAIN_PAT_2;
2533 break;
2534 case DP_TRAINING_PATTERN_3:
2535 if (IS_CHERRYVIEW(dev)) {
2536 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2537 } else {
2538 DRM_ERROR("DP training pattern 3 not supported\n");
2539 *DP |= DP_LINK_TRAIN_PAT_2;
2540 }
2541 break;
2542 }
2543 }
2544}
2545
2546static void intel_dp_enable_port(struct intel_dp *intel_dp)
2547{
2548 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2549 struct drm_i915_private *dev_priv = dev->dev_private;
2550 struct intel_crtc *crtc =
2551 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
2552
2553 /* enable with pattern 1 (as per spec) */
2554 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2555 DP_TRAINING_PATTERN_1);
2556
2557 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2558 POSTING_READ(intel_dp->output_reg);
2559
2560 /*
2561 * Magic for VLV/CHV. We _must_ first set up the register
2562 * without actually enabling the port, and then do another
2563 * write to enable the port. Otherwise link training will
2564 * fail when the power sequencer is freshly used for this port.
2565 */
2566 intel_dp->DP |= DP_PORT_EN;
2567 if (crtc->config->has_audio)
2568 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2569
2570 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2571 POSTING_READ(intel_dp->output_reg);
2572}
2573
2574static void intel_enable_dp(struct intel_encoder *encoder)
2575{
2576 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2577 struct drm_device *dev = encoder->base.dev;
2578 struct drm_i915_private *dev_priv = dev->dev_private;
2579 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2580 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2581 enum port port = dp_to_dig_port(intel_dp)->port;
2582 enum pipe pipe = crtc->pipe;
2583
2584 if (WARN_ON(dp_reg & DP_PORT_EN))
2585 return;
2586
2587 pps_lock(intel_dp);
2588
2589 if (IS_VALLEYVIEW(dev))
2590 vlv_init_panel_power_sequencer(intel_dp);
2591
2592 intel_dp_enable_port(intel_dp);
2593
2594 if (port == PORT_A && IS_GEN5(dev_priv)) {
2595 /*
2596 * Underrun reporting for the other pipe was disabled in
2597 * g4x_pre_enable_dp(). The eDP PLL and port have now been
2598 * enabled, so it's now safe to re-enable underrun reporting.
2599 */
2600 intel_wait_for_vblank_if_active(dev_priv->dev, !pipe);
2601 intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, true);
2602 intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, true);
2603 }
2604
2605 edp_panel_vdd_on(intel_dp);
2606 edp_panel_on(intel_dp);
2607 edp_panel_vdd_off(intel_dp, true);
2608
2609 pps_unlock(intel_dp);
2610
2611 if (IS_VALLEYVIEW(dev)) {
2612 unsigned int lane_mask = 0x0;
2613
2614 if (IS_CHERRYVIEW(dev))
2615 lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);
2616
2617 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2618 lane_mask);
2619 }
2620
2621 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2622 intel_dp_start_link_train(intel_dp);
2623 intel_dp_stop_link_train(intel_dp);
2624
2625 if (crtc->config->has_audio) {
2626 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2627 pipe_name(pipe));
2628 intel_audio_codec_enable(encoder);
2629 }
2630}
2631
2632static void g4x_enable_dp(struct intel_encoder *encoder)
2633{
2634 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2635
2636 intel_enable_dp(encoder);
2637 intel_edp_backlight_on(intel_dp);
2638}
2639
2640static void vlv_enable_dp(struct intel_encoder *encoder)
2641{
2642 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2643
2644 intel_edp_backlight_on(intel_dp);
2645 intel_psr_enable(intel_dp);
2646}
2647
2648static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2649{
2650 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2651 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2652 enum port port = dp_to_dig_port(intel_dp)->port;
2653 enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
2654
2655 intel_dp_prepare(encoder);
2656
2657 if (port == PORT_A && IS_GEN5(dev_priv)) {
2658 /*
2659 * We get FIFO underruns on the other pipe when
2660 * enabling the CPU eDP PLL, and when enabling CPU
2661 * eDP port. We could potentially avoid the PLL
2662 * underrun with a vblank wait just prior to enabling
2663 * the PLL, but that doesn't appear to help the port
2664 * enable case. Just sweep it all under the rug.
2665 */
2666 intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, false);
2667 intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, false);
2668 }
2669
2670 /* Only ilk+ has port A */
2671 if (port == PORT_A)
2672 ironlake_edp_pll_on(intel_dp);
2673}
2674
2675static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2676{
2677 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2678 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2679 enum pipe pipe = intel_dp->pps_pipe;
2680 int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2681
2682 edp_panel_vdd_off_sync(intel_dp);
2683
2684 /*
2685 * VLV seems to get confused when multiple power seqeuencers
2686 * have the same port selected (even if only one has power/vdd
2687 * enabled). The failure manifests as vlv_wait_port_ready() failing
2688 * CHV on the other hand doesn't seem to mind having the same port
2689 * selected in multiple power seqeuencers, but let's clear the
2690 * port select always when logically disconnecting a power sequencer
2691 * from a port.
2692 */
2693 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2694 pipe_name(pipe), port_name(intel_dig_port->port));
2695 I915_WRITE(pp_on_reg, 0);
2696 POSTING_READ(pp_on_reg);
2697
2698 intel_dp->pps_pipe = INVALID_PIPE;
2699}
2700
2701static void vlv_steal_power_sequencer(struct drm_device *dev,
2702 enum pipe pipe)
2703{
2704 struct drm_i915_private *dev_priv = dev->dev_private;
2705 struct intel_encoder *encoder;
2706
2707 lockdep_assert_held(&dev_priv->pps_mutex);
2708
2709 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2710 return;
2711
2712 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2713 base.head) {
2714 struct intel_dp *intel_dp;
2715 enum port port;
2716
2717 if (encoder->type != INTEL_OUTPUT_EDP)
2718 continue;
2719
2720 intel_dp = enc_to_intel_dp(&encoder->base);
2721 port = dp_to_dig_port(intel_dp)->port;
2722
2723 if (intel_dp->pps_pipe != pipe)
2724 continue;
2725
2726 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2727 pipe_name(pipe), port_name(port));
2728
2729 WARN(encoder->base.crtc,
2730 "stealing pipe %c power sequencer from active eDP port %c\n",
2731 pipe_name(pipe), port_name(port));
2732
2733 /* make sure vdd is off before we steal it */
2734 vlv_detach_power_sequencer(intel_dp);
2735 }
2736}
2737
2738static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2739{
2740 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2741 struct intel_encoder *encoder = &intel_dig_port->base;
2742 struct drm_device *dev = encoder->base.dev;
2743 struct drm_i915_private *dev_priv = dev->dev_private;
2744 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2745
2746 lockdep_assert_held(&dev_priv->pps_mutex);
2747
2748 if (!is_edp(intel_dp))
2749 return;
2750
2751 if (intel_dp->pps_pipe == crtc->pipe)
2752 return;
2753
2754 /*
2755 * If another power sequencer was being used on this
2756 * port previously make sure to turn off vdd there while
2757 * we still have control of it.
2758 */
2759 if (intel_dp->pps_pipe != INVALID_PIPE)
2760 vlv_detach_power_sequencer(intel_dp);
2761
2762 /*
2763 * We may be stealing the power
2764 * sequencer from another port.
2765 */
2766 vlv_steal_power_sequencer(dev, crtc->pipe);
2767
2768 /* now it's all ours */
2769 intel_dp->pps_pipe = crtc->pipe;
2770
2771 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2772 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2773
2774 /* init power sequencer on this pipe and port */
2775 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2776 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2777}
2778
2779static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2780{
2781 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2782 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2783 struct drm_device *dev = encoder->base.dev;
2784 struct drm_i915_private *dev_priv = dev->dev_private;
2785 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2786 enum dpio_channel port = vlv_dport_to_channel(dport);
2787 int pipe = intel_crtc->pipe;
2788 u32 val;
2789
2790 mutex_lock(&dev_priv->sb_lock);
2791
2792 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2793 val = 0;
2794 if (pipe)
2795 val |= (1<<21);
2796 else
2797 val &= ~(1<<21);
2798 val |= 0x001000c4;
2799 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2800 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2801 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2802
2803 mutex_unlock(&dev_priv->sb_lock);
2804
2805 intel_enable_dp(encoder);
2806}
2807
2808static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2809{
2810 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2811 struct drm_device *dev = encoder->base.dev;
2812 struct drm_i915_private *dev_priv = dev->dev_private;
2813 struct intel_crtc *intel_crtc =
2814 to_intel_crtc(encoder->base.crtc);
2815 enum dpio_channel port = vlv_dport_to_channel(dport);
2816 int pipe = intel_crtc->pipe;
2817
2818 intel_dp_prepare(encoder);
2819
2820 /* Program Tx lane resets to default */
2821 mutex_lock(&dev_priv->sb_lock);
2822 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2823 DPIO_PCS_TX_LANE2_RESET |
2824 DPIO_PCS_TX_LANE1_RESET);
2825 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2826 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2827 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2828 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2829 DPIO_PCS_CLK_SOFT_RESET);
2830
2831 /* Fix up inter-pair skew failure */
2832 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2833 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2834 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2835 mutex_unlock(&dev_priv->sb_lock);
2836}
2837
2838static void chv_pre_enable_dp(struct intel_encoder *encoder)
2839{
2840 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2841 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2842 struct drm_device *dev = encoder->base.dev;
2843 struct drm_i915_private *dev_priv = dev->dev_private;
2844 struct intel_crtc *intel_crtc =
2845 to_intel_crtc(encoder->base.crtc);
2846 enum dpio_channel ch = vlv_dport_to_channel(dport);
2847 int pipe = intel_crtc->pipe;
2848 int data, i, stagger;
2849 u32 val;
2850
2851 mutex_lock(&dev_priv->sb_lock);
2852
2853 /* allow hardware to manage TX FIFO reset source */
2854 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2855 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2856 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2857
2858 if (intel_crtc->config->lane_count > 2) {
2859 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2860 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2861 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2862 }
2863
2864 /* Program Tx lane latency optimal setting*/
2865 for (i = 0; i < intel_crtc->config->lane_count; i++) {
2866 /* Set the upar bit */
2867 if (intel_crtc->config->lane_count == 1)
2868 data = 0x0;
2869 else
2870 data = (i == 1) ? 0x0 : 0x1;
2871 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2872 data << DPIO_UPAR_SHIFT);
2873 }
2874
2875 /* Data lane stagger programming */
2876 if (intel_crtc->config->port_clock > 270000)
2877 stagger = 0x18;
2878 else if (intel_crtc->config->port_clock > 135000)
2879 stagger = 0xd;
2880 else if (intel_crtc->config->port_clock > 67500)
2881 stagger = 0x7;
2882 else if (intel_crtc->config->port_clock > 33750)
2883 stagger = 0x4;
2884 else
2885 stagger = 0x2;
2886
2887 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2888 val |= DPIO_TX2_STAGGER_MASK(0x1f);
2889 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2890
2891 if (intel_crtc->config->lane_count > 2) {
2892 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2893 val |= DPIO_TX2_STAGGER_MASK(0x1f);
2894 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2895 }
2896
2897 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
2898 DPIO_LANESTAGGER_STRAP(stagger) |
2899 DPIO_LANESTAGGER_STRAP_OVRD |
2900 DPIO_TX1_STAGGER_MASK(0x1f) |
2901 DPIO_TX1_STAGGER_MULT(6) |
2902 DPIO_TX2_STAGGER_MULT(0));
2903
2904 if (intel_crtc->config->lane_count > 2) {
2905 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
2906 DPIO_LANESTAGGER_STRAP(stagger) |
2907 DPIO_LANESTAGGER_STRAP_OVRD |
2908 DPIO_TX1_STAGGER_MASK(0x1f) |
2909 DPIO_TX1_STAGGER_MULT(7) |
2910 DPIO_TX2_STAGGER_MULT(5));
2911 }
2912
2913 /* Deassert data lane reset */
2914 chv_data_lane_soft_reset(encoder, false);
2915
2916 mutex_unlock(&dev_priv->sb_lock);
2917
2918 intel_enable_dp(encoder);
2919
2920 /* Second common lane will stay alive on its own now */
2921 if (dport->release_cl2_override) {
2922 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
2923 dport->release_cl2_override = false;
2924 }
2925}
2926
2927static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2928{
2929 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2930 struct drm_device *dev = encoder->base.dev;
2931 struct drm_i915_private *dev_priv = dev->dev_private;
2932 struct intel_crtc *intel_crtc =
2933 to_intel_crtc(encoder->base.crtc);
2934 enum dpio_channel ch = vlv_dport_to_channel(dport);
2935 enum pipe pipe = intel_crtc->pipe;
2936 unsigned int lane_mask =
2937 intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
2938 u32 val;
2939
2940 intel_dp_prepare(encoder);
2941
2942 /*
2943 * Must trick the second common lane into life.
2944 * Otherwise we can't even access the PLL.
2945 */
2946 if (ch == DPIO_CH0 && pipe == PIPE_B)
2947 dport->release_cl2_override =
2948 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
2949
2950 chv_phy_powergate_lanes(encoder, true, lane_mask);
2951
2952 mutex_lock(&dev_priv->sb_lock);
2953
2954 /* Assert data lane reset */
2955 chv_data_lane_soft_reset(encoder, true);
2956
2957 /* program left/right clock distribution */
2958 if (pipe != PIPE_B) {
2959 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2960 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2961 if (ch == DPIO_CH0)
2962 val |= CHV_BUFLEFTENA1_FORCE;
2963 if (ch == DPIO_CH1)
2964 val |= CHV_BUFRIGHTENA1_FORCE;
2965 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2966 } else {
2967 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2968 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2969 if (ch == DPIO_CH0)
2970 val |= CHV_BUFLEFTENA2_FORCE;
2971 if (ch == DPIO_CH1)
2972 val |= CHV_BUFRIGHTENA2_FORCE;
2973 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2974 }
2975
2976 /* program clock channel usage */
2977 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2978 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2979 if (pipe != PIPE_B)
2980 val &= ~CHV_PCS_USEDCLKCHANNEL;
2981 else
2982 val |= CHV_PCS_USEDCLKCHANNEL;
2983 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2984
2985 if (intel_crtc->config->lane_count > 2) {
2986 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2987 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2988 if (pipe != PIPE_B)
2989 val &= ~CHV_PCS_USEDCLKCHANNEL;
2990 else
2991 val |= CHV_PCS_USEDCLKCHANNEL;
2992 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2993 }
2994
2995 /*
2996 * This a a bit weird since generally CL
2997 * matches the pipe, but here we need to
2998 * pick the CL based on the port.
2999 */
3000 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
3001 if (pipe != PIPE_B)
3002 val &= ~CHV_CMN_USEDCLKCHANNEL;
3003 else
3004 val |= CHV_CMN_USEDCLKCHANNEL;
3005 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
3006
3007 mutex_unlock(&dev_priv->sb_lock);
3008}
3009
3010static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
3011{
3012 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3013 enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
3014 u32 val;
3015
3016 mutex_lock(&dev_priv->sb_lock);
3017
3018 /* disable left/right clock distribution */
3019 if (pipe != PIPE_B) {
3020 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
3021 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
3022 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
3023 } else {
3024 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
3025 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
3026 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
3027 }
3028
3029 mutex_unlock(&dev_priv->sb_lock);
3030
3031 /*
3032 * Leave the power down bit cleared for at least one
3033 * lane so that chv_powergate_phy_ch() will power
3034 * on something when the channel is otherwise unused.
3035 * When the port is off and the override is removed
3036 * the lanes power down anyway, so otherwise it doesn't
3037 * really matter what the state of power down bits is
3038 * after this.
3039 */
3040 chv_phy_powergate_lanes(encoder, false, 0x0);
3041}
3042
3043/*
3044 * Native read with retry for link status and receiver capability reads for
3045 * cases where the sink may still be asleep.
3046 *
3047 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
3048 * supposed to retry 3 times per the spec.
3049 */
3050static ssize_t
3051intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
3052 void *buffer, size_t size)
3053{
3054 ssize_t ret;
3055 int i;
3056
3057 /*
3058 * Sometime we just get the same incorrect byte repeated
3059 * over the entire buffer. Doing just one throw away read
3060 * initially seems to "solve" it.
3061 */
3062 drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
3063
3064 for (i = 0; i < 3; i++) {
3065 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
3066 if (ret == size)
3067 return ret;
3068 msleep(1);
3069 }
3070
3071 return ret;
3072}
3073
3074/*
3075 * Fetch AUX CH registers 0x202 - 0x207 which contain
3076 * link status information
3077 */
3078bool
3079intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3080{
3081 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3082 DP_LANE0_1_STATUS,
3083 link_status,
3084 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3085}
3086
3087/* These are source-specific values. */
3088uint8_t
3089intel_dp_voltage_max(struct intel_dp *intel_dp)
3090{
3091 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3092 struct drm_i915_private *dev_priv = dev->dev_private;
3093 enum port port = dp_to_dig_port(intel_dp)->port;
3094
3095 if (IS_BROXTON(dev))
3096 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3097 else if (INTEL_INFO(dev)->gen >= 9) {
3098 if (dev_priv->edp_low_vswing && port == PORT_A)
3099 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3100 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3101 } else if (IS_VALLEYVIEW(dev))
3102 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3103 else if (IS_GEN7(dev) && port == PORT_A)
3104 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3105 else if (HAS_PCH_CPT(dev) && port != PORT_A)
3106 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3107 else
3108 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3109}
3110
3111uint8_t
3112intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3113{
3114 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3115 enum port port = dp_to_dig_port(intel_dp)->port;
3116
3117 if (INTEL_INFO(dev)->gen >= 9) {
3118 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3119 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3120 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3121 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3122 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3123 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3124 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3125 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3126 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3127 default:
3128 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3129 }
3130 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3131 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3132 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3133 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3134 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3135 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3136 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3137 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3138 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3139 default:
3140 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3141 }
3142 } else if (IS_VALLEYVIEW(dev)) {
3143 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3144 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3145 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3146 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3147 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3148 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3149 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3150 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3151 default:
3152 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3153 }
3154 } else if (IS_GEN7(dev) && port == PORT_A) {
3155 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3156 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3157 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3158 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3159 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3160 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3161 default:
3162 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3163 }
3164 } else {
3165 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3166 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3167 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3168 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3169 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3170 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3171 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3172 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3173 default:
3174 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3175 }
3176 }
3177}
3178
3179static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3180{
3181 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3182 struct drm_i915_private *dev_priv = dev->dev_private;
3183 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3184 struct intel_crtc *intel_crtc =
3185 to_intel_crtc(dport->base.base.crtc);
3186 unsigned long demph_reg_value, preemph_reg_value,
3187 uniqtranscale_reg_value;
3188 uint8_t train_set = intel_dp->train_set[0];
3189 enum dpio_channel port = vlv_dport_to_channel(dport);
3190 int pipe = intel_crtc->pipe;
3191
3192 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3193 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3194 preemph_reg_value = 0x0004000;
3195 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3196 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3197 demph_reg_value = 0x2B405555;
3198 uniqtranscale_reg_value = 0x552AB83A;
3199 break;
3200 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3201 demph_reg_value = 0x2B404040;
3202 uniqtranscale_reg_value = 0x5548B83A;
3203 break;
3204 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3205 demph_reg_value = 0x2B245555;
3206 uniqtranscale_reg_value = 0x5560B83A;
3207 break;
3208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3209 demph_reg_value = 0x2B405555;
3210 uniqtranscale_reg_value = 0x5598DA3A;
3211 break;
3212 default:
3213 return 0;
3214 }
3215 break;
3216 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3217 preemph_reg_value = 0x0002000;
3218 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3220 demph_reg_value = 0x2B404040;
3221 uniqtranscale_reg_value = 0x5552B83A;
3222 break;
3223 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3224 demph_reg_value = 0x2B404848;
3225 uniqtranscale_reg_value = 0x5580B83A;
3226 break;
3227 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3228 demph_reg_value = 0x2B404040;
3229 uniqtranscale_reg_value = 0x55ADDA3A;
3230 break;
3231 default:
3232 return 0;
3233 }
3234 break;
3235 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3236 preemph_reg_value = 0x0000000;
3237 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3238 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3239 demph_reg_value = 0x2B305555;
3240 uniqtranscale_reg_value = 0x5570B83A;
3241 break;
3242 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3243 demph_reg_value = 0x2B2B4040;
3244 uniqtranscale_reg_value = 0x55ADDA3A;
3245 break;
3246 default:
3247 return 0;
3248 }
3249 break;
3250 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3251 preemph_reg_value = 0x0006000;
3252 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3253 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3254 demph_reg_value = 0x1B405555;
3255 uniqtranscale_reg_value = 0x55ADDA3A;
3256 break;
3257 default:
3258 return 0;
3259 }
3260 break;
3261 default:
3262 return 0;
3263 }
3264
3265 mutex_lock(&dev_priv->sb_lock);
3266 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3267 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3268 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
3269 uniqtranscale_reg_value);
3270 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3271 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3272 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3273 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
3274 mutex_unlock(&dev_priv->sb_lock);
3275
3276 return 0;
3277}
3278
3279static bool chv_need_uniq_trans_scale(uint8_t train_set)
3280{
3281 return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 &&
3282 (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3283}
3284
3285static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3286{
3287 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3288 struct drm_i915_private *dev_priv = dev->dev_private;
3289 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3290 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
3291 u32 deemph_reg_value, margin_reg_value, val;
3292 uint8_t train_set = intel_dp->train_set[0];
3293 enum dpio_channel ch = vlv_dport_to_channel(dport);
3294 enum pipe pipe = intel_crtc->pipe;
3295 int i;
3296
3297 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3298 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3299 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3300 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3301 deemph_reg_value = 128;
3302 margin_reg_value = 52;
3303 break;
3304 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3305 deemph_reg_value = 128;
3306 margin_reg_value = 77;
3307 break;
3308 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3309 deemph_reg_value = 128;
3310 margin_reg_value = 102;
3311 break;
3312 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3313 deemph_reg_value = 128;
3314 margin_reg_value = 154;
3315 /* FIXME extra to set for 1200 */
3316 break;
3317 default:
3318 return 0;
3319 }
3320 break;
3321 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3322 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3323 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3324 deemph_reg_value = 85;
3325 margin_reg_value = 78;
3326 break;
3327 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3328 deemph_reg_value = 85;
3329 margin_reg_value = 116;
3330 break;
3331 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3332 deemph_reg_value = 85;
3333 margin_reg_value = 154;
3334 break;
3335 default:
3336 return 0;
3337 }
3338 break;
3339 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3340 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3341 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3342 deemph_reg_value = 64;
3343 margin_reg_value = 104;
3344 break;
3345 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3346 deemph_reg_value = 64;
3347 margin_reg_value = 154;
3348 break;
3349 default:
3350 return 0;
3351 }
3352 break;
3353 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3354 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3355 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3356 deemph_reg_value = 43;
3357 margin_reg_value = 154;
3358 break;
3359 default:
3360 return 0;
3361 }
3362 break;
3363 default:
3364 return 0;
3365 }
3366
3367 mutex_lock(&dev_priv->sb_lock);
3368
3369 /* Clear calc init */
3370 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3371 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3372 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3373 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3374 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3375
3376 if (intel_crtc->config->lane_count > 2) {
3377 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3378 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3379 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3380 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3381 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3382 }
3383
3384 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3385 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3386 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3387 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3388
3389 if (intel_crtc->config->lane_count > 2) {
3390 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3391 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3392 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3393 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3394 }
3395
3396 /* Program swing deemph */
3397 for (i = 0; i < intel_crtc->config->lane_count; i++) {
3398 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3399 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3400 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3401 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3402 }
3403
3404 /* Program swing margin */
3405 for (i = 0; i < intel_crtc->config->lane_count; i++) {
3406 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3407
3408 val &= ~DPIO_SWING_MARGIN000_MASK;
3409 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
3410
3411 /*
3412 * Supposedly this value shouldn't matter when unique transition
3413 * scale is disabled, but in fact it does matter. Let's just
3414 * always program the same value and hope it's OK.
3415 */
3416 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3417 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
3418
3419 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3420 }
3421
3422 /*
3423 * The document said it needs to set bit 27 for ch0 and bit 26
3424 * for ch1. Might be a typo in the doc.
3425 * For now, for this unique transition scale selection, set bit
3426 * 27 for ch0 and ch1.
3427 */
3428 for (i = 0; i < intel_crtc->config->lane_count; i++) {
3429 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3430 if (chv_need_uniq_trans_scale(train_set))
3431 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3432 else
3433 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3434 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3435 }
3436
3437 /* Start swing calculation */
3438 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3439 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3440 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3441
3442 if (intel_crtc->config->lane_count > 2) {
3443 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3444 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3445 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3446 }
3447
3448 mutex_unlock(&dev_priv->sb_lock);
3449
3450 return 0;
3451}
3452
3453static uint32_t
3454gen4_signal_levels(uint8_t train_set)
3455{
3456 uint32_t signal_levels = 0;
3457
3458 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3459 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3460 default:
3461 signal_levels |= DP_VOLTAGE_0_4;
3462 break;
3463 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3464 signal_levels |= DP_VOLTAGE_0_6;
3465 break;
3466 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3467 signal_levels |= DP_VOLTAGE_0_8;
3468 break;
3469 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3470 signal_levels |= DP_VOLTAGE_1_2;
3471 break;
3472 }
3473 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3474 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3475 default:
3476 signal_levels |= DP_PRE_EMPHASIS_0;
3477 break;
3478 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3479 signal_levels |= DP_PRE_EMPHASIS_3_5;
3480 break;
3481 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3482 signal_levels |= DP_PRE_EMPHASIS_6;
3483 break;
3484 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3485 signal_levels |= DP_PRE_EMPHASIS_9_5;
3486 break;
3487 }
3488 return signal_levels;
3489}
3490
3491/* Gen6's DP voltage swing and pre-emphasis control */
3492static uint32_t
3493gen6_edp_signal_levels(uint8_t train_set)
3494{
3495 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3496 DP_TRAIN_PRE_EMPHASIS_MASK);
3497 switch (signal_levels) {
3498 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3499 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3500 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3501 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3502 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3503 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3504 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3505 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3506 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3507 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3508 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3509 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3510 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3511 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3512 default:
3513 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3514 "0x%x\n", signal_levels);
3515 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3516 }
3517}
3518
3519/* Gen7's DP voltage swing and pre-emphasis control */
3520static uint32_t
3521gen7_edp_signal_levels(uint8_t train_set)
3522{
3523 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3524 DP_TRAIN_PRE_EMPHASIS_MASK);
3525 switch (signal_levels) {
3526 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3527 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3528 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3529 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3530 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3531 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3532
3533 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3534 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3535 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3536 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3537
3538 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3539 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3540 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3541 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3542
3543 default:
3544 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3545 "0x%x\n", signal_levels);
3546 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3547 }
3548}
3549
3550void
3551intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3552{
3553 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3554 enum port port = intel_dig_port->port;
3555 struct drm_device *dev = intel_dig_port->base.base.dev;
3556 struct drm_i915_private *dev_priv = to_i915(dev);
3557 uint32_t signal_levels, mask = 0;
3558 uint8_t train_set = intel_dp->train_set[0];
3559
3560 if (HAS_DDI(dev)) {
3561 signal_levels = ddi_signal_levels(intel_dp);
3562
3563 if (IS_BROXTON(dev))
3564 signal_levels = 0;
3565 else
3566 mask = DDI_BUF_EMP_MASK;
3567 } else if (IS_CHERRYVIEW(dev)) {
3568 signal_levels = chv_signal_levels(intel_dp);
3569 } else if (IS_VALLEYVIEW(dev)) {
3570 signal_levels = vlv_signal_levels(intel_dp);
3571 } else if (IS_GEN7(dev) && port == PORT_A) {
3572 signal_levels = gen7_edp_signal_levels(train_set);
3573 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3574 } else if (IS_GEN6(dev) && port == PORT_A) {
3575 signal_levels = gen6_edp_signal_levels(train_set);
3576 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3577 } else {
3578 signal_levels = gen4_signal_levels(train_set);
3579 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3580 }
3581
3582 if (mask)
3583 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3584
3585 DRM_DEBUG_KMS("Using vswing level %d\n",
3586 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3587 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3588 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3589 DP_TRAIN_PRE_EMPHASIS_SHIFT);
3590
3591 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3592
3593 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3594 POSTING_READ(intel_dp->output_reg);
3595}
3596
3597void
3598intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3599 uint8_t dp_train_pat)
3600{
3601 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3602 struct drm_i915_private *dev_priv =
3603 to_i915(intel_dig_port->base.base.dev);
3604
3605 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3606
3607 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3608 POSTING_READ(intel_dp->output_reg);
3609}
3610
3611void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3612{
3613 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3614 struct drm_device *dev = intel_dig_port->base.base.dev;
3615 struct drm_i915_private *dev_priv = dev->dev_private;
3616 enum port port = intel_dig_port->port;
3617 uint32_t val;
3618
3619 if (!HAS_DDI(dev))
3620 return;
3621
3622 val = I915_READ(DP_TP_CTL(port));
3623 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3624 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3625 I915_WRITE(DP_TP_CTL(port), val);
3626
3627 /*
3628 * On PORT_A we can have only eDP in SST mode. There the only reason
3629 * we need to set idle transmission mode is to work around a HW issue
3630 * where we enable the pipe while not in idle link-training mode.
3631 * In this case there is requirement to wait for a minimum number of
3632 * idle patterns to be sent.
3633 */
3634 if (port == PORT_A)
3635 return;
3636
3637 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3638 1))
3639 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3640}
3641
3642static void
3643intel_dp_link_down(struct intel_dp *intel_dp)
3644{
3645 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3646 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3647 enum port port = intel_dig_port->port;
3648 struct drm_device *dev = intel_dig_port->base.base.dev;
3649 struct drm_i915_private *dev_priv = dev->dev_private;
3650 uint32_t DP = intel_dp->DP;
3651
3652 if (WARN_ON(HAS_DDI(dev)))
3653 return;
3654
3655 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3656 return;
3657
3658 DRM_DEBUG_KMS("\n");
3659
3660 if ((IS_GEN7(dev) && port == PORT_A) ||
3661 (HAS_PCH_CPT(dev) && port != PORT_A)) {
3662 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3663 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3664 } else {
3665 if (IS_CHERRYVIEW(dev))
3666 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3667 else
3668 DP &= ~DP_LINK_TRAIN_MASK;
3669 DP |= DP_LINK_TRAIN_PAT_IDLE;
3670 }
3671 I915_WRITE(intel_dp->output_reg, DP);
3672 POSTING_READ(intel_dp->output_reg);
3673
3674 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3675 I915_WRITE(intel_dp->output_reg, DP);
3676 POSTING_READ(intel_dp->output_reg);
3677
3678 /*
3679 * HW workaround for IBX, we need to move the port
3680 * to transcoder A after disabling it to allow the
3681 * matching HDMI port to be enabled on transcoder A.
3682 */
3683 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
3684 /*
3685 * We get CPU/PCH FIFO underruns on the other pipe when
3686 * doing the workaround. Sweep them under the rug.
3687 */
3688 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3689 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3690
3691 /* always enable with pattern 1 (as per spec) */
3692 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3693 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3694 I915_WRITE(intel_dp->output_reg, DP);
3695 POSTING_READ(intel_dp->output_reg);
3696
3697 DP &= ~DP_PORT_EN;
3698 I915_WRITE(intel_dp->output_reg, DP);
3699 POSTING_READ(intel_dp->output_reg);
3700
3701 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
3702 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3703 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3704 }
3705
3706 msleep(intel_dp->panel_power_down_delay);
3707
3708 intel_dp->DP = DP;
3709}
3710
3711static bool
3712intel_dp_get_dpcd(struct intel_dp *intel_dp)
3713{
3714 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3715 struct drm_device *dev = dig_port->base.base.dev;
3716 struct drm_i915_private *dev_priv = dev->dev_private;
3717 uint8_t rev;
3718
3719 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3720 sizeof(intel_dp->dpcd)) < 0)
3721 return false; /* aux transfer failed */
3722
3723 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3724
3725 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3726 return false; /* DPCD not present */
3727
3728 /* Check if the panel supports PSR */
3729 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3730 if (is_edp(intel_dp)) {
3731 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3732 intel_dp->psr_dpcd,
3733 sizeof(intel_dp->psr_dpcd));
3734 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3735 dev_priv->psr.sink_support = true;
3736 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3737 }
3738
3739 if (INTEL_INFO(dev)->gen >= 9 &&
3740 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3741 uint8_t frame_sync_cap;
3742
3743 dev_priv->psr.sink_support = true;
3744 intel_dp_dpcd_read_wake(&intel_dp->aux,
3745 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3746 &frame_sync_cap, 1);
3747 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3748 /* PSR2 needs frame sync as well */
3749 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3750 DRM_DEBUG_KMS("PSR2 %s on sink",
3751 dev_priv->psr.psr2_support ? "supported" : "not supported");
3752 }
3753 }
3754
3755 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
3756 yesno(intel_dp_source_supports_hbr2(intel_dp)),
3757 yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
3758
3759 /* Intermediate frequency support */
3760 if (is_edp(intel_dp) &&
3761 (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3762 (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
3763 (rev >= 0x03)) { /* eDp v1.4 or higher */
3764 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3765 int i;
3766
3767 intel_dp_dpcd_read_wake(&intel_dp->aux,
3768 DP_SUPPORTED_LINK_RATES,
3769 sink_rates,
3770 sizeof(sink_rates));
3771
3772 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3773 int val = le16_to_cpu(sink_rates[i]);
3774
3775 if (val == 0)
3776 break;
3777
3778 /* Value read is in kHz while drm clock is saved in deca-kHz */
3779 intel_dp->sink_rates[i] = (val * 200) / 10;
3780 }
3781 intel_dp->num_sink_rates = i;
3782 }
3783
3784 intel_dp_print_rates(intel_dp);
3785
3786 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3787 DP_DWN_STRM_PORT_PRESENT))
3788 return true; /* native DP sink */
3789
3790 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3791 return true; /* no per-port downstream info */
3792
3793 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3794 intel_dp->downstream_ports,
3795 DP_MAX_DOWNSTREAM_PORTS) < 0)
3796 return false; /* downstream port status fetch failed */
3797
3798 return true;
3799}
3800
3801static void
3802intel_dp_probe_oui(struct intel_dp *intel_dp)
3803{
3804 u8 buf[3];
3805
3806 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3807 return;
3808
3809 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3810 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3811 buf[0], buf[1], buf[2]);
3812
3813 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3814 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3815 buf[0], buf[1], buf[2]);
3816}
3817
3818static bool
3819intel_dp_probe_mst(struct intel_dp *intel_dp)
3820{
3821 u8 buf[1];
3822
3823 if (!intel_dp->can_mst)
3824 return false;
3825
3826 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3827 return false;
3828
3829 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3830 if (buf[0] & DP_MST_CAP) {
3831 DRM_DEBUG_KMS("Sink is MST capable\n");
3832 intel_dp->is_mst = true;
3833 } else {
3834 DRM_DEBUG_KMS("Sink is not MST capable\n");
3835 intel_dp->is_mst = false;
3836 }
3837 }
3838
3839 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3840 return intel_dp->is_mst;
3841}
3842
3843static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3844{
3845 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3846 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3847 u8 buf;
3848 int ret = 0;
3849
3850 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3851 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3852 ret = -EIO;
3853 goto out;
3854 }
3855
3856 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3857 buf & ~DP_TEST_SINK_START) < 0) {
3858 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3859 ret = -EIO;
3860 goto out;
3861 }
3862
3863 intel_dp->sink_crc.started = false;
3864 out:
3865 hsw_enable_ips(intel_crtc);
3866 return ret;
3867}
3868
3869static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3870{
3871 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3872 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3873 u8 buf;
3874 int ret;
3875
3876 if (intel_dp->sink_crc.started) {
3877 ret = intel_dp_sink_crc_stop(intel_dp);
3878 if (ret)
3879 return ret;
3880 }
3881
3882 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3883 return -EIO;
3884
3885 if (!(buf & DP_TEST_CRC_SUPPORTED))
3886 return -ENOTTY;
3887
3888 intel_dp->sink_crc.last_count = buf & DP_TEST_COUNT_MASK;
3889
3890 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3891 return -EIO;
3892
3893 hsw_disable_ips(intel_crtc);
3894
3895 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3896 buf | DP_TEST_SINK_START) < 0) {
3897 hsw_enable_ips(intel_crtc);
3898 return -EIO;
3899 }
3900
3901 intel_dp->sink_crc.started = true;
3902 return 0;
3903}
3904
3905int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3906{
3907 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3908 struct drm_device *dev = dig_port->base.base.dev;
3909 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3910 u8 buf;
3911 int count, ret;
3912 int attempts = 6;
3913 bool old_equal_new;
3914
3915 ret = intel_dp_sink_crc_start(intel_dp);
3916 if (ret)
3917 return ret;
3918
3919 do {
3920 intel_wait_for_vblank(dev, intel_crtc->pipe);
3921
3922 if (drm_dp_dpcd_readb(&intel_dp->aux,
3923 DP_TEST_SINK_MISC, &buf) < 0) {
3924 ret = -EIO;
3925 goto stop;
3926 }
3927 count = buf & DP_TEST_COUNT_MASK;
3928
3929 /*
3930 * Count might be reset during the loop. In this case
3931 * last known count needs to be reset as well.
3932 */
3933 if (count == 0)
3934 intel_dp->sink_crc.last_count = 0;
3935
3936 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3937 ret = -EIO;
3938 goto stop;
3939 }
3940
3941 old_equal_new = (count == intel_dp->sink_crc.last_count &&
3942 !memcmp(intel_dp->sink_crc.last_crc, crc,
3943 6 * sizeof(u8)));
3944
3945 } while (--attempts && (count == 0 || old_equal_new));
3946
3947 intel_dp->sink_crc.last_count = buf & DP_TEST_COUNT_MASK;
3948 memcpy(intel_dp->sink_crc.last_crc, crc, 6 * sizeof(u8));
3949
3950 if (attempts == 0) {
3951 if (old_equal_new) {
3952 DRM_DEBUG_KMS("Unreliable Sink CRC counter: Current returned CRC is identical to the previous one\n");
3953 } else {
3954 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3955 ret = -ETIMEDOUT;
3956 goto stop;
3957 }
3958 }
3959
3960stop:
3961 intel_dp_sink_crc_stop(intel_dp);
3962 return ret;
3963}
3964
3965static bool
3966intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3967{
3968 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3969 DP_DEVICE_SERVICE_IRQ_VECTOR,
3970 sink_irq_vector, 1) == 1;
3971}
3972
3973static bool
3974intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3975{
3976 int ret;
3977
3978 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3979 DP_SINK_COUNT_ESI,
3980 sink_irq_vector, 14);
3981 if (ret != 14)
3982 return false;
3983
3984 return true;
3985}
3986
3987static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3988{
3989 uint8_t test_result = DP_TEST_ACK;
3990 return test_result;
3991}
3992
3993static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3994{
3995 uint8_t test_result = DP_TEST_NAK;
3996 return test_result;
3997}
3998
3999static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4000{
4001 uint8_t test_result = DP_TEST_NAK;
4002 struct intel_connector *intel_connector = intel_dp->attached_connector;
4003 struct drm_connector *connector = &intel_connector->base;
4004
4005 if (intel_connector->detect_edid == NULL ||
4006 connector->edid_corrupt ||
4007 intel_dp->aux.i2c_defer_count > 6) {
4008 /* Check EDID read for NACKs, DEFERs and corruption
4009 * (DP CTS 1.2 Core r1.1)
4010 * 4.2.2.4 : Failed EDID read, I2C_NAK
4011 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4012 * 4.2.2.6 : EDID corruption detected
4013 * Use failsafe mode for all cases
4014 */
4015 if (intel_dp->aux.i2c_nack_count > 0 ||
4016 intel_dp->aux.i2c_defer_count > 0)
4017 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4018 intel_dp->aux.i2c_nack_count,
4019 intel_dp->aux.i2c_defer_count);
4020 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
4021 } else {
4022 struct edid *block = intel_connector->detect_edid;
4023
4024 /* We have to write the checksum
4025 * of the last block read
4026 */
4027 block += intel_connector->detect_edid->extensions;
4028
4029 if (!drm_dp_dpcd_write(&intel_dp->aux,
4030 DP_TEST_EDID_CHECKSUM,
4031 &block->checksum,
4032 1))
4033 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4034
4035 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4036 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
4037 }
4038
4039 /* Set test active flag here so userspace doesn't interrupt things */
4040 intel_dp->compliance_test_active = 1;
4041
4042 return test_result;
4043}
4044
4045static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4046{
4047 uint8_t test_result = DP_TEST_NAK;
4048 return test_result;
4049}
4050
4051static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4052{
4053 uint8_t response = DP_TEST_NAK;
4054 uint8_t rxdata = 0;
4055 int status = 0;
4056
4057 intel_dp->compliance_test_active = 0;
4058 intel_dp->compliance_test_type = 0;
4059 intel_dp->compliance_test_data = 0;
4060
4061 intel_dp->aux.i2c_nack_count = 0;
4062 intel_dp->aux.i2c_defer_count = 0;
4063
4064 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
4065 if (status <= 0) {
4066 DRM_DEBUG_KMS("Could not read test request from sink\n");
4067 goto update_status;
4068 }
4069
4070 switch (rxdata) {
4071 case DP_TEST_LINK_TRAINING:
4072 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4073 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
4074 response = intel_dp_autotest_link_training(intel_dp);
4075 break;
4076 case DP_TEST_LINK_VIDEO_PATTERN:
4077 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4078 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
4079 response = intel_dp_autotest_video_pattern(intel_dp);
4080 break;
4081 case DP_TEST_LINK_EDID_READ:
4082 DRM_DEBUG_KMS("EDID test requested\n");
4083 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
4084 response = intel_dp_autotest_edid(intel_dp);
4085 break;
4086 case DP_TEST_LINK_PHY_TEST_PATTERN:
4087 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4088 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
4089 response = intel_dp_autotest_phy_pattern(intel_dp);
4090 break;
4091 default:
4092 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
4093 break;
4094 }
4095
4096update_status:
4097 status = drm_dp_dpcd_write(&intel_dp->aux,
4098 DP_TEST_RESPONSE,
4099 &response, 1);
4100 if (status <= 0)
4101 DRM_DEBUG_KMS("Could not write test response to sink\n");
4102}
4103
4104static int
4105intel_dp_check_mst_status(struct intel_dp *intel_dp)
4106{
4107 bool bret;
4108
4109 if (intel_dp->is_mst) {
4110 u8 esi[16] = { 0 };
4111 int ret = 0;
4112 int retry;
4113 bool handled;
4114 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4115go_again:
4116 if (bret == true) {
4117
4118 /* check link status - esi[10] = 0x200c */
4119 if (intel_dp->active_mst_links &&
4120 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4121 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4122 intel_dp_start_link_train(intel_dp);
4123 intel_dp_stop_link_train(intel_dp);
4124 }
4125
4126 DRM_DEBUG_KMS("got esi %3ph\n", esi);
4127 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4128
4129 if (handled) {
4130 for (retry = 0; retry < 3; retry++) {
4131 int wret;
4132 wret = drm_dp_dpcd_write(&intel_dp->aux,
4133 DP_SINK_COUNT_ESI+1,
4134 &esi[1], 3);
4135 if (wret == 3) {
4136 break;
4137 }
4138 }
4139
4140 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4141 if (bret == true) {
4142 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4143 goto go_again;
4144 }
4145 } else
4146 ret = 0;
4147
4148 return ret;
4149 } else {
4150 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4151 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4152 intel_dp->is_mst = false;
4153 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4154 /* send a hotplug event */
4155 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4156 }
4157 }
4158 return -EINVAL;
4159}
4160
4161/*
4162 * According to DP spec
4163 * 5.1.2:
4164 * 1. Read DPCD
4165 * 2. Configure link according to Receiver Capabilities
4166 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4167 * 4. Check link status on receipt of hot-plug interrupt
4168 */
4169static void
4170intel_dp_check_link_status(struct intel_dp *intel_dp)
4171{
4172 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4173 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4174 u8 sink_irq_vector;
4175 u8 link_status[DP_LINK_STATUS_SIZE];
4176
4177 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4178
4179 if (!intel_encoder->base.crtc)
4180 return;
4181
4182 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4183 return;
4184
4185 /* Try to read receiver status if the link appears to be up */
4186 if (!intel_dp_get_link_status(intel_dp, link_status)) {
4187 return;
4188 }
4189
4190 /* Now read the DPCD to see if it's actually running */
4191 if (!intel_dp_get_dpcd(intel_dp)) {
4192 return;
4193 }
4194
4195 /* Try to read the source of the interrupt */
4196 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4197 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4198 /* Clear interrupt source */
4199 drm_dp_dpcd_writeb(&intel_dp->aux,
4200 DP_DEVICE_SERVICE_IRQ_VECTOR,
4201 sink_irq_vector);
4202
4203 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4204 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4205 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4206 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4207 }
4208
4209 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4210 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4211 intel_encoder->base.name);
4212 intel_dp_start_link_train(intel_dp);
4213 intel_dp_stop_link_train(intel_dp);
4214 }
4215}
4216
4217/* XXX this is probably wrong for multiple downstream ports */
4218static enum drm_connector_status
4219intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4220{
4221 uint8_t *dpcd = intel_dp->dpcd;
4222 uint8_t type;
4223
4224 if (!intel_dp_get_dpcd(intel_dp))
4225 return connector_status_disconnected;
4226
4227 /* if there's no downstream port, we're done */
4228 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
4229 return connector_status_connected;
4230
4231 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4232 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4233 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4234 uint8_t reg;
4235
4236 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4237 &reg, 1) < 0)
4238 return connector_status_unknown;
4239
4240 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4241 : connector_status_disconnected;
4242 }
4243
4244 /* If no HPD, poke DDC gently */
4245 if (drm_probe_ddc(&intel_dp->aux.ddc))
4246 return connector_status_connected;
4247
4248 /* Well we tried, say unknown for unreliable port types */
4249 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4250 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4251 if (type == DP_DS_PORT_TYPE_VGA ||
4252 type == DP_DS_PORT_TYPE_NON_EDID)
4253 return connector_status_unknown;
4254 } else {
4255 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4256 DP_DWN_STRM_PORT_TYPE_MASK;
4257 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4258 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4259 return connector_status_unknown;
4260 }
4261
4262 /* Anything else is out of spec, warn and ignore */
4263 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4264 return connector_status_disconnected;
4265}
4266
4267static enum drm_connector_status
4268edp_detect(struct intel_dp *intel_dp)
4269{
4270 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4271 enum drm_connector_status status;
4272
4273 status = intel_panel_detect(dev);
4274 if (status == connector_status_unknown)
4275 status = connector_status_connected;
4276
4277 return status;
4278}
4279
4280static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4281 struct intel_digital_port *port)
4282{
4283 u32 bit;
4284
4285 switch (port->port) {
4286 case PORT_A:
4287 return true;
4288 case PORT_B:
4289 bit = SDE_PORTB_HOTPLUG;
4290 break;
4291 case PORT_C:
4292 bit = SDE_PORTC_HOTPLUG;
4293 break;
4294 case PORT_D:
4295 bit = SDE_PORTD_HOTPLUG;
4296 break;
4297 default:
4298 MISSING_CASE(port->port);
4299 return false;
4300 }
4301
4302 return I915_READ(SDEISR) & bit;
4303}
4304
4305static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4306 struct intel_digital_port *port)
4307{
4308 u32 bit;
4309
4310 switch (port->port) {
4311 case PORT_A:
4312 return true;
4313 case PORT_B:
4314 bit = SDE_PORTB_HOTPLUG_CPT;
4315 break;
4316 case PORT_C:
4317 bit = SDE_PORTC_HOTPLUG_CPT;
4318 break;
4319 case PORT_D:
4320 bit = SDE_PORTD_HOTPLUG_CPT;
4321 break;
4322 case PORT_E:
4323 bit = SDE_PORTE_HOTPLUG_SPT;
4324 break;
4325 default:
4326 MISSING_CASE(port->port);
4327 return false;
4328 }
4329
4330 return I915_READ(SDEISR) & bit;
4331}
4332
4333static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4334 struct intel_digital_port *port)
4335{
4336 u32 bit;
4337
4338 switch (port->port) {
4339 case PORT_B:
4340 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4341 break;
4342 case PORT_C:
4343 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4344 break;
4345 case PORT_D:
4346 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4347 break;
4348 default:
4349 MISSING_CASE(port->port);
4350 return false;
4351 }
4352
4353 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4354}
4355
4356static bool vlv_digital_port_connected(struct drm_i915_private *dev_priv,
4357 struct intel_digital_port *port)
4358{
4359 u32 bit;
4360
4361 switch (port->port) {
4362 case PORT_B:
4363 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4364 break;
4365 case PORT_C:
4366 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4367 break;
4368 case PORT_D:
4369 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4370 break;
4371 default:
4372 MISSING_CASE(port->port);
4373 return false;
4374 }
4375
4376 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4377}
4378
4379static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4380 struct intel_digital_port *intel_dig_port)
4381{
4382 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4383 enum port port;
4384 u32 bit;
4385
4386 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4387 switch (port) {
4388 case PORT_A:
4389 bit = BXT_DE_PORT_HP_DDIA;
4390 break;
4391 case PORT_B:
4392 bit = BXT_DE_PORT_HP_DDIB;
4393 break;
4394 case PORT_C:
4395 bit = BXT_DE_PORT_HP_DDIC;
4396 break;
4397 default:
4398 MISSING_CASE(port);
4399 return false;
4400 }
4401
4402 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4403}
4404
4405/*
4406 * intel_digital_port_connected - is the specified port connected?
4407 * @dev_priv: i915 private structure
4408 * @port: the port to test
4409 *
4410 * Return %true if @port is connected, %false otherwise.
4411 */
4412bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4413 struct intel_digital_port *port)
4414{
4415 if (HAS_PCH_IBX(dev_priv))
4416 return ibx_digital_port_connected(dev_priv, port);
4417 if (HAS_PCH_SPLIT(dev_priv))
4418 return cpt_digital_port_connected(dev_priv, port);
4419 else if (IS_BROXTON(dev_priv))
4420 return bxt_digital_port_connected(dev_priv, port);
4421 else if (IS_VALLEYVIEW(dev_priv))
4422 return vlv_digital_port_connected(dev_priv, port);
4423 else
4424 return g4x_digital_port_connected(dev_priv, port);
4425}
4426
4427static enum drm_connector_status
4428ironlake_dp_detect(struct intel_dp *intel_dp)
4429{
4430 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4431 struct drm_i915_private *dev_priv = dev->dev_private;
4432 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4433
4434 if (!intel_digital_port_connected(dev_priv, intel_dig_port))
4435 return connector_status_disconnected;
4436
4437 return intel_dp_detect_dpcd(intel_dp);
4438}
4439
4440static enum drm_connector_status
4441g4x_dp_detect(struct intel_dp *intel_dp)
4442{
4443 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4444 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4445
4446 /* Can't disconnect eDP, but you can close the lid... */
4447 if (is_edp(intel_dp)) {
4448 enum drm_connector_status status;
4449
4450 status = intel_panel_detect(dev);
4451 if (status == connector_status_unknown)
4452 status = connector_status_connected;
4453 return status;
4454 }
4455
4456 if (!intel_digital_port_connected(dev->dev_private, intel_dig_port))
4457 return connector_status_disconnected;
4458
4459 return intel_dp_detect_dpcd(intel_dp);
4460}
4461
4462static struct edid *
4463intel_dp_get_edid(struct intel_dp *intel_dp)
4464{
4465 struct intel_connector *intel_connector = intel_dp->attached_connector;
4466
4467 /* use cached edid if we have one */
4468 if (intel_connector->edid) {
4469 /* invalid edid */
4470 if (IS_ERR(intel_connector->edid))
4471 return NULL;
4472
4473 return drm_edid_duplicate(intel_connector->edid);
4474 } else
4475 return drm_get_edid(&intel_connector->base,
4476 &intel_dp->aux.ddc);
4477}
4478
4479static void
4480intel_dp_set_edid(struct intel_dp *intel_dp)
4481{
4482 struct intel_connector *intel_connector = intel_dp->attached_connector;
4483 struct edid *edid;
4484
4485 edid = intel_dp_get_edid(intel_dp);
4486 intel_connector->detect_edid = edid;
4487
4488 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4489 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4490 else
4491 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4492}
4493
4494static void
4495intel_dp_unset_edid(struct intel_dp *intel_dp)
4496{
4497 struct intel_connector *intel_connector = intel_dp->attached_connector;
4498
4499 kfree(intel_connector->detect_edid);
4500 intel_connector->detect_edid = NULL;
4501
4502 intel_dp->has_audio = false;
4503}
4504
4505static enum intel_display_power_domain
4506intel_dp_power_get(struct intel_dp *dp)
4507{
4508 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4509 enum intel_display_power_domain power_domain;
4510
4511 power_domain = intel_display_port_power_domain(encoder);
4512 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4513
4514 return power_domain;
4515}
4516
4517static void
4518intel_dp_power_put(struct intel_dp *dp,
4519 enum intel_display_power_domain power_domain)
4520{
4521 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4522 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
4523}
4524
4525static enum drm_connector_status
4526intel_dp_detect(struct drm_connector *connector, bool force)
4527{
4528 struct intel_dp *intel_dp = intel_attached_dp(connector);
4529 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4530 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4531 struct drm_device *dev = connector->dev;
4532 enum drm_connector_status status;
4533 enum intel_display_power_domain power_domain;
4534 bool ret;
4535 u8 sink_irq_vector;
4536
4537 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4538 connector->base.id, connector->name);
4539 intel_dp_unset_edid(intel_dp);
4540
4541 if (intel_dp->is_mst) {
4542 /* MST devices are disconnected from a monitor POV */
4543 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4544 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4545 return connector_status_disconnected;
4546 }
4547
4548 power_domain = intel_dp_power_get(intel_dp);
4549
4550 /* Can't disconnect eDP, but you can close the lid... */
4551 if (is_edp(intel_dp))
4552 status = edp_detect(intel_dp);
4553 else if (HAS_PCH_SPLIT(dev))
4554 status = ironlake_dp_detect(intel_dp);
4555 else
4556 status = g4x_dp_detect(intel_dp);
4557 if (status != connector_status_connected)
4558 goto out;
4559
4560 intel_dp_probe_oui(intel_dp);
4561
4562 ret = intel_dp_probe_mst(intel_dp);
4563 if (ret) {
4564 /* if we are in MST mode then this connector
4565 won't appear connected or have anything with EDID on it */
4566 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4567 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4568 status = connector_status_disconnected;
4569 goto out;
4570 }
4571
4572 intel_dp_set_edid(intel_dp);
4573
4574 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4575 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4576 status = connector_status_connected;
4577
4578 /* Try to read the source of the interrupt */
4579 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4580 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4581 /* Clear interrupt source */
4582 drm_dp_dpcd_writeb(&intel_dp->aux,
4583 DP_DEVICE_SERVICE_IRQ_VECTOR,
4584 sink_irq_vector);
4585
4586 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4587 intel_dp_handle_test_request(intel_dp);
4588 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4589 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4590 }
4591
4592out:
4593 intel_dp_power_put(intel_dp, power_domain);
4594 return status;
4595}
4596
4597static void
4598intel_dp_force(struct drm_connector *connector)
4599{
4600 struct intel_dp *intel_dp = intel_attached_dp(connector);
4601 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4602 enum intel_display_power_domain power_domain;
4603
4604 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4605 connector->base.id, connector->name);
4606 intel_dp_unset_edid(intel_dp);
4607
4608 if (connector->status != connector_status_connected)
4609 return;
4610
4611 power_domain = intel_dp_power_get(intel_dp);
4612
4613 intel_dp_set_edid(intel_dp);
4614
4615 intel_dp_power_put(intel_dp, power_domain);
4616
4617 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4618 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4619}
4620
4621static int intel_dp_get_modes(struct drm_connector *connector)
4622{
4623 struct intel_connector *intel_connector = to_intel_connector(connector);
4624 struct edid *edid;
4625
4626 edid = intel_connector->detect_edid;
4627 if (edid) {
4628 int ret = intel_connector_update_modes(connector, edid);
4629 if (ret)
4630 return ret;
4631 }
4632
4633 /* if eDP has no EDID, fall back to fixed mode */
4634 if (is_edp(intel_attached_dp(connector)) &&
4635 intel_connector->panel.fixed_mode) {
4636 struct drm_display_mode *mode;
4637
4638 mode = drm_mode_duplicate(connector->dev,
4639 intel_connector->panel.fixed_mode);
4640 if (mode) {
4641 drm_mode_probed_add(connector, mode);
4642 return 1;
4643 }
4644 }
4645
4646 return 0;
4647}
4648
4649static bool
4650intel_dp_detect_audio(struct drm_connector *connector)
4651{
4652 bool has_audio = false;
4653 struct edid *edid;
4654
4655 edid = to_intel_connector(connector)->detect_edid;
4656 if (edid)
4657 has_audio = drm_detect_monitor_audio(edid);
4658
4659 return has_audio;
4660}
4661
4662static int
4663intel_dp_set_property(struct drm_connector *connector,
4664 struct drm_property *property,
4665 uint64_t val)
4666{
4667 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4668 struct intel_connector *intel_connector = to_intel_connector(connector);
4669 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4670 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4671 int ret;
4672
4673 ret = drm_object_property_set_value(&connector->base, property, val);
4674 if (ret)
4675 return ret;
4676
4677 if (property == dev_priv->force_audio_property) {
4678 int i = val;
4679 bool has_audio;
4680
4681 if (i == intel_dp->force_audio)
4682 return 0;
4683
4684 intel_dp->force_audio = i;
4685
4686 if (i == HDMI_AUDIO_AUTO)
4687 has_audio = intel_dp_detect_audio(connector);
4688 else
4689 has_audio = (i == HDMI_AUDIO_ON);
4690
4691 if (has_audio == intel_dp->has_audio)
4692 return 0;
4693
4694 intel_dp->has_audio = has_audio;
4695 goto done;
4696 }
4697
4698 if (property == dev_priv->broadcast_rgb_property) {
4699 bool old_auto = intel_dp->color_range_auto;
4700 bool old_range = intel_dp->limited_color_range;
4701
4702 switch (val) {
4703 case INTEL_BROADCAST_RGB_AUTO:
4704 intel_dp->color_range_auto = true;
4705 break;
4706 case INTEL_BROADCAST_RGB_FULL:
4707 intel_dp->color_range_auto = false;
4708 intel_dp->limited_color_range = false;
4709 break;
4710 case INTEL_BROADCAST_RGB_LIMITED:
4711 intel_dp->color_range_auto = false;
4712 intel_dp->limited_color_range = true;
4713 break;
4714 default:
4715 return -EINVAL;
4716 }
4717
4718 if (old_auto == intel_dp->color_range_auto &&
4719 old_range == intel_dp->limited_color_range)
4720 return 0;
4721
4722 goto done;
4723 }
4724
4725 if (is_edp(intel_dp) &&
4726 property == connector->dev->mode_config.scaling_mode_property) {
4727 if (val == DRM_MODE_SCALE_NONE) {
4728 DRM_DEBUG_KMS("no scaling not supported\n");
4729 return -EINVAL;
4730 }
4731
4732 if (intel_connector->panel.fitting_mode == val) {
4733 /* the eDP scaling property is not changed */
4734 return 0;
4735 }
4736 intel_connector->panel.fitting_mode = val;
4737
4738 goto done;
4739 }
4740
4741 return -EINVAL;
4742
4743done:
4744 if (intel_encoder->base.crtc)
4745 intel_crtc_restore_mode(intel_encoder->base.crtc);
4746
4747 return 0;
4748}
4749
4750static void
4751intel_dp_connector_destroy(struct drm_connector *connector)
4752{
4753 struct intel_connector *intel_connector = to_intel_connector(connector);
4754
4755 kfree(intel_connector->detect_edid);
4756
4757 if (!IS_ERR_OR_NULL(intel_connector->edid))
4758 kfree(intel_connector->edid);
4759
4760 /* Can't call is_edp() since the encoder may have been destroyed
4761 * already. */
4762 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4763 intel_panel_fini(&intel_connector->panel);
4764
4765 drm_connector_cleanup(connector);
4766 kfree(connector);
4767}
4768
4769void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4770{
4771 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4772 struct intel_dp *intel_dp = &intel_dig_port->dp;
4773
4774 drm_dp_aux_unregister(&intel_dp->aux);
4775 intel_dp_mst_encoder_cleanup(intel_dig_port);
4776 if (is_edp(intel_dp)) {
4777 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4778 /*
4779 * vdd might still be enabled do to the delayed vdd off.
4780 * Make sure vdd is actually turned off here.
4781 */
4782 pps_lock(intel_dp);
4783 edp_panel_vdd_off_sync(intel_dp);
4784 pps_unlock(intel_dp);
4785
4786 if (intel_dp->edp_notifier.notifier_call) {
4787 unregister_reboot_notifier(&intel_dp->edp_notifier);
4788 intel_dp->edp_notifier.notifier_call = NULL;
4789 }
4790 }
4791 drm_encoder_cleanup(encoder);
4792 kfree(intel_dig_port);
4793}
4794
4795static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4796{
4797 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4798
4799 if (!is_edp(intel_dp))
4800 return;
4801
4802 /*
4803 * vdd might still be enabled do to the delayed vdd off.
4804 * Make sure vdd is actually turned off here.
4805 */
4806 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4807 pps_lock(intel_dp);
4808 edp_panel_vdd_off_sync(intel_dp);
4809 pps_unlock(intel_dp);
4810}
4811
4812static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4813{
4814 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4815 struct drm_device *dev = intel_dig_port->base.base.dev;
4816 struct drm_i915_private *dev_priv = dev->dev_private;
4817 enum intel_display_power_domain power_domain;
4818
4819 lockdep_assert_held(&dev_priv->pps_mutex);
4820
4821 if (!edp_have_panel_vdd(intel_dp))
4822 return;
4823
4824 /*
4825 * The VDD bit needs a power domain reference, so if the bit is
4826 * already enabled when we boot or resume, grab this reference and
4827 * schedule a vdd off, so we don't hold on to the reference
4828 * indefinitely.
4829 */
4830 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4831 power_domain = intel_display_port_power_domain(&intel_dig_port->base);
4832 intel_display_power_get(dev_priv, power_domain);
4833
4834 edp_panel_vdd_schedule_off(intel_dp);
4835}
4836
4837static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4838{
4839 struct intel_dp *intel_dp;
4840
4841 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4842 return;
4843
4844 intel_dp = enc_to_intel_dp(encoder);
4845
4846 pps_lock(intel_dp);
4847
4848 /*
4849 * Read out the current power sequencer assignment,
4850 * in case the BIOS did something with it.
4851 */
4852 if (IS_VALLEYVIEW(encoder->dev))
4853 vlv_initial_power_sequencer_setup(intel_dp);
4854
4855 intel_edp_panel_vdd_sanitize(intel_dp);
4856
4857 pps_unlock(intel_dp);
4858}
4859
4860static const struct drm_connector_funcs intel_dp_connector_funcs = {
4861 .dpms = drm_atomic_helper_connector_dpms,
4862 .detect = intel_dp_detect,
4863 .force = intel_dp_force,
4864 .fill_modes = drm_helper_probe_single_connector_modes,
4865 .set_property = intel_dp_set_property,
4866 .atomic_get_property = intel_connector_atomic_get_property,
4867 .destroy = intel_dp_connector_destroy,
4868 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4869 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4870};
4871
4872static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4873 .get_modes = intel_dp_get_modes,
4874 .mode_valid = intel_dp_mode_valid,
4875 .best_encoder = intel_best_encoder,
4876};
4877
4878static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4879 .reset = intel_dp_encoder_reset,
4880 .destroy = intel_dp_encoder_destroy,
4881};
4882
4883enum irqreturn
4884intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4885{
4886 struct intel_dp *intel_dp = &intel_dig_port->dp;
4887 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4888 struct drm_device *dev = intel_dig_port->base.base.dev;
4889 struct drm_i915_private *dev_priv = dev->dev_private;
4890 enum intel_display_power_domain power_domain;
4891 enum irqreturn ret = IRQ_NONE;
4892
4893 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4894 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4895
4896 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4897 /*
4898 * vdd off can generate a long pulse on eDP which
4899 * would require vdd on to handle it, and thus we
4900 * would end up in an endless cycle of
4901 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4902 */
4903 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4904 port_name(intel_dig_port->port));
4905 return IRQ_HANDLED;
4906 }
4907
4908 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4909 port_name(intel_dig_port->port),
4910 long_hpd ? "long" : "short");
4911
4912 power_domain = intel_display_port_power_domain(intel_encoder);
4913 intel_display_power_get(dev_priv, power_domain);
4914
4915 if (long_hpd) {
4916 /* indicate that we need to restart link training */
4917 intel_dp->train_set_valid = false;
4918
4919 if (!intel_digital_port_connected(dev_priv, intel_dig_port))
4920 goto mst_fail;
4921
4922 if (!intel_dp_get_dpcd(intel_dp)) {
4923 goto mst_fail;
4924 }
4925
4926 intel_dp_probe_oui(intel_dp);
4927
4928 if (!intel_dp_probe_mst(intel_dp)) {
4929 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4930 intel_dp_check_link_status(intel_dp);
4931 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4932 goto mst_fail;
4933 }
4934 } else {
4935 if (intel_dp->is_mst) {
4936 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
4937 goto mst_fail;
4938 }
4939
4940 if (!intel_dp->is_mst) {
4941 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4942 intel_dp_check_link_status(intel_dp);
4943 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4944 }
4945 }
4946
4947 ret = IRQ_HANDLED;
4948
4949 goto put_power;
4950mst_fail:
4951 /* if we were in MST mode, and device is not there get out of MST mode */
4952 if (intel_dp->is_mst) {
4953 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4954 intel_dp->is_mst = false;
4955 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4956 }
4957put_power:
4958 intel_display_power_put(dev_priv, power_domain);
4959
4960 return ret;
4961}
4962
4963/* Return which DP Port should be selected for Transcoder DP control */
4964int
4965intel_trans_dp_port_sel(struct drm_crtc *crtc)
4966{
4967 struct drm_device *dev = crtc->dev;
4968 struct intel_encoder *intel_encoder;
4969 struct intel_dp *intel_dp;
4970
4971 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4972 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4973
4974 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4975 intel_encoder->type == INTEL_OUTPUT_EDP)
4976 return intel_dp->output_reg;
4977 }
4978
4979 return -1;
4980}
4981
4982/* check the VBT to see whether the eDP is on another port */
4983bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4984{
4985 struct drm_i915_private *dev_priv = dev->dev_private;
4986 union child_device_config *p_child;
4987 int i;
4988 static const short port_mapping[] = {
4989 [PORT_B] = DVO_PORT_DPB,
4990 [PORT_C] = DVO_PORT_DPC,
4991 [PORT_D] = DVO_PORT_DPD,
4992 [PORT_E] = DVO_PORT_DPE,
4993 };
4994
4995 /*
4996 * eDP not supported on g4x. so bail out early just
4997 * for a bit extra safety in case the VBT is bonkers.
4998 */
4999 if (INTEL_INFO(dev)->gen < 5)
5000 return false;
5001
5002 if (port == PORT_A)
5003 return true;
5004
5005 if (!dev_priv->vbt.child_dev_num)
5006 return false;
5007
5008 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
5009 p_child = dev_priv->vbt.child_dev + i;
5010
5011 if (p_child->common.dvo_port == port_mapping[port] &&
5012 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
5013 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
5014 return true;
5015 }
5016 return false;
5017}
5018
5019void
5020intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5021{
5022 struct intel_connector *intel_connector = to_intel_connector(connector);
5023
5024 intel_attach_force_audio_property(connector);
5025 intel_attach_broadcast_rgb_property(connector);
5026 intel_dp->color_range_auto = true;
5027
5028 if (is_edp(intel_dp)) {
5029 drm_mode_create_scaling_mode_property(connector->dev);
5030 drm_object_attach_property(
5031 &connector->base,
5032 connector->dev->mode_config.scaling_mode_property,
5033 DRM_MODE_SCALE_ASPECT);
5034 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
5035 }
5036}
5037
5038static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5039{
5040 intel_dp->last_power_cycle = jiffies;
5041 intel_dp->last_power_on = jiffies;
5042 intel_dp->last_backlight_off = jiffies;
5043}
5044
5045static void
5046intel_dp_init_panel_power_sequencer(struct drm_device *dev,
5047 struct intel_dp *intel_dp)
5048{
5049 struct drm_i915_private *dev_priv = dev->dev_private;
5050 struct edp_power_seq cur, vbt, spec,
5051 *final = &intel_dp->pps_delays;
5052 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5053 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg = 0;
5054
5055 lockdep_assert_held(&dev_priv->pps_mutex);
5056
5057 /* already initialized? */
5058 if (final->t11_t12 != 0)
5059 return;
5060
5061 if (IS_BROXTON(dev)) {
5062 /*
5063 * TODO: BXT has 2 sets of PPS registers.
5064 * Correct Register for Broxton need to be identified
5065 * using VBT. hardcoding for now
5066 */
5067 pp_ctrl_reg = BXT_PP_CONTROL(0);
5068 pp_on_reg = BXT_PP_ON_DELAYS(0);
5069 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5070 } else if (HAS_PCH_SPLIT(dev)) {
5071 pp_ctrl_reg = PCH_PP_CONTROL;
5072 pp_on_reg = PCH_PP_ON_DELAYS;
5073 pp_off_reg = PCH_PP_OFF_DELAYS;
5074 pp_div_reg = PCH_PP_DIVISOR;
5075 } else {
5076 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5077
5078 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
5079 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5080 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5081 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
5082 }
5083
5084 /* Workaround: Need to write PP_CONTROL with the unlock key as
5085 * the very first thing. */
5086 pp_ctl = ironlake_get_pp_control(intel_dp);
5087
5088 pp_on = I915_READ(pp_on_reg);
5089 pp_off = I915_READ(pp_off_reg);
5090 if (!IS_BROXTON(dev)) {
5091 I915_WRITE(pp_ctrl_reg, pp_ctl);
5092 pp_div = I915_READ(pp_div_reg);
5093 }
5094
5095 /* Pull timing values out of registers */
5096 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5097 PANEL_POWER_UP_DELAY_SHIFT;
5098
5099 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5100 PANEL_LIGHT_ON_DELAY_SHIFT;
5101
5102 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5103 PANEL_LIGHT_OFF_DELAY_SHIFT;
5104
5105 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5106 PANEL_POWER_DOWN_DELAY_SHIFT;
5107
5108 if (IS_BROXTON(dev)) {
5109 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5110 BXT_POWER_CYCLE_DELAY_SHIFT;
5111 if (tmp > 0)
5112 cur.t11_t12 = (tmp - 1) * 1000;
5113 else
5114 cur.t11_t12 = 0;
5115 } else {
5116 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5117 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5118 }
5119
5120 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5121 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
5122
5123 vbt = dev_priv->vbt.edp_pps;
5124
5125 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5126 * our hw here, which are all in 100usec. */
5127 spec.t1_t3 = 210 * 10;
5128 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5129 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5130 spec.t10 = 500 * 10;
5131 /* This one is special and actually in units of 100ms, but zero
5132 * based in the hw (so we need to add 100 ms). But the sw vbt
5133 * table multiplies it with 1000 to make it in units of 100usec,
5134 * too. */
5135 spec.t11_t12 = (510 + 100) * 10;
5136
5137 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5138 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
5139
5140 /* Use the max of the register settings and vbt. If both are
5141 * unset, fall back to the spec limits. */
5142#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5143 spec.field : \
5144 max(cur.field, vbt.field))
5145 assign_final(t1_t3);
5146 assign_final(t8);
5147 assign_final(t9);
5148 assign_final(t10);
5149 assign_final(t11_t12);
5150#undef assign_final
5151
5152#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5153 intel_dp->panel_power_up_delay = get_delay(t1_t3);
5154 intel_dp->backlight_on_delay = get_delay(t8);
5155 intel_dp->backlight_off_delay = get_delay(t9);
5156 intel_dp->panel_power_down_delay = get_delay(t10);
5157 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5158#undef get_delay
5159
5160 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5161 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5162 intel_dp->panel_power_cycle_delay);
5163
5164 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5165 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5166}
5167
5168static void
5169intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5170 struct intel_dp *intel_dp)
5171{
5172 struct drm_i915_private *dev_priv = dev->dev_private;
5173 u32 pp_on, pp_off, pp_div, port_sel = 0;
5174 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
5175 int pp_on_reg, pp_off_reg, pp_div_reg = 0, pp_ctrl_reg;
5176 enum port port = dp_to_dig_port(intel_dp)->port;
5177 const struct edp_power_seq *seq = &intel_dp->pps_delays;
5178
5179 lockdep_assert_held(&dev_priv->pps_mutex);
5180
5181 if (IS_BROXTON(dev)) {
5182 /*
5183 * TODO: BXT has 2 sets of PPS registers.
5184 * Correct Register for Broxton need to be identified
5185 * using VBT. hardcoding for now
5186 */
5187 pp_ctrl_reg = BXT_PP_CONTROL(0);
5188 pp_on_reg = BXT_PP_ON_DELAYS(0);
5189 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5190
5191 } else if (HAS_PCH_SPLIT(dev)) {
5192 pp_on_reg = PCH_PP_ON_DELAYS;
5193 pp_off_reg = PCH_PP_OFF_DELAYS;
5194 pp_div_reg = PCH_PP_DIVISOR;
5195 } else {
5196 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5197
5198 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5199 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5200 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
5201 }
5202
5203 /*
5204 * And finally store the new values in the power sequencer. The
5205 * backlight delays are set to 1 because we do manual waits on them. For
5206 * T8, even BSpec recommends doing it. For T9, if we don't do this,
5207 * we'll end up waiting for the backlight off delay twice: once when we
5208 * do the manual sleep, and once when we disable the panel and wait for
5209 * the PP_STATUS bit to become zero.
5210 */
5211 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5212 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
5213 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5214 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5215 /* Compute the divisor for the pp clock, simply match the Bspec
5216 * formula. */
5217 if (IS_BROXTON(dev)) {
5218 pp_div = I915_READ(pp_ctrl_reg);
5219 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5220 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5221 << BXT_POWER_CYCLE_DELAY_SHIFT);
5222 } else {
5223 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5224 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5225 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5226 }
5227
5228 /* Haswell doesn't have any port selection bits for the panel
5229 * power sequencer any more. */
5230 if (IS_VALLEYVIEW(dev)) {
5231 port_sel = PANEL_PORT_SELECT_VLV(port);
5232 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5233 if (port == PORT_A)
5234 port_sel = PANEL_PORT_SELECT_DPA;
5235 else
5236 port_sel = PANEL_PORT_SELECT_DPD;
5237 }
5238
5239 pp_on |= port_sel;
5240
5241 I915_WRITE(pp_on_reg, pp_on);
5242 I915_WRITE(pp_off_reg, pp_off);
5243 if (IS_BROXTON(dev))
5244 I915_WRITE(pp_ctrl_reg, pp_div);
5245 else
5246 I915_WRITE(pp_div_reg, pp_div);
5247
5248 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5249 I915_READ(pp_on_reg),
5250 I915_READ(pp_off_reg),
5251 IS_BROXTON(dev) ?
5252 (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) :
5253 I915_READ(pp_div_reg));
5254}
5255
5256/**
5257 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5258 * @dev: DRM device
5259 * @refresh_rate: RR to be programmed
5260 *
5261 * This function gets called when refresh rate (RR) has to be changed from
5262 * one frequency to another. Switches can be between high and low RR
5263 * supported by the panel or to any other RR based on media playback (in
5264 * this case, RR value needs to be passed from user space).
5265 *
5266 * The caller of this function needs to take a lock on dev_priv->drrs.
5267 */
5268static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
5269{
5270 struct drm_i915_private *dev_priv = dev->dev_private;
5271 struct intel_encoder *encoder;
5272 struct intel_digital_port *dig_port = NULL;
5273 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5274 struct intel_crtc_state *config = NULL;
5275 struct intel_crtc *intel_crtc = NULL;
5276 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5277
5278 if (refresh_rate <= 0) {
5279 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5280 return;
5281 }
5282
5283 if (intel_dp == NULL) {
5284 DRM_DEBUG_KMS("DRRS not supported.\n");
5285 return;
5286 }
5287
5288 /*
5289 * FIXME: This needs proper synchronization with psr state for some
5290 * platforms that cannot have PSR and DRRS enabled at the same time.
5291 */
5292
5293 dig_port = dp_to_dig_port(intel_dp);
5294 encoder = &dig_port->base;
5295 intel_crtc = to_intel_crtc(encoder->base.crtc);
5296
5297 if (!intel_crtc) {
5298 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5299 return;
5300 }
5301
5302 config = intel_crtc->config;
5303
5304 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5305 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5306 return;
5307 }
5308
5309 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5310 refresh_rate)
5311 index = DRRS_LOW_RR;
5312
5313 if (index == dev_priv->drrs.refresh_rate_type) {
5314 DRM_DEBUG_KMS(
5315 "DRRS requested for previously set RR...ignoring\n");
5316 return;
5317 }
5318
5319 if (!intel_crtc->active) {
5320 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5321 return;
5322 }
5323
5324 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
5325 switch (index) {
5326 case DRRS_HIGH_RR:
5327 intel_dp_set_m_n(intel_crtc, M1_N1);
5328 break;
5329 case DRRS_LOW_RR:
5330 intel_dp_set_m_n(intel_crtc, M2_N2);
5331 break;
5332 case DRRS_MAX_RR:
5333 default:
5334 DRM_ERROR("Unsupported refreshrate type\n");
5335 }
5336 } else if (INTEL_INFO(dev)->gen > 6) {
5337 u32 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
5338 u32 val;
5339
5340 val = I915_READ(reg);
5341 if (index > DRRS_HIGH_RR) {
5342 if (IS_VALLEYVIEW(dev))
5343 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5344 else
5345 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5346 } else {
5347 if (IS_VALLEYVIEW(dev))
5348 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5349 else
5350 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5351 }
5352 I915_WRITE(reg, val);
5353 }
5354
5355 dev_priv->drrs.refresh_rate_type = index;
5356
5357 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5358}
5359
5360/**
5361 * intel_edp_drrs_enable - init drrs struct if supported
5362 * @intel_dp: DP struct
5363 *
5364 * Initializes frontbuffer_bits and drrs.dp
5365 */
5366void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5367{
5368 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5369 struct drm_i915_private *dev_priv = dev->dev_private;
5370 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5371 struct drm_crtc *crtc = dig_port->base.base.crtc;
5372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5373
5374 if (!intel_crtc->config->has_drrs) {
5375 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5376 return;
5377 }
5378
5379 mutex_lock(&dev_priv->drrs.mutex);
5380 if (WARN_ON(dev_priv->drrs.dp)) {
5381 DRM_ERROR("DRRS already enabled\n");
5382 goto unlock;
5383 }
5384
5385 dev_priv->drrs.busy_frontbuffer_bits = 0;
5386
5387 dev_priv->drrs.dp = intel_dp;
5388
5389unlock:
5390 mutex_unlock(&dev_priv->drrs.mutex);
5391}
5392
5393/**
5394 * intel_edp_drrs_disable - Disable DRRS
5395 * @intel_dp: DP struct
5396 *
5397 */
5398void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5399{
5400 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5401 struct drm_i915_private *dev_priv = dev->dev_private;
5402 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5403 struct drm_crtc *crtc = dig_port->base.base.crtc;
5404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5405
5406 if (!intel_crtc->config->has_drrs)
5407 return;
5408
5409 mutex_lock(&dev_priv->drrs.mutex);
5410 if (!dev_priv->drrs.dp) {
5411 mutex_unlock(&dev_priv->drrs.mutex);
5412 return;
5413 }
5414
5415 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5416 intel_dp_set_drrs_state(dev_priv->dev,
5417 intel_dp->attached_connector->panel.
5418 fixed_mode->vrefresh);
5419
5420 dev_priv->drrs.dp = NULL;
5421 mutex_unlock(&dev_priv->drrs.mutex);
5422
5423 cancel_delayed_work_sync(&dev_priv->drrs.work);
5424}
5425
5426static void intel_edp_drrs_downclock_work(struct work_struct *work)
5427{
5428 struct drm_i915_private *dev_priv =
5429 container_of(work, typeof(*dev_priv), drrs.work.work);
5430 struct intel_dp *intel_dp;
5431
5432 mutex_lock(&dev_priv->drrs.mutex);
5433
5434 intel_dp = dev_priv->drrs.dp;
5435
5436 if (!intel_dp)
5437 goto unlock;
5438
5439 /*
5440 * The delayed work can race with an invalidate hence we need to
5441 * recheck.
5442 */
5443
5444 if (dev_priv->drrs.busy_frontbuffer_bits)
5445 goto unlock;
5446
5447 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5448 intel_dp_set_drrs_state(dev_priv->dev,
5449 intel_dp->attached_connector->panel.
5450 downclock_mode->vrefresh);
5451
5452unlock:
5453 mutex_unlock(&dev_priv->drrs.mutex);
5454}
5455
5456/**
5457 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5458 * @dev: DRM device
5459 * @frontbuffer_bits: frontbuffer plane tracking bits
5460 *
5461 * This function gets called everytime rendering on the given planes start.
5462 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5463 *
5464 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5465 */
5466void intel_edp_drrs_invalidate(struct drm_device *dev,
5467 unsigned frontbuffer_bits)
5468{
5469 struct drm_i915_private *dev_priv = dev->dev_private;
5470 struct drm_crtc *crtc;
5471 enum pipe pipe;
5472
5473 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5474 return;
5475
5476 cancel_delayed_work(&dev_priv->drrs.work);
5477
5478 mutex_lock(&dev_priv->drrs.mutex);
5479 if (!dev_priv->drrs.dp) {
5480 mutex_unlock(&dev_priv->drrs.mutex);
5481 return;
5482 }
5483
5484 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5485 pipe = to_intel_crtc(crtc)->pipe;
5486
5487 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5488 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5489
5490 /* invalidate means busy screen hence upclock */
5491 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5492 intel_dp_set_drrs_state(dev_priv->dev,
5493 dev_priv->drrs.dp->attached_connector->panel.
5494 fixed_mode->vrefresh);
5495
5496 mutex_unlock(&dev_priv->drrs.mutex);
5497}
5498
5499/**
5500 * intel_edp_drrs_flush - Restart Idleness DRRS
5501 * @dev: DRM device
5502 * @frontbuffer_bits: frontbuffer plane tracking bits
5503 *
5504 * This function gets called every time rendering on the given planes has
5505 * completed or flip on a crtc is completed. So DRRS should be upclocked
5506 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5507 * if no other planes are dirty.
5508 *
5509 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5510 */
5511void intel_edp_drrs_flush(struct drm_device *dev,
5512 unsigned frontbuffer_bits)
5513{
5514 struct drm_i915_private *dev_priv = dev->dev_private;
5515 struct drm_crtc *crtc;
5516 enum pipe pipe;
5517
5518 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5519 return;
5520
5521 cancel_delayed_work(&dev_priv->drrs.work);
5522
5523 mutex_lock(&dev_priv->drrs.mutex);
5524 if (!dev_priv->drrs.dp) {
5525 mutex_unlock(&dev_priv->drrs.mutex);
5526 return;
5527 }
5528
5529 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5530 pipe = to_intel_crtc(crtc)->pipe;
5531
5532 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5533 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5534
5535 /* flush means busy screen hence upclock */
5536 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5537 intel_dp_set_drrs_state(dev_priv->dev,
5538 dev_priv->drrs.dp->attached_connector->panel.
5539 fixed_mode->vrefresh);
5540
5541 /*
5542 * flush also means no more activity hence schedule downclock, if all
5543 * other fbs are quiescent too
5544 */
5545 if (!dev_priv->drrs.busy_frontbuffer_bits)
5546 schedule_delayed_work(&dev_priv->drrs.work,
5547 msecs_to_jiffies(1000));
5548 mutex_unlock(&dev_priv->drrs.mutex);
5549}
5550
5551/**
5552 * DOC: Display Refresh Rate Switching (DRRS)
5553 *
5554 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5555 * which enables swtching between low and high refresh rates,
5556 * dynamically, based on the usage scenario. This feature is applicable
5557 * for internal panels.
5558 *
5559 * Indication that the panel supports DRRS is given by the panel EDID, which
5560 * would list multiple refresh rates for one resolution.
5561 *
5562 * DRRS is of 2 types - static and seamless.
5563 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5564 * (may appear as a blink on screen) and is used in dock-undock scenario.
5565 * Seamless DRRS involves changing RR without any visual effect to the user
5566 * and can be used during normal system usage. This is done by programming
5567 * certain registers.
5568 *
5569 * Support for static/seamless DRRS may be indicated in the VBT based on
5570 * inputs from the panel spec.
5571 *
5572 * DRRS saves power by switching to low RR based on usage scenarios.
5573 *
5574 * eDP DRRS:-
5575 * The implementation is based on frontbuffer tracking implementation.
5576 * When there is a disturbance on the screen triggered by user activity or a
5577 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5578 * When there is no movement on screen, after a timeout of 1 second, a switch
5579 * to low RR is made.
5580 * For integration with frontbuffer tracking code,
5581 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5582 *
5583 * DRRS can be further extended to support other internal panels and also
5584 * the scenario of video playback wherein RR is set based on the rate
5585 * requested by userspace.
5586 */
5587
5588/**
5589 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5590 * @intel_connector: eDP connector
5591 * @fixed_mode: preferred mode of panel
5592 *
5593 * This function is called only once at driver load to initialize basic
5594 * DRRS stuff.
5595 *
5596 * Returns:
5597 * Downclock mode if panel supports it, else return NULL.
5598 * DRRS support is determined by the presence of downclock mode (apart
5599 * from VBT setting).
5600 */
5601static struct drm_display_mode *
5602intel_dp_drrs_init(struct intel_connector *intel_connector,
5603 struct drm_display_mode *fixed_mode)
5604{
5605 struct drm_connector *connector = &intel_connector->base;
5606 struct drm_device *dev = connector->dev;
5607 struct drm_i915_private *dev_priv = dev->dev_private;
5608 struct drm_display_mode *downclock_mode = NULL;
5609
5610 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5611 mutex_init(&dev_priv->drrs.mutex);
5612
5613 if (INTEL_INFO(dev)->gen <= 6) {
5614 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5615 return NULL;
5616 }
5617
5618 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5619 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5620 return NULL;
5621 }
5622
5623 downclock_mode = intel_find_panel_downclock
5624 (dev, fixed_mode, connector);
5625
5626 if (!downclock_mode) {
5627 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5628 return NULL;
5629 }
5630
5631 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5632
5633 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5634 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5635 return downclock_mode;
5636}
5637
5638static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5639 struct intel_connector *intel_connector)
5640{
5641 struct drm_connector *connector = &intel_connector->base;
5642 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5643 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5644 struct drm_device *dev = intel_encoder->base.dev;
5645 struct drm_i915_private *dev_priv = dev->dev_private;
5646 struct drm_display_mode *fixed_mode = NULL;
5647 struct drm_display_mode *downclock_mode = NULL;
5648 bool has_dpcd;
5649 struct drm_display_mode *scan;
5650 struct edid *edid;
5651 enum pipe pipe = INVALID_PIPE;
5652
5653 if (!is_edp(intel_dp))
5654 return true;
5655
5656 pps_lock(intel_dp);
5657 intel_edp_panel_vdd_sanitize(intel_dp);
5658 pps_unlock(intel_dp);
5659
5660 /* Cache DPCD and EDID for edp. */
5661 has_dpcd = intel_dp_get_dpcd(intel_dp);
5662
5663 if (has_dpcd) {
5664 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5665 dev_priv->no_aux_handshake =
5666 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5667 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5668 } else {
5669 /* if this fails, presume the device is a ghost */
5670 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5671 return false;
5672 }
5673
5674 /* We now know it's not a ghost, init power sequence regs. */
5675 pps_lock(intel_dp);
5676 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5677 pps_unlock(intel_dp);
5678
5679 mutex_lock(&dev->mode_config.mutex);
5680 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5681 if (edid) {
5682 if (drm_add_edid_modes(connector, edid)) {
5683 drm_mode_connector_update_edid_property(connector,
5684 edid);
5685 drm_edid_to_eld(connector, edid);
5686 } else {
5687 kfree(edid);
5688 edid = ERR_PTR(-EINVAL);
5689 }
5690 } else {
5691 edid = ERR_PTR(-ENOENT);
5692 }
5693 intel_connector->edid = edid;
5694
5695 /* prefer fixed mode from EDID if available */
5696 list_for_each_entry(scan, &connector->probed_modes, head) {
5697 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5698 fixed_mode = drm_mode_duplicate(dev, scan);
5699 downclock_mode = intel_dp_drrs_init(
5700 intel_connector, fixed_mode);
5701 break;
5702 }
5703 }
5704
5705 /* fallback to VBT if available for eDP */
5706 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5707 fixed_mode = drm_mode_duplicate(dev,
5708 dev_priv->vbt.lfp_lvds_vbt_mode);
5709 if (fixed_mode)
5710 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5711 }
5712 mutex_unlock(&dev->mode_config.mutex);
5713
5714 if (IS_VALLEYVIEW(dev)) {
5715 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5716 register_reboot_notifier(&intel_dp->edp_notifier);
5717
5718 /*
5719 * Figure out the current pipe for the initial backlight setup.
5720 * If the current pipe isn't valid, try the PPS pipe, and if that
5721 * fails just assume pipe A.
5722 */
5723 if (IS_CHERRYVIEW(dev))
5724 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5725 else
5726 pipe = PORT_TO_PIPE(intel_dp->DP);
5727
5728 if (pipe != PIPE_A && pipe != PIPE_B)
5729 pipe = intel_dp->pps_pipe;
5730
5731 if (pipe != PIPE_A && pipe != PIPE_B)
5732 pipe = PIPE_A;
5733
5734 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5735 pipe_name(pipe));
5736 }
5737
5738 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5739 intel_connector->panel.backlight.power = intel_edp_backlight_power;
5740 intel_panel_setup_backlight(connector, pipe);
5741
5742 return true;
5743}
5744
5745bool
5746intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5747 struct intel_connector *intel_connector)
5748{
5749 struct drm_connector *connector = &intel_connector->base;
5750 struct intel_dp *intel_dp = &intel_dig_port->dp;
5751 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5752 struct drm_device *dev = intel_encoder->base.dev;
5753 struct drm_i915_private *dev_priv = dev->dev_private;
5754 enum port port = intel_dig_port->port;
5755 int type;
5756
5757 intel_dp->pps_pipe = INVALID_PIPE;
5758
5759 /* intel_dp vfuncs */
5760 if (INTEL_INFO(dev)->gen >= 9)
5761 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5762 else if (IS_VALLEYVIEW(dev))
5763 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5764 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5765 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5766 else if (HAS_PCH_SPLIT(dev))
5767 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5768 else
5769 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5770
5771 if (INTEL_INFO(dev)->gen >= 9)
5772 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5773 else
5774 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
5775
5776 if (HAS_DDI(dev))
5777 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5778
5779 /* Preserve the current hw state. */
5780 intel_dp->DP = I915_READ(intel_dp->output_reg);
5781 intel_dp->attached_connector = intel_connector;
5782
5783 if (intel_dp_is_edp(dev, port))
5784 type = DRM_MODE_CONNECTOR_eDP;
5785 else
5786 type = DRM_MODE_CONNECTOR_DisplayPort;
5787
5788 /*
5789 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5790 * for DP the encoder type can be set by the caller to
5791 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5792 */
5793 if (type == DRM_MODE_CONNECTOR_eDP)
5794 intel_encoder->type = INTEL_OUTPUT_EDP;
5795
5796 /* eDP only on port B and/or C on vlv/chv */
5797 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5798 port != PORT_B && port != PORT_C))
5799 return false;
5800
5801 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5802 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5803 port_name(port));
5804
5805 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5806 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5807
5808 connector->interlace_allowed = true;
5809 connector->doublescan_allowed = 0;
5810
5811 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5812 edp_panel_vdd_work);
5813
5814 intel_connector_attach_encoder(intel_connector, intel_encoder);
5815 drm_connector_register(connector);
5816
5817 if (HAS_DDI(dev))
5818 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5819 else
5820 intel_connector->get_hw_state = intel_connector_get_hw_state;
5821 intel_connector->unregister = intel_dp_connector_unregister;
5822
5823 /* Set up the hotplug pin. */
5824 switch (port) {
5825 case PORT_A:
5826 intel_encoder->hpd_pin = HPD_PORT_A;
5827 break;
5828 case PORT_B:
5829 intel_encoder->hpd_pin = HPD_PORT_B;
5830 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
5831 intel_encoder->hpd_pin = HPD_PORT_A;
5832 break;
5833 case PORT_C:
5834 intel_encoder->hpd_pin = HPD_PORT_C;
5835 break;
5836 case PORT_D:
5837 intel_encoder->hpd_pin = HPD_PORT_D;
5838 break;
5839 case PORT_E:
5840 intel_encoder->hpd_pin = HPD_PORT_E;
5841 break;
5842 default:
5843 BUG();
5844 }
5845
5846 if (is_edp(intel_dp)) {
5847 pps_lock(intel_dp);
5848 intel_dp_init_panel_power_timestamps(intel_dp);
5849 if (IS_VALLEYVIEW(dev))
5850 vlv_initial_power_sequencer_setup(intel_dp);
5851 else
5852 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5853 pps_unlock(intel_dp);
5854 }
5855
5856 intel_dp_aux_init(intel_dp, intel_connector);
5857
5858 /* init MST on ports that can support it */
5859 if (HAS_DP_MST(dev) &&
5860 (port == PORT_B || port == PORT_C || port == PORT_D))
5861 intel_dp_mst_encoder_init(intel_dig_port,
5862 intel_connector->base.base.id);
5863
5864 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5865 drm_dp_aux_unregister(&intel_dp->aux);
5866 if (is_edp(intel_dp)) {
5867 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5868 /*
5869 * vdd might still be enabled do to the delayed vdd off.
5870 * Make sure vdd is actually turned off here.
5871 */
5872 pps_lock(intel_dp);
5873 edp_panel_vdd_off_sync(intel_dp);
5874 pps_unlock(intel_dp);
5875 }
5876 drm_connector_unregister(connector);
5877 drm_connector_cleanup(connector);
5878 return false;
5879 }
5880
5881 intel_dp_add_properties(intel_dp, connector);
5882
5883 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5884 * 0xd. Failure to do so will result in spurious interrupts being
5885 * generated on the port when a cable is not attached.
5886 */
5887 if (IS_G4X(dev) && !IS_GM45(dev)) {
5888 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5889 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5890 }
5891
5892 i915_debugfs_connector_add(connector);
5893
5894 return true;
5895}
5896
5897void
5898intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5899{
5900 struct drm_i915_private *dev_priv = dev->dev_private;
5901 struct intel_digital_port *intel_dig_port;
5902 struct intel_encoder *intel_encoder;
5903 struct drm_encoder *encoder;
5904 struct intel_connector *intel_connector;
5905
5906 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5907 if (!intel_dig_port)
5908 return;
5909
5910 intel_connector = intel_connector_alloc();
5911 if (!intel_connector)
5912 goto err_connector_alloc;
5913
5914 intel_encoder = &intel_dig_port->base;
5915 encoder = &intel_encoder->base;
5916
5917 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5918 DRM_MODE_ENCODER_TMDS);
5919
5920 intel_encoder->compute_config = intel_dp_compute_config;
5921 intel_encoder->disable = intel_disable_dp;
5922 intel_encoder->get_hw_state = intel_dp_get_hw_state;
5923 intel_encoder->get_config = intel_dp_get_config;
5924 intel_encoder->suspend = intel_dp_encoder_suspend;
5925 if (IS_CHERRYVIEW(dev)) {
5926 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5927 intel_encoder->pre_enable = chv_pre_enable_dp;
5928 intel_encoder->enable = vlv_enable_dp;
5929 intel_encoder->post_disable = chv_post_disable_dp;
5930 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
5931 } else if (IS_VALLEYVIEW(dev)) {
5932 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5933 intel_encoder->pre_enable = vlv_pre_enable_dp;
5934 intel_encoder->enable = vlv_enable_dp;
5935 intel_encoder->post_disable = vlv_post_disable_dp;
5936 } else {
5937 intel_encoder->pre_enable = g4x_pre_enable_dp;
5938 intel_encoder->enable = g4x_enable_dp;
5939 if (INTEL_INFO(dev)->gen >= 5)
5940 intel_encoder->post_disable = ilk_post_disable_dp;
5941 }
5942
5943 intel_dig_port->port = port;
5944 intel_dig_port->dp.output_reg = output_reg;
5945
5946 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
5947 if (IS_CHERRYVIEW(dev)) {
5948 if (port == PORT_D)
5949 intel_encoder->crtc_mask = 1 << 2;
5950 else
5951 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5952 } else {
5953 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5954 }
5955 intel_encoder->cloneable = 0;
5956
5957 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5958 dev_priv->hotplug.irq_port[port] = intel_dig_port;
5959
5960 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
5961 goto err_init_connector;
5962
5963 return;
5964
5965err_init_connector:
5966 drm_encoder_cleanup(encoder);
5967 kfree(intel_connector);
5968err_connector_alloc:
5969 kfree(intel_dig_port);
5970
5971 return;
5972}
5973
5974void intel_dp_mst_suspend(struct drm_device *dev)
5975{
5976 struct drm_i915_private *dev_priv = dev->dev_private;
5977 int i;
5978
5979 /* disable MST */
5980 for (i = 0; i < I915_MAX_PORTS; i++) {
5981 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5982 if (!intel_dig_port)
5983 continue;
5984
5985 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5986 if (!intel_dig_port->dp.can_mst)
5987 continue;
5988 if (intel_dig_port->dp.is_mst)
5989 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5990 }
5991 }
5992}
5993
5994void intel_dp_mst_resume(struct drm_device *dev)
5995{
5996 struct drm_i915_private *dev_priv = dev->dev_private;
5997 int i;
5998
5999 for (i = 0; i < I915_MAX_PORTS; i++) {
6000 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6001 if (!intel_dig_port)
6002 continue;
6003 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
6004 int ret;
6005
6006 if (!intel_dig_port->dp.can_mst)
6007 continue;
6008
6009 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6010 if (ret != 0) {
6011 intel_dp_check_mst_status(&intel_dig_port->dp);
6012 }
6013 }
6014 }
6015}
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