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1 | /* | |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
23 | * IN THE SOFTWARE. | |
24 | */ | |
25 | #ifndef __INTEL_DRV_H__ | |
26 | #define __INTEL_DRV_H__ | |
27 | ||
28 | #include <linux/async.h> | |
29 | #include <linux/i2c.h> | |
30 | #include <linux/hdmi.h> | |
31 | #include <drm/i915_drm.h> | |
32 | #include "i915_drv.h" | |
33 | #include <drm/drm_crtc.h> | |
34 | #include <drm/drm_crtc_helper.h> | |
35 | #include <drm/drm_fb_helper.h> | |
36 | #include <drm/drm_dp_mst_helper.h> | |
37 | #include <drm/drm_rect.h> | |
38 | #include <drm/drm_atomic.h> | |
39 | ||
40 | /** | |
41 | * _wait_for - magic (register) wait macro | |
42 | * | |
43 | * Does the right thing for modeset paths when run under kdgb or similar atomic | |
44 | * contexts. Note that it's important that we check the condition again after | |
45 | * having timed out, since the timeout could be due to preemption or similar and | |
46 | * we've never had a chance to check the condition before the timeout. | |
47 | */ | |
48 | #define _wait_for(COND, MS, W) ({ \ | |
49 | unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ | |
50 | int ret__ = 0; \ | |
51 | while (!(COND)) { \ | |
52 | if (time_after(jiffies, timeout__)) { \ | |
53 | if (!(COND)) \ | |
54 | ret__ = -ETIMEDOUT; \ | |
55 | break; \ | |
56 | } \ | |
57 | if ((W) && drm_can_sleep()) { \ | |
58 | usleep_range((W)*1000, (W)*2000); \ | |
59 | } else { \ | |
60 | cpu_relax(); \ | |
61 | } \ | |
62 | } \ | |
63 | ret__; \ | |
64 | }) | |
65 | ||
66 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) | |
67 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) | |
68 | #define wait_for_atomic_us(COND, US) _wait_for((COND), \ | |
69 | DIV_ROUND_UP((US), 1000), 0) | |
70 | ||
71 | #define KHz(x) (1000 * (x)) | |
72 | #define MHz(x) KHz(1000 * (x)) | |
73 | ||
74 | /* | |
75 | * Display related stuff | |
76 | */ | |
77 | ||
78 | /* store information about an Ixxx DVO */ | |
79 | /* The i830->i865 use multiple DVOs with multiple i2cs */ | |
80 | /* the i915, i945 have a single sDVO i2c bus - which is different */ | |
81 | #define MAX_OUTPUTS 6 | |
82 | /* maximum connectors per crtcs in the mode set */ | |
83 | ||
84 | /* Maximum cursor sizes */ | |
85 | #define GEN2_CURSOR_WIDTH 64 | |
86 | #define GEN2_CURSOR_HEIGHT 64 | |
87 | #define MAX_CURSOR_WIDTH 256 | |
88 | #define MAX_CURSOR_HEIGHT 256 | |
89 | ||
90 | #define INTEL_I2C_BUS_DVO 1 | |
91 | #define INTEL_I2C_BUS_SDVO 2 | |
92 | ||
93 | /* these are outputs from the chip - integrated only | |
94 | external chips are via DVO or SDVO output */ | |
95 | enum intel_output_type { | |
96 | INTEL_OUTPUT_UNUSED = 0, | |
97 | INTEL_OUTPUT_ANALOG = 1, | |
98 | INTEL_OUTPUT_DVO = 2, | |
99 | INTEL_OUTPUT_SDVO = 3, | |
100 | INTEL_OUTPUT_LVDS = 4, | |
101 | INTEL_OUTPUT_TVOUT = 5, | |
102 | INTEL_OUTPUT_HDMI = 6, | |
103 | INTEL_OUTPUT_DISPLAYPORT = 7, | |
104 | INTEL_OUTPUT_EDP = 8, | |
105 | INTEL_OUTPUT_DSI = 9, | |
106 | INTEL_OUTPUT_UNKNOWN = 10, | |
107 | INTEL_OUTPUT_DP_MST = 11, | |
108 | }; | |
109 | ||
110 | #define INTEL_DVO_CHIP_NONE 0 | |
111 | #define INTEL_DVO_CHIP_LVDS 1 | |
112 | #define INTEL_DVO_CHIP_TMDS 2 | |
113 | #define INTEL_DVO_CHIP_TVOUT 4 | |
114 | ||
115 | #define INTEL_DSI_VIDEO_MODE 0 | |
116 | #define INTEL_DSI_COMMAND_MODE 1 | |
117 | ||
118 | struct intel_framebuffer { | |
119 | struct drm_framebuffer base; | |
120 | struct drm_i915_gem_object *obj; | |
121 | }; | |
122 | ||
123 | struct intel_fbdev { | |
124 | struct drm_fb_helper helper; | |
125 | struct intel_framebuffer *fb; | |
126 | struct list_head fbdev_list; | |
127 | struct drm_display_mode *our_mode; | |
128 | int preferred_bpp; | |
129 | }; | |
130 | ||
131 | struct intel_encoder { | |
132 | struct drm_encoder base; | |
133 | ||
134 | enum intel_output_type type; | |
135 | unsigned int cloneable; | |
136 | void (*hot_plug)(struct intel_encoder *); | |
137 | bool (*compute_config)(struct intel_encoder *, | |
138 | struct intel_crtc_state *); | |
139 | void (*pre_pll_enable)(struct intel_encoder *); | |
140 | void (*pre_enable)(struct intel_encoder *); | |
141 | void (*enable)(struct intel_encoder *); | |
142 | void (*mode_set)(struct intel_encoder *intel_encoder); | |
143 | void (*disable)(struct intel_encoder *); | |
144 | void (*post_disable)(struct intel_encoder *); | |
145 | void (*post_pll_disable)(struct intel_encoder *); | |
146 | /* Read out the current hw state of this connector, returning true if | |
147 | * the encoder is active. If the encoder is enabled it also set the pipe | |
148 | * it is connected to in the pipe parameter. */ | |
149 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); | |
150 | /* Reconstructs the equivalent mode flags for the current hardware | |
151 | * state. This must be called _after_ display->get_pipe_config has | |
152 | * pre-filled the pipe config. Note that intel_encoder->base.crtc must | |
153 | * be set correctly before calling this function. */ | |
154 | void (*get_config)(struct intel_encoder *, | |
155 | struct intel_crtc_state *pipe_config); | |
156 | /* | |
157 | * Called during system suspend after all pending requests for the | |
158 | * encoder are flushed (for example for DP AUX transactions) and | |
159 | * device interrupts are disabled. | |
160 | */ | |
161 | void (*suspend)(struct intel_encoder *); | |
162 | int crtc_mask; | |
163 | enum hpd_pin hpd_pin; | |
164 | }; | |
165 | ||
166 | struct intel_panel { | |
167 | struct drm_display_mode *fixed_mode; | |
168 | struct drm_display_mode *downclock_mode; | |
169 | int fitting_mode; | |
170 | ||
171 | /* backlight */ | |
172 | struct { | |
173 | bool present; | |
174 | u32 level; | |
175 | u32 min; | |
176 | u32 max; | |
177 | bool enabled; | |
178 | bool combination_mode; /* gen 2/4 only */ | |
179 | bool active_low_pwm; | |
180 | ||
181 | /* PWM chip */ | |
182 | bool util_pin_active_low; /* bxt+ */ | |
183 | u8 controller; /* bxt+ only */ | |
184 | struct pwm_device *pwm; | |
185 | ||
186 | struct backlight_device *device; | |
187 | ||
188 | /* Connector and platform specific backlight functions */ | |
189 | int (*setup)(struct intel_connector *connector, enum pipe pipe); | |
190 | uint32_t (*get)(struct intel_connector *connector); | |
191 | void (*set)(struct intel_connector *connector, uint32_t level); | |
192 | void (*disable)(struct intel_connector *connector); | |
193 | void (*enable)(struct intel_connector *connector); | |
194 | uint32_t (*hz_to_pwm)(struct intel_connector *connector, | |
195 | uint32_t hz); | |
196 | void (*power)(struct intel_connector *, bool enable); | |
197 | } backlight; | |
198 | }; | |
199 | ||
200 | struct intel_connector { | |
201 | struct drm_connector base; | |
202 | /* | |
203 | * The fixed encoder this connector is connected to. | |
204 | */ | |
205 | struct intel_encoder *encoder; | |
206 | ||
207 | /* Reads out the current hw, returning true if the connector is enabled | |
208 | * and active (i.e. dpms ON state). */ | |
209 | bool (*get_hw_state)(struct intel_connector *); | |
210 | ||
211 | /* | |
212 | * Removes all interfaces through which the connector is accessible | |
213 | * - like sysfs, debugfs entries -, so that no new operations can be | |
214 | * started on the connector. Also makes sure all currently pending | |
215 | * operations finish before returing. | |
216 | */ | |
217 | void (*unregister)(struct intel_connector *); | |
218 | ||
219 | /* Panel info for eDP and LVDS */ | |
220 | struct intel_panel panel; | |
221 | ||
222 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ | |
223 | struct edid *edid; | |
224 | struct edid *detect_edid; | |
225 | ||
226 | /* since POLL and HPD connectors may use the same HPD line keep the native | |
227 | state of connector->polled in case hotplug storm detection changes it */ | |
228 | u8 polled; | |
229 | ||
230 | void *port; /* store this opaque as its illegal to dereference it */ | |
231 | ||
232 | struct intel_dp *mst_port; | |
233 | }; | |
234 | ||
235 | typedef struct dpll { | |
236 | /* given values */ | |
237 | int n; | |
238 | int m1, m2; | |
239 | int p1, p2; | |
240 | /* derived values */ | |
241 | int dot; | |
242 | int vco; | |
243 | int m; | |
244 | int p; | |
245 | } intel_clock_t; | |
246 | ||
247 | struct intel_atomic_state { | |
248 | struct drm_atomic_state base; | |
249 | ||
250 | unsigned int cdclk; | |
251 | bool dpll_set; | |
252 | struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS]; | |
253 | struct intel_wm_config wm_config; | |
254 | }; | |
255 | ||
256 | struct intel_plane_state { | |
257 | struct drm_plane_state base; | |
258 | struct drm_rect src; | |
259 | struct drm_rect dst; | |
260 | struct drm_rect clip; | |
261 | bool visible; | |
262 | ||
263 | /* | |
264 | * scaler_id | |
265 | * = -1 : not using a scaler | |
266 | * >= 0 : using a scalers | |
267 | * | |
268 | * plane requiring a scaler: | |
269 | * - During check_plane, its bit is set in | |
270 | * crtc_state->scaler_state.scaler_users by calling helper function | |
271 | * update_scaler_plane. | |
272 | * - scaler_id indicates the scaler it got assigned. | |
273 | * | |
274 | * plane doesn't require a scaler: | |
275 | * - this can happen when scaling is no more required or plane simply | |
276 | * got disabled. | |
277 | * - During check_plane, corresponding bit is reset in | |
278 | * crtc_state->scaler_state.scaler_users by calling helper function | |
279 | * update_scaler_plane. | |
280 | */ | |
281 | int scaler_id; | |
282 | ||
283 | struct drm_intel_sprite_colorkey ckey; | |
284 | ||
285 | /* async flip related structures */ | |
286 | struct drm_i915_gem_request *wait_req; | |
287 | }; | |
288 | ||
289 | struct intel_initial_plane_config { | |
290 | struct intel_framebuffer *fb; | |
291 | unsigned int tiling; | |
292 | int size; | |
293 | u32 base; | |
294 | }; | |
295 | ||
296 | #define SKL_MIN_SRC_W 8 | |
297 | #define SKL_MAX_SRC_W 4096 | |
298 | #define SKL_MIN_SRC_H 8 | |
299 | #define SKL_MAX_SRC_H 4096 | |
300 | #define SKL_MIN_DST_W 8 | |
301 | #define SKL_MAX_DST_W 4096 | |
302 | #define SKL_MIN_DST_H 8 | |
303 | #define SKL_MAX_DST_H 4096 | |
304 | ||
305 | struct intel_scaler { | |
306 | int in_use; | |
307 | uint32_t mode; | |
308 | }; | |
309 | ||
310 | struct intel_crtc_scaler_state { | |
311 | #define SKL_NUM_SCALERS 2 | |
312 | struct intel_scaler scalers[SKL_NUM_SCALERS]; | |
313 | ||
314 | /* | |
315 | * scaler_users: keeps track of users requesting scalers on this crtc. | |
316 | * | |
317 | * If a bit is set, a user is using a scaler. | |
318 | * Here user can be a plane or crtc as defined below: | |
319 | * bits 0-30 - plane (bit position is index from drm_plane_index) | |
320 | * bit 31 - crtc | |
321 | * | |
322 | * Instead of creating a new index to cover planes and crtc, using | |
323 | * existing drm_plane_index for planes which is well less than 31 | |
324 | * planes and bit 31 for crtc. This should be fine to cover all | |
325 | * our platforms. | |
326 | * | |
327 | * intel_atomic_setup_scalers will setup available scalers to users | |
328 | * requesting scalers. It will gracefully fail if request exceeds | |
329 | * avilability. | |
330 | */ | |
331 | #define SKL_CRTC_INDEX 31 | |
332 | unsigned scaler_users; | |
333 | ||
334 | /* scaler used by crtc for panel fitting purpose */ | |
335 | int scaler_id; | |
336 | }; | |
337 | ||
338 | /* drm_mode->private_flags */ | |
339 | #define I915_MODE_FLAG_INHERITED 1 | |
340 | ||
341 | struct intel_pipe_wm { | |
342 | struct intel_wm_level wm[5]; | |
343 | uint32_t linetime; | |
344 | bool fbc_wm_enabled; | |
345 | bool pipe_enabled; | |
346 | bool sprites_enabled; | |
347 | bool sprites_scaled; | |
348 | }; | |
349 | ||
350 | struct skl_pipe_wm { | |
351 | struct skl_wm_level wm[8]; | |
352 | struct skl_wm_level trans_wm; | |
353 | uint32_t linetime; | |
354 | }; | |
355 | ||
356 | struct intel_crtc_state { | |
357 | struct drm_crtc_state base; | |
358 | ||
359 | /** | |
360 | * quirks - bitfield with hw state readout quirks | |
361 | * | |
362 | * For various reasons the hw state readout code might not be able to | |
363 | * completely faithfully read out the current state. These cases are | |
364 | * tracked with quirk flags so that fastboot and state checker can act | |
365 | * accordingly. | |
366 | */ | |
367 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ | |
368 | unsigned long quirks; | |
369 | ||
370 | bool update_pipe; | |
371 | ||
372 | /* Pipe source size (ie. panel fitter input size) | |
373 | * All planes will be positioned inside this space, | |
374 | * and get clipped at the edges. */ | |
375 | int pipe_src_w, pipe_src_h; | |
376 | ||
377 | /* Whether to set up the PCH/FDI. Note that we never allow sharing | |
378 | * between pch encoders and cpu encoders. */ | |
379 | bool has_pch_encoder; | |
380 | ||
381 | /* Are we sending infoframes on the attached port */ | |
382 | bool has_infoframe; | |
383 | ||
384 | /* CPU Transcoder for the pipe. Currently this can only differ from the | |
385 | * pipe on Haswell (where we have a special eDP transcoder). */ | |
386 | enum transcoder cpu_transcoder; | |
387 | ||
388 | /* | |
389 | * Use reduced/limited/broadcast rbg range, compressing from the full | |
390 | * range fed into the crtcs. | |
391 | */ | |
392 | bool limited_color_range; | |
393 | ||
394 | /* DP has a bunch of special case unfortunately, so mark the pipe | |
395 | * accordingly. */ | |
396 | bool has_dp_encoder; | |
397 | ||
398 | /* Whether we should send NULL infoframes. Required for audio. */ | |
399 | bool has_hdmi_sink; | |
400 | ||
401 | /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or | |
402 | * has_dp_encoder is set. */ | |
403 | bool has_audio; | |
404 | ||
405 | /* | |
406 | * Enable dithering, used when the selected pipe bpp doesn't match the | |
407 | * plane bpp. | |
408 | */ | |
409 | bool dither; | |
410 | ||
411 | /* Controls for the clock computation, to override various stages. */ | |
412 | bool clock_set; | |
413 | ||
414 | /* SDVO TV has a bunch of special case. To make multifunction encoders | |
415 | * work correctly, we need to track this at runtime.*/ | |
416 | bool sdvo_tv_clock; | |
417 | ||
418 | /* | |
419 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really | |
420 | * required. This is set in the 2nd loop of calling encoder's | |
421 | * ->compute_config if the first pick doesn't work out. | |
422 | */ | |
423 | bool bw_constrained; | |
424 | ||
425 | /* Settings for the intel dpll used on pretty much everything but | |
426 | * haswell. */ | |
427 | struct dpll dpll; | |
428 | ||
429 | /* Selected dpll when shared or DPLL_ID_PRIVATE. */ | |
430 | enum intel_dpll_id shared_dpll; | |
431 | ||
432 | /* | |
433 | * - PORT_CLK_SEL for DDI ports on HSW/BDW. | |
434 | * - enum skl_dpll on SKL | |
435 | */ | |
436 | uint32_t ddi_pll_sel; | |
437 | ||
438 | /* Actual register state of the dpll, for shared dpll cross-checking. */ | |
439 | struct intel_dpll_hw_state dpll_hw_state; | |
440 | ||
441 | int pipe_bpp; | |
442 | struct intel_link_m_n dp_m_n; | |
443 | ||
444 | /* m2_n2 for eDP downclock */ | |
445 | struct intel_link_m_n dp_m2_n2; | |
446 | bool has_drrs; | |
447 | ||
448 | /* | |
449 | * Frequence the dpll for the port should run at. Differs from the | |
450 | * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also | |
451 | * already multiplied by pixel_multiplier. | |
452 | */ | |
453 | int port_clock; | |
454 | ||
455 | /* Used by SDVO (and if we ever fix it, HDMI). */ | |
456 | unsigned pixel_multiplier; | |
457 | ||
458 | uint8_t lane_count; | |
459 | ||
460 | /* Panel fitter controls for gen2-gen4 + VLV */ | |
461 | struct { | |
462 | u32 control; | |
463 | u32 pgm_ratios; | |
464 | u32 lvds_border_bits; | |
465 | } gmch_pfit; | |
466 | ||
467 | /* Panel fitter placement and size for Ironlake+ */ | |
468 | struct { | |
469 | u32 pos; | |
470 | u32 size; | |
471 | bool enabled; | |
472 | bool force_thru; | |
473 | } pch_pfit; | |
474 | ||
475 | /* FDI configuration, only valid if has_pch_encoder is set. */ | |
476 | int fdi_lanes; | |
477 | struct intel_link_m_n fdi_m_n; | |
478 | ||
479 | bool ips_enabled; | |
480 | ||
481 | bool double_wide; | |
482 | ||
483 | bool dp_encoder_is_mst; | |
484 | int pbn; | |
485 | ||
486 | struct intel_crtc_scaler_state scaler_state; | |
487 | ||
488 | /* w/a for waiting 2 vblanks during crtc enable */ | |
489 | enum pipe hsw_workaround_pipe; | |
490 | ||
491 | /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */ | |
492 | bool disable_lp_wm; | |
493 | ||
494 | struct { | |
495 | /* | |
496 | * optimal watermarks, programmed post-vblank when this state | |
497 | * is committed | |
498 | */ | |
499 | union { | |
500 | struct intel_pipe_wm ilk; | |
501 | struct skl_pipe_wm skl; | |
502 | } optimal; | |
503 | } wm; | |
504 | }; | |
505 | ||
506 | struct vlv_wm_state { | |
507 | struct vlv_pipe_wm wm[3]; | |
508 | struct vlv_sr_wm sr[3]; | |
509 | uint8_t num_active_planes; | |
510 | uint8_t num_levels; | |
511 | uint8_t level; | |
512 | bool cxsr; | |
513 | }; | |
514 | ||
515 | struct intel_mmio_flip { | |
516 | struct work_struct work; | |
517 | struct drm_i915_private *i915; | |
518 | struct drm_i915_gem_request *req; | |
519 | struct intel_crtc *crtc; | |
520 | unsigned int rotation; | |
521 | }; | |
522 | ||
523 | /* | |
524 | * Tracking of operations that need to be performed at the beginning/end of an | |
525 | * atomic commit, outside the atomic section where interrupts are disabled. | |
526 | * These are generally operations that grab mutexes or might otherwise sleep | |
527 | * and thus can't be run with interrupts disabled. | |
528 | */ | |
529 | struct intel_crtc_atomic_commit { | |
530 | /* Sleepable operations to perform before commit */ | |
531 | bool disable_fbc; | |
532 | bool disable_ips; | |
533 | bool disable_cxsr; | |
534 | bool pre_disable_primary; | |
535 | bool update_wm_pre, update_wm_post; | |
536 | ||
537 | /* Sleepable operations to perform after commit */ | |
538 | unsigned fb_bits; | |
539 | bool wait_vblank; | |
540 | bool update_fbc; | |
541 | bool post_enable_primary; | |
542 | unsigned update_sprite_watermarks; | |
543 | }; | |
544 | ||
545 | struct intel_crtc { | |
546 | struct drm_crtc base; | |
547 | enum pipe pipe; | |
548 | enum plane plane; | |
549 | u8 lut_r[256], lut_g[256], lut_b[256]; | |
550 | /* | |
551 | * Whether the crtc and the connected output pipeline is active. Implies | |
552 | * that crtc->enabled is set, i.e. the current mode configuration has | |
553 | * some outputs connected to this crtc. | |
554 | */ | |
555 | bool active; | |
556 | unsigned long enabled_power_domains; | |
557 | bool lowfreq_avail; | |
558 | struct intel_overlay *overlay; | |
559 | struct intel_unpin_work *unpin_work; | |
560 | ||
561 | atomic_t unpin_work_count; | |
562 | ||
563 | /* Display surface base address adjustement for pageflips. Note that on | |
564 | * gen4+ this only adjusts up to a tile, offsets within a tile are | |
565 | * handled in the hw itself (with the TILEOFF register). */ | |
566 | unsigned long dspaddr_offset; | |
567 | int adjusted_x; | |
568 | int adjusted_y; | |
569 | ||
570 | struct drm_i915_gem_object *cursor_bo; | |
571 | uint32_t cursor_addr; | |
572 | uint32_t cursor_cntl; | |
573 | uint32_t cursor_size; | |
574 | uint32_t cursor_base; | |
575 | ||
576 | struct intel_crtc_state *config; | |
577 | ||
578 | /* reset counter value when the last flip was submitted */ | |
579 | unsigned int reset_counter; | |
580 | ||
581 | /* Access to these should be protected by dev_priv->irq_lock. */ | |
582 | bool cpu_fifo_underrun_disabled; | |
583 | bool pch_fifo_underrun_disabled; | |
584 | ||
585 | /* per-pipe watermark state */ | |
586 | struct { | |
587 | /* watermarks currently being used */ | |
588 | union { | |
589 | struct intel_pipe_wm ilk; | |
590 | struct skl_pipe_wm skl; | |
591 | } active; | |
592 | /* allow CxSR on this pipe */ | |
593 | bool cxsr_allowed; | |
594 | } wm; | |
595 | ||
596 | int scanline_offset; | |
597 | ||
598 | struct { | |
599 | unsigned start_vbl_count; | |
600 | ktime_t start_vbl_time; | |
601 | int min_vbl, max_vbl; | |
602 | int scanline_start; | |
603 | } debug; | |
604 | ||
605 | struct intel_crtc_atomic_commit atomic; | |
606 | ||
607 | /* scalers available on this crtc */ | |
608 | int num_scalers; | |
609 | ||
610 | struct vlv_wm_state wm_state; | |
611 | }; | |
612 | ||
613 | struct intel_plane_wm_parameters { | |
614 | uint32_t horiz_pixels; | |
615 | uint32_t vert_pixels; | |
616 | /* | |
617 | * For packed pixel formats: | |
618 | * bytes_per_pixel - holds bytes per pixel | |
619 | * For planar pixel formats: | |
620 | * bytes_per_pixel - holds bytes per pixel for uv-plane | |
621 | * y_bytes_per_pixel - holds bytes per pixel for y-plane | |
622 | */ | |
623 | uint8_t bytes_per_pixel; | |
624 | uint8_t y_bytes_per_pixel; | |
625 | bool enabled; | |
626 | bool scaled; | |
627 | u64 tiling; | |
628 | unsigned int rotation; | |
629 | uint16_t fifo_size; | |
630 | }; | |
631 | ||
632 | struct intel_plane { | |
633 | struct drm_plane base; | |
634 | int plane; | |
635 | enum pipe pipe; | |
636 | bool can_scale; | |
637 | int max_downscale; | |
638 | uint32_t frontbuffer_bit; | |
639 | ||
640 | /* Since we need to change the watermarks before/after | |
641 | * enabling/disabling the planes, we need to store the parameters here | |
642 | * as the other pieces of the struct may not reflect the values we want | |
643 | * for the watermark calculations. Currently only Haswell uses this. | |
644 | */ | |
645 | struct intel_plane_wm_parameters wm; | |
646 | ||
647 | /* | |
648 | * NOTE: Do not place new plane state fields here (e.g., when adding | |
649 | * new plane properties). New runtime state should now be placed in | |
650 | * the intel_plane_state structure and accessed via drm_plane->state. | |
651 | */ | |
652 | ||
653 | void (*update_plane)(struct drm_plane *plane, | |
654 | struct drm_crtc *crtc, | |
655 | struct drm_framebuffer *fb, | |
656 | int crtc_x, int crtc_y, | |
657 | unsigned int crtc_w, unsigned int crtc_h, | |
658 | uint32_t x, uint32_t y, | |
659 | uint32_t src_w, uint32_t src_h); | |
660 | void (*disable_plane)(struct drm_plane *plane, | |
661 | struct drm_crtc *crtc); | |
662 | int (*check_plane)(struct drm_plane *plane, | |
663 | struct intel_crtc_state *crtc_state, | |
664 | struct intel_plane_state *state); | |
665 | void (*commit_plane)(struct drm_plane *plane, | |
666 | struct intel_plane_state *state); | |
667 | }; | |
668 | ||
669 | struct intel_watermark_params { | |
670 | unsigned long fifo_size; | |
671 | unsigned long max_wm; | |
672 | unsigned long default_wm; | |
673 | unsigned long guard_size; | |
674 | unsigned long cacheline_size; | |
675 | }; | |
676 | ||
677 | struct cxsr_latency { | |
678 | int is_desktop; | |
679 | int is_ddr3; | |
680 | unsigned long fsb_freq; | |
681 | unsigned long mem_freq; | |
682 | unsigned long display_sr; | |
683 | unsigned long display_hpll_disable; | |
684 | unsigned long cursor_sr; | |
685 | unsigned long cursor_hpll_disable; | |
686 | }; | |
687 | ||
688 | #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base) | |
689 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) | |
690 | #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base) | |
691 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) | |
692 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) | |
693 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) | |
694 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) | |
695 | #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base) | |
696 | #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL) | |
697 | ||
698 | struct intel_hdmi { | |
699 | u32 hdmi_reg; | |
700 | int ddc_bus; | |
701 | bool limited_color_range; | |
702 | bool color_range_auto; | |
703 | bool has_hdmi_sink; | |
704 | bool has_audio; | |
705 | enum hdmi_force_audio force_audio; | |
706 | bool rgb_quant_range_selectable; | |
707 | enum hdmi_picture_aspect aspect_ratio; | |
708 | struct intel_connector *attached_connector; | |
709 | void (*write_infoframe)(struct drm_encoder *encoder, | |
710 | enum hdmi_infoframe_type type, | |
711 | const void *frame, ssize_t len); | |
712 | void (*set_infoframes)(struct drm_encoder *encoder, | |
713 | bool enable, | |
714 | const struct drm_display_mode *adjusted_mode); | |
715 | bool (*infoframe_enabled)(struct drm_encoder *encoder); | |
716 | }; | |
717 | ||
718 | struct intel_dp_mst_encoder; | |
719 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 | |
720 | ||
721 | /* | |
722 | * enum link_m_n_set: | |
723 | * When platform provides two set of M_N registers for dp, we can | |
724 | * program them and switch between them incase of DRRS. | |
725 | * But When only one such register is provided, we have to program the | |
726 | * required divider value on that registers itself based on the DRRS state. | |
727 | * | |
728 | * M1_N1 : Program dp_m_n on M1_N1 registers | |
729 | * dp_m2_n2 on M2_N2 registers (If supported) | |
730 | * | |
731 | * M2_N2 : Program dp_m2_n2 on M1_N1 registers | |
732 | * M2_N2 registers are not supported | |
733 | */ | |
734 | ||
735 | enum link_m_n_set { | |
736 | /* Sets the m1_n1 and m2_n2 */ | |
737 | M1_N1 = 0, | |
738 | M2_N2 | |
739 | }; | |
740 | ||
741 | struct intel_dp { | |
742 | uint32_t output_reg; | |
743 | uint32_t aux_ch_ctl_reg; | |
744 | uint32_t aux_ch_data_reg[5]; | |
745 | uint32_t DP; | |
746 | int link_rate; | |
747 | uint8_t lane_count; | |
748 | bool has_audio; | |
749 | enum hdmi_force_audio force_audio; | |
750 | bool limited_color_range; | |
751 | bool color_range_auto; | |
752 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; | |
753 | uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; | |
754 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; | |
755 | /* sink rates as reported by DP_SUPPORTED_LINK_RATES */ | |
756 | uint8_t num_sink_rates; | |
757 | int sink_rates[DP_MAX_SUPPORTED_RATES]; | |
758 | struct drm_dp_aux aux; | |
759 | uint8_t train_set[4]; | |
760 | int panel_power_up_delay; | |
761 | int panel_power_down_delay; | |
762 | int panel_power_cycle_delay; | |
763 | int backlight_on_delay; | |
764 | int backlight_off_delay; | |
765 | struct delayed_work panel_vdd_work; | |
766 | bool want_panel_vdd; | |
767 | unsigned long last_power_cycle; | |
768 | unsigned long last_power_on; | |
769 | unsigned long last_backlight_off; | |
770 | ||
771 | struct notifier_block edp_notifier; | |
772 | ||
773 | /* | |
774 | * Pipe whose power sequencer is currently locked into | |
775 | * this port. Only relevant on VLV/CHV. | |
776 | */ | |
777 | enum pipe pps_pipe; | |
778 | struct edp_power_seq pps_delays; | |
779 | ||
780 | bool can_mst; /* this port supports mst */ | |
781 | bool is_mst; | |
782 | int active_mst_links; | |
783 | /* connector directly attached - won't be use for modeset in mst world */ | |
784 | struct intel_connector *attached_connector; | |
785 | ||
786 | /* mst connector list */ | |
787 | struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; | |
788 | struct drm_dp_mst_topology_mgr mst_mgr; | |
789 | ||
790 | uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index); | |
791 | /* | |
792 | * This function returns the value we have to program the AUX_CTL | |
793 | * register with to kick off an AUX transaction. | |
794 | */ | |
795 | uint32_t (*get_aux_send_ctl)(struct intel_dp *dp, | |
796 | bool has_aux_irq, | |
797 | int send_bytes, | |
798 | uint32_t aux_clock_divider); | |
799 | ||
800 | /* This is called before a link training is starterd */ | |
801 | void (*prepare_link_retrain)(struct intel_dp *intel_dp); | |
802 | ||
803 | bool train_set_valid; | |
804 | ||
805 | /* Displayport compliance testing */ | |
806 | unsigned long compliance_test_type; | |
807 | unsigned long compliance_test_data; | |
808 | bool compliance_test_active; | |
809 | }; | |
810 | ||
811 | struct intel_digital_port { | |
812 | struct intel_encoder base; | |
813 | enum port port; | |
814 | u32 saved_port_bits; | |
815 | struct intel_dp dp; | |
816 | struct intel_hdmi hdmi; | |
817 | enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool); | |
818 | bool release_cl2_override; | |
819 | }; | |
820 | ||
821 | struct intel_dp_mst_encoder { | |
822 | struct intel_encoder base; | |
823 | enum pipe pipe; | |
824 | struct intel_digital_port *primary; | |
825 | void *port; /* store this opaque as its illegal to dereference it */ | |
826 | }; | |
827 | ||
828 | static inline enum dpio_channel | |
829 | vlv_dport_to_channel(struct intel_digital_port *dport) | |
830 | { | |
831 | switch (dport->port) { | |
832 | case PORT_B: | |
833 | case PORT_D: | |
834 | return DPIO_CH0; | |
835 | case PORT_C: | |
836 | return DPIO_CH1; | |
837 | default: | |
838 | BUG(); | |
839 | } | |
840 | } | |
841 | ||
842 | static inline enum dpio_phy | |
843 | vlv_dport_to_phy(struct intel_digital_port *dport) | |
844 | { | |
845 | switch (dport->port) { | |
846 | case PORT_B: | |
847 | case PORT_C: | |
848 | return DPIO_PHY0; | |
849 | case PORT_D: | |
850 | return DPIO_PHY1; | |
851 | default: | |
852 | BUG(); | |
853 | } | |
854 | } | |
855 | ||
856 | static inline enum dpio_channel | |
857 | vlv_pipe_to_channel(enum pipe pipe) | |
858 | { | |
859 | switch (pipe) { | |
860 | case PIPE_A: | |
861 | case PIPE_C: | |
862 | return DPIO_CH0; | |
863 | case PIPE_B: | |
864 | return DPIO_CH1; | |
865 | default: | |
866 | BUG(); | |
867 | } | |
868 | } | |
869 | ||
870 | static inline struct drm_crtc * | |
871 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) | |
872 | { | |
873 | struct drm_i915_private *dev_priv = dev->dev_private; | |
874 | return dev_priv->pipe_to_crtc_mapping[pipe]; | |
875 | } | |
876 | ||
877 | static inline struct drm_crtc * | |
878 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) | |
879 | { | |
880 | struct drm_i915_private *dev_priv = dev->dev_private; | |
881 | return dev_priv->plane_to_crtc_mapping[plane]; | |
882 | } | |
883 | ||
884 | struct intel_unpin_work { | |
885 | struct work_struct work; | |
886 | struct drm_crtc *crtc; | |
887 | struct drm_framebuffer *old_fb; | |
888 | struct drm_i915_gem_object *pending_flip_obj; | |
889 | struct drm_pending_vblank_event *event; | |
890 | atomic_t pending; | |
891 | #define INTEL_FLIP_INACTIVE 0 | |
892 | #define INTEL_FLIP_PENDING 1 | |
893 | #define INTEL_FLIP_COMPLETE 2 | |
894 | u32 flip_count; | |
895 | u32 gtt_offset; | |
896 | struct drm_i915_gem_request *flip_queued_req; | |
897 | u32 flip_queued_vblank; | |
898 | u32 flip_ready_vblank; | |
899 | bool enable_stall_check; | |
900 | }; | |
901 | ||
902 | struct intel_load_detect_pipe { | |
903 | struct drm_framebuffer *release_fb; | |
904 | bool load_detect_temp; | |
905 | int dpms_mode; | |
906 | }; | |
907 | ||
908 | static inline struct intel_encoder * | |
909 | intel_attached_encoder(struct drm_connector *connector) | |
910 | { | |
911 | return to_intel_connector(connector)->encoder; | |
912 | } | |
913 | ||
914 | static inline struct intel_digital_port * | |
915 | enc_to_dig_port(struct drm_encoder *encoder) | |
916 | { | |
917 | return container_of(encoder, struct intel_digital_port, base.base); | |
918 | } | |
919 | ||
920 | static inline struct intel_dp_mst_encoder * | |
921 | enc_to_mst(struct drm_encoder *encoder) | |
922 | { | |
923 | return container_of(encoder, struct intel_dp_mst_encoder, base.base); | |
924 | } | |
925 | ||
926 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) | |
927 | { | |
928 | return &enc_to_dig_port(encoder)->dp; | |
929 | } | |
930 | ||
931 | static inline struct intel_digital_port * | |
932 | dp_to_dig_port(struct intel_dp *intel_dp) | |
933 | { | |
934 | return container_of(intel_dp, struct intel_digital_port, dp); | |
935 | } | |
936 | ||
937 | static inline struct intel_digital_port * | |
938 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) | |
939 | { | |
940 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); | |
941 | } | |
942 | ||
943 | /* | |
944 | * Returns the number of planes for this pipe, ie the number of sprites + 1 | |
945 | * (primary plane). This doesn't count the cursor plane then. | |
946 | */ | |
947 | static inline unsigned int intel_num_planes(struct intel_crtc *crtc) | |
948 | { | |
949 | return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1; | |
950 | } | |
951 | ||
952 | /* intel_fifo_underrun.c */ | |
953 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, | |
954 | enum pipe pipe, bool enable); | |
955 | bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, | |
956 | enum transcoder pch_transcoder, | |
957 | bool enable); | |
958 | void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, | |
959 | enum pipe pipe); | |
960 | void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, | |
961 | enum transcoder pch_transcoder); | |
962 | void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv); | |
963 | void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv); | |
964 | ||
965 | /* i915_irq.c */ | |
966 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
967 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
968 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
969 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
970 | void gen6_reset_rps_interrupts(struct drm_device *dev); | |
971 | void gen6_enable_rps_interrupts(struct drm_device *dev); | |
972 | void gen6_disable_rps_interrupts(struct drm_device *dev); | |
973 | u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask); | |
974 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv); | |
975 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv); | |
976 | static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) | |
977 | { | |
978 | /* | |
979 | * We only use drm_irq_uninstall() at unload and VT switch, so | |
980 | * this is the only thing we need to check. | |
981 | */ | |
982 | return dev_priv->pm.irqs_enabled; | |
983 | } | |
984 | ||
985 | int intel_get_crtc_scanline(struct intel_crtc *crtc); | |
986 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, | |
987 | unsigned int pipe_mask); | |
988 | ||
989 | /* intel_crt.c */ | |
990 | void intel_crt_init(struct drm_device *dev); | |
991 | ||
992 | ||
993 | /* intel_ddi.c */ | |
994 | void intel_ddi_clk_select(struct intel_encoder *encoder, | |
995 | const struct intel_crtc_state *pipe_config); | |
996 | void intel_prepare_ddi(struct drm_device *dev); | |
997 | void hsw_fdi_link_train(struct drm_crtc *crtc); | |
998 | void intel_ddi_init(struct drm_device *dev, enum port port); | |
999 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); | |
1000 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); | |
1001 | void intel_ddi_pll_init(struct drm_device *dev); | |
1002 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); | |
1003 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, | |
1004 | enum transcoder cpu_transcoder); | |
1005 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); | |
1006 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); | |
1007 | bool intel_ddi_pll_select(struct intel_crtc *crtc, | |
1008 | struct intel_crtc_state *crtc_state); | |
1009 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); | |
1010 | void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp); | |
1011 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); | |
1012 | void intel_ddi_fdi_disable(struct drm_crtc *crtc); | |
1013 | void intel_ddi_get_config(struct intel_encoder *encoder, | |
1014 | struct intel_crtc_state *pipe_config); | |
1015 | struct intel_encoder * | |
1016 | intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state); | |
1017 | ||
1018 | void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder); | |
1019 | void intel_ddi_clock_get(struct intel_encoder *encoder, | |
1020 | struct intel_crtc_state *pipe_config); | |
1021 | void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state); | |
1022 | uint32_t ddi_signal_levels(struct intel_dp *intel_dp); | |
1023 | ||
1024 | /* intel_frontbuffer.c */ | |
1025 | void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, | |
1026 | enum fb_op_origin origin); | |
1027 | void intel_frontbuffer_flip_prepare(struct drm_device *dev, | |
1028 | unsigned frontbuffer_bits); | |
1029 | void intel_frontbuffer_flip_complete(struct drm_device *dev, | |
1030 | unsigned frontbuffer_bits); | |
1031 | void intel_frontbuffer_flip(struct drm_device *dev, | |
1032 | unsigned frontbuffer_bits); | |
1033 | unsigned int intel_fb_align_height(struct drm_device *dev, | |
1034 | unsigned int height, | |
1035 | uint32_t pixel_format, | |
1036 | uint64_t fb_format_modifier); | |
1037 | void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire, | |
1038 | enum fb_op_origin origin); | |
1039 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, | |
1040 | uint32_t pixel_format); | |
1041 | ||
1042 | /* intel_audio.c */ | |
1043 | void intel_init_audio(struct drm_device *dev); | |
1044 | void intel_audio_codec_enable(struct intel_encoder *encoder); | |
1045 | void intel_audio_codec_disable(struct intel_encoder *encoder); | |
1046 | void i915_audio_component_init(struct drm_i915_private *dev_priv); | |
1047 | void i915_audio_component_cleanup(struct drm_i915_private *dev_priv); | |
1048 | ||
1049 | /* intel_display.c */ | |
1050 | extern const struct drm_plane_funcs intel_plane_funcs; | |
1051 | bool intel_has_pending_fb_unpin(struct drm_device *dev); | |
1052 | int intel_pch_rawclk(struct drm_device *dev); | |
1053 | int intel_hrawclk(struct drm_device *dev); | |
1054 | void intel_mark_busy(struct drm_device *dev); | |
1055 | void intel_mark_idle(struct drm_device *dev); | |
1056 | void intel_crtc_restore_mode(struct drm_crtc *crtc); | |
1057 | int intel_display_suspend(struct drm_device *dev); | |
1058 | void intel_encoder_destroy(struct drm_encoder *encoder); | |
1059 | int intel_connector_init(struct intel_connector *); | |
1060 | struct intel_connector *intel_connector_alloc(void); | |
1061 | bool intel_connector_get_hw_state(struct intel_connector *connector); | |
1062 | void intel_connector_attach_encoder(struct intel_connector *connector, | |
1063 | struct intel_encoder *encoder); | |
1064 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector); | |
1065 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
1066 | struct drm_crtc *crtc); | |
1067 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector); | |
1068 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, | |
1069 | struct drm_file *file_priv); | |
1070 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, | |
1071 | enum pipe pipe); | |
1072 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type); | |
1073 | static inline void | |
1074 | intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
1075 | { | |
1076 | drm_wait_one_vblank(dev, pipe); | |
1077 | } | |
1078 | static inline void | |
1079 | intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe) | |
1080 | { | |
1081 | const struct intel_crtc *crtc = | |
1082 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
1083 | ||
1084 | if (crtc->active) | |
1085 | intel_wait_for_vblank(dev, pipe); | |
1086 | } | |
1087 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); | |
1088 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, | |
1089 | struct intel_digital_port *dport, | |
1090 | unsigned int expected_mask); | |
1091 | bool intel_get_load_detect_pipe(struct drm_connector *connector, | |
1092 | struct drm_display_mode *mode, | |
1093 | struct intel_load_detect_pipe *old, | |
1094 | struct drm_modeset_acquire_ctx *ctx); | |
1095 | void intel_release_load_detect_pipe(struct drm_connector *connector, | |
1096 | struct intel_load_detect_pipe *old, | |
1097 | struct drm_modeset_acquire_ctx *ctx); | |
1098 | int intel_pin_and_fence_fb_obj(struct drm_plane *plane, | |
1099 | struct drm_framebuffer *fb, | |
1100 | const struct drm_plane_state *plane_state); | |
1101 | struct drm_framebuffer * | |
1102 | __intel_framebuffer_create(struct drm_device *dev, | |
1103 | struct drm_mode_fb_cmd2 *mode_cmd, | |
1104 | struct drm_i915_gem_object *obj); | |
1105 | void intel_prepare_page_flip(struct drm_device *dev, int plane); | |
1106 | void intel_finish_page_flip(struct drm_device *dev, int pipe); | |
1107 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane); | |
1108 | void intel_check_page_flip(struct drm_device *dev, int pipe); | |
1109 | int intel_prepare_plane_fb(struct drm_plane *plane, | |
1110 | const struct drm_plane_state *new_state); | |
1111 | void intel_cleanup_plane_fb(struct drm_plane *plane, | |
1112 | const struct drm_plane_state *old_state); | |
1113 | int intel_plane_atomic_get_property(struct drm_plane *plane, | |
1114 | const struct drm_plane_state *state, | |
1115 | struct drm_property *property, | |
1116 | uint64_t *val); | |
1117 | int intel_plane_atomic_set_property(struct drm_plane *plane, | |
1118 | struct drm_plane_state *state, | |
1119 | struct drm_property *property, | |
1120 | uint64_t val); | |
1121 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, | |
1122 | struct drm_plane_state *plane_state); | |
1123 | ||
1124 | unsigned int | |
1125 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, | |
1126 | uint64_t fb_format_modifier, unsigned int plane); | |
1127 | ||
1128 | static inline bool | |
1129 | intel_rotation_90_or_270(unsigned int rotation) | |
1130 | { | |
1131 | return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270)); | |
1132 | } | |
1133 | ||
1134 | void intel_create_rotation_property(struct drm_device *dev, | |
1135 | struct intel_plane *plane); | |
1136 | ||
1137 | /* shared dpll functions */ | |
1138 | struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc); | |
1139 | void assert_shared_dpll(struct drm_i915_private *dev_priv, | |
1140 | struct intel_shared_dpll *pll, | |
1141 | bool state); | |
1142 | #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) | |
1143 | #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) | |
1144 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, | |
1145 | struct intel_crtc_state *state); | |
1146 | ||
1147 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
1148 | const struct dpll *dpll); | |
1149 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe); | |
1150 | ||
1151 | /* modesetting asserts */ | |
1152 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, | |
1153 | enum pipe pipe); | |
1154 | void assert_pll(struct drm_i915_private *dev_priv, | |
1155 | enum pipe pipe, bool state); | |
1156 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
1157 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
1158 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, | |
1159 | enum pipe pipe, bool state); | |
1160 | #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) | |
1161 | #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) | |
1162 | void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); | |
1163 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) | |
1164 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) | |
1165 | unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv, | |
1166 | int *x, int *y, | |
1167 | unsigned int tiling_mode, | |
1168 | unsigned int bpp, | |
1169 | unsigned int pitch); | |
1170 | void intel_prepare_reset(struct drm_device *dev); | |
1171 | void intel_finish_reset(struct drm_device *dev); | |
1172 | void hsw_enable_pc8(struct drm_i915_private *dev_priv); | |
1173 | void hsw_disable_pc8(struct drm_i915_private *dev_priv); | |
1174 | void broxton_init_cdclk(struct drm_device *dev); | |
1175 | void broxton_uninit_cdclk(struct drm_device *dev); | |
1176 | void broxton_ddi_phy_init(struct drm_device *dev); | |
1177 | void broxton_ddi_phy_uninit(struct drm_device *dev); | |
1178 | void bxt_enable_dc9(struct drm_i915_private *dev_priv); | |
1179 | void bxt_disable_dc9(struct drm_i915_private *dev_priv); | |
1180 | void skl_init_cdclk(struct drm_i915_private *dev_priv); | |
1181 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv); | |
1182 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv); | |
1183 | void skl_enable_dc6(struct drm_i915_private *dev_priv); | |
1184 | void skl_disable_dc6(struct drm_i915_private *dev_priv); | |
1185 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
1186 | struct intel_crtc_state *pipe_config); | |
1187 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n); | |
1188 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); | |
1189 | void | |
1190 | ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, | |
1191 | int dotclock); | |
1192 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, | |
1193 | intel_clock_t *best_clock); | |
1194 | int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock); | |
1195 | ||
1196 | bool intel_crtc_active(struct drm_crtc *crtc); | |
1197 | void hsw_enable_ips(struct intel_crtc *crtc); | |
1198 | void hsw_disable_ips(struct intel_crtc *crtc); | |
1199 | enum intel_display_power_domain | |
1200 | intel_display_port_power_domain(struct intel_encoder *intel_encoder); | |
1201 | enum intel_display_power_domain | |
1202 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder); | |
1203 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, | |
1204 | struct intel_crtc_state *pipe_config); | |
1205 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file); | |
1206 | ||
1207 | int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state); | |
1208 | int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state); | |
1209 | ||
1210 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, | |
1211 | struct drm_i915_gem_object *obj, | |
1212 | unsigned int plane); | |
1213 | ||
1214 | u32 skl_plane_ctl_format(uint32_t pixel_format); | |
1215 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier); | |
1216 | u32 skl_plane_ctl_rotation(unsigned int rotation); | |
1217 | ||
1218 | /* intel_csr.c */ | |
1219 | void intel_csr_ucode_init(struct drm_i915_private *); | |
1220 | void intel_csr_load_program(struct drm_i915_private *); | |
1221 | void intel_csr_ucode_fini(struct drm_i915_private *); | |
1222 | ||
1223 | /* intel_dp.c */ | |
1224 | void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); | |
1225 | bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, | |
1226 | struct intel_connector *intel_connector); | |
1227 | void intel_dp_set_link_params(struct intel_dp *intel_dp, | |
1228 | const struct intel_crtc_state *pipe_config); | |
1229 | void intel_dp_start_link_train(struct intel_dp *intel_dp); | |
1230 | void intel_dp_stop_link_train(struct intel_dp *intel_dp); | |
1231 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); | |
1232 | void intel_dp_encoder_destroy(struct drm_encoder *encoder); | |
1233 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); | |
1234 | bool intel_dp_compute_config(struct intel_encoder *encoder, | |
1235 | struct intel_crtc_state *pipe_config); | |
1236 | bool intel_dp_is_edp(struct drm_device *dev, enum port port); | |
1237 | enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, | |
1238 | bool long_hpd); | |
1239 | void intel_edp_backlight_on(struct intel_dp *intel_dp); | |
1240 | void intel_edp_backlight_off(struct intel_dp *intel_dp); | |
1241 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); | |
1242 | void intel_edp_panel_on(struct intel_dp *intel_dp); | |
1243 | void intel_edp_panel_off(struct intel_dp *intel_dp); | |
1244 | void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector); | |
1245 | void intel_dp_mst_suspend(struct drm_device *dev); | |
1246 | void intel_dp_mst_resume(struct drm_device *dev); | |
1247 | int intel_dp_max_link_rate(struct intel_dp *intel_dp); | |
1248 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); | |
1249 | void intel_dp_hot_plug(struct intel_encoder *intel_encoder); | |
1250 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv); | |
1251 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes); | |
1252 | void intel_plane_destroy(struct drm_plane *plane); | |
1253 | void intel_edp_drrs_enable(struct intel_dp *intel_dp); | |
1254 | void intel_edp_drrs_disable(struct intel_dp *intel_dp); | |
1255 | void intel_edp_drrs_invalidate(struct drm_device *dev, | |
1256 | unsigned frontbuffer_bits); | |
1257 | void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits); | |
1258 | bool intel_digital_port_connected(struct drm_i915_private *dev_priv, | |
1259 | struct intel_digital_port *port); | |
1260 | void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config); | |
1261 | ||
1262 | void | |
1263 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, | |
1264 | uint8_t dp_train_pat); | |
1265 | void | |
1266 | intel_dp_set_signal_levels(struct intel_dp *intel_dp); | |
1267 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp); | |
1268 | uint8_t | |
1269 | intel_dp_voltage_max(struct intel_dp *intel_dp); | |
1270 | uint8_t | |
1271 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing); | |
1272 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, | |
1273 | uint8_t *link_bw, uint8_t *rate_select); | |
1274 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp); | |
1275 | bool | |
1276 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]); | |
1277 | ||
1278 | /* intel_dp_mst.c */ | |
1279 | int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); | |
1280 | void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); | |
1281 | /* intel_dsi.c */ | |
1282 | void intel_dsi_init(struct drm_device *dev); | |
1283 | ||
1284 | ||
1285 | /* intel_dvo.c */ | |
1286 | void intel_dvo_init(struct drm_device *dev); | |
1287 | ||
1288 | ||
1289 | /* legacy fbdev emulation in intel_fbdev.c */ | |
1290 | #ifdef CONFIG_DRM_FBDEV_EMULATION | |
1291 | extern int intel_fbdev_init(struct drm_device *dev); | |
1292 | extern void intel_fbdev_initial_config_async(struct drm_device *dev); | |
1293 | extern void intel_fbdev_fini(struct drm_device *dev); | |
1294 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); | |
1295 | extern void intel_fbdev_output_poll_changed(struct drm_device *dev); | |
1296 | extern void intel_fbdev_restore_mode(struct drm_device *dev); | |
1297 | #else | |
1298 | static inline int intel_fbdev_init(struct drm_device *dev) | |
1299 | { | |
1300 | return 0; | |
1301 | } | |
1302 | ||
1303 | static inline void intel_fbdev_initial_config_async(struct drm_device *dev) | |
1304 | { | |
1305 | } | |
1306 | ||
1307 | static inline void intel_fbdev_fini(struct drm_device *dev) | |
1308 | { | |
1309 | } | |
1310 | ||
1311 | static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) | |
1312 | { | |
1313 | } | |
1314 | ||
1315 | static inline void intel_fbdev_restore_mode(struct drm_device *dev) | |
1316 | { | |
1317 | } | |
1318 | #endif | |
1319 | ||
1320 | /* intel_fbc.c */ | |
1321 | bool intel_fbc_enabled(struct drm_i915_private *dev_priv); | |
1322 | void intel_fbc_update(struct drm_i915_private *dev_priv); | |
1323 | void intel_fbc_init(struct drm_i915_private *dev_priv); | |
1324 | void intel_fbc_disable(struct drm_i915_private *dev_priv); | |
1325 | void intel_fbc_disable_crtc(struct intel_crtc *crtc); | |
1326 | void intel_fbc_invalidate(struct drm_i915_private *dev_priv, | |
1327 | unsigned int frontbuffer_bits, | |
1328 | enum fb_op_origin origin); | |
1329 | void intel_fbc_flush(struct drm_i915_private *dev_priv, | |
1330 | unsigned int frontbuffer_bits, enum fb_op_origin origin); | |
1331 | void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv); | |
1332 | ||
1333 | /* intel_hdmi.c */ | |
1334 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port); | |
1335 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, | |
1336 | struct intel_connector *intel_connector); | |
1337 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); | |
1338 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, | |
1339 | struct intel_crtc_state *pipe_config); | |
1340 | ||
1341 | ||
1342 | /* intel_lvds.c */ | |
1343 | void intel_lvds_init(struct drm_device *dev); | |
1344 | bool intel_is_dual_link_lvds(struct drm_device *dev); | |
1345 | ||
1346 | ||
1347 | /* intel_modes.c */ | |
1348 | int intel_connector_update_modes(struct drm_connector *connector, | |
1349 | struct edid *edid); | |
1350 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); | |
1351 | void intel_attach_force_audio_property(struct drm_connector *connector); | |
1352 | void intel_attach_broadcast_rgb_property(struct drm_connector *connector); | |
1353 | void intel_attach_aspect_ratio_property(struct drm_connector *connector); | |
1354 | ||
1355 | ||
1356 | /* intel_overlay.c */ | |
1357 | void intel_setup_overlay(struct drm_device *dev); | |
1358 | void intel_cleanup_overlay(struct drm_device *dev); | |
1359 | int intel_overlay_switch_off(struct intel_overlay *overlay); | |
1360 | int intel_overlay_put_image(struct drm_device *dev, void *data, | |
1361 | struct drm_file *file_priv); | |
1362 | int intel_overlay_attrs(struct drm_device *dev, void *data, | |
1363 | struct drm_file *file_priv); | |
1364 | void intel_overlay_reset(struct drm_i915_private *dev_priv); | |
1365 | ||
1366 | ||
1367 | /* intel_panel.c */ | |
1368 | int intel_panel_init(struct intel_panel *panel, | |
1369 | struct drm_display_mode *fixed_mode, | |
1370 | struct drm_display_mode *downclock_mode); | |
1371 | void intel_panel_fini(struct intel_panel *panel); | |
1372 | void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, | |
1373 | struct drm_display_mode *adjusted_mode); | |
1374 | void intel_pch_panel_fitting(struct intel_crtc *crtc, | |
1375 | struct intel_crtc_state *pipe_config, | |
1376 | int fitting_mode); | |
1377 | void intel_gmch_panel_fitting(struct intel_crtc *crtc, | |
1378 | struct intel_crtc_state *pipe_config, | |
1379 | int fitting_mode); | |
1380 | void intel_panel_set_backlight_acpi(struct intel_connector *connector, | |
1381 | u32 level, u32 max); | |
1382 | int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe); | |
1383 | void intel_panel_enable_backlight(struct intel_connector *connector); | |
1384 | void intel_panel_disable_backlight(struct intel_connector *connector); | |
1385 | void intel_panel_destroy_backlight(struct drm_connector *connector); | |
1386 | enum drm_connector_status intel_panel_detect(struct drm_device *dev); | |
1387 | extern struct drm_display_mode *intel_find_panel_downclock( | |
1388 | struct drm_device *dev, | |
1389 | struct drm_display_mode *fixed_mode, | |
1390 | struct drm_connector *connector); | |
1391 | void intel_backlight_register(struct drm_device *dev); | |
1392 | void intel_backlight_unregister(struct drm_device *dev); | |
1393 | ||
1394 | ||
1395 | /* intel_psr.c */ | |
1396 | void intel_psr_enable(struct intel_dp *intel_dp); | |
1397 | void intel_psr_disable(struct intel_dp *intel_dp); | |
1398 | void intel_psr_invalidate(struct drm_device *dev, | |
1399 | unsigned frontbuffer_bits); | |
1400 | void intel_psr_flush(struct drm_device *dev, | |
1401 | unsigned frontbuffer_bits, | |
1402 | enum fb_op_origin origin); | |
1403 | void intel_psr_init(struct drm_device *dev); | |
1404 | void intel_psr_single_frame_update(struct drm_device *dev, | |
1405 | unsigned frontbuffer_bits); | |
1406 | ||
1407 | /* intel_runtime_pm.c */ | |
1408 | int intel_power_domains_init(struct drm_i915_private *); | |
1409 | void intel_power_domains_fini(struct drm_i915_private *); | |
1410 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); | |
1411 | void intel_power_domains_suspend(struct drm_i915_private *dev_priv); | |
1412 | void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv); | |
1413 | void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv); | |
1414 | void intel_runtime_pm_enable(struct drm_i915_private *dev_priv); | |
1415 | ||
1416 | bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, | |
1417 | enum intel_display_power_domain domain); | |
1418 | bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, | |
1419 | enum intel_display_power_domain domain); | |
1420 | void intel_display_power_get(struct drm_i915_private *dev_priv, | |
1421 | enum intel_display_power_domain domain); | |
1422 | void intel_display_power_put(struct drm_i915_private *dev_priv, | |
1423 | enum intel_display_power_domain domain); | |
1424 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv); | |
1425 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv); | |
1426 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv); | |
1427 | ||
1428 | void intel_display_set_init_power(struct drm_i915_private *dev, bool enable); | |
1429 | ||
1430 | void chv_phy_powergate_lanes(struct intel_encoder *encoder, | |
1431 | bool override, unsigned int mask); | |
1432 | bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, | |
1433 | enum dpio_channel ch, bool override); | |
1434 | ||
1435 | ||
1436 | /* intel_pm.c */ | |
1437 | void intel_init_clock_gating(struct drm_device *dev); | |
1438 | void intel_suspend_hw(struct drm_device *dev); | |
1439 | int ilk_wm_max_level(const struct drm_device *dev); | |
1440 | void intel_update_watermarks(struct drm_crtc *crtc); | |
1441 | void intel_init_pm(struct drm_device *dev); | |
1442 | void intel_pm_setup(struct drm_device *dev); | |
1443 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv); | |
1444 | void intel_gpu_ips_teardown(void); | |
1445 | void intel_init_gt_powersave(struct drm_device *dev); | |
1446 | void intel_cleanup_gt_powersave(struct drm_device *dev); | |
1447 | void intel_enable_gt_powersave(struct drm_device *dev); | |
1448 | void intel_disable_gt_powersave(struct drm_device *dev); | |
1449 | void intel_suspend_gt_powersave(struct drm_device *dev); | |
1450 | void intel_reset_gt_powersave(struct drm_device *dev); | |
1451 | void gen6_update_ring_freq(struct drm_device *dev); | |
1452 | void gen6_rps_busy(struct drm_i915_private *dev_priv); | |
1453 | void gen6_rps_reset_ei(struct drm_i915_private *dev_priv); | |
1454 | void gen6_rps_idle(struct drm_i915_private *dev_priv); | |
1455 | void gen6_rps_boost(struct drm_i915_private *dev_priv, | |
1456 | struct intel_rps_client *rps, | |
1457 | unsigned long submitted); | |
1458 | void intel_queue_rps_boost_for_request(struct drm_device *dev, | |
1459 | struct drm_i915_gem_request *req); | |
1460 | void vlv_wm_get_hw_state(struct drm_device *dev); | |
1461 | void ilk_wm_get_hw_state(struct drm_device *dev); | |
1462 | void skl_wm_get_hw_state(struct drm_device *dev); | |
1463 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, | |
1464 | struct skl_ddb_allocation *ddb /* out */); | |
1465 | uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config); | |
1466 | ||
1467 | /* intel_sdvo.c */ | |
1468 | bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, enum port port); | |
1469 | ||
1470 | ||
1471 | /* intel_sprite.c */ | |
1472 | int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); | |
1473 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, | |
1474 | struct drm_file *file_priv); | |
1475 | void intel_pipe_update_start(struct intel_crtc *crtc); | |
1476 | void intel_pipe_update_end(struct intel_crtc *crtc); | |
1477 | ||
1478 | /* intel_tv.c */ | |
1479 | void intel_tv_init(struct drm_device *dev); | |
1480 | ||
1481 | /* intel_atomic.c */ | |
1482 | int intel_connector_atomic_get_property(struct drm_connector *connector, | |
1483 | const struct drm_connector_state *state, | |
1484 | struct drm_property *property, | |
1485 | uint64_t *val); | |
1486 | struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc); | |
1487 | void intel_crtc_destroy_state(struct drm_crtc *crtc, | |
1488 | struct drm_crtc_state *state); | |
1489 | struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev); | |
1490 | void intel_atomic_state_clear(struct drm_atomic_state *); | |
1491 | struct intel_shared_dpll_config * | |
1492 | intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s); | |
1493 | ||
1494 | static inline struct intel_crtc_state * | |
1495 | intel_atomic_get_crtc_state(struct drm_atomic_state *state, | |
1496 | struct intel_crtc *crtc) | |
1497 | { | |
1498 | struct drm_crtc_state *crtc_state; | |
1499 | crtc_state = drm_atomic_get_crtc_state(state, &crtc->base); | |
1500 | if (IS_ERR(crtc_state)) | |
1501 | return ERR_CAST(crtc_state); | |
1502 | ||
1503 | return to_intel_crtc_state(crtc_state); | |
1504 | } | |
1505 | int intel_atomic_setup_scalers(struct drm_device *dev, | |
1506 | struct intel_crtc *intel_crtc, | |
1507 | struct intel_crtc_state *crtc_state); | |
1508 | ||
1509 | /* intel_atomic_plane.c */ | |
1510 | struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane); | |
1511 | struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane); | |
1512 | void intel_plane_destroy_state(struct drm_plane *plane, | |
1513 | struct drm_plane_state *state); | |
1514 | extern const struct drm_plane_helper_funcs intel_plane_helper_funcs; | |
1515 | ||
1516 | #endif /* __INTEL_DRV_H__ */ |