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1 | /* | |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
30 | #include <acpi/button.h> | |
31 | #include <linux/dmi.h> | |
32 | #include <linux/i2c.h> | |
33 | #include <linux/slab.h> | |
34 | #include <linux/vga_switcheroo.h> | |
35 | #include <drm/drmP.h> | |
36 | #include <drm/drm_atomic_helper.h> | |
37 | #include <drm/drm_crtc.h> | |
38 | #include <drm/drm_edid.h> | |
39 | #include "intel_drv.h" | |
40 | #include <drm/i915_drm.h> | |
41 | #include "i915_drv.h" | |
42 | #include <linux/acpi.h> | |
43 | ||
44 | /* Private structure for the integrated LVDS support */ | |
45 | struct intel_lvds_connector { | |
46 | struct intel_connector base; | |
47 | ||
48 | struct notifier_block lid_notifier; | |
49 | }; | |
50 | ||
51 | struct intel_lvds_pps { | |
52 | /* 100us units */ | |
53 | int t1_t2; | |
54 | int t3; | |
55 | int t4; | |
56 | int t5; | |
57 | int tx; | |
58 | ||
59 | int divider; | |
60 | ||
61 | int port; | |
62 | bool powerdown_on_reset; | |
63 | }; | |
64 | ||
65 | struct intel_lvds_encoder { | |
66 | struct intel_encoder base; | |
67 | ||
68 | bool is_dual_link; | |
69 | i915_reg_t reg; | |
70 | u32 a3_power; | |
71 | ||
72 | struct intel_lvds_pps init_pps; | |
73 | u32 init_lvds_val; | |
74 | ||
75 | struct intel_lvds_connector *attached_connector; | |
76 | }; | |
77 | ||
78 | static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) | |
79 | { | |
80 | return container_of(encoder, struct intel_lvds_encoder, base.base); | |
81 | } | |
82 | ||
83 | static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector) | |
84 | { | |
85 | return container_of(connector, struct intel_lvds_connector, base.base); | |
86 | } | |
87 | ||
88 | static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, | |
89 | enum pipe *pipe) | |
90 | { | |
91 | struct drm_device *dev = encoder->base.dev; | |
92 | struct drm_i915_private *dev_priv = to_i915(dev); | |
93 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
94 | u32 tmp; | |
95 | bool ret; | |
96 | ||
97 | if (!intel_display_power_get_if_enabled(dev_priv, | |
98 | encoder->power_domain)) | |
99 | return false; | |
100 | ||
101 | ret = false; | |
102 | ||
103 | tmp = I915_READ(lvds_encoder->reg); | |
104 | ||
105 | if (!(tmp & LVDS_PORT_EN)) | |
106 | goto out; | |
107 | ||
108 | if (HAS_PCH_CPT(dev_priv)) | |
109 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
110 | else | |
111 | *pipe = PORT_TO_PIPE(tmp); | |
112 | ||
113 | ret = true; | |
114 | ||
115 | out: | |
116 | intel_display_power_put(dev_priv, encoder->power_domain); | |
117 | ||
118 | return ret; | |
119 | } | |
120 | ||
121 | static void intel_lvds_get_config(struct intel_encoder *encoder, | |
122 | struct intel_crtc_state *pipe_config) | |
123 | { | |
124 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
125 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
126 | u32 tmp, flags = 0; | |
127 | ||
128 | tmp = I915_READ(lvds_encoder->reg); | |
129 | if (tmp & LVDS_HSYNC_POLARITY) | |
130 | flags |= DRM_MODE_FLAG_NHSYNC; | |
131 | else | |
132 | flags |= DRM_MODE_FLAG_PHSYNC; | |
133 | if (tmp & LVDS_VSYNC_POLARITY) | |
134 | flags |= DRM_MODE_FLAG_NVSYNC; | |
135 | else | |
136 | flags |= DRM_MODE_FLAG_PVSYNC; | |
137 | ||
138 | pipe_config->base.adjusted_mode.flags |= flags; | |
139 | ||
140 | if (INTEL_GEN(dev_priv) < 5) | |
141 | pipe_config->gmch_pfit.lvds_border_bits = | |
142 | tmp & LVDS_BORDER_ENABLE; | |
143 | ||
144 | /* gen2/3 store dither state in pfit control, needs to match */ | |
145 | if (INTEL_GEN(dev_priv) < 4) { | |
146 | tmp = I915_READ(PFIT_CONTROL); | |
147 | ||
148 | pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; | |
149 | } | |
150 | ||
151 | pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; | |
152 | } | |
153 | ||
154 | static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, | |
155 | struct intel_lvds_pps *pps) | |
156 | { | |
157 | u32 val; | |
158 | ||
159 | pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET; | |
160 | ||
161 | val = I915_READ(PP_ON_DELAYS(0)); | |
162 | pps->port = (val & PANEL_PORT_SELECT_MASK) >> | |
163 | PANEL_PORT_SELECT_SHIFT; | |
164 | pps->t1_t2 = (val & PANEL_POWER_UP_DELAY_MASK) >> | |
165 | PANEL_POWER_UP_DELAY_SHIFT; | |
166 | pps->t5 = (val & PANEL_LIGHT_ON_DELAY_MASK) >> | |
167 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
168 | ||
169 | val = I915_READ(PP_OFF_DELAYS(0)); | |
170 | pps->t3 = (val & PANEL_POWER_DOWN_DELAY_MASK) >> | |
171 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
172 | pps->tx = (val & PANEL_LIGHT_OFF_DELAY_MASK) >> | |
173 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
174 | ||
175 | val = I915_READ(PP_DIVISOR(0)); | |
176 | pps->divider = (val & PP_REFERENCE_DIVIDER_MASK) >> | |
177 | PP_REFERENCE_DIVIDER_SHIFT; | |
178 | val = (val & PANEL_POWER_CYCLE_DELAY_MASK) >> | |
179 | PANEL_POWER_CYCLE_DELAY_SHIFT; | |
180 | /* | |
181 | * Remove the BSpec specified +1 (100ms) offset that accounts for a | |
182 | * too short power-cycle delay due to the asynchronous programming of | |
183 | * the register. | |
184 | */ | |
185 | if (val) | |
186 | val--; | |
187 | /* Convert from 100ms to 100us units */ | |
188 | pps->t4 = val * 1000; | |
189 | ||
190 | if (INTEL_INFO(dev_priv)->gen <= 4 && | |
191 | pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { | |
192 | DRM_DEBUG_KMS("Panel power timings uninitialized, " | |
193 | "setting defaults\n"); | |
194 | /* Set T2 to 40ms and T5 to 200ms in 100 usec units */ | |
195 | pps->t1_t2 = 40 * 10; | |
196 | pps->t5 = 200 * 10; | |
197 | /* Set T3 to 35ms and Tx to 200ms in 100 usec units */ | |
198 | pps->t3 = 35 * 10; | |
199 | pps->tx = 200 * 10; | |
200 | } | |
201 | ||
202 | DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d " | |
203 | "divider %d port %d powerdown_on_reset %d\n", | |
204 | pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx, | |
205 | pps->divider, pps->port, pps->powerdown_on_reset); | |
206 | } | |
207 | ||
208 | static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, | |
209 | struct intel_lvds_pps *pps) | |
210 | { | |
211 | u32 val; | |
212 | ||
213 | val = I915_READ(PP_CONTROL(0)); | |
214 | WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS); | |
215 | if (pps->powerdown_on_reset) | |
216 | val |= PANEL_POWER_RESET; | |
217 | I915_WRITE(PP_CONTROL(0), val); | |
218 | ||
219 | I915_WRITE(PP_ON_DELAYS(0), (pps->port << PANEL_PORT_SELECT_SHIFT) | | |
220 | (pps->t1_t2 << PANEL_POWER_UP_DELAY_SHIFT) | | |
221 | (pps->t5 << PANEL_LIGHT_ON_DELAY_SHIFT)); | |
222 | I915_WRITE(PP_OFF_DELAYS(0), (pps->t3 << PANEL_POWER_DOWN_DELAY_SHIFT) | | |
223 | (pps->tx << PANEL_LIGHT_OFF_DELAY_SHIFT)); | |
224 | ||
225 | val = pps->divider << PP_REFERENCE_DIVIDER_SHIFT; | |
226 | val |= (DIV_ROUND_UP(pps->t4, 1000) + 1) << | |
227 | PANEL_POWER_CYCLE_DELAY_SHIFT; | |
228 | I915_WRITE(PP_DIVISOR(0), val); | |
229 | } | |
230 | ||
231 | static void intel_pre_enable_lvds(struct intel_encoder *encoder, | |
232 | struct intel_crtc_state *pipe_config, | |
233 | struct drm_connector_state *conn_state) | |
234 | { | |
235 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
236 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
237 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); | |
238 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; | |
239 | int pipe = crtc->pipe; | |
240 | u32 temp; | |
241 | ||
242 | if (HAS_PCH_SPLIT(dev_priv)) { | |
243 | assert_fdi_rx_pll_disabled(dev_priv, pipe); | |
244 | assert_shared_dpll_disabled(dev_priv, | |
245 | pipe_config->shared_dpll); | |
246 | } else { | |
247 | assert_pll_disabled(dev_priv, pipe); | |
248 | } | |
249 | ||
250 | intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps); | |
251 | ||
252 | temp = lvds_encoder->init_lvds_val; | |
253 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; | |
254 | ||
255 | if (HAS_PCH_CPT(dev_priv)) { | |
256 | temp &= ~PORT_TRANS_SEL_MASK; | |
257 | temp |= PORT_TRANS_SEL_CPT(pipe); | |
258 | } else { | |
259 | if (pipe == 1) { | |
260 | temp |= LVDS_PIPEB_SELECT; | |
261 | } else { | |
262 | temp &= ~LVDS_PIPEB_SELECT; | |
263 | } | |
264 | } | |
265 | ||
266 | /* set the corresponsding LVDS_BORDER bit */ | |
267 | temp &= ~LVDS_BORDER_ENABLE; | |
268 | temp |= pipe_config->gmch_pfit.lvds_border_bits; | |
269 | /* Set the B0-B3 data pairs corresponding to whether we're going to | |
270 | * set the DPLLs for dual-channel mode or not. | |
271 | */ | |
272 | if (lvds_encoder->is_dual_link) | |
273 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
274 | else | |
275 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
276 | ||
277 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
278 | * appropriately here, but we need to look more thoroughly into how | |
279 | * panels behave in the two modes. For now, let's just maintain the | |
280 | * value we got from the BIOS. | |
281 | */ | |
282 | temp &= ~LVDS_A3_POWER_MASK; | |
283 | temp |= lvds_encoder->a3_power; | |
284 | ||
285 | /* Set the dithering flag on LVDS as needed, note that there is no | |
286 | * special lvds dither control bit on pch-split platforms, dithering is | |
287 | * only controlled through the PIPECONF reg. */ | |
288 | if (IS_GEN4(dev_priv)) { | |
289 | /* Bspec wording suggests that LVDS port dithering only exists | |
290 | * for 18bpp panels. */ | |
291 | if (pipe_config->dither && pipe_config->pipe_bpp == 18) | |
292 | temp |= LVDS_ENABLE_DITHER; | |
293 | else | |
294 | temp &= ~LVDS_ENABLE_DITHER; | |
295 | } | |
296 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
297 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) | |
298 | temp |= LVDS_HSYNC_POLARITY; | |
299 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) | |
300 | temp |= LVDS_VSYNC_POLARITY; | |
301 | ||
302 | I915_WRITE(lvds_encoder->reg, temp); | |
303 | } | |
304 | ||
305 | /** | |
306 | * Sets the power state for the panel. | |
307 | */ | |
308 | static void intel_enable_lvds(struct intel_encoder *encoder, | |
309 | struct intel_crtc_state *pipe_config, | |
310 | struct drm_connector_state *conn_state) | |
311 | { | |
312 | struct drm_device *dev = encoder->base.dev; | |
313 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
314 | struct drm_i915_private *dev_priv = to_i915(dev); | |
315 | ||
316 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); | |
317 | ||
318 | I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON); | |
319 | POSTING_READ(lvds_encoder->reg); | |
320 | if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 1000)) | |
321 | DRM_ERROR("timed out waiting for panel to power on\n"); | |
322 | ||
323 | intel_panel_enable_backlight(pipe_config, conn_state); | |
324 | } | |
325 | ||
326 | static void intel_disable_lvds(struct intel_encoder *encoder, | |
327 | struct intel_crtc_state *old_crtc_state, | |
328 | struct drm_connector_state *old_conn_state) | |
329 | { | |
330 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
331 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
332 | ||
333 | I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON); | |
334 | if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, 0, 1000)) | |
335 | DRM_ERROR("timed out waiting for panel to power off\n"); | |
336 | ||
337 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); | |
338 | POSTING_READ(lvds_encoder->reg); | |
339 | } | |
340 | ||
341 | static void gmch_disable_lvds(struct intel_encoder *encoder, | |
342 | struct intel_crtc_state *old_crtc_state, | |
343 | struct drm_connector_state *old_conn_state) | |
344 | ||
345 | { | |
346 | intel_panel_disable_backlight(old_conn_state); | |
347 | ||
348 | intel_disable_lvds(encoder, old_crtc_state, old_conn_state); | |
349 | } | |
350 | ||
351 | static void pch_disable_lvds(struct intel_encoder *encoder, | |
352 | struct intel_crtc_state *old_crtc_state, | |
353 | struct drm_connector_state *old_conn_state) | |
354 | { | |
355 | intel_panel_disable_backlight(old_conn_state); | |
356 | } | |
357 | ||
358 | static void pch_post_disable_lvds(struct intel_encoder *encoder, | |
359 | struct intel_crtc_state *old_crtc_state, | |
360 | struct drm_connector_state *old_conn_state) | |
361 | { | |
362 | intel_disable_lvds(encoder, old_crtc_state, old_conn_state); | |
363 | } | |
364 | ||
365 | static enum drm_mode_status | |
366 | intel_lvds_mode_valid(struct drm_connector *connector, | |
367 | struct drm_display_mode *mode) | |
368 | { | |
369 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
370 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
371 | int max_pixclk = to_i915(connector->dev)->max_dotclk_freq; | |
372 | ||
373 | if (mode->hdisplay > fixed_mode->hdisplay) | |
374 | return MODE_PANEL; | |
375 | if (mode->vdisplay > fixed_mode->vdisplay) | |
376 | return MODE_PANEL; | |
377 | if (fixed_mode->clock > max_pixclk) | |
378 | return MODE_CLOCK_HIGH; | |
379 | ||
380 | return MODE_OK; | |
381 | } | |
382 | ||
383 | static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, | |
384 | struct intel_crtc_state *pipe_config, | |
385 | struct drm_connector_state *conn_state) | |
386 | { | |
387 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); | |
388 | struct intel_lvds_encoder *lvds_encoder = | |
389 | to_lvds_encoder(&intel_encoder->base); | |
390 | struct intel_connector *intel_connector = | |
391 | &lvds_encoder->attached_connector->base; | |
392 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; | |
393 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); | |
394 | unsigned int lvds_bpp; | |
395 | ||
396 | /* Should never happen!! */ | |
397 | if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) { | |
398 | DRM_ERROR("Can't support LVDS on pipe A\n"); | |
399 | return false; | |
400 | } | |
401 | ||
402 | if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) | |
403 | lvds_bpp = 8*3; | |
404 | else | |
405 | lvds_bpp = 6*3; | |
406 | ||
407 | if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { | |
408 | DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n", | |
409 | pipe_config->pipe_bpp, lvds_bpp); | |
410 | pipe_config->pipe_bpp = lvds_bpp; | |
411 | } | |
412 | ||
413 | /* | |
414 | * We have timings from the BIOS for the panel, put them in | |
415 | * to the adjusted mode. The CRTC will be set up for this mode, | |
416 | * with the panel scaling set up to source from the H/VDisplay | |
417 | * of the original mode. | |
418 | */ | |
419 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, | |
420 | adjusted_mode); | |
421 | ||
422 | if (HAS_PCH_SPLIT(dev_priv)) { | |
423 | pipe_config->has_pch_encoder = true; | |
424 | ||
425 | intel_pch_panel_fitting(intel_crtc, pipe_config, | |
426 | conn_state->scaling_mode); | |
427 | } else { | |
428 | intel_gmch_panel_fitting(intel_crtc, pipe_config, | |
429 | conn_state->scaling_mode); | |
430 | ||
431 | } | |
432 | ||
433 | /* | |
434 | * XXX: It would be nice to support lower refresh rates on the | |
435 | * panels to reduce power consumption, and perhaps match the | |
436 | * user's requested refresh rate. | |
437 | */ | |
438 | ||
439 | return true; | |
440 | } | |
441 | ||
442 | /** | |
443 | * Detect the LVDS connection. | |
444 | * | |
445 | * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means | |
446 | * connected and closed means disconnected. We also send hotplug events as | |
447 | * needed, using lid status notification from the input layer. | |
448 | */ | |
449 | static enum drm_connector_status | |
450 | intel_lvds_detect(struct drm_connector *connector, bool force) | |
451 | { | |
452 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
453 | enum drm_connector_status status; | |
454 | ||
455 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
456 | connector->base.id, connector->name); | |
457 | ||
458 | status = intel_panel_detect(dev_priv); | |
459 | if (status != connector_status_unknown) | |
460 | return status; | |
461 | ||
462 | return connector_status_connected; | |
463 | } | |
464 | ||
465 | /** | |
466 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
467 | */ | |
468 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
469 | { | |
470 | struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector); | |
471 | struct drm_device *dev = connector->dev; | |
472 | struct drm_display_mode *mode; | |
473 | ||
474 | /* use cached edid if we have one */ | |
475 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) | |
476 | return drm_add_edid_modes(connector, lvds_connector->base.edid); | |
477 | ||
478 | mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode); | |
479 | if (mode == NULL) | |
480 | return 0; | |
481 | ||
482 | drm_mode_probed_add(connector, mode); | |
483 | return 1; | |
484 | } | |
485 | ||
486 | static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) | |
487 | { | |
488 | DRM_INFO("Skipping forced modeset for %s\n", id->ident); | |
489 | return 1; | |
490 | } | |
491 | ||
492 | /* The GPU hangs up on these systems if modeset is performed on LID open */ | |
493 | static const struct dmi_system_id intel_no_modeset_on_lid[] = { | |
494 | { | |
495 | .callback = intel_no_modeset_on_lid_dmi_callback, | |
496 | .ident = "Toshiba Tecra A11", | |
497 | .matches = { | |
498 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
499 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), | |
500 | }, | |
501 | }, | |
502 | ||
503 | { } /* terminating entry */ | |
504 | }; | |
505 | ||
506 | /* | |
507 | * Lid events. Note the use of 'modeset': | |
508 | * - we set it to MODESET_ON_LID_OPEN on lid close, | |
509 | * and set it to MODESET_DONE on open | |
510 | * - we use it as a "only once" bit (ie we ignore | |
511 | * duplicate events where it was already properly set) | |
512 | * - the suspend/resume paths will set it to | |
513 | * MODESET_SUSPENDED and ignore the lid open event, | |
514 | * because they restore the mode ("lid open"). | |
515 | */ | |
516 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, | |
517 | void *unused) | |
518 | { | |
519 | struct intel_lvds_connector *lvds_connector = | |
520 | container_of(nb, struct intel_lvds_connector, lid_notifier); | |
521 | struct drm_connector *connector = &lvds_connector->base.base; | |
522 | struct drm_device *dev = connector->dev; | |
523 | struct drm_i915_private *dev_priv = to_i915(dev); | |
524 | ||
525 | if (dev->switch_power_state != DRM_SWITCH_POWER_ON) | |
526 | return NOTIFY_OK; | |
527 | ||
528 | mutex_lock(&dev_priv->modeset_restore_lock); | |
529 | if (dev_priv->modeset_restore == MODESET_SUSPENDED) | |
530 | goto exit; | |
531 | /* | |
532 | * check and update the status of LVDS connector after receiving | |
533 | * the LID nofication event. | |
534 | */ | |
535 | connector->status = connector->funcs->detect(connector, false); | |
536 | ||
537 | /* Don't force modeset on machines where it causes a GPU lockup */ | |
538 | if (dmi_check_system(intel_no_modeset_on_lid)) | |
539 | goto exit; | |
540 | if (!acpi_lid_open()) { | |
541 | /* do modeset on next lid open event */ | |
542 | dev_priv->modeset_restore = MODESET_ON_LID_OPEN; | |
543 | goto exit; | |
544 | } | |
545 | ||
546 | if (dev_priv->modeset_restore == MODESET_DONE) | |
547 | goto exit; | |
548 | ||
549 | /* | |
550 | * Some old platform's BIOS love to wreak havoc while the lid is closed. | |
551 | * We try to detect this here and undo any damage. The split for PCH | |
552 | * platforms is rather conservative and a bit arbitrary expect that on | |
553 | * those platforms VGA disabling requires actual legacy VGA I/O access, | |
554 | * and as part of the cleanup in the hw state restore we also redisable | |
555 | * the vga plane. | |
556 | */ | |
557 | if (!HAS_PCH_SPLIT(dev_priv)) | |
558 | intel_display_resume(dev); | |
559 | ||
560 | dev_priv->modeset_restore = MODESET_DONE; | |
561 | ||
562 | exit: | |
563 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
564 | return NOTIFY_OK; | |
565 | } | |
566 | ||
567 | /** | |
568 | * intel_lvds_destroy - unregister and free LVDS structures | |
569 | * @connector: connector to free | |
570 | * | |
571 | * Unregister the DDC bus for this connector then free the driver private | |
572 | * structure. | |
573 | */ | |
574 | static void intel_lvds_destroy(struct drm_connector *connector) | |
575 | { | |
576 | struct intel_lvds_connector *lvds_connector = | |
577 | to_lvds_connector(connector); | |
578 | ||
579 | if (lvds_connector->lid_notifier.notifier_call) | |
580 | acpi_lid_notifier_unregister(&lvds_connector->lid_notifier); | |
581 | ||
582 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) | |
583 | kfree(lvds_connector->base.edid); | |
584 | ||
585 | intel_panel_fini(&lvds_connector->base.panel); | |
586 | ||
587 | drm_connector_cleanup(connector); | |
588 | kfree(connector); | |
589 | } | |
590 | ||
591 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { | |
592 | .get_modes = intel_lvds_get_modes, | |
593 | .mode_valid = intel_lvds_mode_valid, | |
594 | .atomic_check = intel_digital_connector_atomic_check, | |
595 | }; | |
596 | ||
597 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
598 | .dpms = drm_atomic_helper_connector_dpms, | |
599 | .detect = intel_lvds_detect, | |
600 | .fill_modes = drm_helper_probe_single_connector_modes, | |
601 | .set_property = drm_atomic_helper_connector_set_property, | |
602 | .atomic_get_property = intel_digital_connector_atomic_get_property, | |
603 | .atomic_set_property = intel_digital_connector_atomic_set_property, | |
604 | .late_register = intel_connector_register, | |
605 | .early_unregister = intel_connector_unregister, | |
606 | .destroy = intel_lvds_destroy, | |
607 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, | |
608 | .atomic_duplicate_state = intel_digital_connector_duplicate_state, | |
609 | }; | |
610 | ||
611 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { | |
612 | .destroy = intel_encoder_destroy, | |
613 | }; | |
614 | ||
615 | static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) | |
616 | { | |
617 | DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); | |
618 | return 1; | |
619 | } | |
620 | ||
621 | /* These systems claim to have LVDS, but really don't */ | |
622 | static const struct dmi_system_id intel_no_lvds[] = { | |
623 | { | |
624 | .callback = intel_no_lvds_dmi_callback, | |
625 | .ident = "Apple Mac Mini (Core series)", | |
626 | .matches = { | |
627 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), | |
628 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), | |
629 | }, | |
630 | }, | |
631 | { | |
632 | .callback = intel_no_lvds_dmi_callback, | |
633 | .ident = "Apple Mac Mini (Core 2 series)", | |
634 | .matches = { | |
635 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), | |
636 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), | |
637 | }, | |
638 | }, | |
639 | { | |
640 | .callback = intel_no_lvds_dmi_callback, | |
641 | .ident = "MSI IM-945GSE-A", | |
642 | .matches = { | |
643 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
644 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
645 | }, | |
646 | }, | |
647 | { | |
648 | .callback = intel_no_lvds_dmi_callback, | |
649 | .ident = "Dell Studio Hybrid", | |
650 | .matches = { | |
651 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
652 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
653 | }, | |
654 | }, | |
655 | { | |
656 | .callback = intel_no_lvds_dmi_callback, | |
657 | .ident = "Dell OptiPlex FX170", | |
658 | .matches = { | |
659 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
660 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), | |
661 | }, | |
662 | }, | |
663 | { | |
664 | .callback = intel_no_lvds_dmi_callback, | |
665 | .ident = "AOpen Mini PC", | |
666 | .matches = { | |
667 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
668 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
669 | }, | |
670 | }, | |
671 | { | |
672 | .callback = intel_no_lvds_dmi_callback, | |
673 | .ident = "AOpen Mini PC MP915", | |
674 | .matches = { | |
675 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
676 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), | |
677 | }, | |
678 | }, | |
679 | { | |
680 | .callback = intel_no_lvds_dmi_callback, | |
681 | .ident = "AOpen i915GMm-HFS", | |
682 | .matches = { | |
683 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
684 | DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), | |
685 | }, | |
686 | }, | |
687 | { | |
688 | .callback = intel_no_lvds_dmi_callback, | |
689 | .ident = "AOpen i45GMx-I", | |
690 | .matches = { | |
691 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
692 | DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), | |
693 | }, | |
694 | }, | |
695 | { | |
696 | .callback = intel_no_lvds_dmi_callback, | |
697 | .ident = "Aopen i945GTt-VFA", | |
698 | .matches = { | |
699 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), | |
700 | }, | |
701 | }, | |
702 | { | |
703 | .callback = intel_no_lvds_dmi_callback, | |
704 | .ident = "Clientron U800", | |
705 | .matches = { | |
706 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
707 | DMI_MATCH(DMI_PRODUCT_NAME, "U800"), | |
708 | }, | |
709 | }, | |
710 | { | |
711 | .callback = intel_no_lvds_dmi_callback, | |
712 | .ident = "Clientron E830", | |
713 | .matches = { | |
714 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
715 | DMI_MATCH(DMI_PRODUCT_NAME, "E830"), | |
716 | }, | |
717 | }, | |
718 | { | |
719 | .callback = intel_no_lvds_dmi_callback, | |
720 | .ident = "Asus EeeBox PC EB1007", | |
721 | .matches = { | |
722 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), | |
723 | DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), | |
724 | }, | |
725 | }, | |
726 | { | |
727 | .callback = intel_no_lvds_dmi_callback, | |
728 | .ident = "Asus AT5NM10T-I", | |
729 | .matches = { | |
730 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
731 | DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), | |
732 | }, | |
733 | }, | |
734 | { | |
735 | .callback = intel_no_lvds_dmi_callback, | |
736 | .ident = "Hewlett-Packard HP t5740", | |
737 | .matches = { | |
738 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
739 | DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), | |
740 | }, | |
741 | }, | |
742 | { | |
743 | .callback = intel_no_lvds_dmi_callback, | |
744 | .ident = "Hewlett-Packard t5745", | |
745 | .matches = { | |
746 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
747 | DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), | |
748 | }, | |
749 | }, | |
750 | { | |
751 | .callback = intel_no_lvds_dmi_callback, | |
752 | .ident = "Hewlett-Packard st5747", | |
753 | .matches = { | |
754 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
755 | DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), | |
756 | }, | |
757 | }, | |
758 | { | |
759 | .callback = intel_no_lvds_dmi_callback, | |
760 | .ident = "MSI Wind Box DC500", | |
761 | .matches = { | |
762 | DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), | |
763 | DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), | |
764 | }, | |
765 | }, | |
766 | { | |
767 | .callback = intel_no_lvds_dmi_callback, | |
768 | .ident = "Gigabyte GA-D525TUD", | |
769 | .matches = { | |
770 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), | |
771 | DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), | |
772 | }, | |
773 | }, | |
774 | { | |
775 | .callback = intel_no_lvds_dmi_callback, | |
776 | .ident = "Supermicro X7SPA-H", | |
777 | .matches = { | |
778 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
779 | DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), | |
780 | }, | |
781 | }, | |
782 | { | |
783 | .callback = intel_no_lvds_dmi_callback, | |
784 | .ident = "Fujitsu Esprimo Q900", | |
785 | .matches = { | |
786 | DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), | |
787 | DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), | |
788 | }, | |
789 | }, | |
790 | { | |
791 | .callback = intel_no_lvds_dmi_callback, | |
792 | .ident = "Intel D410PT", | |
793 | .matches = { | |
794 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
795 | DMI_MATCH(DMI_BOARD_NAME, "D410PT"), | |
796 | }, | |
797 | }, | |
798 | { | |
799 | .callback = intel_no_lvds_dmi_callback, | |
800 | .ident = "Intel D425KT", | |
801 | .matches = { | |
802 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
803 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), | |
804 | }, | |
805 | }, | |
806 | { | |
807 | .callback = intel_no_lvds_dmi_callback, | |
808 | .ident = "Intel D510MO", | |
809 | .matches = { | |
810 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
811 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), | |
812 | }, | |
813 | }, | |
814 | { | |
815 | .callback = intel_no_lvds_dmi_callback, | |
816 | .ident = "Intel D525MW", | |
817 | .matches = { | |
818 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
819 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), | |
820 | }, | |
821 | }, | |
822 | ||
823 | { } /* terminating entry */ | |
824 | }; | |
825 | ||
826 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) | |
827 | { | |
828 | DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); | |
829 | return 1; | |
830 | } | |
831 | ||
832 | static const struct dmi_system_id intel_dual_link_lvds[] = { | |
833 | { | |
834 | .callback = intel_dual_link_lvds_callback, | |
835 | .ident = "Apple MacBook Pro 15\" (2010)", | |
836 | .matches = { | |
837 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
838 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"), | |
839 | }, | |
840 | }, | |
841 | { | |
842 | .callback = intel_dual_link_lvds_callback, | |
843 | .ident = "Apple MacBook Pro 15\" (2011)", | |
844 | .matches = { | |
845 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
846 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), | |
847 | }, | |
848 | }, | |
849 | { | |
850 | .callback = intel_dual_link_lvds_callback, | |
851 | .ident = "Apple MacBook Pro 15\" (2012)", | |
852 | .matches = { | |
853 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
854 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"), | |
855 | }, | |
856 | }, | |
857 | { } /* terminating entry */ | |
858 | }; | |
859 | ||
860 | struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev) | |
861 | { | |
862 | struct intel_encoder *intel_encoder; | |
863 | ||
864 | for_each_intel_encoder(dev, intel_encoder) | |
865 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
866 | return intel_encoder; | |
867 | ||
868 | return NULL; | |
869 | } | |
870 | ||
871 | bool intel_is_dual_link_lvds(struct drm_device *dev) | |
872 | { | |
873 | struct intel_encoder *encoder = intel_get_lvds_encoder(dev); | |
874 | ||
875 | return encoder && to_lvds_encoder(&encoder->base)->is_dual_link; | |
876 | } | |
877 | ||
878 | static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) | |
879 | { | |
880 | struct drm_device *dev = lvds_encoder->base.base.dev; | |
881 | unsigned int val; | |
882 | struct drm_i915_private *dev_priv = to_i915(dev); | |
883 | ||
884 | /* use the module option value if specified */ | |
885 | if (i915.lvds_channel_mode > 0) | |
886 | return i915.lvds_channel_mode == 2; | |
887 | ||
888 | /* single channel LVDS is limited to 112 MHz */ | |
889 | if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock | |
890 | > 112999) | |
891 | return true; | |
892 | ||
893 | if (dmi_check_system(intel_dual_link_lvds)) | |
894 | return true; | |
895 | ||
896 | /* BIOS should set the proper LVDS register value at boot, but | |
897 | * in reality, it doesn't set the value when the lid is closed; | |
898 | * we need to check "the value to be set" in VBT when LVDS | |
899 | * register is uninitialized. | |
900 | */ | |
901 | val = I915_READ(lvds_encoder->reg); | |
902 | if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) | |
903 | val = dev_priv->vbt.bios_lvds_val; | |
904 | ||
905 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; | |
906 | } | |
907 | ||
908 | static bool intel_lvds_supported(struct drm_i915_private *dev_priv) | |
909 | { | |
910 | /* With the introduction of the PCH we gained a dedicated | |
911 | * LVDS presence pin, use it. */ | |
912 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) | |
913 | return true; | |
914 | ||
915 | /* Otherwise LVDS was only attached to mobile products, | |
916 | * except for the inglorious 830gm */ | |
917 | if (INTEL_GEN(dev_priv) <= 4 && | |
918 | IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) | |
919 | return true; | |
920 | ||
921 | return false; | |
922 | } | |
923 | ||
924 | /** | |
925 | * intel_lvds_init - setup LVDS connectors on this device | |
926 | * @dev: drm device | |
927 | * | |
928 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
929 | * modes we can display on the LVDS panel (if present). | |
930 | */ | |
931 | void intel_lvds_init(struct drm_i915_private *dev_priv) | |
932 | { | |
933 | struct drm_device *dev = &dev_priv->drm; | |
934 | struct intel_lvds_encoder *lvds_encoder; | |
935 | struct intel_encoder *intel_encoder; | |
936 | struct intel_lvds_connector *lvds_connector; | |
937 | struct intel_connector *intel_connector; | |
938 | struct drm_connector *connector; | |
939 | struct drm_encoder *encoder; | |
940 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
941 | struct drm_display_mode *fixed_mode = NULL; | |
942 | struct drm_display_mode *downclock_mode = NULL; | |
943 | struct edid *edid; | |
944 | struct intel_crtc *crtc; | |
945 | i915_reg_t lvds_reg; | |
946 | u32 lvds; | |
947 | int pipe; | |
948 | u8 pin; | |
949 | u32 allowed_scalers; | |
950 | ||
951 | if (!intel_lvds_supported(dev_priv)) | |
952 | return; | |
953 | ||
954 | /* Skip init on machines we know falsely report LVDS */ | |
955 | if (dmi_check_system(intel_no_lvds)) | |
956 | return; | |
957 | ||
958 | if (HAS_PCH_SPLIT(dev_priv)) | |
959 | lvds_reg = PCH_LVDS; | |
960 | else | |
961 | lvds_reg = LVDS; | |
962 | ||
963 | lvds = I915_READ(lvds_reg); | |
964 | ||
965 | if (HAS_PCH_SPLIT(dev_priv)) { | |
966 | if ((lvds & LVDS_DETECTED) == 0) | |
967 | return; | |
968 | if (dev_priv->vbt.edp.support) { | |
969 | DRM_DEBUG_KMS("disable LVDS for eDP support\n"); | |
970 | return; | |
971 | } | |
972 | } | |
973 | ||
974 | pin = GMBUS_PIN_PANEL; | |
975 | if (!intel_bios_is_lvds_present(dev_priv, &pin)) { | |
976 | if ((lvds & LVDS_PORT_EN) == 0) { | |
977 | DRM_DEBUG_KMS("LVDS is not present in VBT\n"); | |
978 | return; | |
979 | } | |
980 | DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n"); | |
981 | } | |
982 | ||
983 | lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); | |
984 | if (!lvds_encoder) | |
985 | return; | |
986 | ||
987 | lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL); | |
988 | if (!lvds_connector) { | |
989 | kfree(lvds_encoder); | |
990 | return; | |
991 | } | |
992 | ||
993 | if (intel_connector_init(&lvds_connector->base) < 0) { | |
994 | kfree(lvds_connector); | |
995 | kfree(lvds_encoder); | |
996 | return; | |
997 | } | |
998 | ||
999 | lvds_encoder->attached_connector = lvds_connector; | |
1000 | ||
1001 | intel_encoder = &lvds_encoder->base; | |
1002 | encoder = &intel_encoder->base; | |
1003 | intel_connector = &lvds_connector->base; | |
1004 | connector = &intel_connector->base; | |
1005 | drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, | |
1006 | DRM_MODE_CONNECTOR_LVDS); | |
1007 | ||
1008 | drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, | |
1009 | DRM_MODE_ENCODER_LVDS, "LVDS"); | |
1010 | ||
1011 | intel_encoder->enable = intel_enable_lvds; | |
1012 | intel_encoder->pre_enable = intel_pre_enable_lvds; | |
1013 | intel_encoder->compute_config = intel_lvds_compute_config; | |
1014 | if (HAS_PCH_SPLIT(dev_priv)) { | |
1015 | intel_encoder->disable = pch_disable_lvds; | |
1016 | intel_encoder->post_disable = pch_post_disable_lvds; | |
1017 | } else { | |
1018 | intel_encoder->disable = gmch_disable_lvds; | |
1019 | } | |
1020 | intel_encoder->get_hw_state = intel_lvds_get_hw_state; | |
1021 | intel_encoder->get_config = intel_lvds_get_config; | |
1022 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
1023 | ||
1024 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
1025 | ||
1026 | intel_encoder->type = INTEL_OUTPUT_LVDS; | |
1027 | intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; | |
1028 | intel_encoder->port = PORT_NONE; | |
1029 | intel_encoder->cloneable = 0; | |
1030 | if (HAS_PCH_SPLIT(dev_priv)) | |
1031 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
1032 | else if (IS_GEN4(dev_priv)) | |
1033 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
1034 | else | |
1035 | intel_encoder->crtc_mask = (1 << 1); | |
1036 | ||
1037 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); | |
1038 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
1039 | connector->interlace_allowed = false; | |
1040 | connector->doublescan_allowed = false; | |
1041 | ||
1042 | lvds_encoder->reg = lvds_reg; | |
1043 | ||
1044 | /* create the scaling mode property */ | |
1045 | allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT); | |
1046 | allowed_scalers |= BIT(DRM_MODE_SCALE_FULLSCREEN); | |
1047 | allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); | |
1048 | drm_connector_attach_scaling_mode_property(connector, allowed_scalers); | |
1049 | connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; | |
1050 | ||
1051 | intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps); | |
1052 | lvds_encoder->init_lvds_val = lvds; | |
1053 | ||
1054 | /* | |
1055 | * LVDS discovery: | |
1056 | * 1) check for EDID on DDC | |
1057 | * 2) check for VBT data | |
1058 | * 3) check to see if LVDS is already on | |
1059 | * if none of the above, no panel | |
1060 | * 4) make sure lid is open | |
1061 | * if closed, act like it's not there for now | |
1062 | */ | |
1063 | ||
1064 | /* | |
1065 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
1066 | * preferred mode is the right one. | |
1067 | */ | |
1068 | mutex_lock(&dev->mode_config.mutex); | |
1069 | if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) | |
1070 | edid = drm_get_edid_switcheroo(connector, | |
1071 | intel_gmbus_get_adapter(dev_priv, pin)); | |
1072 | else | |
1073 | edid = drm_get_edid(connector, | |
1074 | intel_gmbus_get_adapter(dev_priv, pin)); | |
1075 | if (edid) { | |
1076 | if (drm_add_edid_modes(connector, edid)) { | |
1077 | drm_mode_connector_update_edid_property(connector, | |
1078 | edid); | |
1079 | } else { | |
1080 | kfree(edid); | |
1081 | edid = ERR_PTR(-EINVAL); | |
1082 | } | |
1083 | } else { | |
1084 | edid = ERR_PTR(-ENOENT); | |
1085 | } | |
1086 | lvds_connector->base.edid = edid; | |
1087 | ||
1088 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
1089 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { | |
1090 | DRM_DEBUG_KMS("using preferred mode from EDID: "); | |
1091 | drm_mode_debug_printmodeline(scan); | |
1092 | ||
1093 | fixed_mode = drm_mode_duplicate(dev, scan); | |
1094 | if (fixed_mode) | |
1095 | goto out; | |
1096 | } | |
1097 | } | |
1098 | ||
1099 | /* Failed to get EDID, what about VBT? */ | |
1100 | if (dev_priv->vbt.lfp_lvds_vbt_mode) { | |
1101 | DRM_DEBUG_KMS("using mode from VBT: "); | |
1102 | drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode); | |
1103 | ||
1104 | fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode); | |
1105 | if (fixed_mode) { | |
1106 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
1107 | connector->display_info.width_mm = fixed_mode->width_mm; | |
1108 | connector->display_info.height_mm = fixed_mode->height_mm; | |
1109 | goto out; | |
1110 | } | |
1111 | } | |
1112 | ||
1113 | /* | |
1114 | * If we didn't get EDID, try checking if the panel is already turned | |
1115 | * on. If so, assume that whatever is currently programmed is the | |
1116 | * correct mode. | |
1117 | */ | |
1118 | ||
1119 | /* Ironlake: FIXME if still fail, not try pipe mode now */ | |
1120 | if (HAS_PCH_SPLIT(dev_priv)) | |
1121 | goto failed; | |
1122 | ||
1123 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; | |
1124 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); | |
1125 | ||
1126 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
1127 | fixed_mode = intel_crtc_mode_get(dev, &crtc->base); | |
1128 | if (fixed_mode) { | |
1129 | DRM_DEBUG_KMS("using current (BIOS) mode: "); | |
1130 | drm_mode_debug_printmodeline(fixed_mode); | |
1131 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
1132 | goto out; | |
1133 | } | |
1134 | } | |
1135 | ||
1136 | /* If we still don't have a mode after all that, give up. */ | |
1137 | if (!fixed_mode) | |
1138 | goto failed; | |
1139 | ||
1140 | out: | |
1141 | mutex_unlock(&dev->mode_config.mutex); | |
1142 | ||
1143 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); | |
1144 | intel_panel_setup_backlight(connector, INVALID_PIPE); | |
1145 | ||
1146 | lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); | |
1147 | DRM_DEBUG_KMS("detected %s-link lvds configuration\n", | |
1148 | lvds_encoder->is_dual_link ? "dual" : "single"); | |
1149 | ||
1150 | lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; | |
1151 | ||
1152 | lvds_connector->lid_notifier.notifier_call = intel_lid_notify; | |
1153 | if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) { | |
1154 | DRM_DEBUG_KMS("lid notifier registration failed\n"); | |
1155 | lvds_connector->lid_notifier.notifier_call = NULL; | |
1156 | } | |
1157 | ||
1158 | return; | |
1159 | ||
1160 | failed: | |
1161 | mutex_unlock(&dev->mode_config.mutex); | |
1162 | ||
1163 | DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); | |
1164 | drm_connector_cleanup(connector); | |
1165 | drm_encoder_cleanup(encoder); | |
1166 | kfree(lvds_encoder); | |
1167 | kfree(lvds_connector); | |
1168 | return; | |
1169 | } |