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1 | /* | |
2 | * Copyright © 2009 | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Daniel Vetter <daniel@ffwll.ch> | |
25 | * | |
26 | * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c | |
27 | */ | |
28 | #include <drm/drmP.h> | |
29 | #include <drm/i915_drm.h> | |
30 | #include "i915_drv.h" | |
31 | #include "i915_reg.h" | |
32 | #include "intel_drv.h" | |
33 | #include "intel_frontbuffer.h" | |
34 | ||
35 | /* Limits for overlay size. According to intel doc, the real limits are: | |
36 | * Y width: 4095, UV width (planar): 2047, Y height: 2047, | |
37 | * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use | |
38 | * the mininum of both. */ | |
39 | #define IMAGE_MAX_WIDTH 2048 | |
40 | #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */ | |
41 | /* on 830 and 845 these large limits result in the card hanging */ | |
42 | #define IMAGE_MAX_WIDTH_LEGACY 1024 | |
43 | #define IMAGE_MAX_HEIGHT_LEGACY 1088 | |
44 | ||
45 | /* overlay register definitions */ | |
46 | /* OCMD register */ | |
47 | #define OCMD_TILED_SURFACE (0x1<<19) | |
48 | #define OCMD_MIRROR_MASK (0x3<<17) | |
49 | #define OCMD_MIRROR_MODE (0x3<<17) | |
50 | #define OCMD_MIRROR_HORIZONTAL (0x1<<17) | |
51 | #define OCMD_MIRROR_VERTICAL (0x2<<17) | |
52 | #define OCMD_MIRROR_BOTH (0x3<<17) | |
53 | #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */ | |
54 | #define OCMD_UV_SWAP (0x1<<14) /* YVYU */ | |
55 | #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */ | |
56 | #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */ | |
57 | #define OCMD_SOURCE_FORMAT_MASK (0xf<<10) | |
58 | #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */ | |
59 | #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */ | |
60 | #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */ | |
61 | #define OCMD_YUV_422_PACKED (0x8<<10) | |
62 | #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */ | |
63 | #define OCMD_YUV_420_PLANAR (0xc<<10) | |
64 | #define OCMD_YUV_422_PLANAR (0xd<<10) | |
65 | #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */ | |
66 | #define OCMD_TVSYNCFLIP_PARITY (0x1<<9) | |
67 | #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7) | |
68 | #define OCMD_BUF_TYPE_MASK (0x1<<5) | |
69 | #define OCMD_BUF_TYPE_FRAME (0x0<<5) | |
70 | #define OCMD_BUF_TYPE_FIELD (0x1<<5) | |
71 | #define OCMD_TEST_MODE (0x1<<4) | |
72 | #define OCMD_BUFFER_SELECT (0x3<<2) | |
73 | #define OCMD_BUFFER0 (0x0<<2) | |
74 | #define OCMD_BUFFER1 (0x1<<2) | |
75 | #define OCMD_FIELD_SELECT (0x1<<2) | |
76 | #define OCMD_FIELD0 (0x0<<1) | |
77 | #define OCMD_FIELD1 (0x1<<1) | |
78 | #define OCMD_ENABLE (0x1<<0) | |
79 | ||
80 | /* OCONFIG register */ | |
81 | #define OCONF_PIPE_MASK (0x1<<18) | |
82 | #define OCONF_PIPE_A (0x0<<18) | |
83 | #define OCONF_PIPE_B (0x1<<18) | |
84 | #define OCONF_GAMMA2_ENABLE (0x1<<16) | |
85 | #define OCONF_CSC_MODE_BT601 (0x0<<5) | |
86 | #define OCONF_CSC_MODE_BT709 (0x1<<5) | |
87 | #define OCONF_CSC_BYPASS (0x1<<4) | |
88 | #define OCONF_CC_OUT_8BIT (0x1<<3) | |
89 | #define OCONF_TEST_MODE (0x1<<2) | |
90 | #define OCONF_THREE_LINE_BUFFER (0x1<<0) | |
91 | #define OCONF_TWO_LINE_BUFFER (0x0<<0) | |
92 | ||
93 | /* DCLRKM (dst-key) register */ | |
94 | #define DST_KEY_ENABLE (0x1<<31) | |
95 | #define CLK_RGB24_MASK 0x0 | |
96 | #define CLK_RGB16_MASK 0x070307 | |
97 | #define CLK_RGB15_MASK 0x070707 | |
98 | #define CLK_RGB8I_MASK 0xffffff | |
99 | ||
100 | #define RGB16_TO_COLORKEY(c) \ | |
101 | (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3)) | |
102 | #define RGB15_TO_COLORKEY(c) \ | |
103 | (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3)) | |
104 | ||
105 | /* overlay flip addr flag */ | |
106 | #define OFC_UPDATE 0x1 | |
107 | ||
108 | /* polyphase filter coefficients */ | |
109 | #define N_HORIZ_Y_TAPS 5 | |
110 | #define N_VERT_Y_TAPS 3 | |
111 | #define N_HORIZ_UV_TAPS 3 | |
112 | #define N_VERT_UV_TAPS 3 | |
113 | #define N_PHASES 17 | |
114 | #define MAX_TAPS 5 | |
115 | ||
116 | /* memory bufferd overlay registers */ | |
117 | struct overlay_registers { | |
118 | u32 OBUF_0Y; | |
119 | u32 OBUF_1Y; | |
120 | u32 OBUF_0U; | |
121 | u32 OBUF_0V; | |
122 | u32 OBUF_1U; | |
123 | u32 OBUF_1V; | |
124 | u32 OSTRIDE; | |
125 | u32 YRGB_VPH; | |
126 | u32 UV_VPH; | |
127 | u32 HORZ_PH; | |
128 | u32 INIT_PHS; | |
129 | u32 DWINPOS; | |
130 | u32 DWINSZ; | |
131 | u32 SWIDTH; | |
132 | u32 SWIDTHSW; | |
133 | u32 SHEIGHT; | |
134 | u32 YRGBSCALE; | |
135 | u32 UVSCALE; | |
136 | u32 OCLRC0; | |
137 | u32 OCLRC1; | |
138 | u32 DCLRKV; | |
139 | u32 DCLRKM; | |
140 | u32 SCLRKVH; | |
141 | u32 SCLRKVL; | |
142 | u32 SCLRKEN; | |
143 | u32 OCONFIG; | |
144 | u32 OCMD; | |
145 | u32 RESERVED1; /* 0x6C */ | |
146 | u32 OSTART_0Y; | |
147 | u32 OSTART_1Y; | |
148 | u32 OSTART_0U; | |
149 | u32 OSTART_0V; | |
150 | u32 OSTART_1U; | |
151 | u32 OSTART_1V; | |
152 | u32 OTILEOFF_0Y; | |
153 | u32 OTILEOFF_1Y; | |
154 | u32 OTILEOFF_0U; | |
155 | u32 OTILEOFF_0V; | |
156 | u32 OTILEOFF_1U; | |
157 | u32 OTILEOFF_1V; | |
158 | u32 FASTHSCALE; /* 0xA0 */ | |
159 | u32 UVSCALEV; /* 0xA4 */ | |
160 | u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ | |
161 | u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ | |
162 | u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; | |
163 | u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ | |
164 | u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; | |
165 | u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ | |
166 | u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; | |
167 | u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ | |
168 | u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; | |
169 | }; | |
170 | ||
171 | struct intel_overlay { | |
172 | struct drm_i915_private *i915; | |
173 | struct intel_crtc *crtc; | |
174 | struct i915_vma *vma; | |
175 | struct i915_vma *old_vma; | |
176 | bool active; | |
177 | bool pfit_active; | |
178 | u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ | |
179 | u32 color_key:24; | |
180 | u32 color_key_enabled:1; | |
181 | u32 brightness, contrast, saturation; | |
182 | u32 old_xscale, old_yscale; | |
183 | /* register access */ | |
184 | u32 flip_addr; | |
185 | struct drm_i915_gem_object *reg_bo; | |
186 | /* flip handling */ | |
187 | struct i915_gem_active last_flip; | |
188 | }; | |
189 | ||
190 | static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv, | |
191 | bool enable) | |
192 | { | |
193 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
194 | u8 val; | |
195 | ||
196 | /* WA_OVERLAY_CLKGATE:alm */ | |
197 | if (enable) | |
198 | I915_WRITE(DSPCLK_GATE_D, 0); | |
199 | else | |
200 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); | |
201 | ||
202 | /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ | |
203 | pci_bus_read_config_byte(pdev->bus, | |
204 | PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val); | |
205 | if (enable) | |
206 | val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE; | |
207 | else | |
208 | val |= I830_L2_CACHE_CLOCK_GATE_DISABLE; | |
209 | pci_bus_write_config_byte(pdev->bus, | |
210 | PCI_DEVFN(0, 0), I830_CLOCK_GATE, val); | |
211 | } | |
212 | ||
213 | static struct overlay_registers __iomem * | |
214 | intel_overlay_map_regs(struct intel_overlay *overlay) | |
215 | { | |
216 | struct drm_i915_private *dev_priv = overlay->i915; | |
217 | struct overlay_registers __iomem *regs; | |
218 | ||
219 | if (OVERLAY_NEEDS_PHYSICAL(dev_priv)) | |
220 | regs = (struct overlay_registers __iomem *)overlay->reg_bo->phys_handle->vaddr; | |
221 | else | |
222 | regs = io_mapping_map_wc(&dev_priv->ggtt.mappable, | |
223 | overlay->flip_addr, | |
224 | PAGE_SIZE); | |
225 | ||
226 | return regs; | |
227 | } | |
228 | ||
229 | static void intel_overlay_unmap_regs(struct intel_overlay *overlay, | |
230 | struct overlay_registers __iomem *regs) | |
231 | { | |
232 | if (!OVERLAY_NEEDS_PHYSICAL(overlay->i915)) | |
233 | io_mapping_unmap(regs); | |
234 | } | |
235 | ||
236 | static void intel_overlay_submit_request(struct intel_overlay *overlay, | |
237 | struct drm_i915_gem_request *req, | |
238 | i915_gem_retire_fn retire) | |
239 | { | |
240 | GEM_BUG_ON(i915_gem_active_peek(&overlay->last_flip, | |
241 | &overlay->i915->drm.struct_mutex)); | |
242 | i915_gem_active_set_retire_fn(&overlay->last_flip, retire, | |
243 | &overlay->i915->drm.struct_mutex); | |
244 | i915_gem_active_set(&overlay->last_flip, req); | |
245 | i915_add_request(req); | |
246 | } | |
247 | ||
248 | static int intel_overlay_do_wait_request(struct intel_overlay *overlay, | |
249 | struct drm_i915_gem_request *req, | |
250 | i915_gem_retire_fn retire) | |
251 | { | |
252 | intel_overlay_submit_request(overlay, req, retire); | |
253 | return i915_gem_active_retire(&overlay->last_flip, | |
254 | &overlay->i915->drm.struct_mutex); | |
255 | } | |
256 | ||
257 | static struct drm_i915_gem_request *alloc_request(struct intel_overlay *overlay) | |
258 | { | |
259 | struct drm_i915_private *dev_priv = overlay->i915; | |
260 | struct intel_engine_cs *engine = dev_priv->engine[RCS]; | |
261 | ||
262 | return i915_gem_request_alloc(engine, dev_priv->kernel_context); | |
263 | } | |
264 | ||
265 | /* overlay needs to be disable in OCMD reg */ | |
266 | static int intel_overlay_on(struct intel_overlay *overlay) | |
267 | { | |
268 | struct drm_i915_private *dev_priv = overlay->i915; | |
269 | struct drm_i915_gem_request *req; | |
270 | u32 *cs; | |
271 | ||
272 | WARN_ON(overlay->active); | |
273 | ||
274 | req = alloc_request(overlay); | |
275 | if (IS_ERR(req)) | |
276 | return PTR_ERR(req); | |
277 | ||
278 | cs = intel_ring_begin(req, 4); | |
279 | if (IS_ERR(cs)) { | |
280 | i915_add_request(req); | |
281 | return PTR_ERR(cs); | |
282 | } | |
283 | ||
284 | overlay->active = true; | |
285 | ||
286 | if (IS_I830(dev_priv)) | |
287 | i830_overlay_clock_gating(dev_priv, false); | |
288 | ||
289 | *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON; | |
290 | *cs++ = overlay->flip_addr | OFC_UPDATE; | |
291 | *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; | |
292 | *cs++ = MI_NOOP; | |
293 | intel_ring_advance(req, cs); | |
294 | ||
295 | return intel_overlay_do_wait_request(overlay, req, NULL); | |
296 | } | |
297 | ||
298 | static void intel_overlay_flip_prepare(struct intel_overlay *overlay, | |
299 | struct i915_vma *vma) | |
300 | { | |
301 | enum pipe pipe = overlay->crtc->pipe; | |
302 | ||
303 | WARN_ON(overlay->old_vma); | |
304 | ||
305 | i915_gem_track_fb(overlay->vma ? overlay->vma->obj : NULL, | |
306 | vma ? vma->obj : NULL, | |
307 | INTEL_FRONTBUFFER_OVERLAY(pipe)); | |
308 | ||
309 | intel_frontbuffer_flip_prepare(overlay->i915, | |
310 | INTEL_FRONTBUFFER_OVERLAY(pipe)); | |
311 | ||
312 | overlay->old_vma = overlay->vma; | |
313 | if (vma) | |
314 | overlay->vma = i915_vma_get(vma); | |
315 | else | |
316 | overlay->vma = NULL; | |
317 | } | |
318 | ||
319 | /* overlay needs to be enabled in OCMD reg */ | |
320 | static int intel_overlay_continue(struct intel_overlay *overlay, | |
321 | struct i915_vma *vma, | |
322 | bool load_polyphase_filter) | |
323 | { | |
324 | struct drm_i915_private *dev_priv = overlay->i915; | |
325 | struct drm_i915_gem_request *req; | |
326 | u32 flip_addr = overlay->flip_addr; | |
327 | u32 tmp, *cs; | |
328 | ||
329 | WARN_ON(!overlay->active); | |
330 | ||
331 | if (load_polyphase_filter) | |
332 | flip_addr |= OFC_UPDATE; | |
333 | ||
334 | /* check for underruns */ | |
335 | tmp = I915_READ(DOVSTA); | |
336 | if (tmp & (1 << 17)) | |
337 | DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp); | |
338 | ||
339 | req = alloc_request(overlay); | |
340 | if (IS_ERR(req)) | |
341 | return PTR_ERR(req); | |
342 | ||
343 | cs = intel_ring_begin(req, 2); | |
344 | if (IS_ERR(cs)) { | |
345 | i915_add_request(req); | |
346 | return PTR_ERR(cs); | |
347 | } | |
348 | ||
349 | *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; | |
350 | *cs++ = flip_addr; | |
351 | intel_ring_advance(req, cs); | |
352 | ||
353 | intel_overlay_flip_prepare(overlay, vma); | |
354 | ||
355 | intel_overlay_submit_request(overlay, req, NULL); | |
356 | ||
357 | return 0; | |
358 | } | |
359 | ||
360 | static void intel_overlay_release_old_vma(struct intel_overlay *overlay) | |
361 | { | |
362 | struct i915_vma *vma; | |
363 | ||
364 | vma = fetch_and_zero(&overlay->old_vma); | |
365 | if (WARN_ON(!vma)) | |
366 | return; | |
367 | ||
368 | intel_frontbuffer_flip_complete(overlay->i915, | |
369 | INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); | |
370 | ||
371 | i915_gem_object_unpin_from_display_plane(vma); | |
372 | i915_vma_put(vma); | |
373 | } | |
374 | ||
375 | static void intel_overlay_release_old_vid_tail(struct i915_gem_active *active, | |
376 | struct drm_i915_gem_request *req) | |
377 | { | |
378 | struct intel_overlay *overlay = | |
379 | container_of(active, typeof(*overlay), last_flip); | |
380 | ||
381 | intel_overlay_release_old_vma(overlay); | |
382 | } | |
383 | ||
384 | static void intel_overlay_off_tail(struct i915_gem_active *active, | |
385 | struct drm_i915_gem_request *req) | |
386 | { | |
387 | struct intel_overlay *overlay = | |
388 | container_of(active, typeof(*overlay), last_flip); | |
389 | struct drm_i915_private *dev_priv = overlay->i915; | |
390 | ||
391 | intel_overlay_release_old_vma(overlay); | |
392 | ||
393 | overlay->crtc->overlay = NULL; | |
394 | overlay->crtc = NULL; | |
395 | overlay->active = false; | |
396 | ||
397 | if (IS_I830(dev_priv)) | |
398 | i830_overlay_clock_gating(dev_priv, true); | |
399 | } | |
400 | ||
401 | /* overlay needs to be disabled in OCMD reg */ | |
402 | static int intel_overlay_off(struct intel_overlay *overlay) | |
403 | { | |
404 | struct drm_i915_gem_request *req; | |
405 | u32 *cs, flip_addr = overlay->flip_addr; | |
406 | ||
407 | WARN_ON(!overlay->active); | |
408 | ||
409 | /* According to intel docs the overlay hw may hang (when switching | |
410 | * off) without loading the filter coeffs. It is however unclear whether | |
411 | * this applies to the disabling of the overlay or to the switching off | |
412 | * of the hw. Do it in both cases */ | |
413 | flip_addr |= OFC_UPDATE; | |
414 | ||
415 | req = alloc_request(overlay); | |
416 | if (IS_ERR(req)) | |
417 | return PTR_ERR(req); | |
418 | ||
419 | cs = intel_ring_begin(req, 6); | |
420 | if (IS_ERR(cs)) { | |
421 | i915_add_request(req); | |
422 | return PTR_ERR(cs); | |
423 | } | |
424 | ||
425 | /* wait for overlay to go idle */ | |
426 | *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; | |
427 | *cs++ = flip_addr; | |
428 | *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; | |
429 | ||
430 | /* turn overlay off */ | |
431 | *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF; | |
432 | *cs++ = flip_addr; | |
433 | *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; | |
434 | ||
435 | intel_ring_advance(req, cs); | |
436 | ||
437 | intel_overlay_flip_prepare(overlay, NULL); | |
438 | ||
439 | return intel_overlay_do_wait_request(overlay, req, | |
440 | intel_overlay_off_tail); | |
441 | } | |
442 | ||
443 | /* recover from an interruption due to a signal | |
444 | * We have to be careful not to repeat work forever an make forward progess. */ | |
445 | static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) | |
446 | { | |
447 | return i915_gem_active_retire(&overlay->last_flip, | |
448 | &overlay->i915->drm.struct_mutex); | |
449 | } | |
450 | ||
451 | /* Wait for pending overlay flip and release old frame. | |
452 | * Needs to be called before the overlay register are changed | |
453 | * via intel_overlay_(un)map_regs | |
454 | */ | |
455 | static int intel_overlay_release_old_vid(struct intel_overlay *overlay) | |
456 | { | |
457 | struct drm_i915_private *dev_priv = overlay->i915; | |
458 | u32 *cs; | |
459 | int ret; | |
460 | ||
461 | lockdep_assert_held(&dev_priv->drm.struct_mutex); | |
462 | ||
463 | /* Only wait if there is actually an old frame to release to | |
464 | * guarantee forward progress. | |
465 | */ | |
466 | if (!overlay->old_vma) | |
467 | return 0; | |
468 | ||
469 | if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) { | |
470 | /* synchronous slowpath */ | |
471 | struct drm_i915_gem_request *req; | |
472 | ||
473 | req = alloc_request(overlay); | |
474 | if (IS_ERR(req)) | |
475 | return PTR_ERR(req); | |
476 | ||
477 | cs = intel_ring_begin(req, 2); | |
478 | if (IS_ERR(cs)) { | |
479 | i915_add_request(req); | |
480 | return PTR_ERR(cs); | |
481 | } | |
482 | ||
483 | *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; | |
484 | *cs++ = MI_NOOP; | |
485 | intel_ring_advance(req, cs); | |
486 | ||
487 | ret = intel_overlay_do_wait_request(overlay, req, | |
488 | intel_overlay_release_old_vid_tail); | |
489 | if (ret) | |
490 | return ret; | |
491 | } else | |
492 | intel_overlay_release_old_vid_tail(&overlay->last_flip, NULL); | |
493 | ||
494 | return 0; | |
495 | } | |
496 | ||
497 | void intel_overlay_reset(struct drm_i915_private *dev_priv) | |
498 | { | |
499 | struct intel_overlay *overlay = dev_priv->overlay; | |
500 | ||
501 | if (!overlay) | |
502 | return; | |
503 | ||
504 | intel_overlay_release_old_vid(overlay); | |
505 | ||
506 | overlay->old_xscale = 0; | |
507 | overlay->old_yscale = 0; | |
508 | overlay->crtc = NULL; | |
509 | overlay->active = false; | |
510 | } | |
511 | ||
512 | struct put_image_params { | |
513 | int format; | |
514 | short dst_x; | |
515 | short dst_y; | |
516 | short dst_w; | |
517 | short dst_h; | |
518 | short src_w; | |
519 | short src_scan_h; | |
520 | short src_scan_w; | |
521 | short src_h; | |
522 | short stride_Y; | |
523 | short stride_UV; | |
524 | int offset_Y; | |
525 | int offset_U; | |
526 | int offset_V; | |
527 | }; | |
528 | ||
529 | static int packed_depth_bytes(u32 format) | |
530 | { | |
531 | switch (format & I915_OVERLAY_DEPTH_MASK) { | |
532 | case I915_OVERLAY_YUV422: | |
533 | return 4; | |
534 | case I915_OVERLAY_YUV411: | |
535 | /* return 6; not implemented */ | |
536 | default: | |
537 | return -EINVAL; | |
538 | } | |
539 | } | |
540 | ||
541 | static int packed_width_bytes(u32 format, short width) | |
542 | { | |
543 | switch (format & I915_OVERLAY_DEPTH_MASK) { | |
544 | case I915_OVERLAY_YUV422: | |
545 | return width << 1; | |
546 | default: | |
547 | return -EINVAL; | |
548 | } | |
549 | } | |
550 | ||
551 | static int uv_hsubsampling(u32 format) | |
552 | { | |
553 | switch (format & I915_OVERLAY_DEPTH_MASK) { | |
554 | case I915_OVERLAY_YUV422: | |
555 | case I915_OVERLAY_YUV420: | |
556 | return 2; | |
557 | case I915_OVERLAY_YUV411: | |
558 | case I915_OVERLAY_YUV410: | |
559 | return 4; | |
560 | default: | |
561 | return -EINVAL; | |
562 | } | |
563 | } | |
564 | ||
565 | static int uv_vsubsampling(u32 format) | |
566 | { | |
567 | switch (format & I915_OVERLAY_DEPTH_MASK) { | |
568 | case I915_OVERLAY_YUV420: | |
569 | case I915_OVERLAY_YUV410: | |
570 | return 2; | |
571 | case I915_OVERLAY_YUV422: | |
572 | case I915_OVERLAY_YUV411: | |
573 | return 1; | |
574 | default: | |
575 | return -EINVAL; | |
576 | } | |
577 | } | |
578 | ||
579 | static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width) | |
580 | { | |
581 | u32 sw; | |
582 | ||
583 | if (IS_GEN2(dev_priv)) | |
584 | sw = ALIGN((offset & 31) + width, 32); | |
585 | else | |
586 | sw = ALIGN((offset & 63) + width, 64); | |
587 | ||
588 | if (sw == 0) | |
589 | return 0; | |
590 | ||
591 | return (sw - 32) >> 3; | |
592 | } | |
593 | ||
594 | static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = { | |
595 | [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, }, | |
596 | [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, }, | |
597 | [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, }, | |
598 | [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, }, | |
599 | [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, }, | |
600 | [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, }, | |
601 | [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, }, | |
602 | [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, }, | |
603 | [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, }, | |
604 | [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, }, | |
605 | [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, }, | |
606 | [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, }, | |
607 | [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, }, | |
608 | [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, }, | |
609 | [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, }, | |
610 | [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, }, | |
611 | [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, }, | |
612 | }; | |
613 | ||
614 | static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = { | |
615 | [ 0] = { 0x3000, 0x1800, 0x1800, }, | |
616 | [ 1] = { 0xb000, 0x18d0, 0x2e60, }, | |
617 | [ 2] = { 0xb000, 0x1990, 0x2ce0, }, | |
618 | [ 3] = { 0xb020, 0x1a68, 0x2b40, }, | |
619 | [ 4] = { 0xb040, 0x1b20, 0x29e0, }, | |
620 | [ 5] = { 0xb060, 0x1bd8, 0x2880, }, | |
621 | [ 6] = { 0xb080, 0x1c88, 0x3e60, }, | |
622 | [ 7] = { 0xb0a0, 0x1d28, 0x3c00, }, | |
623 | [ 8] = { 0xb0c0, 0x1db8, 0x39e0, }, | |
624 | [ 9] = { 0xb0e0, 0x1e40, 0x37e0, }, | |
625 | [10] = { 0xb100, 0x1eb8, 0x3620, }, | |
626 | [11] = { 0xb100, 0x1f18, 0x34a0, }, | |
627 | [12] = { 0xb100, 0x1f68, 0x3360, }, | |
628 | [13] = { 0xb0e0, 0x1fa8, 0x3240, }, | |
629 | [14] = { 0xb0c0, 0x1fe0, 0x3140, }, | |
630 | [15] = { 0xb060, 0x1ff0, 0x30a0, }, | |
631 | [16] = { 0x3000, 0x0800, 0x3000, }, | |
632 | }; | |
633 | ||
634 | static void update_polyphase_filter(struct overlay_registers __iomem *regs) | |
635 | { | |
636 | memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs)); | |
637 | memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs, | |
638 | sizeof(uv_static_hcoeffs)); | |
639 | } | |
640 | ||
641 | static bool update_scaling_factors(struct intel_overlay *overlay, | |
642 | struct overlay_registers __iomem *regs, | |
643 | struct put_image_params *params) | |
644 | { | |
645 | /* fixed point with a 12 bit shift */ | |
646 | u32 xscale, yscale, xscale_UV, yscale_UV; | |
647 | #define FP_SHIFT 12 | |
648 | #define FRACT_MASK 0xfff | |
649 | bool scale_changed = false; | |
650 | int uv_hscale = uv_hsubsampling(params->format); | |
651 | int uv_vscale = uv_vsubsampling(params->format); | |
652 | ||
653 | if (params->dst_w > 1) | |
654 | xscale = ((params->src_scan_w - 1) << FP_SHIFT) | |
655 | /(params->dst_w); | |
656 | else | |
657 | xscale = 1 << FP_SHIFT; | |
658 | ||
659 | if (params->dst_h > 1) | |
660 | yscale = ((params->src_scan_h - 1) << FP_SHIFT) | |
661 | /(params->dst_h); | |
662 | else | |
663 | yscale = 1 << FP_SHIFT; | |
664 | ||
665 | /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/ | |
666 | xscale_UV = xscale/uv_hscale; | |
667 | yscale_UV = yscale/uv_vscale; | |
668 | /* make the Y scale to UV scale ratio an exact multiply */ | |
669 | xscale = xscale_UV * uv_hscale; | |
670 | yscale = yscale_UV * uv_vscale; | |
671 | /*} else { | |
672 | xscale_UV = 0; | |
673 | yscale_UV = 0; | |
674 | }*/ | |
675 | ||
676 | if (xscale != overlay->old_xscale || yscale != overlay->old_yscale) | |
677 | scale_changed = true; | |
678 | overlay->old_xscale = xscale; | |
679 | overlay->old_yscale = yscale; | |
680 | ||
681 | iowrite32(((yscale & FRACT_MASK) << 20) | | |
682 | ((xscale >> FP_SHIFT) << 16) | | |
683 | ((xscale & FRACT_MASK) << 3), | |
684 | ®s->YRGBSCALE); | |
685 | ||
686 | iowrite32(((yscale_UV & FRACT_MASK) << 20) | | |
687 | ((xscale_UV >> FP_SHIFT) << 16) | | |
688 | ((xscale_UV & FRACT_MASK) << 3), | |
689 | ®s->UVSCALE); | |
690 | ||
691 | iowrite32((((yscale >> FP_SHIFT) << 16) | | |
692 | ((yscale_UV >> FP_SHIFT) << 0)), | |
693 | ®s->UVSCALEV); | |
694 | ||
695 | if (scale_changed) | |
696 | update_polyphase_filter(regs); | |
697 | ||
698 | return scale_changed; | |
699 | } | |
700 | ||
701 | static void update_colorkey(struct intel_overlay *overlay, | |
702 | struct overlay_registers __iomem *regs) | |
703 | { | |
704 | const struct intel_plane_state *state = | |
705 | to_intel_plane_state(overlay->crtc->base.primary->state); | |
706 | u32 key = overlay->color_key; | |
707 | u32 format = 0; | |
708 | u32 flags = 0; | |
709 | ||
710 | if (overlay->color_key_enabled) | |
711 | flags |= DST_KEY_ENABLE; | |
712 | ||
713 | if (state->base.visible) | |
714 | format = state->base.fb->format->format; | |
715 | ||
716 | switch (format) { | |
717 | case DRM_FORMAT_C8: | |
718 | key = 0; | |
719 | flags |= CLK_RGB8I_MASK; | |
720 | break; | |
721 | case DRM_FORMAT_XRGB1555: | |
722 | key = RGB15_TO_COLORKEY(key); | |
723 | flags |= CLK_RGB15_MASK; | |
724 | break; | |
725 | case DRM_FORMAT_RGB565: | |
726 | key = RGB16_TO_COLORKEY(key); | |
727 | flags |= CLK_RGB16_MASK; | |
728 | break; | |
729 | default: | |
730 | flags |= CLK_RGB24_MASK; | |
731 | break; | |
732 | } | |
733 | ||
734 | iowrite32(key, ®s->DCLRKV); | |
735 | iowrite32(flags, ®s->DCLRKM); | |
736 | } | |
737 | ||
738 | static u32 overlay_cmd_reg(struct put_image_params *params) | |
739 | { | |
740 | u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0; | |
741 | ||
742 | if (params->format & I915_OVERLAY_YUV_PLANAR) { | |
743 | switch (params->format & I915_OVERLAY_DEPTH_MASK) { | |
744 | case I915_OVERLAY_YUV422: | |
745 | cmd |= OCMD_YUV_422_PLANAR; | |
746 | break; | |
747 | case I915_OVERLAY_YUV420: | |
748 | cmd |= OCMD_YUV_420_PLANAR; | |
749 | break; | |
750 | case I915_OVERLAY_YUV411: | |
751 | case I915_OVERLAY_YUV410: | |
752 | cmd |= OCMD_YUV_410_PLANAR; | |
753 | break; | |
754 | } | |
755 | } else { /* YUV packed */ | |
756 | switch (params->format & I915_OVERLAY_DEPTH_MASK) { | |
757 | case I915_OVERLAY_YUV422: | |
758 | cmd |= OCMD_YUV_422_PACKED; | |
759 | break; | |
760 | case I915_OVERLAY_YUV411: | |
761 | cmd |= OCMD_YUV_411_PACKED; | |
762 | break; | |
763 | } | |
764 | ||
765 | switch (params->format & I915_OVERLAY_SWAP_MASK) { | |
766 | case I915_OVERLAY_NO_SWAP: | |
767 | break; | |
768 | case I915_OVERLAY_UV_SWAP: | |
769 | cmd |= OCMD_UV_SWAP; | |
770 | break; | |
771 | case I915_OVERLAY_Y_SWAP: | |
772 | cmd |= OCMD_Y_SWAP; | |
773 | break; | |
774 | case I915_OVERLAY_Y_AND_UV_SWAP: | |
775 | cmd |= OCMD_Y_AND_UV_SWAP; | |
776 | break; | |
777 | } | |
778 | } | |
779 | ||
780 | return cmd; | |
781 | } | |
782 | ||
783 | static int intel_overlay_do_put_image(struct intel_overlay *overlay, | |
784 | struct drm_i915_gem_object *new_bo, | |
785 | struct put_image_params *params) | |
786 | { | |
787 | int ret, tmp_width; | |
788 | struct overlay_registers __iomem *regs; | |
789 | bool scale_changed = false; | |
790 | struct drm_i915_private *dev_priv = overlay->i915; | |
791 | u32 swidth, swidthsw, sheight, ostride; | |
792 | enum pipe pipe = overlay->crtc->pipe; | |
793 | struct i915_vma *vma; | |
794 | ||
795 | lockdep_assert_held(&dev_priv->drm.struct_mutex); | |
796 | WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); | |
797 | ||
798 | ret = intel_overlay_release_old_vid(overlay); | |
799 | if (ret != 0) | |
800 | return ret; | |
801 | ||
802 | vma = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL); | |
803 | if (IS_ERR(vma)) | |
804 | return PTR_ERR(vma); | |
805 | ||
806 | ret = i915_vma_put_fence(vma); | |
807 | if (ret) | |
808 | goto out_unpin; | |
809 | ||
810 | if (!overlay->active) { | |
811 | u32 oconfig; | |
812 | regs = intel_overlay_map_regs(overlay); | |
813 | if (!regs) { | |
814 | ret = -ENOMEM; | |
815 | goto out_unpin; | |
816 | } | |
817 | oconfig = OCONF_CC_OUT_8BIT; | |
818 | if (IS_GEN4(dev_priv)) | |
819 | oconfig |= OCONF_CSC_MODE_BT709; | |
820 | oconfig |= pipe == 0 ? | |
821 | OCONF_PIPE_A : OCONF_PIPE_B; | |
822 | iowrite32(oconfig, ®s->OCONFIG); | |
823 | intel_overlay_unmap_regs(overlay, regs); | |
824 | ||
825 | ret = intel_overlay_on(overlay); | |
826 | if (ret != 0) | |
827 | goto out_unpin; | |
828 | } | |
829 | ||
830 | regs = intel_overlay_map_regs(overlay); | |
831 | if (!regs) { | |
832 | ret = -ENOMEM; | |
833 | goto out_unpin; | |
834 | } | |
835 | ||
836 | iowrite32((params->dst_y << 16) | params->dst_x, ®s->DWINPOS); | |
837 | iowrite32((params->dst_h << 16) | params->dst_w, ®s->DWINSZ); | |
838 | ||
839 | if (params->format & I915_OVERLAY_YUV_PACKED) | |
840 | tmp_width = packed_width_bytes(params->format, params->src_w); | |
841 | else | |
842 | tmp_width = params->src_w; | |
843 | ||
844 | swidth = params->src_w; | |
845 | swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width); | |
846 | sheight = params->src_h; | |
847 | iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y); | |
848 | ostride = params->stride_Y; | |
849 | ||
850 | if (params->format & I915_OVERLAY_YUV_PLANAR) { | |
851 | int uv_hscale = uv_hsubsampling(params->format); | |
852 | int uv_vscale = uv_vsubsampling(params->format); | |
853 | u32 tmp_U, tmp_V; | |
854 | swidth |= (params->src_w/uv_hscale) << 16; | |
855 | tmp_U = calc_swidthsw(dev_priv, params->offset_U, | |
856 | params->src_w/uv_hscale); | |
857 | tmp_V = calc_swidthsw(dev_priv, params->offset_V, | |
858 | params->src_w/uv_hscale); | |
859 | swidthsw |= max_t(u32, tmp_U, tmp_V) << 16; | |
860 | sheight |= (params->src_h/uv_vscale) << 16; | |
861 | iowrite32(i915_ggtt_offset(vma) + params->offset_U, | |
862 | ®s->OBUF_0U); | |
863 | iowrite32(i915_ggtt_offset(vma) + params->offset_V, | |
864 | ®s->OBUF_0V); | |
865 | ostride |= params->stride_UV << 16; | |
866 | } | |
867 | ||
868 | iowrite32(swidth, ®s->SWIDTH); | |
869 | iowrite32(swidthsw, ®s->SWIDTHSW); | |
870 | iowrite32(sheight, ®s->SHEIGHT); | |
871 | iowrite32(ostride, ®s->OSTRIDE); | |
872 | ||
873 | scale_changed = update_scaling_factors(overlay, regs, params); | |
874 | ||
875 | update_colorkey(overlay, regs); | |
876 | ||
877 | iowrite32(overlay_cmd_reg(params), ®s->OCMD); | |
878 | ||
879 | intel_overlay_unmap_regs(overlay, regs); | |
880 | ||
881 | ret = intel_overlay_continue(overlay, vma, scale_changed); | |
882 | if (ret) | |
883 | goto out_unpin; | |
884 | ||
885 | return 0; | |
886 | ||
887 | out_unpin: | |
888 | i915_gem_object_unpin_from_display_plane(vma); | |
889 | return ret; | |
890 | } | |
891 | ||
892 | int intel_overlay_switch_off(struct intel_overlay *overlay) | |
893 | { | |
894 | struct drm_i915_private *dev_priv = overlay->i915; | |
895 | struct overlay_registers __iomem *regs; | |
896 | int ret; | |
897 | ||
898 | lockdep_assert_held(&dev_priv->drm.struct_mutex); | |
899 | WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); | |
900 | ||
901 | ret = intel_overlay_recover_from_interrupt(overlay); | |
902 | if (ret != 0) | |
903 | return ret; | |
904 | ||
905 | if (!overlay->active) | |
906 | return 0; | |
907 | ||
908 | ret = intel_overlay_release_old_vid(overlay); | |
909 | if (ret != 0) | |
910 | return ret; | |
911 | ||
912 | regs = intel_overlay_map_regs(overlay); | |
913 | iowrite32(0, ®s->OCMD); | |
914 | intel_overlay_unmap_regs(overlay, regs); | |
915 | ||
916 | return intel_overlay_off(overlay); | |
917 | } | |
918 | ||
919 | static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, | |
920 | struct intel_crtc *crtc) | |
921 | { | |
922 | if (!crtc->active) | |
923 | return -EINVAL; | |
924 | ||
925 | /* can't use the overlay with double wide pipe */ | |
926 | if (crtc->config->double_wide) | |
927 | return -EINVAL; | |
928 | ||
929 | return 0; | |
930 | } | |
931 | ||
932 | static void update_pfit_vscale_ratio(struct intel_overlay *overlay) | |
933 | { | |
934 | struct drm_i915_private *dev_priv = overlay->i915; | |
935 | u32 pfit_control = I915_READ(PFIT_CONTROL); | |
936 | u32 ratio; | |
937 | ||
938 | /* XXX: This is not the same logic as in the xorg driver, but more in | |
939 | * line with the intel documentation for the i965 | |
940 | */ | |
941 | if (INTEL_GEN(dev_priv) >= 4) { | |
942 | /* on i965 use the PGM reg to read out the autoscaler values */ | |
943 | ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; | |
944 | } else { | |
945 | if (pfit_control & VERT_AUTO_SCALE) | |
946 | ratio = I915_READ(PFIT_AUTO_RATIOS); | |
947 | else | |
948 | ratio = I915_READ(PFIT_PGM_RATIOS); | |
949 | ratio >>= PFIT_VERT_SCALE_SHIFT; | |
950 | } | |
951 | ||
952 | overlay->pfit_vscale_ratio = ratio; | |
953 | } | |
954 | ||
955 | static int check_overlay_dst(struct intel_overlay *overlay, | |
956 | struct drm_intel_overlay_put_image *rec) | |
957 | { | |
958 | const struct intel_crtc_state *pipe_config = | |
959 | overlay->crtc->config; | |
960 | ||
961 | if (rec->dst_x < pipe_config->pipe_src_w && | |
962 | rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w && | |
963 | rec->dst_y < pipe_config->pipe_src_h && | |
964 | rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h) | |
965 | return 0; | |
966 | else | |
967 | return -EINVAL; | |
968 | } | |
969 | ||
970 | static int check_overlay_scaling(struct put_image_params *rec) | |
971 | { | |
972 | u32 tmp; | |
973 | ||
974 | /* downscaling limit is 8.0 */ | |
975 | tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16; | |
976 | if (tmp > 7) | |
977 | return -EINVAL; | |
978 | tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16; | |
979 | if (tmp > 7) | |
980 | return -EINVAL; | |
981 | ||
982 | return 0; | |
983 | } | |
984 | ||
985 | static int check_overlay_src(struct drm_i915_private *dev_priv, | |
986 | struct drm_intel_overlay_put_image *rec, | |
987 | struct drm_i915_gem_object *new_bo) | |
988 | { | |
989 | int uv_hscale = uv_hsubsampling(rec->flags); | |
990 | int uv_vscale = uv_vsubsampling(rec->flags); | |
991 | u32 stride_mask; | |
992 | int depth; | |
993 | u32 tmp; | |
994 | ||
995 | /* check src dimensions */ | |
996 | if (IS_I845G(dev_priv) || IS_I830(dev_priv)) { | |
997 | if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY || | |
998 | rec->src_width > IMAGE_MAX_WIDTH_LEGACY) | |
999 | return -EINVAL; | |
1000 | } else { | |
1001 | if (rec->src_height > IMAGE_MAX_HEIGHT || | |
1002 | rec->src_width > IMAGE_MAX_WIDTH) | |
1003 | return -EINVAL; | |
1004 | } | |
1005 | ||
1006 | /* better safe than sorry, use 4 as the maximal subsampling ratio */ | |
1007 | if (rec->src_height < N_VERT_Y_TAPS*4 || | |
1008 | rec->src_width < N_HORIZ_Y_TAPS*4) | |
1009 | return -EINVAL; | |
1010 | ||
1011 | /* check alignment constraints */ | |
1012 | switch (rec->flags & I915_OVERLAY_TYPE_MASK) { | |
1013 | case I915_OVERLAY_RGB: | |
1014 | /* not implemented */ | |
1015 | return -EINVAL; | |
1016 | ||
1017 | case I915_OVERLAY_YUV_PACKED: | |
1018 | if (uv_vscale != 1) | |
1019 | return -EINVAL; | |
1020 | ||
1021 | depth = packed_depth_bytes(rec->flags); | |
1022 | if (depth < 0) | |
1023 | return depth; | |
1024 | ||
1025 | /* ignore UV planes */ | |
1026 | rec->stride_UV = 0; | |
1027 | rec->offset_U = 0; | |
1028 | rec->offset_V = 0; | |
1029 | /* check pixel alignment */ | |
1030 | if (rec->offset_Y % depth) | |
1031 | return -EINVAL; | |
1032 | break; | |
1033 | ||
1034 | case I915_OVERLAY_YUV_PLANAR: | |
1035 | if (uv_vscale < 0 || uv_hscale < 0) | |
1036 | return -EINVAL; | |
1037 | /* no offset restrictions for planar formats */ | |
1038 | break; | |
1039 | ||
1040 | default: | |
1041 | return -EINVAL; | |
1042 | } | |
1043 | ||
1044 | if (rec->src_width % uv_hscale) | |
1045 | return -EINVAL; | |
1046 | ||
1047 | /* stride checking */ | |
1048 | if (IS_I830(dev_priv) || IS_I845G(dev_priv)) | |
1049 | stride_mask = 255; | |
1050 | else | |
1051 | stride_mask = 63; | |
1052 | ||
1053 | if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) | |
1054 | return -EINVAL; | |
1055 | if (IS_GEN4(dev_priv) && rec->stride_Y < 512) | |
1056 | return -EINVAL; | |
1057 | ||
1058 | tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? | |
1059 | 4096 : 8192; | |
1060 | if (rec->stride_Y > tmp || rec->stride_UV > 2*1024) | |
1061 | return -EINVAL; | |
1062 | ||
1063 | /* check buffer dimensions */ | |
1064 | switch (rec->flags & I915_OVERLAY_TYPE_MASK) { | |
1065 | case I915_OVERLAY_RGB: | |
1066 | case I915_OVERLAY_YUV_PACKED: | |
1067 | /* always 4 Y values per depth pixels */ | |
1068 | if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y) | |
1069 | return -EINVAL; | |
1070 | ||
1071 | tmp = rec->stride_Y*rec->src_height; | |
1072 | if (rec->offset_Y + tmp > new_bo->base.size) | |
1073 | return -EINVAL; | |
1074 | break; | |
1075 | ||
1076 | case I915_OVERLAY_YUV_PLANAR: | |
1077 | if (rec->src_width > rec->stride_Y) | |
1078 | return -EINVAL; | |
1079 | if (rec->src_width/uv_hscale > rec->stride_UV) | |
1080 | return -EINVAL; | |
1081 | ||
1082 | tmp = rec->stride_Y * rec->src_height; | |
1083 | if (rec->offset_Y + tmp > new_bo->base.size) | |
1084 | return -EINVAL; | |
1085 | ||
1086 | tmp = rec->stride_UV * (rec->src_height / uv_vscale); | |
1087 | if (rec->offset_U + tmp > new_bo->base.size || | |
1088 | rec->offset_V + tmp > new_bo->base.size) | |
1089 | return -EINVAL; | |
1090 | break; | |
1091 | } | |
1092 | ||
1093 | return 0; | |
1094 | } | |
1095 | ||
1096 | int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, | |
1097 | struct drm_file *file_priv) | |
1098 | { | |
1099 | struct drm_intel_overlay_put_image *put_image_rec = data; | |
1100 | struct drm_i915_private *dev_priv = to_i915(dev); | |
1101 | struct intel_overlay *overlay; | |
1102 | struct drm_crtc *drmmode_crtc; | |
1103 | struct intel_crtc *crtc; | |
1104 | struct drm_i915_gem_object *new_bo; | |
1105 | struct put_image_params *params; | |
1106 | int ret; | |
1107 | ||
1108 | overlay = dev_priv->overlay; | |
1109 | if (!overlay) { | |
1110 | DRM_DEBUG("userspace bug: no overlay\n"); | |
1111 | return -ENODEV; | |
1112 | } | |
1113 | ||
1114 | if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) { | |
1115 | drm_modeset_lock_all(dev); | |
1116 | mutex_lock(&dev->struct_mutex); | |
1117 | ||
1118 | ret = intel_overlay_switch_off(overlay); | |
1119 | ||
1120 | mutex_unlock(&dev->struct_mutex); | |
1121 | drm_modeset_unlock_all(dev); | |
1122 | ||
1123 | return ret; | |
1124 | } | |
1125 | ||
1126 | params = kmalloc(sizeof(*params), GFP_KERNEL); | |
1127 | if (!params) | |
1128 | return -ENOMEM; | |
1129 | ||
1130 | drmmode_crtc = drm_crtc_find(dev, put_image_rec->crtc_id); | |
1131 | if (!drmmode_crtc) { | |
1132 | ret = -ENOENT; | |
1133 | goto out_free; | |
1134 | } | |
1135 | crtc = to_intel_crtc(drmmode_crtc); | |
1136 | ||
1137 | new_bo = i915_gem_object_lookup(file_priv, put_image_rec->bo_handle); | |
1138 | if (!new_bo) { | |
1139 | ret = -ENOENT; | |
1140 | goto out_free; | |
1141 | } | |
1142 | ||
1143 | drm_modeset_lock_all(dev); | |
1144 | mutex_lock(&dev->struct_mutex); | |
1145 | ||
1146 | if (i915_gem_object_is_tiled(new_bo)) { | |
1147 | DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n"); | |
1148 | ret = -EINVAL; | |
1149 | goto out_unlock; | |
1150 | } | |
1151 | ||
1152 | ret = intel_overlay_recover_from_interrupt(overlay); | |
1153 | if (ret != 0) | |
1154 | goto out_unlock; | |
1155 | ||
1156 | if (overlay->crtc != crtc) { | |
1157 | ret = intel_overlay_switch_off(overlay); | |
1158 | if (ret != 0) | |
1159 | goto out_unlock; | |
1160 | ||
1161 | ret = check_overlay_possible_on_crtc(overlay, crtc); | |
1162 | if (ret != 0) | |
1163 | goto out_unlock; | |
1164 | ||
1165 | overlay->crtc = crtc; | |
1166 | crtc->overlay = overlay; | |
1167 | ||
1168 | /* line too wide, i.e. one-line-mode */ | |
1169 | if (crtc->config->pipe_src_w > 1024 && | |
1170 | crtc->config->gmch_pfit.control & PFIT_ENABLE) { | |
1171 | overlay->pfit_active = true; | |
1172 | update_pfit_vscale_ratio(overlay); | |
1173 | } else | |
1174 | overlay->pfit_active = false; | |
1175 | } | |
1176 | ||
1177 | ret = check_overlay_dst(overlay, put_image_rec); | |
1178 | if (ret != 0) | |
1179 | goto out_unlock; | |
1180 | ||
1181 | if (overlay->pfit_active) { | |
1182 | params->dst_y = ((((u32)put_image_rec->dst_y) << 12) / | |
1183 | overlay->pfit_vscale_ratio); | |
1184 | /* shifting right rounds downwards, so add 1 */ | |
1185 | params->dst_h = ((((u32)put_image_rec->dst_height) << 12) / | |
1186 | overlay->pfit_vscale_ratio) + 1; | |
1187 | } else { | |
1188 | params->dst_y = put_image_rec->dst_y; | |
1189 | params->dst_h = put_image_rec->dst_height; | |
1190 | } | |
1191 | params->dst_x = put_image_rec->dst_x; | |
1192 | params->dst_w = put_image_rec->dst_width; | |
1193 | ||
1194 | params->src_w = put_image_rec->src_width; | |
1195 | params->src_h = put_image_rec->src_height; | |
1196 | params->src_scan_w = put_image_rec->src_scan_width; | |
1197 | params->src_scan_h = put_image_rec->src_scan_height; | |
1198 | if (params->src_scan_h > params->src_h || | |
1199 | params->src_scan_w > params->src_w) { | |
1200 | ret = -EINVAL; | |
1201 | goto out_unlock; | |
1202 | } | |
1203 | ||
1204 | ret = check_overlay_src(dev_priv, put_image_rec, new_bo); | |
1205 | if (ret != 0) | |
1206 | goto out_unlock; | |
1207 | params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK; | |
1208 | params->stride_Y = put_image_rec->stride_Y; | |
1209 | params->stride_UV = put_image_rec->stride_UV; | |
1210 | params->offset_Y = put_image_rec->offset_Y; | |
1211 | params->offset_U = put_image_rec->offset_U; | |
1212 | params->offset_V = put_image_rec->offset_V; | |
1213 | ||
1214 | /* Check scaling after src size to prevent a divide-by-zero. */ | |
1215 | ret = check_overlay_scaling(params); | |
1216 | if (ret != 0) | |
1217 | goto out_unlock; | |
1218 | ||
1219 | ret = intel_overlay_do_put_image(overlay, new_bo, params); | |
1220 | if (ret != 0) | |
1221 | goto out_unlock; | |
1222 | ||
1223 | mutex_unlock(&dev->struct_mutex); | |
1224 | drm_modeset_unlock_all(dev); | |
1225 | i915_gem_object_put(new_bo); | |
1226 | ||
1227 | kfree(params); | |
1228 | ||
1229 | return 0; | |
1230 | ||
1231 | out_unlock: | |
1232 | mutex_unlock(&dev->struct_mutex); | |
1233 | drm_modeset_unlock_all(dev); | |
1234 | i915_gem_object_put(new_bo); | |
1235 | out_free: | |
1236 | kfree(params); | |
1237 | ||
1238 | return ret; | |
1239 | } | |
1240 | ||
1241 | static void update_reg_attrs(struct intel_overlay *overlay, | |
1242 | struct overlay_registers __iomem *regs) | |
1243 | { | |
1244 | iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff), | |
1245 | ®s->OCLRC0); | |
1246 | iowrite32(overlay->saturation, ®s->OCLRC1); | |
1247 | } | |
1248 | ||
1249 | static bool check_gamma_bounds(u32 gamma1, u32 gamma2) | |
1250 | { | |
1251 | int i; | |
1252 | ||
1253 | if (gamma1 & 0xff000000 || gamma2 & 0xff000000) | |
1254 | return false; | |
1255 | ||
1256 | for (i = 0; i < 3; i++) { | |
1257 | if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff)) | |
1258 | return false; | |
1259 | } | |
1260 | ||
1261 | return true; | |
1262 | } | |
1263 | ||
1264 | static bool check_gamma5_errata(u32 gamma5) | |
1265 | { | |
1266 | int i; | |
1267 | ||
1268 | for (i = 0; i < 3; i++) { | |
1269 | if (((gamma5 >> i*8) & 0xff) == 0x80) | |
1270 | return false; | |
1271 | } | |
1272 | ||
1273 | return true; | |
1274 | } | |
1275 | ||
1276 | static int check_gamma(struct drm_intel_overlay_attrs *attrs) | |
1277 | { | |
1278 | if (!check_gamma_bounds(0, attrs->gamma0) || | |
1279 | !check_gamma_bounds(attrs->gamma0, attrs->gamma1) || | |
1280 | !check_gamma_bounds(attrs->gamma1, attrs->gamma2) || | |
1281 | !check_gamma_bounds(attrs->gamma2, attrs->gamma3) || | |
1282 | !check_gamma_bounds(attrs->gamma3, attrs->gamma4) || | |
1283 | !check_gamma_bounds(attrs->gamma4, attrs->gamma5) || | |
1284 | !check_gamma_bounds(attrs->gamma5, 0x00ffffff)) | |
1285 | return -EINVAL; | |
1286 | ||
1287 | if (!check_gamma5_errata(attrs->gamma5)) | |
1288 | return -EINVAL; | |
1289 | ||
1290 | return 0; | |
1291 | } | |
1292 | ||
1293 | int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, | |
1294 | struct drm_file *file_priv) | |
1295 | { | |
1296 | struct drm_intel_overlay_attrs *attrs = data; | |
1297 | struct drm_i915_private *dev_priv = to_i915(dev); | |
1298 | struct intel_overlay *overlay; | |
1299 | struct overlay_registers __iomem *regs; | |
1300 | int ret; | |
1301 | ||
1302 | overlay = dev_priv->overlay; | |
1303 | if (!overlay) { | |
1304 | DRM_DEBUG("userspace bug: no overlay\n"); | |
1305 | return -ENODEV; | |
1306 | } | |
1307 | ||
1308 | drm_modeset_lock_all(dev); | |
1309 | mutex_lock(&dev->struct_mutex); | |
1310 | ||
1311 | ret = -EINVAL; | |
1312 | if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) { | |
1313 | attrs->color_key = overlay->color_key; | |
1314 | attrs->brightness = overlay->brightness; | |
1315 | attrs->contrast = overlay->contrast; | |
1316 | attrs->saturation = overlay->saturation; | |
1317 | ||
1318 | if (!IS_GEN2(dev_priv)) { | |
1319 | attrs->gamma0 = I915_READ(OGAMC0); | |
1320 | attrs->gamma1 = I915_READ(OGAMC1); | |
1321 | attrs->gamma2 = I915_READ(OGAMC2); | |
1322 | attrs->gamma3 = I915_READ(OGAMC3); | |
1323 | attrs->gamma4 = I915_READ(OGAMC4); | |
1324 | attrs->gamma5 = I915_READ(OGAMC5); | |
1325 | } | |
1326 | } else { | |
1327 | if (attrs->brightness < -128 || attrs->brightness > 127) | |
1328 | goto out_unlock; | |
1329 | if (attrs->contrast > 255) | |
1330 | goto out_unlock; | |
1331 | if (attrs->saturation > 1023) | |
1332 | goto out_unlock; | |
1333 | ||
1334 | overlay->color_key = attrs->color_key; | |
1335 | overlay->brightness = attrs->brightness; | |
1336 | overlay->contrast = attrs->contrast; | |
1337 | overlay->saturation = attrs->saturation; | |
1338 | ||
1339 | regs = intel_overlay_map_regs(overlay); | |
1340 | if (!regs) { | |
1341 | ret = -ENOMEM; | |
1342 | goto out_unlock; | |
1343 | } | |
1344 | ||
1345 | update_reg_attrs(overlay, regs); | |
1346 | ||
1347 | intel_overlay_unmap_regs(overlay, regs); | |
1348 | ||
1349 | if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { | |
1350 | if (IS_GEN2(dev_priv)) | |
1351 | goto out_unlock; | |
1352 | ||
1353 | if (overlay->active) { | |
1354 | ret = -EBUSY; | |
1355 | goto out_unlock; | |
1356 | } | |
1357 | ||
1358 | ret = check_gamma(attrs); | |
1359 | if (ret) | |
1360 | goto out_unlock; | |
1361 | ||
1362 | I915_WRITE(OGAMC0, attrs->gamma0); | |
1363 | I915_WRITE(OGAMC1, attrs->gamma1); | |
1364 | I915_WRITE(OGAMC2, attrs->gamma2); | |
1365 | I915_WRITE(OGAMC3, attrs->gamma3); | |
1366 | I915_WRITE(OGAMC4, attrs->gamma4); | |
1367 | I915_WRITE(OGAMC5, attrs->gamma5); | |
1368 | } | |
1369 | } | |
1370 | overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; | |
1371 | ||
1372 | ret = 0; | |
1373 | out_unlock: | |
1374 | mutex_unlock(&dev->struct_mutex); | |
1375 | drm_modeset_unlock_all(dev); | |
1376 | ||
1377 | return ret; | |
1378 | } | |
1379 | ||
1380 | void intel_setup_overlay(struct drm_i915_private *dev_priv) | |
1381 | { | |
1382 | struct intel_overlay *overlay; | |
1383 | struct drm_i915_gem_object *reg_bo; | |
1384 | struct overlay_registers __iomem *regs; | |
1385 | struct i915_vma *vma = NULL; | |
1386 | int ret; | |
1387 | ||
1388 | if (!HAS_OVERLAY(dev_priv)) | |
1389 | return; | |
1390 | ||
1391 | overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); | |
1392 | if (!overlay) | |
1393 | return; | |
1394 | ||
1395 | mutex_lock(&dev_priv->drm.struct_mutex); | |
1396 | if (WARN_ON(dev_priv->overlay)) | |
1397 | goto out_free; | |
1398 | ||
1399 | overlay->i915 = dev_priv; | |
1400 | ||
1401 | reg_bo = NULL; | |
1402 | if (!OVERLAY_NEEDS_PHYSICAL(dev_priv)) | |
1403 | reg_bo = i915_gem_object_create_stolen(dev_priv, PAGE_SIZE); | |
1404 | if (reg_bo == NULL) | |
1405 | reg_bo = i915_gem_object_create(dev_priv, PAGE_SIZE); | |
1406 | if (IS_ERR(reg_bo)) | |
1407 | goto out_free; | |
1408 | overlay->reg_bo = reg_bo; | |
1409 | ||
1410 | if (OVERLAY_NEEDS_PHYSICAL(dev_priv)) { | |
1411 | ret = i915_gem_object_attach_phys(reg_bo, PAGE_SIZE); | |
1412 | if (ret) { | |
1413 | DRM_ERROR("failed to attach phys overlay regs\n"); | |
1414 | goto out_free_bo; | |
1415 | } | |
1416 | overlay->flip_addr = reg_bo->phys_handle->busaddr; | |
1417 | } else { | |
1418 | vma = i915_gem_object_ggtt_pin(reg_bo, NULL, | |
1419 | 0, PAGE_SIZE, PIN_MAPPABLE); | |
1420 | if (IS_ERR(vma)) { | |
1421 | DRM_ERROR("failed to pin overlay register bo\n"); | |
1422 | ret = PTR_ERR(vma); | |
1423 | goto out_free_bo; | |
1424 | } | |
1425 | overlay->flip_addr = i915_ggtt_offset(vma); | |
1426 | ||
1427 | ret = i915_gem_object_set_to_gtt_domain(reg_bo, true); | |
1428 | if (ret) { | |
1429 | DRM_ERROR("failed to move overlay register bo into the GTT\n"); | |
1430 | goto out_unpin_bo; | |
1431 | } | |
1432 | } | |
1433 | ||
1434 | /* init all values */ | |
1435 | overlay->color_key = 0x0101fe; | |
1436 | overlay->color_key_enabled = true; | |
1437 | overlay->brightness = -19; | |
1438 | overlay->contrast = 75; | |
1439 | overlay->saturation = 146; | |
1440 | ||
1441 | init_request_active(&overlay->last_flip, NULL); | |
1442 | ||
1443 | regs = intel_overlay_map_regs(overlay); | |
1444 | if (!regs) | |
1445 | goto out_unpin_bo; | |
1446 | ||
1447 | memset_io(regs, 0, sizeof(struct overlay_registers)); | |
1448 | update_polyphase_filter(regs); | |
1449 | update_reg_attrs(overlay, regs); | |
1450 | ||
1451 | intel_overlay_unmap_regs(overlay, regs); | |
1452 | ||
1453 | dev_priv->overlay = overlay; | |
1454 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
1455 | DRM_INFO("initialized overlay support\n"); | |
1456 | return; | |
1457 | ||
1458 | out_unpin_bo: | |
1459 | if (vma) | |
1460 | i915_vma_unpin(vma); | |
1461 | out_free_bo: | |
1462 | i915_gem_object_put(reg_bo); | |
1463 | out_free: | |
1464 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
1465 | kfree(overlay); | |
1466 | return; | |
1467 | } | |
1468 | ||
1469 | void intel_cleanup_overlay(struct drm_i915_private *dev_priv) | |
1470 | { | |
1471 | if (!dev_priv->overlay) | |
1472 | return; | |
1473 | ||
1474 | /* The bo's should be free'd by the generic code already. | |
1475 | * Furthermore modesetting teardown happens beforehand so the | |
1476 | * hardware should be off already */ | |
1477 | WARN_ON(dev_priv->overlay->active); | |
1478 | ||
1479 | i915_gem_object_put(dev_priv->overlay->reg_bo); | |
1480 | kfree(dev_priv->overlay); | |
1481 | } | |
1482 | ||
1483 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) | |
1484 | ||
1485 | struct intel_overlay_error_state { | |
1486 | struct overlay_registers regs; | |
1487 | unsigned long base; | |
1488 | u32 dovsta; | |
1489 | u32 isr; | |
1490 | }; | |
1491 | ||
1492 | static struct overlay_registers __iomem * | |
1493 | intel_overlay_map_regs_atomic(struct intel_overlay *overlay) | |
1494 | { | |
1495 | struct drm_i915_private *dev_priv = overlay->i915; | |
1496 | struct overlay_registers __iomem *regs; | |
1497 | ||
1498 | if (OVERLAY_NEEDS_PHYSICAL(dev_priv)) | |
1499 | /* Cast to make sparse happy, but it's wc memory anyway, so | |
1500 | * equivalent to the wc io mapping on X86. */ | |
1501 | regs = (struct overlay_registers __iomem *) | |
1502 | overlay->reg_bo->phys_handle->vaddr; | |
1503 | else | |
1504 | regs = io_mapping_map_atomic_wc(&dev_priv->ggtt.mappable, | |
1505 | overlay->flip_addr); | |
1506 | ||
1507 | return regs; | |
1508 | } | |
1509 | ||
1510 | static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay, | |
1511 | struct overlay_registers __iomem *regs) | |
1512 | { | |
1513 | if (!OVERLAY_NEEDS_PHYSICAL(overlay->i915)) | |
1514 | io_mapping_unmap_atomic(regs); | |
1515 | } | |
1516 | ||
1517 | struct intel_overlay_error_state * | |
1518 | intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) | |
1519 | { | |
1520 | struct intel_overlay *overlay = dev_priv->overlay; | |
1521 | struct intel_overlay_error_state *error; | |
1522 | struct overlay_registers __iomem *regs; | |
1523 | ||
1524 | if (!overlay || !overlay->active) | |
1525 | return NULL; | |
1526 | ||
1527 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
1528 | if (error == NULL) | |
1529 | return NULL; | |
1530 | ||
1531 | error->dovsta = I915_READ(DOVSTA); | |
1532 | error->isr = I915_READ(ISR); | |
1533 | error->base = overlay->flip_addr; | |
1534 | ||
1535 | regs = intel_overlay_map_regs_atomic(overlay); | |
1536 | if (!regs) | |
1537 | goto err; | |
1538 | ||
1539 | memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers)); | |
1540 | intel_overlay_unmap_regs_atomic(overlay, regs); | |
1541 | ||
1542 | return error; | |
1543 | ||
1544 | err: | |
1545 | kfree(error); | |
1546 | return NULL; | |
1547 | } | |
1548 | ||
1549 | void | |
1550 | intel_overlay_print_error_state(struct drm_i915_error_state_buf *m, | |
1551 | struct intel_overlay_error_state *error) | |
1552 | { | |
1553 | i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", | |
1554 | error->dovsta, error->isr); | |
1555 | i915_error_printf(m, " Register file at 0x%08lx:\n", | |
1556 | error->base); | |
1557 | ||
1558 | #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x) | |
1559 | P(OBUF_0Y); | |
1560 | P(OBUF_1Y); | |
1561 | P(OBUF_0U); | |
1562 | P(OBUF_0V); | |
1563 | P(OBUF_1U); | |
1564 | P(OBUF_1V); | |
1565 | P(OSTRIDE); | |
1566 | P(YRGB_VPH); | |
1567 | P(UV_VPH); | |
1568 | P(HORZ_PH); | |
1569 | P(INIT_PHS); | |
1570 | P(DWINPOS); | |
1571 | P(DWINSZ); | |
1572 | P(SWIDTH); | |
1573 | P(SWIDTHSW); | |
1574 | P(SHEIGHT); | |
1575 | P(YRGBSCALE); | |
1576 | P(UVSCALE); | |
1577 | P(OCLRC0); | |
1578 | P(OCLRC1); | |
1579 | P(DCLRKV); | |
1580 | P(DCLRKM); | |
1581 | P(SCLRKVH); | |
1582 | P(SCLRKVL); | |
1583 | P(SCLRKEN); | |
1584 | P(OCONFIG); | |
1585 | P(OCMD); | |
1586 | P(OSTART_0Y); | |
1587 | P(OSTART_1Y); | |
1588 | P(OSTART_0U); | |
1589 | P(OSTART_0V); | |
1590 | P(OSTART_1U); | |
1591 | P(OSTART_1V); | |
1592 | P(OTILEOFF_0Y); | |
1593 | P(OTILEOFF_1Y); | |
1594 | P(OTILEOFF_0U); | |
1595 | P(OTILEOFF_0V); | |
1596 | P(OTILEOFF_1U); | |
1597 | P(OTILEOFF_1V); | |
1598 | P(FASTHSCALE); | |
1599 | P(UVSCALEV); | |
1600 | #undef P | |
1601 | } | |
1602 | ||
1603 | #endif |