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1 | /* | |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/cpufreq.h> | |
29 | #include "i915_drv.h" | |
30 | #include "intel_drv.h" | |
31 | #include "../../../platform/x86/intel_ips.h" | |
32 | #include <linux/module.h> | |
33 | ||
34 | /** | |
35 | * RC6 is a special power stage which allows the GPU to enter an very | |
36 | * low-voltage mode when idle, using down to 0V while at this stage. This | |
37 | * stage is entered automatically when the GPU is idle when RC6 support is | |
38 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. | |
39 | * | |
40 | * There are different RC6 modes available in Intel GPU, which differentiate | |
41 | * among each other with the latency required to enter and leave RC6 and | |
42 | * voltage consumed by the GPU in different states. | |
43 | * | |
44 | * The combination of the following flags define which states GPU is allowed | |
45 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and | |
46 | * RC6pp is deepest RC6. Their support by hardware varies according to the | |
47 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one | |
48 | * which brings the most power savings; deeper states save more power, but | |
49 | * require higher latency to switch to and wake up. | |
50 | */ | |
51 | #define INTEL_RC6_ENABLE (1<<0) | |
52 | #define INTEL_RC6p_ENABLE (1<<1) | |
53 | #define INTEL_RC6pp_ENABLE (1<<2) | |
54 | ||
55 | static void gen9_init_clock_gating(struct drm_device *dev) | |
56 | { | |
57 | struct drm_i915_private *dev_priv = dev->dev_private; | |
58 | ||
59 | /* | |
60 | * WaDisableSDEUnitClockGating:skl | |
61 | * This seems to be a pre-production w/a. | |
62 | */ | |
63 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
64 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
65 | ||
66 | /* | |
67 | * WaDisableDgMirrorFixInHalfSliceChicken5:skl | |
68 | * This is a pre-production w/a. | |
69 | */ | |
70 | I915_WRITE(GEN9_HALF_SLICE_CHICKEN5, | |
71 | I915_READ(GEN9_HALF_SLICE_CHICKEN5) & | |
72 | ~GEN9_DG_MIRROR_FIX_ENABLE); | |
73 | ||
74 | /* Wa4x4STCOptimizationDisable:skl */ | |
75 | I915_WRITE(CACHE_MODE_1, | |
76 | _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE)); | |
77 | } | |
78 | ||
79 | static void i915_pineview_get_mem_freq(struct drm_device *dev) | |
80 | { | |
81 | struct drm_i915_private *dev_priv = dev->dev_private; | |
82 | u32 tmp; | |
83 | ||
84 | tmp = I915_READ(CLKCFG); | |
85 | ||
86 | switch (tmp & CLKCFG_FSB_MASK) { | |
87 | case CLKCFG_FSB_533: | |
88 | dev_priv->fsb_freq = 533; /* 133*4 */ | |
89 | break; | |
90 | case CLKCFG_FSB_800: | |
91 | dev_priv->fsb_freq = 800; /* 200*4 */ | |
92 | break; | |
93 | case CLKCFG_FSB_667: | |
94 | dev_priv->fsb_freq = 667; /* 167*4 */ | |
95 | break; | |
96 | case CLKCFG_FSB_400: | |
97 | dev_priv->fsb_freq = 400; /* 100*4 */ | |
98 | break; | |
99 | } | |
100 | ||
101 | switch (tmp & CLKCFG_MEM_MASK) { | |
102 | case CLKCFG_MEM_533: | |
103 | dev_priv->mem_freq = 533; | |
104 | break; | |
105 | case CLKCFG_MEM_667: | |
106 | dev_priv->mem_freq = 667; | |
107 | break; | |
108 | case CLKCFG_MEM_800: | |
109 | dev_priv->mem_freq = 800; | |
110 | break; | |
111 | } | |
112 | ||
113 | /* detect pineview DDR3 setting */ | |
114 | tmp = I915_READ(CSHRDDR3CTL); | |
115 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; | |
116 | } | |
117 | ||
118 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) | |
119 | { | |
120 | struct drm_i915_private *dev_priv = dev->dev_private; | |
121 | u16 ddrpll, csipll; | |
122 | ||
123 | ddrpll = I915_READ16(DDRMPLL1); | |
124 | csipll = I915_READ16(CSIPLL0); | |
125 | ||
126 | switch (ddrpll & 0xff) { | |
127 | case 0xc: | |
128 | dev_priv->mem_freq = 800; | |
129 | break; | |
130 | case 0x10: | |
131 | dev_priv->mem_freq = 1066; | |
132 | break; | |
133 | case 0x14: | |
134 | dev_priv->mem_freq = 1333; | |
135 | break; | |
136 | case 0x18: | |
137 | dev_priv->mem_freq = 1600; | |
138 | break; | |
139 | default: | |
140 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", | |
141 | ddrpll & 0xff); | |
142 | dev_priv->mem_freq = 0; | |
143 | break; | |
144 | } | |
145 | ||
146 | dev_priv->ips.r_t = dev_priv->mem_freq; | |
147 | ||
148 | switch (csipll & 0x3ff) { | |
149 | case 0x00c: | |
150 | dev_priv->fsb_freq = 3200; | |
151 | break; | |
152 | case 0x00e: | |
153 | dev_priv->fsb_freq = 3733; | |
154 | break; | |
155 | case 0x010: | |
156 | dev_priv->fsb_freq = 4266; | |
157 | break; | |
158 | case 0x012: | |
159 | dev_priv->fsb_freq = 4800; | |
160 | break; | |
161 | case 0x014: | |
162 | dev_priv->fsb_freq = 5333; | |
163 | break; | |
164 | case 0x016: | |
165 | dev_priv->fsb_freq = 5866; | |
166 | break; | |
167 | case 0x018: | |
168 | dev_priv->fsb_freq = 6400; | |
169 | break; | |
170 | default: | |
171 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", | |
172 | csipll & 0x3ff); | |
173 | dev_priv->fsb_freq = 0; | |
174 | break; | |
175 | } | |
176 | ||
177 | if (dev_priv->fsb_freq == 3200) { | |
178 | dev_priv->ips.c_m = 0; | |
179 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { | |
180 | dev_priv->ips.c_m = 1; | |
181 | } else { | |
182 | dev_priv->ips.c_m = 2; | |
183 | } | |
184 | } | |
185 | ||
186 | static const struct cxsr_latency cxsr_latency_table[] = { | |
187 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ | |
188 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
189 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
190 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
191 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
192 | ||
193 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
194 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
195 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
196 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
197 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
198 | ||
199 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
200 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
201 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
202 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
203 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
204 | ||
205 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
206 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
207 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
208 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
209 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
210 | ||
211 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
212 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
213 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
214 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
215 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
216 | ||
217 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
218 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
219 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
220 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
221 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
222 | }; | |
223 | ||
224 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, | |
225 | int is_ddr3, | |
226 | int fsb, | |
227 | int mem) | |
228 | { | |
229 | const struct cxsr_latency *latency; | |
230 | int i; | |
231 | ||
232 | if (fsb == 0 || mem == 0) | |
233 | return NULL; | |
234 | ||
235 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
236 | latency = &cxsr_latency_table[i]; | |
237 | if (is_desktop == latency->is_desktop && | |
238 | is_ddr3 == latency->is_ddr3 && | |
239 | fsb == latency->fsb_freq && mem == latency->mem_freq) | |
240 | return latency; | |
241 | } | |
242 | ||
243 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
244 | ||
245 | return NULL; | |
246 | } | |
247 | ||
248 | void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) | |
249 | { | |
250 | struct drm_device *dev = dev_priv->dev; | |
251 | u32 val; | |
252 | ||
253 | if (IS_VALLEYVIEW(dev)) { | |
254 | I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); | |
255 | } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) { | |
256 | I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); | |
257 | } else if (IS_PINEVIEW(dev)) { | |
258 | val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN; | |
259 | val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0; | |
260 | I915_WRITE(DSPFW3, val); | |
261 | } else if (IS_I945G(dev) || IS_I945GM(dev)) { | |
262 | val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : | |
263 | _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); | |
264 | I915_WRITE(FW_BLC_SELF, val); | |
265 | } else if (IS_I915GM(dev)) { | |
266 | val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : | |
267 | _MASKED_BIT_DISABLE(INSTPM_SELF_EN); | |
268 | I915_WRITE(INSTPM, val); | |
269 | } else { | |
270 | return; | |
271 | } | |
272 | ||
273 | DRM_DEBUG_KMS("memory self-refresh is %s\n", | |
274 | enable ? "enabled" : "disabled"); | |
275 | } | |
276 | ||
277 | /* | |
278 | * Latency for FIFO fetches is dependent on several factors: | |
279 | * - memory configuration (speed, channels) | |
280 | * - chipset | |
281 | * - current MCH state | |
282 | * It can be fairly high in some situations, so here we assume a fairly | |
283 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
284 | * set this value too high, the FIFO will fetch frequently to stay full) | |
285 | * and power consumption (set it too low to save power and we might see | |
286 | * FIFO underruns and display "flicker"). | |
287 | * | |
288 | * A value of 5us seems to be a good balance; safe for very low end | |
289 | * platforms but not overly aggressive on lower latency configs. | |
290 | */ | |
291 | static const int pessimal_latency_ns = 5000; | |
292 | ||
293 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) | |
294 | { | |
295 | struct drm_i915_private *dev_priv = dev->dev_private; | |
296 | uint32_t dsparb = I915_READ(DSPARB); | |
297 | int size; | |
298 | ||
299 | size = dsparb & 0x7f; | |
300 | if (plane) | |
301 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
302 | ||
303 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
304 | plane ? "B" : "A", size); | |
305 | ||
306 | return size; | |
307 | } | |
308 | ||
309 | static int i830_get_fifo_size(struct drm_device *dev, int plane) | |
310 | { | |
311 | struct drm_i915_private *dev_priv = dev->dev_private; | |
312 | uint32_t dsparb = I915_READ(DSPARB); | |
313 | int size; | |
314 | ||
315 | size = dsparb & 0x1ff; | |
316 | if (plane) | |
317 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
318 | size >>= 1; /* Convert to cachelines */ | |
319 | ||
320 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
321 | plane ? "B" : "A", size); | |
322 | ||
323 | return size; | |
324 | } | |
325 | ||
326 | static int i845_get_fifo_size(struct drm_device *dev, int plane) | |
327 | { | |
328 | struct drm_i915_private *dev_priv = dev->dev_private; | |
329 | uint32_t dsparb = I915_READ(DSPARB); | |
330 | int size; | |
331 | ||
332 | size = dsparb & 0x7f; | |
333 | size >>= 2; /* Convert to cachelines */ | |
334 | ||
335 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
336 | plane ? "B" : "A", | |
337 | size); | |
338 | ||
339 | return size; | |
340 | } | |
341 | ||
342 | /* Pineview has different values for various configs */ | |
343 | static const struct intel_watermark_params pineview_display_wm = { | |
344 | .fifo_size = PINEVIEW_DISPLAY_FIFO, | |
345 | .max_wm = PINEVIEW_MAX_WM, | |
346 | .default_wm = PINEVIEW_DFT_WM, | |
347 | .guard_size = PINEVIEW_GUARD_WM, | |
348 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
349 | }; | |
350 | static const struct intel_watermark_params pineview_display_hplloff_wm = { | |
351 | .fifo_size = PINEVIEW_DISPLAY_FIFO, | |
352 | .max_wm = PINEVIEW_MAX_WM, | |
353 | .default_wm = PINEVIEW_DFT_HPLLOFF_WM, | |
354 | .guard_size = PINEVIEW_GUARD_WM, | |
355 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
356 | }; | |
357 | static const struct intel_watermark_params pineview_cursor_wm = { | |
358 | .fifo_size = PINEVIEW_CURSOR_FIFO, | |
359 | .max_wm = PINEVIEW_CURSOR_MAX_WM, | |
360 | .default_wm = PINEVIEW_CURSOR_DFT_WM, | |
361 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, | |
362 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
363 | }; | |
364 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { | |
365 | .fifo_size = PINEVIEW_CURSOR_FIFO, | |
366 | .max_wm = PINEVIEW_CURSOR_MAX_WM, | |
367 | .default_wm = PINEVIEW_CURSOR_DFT_WM, | |
368 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, | |
369 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
370 | }; | |
371 | static const struct intel_watermark_params g4x_wm_info = { | |
372 | .fifo_size = G4X_FIFO_SIZE, | |
373 | .max_wm = G4X_MAX_WM, | |
374 | .default_wm = G4X_MAX_WM, | |
375 | .guard_size = 2, | |
376 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
377 | }; | |
378 | static const struct intel_watermark_params g4x_cursor_wm_info = { | |
379 | .fifo_size = I965_CURSOR_FIFO, | |
380 | .max_wm = I965_CURSOR_MAX_WM, | |
381 | .default_wm = I965_CURSOR_DFT_WM, | |
382 | .guard_size = 2, | |
383 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
384 | }; | |
385 | static const struct intel_watermark_params valleyview_wm_info = { | |
386 | .fifo_size = VALLEYVIEW_FIFO_SIZE, | |
387 | .max_wm = VALLEYVIEW_MAX_WM, | |
388 | .default_wm = VALLEYVIEW_MAX_WM, | |
389 | .guard_size = 2, | |
390 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
391 | }; | |
392 | static const struct intel_watermark_params valleyview_cursor_wm_info = { | |
393 | .fifo_size = I965_CURSOR_FIFO, | |
394 | .max_wm = VALLEYVIEW_CURSOR_MAX_WM, | |
395 | .default_wm = I965_CURSOR_DFT_WM, | |
396 | .guard_size = 2, | |
397 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
398 | }; | |
399 | static const struct intel_watermark_params i965_cursor_wm_info = { | |
400 | .fifo_size = I965_CURSOR_FIFO, | |
401 | .max_wm = I965_CURSOR_MAX_WM, | |
402 | .default_wm = I965_CURSOR_DFT_WM, | |
403 | .guard_size = 2, | |
404 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
405 | }; | |
406 | static const struct intel_watermark_params i945_wm_info = { | |
407 | .fifo_size = I945_FIFO_SIZE, | |
408 | .max_wm = I915_MAX_WM, | |
409 | .default_wm = 1, | |
410 | .guard_size = 2, | |
411 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
412 | }; | |
413 | static const struct intel_watermark_params i915_wm_info = { | |
414 | .fifo_size = I915_FIFO_SIZE, | |
415 | .max_wm = I915_MAX_WM, | |
416 | .default_wm = 1, | |
417 | .guard_size = 2, | |
418 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
419 | }; | |
420 | static const struct intel_watermark_params i830_a_wm_info = { | |
421 | .fifo_size = I855GM_FIFO_SIZE, | |
422 | .max_wm = I915_MAX_WM, | |
423 | .default_wm = 1, | |
424 | .guard_size = 2, | |
425 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
426 | }; | |
427 | static const struct intel_watermark_params i830_bc_wm_info = { | |
428 | .fifo_size = I855GM_FIFO_SIZE, | |
429 | .max_wm = I915_MAX_WM/2, | |
430 | .default_wm = 1, | |
431 | .guard_size = 2, | |
432 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
433 | }; | |
434 | static const struct intel_watermark_params i845_wm_info = { | |
435 | .fifo_size = I830_FIFO_SIZE, | |
436 | .max_wm = I915_MAX_WM, | |
437 | .default_wm = 1, | |
438 | .guard_size = 2, | |
439 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
440 | }; | |
441 | ||
442 | /** | |
443 | * intel_calculate_wm - calculate watermark level | |
444 | * @clock_in_khz: pixel clock | |
445 | * @wm: chip FIFO params | |
446 | * @pixel_size: display pixel size | |
447 | * @latency_ns: memory latency for the platform | |
448 | * | |
449 | * Calculate the watermark level (the level at which the display plane will | |
450 | * start fetching from memory again). Each chip has a different display | |
451 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
452 | * in the correct intel_watermark_params structure. | |
453 | * | |
454 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
455 | * on the pixel size. When it reaches the watermark level, it'll start | |
456 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
457 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
458 | * will occur, and a display engine hang could result. | |
459 | */ | |
460 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, | |
461 | const struct intel_watermark_params *wm, | |
462 | int fifo_size, | |
463 | int pixel_size, | |
464 | unsigned long latency_ns) | |
465 | { | |
466 | long entries_required, wm_size; | |
467 | ||
468 | /* | |
469 | * Note: we need to make sure we don't overflow for various clock & | |
470 | * latency values. | |
471 | * clocks go from a few thousand to several hundred thousand. | |
472 | * latency is usually a few thousand | |
473 | */ | |
474 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / | |
475 | 1000; | |
476 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); | |
477 | ||
478 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); | |
479 | ||
480 | wm_size = fifo_size - (entries_required + wm->guard_size); | |
481 | ||
482 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); | |
483 | ||
484 | /* Don't promote wm_size to unsigned... */ | |
485 | if (wm_size > (long)wm->max_wm) | |
486 | wm_size = wm->max_wm; | |
487 | if (wm_size <= 0) | |
488 | wm_size = wm->default_wm; | |
489 | ||
490 | /* | |
491 | * Bspec seems to indicate that the value shouldn't be lower than | |
492 | * 'burst size + 1'. Certainly 830 is quite unhappy with low values. | |
493 | * Lets go for 8 which is the burst size since certain platforms | |
494 | * already use a hardcoded 8 (which is what the spec says should be | |
495 | * done). | |
496 | */ | |
497 | if (wm_size <= 8) | |
498 | wm_size = 8; | |
499 | ||
500 | return wm_size; | |
501 | } | |
502 | ||
503 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) | |
504 | { | |
505 | struct drm_crtc *crtc, *enabled = NULL; | |
506 | ||
507 | for_each_crtc(dev, crtc) { | |
508 | if (intel_crtc_active(crtc)) { | |
509 | if (enabled) | |
510 | return NULL; | |
511 | enabled = crtc; | |
512 | } | |
513 | } | |
514 | ||
515 | return enabled; | |
516 | } | |
517 | ||
518 | static void pineview_update_wm(struct drm_crtc *unused_crtc) | |
519 | { | |
520 | struct drm_device *dev = unused_crtc->dev; | |
521 | struct drm_i915_private *dev_priv = dev->dev_private; | |
522 | struct drm_crtc *crtc; | |
523 | const struct cxsr_latency *latency; | |
524 | u32 reg; | |
525 | unsigned long wm; | |
526 | ||
527 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, | |
528 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
529 | if (!latency) { | |
530 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
531 | intel_set_memory_cxsr(dev_priv, false); | |
532 | return; | |
533 | } | |
534 | ||
535 | crtc = single_enabled_crtc(dev); | |
536 | if (crtc) { | |
537 | const struct drm_display_mode *adjusted_mode; | |
538 | int pixel_size = crtc->primary->fb->bits_per_pixel / 8; | |
539 | int clock; | |
540 | ||
541 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; | |
542 | clock = adjusted_mode->crtc_clock; | |
543 | ||
544 | /* Display SR */ | |
545 | wm = intel_calculate_wm(clock, &pineview_display_wm, | |
546 | pineview_display_wm.fifo_size, | |
547 | pixel_size, latency->display_sr); | |
548 | reg = I915_READ(DSPFW1); | |
549 | reg &= ~DSPFW_SR_MASK; | |
550 | reg |= wm << DSPFW_SR_SHIFT; | |
551 | I915_WRITE(DSPFW1, reg); | |
552 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
553 | ||
554 | /* cursor SR */ | |
555 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, | |
556 | pineview_display_wm.fifo_size, | |
557 | pixel_size, latency->cursor_sr); | |
558 | reg = I915_READ(DSPFW3); | |
559 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
560 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; | |
561 | I915_WRITE(DSPFW3, reg); | |
562 | ||
563 | /* Display HPLL off SR */ | |
564 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, | |
565 | pineview_display_hplloff_wm.fifo_size, | |
566 | pixel_size, latency->display_hpll_disable); | |
567 | reg = I915_READ(DSPFW3); | |
568 | reg &= ~DSPFW_HPLL_SR_MASK; | |
569 | reg |= wm & DSPFW_HPLL_SR_MASK; | |
570 | I915_WRITE(DSPFW3, reg); | |
571 | ||
572 | /* cursor HPLL off SR */ | |
573 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, | |
574 | pineview_display_hplloff_wm.fifo_size, | |
575 | pixel_size, latency->cursor_hpll_disable); | |
576 | reg = I915_READ(DSPFW3); | |
577 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
578 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; | |
579 | I915_WRITE(DSPFW3, reg); | |
580 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
581 | ||
582 | intel_set_memory_cxsr(dev_priv, true); | |
583 | } else { | |
584 | intel_set_memory_cxsr(dev_priv, false); | |
585 | } | |
586 | } | |
587 | ||
588 | static bool g4x_compute_wm0(struct drm_device *dev, | |
589 | int plane, | |
590 | const struct intel_watermark_params *display, | |
591 | int display_latency_ns, | |
592 | const struct intel_watermark_params *cursor, | |
593 | int cursor_latency_ns, | |
594 | int *plane_wm, | |
595 | int *cursor_wm) | |
596 | { | |
597 | struct drm_crtc *crtc; | |
598 | const struct drm_display_mode *adjusted_mode; | |
599 | int htotal, hdisplay, clock, pixel_size; | |
600 | int line_time_us, line_count; | |
601 | int entries, tlb_miss; | |
602 | ||
603 | crtc = intel_get_crtc_for_plane(dev, plane); | |
604 | if (!intel_crtc_active(crtc)) { | |
605 | *cursor_wm = cursor->guard_size; | |
606 | *plane_wm = display->guard_size; | |
607 | return false; | |
608 | } | |
609 | ||
610 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; | |
611 | clock = adjusted_mode->crtc_clock; | |
612 | htotal = adjusted_mode->crtc_htotal; | |
613 | hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; | |
614 | pixel_size = crtc->primary->fb->bits_per_pixel / 8; | |
615 | ||
616 | /* Use the small buffer method to calculate plane watermark */ | |
617 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; | |
618 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; | |
619 | if (tlb_miss > 0) | |
620 | entries += tlb_miss; | |
621 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | |
622 | *plane_wm = entries + display->guard_size; | |
623 | if (*plane_wm > (int)display->max_wm) | |
624 | *plane_wm = display->max_wm; | |
625 | ||
626 | /* Use the large buffer method to calculate cursor watermark */ | |
627 | line_time_us = max(htotal * 1000 / clock, 1); | |
628 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; | |
629 | entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size; | |
630 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; | |
631 | if (tlb_miss > 0) | |
632 | entries += tlb_miss; | |
633 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
634 | *cursor_wm = entries + cursor->guard_size; | |
635 | if (*cursor_wm > (int)cursor->max_wm) | |
636 | *cursor_wm = (int)cursor->max_wm; | |
637 | ||
638 | return true; | |
639 | } | |
640 | ||
641 | /* | |
642 | * Check the wm result. | |
643 | * | |
644 | * If any calculated watermark values is larger than the maximum value that | |
645 | * can be programmed into the associated watermark register, that watermark | |
646 | * must be disabled. | |
647 | */ | |
648 | static bool g4x_check_srwm(struct drm_device *dev, | |
649 | int display_wm, int cursor_wm, | |
650 | const struct intel_watermark_params *display, | |
651 | const struct intel_watermark_params *cursor) | |
652 | { | |
653 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", | |
654 | display_wm, cursor_wm); | |
655 | ||
656 | if (display_wm > display->max_wm) { | |
657 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", | |
658 | display_wm, display->max_wm); | |
659 | return false; | |
660 | } | |
661 | ||
662 | if (cursor_wm > cursor->max_wm) { | |
663 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", | |
664 | cursor_wm, cursor->max_wm); | |
665 | return false; | |
666 | } | |
667 | ||
668 | if (!(display_wm || cursor_wm)) { | |
669 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); | |
670 | return false; | |
671 | } | |
672 | ||
673 | return true; | |
674 | } | |
675 | ||
676 | static bool g4x_compute_srwm(struct drm_device *dev, | |
677 | int plane, | |
678 | int latency_ns, | |
679 | const struct intel_watermark_params *display, | |
680 | const struct intel_watermark_params *cursor, | |
681 | int *display_wm, int *cursor_wm) | |
682 | { | |
683 | struct drm_crtc *crtc; | |
684 | const struct drm_display_mode *adjusted_mode; | |
685 | int hdisplay, htotal, pixel_size, clock; | |
686 | unsigned long line_time_us; | |
687 | int line_count, line_size; | |
688 | int small, large; | |
689 | int entries; | |
690 | ||
691 | if (!latency_ns) { | |
692 | *display_wm = *cursor_wm = 0; | |
693 | return false; | |
694 | } | |
695 | ||
696 | crtc = intel_get_crtc_for_plane(dev, plane); | |
697 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; | |
698 | clock = adjusted_mode->crtc_clock; | |
699 | htotal = adjusted_mode->crtc_htotal; | |
700 | hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; | |
701 | pixel_size = crtc->primary->fb->bits_per_pixel / 8; | |
702 | ||
703 | line_time_us = max(htotal * 1000 / clock, 1); | |
704 | line_count = (latency_ns / line_time_us + 1000) / 1000; | |
705 | line_size = hdisplay * pixel_size; | |
706 | ||
707 | /* Use the minimum of the small and large buffer method for primary */ | |
708 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
709 | large = line_count * line_size; | |
710 | ||
711 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); | |
712 | *display_wm = entries + display->guard_size; | |
713 | ||
714 | /* calculate the self-refresh watermark for display cursor */ | |
715 | entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width; | |
716 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
717 | *cursor_wm = entries + cursor->guard_size; | |
718 | ||
719 | return g4x_check_srwm(dev, | |
720 | *display_wm, *cursor_wm, | |
721 | display, cursor); | |
722 | } | |
723 | ||
724 | static bool vlv_compute_drain_latency(struct drm_crtc *crtc, | |
725 | int pixel_size, | |
726 | int *prec_mult, | |
727 | int *drain_latency) | |
728 | { | |
729 | struct drm_device *dev = crtc->dev; | |
730 | int entries; | |
731 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; | |
732 | ||
733 | if (WARN(clock == 0, "Pixel clock is zero!\n")) | |
734 | return false; | |
735 | ||
736 | if (WARN(pixel_size == 0, "Pixel size is zero!\n")) | |
737 | return false; | |
738 | ||
739 | entries = DIV_ROUND_UP(clock, 1000) * pixel_size; | |
740 | if (IS_CHERRYVIEW(dev)) | |
741 | *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_32 : | |
742 | DRAIN_LATENCY_PRECISION_16; | |
743 | else | |
744 | *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 : | |
745 | DRAIN_LATENCY_PRECISION_32; | |
746 | *drain_latency = (64 * (*prec_mult) * 4) / entries; | |
747 | ||
748 | if (*drain_latency > DRAIN_LATENCY_MASK) | |
749 | *drain_latency = DRAIN_LATENCY_MASK; | |
750 | ||
751 | return true; | |
752 | } | |
753 | ||
754 | /* | |
755 | * Update drain latency registers of memory arbiter | |
756 | * | |
757 | * Valleyview SoC has a new memory arbiter and needs drain latency registers | |
758 | * to be programmed. Each plane has a drain latency multiplier and a drain | |
759 | * latency value. | |
760 | */ | |
761 | ||
762 | static void vlv_update_drain_latency(struct drm_crtc *crtc) | |
763 | { | |
764 | struct drm_device *dev = crtc->dev; | |
765 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
767 | int pixel_size; | |
768 | int drain_latency; | |
769 | enum pipe pipe = intel_crtc->pipe; | |
770 | int plane_prec, prec_mult, plane_dl; | |
771 | const int high_precision = IS_CHERRYVIEW(dev) ? | |
772 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64; | |
773 | ||
774 | plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_HIGH | | |
775 | DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_HIGH | | |
776 | (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT)); | |
777 | ||
778 | if (!intel_crtc_active(crtc)) { | |
779 | I915_WRITE(VLV_DDL(pipe), plane_dl); | |
780 | return; | |
781 | } | |
782 | ||
783 | /* Primary plane Drain Latency */ | |
784 | pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */ | |
785 | if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) { | |
786 | plane_prec = (prec_mult == high_precision) ? | |
787 | DDL_PLANE_PRECISION_HIGH : | |
788 | DDL_PLANE_PRECISION_LOW; | |
789 | plane_dl |= plane_prec | drain_latency; | |
790 | } | |
791 | ||
792 | /* Cursor Drain Latency | |
793 | * BPP is always 4 for cursor | |
794 | */ | |
795 | pixel_size = 4; | |
796 | ||
797 | /* Program cursor DL only if it is enabled */ | |
798 | if (intel_crtc->cursor_base && | |
799 | vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) { | |
800 | plane_prec = (prec_mult == high_precision) ? | |
801 | DDL_CURSOR_PRECISION_HIGH : | |
802 | DDL_CURSOR_PRECISION_LOW; | |
803 | plane_dl |= plane_prec | (drain_latency << DDL_CURSOR_SHIFT); | |
804 | } | |
805 | ||
806 | I915_WRITE(VLV_DDL(pipe), plane_dl); | |
807 | } | |
808 | ||
809 | #define single_plane_enabled(mask) is_power_of_2(mask) | |
810 | ||
811 | static void valleyview_update_wm(struct drm_crtc *crtc) | |
812 | { | |
813 | struct drm_device *dev = crtc->dev; | |
814 | static const int sr_latency_ns = 12000; | |
815 | struct drm_i915_private *dev_priv = dev->dev_private; | |
816 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
817 | int plane_sr, cursor_sr; | |
818 | int ignore_plane_sr, ignore_cursor_sr; | |
819 | unsigned int enabled = 0; | |
820 | bool cxsr_enabled; | |
821 | ||
822 | vlv_update_drain_latency(crtc); | |
823 | ||
824 | if (g4x_compute_wm0(dev, PIPE_A, | |
825 | &valleyview_wm_info, pessimal_latency_ns, | |
826 | &valleyview_cursor_wm_info, pessimal_latency_ns, | |
827 | &planea_wm, &cursora_wm)) | |
828 | enabled |= 1 << PIPE_A; | |
829 | ||
830 | if (g4x_compute_wm0(dev, PIPE_B, | |
831 | &valleyview_wm_info, pessimal_latency_ns, | |
832 | &valleyview_cursor_wm_info, pessimal_latency_ns, | |
833 | &planeb_wm, &cursorb_wm)) | |
834 | enabled |= 1 << PIPE_B; | |
835 | ||
836 | if (single_plane_enabled(enabled) && | |
837 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
838 | sr_latency_ns, | |
839 | &valleyview_wm_info, | |
840 | &valleyview_cursor_wm_info, | |
841 | &plane_sr, &ignore_cursor_sr) && | |
842 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
843 | 2*sr_latency_ns, | |
844 | &valleyview_wm_info, | |
845 | &valleyview_cursor_wm_info, | |
846 | &ignore_plane_sr, &cursor_sr)) { | |
847 | cxsr_enabled = true; | |
848 | } else { | |
849 | cxsr_enabled = false; | |
850 | intel_set_memory_cxsr(dev_priv, false); | |
851 | plane_sr = cursor_sr = 0; | |
852 | } | |
853 | ||
854 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " | |
855 | "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", | |
856 | planea_wm, cursora_wm, | |
857 | planeb_wm, cursorb_wm, | |
858 | plane_sr, cursor_sr); | |
859 | ||
860 | I915_WRITE(DSPFW1, | |
861 | (plane_sr << DSPFW_SR_SHIFT) | | |
862 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
863 | (planeb_wm << DSPFW_PLANEB_SHIFT) | | |
864 | (planea_wm << DSPFW_PLANEA_SHIFT)); | |
865 | I915_WRITE(DSPFW2, | |
866 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | | |
867 | (cursora_wm << DSPFW_CURSORA_SHIFT)); | |
868 | I915_WRITE(DSPFW3, | |
869 | (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | | |
870 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
871 | ||
872 | if (cxsr_enabled) | |
873 | intel_set_memory_cxsr(dev_priv, true); | |
874 | } | |
875 | ||
876 | static void cherryview_update_wm(struct drm_crtc *crtc) | |
877 | { | |
878 | struct drm_device *dev = crtc->dev; | |
879 | static const int sr_latency_ns = 12000; | |
880 | struct drm_i915_private *dev_priv = dev->dev_private; | |
881 | int planea_wm, planeb_wm, planec_wm; | |
882 | int cursora_wm, cursorb_wm, cursorc_wm; | |
883 | int plane_sr, cursor_sr; | |
884 | int ignore_plane_sr, ignore_cursor_sr; | |
885 | unsigned int enabled = 0; | |
886 | bool cxsr_enabled; | |
887 | ||
888 | vlv_update_drain_latency(crtc); | |
889 | ||
890 | if (g4x_compute_wm0(dev, PIPE_A, | |
891 | &valleyview_wm_info, pessimal_latency_ns, | |
892 | &valleyview_cursor_wm_info, pessimal_latency_ns, | |
893 | &planea_wm, &cursora_wm)) | |
894 | enabled |= 1 << PIPE_A; | |
895 | ||
896 | if (g4x_compute_wm0(dev, PIPE_B, | |
897 | &valleyview_wm_info, pessimal_latency_ns, | |
898 | &valleyview_cursor_wm_info, pessimal_latency_ns, | |
899 | &planeb_wm, &cursorb_wm)) | |
900 | enabled |= 1 << PIPE_B; | |
901 | ||
902 | if (g4x_compute_wm0(dev, PIPE_C, | |
903 | &valleyview_wm_info, pessimal_latency_ns, | |
904 | &valleyview_cursor_wm_info, pessimal_latency_ns, | |
905 | &planec_wm, &cursorc_wm)) | |
906 | enabled |= 1 << PIPE_C; | |
907 | ||
908 | if (single_plane_enabled(enabled) && | |
909 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
910 | sr_latency_ns, | |
911 | &valleyview_wm_info, | |
912 | &valleyview_cursor_wm_info, | |
913 | &plane_sr, &ignore_cursor_sr) && | |
914 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
915 | 2*sr_latency_ns, | |
916 | &valleyview_wm_info, | |
917 | &valleyview_cursor_wm_info, | |
918 | &ignore_plane_sr, &cursor_sr)) { | |
919 | cxsr_enabled = true; | |
920 | } else { | |
921 | cxsr_enabled = false; | |
922 | intel_set_memory_cxsr(dev_priv, false); | |
923 | plane_sr = cursor_sr = 0; | |
924 | } | |
925 | ||
926 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " | |
927 | "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, " | |
928 | "SR: plane=%d, cursor=%d\n", | |
929 | planea_wm, cursora_wm, | |
930 | planeb_wm, cursorb_wm, | |
931 | planec_wm, cursorc_wm, | |
932 | plane_sr, cursor_sr); | |
933 | ||
934 | I915_WRITE(DSPFW1, | |
935 | (plane_sr << DSPFW_SR_SHIFT) | | |
936 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
937 | (planeb_wm << DSPFW_PLANEB_SHIFT) | | |
938 | (planea_wm << DSPFW_PLANEA_SHIFT)); | |
939 | I915_WRITE(DSPFW2, | |
940 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | | |
941 | (cursora_wm << DSPFW_CURSORA_SHIFT)); | |
942 | I915_WRITE(DSPFW3, | |
943 | (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | | |
944 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
945 | I915_WRITE(DSPFW9_CHV, | |
946 | (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK | | |
947 | DSPFW_CURSORC_MASK)) | | |
948 | (planec_wm << DSPFW_PLANEC_SHIFT) | | |
949 | (cursorc_wm << DSPFW_CURSORC_SHIFT)); | |
950 | ||
951 | if (cxsr_enabled) | |
952 | intel_set_memory_cxsr(dev_priv, true); | |
953 | } | |
954 | ||
955 | static void valleyview_update_sprite_wm(struct drm_plane *plane, | |
956 | struct drm_crtc *crtc, | |
957 | uint32_t sprite_width, | |
958 | uint32_t sprite_height, | |
959 | int pixel_size, | |
960 | bool enabled, bool scaled) | |
961 | { | |
962 | struct drm_device *dev = crtc->dev; | |
963 | struct drm_i915_private *dev_priv = dev->dev_private; | |
964 | int pipe = to_intel_plane(plane)->pipe; | |
965 | int sprite = to_intel_plane(plane)->plane; | |
966 | int drain_latency; | |
967 | int plane_prec; | |
968 | int sprite_dl; | |
969 | int prec_mult; | |
970 | const int high_precision = IS_CHERRYVIEW(dev) ? | |
971 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64; | |
972 | ||
973 | sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_HIGH(sprite) | | |
974 | (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite))); | |
975 | ||
976 | if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, | |
977 | &drain_latency)) { | |
978 | plane_prec = (prec_mult == high_precision) ? | |
979 | DDL_SPRITE_PRECISION_HIGH(sprite) : | |
980 | DDL_SPRITE_PRECISION_LOW(sprite); | |
981 | sprite_dl |= plane_prec | | |
982 | (drain_latency << DDL_SPRITE_SHIFT(sprite)); | |
983 | } | |
984 | ||
985 | I915_WRITE(VLV_DDL(pipe), sprite_dl); | |
986 | } | |
987 | ||
988 | static void g4x_update_wm(struct drm_crtc *crtc) | |
989 | { | |
990 | struct drm_device *dev = crtc->dev; | |
991 | static const int sr_latency_ns = 12000; | |
992 | struct drm_i915_private *dev_priv = dev->dev_private; | |
993 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
994 | int plane_sr, cursor_sr; | |
995 | unsigned int enabled = 0; | |
996 | bool cxsr_enabled; | |
997 | ||
998 | if (g4x_compute_wm0(dev, PIPE_A, | |
999 | &g4x_wm_info, pessimal_latency_ns, | |
1000 | &g4x_cursor_wm_info, pessimal_latency_ns, | |
1001 | &planea_wm, &cursora_wm)) | |
1002 | enabled |= 1 << PIPE_A; | |
1003 | ||
1004 | if (g4x_compute_wm0(dev, PIPE_B, | |
1005 | &g4x_wm_info, pessimal_latency_ns, | |
1006 | &g4x_cursor_wm_info, pessimal_latency_ns, | |
1007 | &planeb_wm, &cursorb_wm)) | |
1008 | enabled |= 1 << PIPE_B; | |
1009 | ||
1010 | if (single_plane_enabled(enabled) && | |
1011 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1012 | sr_latency_ns, | |
1013 | &g4x_wm_info, | |
1014 | &g4x_cursor_wm_info, | |
1015 | &plane_sr, &cursor_sr)) { | |
1016 | cxsr_enabled = true; | |
1017 | } else { | |
1018 | cxsr_enabled = false; | |
1019 | intel_set_memory_cxsr(dev_priv, false); | |
1020 | plane_sr = cursor_sr = 0; | |
1021 | } | |
1022 | ||
1023 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " | |
1024 | "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", | |
1025 | planea_wm, cursora_wm, | |
1026 | planeb_wm, cursorb_wm, | |
1027 | plane_sr, cursor_sr); | |
1028 | ||
1029 | I915_WRITE(DSPFW1, | |
1030 | (plane_sr << DSPFW_SR_SHIFT) | | |
1031 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
1032 | (planeb_wm << DSPFW_PLANEB_SHIFT) | | |
1033 | (planea_wm << DSPFW_PLANEA_SHIFT)); | |
1034 | I915_WRITE(DSPFW2, | |
1035 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | | |
1036 | (cursora_wm << DSPFW_CURSORA_SHIFT)); | |
1037 | /* HPLL off in SR has some issues on G4x... disable it */ | |
1038 | I915_WRITE(DSPFW3, | |
1039 | (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | | |
1040 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
1041 | ||
1042 | if (cxsr_enabled) | |
1043 | intel_set_memory_cxsr(dev_priv, true); | |
1044 | } | |
1045 | ||
1046 | static void i965_update_wm(struct drm_crtc *unused_crtc) | |
1047 | { | |
1048 | struct drm_device *dev = unused_crtc->dev; | |
1049 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1050 | struct drm_crtc *crtc; | |
1051 | int srwm = 1; | |
1052 | int cursor_sr = 16; | |
1053 | bool cxsr_enabled; | |
1054 | ||
1055 | /* Calc sr entries for one plane configs */ | |
1056 | crtc = single_enabled_crtc(dev); | |
1057 | if (crtc) { | |
1058 | /* self-refresh has much higher latency */ | |
1059 | static const int sr_latency_ns = 12000; | |
1060 | const struct drm_display_mode *adjusted_mode = | |
1061 | &to_intel_crtc(crtc)->config->base.adjusted_mode; | |
1062 | int clock = adjusted_mode->crtc_clock; | |
1063 | int htotal = adjusted_mode->crtc_htotal; | |
1064 | int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; | |
1065 | int pixel_size = crtc->primary->fb->bits_per_pixel / 8; | |
1066 | unsigned long line_time_us; | |
1067 | int entries; | |
1068 | ||
1069 | line_time_us = max(htotal * 1000 / clock, 1); | |
1070 | ||
1071 | /* Use ns/us then divide to preserve precision */ | |
1072 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1073 | pixel_size * hdisplay; | |
1074 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); | |
1075 | srwm = I965_FIFO_SIZE - entries; | |
1076 | if (srwm < 0) | |
1077 | srwm = 1; | |
1078 | srwm &= 0x1ff; | |
1079 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", | |
1080 | entries, srwm); | |
1081 | ||
1082 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1083 | pixel_size * to_intel_crtc(crtc)->cursor_width; | |
1084 | entries = DIV_ROUND_UP(entries, | |
1085 | i965_cursor_wm_info.cacheline_size); | |
1086 | cursor_sr = i965_cursor_wm_info.fifo_size - | |
1087 | (entries + i965_cursor_wm_info.guard_size); | |
1088 | ||
1089 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
1090 | cursor_sr = i965_cursor_wm_info.max_wm; | |
1091 | ||
1092 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
1093 | "cursor %d\n", srwm, cursor_sr); | |
1094 | ||
1095 | cxsr_enabled = true; | |
1096 | } else { | |
1097 | cxsr_enabled = false; | |
1098 | /* Turn off self refresh if both pipes are enabled */ | |
1099 | intel_set_memory_cxsr(dev_priv, false); | |
1100 | } | |
1101 | ||
1102 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", | |
1103 | srwm); | |
1104 | ||
1105 | /* 965 has limitations... */ | |
1106 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | | |
1107 | (8 << DSPFW_CURSORB_SHIFT) | | |
1108 | (8 << DSPFW_PLANEB_SHIFT) | | |
1109 | (8 << DSPFW_PLANEA_SHIFT)); | |
1110 | I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) | | |
1111 | (8 << DSPFW_PLANEC_SHIFT_OLD)); | |
1112 | /* update cursor SR watermark */ | |
1113 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
1114 | ||
1115 | if (cxsr_enabled) | |
1116 | intel_set_memory_cxsr(dev_priv, true); | |
1117 | } | |
1118 | ||
1119 | static void i9xx_update_wm(struct drm_crtc *unused_crtc) | |
1120 | { | |
1121 | struct drm_device *dev = unused_crtc->dev; | |
1122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1123 | const struct intel_watermark_params *wm_info; | |
1124 | uint32_t fwater_lo; | |
1125 | uint32_t fwater_hi; | |
1126 | int cwm, srwm = 1; | |
1127 | int fifo_size; | |
1128 | int planea_wm, planeb_wm; | |
1129 | struct drm_crtc *crtc, *enabled = NULL; | |
1130 | ||
1131 | if (IS_I945GM(dev)) | |
1132 | wm_info = &i945_wm_info; | |
1133 | else if (!IS_GEN2(dev)) | |
1134 | wm_info = &i915_wm_info; | |
1135 | else | |
1136 | wm_info = &i830_a_wm_info; | |
1137 | ||
1138 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); | |
1139 | crtc = intel_get_crtc_for_plane(dev, 0); | |
1140 | if (intel_crtc_active(crtc)) { | |
1141 | const struct drm_display_mode *adjusted_mode; | |
1142 | int cpp = crtc->primary->fb->bits_per_pixel / 8; | |
1143 | if (IS_GEN2(dev)) | |
1144 | cpp = 4; | |
1145 | ||
1146 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; | |
1147 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, | |
1148 | wm_info, fifo_size, cpp, | |
1149 | pessimal_latency_ns); | |
1150 | enabled = crtc; | |
1151 | } else { | |
1152 | planea_wm = fifo_size - wm_info->guard_size; | |
1153 | if (planea_wm > (long)wm_info->max_wm) | |
1154 | planea_wm = wm_info->max_wm; | |
1155 | } | |
1156 | ||
1157 | if (IS_GEN2(dev)) | |
1158 | wm_info = &i830_bc_wm_info; | |
1159 | ||
1160 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); | |
1161 | crtc = intel_get_crtc_for_plane(dev, 1); | |
1162 | if (intel_crtc_active(crtc)) { | |
1163 | const struct drm_display_mode *adjusted_mode; | |
1164 | int cpp = crtc->primary->fb->bits_per_pixel / 8; | |
1165 | if (IS_GEN2(dev)) | |
1166 | cpp = 4; | |
1167 | ||
1168 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; | |
1169 | planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, | |
1170 | wm_info, fifo_size, cpp, | |
1171 | pessimal_latency_ns); | |
1172 | if (enabled == NULL) | |
1173 | enabled = crtc; | |
1174 | else | |
1175 | enabled = NULL; | |
1176 | } else { | |
1177 | planeb_wm = fifo_size - wm_info->guard_size; | |
1178 | if (planeb_wm > (long)wm_info->max_wm) | |
1179 | planeb_wm = wm_info->max_wm; | |
1180 | } | |
1181 | ||
1182 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); | |
1183 | ||
1184 | if (IS_I915GM(dev) && enabled) { | |
1185 | struct drm_i915_gem_object *obj; | |
1186 | ||
1187 | obj = intel_fb_obj(enabled->primary->fb); | |
1188 | ||
1189 | /* self-refresh seems busted with untiled */ | |
1190 | if (obj->tiling_mode == I915_TILING_NONE) | |
1191 | enabled = NULL; | |
1192 | } | |
1193 | ||
1194 | /* | |
1195 | * Overlay gets an aggressive default since video jitter is bad. | |
1196 | */ | |
1197 | cwm = 2; | |
1198 | ||
1199 | /* Play safe and disable self-refresh before adjusting watermarks. */ | |
1200 | intel_set_memory_cxsr(dev_priv, false); | |
1201 | ||
1202 | /* Calc sr entries for one plane configs */ | |
1203 | if (HAS_FW_BLC(dev) && enabled) { | |
1204 | /* self-refresh has much higher latency */ | |
1205 | static const int sr_latency_ns = 6000; | |
1206 | const struct drm_display_mode *adjusted_mode = | |
1207 | &to_intel_crtc(enabled)->config->base.adjusted_mode; | |
1208 | int clock = adjusted_mode->crtc_clock; | |
1209 | int htotal = adjusted_mode->crtc_htotal; | |
1210 | int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w; | |
1211 | int pixel_size = enabled->primary->fb->bits_per_pixel / 8; | |
1212 | unsigned long line_time_us; | |
1213 | int entries; | |
1214 | ||
1215 | line_time_us = max(htotal * 1000 / clock, 1); | |
1216 | ||
1217 | /* Use ns/us then divide to preserve precision */ | |
1218 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1219 | pixel_size * hdisplay; | |
1220 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); | |
1221 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); | |
1222 | srwm = wm_info->fifo_size - entries; | |
1223 | if (srwm < 0) | |
1224 | srwm = 1; | |
1225 | ||
1226 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
1227 | I915_WRITE(FW_BLC_SELF, | |
1228 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
1229 | else if (IS_I915GM(dev)) | |
1230 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); | |
1231 | } | |
1232 | ||
1233 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", | |
1234 | planea_wm, planeb_wm, cwm, srwm); | |
1235 | ||
1236 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); | |
1237 | fwater_hi = (cwm & 0x1f); | |
1238 | ||
1239 | /* Set request length to 8 cachelines per fetch */ | |
1240 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
1241 | fwater_hi = fwater_hi | (1 << 8); | |
1242 | ||
1243 | I915_WRITE(FW_BLC, fwater_lo); | |
1244 | I915_WRITE(FW_BLC2, fwater_hi); | |
1245 | ||
1246 | if (enabled) | |
1247 | intel_set_memory_cxsr(dev_priv, true); | |
1248 | } | |
1249 | ||
1250 | static void i845_update_wm(struct drm_crtc *unused_crtc) | |
1251 | { | |
1252 | struct drm_device *dev = unused_crtc->dev; | |
1253 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1254 | struct drm_crtc *crtc; | |
1255 | const struct drm_display_mode *adjusted_mode; | |
1256 | uint32_t fwater_lo; | |
1257 | int planea_wm; | |
1258 | ||
1259 | crtc = single_enabled_crtc(dev); | |
1260 | if (crtc == NULL) | |
1261 | return; | |
1262 | ||
1263 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; | |
1264 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, | |
1265 | &i845_wm_info, | |
1266 | dev_priv->display.get_fifo_size(dev, 0), | |
1267 | 4, pessimal_latency_ns); | |
1268 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; | |
1269 | fwater_lo |= (3<<8) | planea_wm; | |
1270 | ||
1271 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); | |
1272 | ||
1273 | I915_WRITE(FW_BLC, fwater_lo); | |
1274 | } | |
1275 | ||
1276 | static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev, | |
1277 | struct drm_crtc *crtc) | |
1278 | { | |
1279 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1280 | uint32_t pixel_rate; | |
1281 | ||
1282 | pixel_rate = intel_crtc->config->base.adjusted_mode.crtc_clock; | |
1283 | ||
1284 | /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to | |
1285 | * adjust the pixel_rate here. */ | |
1286 | ||
1287 | if (intel_crtc->config->pch_pfit.enabled) { | |
1288 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; | |
1289 | uint32_t pfit_size = intel_crtc->config->pch_pfit.size; | |
1290 | ||
1291 | pipe_w = intel_crtc->config->pipe_src_w; | |
1292 | pipe_h = intel_crtc->config->pipe_src_h; | |
1293 | pfit_w = (pfit_size >> 16) & 0xFFFF; | |
1294 | pfit_h = pfit_size & 0xFFFF; | |
1295 | if (pipe_w < pfit_w) | |
1296 | pipe_w = pfit_w; | |
1297 | if (pipe_h < pfit_h) | |
1298 | pipe_h = pfit_h; | |
1299 | ||
1300 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, | |
1301 | pfit_w * pfit_h); | |
1302 | } | |
1303 | ||
1304 | return pixel_rate; | |
1305 | } | |
1306 | ||
1307 | /* latency must be in 0.1us units. */ | |
1308 | static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, | |
1309 | uint32_t latency) | |
1310 | { | |
1311 | uint64_t ret; | |
1312 | ||
1313 | if (WARN(latency == 0, "Latency value missing\n")) | |
1314 | return UINT_MAX; | |
1315 | ||
1316 | ret = (uint64_t) pixel_rate * bytes_per_pixel * latency; | |
1317 | ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; | |
1318 | ||
1319 | return ret; | |
1320 | } | |
1321 | ||
1322 | /* latency must be in 0.1us units. */ | |
1323 | static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, | |
1324 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, | |
1325 | uint32_t latency) | |
1326 | { | |
1327 | uint32_t ret; | |
1328 | ||
1329 | if (WARN(latency == 0, "Latency value missing\n")) | |
1330 | return UINT_MAX; | |
1331 | ||
1332 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); | |
1333 | ret = (ret + 1) * horiz_pixels * bytes_per_pixel; | |
1334 | ret = DIV_ROUND_UP(ret, 64) + 2; | |
1335 | return ret; | |
1336 | } | |
1337 | ||
1338 | static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, | |
1339 | uint8_t bytes_per_pixel) | |
1340 | { | |
1341 | return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2; | |
1342 | } | |
1343 | ||
1344 | struct skl_pipe_wm_parameters { | |
1345 | bool active; | |
1346 | uint32_t pipe_htotal; | |
1347 | uint32_t pixel_rate; /* in KHz */ | |
1348 | struct intel_plane_wm_parameters plane[I915_MAX_PLANES]; | |
1349 | struct intel_plane_wm_parameters cursor; | |
1350 | }; | |
1351 | ||
1352 | struct ilk_pipe_wm_parameters { | |
1353 | bool active; | |
1354 | uint32_t pipe_htotal; | |
1355 | uint32_t pixel_rate; | |
1356 | struct intel_plane_wm_parameters pri; | |
1357 | struct intel_plane_wm_parameters spr; | |
1358 | struct intel_plane_wm_parameters cur; | |
1359 | }; | |
1360 | ||
1361 | struct ilk_wm_maximums { | |
1362 | uint16_t pri; | |
1363 | uint16_t spr; | |
1364 | uint16_t cur; | |
1365 | uint16_t fbc; | |
1366 | }; | |
1367 | ||
1368 | /* used in computing the new watermarks state */ | |
1369 | struct intel_wm_config { | |
1370 | unsigned int num_pipes_active; | |
1371 | bool sprites_enabled; | |
1372 | bool sprites_scaled; | |
1373 | }; | |
1374 | ||
1375 | /* | |
1376 | * For both WM_PIPE and WM_LP. | |
1377 | * mem_value must be in 0.1us units. | |
1378 | */ | |
1379 | static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params, | |
1380 | uint32_t mem_value, | |
1381 | bool is_lp) | |
1382 | { | |
1383 | uint32_t method1, method2; | |
1384 | ||
1385 | if (!params->active || !params->pri.enabled) | |
1386 | return 0; | |
1387 | ||
1388 | method1 = ilk_wm_method1(params->pixel_rate, | |
1389 | params->pri.bytes_per_pixel, | |
1390 | mem_value); | |
1391 | ||
1392 | if (!is_lp) | |
1393 | return method1; | |
1394 | ||
1395 | method2 = ilk_wm_method2(params->pixel_rate, | |
1396 | params->pipe_htotal, | |
1397 | params->pri.horiz_pixels, | |
1398 | params->pri.bytes_per_pixel, | |
1399 | mem_value); | |
1400 | ||
1401 | return min(method1, method2); | |
1402 | } | |
1403 | ||
1404 | /* | |
1405 | * For both WM_PIPE and WM_LP. | |
1406 | * mem_value must be in 0.1us units. | |
1407 | */ | |
1408 | static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params, | |
1409 | uint32_t mem_value) | |
1410 | { | |
1411 | uint32_t method1, method2; | |
1412 | ||
1413 | if (!params->active || !params->spr.enabled) | |
1414 | return 0; | |
1415 | ||
1416 | method1 = ilk_wm_method1(params->pixel_rate, | |
1417 | params->spr.bytes_per_pixel, | |
1418 | mem_value); | |
1419 | method2 = ilk_wm_method2(params->pixel_rate, | |
1420 | params->pipe_htotal, | |
1421 | params->spr.horiz_pixels, | |
1422 | params->spr.bytes_per_pixel, | |
1423 | mem_value); | |
1424 | return min(method1, method2); | |
1425 | } | |
1426 | ||
1427 | /* | |
1428 | * For both WM_PIPE and WM_LP. | |
1429 | * mem_value must be in 0.1us units. | |
1430 | */ | |
1431 | static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params, | |
1432 | uint32_t mem_value) | |
1433 | { | |
1434 | if (!params->active || !params->cur.enabled) | |
1435 | return 0; | |
1436 | ||
1437 | return ilk_wm_method2(params->pixel_rate, | |
1438 | params->pipe_htotal, | |
1439 | params->cur.horiz_pixels, | |
1440 | params->cur.bytes_per_pixel, | |
1441 | mem_value); | |
1442 | } | |
1443 | ||
1444 | /* Only for WM_LP. */ | |
1445 | static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params, | |
1446 | uint32_t pri_val) | |
1447 | { | |
1448 | if (!params->active || !params->pri.enabled) | |
1449 | return 0; | |
1450 | ||
1451 | return ilk_wm_fbc(pri_val, | |
1452 | params->pri.horiz_pixels, | |
1453 | params->pri.bytes_per_pixel); | |
1454 | } | |
1455 | ||
1456 | static unsigned int ilk_display_fifo_size(const struct drm_device *dev) | |
1457 | { | |
1458 | if (INTEL_INFO(dev)->gen >= 8) | |
1459 | return 3072; | |
1460 | else if (INTEL_INFO(dev)->gen >= 7) | |
1461 | return 768; | |
1462 | else | |
1463 | return 512; | |
1464 | } | |
1465 | ||
1466 | static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev, | |
1467 | int level, bool is_sprite) | |
1468 | { | |
1469 | if (INTEL_INFO(dev)->gen >= 8) | |
1470 | /* BDW primary/sprite plane watermarks */ | |
1471 | return level == 0 ? 255 : 2047; | |
1472 | else if (INTEL_INFO(dev)->gen >= 7) | |
1473 | /* IVB/HSW primary/sprite plane watermarks */ | |
1474 | return level == 0 ? 127 : 1023; | |
1475 | else if (!is_sprite) | |
1476 | /* ILK/SNB primary plane watermarks */ | |
1477 | return level == 0 ? 127 : 511; | |
1478 | else | |
1479 | /* ILK/SNB sprite plane watermarks */ | |
1480 | return level == 0 ? 63 : 255; | |
1481 | } | |
1482 | ||
1483 | static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev, | |
1484 | int level) | |
1485 | { | |
1486 | if (INTEL_INFO(dev)->gen >= 7) | |
1487 | return level == 0 ? 63 : 255; | |
1488 | else | |
1489 | return level == 0 ? 31 : 63; | |
1490 | } | |
1491 | ||
1492 | static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev) | |
1493 | { | |
1494 | if (INTEL_INFO(dev)->gen >= 8) | |
1495 | return 31; | |
1496 | else | |
1497 | return 15; | |
1498 | } | |
1499 | ||
1500 | /* Calculate the maximum primary/sprite plane watermark */ | |
1501 | static unsigned int ilk_plane_wm_max(const struct drm_device *dev, | |
1502 | int level, | |
1503 | const struct intel_wm_config *config, | |
1504 | enum intel_ddb_partitioning ddb_partitioning, | |
1505 | bool is_sprite) | |
1506 | { | |
1507 | unsigned int fifo_size = ilk_display_fifo_size(dev); | |
1508 | ||
1509 | /* if sprites aren't enabled, sprites get nothing */ | |
1510 | if (is_sprite && !config->sprites_enabled) | |
1511 | return 0; | |
1512 | ||
1513 | /* HSW allows LP1+ watermarks even with multiple pipes */ | |
1514 | if (level == 0 || config->num_pipes_active > 1) { | |
1515 | fifo_size /= INTEL_INFO(dev)->num_pipes; | |
1516 | ||
1517 | /* | |
1518 | * For some reason the non self refresh | |
1519 | * FIFO size is only half of the self | |
1520 | * refresh FIFO size on ILK/SNB. | |
1521 | */ | |
1522 | if (INTEL_INFO(dev)->gen <= 6) | |
1523 | fifo_size /= 2; | |
1524 | } | |
1525 | ||
1526 | if (config->sprites_enabled) { | |
1527 | /* level 0 is always calculated with 1:1 split */ | |
1528 | if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { | |
1529 | if (is_sprite) | |
1530 | fifo_size *= 5; | |
1531 | fifo_size /= 6; | |
1532 | } else { | |
1533 | fifo_size /= 2; | |
1534 | } | |
1535 | } | |
1536 | ||
1537 | /* clamp to max that the registers can hold */ | |
1538 | return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite)); | |
1539 | } | |
1540 | ||
1541 | /* Calculate the maximum cursor plane watermark */ | |
1542 | static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, | |
1543 | int level, | |
1544 | const struct intel_wm_config *config) | |
1545 | { | |
1546 | /* HSW LP1+ watermarks w/ multiple pipes */ | |
1547 | if (level > 0 && config->num_pipes_active > 1) | |
1548 | return 64; | |
1549 | ||
1550 | /* otherwise just report max that registers can hold */ | |
1551 | return ilk_cursor_wm_reg_max(dev, level); | |
1552 | } | |
1553 | ||
1554 | static void ilk_compute_wm_maximums(const struct drm_device *dev, | |
1555 | int level, | |
1556 | const struct intel_wm_config *config, | |
1557 | enum intel_ddb_partitioning ddb_partitioning, | |
1558 | struct ilk_wm_maximums *max) | |
1559 | { | |
1560 | max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); | |
1561 | max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); | |
1562 | max->cur = ilk_cursor_wm_max(dev, level, config); | |
1563 | max->fbc = ilk_fbc_wm_reg_max(dev); | |
1564 | } | |
1565 | ||
1566 | static void ilk_compute_wm_reg_maximums(struct drm_device *dev, | |
1567 | int level, | |
1568 | struct ilk_wm_maximums *max) | |
1569 | { | |
1570 | max->pri = ilk_plane_wm_reg_max(dev, level, false); | |
1571 | max->spr = ilk_plane_wm_reg_max(dev, level, true); | |
1572 | max->cur = ilk_cursor_wm_reg_max(dev, level); | |
1573 | max->fbc = ilk_fbc_wm_reg_max(dev); | |
1574 | } | |
1575 | ||
1576 | static bool ilk_validate_wm_level(int level, | |
1577 | const struct ilk_wm_maximums *max, | |
1578 | struct intel_wm_level *result) | |
1579 | { | |
1580 | bool ret; | |
1581 | ||
1582 | /* already determined to be invalid? */ | |
1583 | if (!result->enable) | |
1584 | return false; | |
1585 | ||
1586 | result->enable = result->pri_val <= max->pri && | |
1587 | result->spr_val <= max->spr && | |
1588 | result->cur_val <= max->cur; | |
1589 | ||
1590 | ret = result->enable; | |
1591 | ||
1592 | /* | |
1593 | * HACK until we can pre-compute everything, | |
1594 | * and thus fail gracefully if LP0 watermarks | |
1595 | * are exceeded... | |
1596 | */ | |
1597 | if (level == 0 && !result->enable) { | |
1598 | if (result->pri_val > max->pri) | |
1599 | DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", | |
1600 | level, result->pri_val, max->pri); | |
1601 | if (result->spr_val > max->spr) | |
1602 | DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", | |
1603 | level, result->spr_val, max->spr); | |
1604 | if (result->cur_val > max->cur) | |
1605 | DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", | |
1606 | level, result->cur_val, max->cur); | |
1607 | ||
1608 | result->pri_val = min_t(uint32_t, result->pri_val, max->pri); | |
1609 | result->spr_val = min_t(uint32_t, result->spr_val, max->spr); | |
1610 | result->cur_val = min_t(uint32_t, result->cur_val, max->cur); | |
1611 | result->enable = true; | |
1612 | } | |
1613 | ||
1614 | return ret; | |
1615 | } | |
1616 | ||
1617 | static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, | |
1618 | int level, | |
1619 | const struct ilk_pipe_wm_parameters *p, | |
1620 | struct intel_wm_level *result) | |
1621 | { | |
1622 | uint16_t pri_latency = dev_priv->wm.pri_latency[level]; | |
1623 | uint16_t spr_latency = dev_priv->wm.spr_latency[level]; | |
1624 | uint16_t cur_latency = dev_priv->wm.cur_latency[level]; | |
1625 | ||
1626 | /* WM1+ latency values stored in 0.5us units */ | |
1627 | if (level > 0) { | |
1628 | pri_latency *= 5; | |
1629 | spr_latency *= 5; | |
1630 | cur_latency *= 5; | |
1631 | } | |
1632 | ||
1633 | result->pri_val = ilk_compute_pri_wm(p, pri_latency, level); | |
1634 | result->spr_val = ilk_compute_spr_wm(p, spr_latency); | |
1635 | result->cur_val = ilk_compute_cur_wm(p, cur_latency); | |
1636 | result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val); | |
1637 | result->enable = true; | |
1638 | } | |
1639 | ||
1640 | static uint32_t | |
1641 | hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) | |
1642 | { | |
1643 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1644 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1645 | struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode; | |
1646 | u32 linetime, ips_linetime; | |
1647 | ||
1648 | if (!intel_crtc_active(crtc)) | |
1649 | return 0; | |
1650 | ||
1651 | /* The WM are computed with base on how long it takes to fill a single | |
1652 | * row at the given clock rate, multiplied by 8. | |
1653 | * */ | |
1654 | linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, | |
1655 | mode->crtc_clock); | |
1656 | ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, | |
1657 | intel_ddi_get_cdclk_freq(dev_priv)); | |
1658 | ||
1659 | return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | | |
1660 | PIPE_WM_LINETIME_TIME(linetime); | |
1661 | } | |
1662 | ||
1663 | static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8]) | |
1664 | { | |
1665 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1666 | ||
1667 | if (IS_GEN9(dev)) { | |
1668 | uint32_t val; | |
1669 | int ret, i; | |
1670 | int level, max_level = ilk_wm_max_level(dev); | |
1671 | ||
1672 | /* read the first set of memory latencies[0:3] */ | |
1673 | val = 0; /* data0 to be programmed to 0 for first set */ | |
1674 | mutex_lock(&dev_priv->rps.hw_lock); | |
1675 | ret = sandybridge_pcode_read(dev_priv, | |
1676 | GEN9_PCODE_READ_MEM_LATENCY, | |
1677 | &val); | |
1678 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1679 | ||
1680 | if (ret) { | |
1681 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); | |
1682 | return; | |
1683 | } | |
1684 | ||
1685 | wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; | |
1686 | wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & | |
1687 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
1688 | wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & | |
1689 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
1690 | wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & | |
1691 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
1692 | ||
1693 | /* read the second set of memory latencies[4:7] */ | |
1694 | val = 1; /* data0 to be programmed to 1 for second set */ | |
1695 | mutex_lock(&dev_priv->rps.hw_lock); | |
1696 | ret = sandybridge_pcode_read(dev_priv, | |
1697 | GEN9_PCODE_READ_MEM_LATENCY, | |
1698 | &val); | |
1699 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1700 | if (ret) { | |
1701 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); | |
1702 | return; | |
1703 | } | |
1704 | ||
1705 | wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; | |
1706 | wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & | |
1707 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
1708 | wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & | |
1709 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
1710 | wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & | |
1711 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
1712 | ||
1713 | /* | |
1714 | * punit doesn't take into account the read latency so we need | |
1715 | * to add 2us to the various latency levels we retrieve from | |
1716 | * the punit. | |
1717 | * - W0 is a bit special in that it's the only level that | |
1718 | * can't be disabled if we want to have display working, so | |
1719 | * we always add 2us there. | |
1720 | * - For levels >=1, punit returns 0us latency when they are | |
1721 | * disabled, so we respect that and don't add 2us then | |
1722 | * | |
1723 | * Additionally, if a level n (n > 1) has a 0us latency, all | |
1724 | * levels m (m >= n) need to be disabled. We make sure to | |
1725 | * sanitize the values out of the punit to satisfy this | |
1726 | * requirement. | |
1727 | */ | |
1728 | wm[0] += 2; | |
1729 | for (level = 1; level <= max_level; level++) | |
1730 | if (wm[level] != 0) | |
1731 | wm[level] += 2; | |
1732 | else { | |
1733 | for (i = level + 1; i <= max_level; i++) | |
1734 | wm[i] = 0; | |
1735 | ||
1736 | break; | |
1737 | } | |
1738 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
1739 | uint64_t sskpd = I915_READ64(MCH_SSKPD); | |
1740 | ||
1741 | wm[0] = (sskpd >> 56) & 0xFF; | |
1742 | if (wm[0] == 0) | |
1743 | wm[0] = sskpd & 0xF; | |
1744 | wm[1] = (sskpd >> 4) & 0xFF; | |
1745 | wm[2] = (sskpd >> 12) & 0xFF; | |
1746 | wm[3] = (sskpd >> 20) & 0x1FF; | |
1747 | wm[4] = (sskpd >> 32) & 0x1FF; | |
1748 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
1749 | uint32_t sskpd = I915_READ(MCH_SSKPD); | |
1750 | ||
1751 | wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; | |
1752 | wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; | |
1753 | wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; | |
1754 | wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; | |
1755 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1756 | uint32_t mltr = I915_READ(MLTR_ILK); | |
1757 | ||
1758 | /* ILK primary LP0 latency is 700 ns */ | |
1759 | wm[0] = 7; | |
1760 | wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; | |
1761 | wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; | |
1762 | } | |
1763 | } | |
1764 | ||
1765 | static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5]) | |
1766 | { | |
1767 | /* ILK sprite LP0 latency is 1300 ns */ | |
1768 | if (INTEL_INFO(dev)->gen == 5) | |
1769 | wm[0] = 13; | |
1770 | } | |
1771 | ||
1772 | static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) | |
1773 | { | |
1774 | /* ILK cursor LP0 latency is 1300 ns */ | |
1775 | if (INTEL_INFO(dev)->gen == 5) | |
1776 | wm[0] = 13; | |
1777 | ||
1778 | /* WaDoubleCursorLP3Latency:ivb */ | |
1779 | if (IS_IVYBRIDGE(dev)) | |
1780 | wm[3] *= 2; | |
1781 | } | |
1782 | ||
1783 | int ilk_wm_max_level(const struct drm_device *dev) | |
1784 | { | |
1785 | /* how many WM levels are we expecting */ | |
1786 | if (IS_GEN9(dev)) | |
1787 | return 7; | |
1788 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
1789 | return 4; | |
1790 | else if (INTEL_INFO(dev)->gen >= 6) | |
1791 | return 3; | |
1792 | else | |
1793 | return 2; | |
1794 | } | |
1795 | ||
1796 | static void intel_print_wm_latency(struct drm_device *dev, | |
1797 | const char *name, | |
1798 | const uint16_t wm[8]) | |
1799 | { | |
1800 | int level, max_level = ilk_wm_max_level(dev); | |
1801 | ||
1802 | for (level = 0; level <= max_level; level++) { | |
1803 | unsigned int latency = wm[level]; | |
1804 | ||
1805 | if (latency == 0) { | |
1806 | DRM_ERROR("%s WM%d latency not provided\n", | |
1807 | name, level); | |
1808 | continue; | |
1809 | } | |
1810 | ||
1811 | /* | |
1812 | * - latencies are in us on gen9. | |
1813 | * - before then, WM1+ latency values are in 0.5us units | |
1814 | */ | |
1815 | if (IS_GEN9(dev)) | |
1816 | latency *= 10; | |
1817 | else if (level > 0) | |
1818 | latency *= 5; | |
1819 | ||
1820 | DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", | |
1821 | name, level, wm[level], | |
1822 | latency / 10, latency % 10); | |
1823 | } | |
1824 | } | |
1825 | ||
1826 | static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, | |
1827 | uint16_t wm[5], uint16_t min) | |
1828 | { | |
1829 | int level, max_level = ilk_wm_max_level(dev_priv->dev); | |
1830 | ||
1831 | if (wm[0] >= min) | |
1832 | return false; | |
1833 | ||
1834 | wm[0] = max(wm[0], min); | |
1835 | for (level = 1; level <= max_level; level++) | |
1836 | wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); | |
1837 | ||
1838 | return true; | |
1839 | } | |
1840 | ||
1841 | static void snb_wm_latency_quirk(struct drm_device *dev) | |
1842 | { | |
1843 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1844 | bool changed; | |
1845 | ||
1846 | /* | |
1847 | * The BIOS provided WM memory latency values are often | |
1848 | * inadequate for high resolution displays. Adjust them. | |
1849 | */ | |
1850 | changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | | |
1851 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | | |
1852 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); | |
1853 | ||
1854 | if (!changed) | |
1855 | return; | |
1856 | ||
1857 | DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); | |
1858 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); | |
1859 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); | |
1860 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); | |
1861 | } | |
1862 | ||
1863 | static void ilk_setup_wm_latency(struct drm_device *dev) | |
1864 | { | |
1865 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1866 | ||
1867 | intel_read_wm_latency(dev, dev_priv->wm.pri_latency); | |
1868 | ||
1869 | memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, | |
1870 | sizeof(dev_priv->wm.pri_latency)); | |
1871 | memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, | |
1872 | sizeof(dev_priv->wm.pri_latency)); | |
1873 | ||
1874 | intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); | |
1875 | intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency); | |
1876 | ||
1877 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); | |
1878 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); | |
1879 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); | |
1880 | ||
1881 | if (IS_GEN6(dev)) | |
1882 | snb_wm_latency_quirk(dev); | |
1883 | } | |
1884 | ||
1885 | static void skl_setup_wm_latency(struct drm_device *dev) | |
1886 | { | |
1887 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1888 | ||
1889 | intel_read_wm_latency(dev, dev_priv->wm.skl_latency); | |
1890 | intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency); | |
1891 | } | |
1892 | ||
1893 | static void ilk_compute_wm_parameters(struct drm_crtc *crtc, | |
1894 | struct ilk_pipe_wm_parameters *p) | |
1895 | { | |
1896 | struct drm_device *dev = crtc->dev; | |
1897 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1898 | enum pipe pipe = intel_crtc->pipe; | |
1899 | struct drm_plane *plane; | |
1900 | ||
1901 | if (!intel_crtc_active(crtc)) | |
1902 | return; | |
1903 | ||
1904 | p->active = true; | |
1905 | p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal; | |
1906 | p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc); | |
1907 | p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8; | |
1908 | p->cur.bytes_per_pixel = 4; | |
1909 | p->pri.horiz_pixels = intel_crtc->config->pipe_src_w; | |
1910 | p->cur.horiz_pixels = intel_crtc->cursor_width; | |
1911 | /* TODO: for now, assume primary and cursor planes are always enabled. */ | |
1912 | p->pri.enabled = true; | |
1913 | p->cur.enabled = true; | |
1914 | ||
1915 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { | |
1916 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
1917 | ||
1918 | if (intel_plane->pipe == pipe) { | |
1919 | p->spr = intel_plane->wm; | |
1920 | break; | |
1921 | } | |
1922 | } | |
1923 | } | |
1924 | ||
1925 | static void ilk_compute_wm_config(struct drm_device *dev, | |
1926 | struct intel_wm_config *config) | |
1927 | { | |
1928 | struct intel_crtc *intel_crtc; | |
1929 | ||
1930 | /* Compute the currently _active_ config */ | |
1931 | for_each_intel_crtc(dev, intel_crtc) { | |
1932 | const struct intel_pipe_wm *wm = &intel_crtc->wm.active; | |
1933 | ||
1934 | if (!wm->pipe_enabled) | |
1935 | continue; | |
1936 | ||
1937 | config->sprites_enabled |= wm->sprites_enabled; | |
1938 | config->sprites_scaled |= wm->sprites_scaled; | |
1939 | config->num_pipes_active++; | |
1940 | } | |
1941 | } | |
1942 | ||
1943 | /* Compute new watermarks for the pipe */ | |
1944 | static bool intel_compute_pipe_wm(struct drm_crtc *crtc, | |
1945 | const struct ilk_pipe_wm_parameters *params, | |
1946 | struct intel_pipe_wm *pipe_wm) | |
1947 | { | |
1948 | struct drm_device *dev = crtc->dev; | |
1949 | const struct drm_i915_private *dev_priv = dev->dev_private; | |
1950 | int level, max_level = ilk_wm_max_level(dev); | |
1951 | /* LP0 watermark maximums depend on this pipe alone */ | |
1952 | struct intel_wm_config config = { | |
1953 | .num_pipes_active = 1, | |
1954 | .sprites_enabled = params->spr.enabled, | |
1955 | .sprites_scaled = params->spr.scaled, | |
1956 | }; | |
1957 | struct ilk_wm_maximums max; | |
1958 | ||
1959 | pipe_wm->pipe_enabled = params->active; | |
1960 | pipe_wm->sprites_enabled = params->spr.enabled; | |
1961 | pipe_wm->sprites_scaled = params->spr.scaled; | |
1962 | ||
1963 | /* ILK/SNB: LP2+ watermarks only w/o sprites */ | |
1964 | if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled) | |
1965 | max_level = 1; | |
1966 | ||
1967 | /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ | |
1968 | if (params->spr.scaled) | |
1969 | max_level = 0; | |
1970 | ||
1971 | ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]); | |
1972 | ||
1973 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
1974 | pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc); | |
1975 | ||
1976 | /* LP0 watermarks always use 1/2 DDB partitioning */ | |
1977 | ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); | |
1978 | ||
1979 | /* At least LP0 must be valid */ | |
1980 | if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) | |
1981 | return false; | |
1982 | ||
1983 | ilk_compute_wm_reg_maximums(dev, 1, &max); | |
1984 | ||
1985 | for (level = 1; level <= max_level; level++) { | |
1986 | struct intel_wm_level wm = {}; | |
1987 | ||
1988 | ilk_compute_wm_level(dev_priv, level, params, &wm); | |
1989 | ||
1990 | /* | |
1991 | * Disable any watermark level that exceeds the | |
1992 | * register maximums since such watermarks are | |
1993 | * always invalid. | |
1994 | */ | |
1995 | if (!ilk_validate_wm_level(level, &max, &wm)) | |
1996 | break; | |
1997 | ||
1998 | pipe_wm->wm[level] = wm; | |
1999 | } | |
2000 | ||
2001 | return true; | |
2002 | } | |
2003 | ||
2004 | /* | |
2005 | * Merge the watermarks from all active pipes for a specific level. | |
2006 | */ | |
2007 | static void ilk_merge_wm_level(struct drm_device *dev, | |
2008 | int level, | |
2009 | struct intel_wm_level *ret_wm) | |
2010 | { | |
2011 | const struct intel_crtc *intel_crtc; | |
2012 | ||
2013 | ret_wm->enable = true; | |
2014 | ||
2015 | for_each_intel_crtc(dev, intel_crtc) { | |
2016 | const struct intel_pipe_wm *active = &intel_crtc->wm.active; | |
2017 | const struct intel_wm_level *wm = &active->wm[level]; | |
2018 | ||
2019 | if (!active->pipe_enabled) | |
2020 | continue; | |
2021 | ||
2022 | /* | |
2023 | * The watermark values may have been used in the past, | |
2024 | * so we must maintain them in the registers for some | |
2025 | * time even if the level is now disabled. | |
2026 | */ | |
2027 | if (!wm->enable) | |
2028 | ret_wm->enable = false; | |
2029 | ||
2030 | ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); | |
2031 | ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); | |
2032 | ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); | |
2033 | ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); | |
2034 | } | |
2035 | } | |
2036 | ||
2037 | /* | |
2038 | * Merge all low power watermarks for all active pipes. | |
2039 | */ | |
2040 | static void ilk_wm_merge(struct drm_device *dev, | |
2041 | const struct intel_wm_config *config, | |
2042 | const struct ilk_wm_maximums *max, | |
2043 | struct intel_pipe_wm *merged) | |
2044 | { | |
2045 | int level, max_level = ilk_wm_max_level(dev); | |
2046 | int last_enabled_level = max_level; | |
2047 | ||
2048 | /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ | |
2049 | if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && | |
2050 | config->num_pipes_active > 1) | |
2051 | return; | |
2052 | ||
2053 | /* ILK: FBC WM must be disabled always */ | |
2054 | merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; | |
2055 | ||
2056 | /* merge each WM1+ level */ | |
2057 | for (level = 1; level <= max_level; level++) { | |
2058 | struct intel_wm_level *wm = &merged->wm[level]; | |
2059 | ||
2060 | ilk_merge_wm_level(dev, level, wm); | |
2061 | ||
2062 | if (level > last_enabled_level) | |
2063 | wm->enable = false; | |
2064 | else if (!ilk_validate_wm_level(level, max, wm)) | |
2065 | /* make sure all following levels get disabled */ | |
2066 | last_enabled_level = level - 1; | |
2067 | ||
2068 | /* | |
2069 | * The spec says it is preferred to disable | |
2070 | * FBC WMs instead of disabling a WM level. | |
2071 | */ | |
2072 | if (wm->fbc_val > max->fbc) { | |
2073 | if (wm->enable) | |
2074 | merged->fbc_wm_enabled = false; | |
2075 | wm->fbc_val = 0; | |
2076 | } | |
2077 | } | |
2078 | ||
2079 | /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ | |
2080 | /* | |
2081 | * FIXME this is racy. FBC might get enabled later. | |
2082 | * What we should check here is whether FBC can be | |
2083 | * enabled sometime later. | |
2084 | */ | |
2085 | if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) { | |
2086 | for (level = 2; level <= max_level; level++) { | |
2087 | struct intel_wm_level *wm = &merged->wm[level]; | |
2088 | ||
2089 | wm->enable = false; | |
2090 | } | |
2091 | } | |
2092 | } | |
2093 | ||
2094 | static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) | |
2095 | { | |
2096 | /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ | |
2097 | return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); | |
2098 | } | |
2099 | ||
2100 | /* The value we need to program into the WM_LPx latency field */ | |
2101 | static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) | |
2102 | { | |
2103 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2104 | ||
2105 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2106 | return 2 * level; | |
2107 | else | |
2108 | return dev_priv->wm.pri_latency[level]; | |
2109 | } | |
2110 | ||
2111 | static void ilk_compute_wm_results(struct drm_device *dev, | |
2112 | const struct intel_pipe_wm *merged, | |
2113 | enum intel_ddb_partitioning partitioning, | |
2114 | struct ilk_wm_values *results) | |
2115 | { | |
2116 | struct intel_crtc *intel_crtc; | |
2117 | int level, wm_lp; | |
2118 | ||
2119 | results->enable_fbc_wm = merged->fbc_wm_enabled; | |
2120 | results->partitioning = partitioning; | |
2121 | ||
2122 | /* LP1+ register values */ | |
2123 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { | |
2124 | const struct intel_wm_level *r; | |
2125 | ||
2126 | level = ilk_wm_lp_to_level(wm_lp, merged); | |
2127 | ||
2128 | r = &merged->wm[level]; | |
2129 | ||
2130 | /* | |
2131 | * Maintain the watermark values even if the level is | |
2132 | * disabled. Doing otherwise could cause underruns. | |
2133 | */ | |
2134 | results->wm_lp[wm_lp - 1] = | |
2135 | (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | | |
2136 | (r->pri_val << WM1_LP_SR_SHIFT) | | |
2137 | r->cur_val; | |
2138 | ||
2139 | if (r->enable) | |
2140 | results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; | |
2141 | ||
2142 | if (INTEL_INFO(dev)->gen >= 8) | |
2143 | results->wm_lp[wm_lp - 1] |= | |
2144 | r->fbc_val << WM1_LP_FBC_SHIFT_BDW; | |
2145 | else | |
2146 | results->wm_lp[wm_lp - 1] |= | |
2147 | r->fbc_val << WM1_LP_FBC_SHIFT; | |
2148 | ||
2149 | /* | |
2150 | * Always set WM1S_LP_EN when spr_val != 0, even if the | |
2151 | * level is disabled. Doing otherwise could cause underruns. | |
2152 | */ | |
2153 | if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) { | |
2154 | WARN_ON(wm_lp != 1); | |
2155 | results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; | |
2156 | } else | |
2157 | results->wm_lp_spr[wm_lp - 1] = r->spr_val; | |
2158 | } | |
2159 | ||
2160 | /* LP0 register values */ | |
2161 | for_each_intel_crtc(dev, intel_crtc) { | |
2162 | enum pipe pipe = intel_crtc->pipe; | |
2163 | const struct intel_wm_level *r = | |
2164 | &intel_crtc->wm.active.wm[0]; | |
2165 | ||
2166 | if (WARN_ON(!r->enable)) | |
2167 | continue; | |
2168 | ||
2169 | results->wm_linetime[pipe] = intel_crtc->wm.active.linetime; | |
2170 | ||
2171 | results->wm_pipe[pipe] = | |
2172 | (r->pri_val << WM0_PIPE_PLANE_SHIFT) | | |
2173 | (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | | |
2174 | r->cur_val; | |
2175 | } | |
2176 | } | |
2177 | ||
2178 | /* Find the result with the highest level enabled. Check for enable_fbc_wm in | |
2179 | * case both are at the same level. Prefer r1 in case they're the same. */ | |
2180 | static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, | |
2181 | struct intel_pipe_wm *r1, | |
2182 | struct intel_pipe_wm *r2) | |
2183 | { | |
2184 | int level, max_level = ilk_wm_max_level(dev); | |
2185 | int level1 = 0, level2 = 0; | |
2186 | ||
2187 | for (level = 1; level <= max_level; level++) { | |
2188 | if (r1->wm[level].enable) | |
2189 | level1 = level; | |
2190 | if (r2->wm[level].enable) | |
2191 | level2 = level; | |
2192 | } | |
2193 | ||
2194 | if (level1 == level2) { | |
2195 | if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) | |
2196 | return r2; | |
2197 | else | |
2198 | return r1; | |
2199 | } else if (level1 > level2) { | |
2200 | return r1; | |
2201 | } else { | |
2202 | return r2; | |
2203 | } | |
2204 | } | |
2205 | ||
2206 | /* dirty bits used to track which watermarks need changes */ | |
2207 | #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) | |
2208 | #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) | |
2209 | #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) | |
2210 | #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) | |
2211 | #define WM_DIRTY_FBC (1 << 24) | |
2212 | #define WM_DIRTY_DDB (1 << 25) | |
2213 | ||
2214 | static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv, | |
2215 | const struct ilk_wm_values *old, | |
2216 | const struct ilk_wm_values *new) | |
2217 | { | |
2218 | unsigned int dirty = 0; | |
2219 | enum pipe pipe; | |
2220 | int wm_lp; | |
2221 | ||
2222 | for_each_pipe(dev_priv, pipe) { | |
2223 | if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { | |
2224 | dirty |= WM_DIRTY_LINETIME(pipe); | |
2225 | /* Must disable LP1+ watermarks too */ | |
2226 | dirty |= WM_DIRTY_LP_ALL; | |
2227 | } | |
2228 | ||
2229 | if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { | |
2230 | dirty |= WM_DIRTY_PIPE(pipe); | |
2231 | /* Must disable LP1+ watermarks too */ | |
2232 | dirty |= WM_DIRTY_LP_ALL; | |
2233 | } | |
2234 | } | |
2235 | ||
2236 | if (old->enable_fbc_wm != new->enable_fbc_wm) { | |
2237 | dirty |= WM_DIRTY_FBC; | |
2238 | /* Must disable LP1+ watermarks too */ | |
2239 | dirty |= WM_DIRTY_LP_ALL; | |
2240 | } | |
2241 | ||
2242 | if (old->partitioning != new->partitioning) { | |
2243 | dirty |= WM_DIRTY_DDB; | |
2244 | /* Must disable LP1+ watermarks too */ | |
2245 | dirty |= WM_DIRTY_LP_ALL; | |
2246 | } | |
2247 | ||
2248 | /* LP1+ watermarks already deemed dirty, no need to continue */ | |
2249 | if (dirty & WM_DIRTY_LP_ALL) | |
2250 | return dirty; | |
2251 | ||
2252 | /* Find the lowest numbered LP1+ watermark in need of an update... */ | |
2253 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { | |
2254 | if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || | |
2255 | old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) | |
2256 | break; | |
2257 | } | |
2258 | ||
2259 | /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ | |
2260 | for (; wm_lp <= 3; wm_lp++) | |
2261 | dirty |= WM_DIRTY_LP(wm_lp); | |
2262 | ||
2263 | return dirty; | |
2264 | } | |
2265 | ||
2266 | static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, | |
2267 | unsigned int dirty) | |
2268 | { | |
2269 | struct ilk_wm_values *previous = &dev_priv->wm.hw; | |
2270 | bool changed = false; | |
2271 | ||
2272 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { | |
2273 | previous->wm_lp[2] &= ~WM1_LP_SR_EN; | |
2274 | I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); | |
2275 | changed = true; | |
2276 | } | |
2277 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { | |
2278 | previous->wm_lp[1] &= ~WM1_LP_SR_EN; | |
2279 | I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); | |
2280 | changed = true; | |
2281 | } | |
2282 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { | |
2283 | previous->wm_lp[0] &= ~WM1_LP_SR_EN; | |
2284 | I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); | |
2285 | changed = true; | |
2286 | } | |
2287 | ||
2288 | /* | |
2289 | * Don't touch WM1S_LP_EN here. | |
2290 | * Doing so could cause underruns. | |
2291 | */ | |
2292 | ||
2293 | return changed; | |
2294 | } | |
2295 | ||
2296 | /* | |
2297 | * The spec says we shouldn't write when we don't need, because every write | |
2298 | * causes WMs to be re-evaluated, expending some power. | |
2299 | */ | |
2300 | static void ilk_write_wm_values(struct drm_i915_private *dev_priv, | |
2301 | struct ilk_wm_values *results) | |
2302 | { | |
2303 | struct drm_device *dev = dev_priv->dev; | |
2304 | struct ilk_wm_values *previous = &dev_priv->wm.hw; | |
2305 | unsigned int dirty; | |
2306 | uint32_t val; | |
2307 | ||
2308 | dirty = ilk_compute_wm_dirty(dev_priv, previous, results); | |
2309 | if (!dirty) | |
2310 | return; | |
2311 | ||
2312 | _ilk_disable_lp_wm(dev_priv, dirty); | |
2313 | ||
2314 | if (dirty & WM_DIRTY_PIPE(PIPE_A)) | |
2315 | I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); | |
2316 | if (dirty & WM_DIRTY_PIPE(PIPE_B)) | |
2317 | I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); | |
2318 | if (dirty & WM_DIRTY_PIPE(PIPE_C)) | |
2319 | I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); | |
2320 | ||
2321 | if (dirty & WM_DIRTY_LINETIME(PIPE_A)) | |
2322 | I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); | |
2323 | if (dirty & WM_DIRTY_LINETIME(PIPE_B)) | |
2324 | I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); | |
2325 | if (dirty & WM_DIRTY_LINETIME(PIPE_C)) | |
2326 | I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); | |
2327 | ||
2328 | if (dirty & WM_DIRTY_DDB) { | |
2329 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
2330 | val = I915_READ(WM_MISC); | |
2331 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
2332 | val &= ~WM_MISC_DATA_PARTITION_5_6; | |
2333 | else | |
2334 | val |= WM_MISC_DATA_PARTITION_5_6; | |
2335 | I915_WRITE(WM_MISC, val); | |
2336 | } else { | |
2337 | val = I915_READ(DISP_ARB_CTL2); | |
2338 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
2339 | val &= ~DISP_DATA_PARTITION_5_6; | |
2340 | else | |
2341 | val |= DISP_DATA_PARTITION_5_6; | |
2342 | I915_WRITE(DISP_ARB_CTL2, val); | |
2343 | } | |
2344 | } | |
2345 | ||
2346 | if (dirty & WM_DIRTY_FBC) { | |
2347 | val = I915_READ(DISP_ARB_CTL); | |
2348 | if (results->enable_fbc_wm) | |
2349 | val &= ~DISP_FBC_WM_DIS; | |
2350 | else | |
2351 | val |= DISP_FBC_WM_DIS; | |
2352 | I915_WRITE(DISP_ARB_CTL, val); | |
2353 | } | |
2354 | ||
2355 | if (dirty & WM_DIRTY_LP(1) && | |
2356 | previous->wm_lp_spr[0] != results->wm_lp_spr[0]) | |
2357 | I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); | |
2358 | ||
2359 | if (INTEL_INFO(dev)->gen >= 7) { | |
2360 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) | |
2361 | I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); | |
2362 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) | |
2363 | I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); | |
2364 | } | |
2365 | ||
2366 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) | |
2367 | I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); | |
2368 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) | |
2369 | I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); | |
2370 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) | |
2371 | I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); | |
2372 | ||
2373 | dev_priv->wm.hw = *results; | |
2374 | } | |
2375 | ||
2376 | static bool ilk_disable_lp_wm(struct drm_device *dev) | |
2377 | { | |
2378 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2379 | ||
2380 | return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); | |
2381 | } | |
2382 | ||
2383 | /* | |
2384 | * On gen9, we need to allocate Display Data Buffer (DDB) portions to the | |
2385 | * different active planes. | |
2386 | */ | |
2387 | ||
2388 | #define SKL_DDB_SIZE 896 /* in blocks */ | |
2389 | ||
2390 | static void | |
2391 | skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, | |
2392 | struct drm_crtc *for_crtc, | |
2393 | const struct intel_wm_config *config, | |
2394 | const struct skl_pipe_wm_parameters *params, | |
2395 | struct skl_ddb_entry *alloc /* out */) | |
2396 | { | |
2397 | struct drm_crtc *crtc; | |
2398 | unsigned int pipe_size, ddb_size; | |
2399 | int nth_active_pipe; | |
2400 | ||
2401 | if (!params->active) { | |
2402 | alloc->start = 0; | |
2403 | alloc->end = 0; | |
2404 | return; | |
2405 | } | |
2406 | ||
2407 | ddb_size = SKL_DDB_SIZE; | |
2408 | ||
2409 | ddb_size -= 4; /* 4 blocks for bypass path allocation */ | |
2410 | ||
2411 | nth_active_pipe = 0; | |
2412 | for_each_crtc(dev, crtc) { | |
2413 | if (!intel_crtc_active(crtc)) | |
2414 | continue; | |
2415 | ||
2416 | if (crtc == for_crtc) | |
2417 | break; | |
2418 | ||
2419 | nth_active_pipe++; | |
2420 | } | |
2421 | ||
2422 | pipe_size = ddb_size / config->num_pipes_active; | |
2423 | alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active; | |
2424 | alloc->end = alloc->start + pipe_size; | |
2425 | } | |
2426 | ||
2427 | static unsigned int skl_cursor_allocation(const struct intel_wm_config *config) | |
2428 | { | |
2429 | if (config->num_pipes_active == 1) | |
2430 | return 32; | |
2431 | ||
2432 | return 8; | |
2433 | } | |
2434 | ||
2435 | static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) | |
2436 | { | |
2437 | entry->start = reg & 0x3ff; | |
2438 | entry->end = (reg >> 16) & 0x3ff; | |
2439 | if (entry->end) | |
2440 | entry->end += 1; | |
2441 | } | |
2442 | ||
2443 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, | |
2444 | struct skl_ddb_allocation *ddb /* out */) | |
2445 | { | |
2446 | struct drm_device *dev = dev_priv->dev; | |
2447 | enum pipe pipe; | |
2448 | int plane; | |
2449 | u32 val; | |
2450 | ||
2451 | for_each_pipe(dev_priv, pipe) { | |
2452 | for_each_plane(pipe, plane) { | |
2453 | val = I915_READ(PLANE_BUF_CFG(pipe, plane)); | |
2454 | skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane], | |
2455 | val); | |
2456 | } | |
2457 | ||
2458 | val = I915_READ(CUR_BUF_CFG(pipe)); | |
2459 | skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val); | |
2460 | } | |
2461 | } | |
2462 | ||
2463 | static unsigned int | |
2464 | skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p) | |
2465 | { | |
2466 | return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel; | |
2467 | } | |
2468 | ||
2469 | /* | |
2470 | * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching | |
2471 | * a 8192x4096@32bpp framebuffer: | |
2472 | * 3 * 4096 * 8192 * 4 < 2^32 | |
2473 | */ | |
2474 | static unsigned int | |
2475 | skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc, | |
2476 | const struct skl_pipe_wm_parameters *params) | |
2477 | { | |
2478 | unsigned int total_data_rate = 0; | |
2479 | int plane; | |
2480 | ||
2481 | for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { | |
2482 | const struct intel_plane_wm_parameters *p; | |
2483 | ||
2484 | p = ¶ms->plane[plane]; | |
2485 | if (!p->enabled) | |
2486 | continue; | |
2487 | ||
2488 | total_data_rate += skl_plane_relative_data_rate(p); | |
2489 | } | |
2490 | ||
2491 | return total_data_rate; | |
2492 | } | |
2493 | ||
2494 | static void | |
2495 | skl_allocate_pipe_ddb(struct drm_crtc *crtc, | |
2496 | const struct intel_wm_config *config, | |
2497 | const struct skl_pipe_wm_parameters *params, | |
2498 | struct skl_ddb_allocation *ddb /* out */) | |
2499 | { | |
2500 | struct drm_device *dev = crtc->dev; | |
2501 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2502 | enum pipe pipe = intel_crtc->pipe; | |
2503 | struct skl_ddb_entry *alloc = &ddb->pipe[pipe]; | |
2504 | uint16_t alloc_size, start, cursor_blocks; | |
2505 | unsigned int total_data_rate; | |
2506 | int plane; | |
2507 | ||
2508 | skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc); | |
2509 | alloc_size = skl_ddb_entry_size(alloc); | |
2510 | if (alloc_size == 0) { | |
2511 | memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); | |
2512 | memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe])); | |
2513 | return; | |
2514 | } | |
2515 | ||
2516 | cursor_blocks = skl_cursor_allocation(config); | |
2517 | ddb->cursor[pipe].start = alloc->end - cursor_blocks; | |
2518 | ddb->cursor[pipe].end = alloc->end; | |
2519 | ||
2520 | alloc_size -= cursor_blocks; | |
2521 | alloc->end -= cursor_blocks; | |
2522 | ||
2523 | /* | |
2524 | * Each active plane get a portion of the remaining space, in | |
2525 | * proportion to the amount of data they need to fetch from memory. | |
2526 | * | |
2527 | * FIXME: we may not allocate every single block here. | |
2528 | */ | |
2529 | total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params); | |
2530 | ||
2531 | start = alloc->start; | |
2532 | for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { | |
2533 | const struct intel_plane_wm_parameters *p; | |
2534 | unsigned int data_rate; | |
2535 | uint16_t plane_blocks; | |
2536 | ||
2537 | p = ¶ms->plane[plane]; | |
2538 | if (!p->enabled) | |
2539 | continue; | |
2540 | ||
2541 | data_rate = skl_plane_relative_data_rate(p); | |
2542 | ||
2543 | /* | |
2544 | * promote the expression to 64 bits to avoid overflowing, the | |
2545 | * result is < available as data_rate / total_data_rate < 1 | |
2546 | */ | |
2547 | plane_blocks = div_u64((uint64_t)alloc_size * data_rate, | |
2548 | total_data_rate); | |
2549 | ||
2550 | ddb->plane[pipe][plane].start = start; | |
2551 | ddb->plane[pipe][plane].end = start + plane_blocks; | |
2552 | ||
2553 | start += plane_blocks; | |
2554 | } | |
2555 | ||
2556 | } | |
2557 | ||
2558 | static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config) | |
2559 | { | |
2560 | /* TODO: Take into account the scalers once we support them */ | |
2561 | return config->base.adjusted_mode.crtc_clock; | |
2562 | } | |
2563 | ||
2564 | /* | |
2565 | * The max latency should be 257 (max the punit can code is 255 and we add 2us | |
2566 | * for the read latency) and bytes_per_pixel should always be <= 8, so that | |
2567 | * should allow pixel_rate up to ~2 GHz which seems sufficient since max | |
2568 | * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. | |
2569 | */ | |
2570 | static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, | |
2571 | uint32_t latency) | |
2572 | { | |
2573 | uint32_t wm_intermediate_val, ret; | |
2574 | ||
2575 | if (latency == 0) | |
2576 | return UINT_MAX; | |
2577 | ||
2578 | wm_intermediate_val = latency * pixel_rate * bytes_per_pixel; | |
2579 | ret = DIV_ROUND_UP(wm_intermediate_val, 1000); | |
2580 | ||
2581 | return ret; | |
2582 | } | |
2583 | ||
2584 | static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, | |
2585 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, | |
2586 | uint32_t latency) | |
2587 | { | |
2588 | uint32_t ret, plane_bytes_per_line, wm_intermediate_val; | |
2589 | ||
2590 | if (latency == 0) | |
2591 | return UINT_MAX; | |
2592 | ||
2593 | plane_bytes_per_line = horiz_pixels * bytes_per_pixel; | |
2594 | wm_intermediate_val = latency * pixel_rate; | |
2595 | ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) * | |
2596 | plane_bytes_per_line; | |
2597 | ||
2598 | return ret; | |
2599 | } | |
2600 | ||
2601 | static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb, | |
2602 | const struct intel_crtc *intel_crtc) | |
2603 | { | |
2604 | struct drm_device *dev = intel_crtc->base.dev; | |
2605 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2606 | const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb; | |
2607 | enum pipe pipe = intel_crtc->pipe; | |
2608 | ||
2609 | if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe], | |
2610 | sizeof(new_ddb->plane[pipe]))) | |
2611 | return true; | |
2612 | ||
2613 | if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe], | |
2614 | sizeof(new_ddb->cursor[pipe]))) | |
2615 | return true; | |
2616 | ||
2617 | return false; | |
2618 | } | |
2619 | ||
2620 | static void skl_compute_wm_global_parameters(struct drm_device *dev, | |
2621 | struct intel_wm_config *config) | |
2622 | { | |
2623 | struct drm_crtc *crtc; | |
2624 | struct drm_plane *plane; | |
2625 | ||
2626 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
2627 | config->num_pipes_active += intel_crtc_active(crtc); | |
2628 | ||
2629 | /* FIXME: I don't think we need those two global parameters on SKL */ | |
2630 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
2631 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
2632 | ||
2633 | config->sprites_enabled |= intel_plane->wm.enabled; | |
2634 | config->sprites_scaled |= intel_plane->wm.scaled; | |
2635 | } | |
2636 | } | |
2637 | ||
2638 | static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc, | |
2639 | struct skl_pipe_wm_parameters *p) | |
2640 | { | |
2641 | struct drm_device *dev = crtc->dev; | |
2642 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2643 | enum pipe pipe = intel_crtc->pipe; | |
2644 | struct drm_plane *plane; | |
2645 | int i = 1; /* Index for sprite planes start */ | |
2646 | ||
2647 | p->active = intel_crtc_active(crtc); | |
2648 | if (p->active) { | |
2649 | p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal; | |
2650 | p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config); | |
2651 | ||
2652 | /* | |
2653 | * For now, assume primary and cursor planes are always enabled. | |
2654 | */ | |
2655 | p->plane[0].enabled = true; | |
2656 | p->plane[0].bytes_per_pixel = | |
2657 | crtc->primary->fb->bits_per_pixel / 8; | |
2658 | p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w; | |
2659 | p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h; | |
2660 | ||
2661 | p->cursor.enabled = true; | |
2662 | p->cursor.bytes_per_pixel = 4; | |
2663 | p->cursor.horiz_pixels = intel_crtc->cursor_width ? | |
2664 | intel_crtc->cursor_width : 64; | |
2665 | } | |
2666 | ||
2667 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
2668 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
2669 | ||
2670 | if (intel_plane->pipe == pipe && | |
2671 | plane->type == DRM_PLANE_TYPE_OVERLAY) | |
2672 | p->plane[i++] = intel_plane->wm; | |
2673 | } | |
2674 | } | |
2675 | ||
2676 | static bool skl_compute_plane_wm(struct skl_pipe_wm_parameters *p, | |
2677 | struct intel_plane_wm_parameters *p_params, | |
2678 | uint16_t ddb_allocation, | |
2679 | uint32_t mem_value, | |
2680 | uint16_t *out_blocks, /* out */ | |
2681 | uint8_t *out_lines /* out */) | |
2682 | { | |
2683 | uint32_t method1, method2, plane_bytes_per_line, res_blocks, res_lines; | |
2684 | uint32_t result_bytes; | |
2685 | ||
2686 | if (mem_value == 0 || !p->active || !p_params->enabled) | |
2687 | return false; | |
2688 | ||
2689 | method1 = skl_wm_method1(p->pixel_rate, | |
2690 | p_params->bytes_per_pixel, | |
2691 | mem_value); | |
2692 | method2 = skl_wm_method2(p->pixel_rate, | |
2693 | p->pipe_htotal, | |
2694 | p_params->horiz_pixels, | |
2695 | p_params->bytes_per_pixel, | |
2696 | mem_value); | |
2697 | ||
2698 | plane_bytes_per_line = p_params->horiz_pixels * | |
2699 | p_params->bytes_per_pixel; | |
2700 | ||
2701 | /* For now xtile and linear */ | |
2702 | if (((ddb_allocation * 512) / plane_bytes_per_line) >= 1) | |
2703 | result_bytes = min(method1, method2); | |
2704 | else | |
2705 | result_bytes = method1; | |
2706 | ||
2707 | res_blocks = DIV_ROUND_UP(result_bytes, 512) + 1; | |
2708 | res_lines = DIV_ROUND_UP(result_bytes, plane_bytes_per_line); | |
2709 | ||
2710 | if (res_blocks > ddb_allocation || res_lines > 31) | |
2711 | return false; | |
2712 | ||
2713 | *out_blocks = res_blocks; | |
2714 | *out_lines = res_lines; | |
2715 | ||
2716 | return true; | |
2717 | } | |
2718 | ||
2719 | static void skl_compute_wm_level(const struct drm_i915_private *dev_priv, | |
2720 | struct skl_ddb_allocation *ddb, | |
2721 | struct skl_pipe_wm_parameters *p, | |
2722 | enum pipe pipe, | |
2723 | int level, | |
2724 | int num_planes, | |
2725 | struct skl_wm_level *result) | |
2726 | { | |
2727 | uint16_t latency = dev_priv->wm.skl_latency[level]; | |
2728 | uint16_t ddb_blocks; | |
2729 | int i; | |
2730 | ||
2731 | for (i = 0; i < num_planes; i++) { | |
2732 | ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]); | |
2733 | ||
2734 | result->plane_en[i] = skl_compute_plane_wm(p, &p->plane[i], | |
2735 | ddb_blocks, | |
2736 | latency, | |
2737 | &result->plane_res_b[i], | |
2738 | &result->plane_res_l[i]); | |
2739 | } | |
2740 | ||
2741 | ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]); | |
2742 | result->cursor_en = skl_compute_plane_wm(p, &p->cursor, ddb_blocks, | |
2743 | latency, &result->cursor_res_b, | |
2744 | &result->cursor_res_l); | |
2745 | } | |
2746 | ||
2747 | static uint32_t | |
2748 | skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p) | |
2749 | { | |
2750 | if (!intel_crtc_active(crtc)) | |
2751 | return 0; | |
2752 | ||
2753 | return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate); | |
2754 | ||
2755 | } | |
2756 | ||
2757 | static void skl_compute_transition_wm(struct drm_crtc *crtc, | |
2758 | struct skl_pipe_wm_parameters *params, | |
2759 | struct skl_wm_level *trans_wm /* out */) | |
2760 | { | |
2761 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2762 | int i; | |
2763 | ||
2764 | if (!params->active) | |
2765 | return; | |
2766 | ||
2767 | /* Until we know more, just disable transition WMs */ | |
2768 | for (i = 0; i < intel_num_planes(intel_crtc); i++) | |
2769 | trans_wm->plane_en[i] = false; | |
2770 | trans_wm->cursor_en = false; | |
2771 | } | |
2772 | ||
2773 | static void skl_compute_pipe_wm(struct drm_crtc *crtc, | |
2774 | struct skl_ddb_allocation *ddb, | |
2775 | struct skl_pipe_wm_parameters *params, | |
2776 | struct skl_pipe_wm *pipe_wm) | |
2777 | { | |
2778 | struct drm_device *dev = crtc->dev; | |
2779 | const struct drm_i915_private *dev_priv = dev->dev_private; | |
2780 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2781 | int level, max_level = ilk_wm_max_level(dev); | |
2782 | ||
2783 | for (level = 0; level <= max_level; level++) { | |
2784 | skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe, | |
2785 | level, intel_num_planes(intel_crtc), | |
2786 | &pipe_wm->wm[level]); | |
2787 | } | |
2788 | pipe_wm->linetime = skl_compute_linetime_wm(crtc, params); | |
2789 | ||
2790 | skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm); | |
2791 | } | |
2792 | ||
2793 | static void skl_compute_wm_results(struct drm_device *dev, | |
2794 | struct skl_pipe_wm_parameters *p, | |
2795 | struct skl_pipe_wm *p_wm, | |
2796 | struct skl_wm_values *r, | |
2797 | struct intel_crtc *intel_crtc) | |
2798 | { | |
2799 | int level, max_level = ilk_wm_max_level(dev); | |
2800 | enum pipe pipe = intel_crtc->pipe; | |
2801 | uint32_t temp; | |
2802 | int i; | |
2803 | ||
2804 | for (level = 0; level <= max_level; level++) { | |
2805 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { | |
2806 | temp = 0; | |
2807 | ||
2808 | temp |= p_wm->wm[level].plane_res_l[i] << | |
2809 | PLANE_WM_LINES_SHIFT; | |
2810 | temp |= p_wm->wm[level].plane_res_b[i]; | |
2811 | if (p_wm->wm[level].plane_en[i]) | |
2812 | temp |= PLANE_WM_EN; | |
2813 | ||
2814 | r->plane[pipe][i][level] = temp; | |
2815 | } | |
2816 | ||
2817 | temp = 0; | |
2818 | ||
2819 | temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT; | |
2820 | temp |= p_wm->wm[level].cursor_res_b; | |
2821 | ||
2822 | if (p_wm->wm[level].cursor_en) | |
2823 | temp |= PLANE_WM_EN; | |
2824 | ||
2825 | r->cursor[pipe][level] = temp; | |
2826 | ||
2827 | } | |
2828 | ||
2829 | /* transition WMs */ | |
2830 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { | |
2831 | temp = 0; | |
2832 | temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT; | |
2833 | temp |= p_wm->trans_wm.plane_res_b[i]; | |
2834 | if (p_wm->trans_wm.plane_en[i]) | |
2835 | temp |= PLANE_WM_EN; | |
2836 | ||
2837 | r->plane_trans[pipe][i] = temp; | |
2838 | } | |
2839 | ||
2840 | temp = 0; | |
2841 | temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT; | |
2842 | temp |= p_wm->trans_wm.cursor_res_b; | |
2843 | if (p_wm->trans_wm.cursor_en) | |
2844 | temp |= PLANE_WM_EN; | |
2845 | ||
2846 | r->cursor_trans[pipe] = temp; | |
2847 | ||
2848 | r->wm_linetime[pipe] = p_wm->linetime; | |
2849 | } | |
2850 | ||
2851 | static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg, | |
2852 | const struct skl_ddb_entry *entry) | |
2853 | { | |
2854 | if (entry->end) | |
2855 | I915_WRITE(reg, (entry->end - 1) << 16 | entry->start); | |
2856 | else | |
2857 | I915_WRITE(reg, 0); | |
2858 | } | |
2859 | ||
2860 | static void skl_write_wm_values(struct drm_i915_private *dev_priv, | |
2861 | const struct skl_wm_values *new) | |
2862 | { | |
2863 | struct drm_device *dev = dev_priv->dev; | |
2864 | struct intel_crtc *crtc; | |
2865 | ||
2866 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
2867 | int i, level, max_level = ilk_wm_max_level(dev); | |
2868 | enum pipe pipe = crtc->pipe; | |
2869 | ||
2870 | if (!new->dirty[pipe]) | |
2871 | continue; | |
2872 | ||
2873 | I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]); | |
2874 | ||
2875 | for (level = 0; level <= max_level; level++) { | |
2876 | for (i = 0; i < intel_num_planes(crtc); i++) | |
2877 | I915_WRITE(PLANE_WM(pipe, i, level), | |
2878 | new->plane[pipe][i][level]); | |
2879 | I915_WRITE(CUR_WM(pipe, level), | |
2880 | new->cursor[pipe][level]); | |
2881 | } | |
2882 | for (i = 0; i < intel_num_planes(crtc); i++) | |
2883 | I915_WRITE(PLANE_WM_TRANS(pipe, i), | |
2884 | new->plane_trans[pipe][i]); | |
2885 | I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]); | |
2886 | ||
2887 | for (i = 0; i < intel_num_planes(crtc); i++) | |
2888 | skl_ddb_entry_write(dev_priv, | |
2889 | PLANE_BUF_CFG(pipe, i), | |
2890 | &new->ddb.plane[pipe][i]); | |
2891 | ||
2892 | skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), | |
2893 | &new->ddb.cursor[pipe]); | |
2894 | } | |
2895 | } | |
2896 | ||
2897 | /* | |
2898 | * When setting up a new DDB allocation arrangement, we need to correctly | |
2899 | * sequence the times at which the new allocations for the pipes are taken into | |
2900 | * account or we'll have pipes fetching from space previously allocated to | |
2901 | * another pipe. | |
2902 | * | |
2903 | * Roughly the sequence looks like: | |
2904 | * 1. re-allocate the pipe(s) with the allocation being reduced and not | |
2905 | * overlapping with a previous light-up pipe (another way to put it is: | |
2906 | * pipes with their new allocation strickly included into their old ones). | |
2907 | * 2. re-allocate the other pipes that get their allocation reduced | |
2908 | * 3. allocate the pipes having their allocation increased | |
2909 | * | |
2910 | * Steps 1. and 2. are here to take care of the following case: | |
2911 | * - Initially DDB looks like this: | |
2912 | * | B | C | | |
2913 | * - enable pipe A. | |
2914 | * - pipe B has a reduced DDB allocation that overlaps with the old pipe C | |
2915 | * allocation | |
2916 | * | A | B | C | | |
2917 | * | |
2918 | * We need to sequence the re-allocation: C, B, A (and not B, C, A). | |
2919 | */ | |
2920 | ||
2921 | static void | |
2922 | skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass) | |
2923 | { | |
2924 | struct drm_device *dev = dev_priv->dev; | |
2925 | int plane; | |
2926 | ||
2927 | DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass); | |
2928 | ||
2929 | for_each_plane(pipe, plane) { | |
2930 | I915_WRITE(PLANE_SURF(pipe, plane), | |
2931 | I915_READ(PLANE_SURF(pipe, plane))); | |
2932 | } | |
2933 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); | |
2934 | } | |
2935 | ||
2936 | static bool | |
2937 | skl_ddb_allocation_included(const struct skl_ddb_allocation *old, | |
2938 | const struct skl_ddb_allocation *new, | |
2939 | enum pipe pipe) | |
2940 | { | |
2941 | uint16_t old_size, new_size; | |
2942 | ||
2943 | old_size = skl_ddb_entry_size(&old->pipe[pipe]); | |
2944 | new_size = skl_ddb_entry_size(&new->pipe[pipe]); | |
2945 | ||
2946 | return old_size != new_size && | |
2947 | new->pipe[pipe].start >= old->pipe[pipe].start && | |
2948 | new->pipe[pipe].end <= old->pipe[pipe].end; | |
2949 | } | |
2950 | ||
2951 | static void skl_flush_wm_values(struct drm_i915_private *dev_priv, | |
2952 | struct skl_wm_values *new_values) | |
2953 | { | |
2954 | struct drm_device *dev = dev_priv->dev; | |
2955 | struct skl_ddb_allocation *cur_ddb, *new_ddb; | |
2956 | bool reallocated[I915_MAX_PIPES] = {false, false, false}; | |
2957 | struct intel_crtc *crtc; | |
2958 | enum pipe pipe; | |
2959 | ||
2960 | new_ddb = &new_values->ddb; | |
2961 | cur_ddb = &dev_priv->wm.skl_hw.ddb; | |
2962 | ||
2963 | /* | |
2964 | * First pass: flush the pipes with the new allocation contained into | |
2965 | * the old space. | |
2966 | * | |
2967 | * We'll wait for the vblank on those pipes to ensure we can safely | |
2968 | * re-allocate the freed space without this pipe fetching from it. | |
2969 | */ | |
2970 | for_each_intel_crtc(dev, crtc) { | |
2971 | if (!crtc->active) | |
2972 | continue; | |
2973 | ||
2974 | pipe = crtc->pipe; | |
2975 | ||
2976 | if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe)) | |
2977 | continue; | |
2978 | ||
2979 | skl_wm_flush_pipe(dev_priv, pipe, 1); | |
2980 | intel_wait_for_vblank(dev, pipe); | |
2981 | ||
2982 | reallocated[pipe] = true; | |
2983 | } | |
2984 | ||
2985 | ||
2986 | /* | |
2987 | * Second pass: flush the pipes that are having their allocation | |
2988 | * reduced, but overlapping with a previous allocation. | |
2989 | * | |
2990 | * Here as well we need to wait for the vblank to make sure the freed | |
2991 | * space is not used anymore. | |
2992 | */ | |
2993 | for_each_intel_crtc(dev, crtc) { | |
2994 | if (!crtc->active) | |
2995 | continue; | |
2996 | ||
2997 | pipe = crtc->pipe; | |
2998 | ||
2999 | if (reallocated[pipe]) | |
3000 | continue; | |
3001 | ||
3002 | if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) < | |
3003 | skl_ddb_entry_size(&cur_ddb->pipe[pipe])) { | |
3004 | skl_wm_flush_pipe(dev_priv, pipe, 2); | |
3005 | intel_wait_for_vblank(dev, pipe); | |
3006 | reallocated[pipe] = true; | |
3007 | } | |
3008 | } | |
3009 | ||
3010 | /* | |
3011 | * Third pass: flush the pipes that got more space allocated. | |
3012 | * | |
3013 | * We don't need to actively wait for the update here, next vblank | |
3014 | * will just get more DDB space with the correct WM values. | |
3015 | */ | |
3016 | for_each_intel_crtc(dev, crtc) { | |
3017 | if (!crtc->active) | |
3018 | continue; | |
3019 | ||
3020 | pipe = crtc->pipe; | |
3021 | ||
3022 | /* | |
3023 | * At this point, only the pipes more space than before are | |
3024 | * left to re-allocate. | |
3025 | */ | |
3026 | if (reallocated[pipe]) | |
3027 | continue; | |
3028 | ||
3029 | skl_wm_flush_pipe(dev_priv, pipe, 3); | |
3030 | } | |
3031 | } | |
3032 | ||
3033 | static bool skl_update_pipe_wm(struct drm_crtc *crtc, | |
3034 | struct skl_pipe_wm_parameters *params, | |
3035 | struct intel_wm_config *config, | |
3036 | struct skl_ddb_allocation *ddb, /* out */ | |
3037 | struct skl_pipe_wm *pipe_wm /* out */) | |
3038 | { | |
3039 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3040 | ||
3041 | skl_compute_wm_pipe_parameters(crtc, params); | |
3042 | skl_allocate_pipe_ddb(crtc, config, params, ddb); | |
3043 | skl_compute_pipe_wm(crtc, ddb, params, pipe_wm); | |
3044 | ||
3045 | if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm))) | |
3046 | return false; | |
3047 | ||
3048 | intel_crtc->wm.skl_active = *pipe_wm; | |
3049 | return true; | |
3050 | } | |
3051 | ||
3052 | static void skl_update_other_pipe_wm(struct drm_device *dev, | |
3053 | struct drm_crtc *crtc, | |
3054 | struct intel_wm_config *config, | |
3055 | struct skl_wm_values *r) | |
3056 | { | |
3057 | struct intel_crtc *intel_crtc; | |
3058 | struct intel_crtc *this_crtc = to_intel_crtc(crtc); | |
3059 | ||
3060 | /* | |
3061 | * If the WM update hasn't changed the allocation for this_crtc (the | |
3062 | * crtc we are currently computing the new WM values for), other | |
3063 | * enabled crtcs will keep the same allocation and we don't need to | |
3064 | * recompute anything for them. | |
3065 | */ | |
3066 | if (!skl_ddb_allocation_changed(&r->ddb, this_crtc)) | |
3067 | return; | |
3068 | ||
3069 | /* | |
3070 | * Otherwise, because of this_crtc being freshly enabled/disabled, the | |
3071 | * other active pipes need new DDB allocation and WM values. | |
3072 | */ | |
3073 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
3074 | base.head) { | |
3075 | struct skl_pipe_wm_parameters params = {}; | |
3076 | struct skl_pipe_wm pipe_wm = {}; | |
3077 | bool wm_changed; | |
3078 | ||
3079 | if (this_crtc->pipe == intel_crtc->pipe) | |
3080 | continue; | |
3081 | ||
3082 | if (!intel_crtc->active) | |
3083 | continue; | |
3084 | ||
3085 | wm_changed = skl_update_pipe_wm(&intel_crtc->base, | |
3086 | ¶ms, config, | |
3087 | &r->ddb, &pipe_wm); | |
3088 | ||
3089 | /* | |
3090 | * If we end up re-computing the other pipe WM values, it's | |
3091 | * because it was really needed, so we expect the WM values to | |
3092 | * be different. | |
3093 | */ | |
3094 | WARN_ON(!wm_changed); | |
3095 | ||
3096 | skl_compute_wm_results(dev, ¶ms, &pipe_wm, r, intel_crtc); | |
3097 | r->dirty[intel_crtc->pipe] = true; | |
3098 | } | |
3099 | } | |
3100 | ||
3101 | static void skl_update_wm(struct drm_crtc *crtc) | |
3102 | { | |
3103 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3104 | struct drm_device *dev = crtc->dev; | |
3105 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3106 | struct skl_pipe_wm_parameters params = {}; | |
3107 | struct skl_wm_values *results = &dev_priv->wm.skl_results; | |
3108 | struct skl_pipe_wm pipe_wm = {}; | |
3109 | struct intel_wm_config config = {}; | |
3110 | ||
3111 | memset(results, 0, sizeof(*results)); | |
3112 | ||
3113 | skl_compute_wm_global_parameters(dev, &config); | |
3114 | ||
3115 | if (!skl_update_pipe_wm(crtc, ¶ms, &config, | |
3116 | &results->ddb, &pipe_wm)) | |
3117 | return; | |
3118 | ||
3119 | skl_compute_wm_results(dev, ¶ms, &pipe_wm, results, intel_crtc); | |
3120 | results->dirty[intel_crtc->pipe] = true; | |
3121 | ||
3122 | skl_update_other_pipe_wm(dev, crtc, &config, results); | |
3123 | skl_write_wm_values(dev_priv, results); | |
3124 | skl_flush_wm_values(dev_priv, results); | |
3125 | ||
3126 | /* store the new configuration */ | |
3127 | dev_priv->wm.skl_hw = *results; | |
3128 | } | |
3129 | ||
3130 | static void | |
3131 | skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc, | |
3132 | uint32_t sprite_width, uint32_t sprite_height, | |
3133 | int pixel_size, bool enabled, bool scaled) | |
3134 | { | |
3135 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
3136 | ||
3137 | intel_plane->wm.enabled = enabled; | |
3138 | intel_plane->wm.scaled = scaled; | |
3139 | intel_plane->wm.horiz_pixels = sprite_width; | |
3140 | intel_plane->wm.vert_pixels = sprite_height; | |
3141 | intel_plane->wm.bytes_per_pixel = pixel_size; | |
3142 | ||
3143 | skl_update_wm(crtc); | |
3144 | } | |
3145 | ||
3146 | static void ilk_update_wm(struct drm_crtc *crtc) | |
3147 | { | |
3148 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3149 | struct drm_device *dev = crtc->dev; | |
3150 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3151 | struct ilk_wm_maximums max; | |
3152 | struct ilk_pipe_wm_parameters params = {}; | |
3153 | struct ilk_wm_values results = {}; | |
3154 | enum intel_ddb_partitioning partitioning; | |
3155 | struct intel_pipe_wm pipe_wm = {}; | |
3156 | struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; | |
3157 | struct intel_wm_config config = {}; | |
3158 | ||
3159 | ilk_compute_wm_parameters(crtc, ¶ms); | |
3160 | ||
3161 | intel_compute_pipe_wm(crtc, ¶ms, &pipe_wm); | |
3162 | ||
3163 | if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm))) | |
3164 | return; | |
3165 | ||
3166 | intel_crtc->wm.active = pipe_wm; | |
3167 | ||
3168 | ilk_compute_wm_config(dev, &config); | |
3169 | ||
3170 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); | |
3171 | ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); | |
3172 | ||
3173 | /* 5/6 split only in single pipe config on IVB+ */ | |
3174 | if (INTEL_INFO(dev)->gen >= 7 && | |
3175 | config.num_pipes_active == 1 && config.sprites_enabled) { | |
3176 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); | |
3177 | ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); | |
3178 | ||
3179 | best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); | |
3180 | } else { | |
3181 | best_lp_wm = &lp_wm_1_2; | |
3182 | } | |
3183 | ||
3184 | partitioning = (best_lp_wm == &lp_wm_1_2) ? | |
3185 | INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; | |
3186 | ||
3187 | ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); | |
3188 | ||
3189 | ilk_write_wm_values(dev_priv, &results); | |
3190 | } | |
3191 | ||
3192 | static void | |
3193 | ilk_update_sprite_wm(struct drm_plane *plane, | |
3194 | struct drm_crtc *crtc, | |
3195 | uint32_t sprite_width, uint32_t sprite_height, | |
3196 | int pixel_size, bool enabled, bool scaled) | |
3197 | { | |
3198 | struct drm_device *dev = plane->dev; | |
3199 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
3200 | ||
3201 | intel_plane->wm.enabled = enabled; | |
3202 | intel_plane->wm.scaled = scaled; | |
3203 | intel_plane->wm.horiz_pixels = sprite_width; | |
3204 | intel_plane->wm.vert_pixels = sprite_width; | |
3205 | intel_plane->wm.bytes_per_pixel = pixel_size; | |
3206 | ||
3207 | /* | |
3208 | * IVB workaround: must disable low power watermarks for at least | |
3209 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
3210 | * when scaling is disabled. | |
3211 | * | |
3212 | * WaCxSRDisabledForSpriteScaling:ivb | |
3213 | */ | |
3214 | if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev)) | |
3215 | intel_wait_for_vblank(dev, intel_plane->pipe); | |
3216 | ||
3217 | ilk_update_wm(crtc); | |
3218 | } | |
3219 | ||
3220 | static void skl_pipe_wm_active_state(uint32_t val, | |
3221 | struct skl_pipe_wm *active, | |
3222 | bool is_transwm, | |
3223 | bool is_cursor, | |
3224 | int i, | |
3225 | int level) | |
3226 | { | |
3227 | bool is_enabled = (val & PLANE_WM_EN) != 0; | |
3228 | ||
3229 | if (!is_transwm) { | |
3230 | if (!is_cursor) { | |
3231 | active->wm[level].plane_en[i] = is_enabled; | |
3232 | active->wm[level].plane_res_b[i] = | |
3233 | val & PLANE_WM_BLOCKS_MASK; | |
3234 | active->wm[level].plane_res_l[i] = | |
3235 | (val >> PLANE_WM_LINES_SHIFT) & | |
3236 | PLANE_WM_LINES_MASK; | |
3237 | } else { | |
3238 | active->wm[level].cursor_en = is_enabled; | |
3239 | active->wm[level].cursor_res_b = | |
3240 | val & PLANE_WM_BLOCKS_MASK; | |
3241 | active->wm[level].cursor_res_l = | |
3242 | (val >> PLANE_WM_LINES_SHIFT) & | |
3243 | PLANE_WM_LINES_MASK; | |
3244 | } | |
3245 | } else { | |
3246 | if (!is_cursor) { | |
3247 | active->trans_wm.plane_en[i] = is_enabled; | |
3248 | active->trans_wm.plane_res_b[i] = | |
3249 | val & PLANE_WM_BLOCKS_MASK; | |
3250 | active->trans_wm.plane_res_l[i] = | |
3251 | (val >> PLANE_WM_LINES_SHIFT) & | |
3252 | PLANE_WM_LINES_MASK; | |
3253 | } else { | |
3254 | active->trans_wm.cursor_en = is_enabled; | |
3255 | active->trans_wm.cursor_res_b = | |
3256 | val & PLANE_WM_BLOCKS_MASK; | |
3257 | active->trans_wm.cursor_res_l = | |
3258 | (val >> PLANE_WM_LINES_SHIFT) & | |
3259 | PLANE_WM_LINES_MASK; | |
3260 | } | |
3261 | } | |
3262 | } | |
3263 | ||
3264 | static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc) | |
3265 | { | |
3266 | struct drm_device *dev = crtc->dev; | |
3267 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3268 | struct skl_wm_values *hw = &dev_priv->wm.skl_hw; | |
3269 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3270 | struct skl_pipe_wm *active = &intel_crtc->wm.skl_active; | |
3271 | enum pipe pipe = intel_crtc->pipe; | |
3272 | int level, i, max_level; | |
3273 | uint32_t temp; | |
3274 | ||
3275 | max_level = ilk_wm_max_level(dev); | |
3276 | ||
3277 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); | |
3278 | ||
3279 | for (level = 0; level <= max_level; level++) { | |
3280 | for (i = 0; i < intel_num_planes(intel_crtc); i++) | |
3281 | hw->plane[pipe][i][level] = | |
3282 | I915_READ(PLANE_WM(pipe, i, level)); | |
3283 | hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level)); | |
3284 | } | |
3285 | ||
3286 | for (i = 0; i < intel_num_planes(intel_crtc); i++) | |
3287 | hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i)); | |
3288 | hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe)); | |
3289 | ||
3290 | if (!intel_crtc_active(crtc)) | |
3291 | return; | |
3292 | ||
3293 | hw->dirty[pipe] = true; | |
3294 | ||
3295 | active->linetime = hw->wm_linetime[pipe]; | |
3296 | ||
3297 | for (level = 0; level <= max_level; level++) { | |
3298 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { | |
3299 | temp = hw->plane[pipe][i][level]; | |
3300 | skl_pipe_wm_active_state(temp, active, false, | |
3301 | false, i, level); | |
3302 | } | |
3303 | temp = hw->cursor[pipe][level]; | |
3304 | skl_pipe_wm_active_state(temp, active, false, true, i, level); | |
3305 | } | |
3306 | ||
3307 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { | |
3308 | temp = hw->plane_trans[pipe][i]; | |
3309 | skl_pipe_wm_active_state(temp, active, true, false, i, 0); | |
3310 | } | |
3311 | ||
3312 | temp = hw->cursor_trans[pipe]; | |
3313 | skl_pipe_wm_active_state(temp, active, true, true, i, 0); | |
3314 | } | |
3315 | ||
3316 | void skl_wm_get_hw_state(struct drm_device *dev) | |
3317 | { | |
3318 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3319 | struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; | |
3320 | struct drm_crtc *crtc; | |
3321 | ||
3322 | skl_ddb_get_hw_state(dev_priv, ddb); | |
3323 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
3324 | skl_pipe_wm_get_hw_state(crtc); | |
3325 | } | |
3326 | ||
3327 | static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) | |
3328 | { | |
3329 | struct drm_device *dev = crtc->dev; | |
3330 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3331 | struct ilk_wm_values *hw = &dev_priv->wm.hw; | |
3332 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3333 | struct intel_pipe_wm *active = &intel_crtc->wm.active; | |
3334 | enum pipe pipe = intel_crtc->pipe; | |
3335 | static const unsigned int wm0_pipe_reg[] = { | |
3336 | [PIPE_A] = WM0_PIPEA_ILK, | |
3337 | [PIPE_B] = WM0_PIPEB_ILK, | |
3338 | [PIPE_C] = WM0_PIPEC_IVB, | |
3339 | }; | |
3340 | ||
3341 | hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); | |
3342 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
3343 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); | |
3344 | ||
3345 | active->pipe_enabled = intel_crtc_active(crtc); | |
3346 | ||
3347 | if (active->pipe_enabled) { | |
3348 | u32 tmp = hw->wm_pipe[pipe]; | |
3349 | ||
3350 | /* | |
3351 | * For active pipes LP0 watermark is marked as | |
3352 | * enabled, and LP1+ watermaks as disabled since | |
3353 | * we can't really reverse compute them in case | |
3354 | * multiple pipes are active. | |
3355 | */ | |
3356 | active->wm[0].enable = true; | |
3357 | active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; | |
3358 | active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; | |
3359 | active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; | |
3360 | active->linetime = hw->wm_linetime[pipe]; | |
3361 | } else { | |
3362 | int level, max_level = ilk_wm_max_level(dev); | |
3363 | ||
3364 | /* | |
3365 | * For inactive pipes, all watermark levels | |
3366 | * should be marked as enabled but zeroed, | |
3367 | * which is what we'd compute them to. | |
3368 | */ | |
3369 | for (level = 0; level <= max_level; level++) | |
3370 | active->wm[level].enable = true; | |
3371 | } | |
3372 | } | |
3373 | ||
3374 | void ilk_wm_get_hw_state(struct drm_device *dev) | |
3375 | { | |
3376 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3377 | struct ilk_wm_values *hw = &dev_priv->wm.hw; | |
3378 | struct drm_crtc *crtc; | |
3379 | ||
3380 | for_each_crtc(dev, crtc) | |
3381 | ilk_pipe_wm_get_hw_state(crtc); | |
3382 | ||
3383 | hw->wm_lp[0] = I915_READ(WM1_LP_ILK); | |
3384 | hw->wm_lp[1] = I915_READ(WM2_LP_ILK); | |
3385 | hw->wm_lp[2] = I915_READ(WM3_LP_ILK); | |
3386 | ||
3387 | hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); | |
3388 | if (INTEL_INFO(dev)->gen >= 7) { | |
3389 | hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); | |
3390 | hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); | |
3391 | } | |
3392 | ||
3393 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
3394 | hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? | |
3395 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
3396 | else if (IS_IVYBRIDGE(dev)) | |
3397 | hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? | |
3398 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
3399 | ||
3400 | hw->enable_fbc_wm = | |
3401 | !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); | |
3402 | } | |
3403 | ||
3404 | /** | |
3405 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
3406 | * | |
3407 | * Calculate watermark values for the various WM regs based on current mode | |
3408 | * and plane configuration. | |
3409 | * | |
3410 | * There are several cases to deal with here: | |
3411 | * - normal (i.e. non-self-refresh) | |
3412 | * - self-refresh (SR) mode | |
3413 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
3414 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
3415 | * lines), so need to account for TLB latency | |
3416 | * | |
3417 | * The normal calculation is: | |
3418 | * watermark = dotclock * bytes per pixel * latency | |
3419 | * where latency is platform & configuration dependent (we assume pessimal | |
3420 | * values here). | |
3421 | * | |
3422 | * The SR calculation is: | |
3423 | * watermark = (trunc(latency/line time)+1) * surface width * | |
3424 | * bytes per pixel | |
3425 | * where | |
3426 | * line time = htotal / dotclock | |
3427 | * surface width = hdisplay for normal plane and 64 for cursor | |
3428 | * and latency is assumed to be high, as above. | |
3429 | * | |
3430 | * The final value programmed to the register should always be rounded up, | |
3431 | * and include an extra 2 entries to account for clock crossings. | |
3432 | * | |
3433 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
3434 | * to set the non-SR watermarks to 8. | |
3435 | */ | |
3436 | void intel_update_watermarks(struct drm_crtc *crtc) | |
3437 | { | |
3438 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
3439 | ||
3440 | if (dev_priv->display.update_wm) | |
3441 | dev_priv->display.update_wm(crtc); | |
3442 | } | |
3443 | ||
3444 | void intel_update_sprite_watermarks(struct drm_plane *plane, | |
3445 | struct drm_crtc *crtc, | |
3446 | uint32_t sprite_width, | |
3447 | uint32_t sprite_height, | |
3448 | int pixel_size, | |
3449 | bool enabled, bool scaled) | |
3450 | { | |
3451 | struct drm_i915_private *dev_priv = plane->dev->dev_private; | |
3452 | ||
3453 | if (dev_priv->display.update_sprite_wm) | |
3454 | dev_priv->display.update_sprite_wm(plane, crtc, | |
3455 | sprite_width, sprite_height, | |
3456 | pixel_size, enabled, scaled); | |
3457 | } | |
3458 | ||
3459 | static struct drm_i915_gem_object * | |
3460 | intel_alloc_context_page(struct drm_device *dev) | |
3461 | { | |
3462 | struct drm_i915_gem_object *ctx; | |
3463 | int ret; | |
3464 | ||
3465 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
3466 | ||
3467 | ctx = i915_gem_alloc_object(dev, 4096); | |
3468 | if (!ctx) { | |
3469 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); | |
3470 | return NULL; | |
3471 | } | |
3472 | ||
3473 | ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0); | |
3474 | if (ret) { | |
3475 | DRM_ERROR("failed to pin power context: %d\n", ret); | |
3476 | goto err_unref; | |
3477 | } | |
3478 | ||
3479 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); | |
3480 | if (ret) { | |
3481 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); | |
3482 | goto err_unpin; | |
3483 | } | |
3484 | ||
3485 | return ctx; | |
3486 | ||
3487 | err_unpin: | |
3488 | i915_gem_object_ggtt_unpin(ctx); | |
3489 | err_unref: | |
3490 | drm_gem_object_unreference(&ctx->base); | |
3491 | return NULL; | |
3492 | } | |
3493 | ||
3494 | /** | |
3495 | * Lock protecting IPS related data structures | |
3496 | */ | |
3497 | DEFINE_SPINLOCK(mchdev_lock); | |
3498 | ||
3499 | /* Global for IPS driver to get at the current i915 device. Protected by | |
3500 | * mchdev_lock. */ | |
3501 | static struct drm_i915_private *i915_mch_dev; | |
3502 | ||
3503 | bool ironlake_set_drps(struct drm_device *dev, u8 val) | |
3504 | { | |
3505 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3506 | u16 rgvswctl; | |
3507 | ||
3508 | assert_spin_locked(&mchdev_lock); | |
3509 | ||
3510 | rgvswctl = I915_READ16(MEMSWCTL); | |
3511 | if (rgvswctl & MEMCTL_CMD_STS) { | |
3512 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
3513 | return false; /* still busy with another command */ | |
3514 | } | |
3515 | ||
3516 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
3517 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
3518 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
3519 | POSTING_READ16(MEMSWCTL); | |
3520 | ||
3521 | rgvswctl |= MEMCTL_CMD_STS; | |
3522 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
3523 | ||
3524 | return true; | |
3525 | } | |
3526 | ||
3527 | static void ironlake_enable_drps(struct drm_device *dev) | |
3528 | { | |
3529 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3530 | u32 rgvmodectl = I915_READ(MEMMODECTL); | |
3531 | u8 fmax, fmin, fstart, vstart; | |
3532 | ||
3533 | spin_lock_irq(&mchdev_lock); | |
3534 | ||
3535 | /* Enable temp reporting */ | |
3536 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
3537 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
3538 | ||
3539 | /* 100ms RC evaluation intervals */ | |
3540 | I915_WRITE(RCUPEI, 100000); | |
3541 | I915_WRITE(RCDNEI, 100000); | |
3542 | ||
3543 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
3544 | I915_WRITE(RCBMAXAVG, 90000); | |
3545 | I915_WRITE(RCBMINAVG, 80000); | |
3546 | ||
3547 | I915_WRITE(MEMIHYST, 1); | |
3548 | ||
3549 | /* Set up min, max, and cur for interrupt handling */ | |
3550 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
3551 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
3552 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
3553 | MEMMODE_FSTART_SHIFT; | |
3554 | ||
3555 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> | |
3556 | PXVFREQ_PX_SHIFT; | |
3557 | ||
3558 | dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ | |
3559 | dev_priv->ips.fstart = fstart; | |
3560 | ||
3561 | dev_priv->ips.max_delay = fstart; | |
3562 | dev_priv->ips.min_delay = fmin; | |
3563 | dev_priv->ips.cur_delay = fstart; | |
3564 | ||
3565 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", | |
3566 | fmax, fmin, fstart); | |
3567 | ||
3568 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); | |
3569 | ||
3570 | /* | |
3571 | * Interrupts will be enabled in ironlake_irq_postinstall | |
3572 | */ | |
3573 | ||
3574 | I915_WRITE(VIDSTART, vstart); | |
3575 | POSTING_READ(VIDSTART); | |
3576 | ||
3577 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
3578 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
3579 | ||
3580 | if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) | |
3581 | DRM_ERROR("stuck trying to change perf mode\n"); | |
3582 | mdelay(1); | |
3583 | ||
3584 | ironlake_set_drps(dev, fstart); | |
3585 | ||
3586 | dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + | |
3587 | I915_READ(0x112e0); | |
3588 | dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); | |
3589 | dev_priv->ips.last_count2 = I915_READ(0x112f4); | |
3590 | dev_priv->ips.last_time2 = ktime_get_raw_ns(); | |
3591 | ||
3592 | spin_unlock_irq(&mchdev_lock); | |
3593 | } | |
3594 | ||
3595 | static void ironlake_disable_drps(struct drm_device *dev) | |
3596 | { | |
3597 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3598 | u16 rgvswctl; | |
3599 | ||
3600 | spin_lock_irq(&mchdev_lock); | |
3601 | ||
3602 | rgvswctl = I915_READ16(MEMSWCTL); | |
3603 | ||
3604 | /* Ack interrupts, disable EFC interrupt */ | |
3605 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
3606 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
3607 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
3608 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
3609 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
3610 | ||
3611 | /* Go back to the starting frequency */ | |
3612 | ironlake_set_drps(dev, dev_priv->ips.fstart); | |
3613 | mdelay(1); | |
3614 | rgvswctl |= MEMCTL_CMD_STS; | |
3615 | I915_WRITE(MEMSWCTL, rgvswctl); | |
3616 | mdelay(1); | |
3617 | ||
3618 | spin_unlock_irq(&mchdev_lock); | |
3619 | } | |
3620 | ||
3621 | /* There's a funny hw issue where the hw returns all 0 when reading from | |
3622 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value | |
3623 | * ourselves, instead of doing a rmw cycle (which might result in us clearing | |
3624 | * all limits and the gpu stuck at whatever frequency it is at atm). | |
3625 | */ | |
3626 | static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val) | |
3627 | { | |
3628 | u32 limits; | |
3629 | ||
3630 | /* Only set the down limit when we've reached the lowest level to avoid | |
3631 | * getting more interrupts, otherwise leave this clear. This prevents a | |
3632 | * race in the hw when coming out of rc6: There's a tiny window where | |
3633 | * the hw runs at the minimal clock before selecting the desired | |
3634 | * frequency, if the down threshold expires in that window we will not | |
3635 | * receive a down interrupt. */ | |
3636 | limits = dev_priv->rps.max_freq_softlimit << 24; | |
3637 | if (val <= dev_priv->rps.min_freq_softlimit) | |
3638 | limits |= dev_priv->rps.min_freq_softlimit << 16; | |
3639 | ||
3640 | return limits; | |
3641 | } | |
3642 | ||
3643 | static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) | |
3644 | { | |
3645 | int new_power; | |
3646 | ||
3647 | new_power = dev_priv->rps.power; | |
3648 | switch (dev_priv->rps.power) { | |
3649 | case LOW_POWER: | |
3650 | if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) | |
3651 | new_power = BETWEEN; | |
3652 | break; | |
3653 | ||
3654 | case BETWEEN: | |
3655 | if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) | |
3656 | new_power = LOW_POWER; | |
3657 | else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) | |
3658 | new_power = HIGH_POWER; | |
3659 | break; | |
3660 | ||
3661 | case HIGH_POWER: | |
3662 | if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) | |
3663 | new_power = BETWEEN; | |
3664 | break; | |
3665 | } | |
3666 | /* Max/min bins are special */ | |
3667 | if (val == dev_priv->rps.min_freq_softlimit) | |
3668 | new_power = LOW_POWER; | |
3669 | if (val == dev_priv->rps.max_freq_softlimit) | |
3670 | new_power = HIGH_POWER; | |
3671 | if (new_power == dev_priv->rps.power) | |
3672 | return; | |
3673 | ||
3674 | /* Note the units here are not exactly 1us, but 1280ns. */ | |
3675 | switch (new_power) { | |
3676 | case LOW_POWER: | |
3677 | /* Upclock if more than 95% busy over 16ms */ | |
3678 | I915_WRITE(GEN6_RP_UP_EI, 12500); | |
3679 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800); | |
3680 | ||
3681 | /* Downclock if less than 85% busy over 32ms */ | |
3682 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); | |
3683 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250); | |
3684 | ||
3685 | I915_WRITE(GEN6_RP_CONTROL, | |
3686 | GEN6_RP_MEDIA_TURBO | | |
3687 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
3688 | GEN6_RP_MEDIA_IS_GFX | | |
3689 | GEN6_RP_ENABLE | | |
3690 | GEN6_RP_UP_BUSY_AVG | | |
3691 | GEN6_RP_DOWN_IDLE_AVG); | |
3692 | break; | |
3693 | ||
3694 | case BETWEEN: | |
3695 | /* Upclock if more than 90% busy over 13ms */ | |
3696 | I915_WRITE(GEN6_RP_UP_EI, 10250); | |
3697 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225); | |
3698 | ||
3699 | /* Downclock if less than 75% busy over 32ms */ | |
3700 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); | |
3701 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750); | |
3702 | ||
3703 | I915_WRITE(GEN6_RP_CONTROL, | |
3704 | GEN6_RP_MEDIA_TURBO | | |
3705 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
3706 | GEN6_RP_MEDIA_IS_GFX | | |
3707 | GEN6_RP_ENABLE | | |
3708 | GEN6_RP_UP_BUSY_AVG | | |
3709 | GEN6_RP_DOWN_IDLE_AVG); | |
3710 | break; | |
3711 | ||
3712 | case HIGH_POWER: | |
3713 | /* Upclock if more than 85% busy over 10ms */ | |
3714 | I915_WRITE(GEN6_RP_UP_EI, 8000); | |
3715 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800); | |
3716 | ||
3717 | /* Downclock if less than 60% busy over 32ms */ | |
3718 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); | |
3719 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000); | |
3720 | ||
3721 | I915_WRITE(GEN6_RP_CONTROL, | |
3722 | GEN6_RP_MEDIA_TURBO | | |
3723 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
3724 | GEN6_RP_MEDIA_IS_GFX | | |
3725 | GEN6_RP_ENABLE | | |
3726 | GEN6_RP_UP_BUSY_AVG | | |
3727 | GEN6_RP_DOWN_IDLE_AVG); | |
3728 | break; | |
3729 | } | |
3730 | ||
3731 | dev_priv->rps.power = new_power; | |
3732 | dev_priv->rps.last_adj = 0; | |
3733 | } | |
3734 | ||
3735 | static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) | |
3736 | { | |
3737 | u32 mask = 0; | |
3738 | ||
3739 | if (val > dev_priv->rps.min_freq_softlimit) | |
3740 | mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; | |
3741 | if (val < dev_priv->rps.max_freq_softlimit) | |
3742 | mask |= GEN6_PM_RP_UP_THRESHOLD; | |
3743 | ||
3744 | mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED); | |
3745 | mask &= dev_priv->pm_rps_events; | |
3746 | ||
3747 | return gen6_sanitize_rps_pm_mask(dev_priv, ~mask); | |
3748 | } | |
3749 | ||
3750 | /* gen6_set_rps is called to update the frequency request, but should also be | |
3751 | * called when the range (min_delay and max_delay) is modified so that we can | |
3752 | * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ | |
3753 | void gen6_set_rps(struct drm_device *dev, u8 val) | |
3754 | { | |
3755 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3756 | ||
3757 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
3758 | WARN_ON(val > dev_priv->rps.max_freq_softlimit); | |
3759 | WARN_ON(val < dev_priv->rps.min_freq_softlimit); | |
3760 | ||
3761 | /* min/max delay may still have been modified so be sure to | |
3762 | * write the limits value. | |
3763 | */ | |
3764 | if (val != dev_priv->rps.cur_freq) { | |
3765 | gen6_set_rps_thresholds(dev_priv, val); | |
3766 | ||
3767 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
3768 | I915_WRITE(GEN6_RPNSWREQ, | |
3769 | HSW_FREQUENCY(val)); | |
3770 | else | |
3771 | I915_WRITE(GEN6_RPNSWREQ, | |
3772 | GEN6_FREQUENCY(val) | | |
3773 | GEN6_OFFSET(0) | | |
3774 | GEN6_AGGRESSIVE_TURBO); | |
3775 | } | |
3776 | ||
3777 | /* Make sure we continue to get interrupts | |
3778 | * until we hit the minimum or maximum frequencies. | |
3779 | */ | |
3780 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val)); | |
3781 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); | |
3782 | ||
3783 | POSTING_READ(GEN6_RPNSWREQ); | |
3784 | ||
3785 | dev_priv->rps.cur_freq = val; | |
3786 | trace_intel_gpu_freq_change(val * 50); | |
3787 | } | |
3788 | ||
3789 | /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down | |
3790 | * | |
3791 | * * If Gfx is Idle, then | |
3792 | * 1. Mask Turbo interrupts | |
3793 | * 2. Bring up Gfx clock | |
3794 | * 3. Change the freq to Rpn and wait till P-Unit updates freq | |
3795 | * 4. Clear the Force GFX CLK ON bit so that Gfx can down | |
3796 | * 5. Unmask Turbo interrupts | |
3797 | */ | |
3798 | static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) | |
3799 | { | |
3800 | struct drm_device *dev = dev_priv->dev; | |
3801 | ||
3802 | /* Latest VLV doesn't need to force the gfx clock */ | |
3803 | if (dev->pdev->revision >= 0xd) { | |
3804 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); | |
3805 | return; | |
3806 | } | |
3807 | ||
3808 | /* | |
3809 | * When we are idle. Drop to min voltage state. | |
3810 | */ | |
3811 | ||
3812 | if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit) | |
3813 | return; | |
3814 | ||
3815 | /* Mask turbo interrupt so that they will not come in between */ | |
3816 | I915_WRITE(GEN6_PMINTRMSK, | |
3817 | gen6_sanitize_rps_pm_mask(dev_priv, ~0)); | |
3818 | ||
3819 | vlv_force_gfx_clock(dev_priv, true); | |
3820 | ||
3821 | dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit; | |
3822 | ||
3823 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, | |
3824 | dev_priv->rps.min_freq_softlimit); | |
3825 | ||
3826 | if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) | |
3827 | & GENFREQSTATUS) == 0, 100)) | |
3828 | DRM_ERROR("timed out waiting for Punit\n"); | |
3829 | ||
3830 | vlv_force_gfx_clock(dev_priv, false); | |
3831 | ||
3832 | I915_WRITE(GEN6_PMINTRMSK, | |
3833 | gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); | |
3834 | } | |
3835 | ||
3836 | void gen6_rps_idle(struct drm_i915_private *dev_priv) | |
3837 | { | |
3838 | struct drm_device *dev = dev_priv->dev; | |
3839 | ||
3840 | mutex_lock(&dev_priv->rps.hw_lock); | |
3841 | if (dev_priv->rps.enabled) { | |
3842 | if (IS_CHERRYVIEW(dev)) | |
3843 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); | |
3844 | else if (IS_VALLEYVIEW(dev)) | |
3845 | vlv_set_rps_idle(dev_priv); | |
3846 | else | |
3847 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); | |
3848 | dev_priv->rps.last_adj = 0; | |
3849 | } | |
3850 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3851 | } | |
3852 | ||
3853 | void gen6_rps_boost(struct drm_i915_private *dev_priv) | |
3854 | { | |
3855 | struct drm_device *dev = dev_priv->dev; | |
3856 | ||
3857 | mutex_lock(&dev_priv->rps.hw_lock); | |
3858 | if (dev_priv->rps.enabled) { | |
3859 | if (IS_VALLEYVIEW(dev)) | |
3860 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit); | |
3861 | else | |
3862 | gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit); | |
3863 | dev_priv->rps.last_adj = 0; | |
3864 | } | |
3865 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3866 | } | |
3867 | ||
3868 | void valleyview_set_rps(struct drm_device *dev, u8 val) | |
3869 | { | |
3870 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3871 | ||
3872 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
3873 | WARN_ON(val > dev_priv->rps.max_freq_softlimit); | |
3874 | WARN_ON(val < dev_priv->rps.min_freq_softlimit); | |
3875 | ||
3876 | if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1), | |
3877 | "Odd GPU freq value\n")) | |
3878 | val &= ~1; | |
3879 | ||
3880 | if (val != dev_priv->rps.cur_freq) | |
3881 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); | |
3882 | ||
3883 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); | |
3884 | ||
3885 | dev_priv->rps.cur_freq = val; | |
3886 | trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val)); | |
3887 | } | |
3888 | ||
3889 | static void gen9_disable_rps(struct drm_device *dev) | |
3890 | { | |
3891 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3892 | ||
3893 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
3894 | I915_WRITE(GEN9_PG_ENABLE, 0); | |
3895 | } | |
3896 | ||
3897 | static void gen6_disable_rps(struct drm_device *dev) | |
3898 | { | |
3899 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3900 | ||
3901 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
3902 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); | |
3903 | } | |
3904 | ||
3905 | static void cherryview_disable_rps(struct drm_device *dev) | |
3906 | { | |
3907 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3908 | ||
3909 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
3910 | } | |
3911 | ||
3912 | static void valleyview_disable_rps(struct drm_device *dev) | |
3913 | { | |
3914 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3915 | ||
3916 | /* we're doing forcewake before Disabling RC6, | |
3917 | * This what the BIOS expects when going into suspend */ | |
3918 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
3919 | ||
3920 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
3921 | ||
3922 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
3923 | } | |
3924 | ||
3925 | static void intel_print_rc6_info(struct drm_device *dev, u32 mode) | |
3926 | { | |
3927 | if (IS_VALLEYVIEW(dev)) { | |
3928 | if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) | |
3929 | mode = GEN6_RC_CTL_RC6_ENABLE; | |
3930 | else | |
3931 | mode = 0; | |
3932 | } | |
3933 | if (HAS_RC6p(dev)) | |
3934 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n", | |
3935 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", | |
3936 | (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", | |
3937 | (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); | |
3938 | ||
3939 | else | |
3940 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n", | |
3941 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off"); | |
3942 | } | |
3943 | ||
3944 | static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6) | |
3945 | { | |
3946 | /* No RC6 before Ironlake */ | |
3947 | if (INTEL_INFO(dev)->gen < 5) | |
3948 | return 0; | |
3949 | ||
3950 | /* RC6 is only on Ironlake mobile not on desktop */ | |
3951 | if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev)) | |
3952 | return 0; | |
3953 | ||
3954 | /* Respect the kernel parameter if it is set */ | |
3955 | if (enable_rc6 >= 0) { | |
3956 | int mask; | |
3957 | ||
3958 | if (HAS_RC6p(dev)) | |
3959 | mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | | |
3960 | INTEL_RC6pp_ENABLE; | |
3961 | else | |
3962 | mask = INTEL_RC6_ENABLE; | |
3963 | ||
3964 | if ((enable_rc6 & mask) != enable_rc6) | |
3965 | DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n", | |
3966 | enable_rc6 & mask, enable_rc6, mask); | |
3967 | ||
3968 | return enable_rc6 & mask; | |
3969 | } | |
3970 | ||
3971 | /* Disable RC6 on Ironlake */ | |
3972 | if (INTEL_INFO(dev)->gen == 5) | |
3973 | return 0; | |
3974 | ||
3975 | if (IS_IVYBRIDGE(dev)) | |
3976 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); | |
3977 | ||
3978 | return INTEL_RC6_ENABLE; | |
3979 | } | |
3980 | ||
3981 | int intel_enable_rc6(const struct drm_device *dev) | |
3982 | { | |
3983 | return i915.enable_rc6; | |
3984 | } | |
3985 | ||
3986 | static void gen6_init_rps_frequencies(struct drm_device *dev) | |
3987 | { | |
3988 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3989 | uint32_t rp_state_cap; | |
3990 | u32 ddcc_status = 0; | |
3991 | int ret; | |
3992 | ||
3993 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
3994 | /* All of these values are in units of 50MHz */ | |
3995 | dev_priv->rps.cur_freq = 0; | |
3996 | /* static values from HW: RP0 > RP1 > RPn (min_freq) */ | |
3997 | dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; | |
3998 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; | |
3999 | dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; | |
4000 | /* hw_max = RP0 until we check for overclocking */ | |
4001 | dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; | |
4002 | ||
4003 | dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; | |
4004 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
4005 | ret = sandybridge_pcode_read(dev_priv, | |
4006 | HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, | |
4007 | &ddcc_status); | |
4008 | if (0 == ret) | |
4009 | dev_priv->rps.efficient_freq = | |
4010 | (ddcc_status >> 8) & 0xff; | |
4011 | } | |
4012 | ||
4013 | /* Preserve min/max settings in case of re-init */ | |
4014 | if (dev_priv->rps.max_freq_softlimit == 0) | |
4015 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
4016 | ||
4017 | if (dev_priv->rps.min_freq_softlimit == 0) { | |
4018 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
4019 | dev_priv->rps.min_freq_softlimit = | |
4020 | /* max(RPe, 450 MHz) */ | |
4021 | max(dev_priv->rps.efficient_freq, (u8) 9); | |
4022 | else | |
4023 | dev_priv->rps.min_freq_softlimit = | |
4024 | dev_priv->rps.min_freq; | |
4025 | } | |
4026 | } | |
4027 | ||
4028 | /* See the Gen9_GT_PM_Programming_Guide doc for the below */ | |
4029 | static void gen9_enable_rps(struct drm_device *dev) | |
4030 | { | |
4031 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4032 | ||
4033 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4034 | ||
4035 | gen6_init_rps_frequencies(dev); | |
4036 | ||
4037 | I915_WRITE(GEN6_RPNSWREQ, 0xc800000); | |
4038 | I915_WRITE(GEN6_RC_VIDEO_FREQ, 0xc800000); | |
4039 | ||
4040 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240); | |
4041 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 0x12060000); | |
4042 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 0xe808); | |
4043 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 0x3bd08); | |
4044 | I915_WRITE(GEN6_RP_UP_EI, 0x101d0); | |
4045 | I915_WRITE(GEN6_RP_DOWN_EI, 0x55730); | |
4046 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); | |
4047 | I915_WRITE(GEN6_PMINTRMSK, 0x6); | |
4048 | I915_WRITE(GEN6_RP_CONTROL, GEN6_RP_MEDIA_TURBO | | |
4049 | GEN6_RP_MEDIA_HW_MODE | GEN6_RP_MEDIA_IS_GFX | | |
4050 | GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG | | |
4051 | GEN6_RP_DOWN_IDLE_AVG); | |
4052 | ||
4053 | gen6_enable_rps_interrupts(dev); | |
4054 | ||
4055 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
4056 | } | |
4057 | ||
4058 | static void gen9_enable_rc6(struct drm_device *dev) | |
4059 | { | |
4060 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4061 | struct intel_engine_cs *ring; | |
4062 | uint32_t rc6_mask = 0; | |
4063 | int unused; | |
4064 | ||
4065 | /* 1a: Software RC state - RC0 */ | |
4066 | I915_WRITE(GEN6_RC_STATE, 0); | |
4067 | ||
4068 | /* 1b: Get forcewake during program sequence. Although the driver | |
4069 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
4070 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4071 | ||
4072 | /* 2a: Disable RC states. */ | |
4073 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4074 | ||
4075 | /* 2b: Program RC6 thresholds.*/ | |
4076 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); | |
4077 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
4078 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
4079 | for_each_ring(ring, dev_priv, unused) | |
4080 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
4081 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
4082 | I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ | |
4083 | ||
4084 | /* 2c: Program Coarse Power Gating Policies. */ | |
4085 | I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25); | |
4086 | I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); | |
4087 | ||
4088 | /* 3a: Enable RC6 */ | |
4089 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) | |
4090 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; | |
4091 | DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? | |
4092 | "on" : "off"); | |
4093 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | | |
4094 | GEN6_RC_CTL_EI_MODE(1) | | |
4095 | rc6_mask); | |
4096 | ||
4097 | /* 3b: Enable Coarse Power Gating only when RC6 is enabled */ | |
4098 | I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 3 : 0); | |
4099 | ||
4100 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
4101 | ||
4102 | } | |
4103 | ||
4104 | static void gen8_enable_rps(struct drm_device *dev) | |
4105 | { | |
4106 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4107 | struct intel_engine_cs *ring; | |
4108 | uint32_t rc6_mask = 0; | |
4109 | int unused; | |
4110 | ||
4111 | /* 1a: Software RC state - RC0 */ | |
4112 | I915_WRITE(GEN6_RC_STATE, 0); | |
4113 | ||
4114 | /* 1c & 1d: Get forcewake during program sequence. Although the driver | |
4115 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
4116 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4117 | ||
4118 | /* 2a: Disable RC states. */ | |
4119 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4120 | ||
4121 | /* Initialize rps frequencies */ | |
4122 | gen6_init_rps_frequencies(dev); | |
4123 | ||
4124 | /* 2b: Program RC6 thresholds.*/ | |
4125 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
4126 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
4127 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
4128 | for_each_ring(ring, dev_priv, unused) | |
4129 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
4130 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
4131 | if (IS_BROADWELL(dev)) | |
4132 | I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ | |
4133 | else | |
4134 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ | |
4135 | ||
4136 | /* 3: Enable RC6 */ | |
4137 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) | |
4138 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; | |
4139 | intel_print_rc6_info(dev, rc6_mask); | |
4140 | if (IS_BROADWELL(dev)) | |
4141 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | | |
4142 | GEN7_RC_CTL_TO_MODE | | |
4143 | rc6_mask); | |
4144 | else | |
4145 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | | |
4146 | GEN6_RC_CTL_EI_MODE(1) | | |
4147 | rc6_mask); | |
4148 | ||
4149 | /* 4 Program defaults and thresholds for RPS*/ | |
4150 | I915_WRITE(GEN6_RPNSWREQ, | |
4151 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); | |
4152 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
4153 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); | |
4154 | /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ | |
4155 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ | |
4156 | ||
4157 | /* Docs recommend 900MHz, and 300 MHz respectively */ | |
4158 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
4159 | dev_priv->rps.max_freq_softlimit << 24 | | |
4160 | dev_priv->rps.min_freq_softlimit << 16); | |
4161 | ||
4162 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ | |
4163 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ | |
4164 | I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ | |
4165 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ | |
4166 | ||
4167 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
4168 | ||
4169 | /* 5: Enable RPS */ | |
4170 | I915_WRITE(GEN6_RP_CONTROL, | |
4171 | GEN6_RP_MEDIA_TURBO | | |
4172 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
4173 | GEN6_RP_MEDIA_IS_GFX | | |
4174 | GEN6_RP_ENABLE | | |
4175 | GEN6_RP_UP_BUSY_AVG | | |
4176 | GEN6_RP_DOWN_IDLE_AVG); | |
4177 | ||
4178 | /* 6: Ring frequency + overclocking (our driver does this later */ | |
4179 | ||
4180 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ | |
4181 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); | |
4182 | ||
4183 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
4184 | } | |
4185 | ||
4186 | static void gen6_enable_rps(struct drm_device *dev) | |
4187 | { | |
4188 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4189 | struct intel_engine_cs *ring; | |
4190 | u32 rc6vids, pcu_mbox = 0, rc6_mask = 0; | |
4191 | u32 gtfifodbg; | |
4192 | int rc6_mode; | |
4193 | int i, ret; | |
4194 | ||
4195 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
4196 | ||
4197 | /* Here begins a magic sequence of register writes to enable | |
4198 | * auto-downclocking. | |
4199 | * | |
4200 | * Perhaps there might be some value in exposing these to | |
4201 | * userspace... | |
4202 | */ | |
4203 | I915_WRITE(GEN6_RC_STATE, 0); | |
4204 | ||
4205 | /* Clear the DBG now so we don't confuse earlier errors */ | |
4206 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { | |
4207 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); | |
4208 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
4209 | } | |
4210 | ||
4211 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4212 | ||
4213 | /* Initialize rps frequencies */ | |
4214 | gen6_init_rps_frequencies(dev); | |
4215 | ||
4216 | /* disable the counters and set deterministic thresholds */ | |
4217 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4218 | ||
4219 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); | |
4220 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); | |
4221 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); | |
4222 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
4223 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
4224 | ||
4225 | for_each_ring(ring, dev_priv, i) | |
4226 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
4227 | ||
4228 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
4229 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); | |
4230 | if (IS_IVYBRIDGE(dev)) | |
4231 | I915_WRITE(GEN6_RC6_THRESHOLD, 125000); | |
4232 | else | |
4233 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); | |
4234 | I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); | |
4235 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ | |
4236 | ||
4237 | /* Check if we are enabling RC6 */ | |
4238 | rc6_mode = intel_enable_rc6(dev_priv->dev); | |
4239 | if (rc6_mode & INTEL_RC6_ENABLE) | |
4240 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; | |
4241 | ||
4242 | /* We don't use those on Haswell */ | |
4243 | if (!IS_HASWELL(dev)) { | |
4244 | if (rc6_mode & INTEL_RC6p_ENABLE) | |
4245 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; | |
4246 | ||
4247 | if (rc6_mode & INTEL_RC6pp_ENABLE) | |
4248 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; | |
4249 | } | |
4250 | ||
4251 | intel_print_rc6_info(dev, rc6_mask); | |
4252 | ||
4253 | I915_WRITE(GEN6_RC_CONTROL, | |
4254 | rc6_mask | | |
4255 | GEN6_RC_CTL_EI_MODE(1) | | |
4256 | GEN6_RC_CTL_HW_ENABLE); | |
4257 | ||
4258 | /* Power down if completely idle for over 50ms */ | |
4259 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); | |
4260 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
4261 | ||
4262 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); | |
4263 | if (ret) | |
4264 | DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); | |
4265 | ||
4266 | ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); | |
4267 | if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ | |
4268 | DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", | |
4269 | (dev_priv->rps.max_freq_softlimit & 0xff) * 50, | |
4270 | (pcu_mbox & 0xff) * 50); | |
4271 | dev_priv->rps.max_freq = pcu_mbox & 0xff; | |
4272 | } | |
4273 | ||
4274 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ | |
4275 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); | |
4276 | ||
4277 | rc6vids = 0; | |
4278 | ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
4279 | if (IS_GEN6(dev) && ret) { | |
4280 | DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); | |
4281 | } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { | |
4282 | DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", | |
4283 | GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); | |
4284 | rc6vids &= 0xffff00; | |
4285 | rc6vids |= GEN6_ENCODE_RC6_VID(450); | |
4286 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); | |
4287 | if (ret) | |
4288 | DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); | |
4289 | } | |
4290 | ||
4291 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
4292 | } | |
4293 | ||
4294 | static void __gen6_update_ring_freq(struct drm_device *dev) | |
4295 | { | |
4296 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4297 | int min_freq = 15; | |
4298 | unsigned int gpu_freq; | |
4299 | unsigned int max_ia_freq, min_ring_freq; | |
4300 | int scaling_factor = 180; | |
4301 | struct cpufreq_policy *policy; | |
4302 | ||
4303 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
4304 | ||
4305 | policy = cpufreq_cpu_get(0); | |
4306 | if (policy) { | |
4307 | max_ia_freq = policy->cpuinfo.max_freq; | |
4308 | cpufreq_cpu_put(policy); | |
4309 | } else { | |
4310 | /* | |
4311 | * Default to measured freq if none found, PCU will ensure we | |
4312 | * don't go over | |
4313 | */ | |
4314 | max_ia_freq = tsc_khz; | |
4315 | } | |
4316 | ||
4317 | /* Convert from kHz to MHz */ | |
4318 | max_ia_freq /= 1000; | |
4319 | ||
4320 | min_ring_freq = I915_READ(DCLK) & 0xf; | |
4321 | /* convert DDR frequency from units of 266.6MHz to bandwidth */ | |
4322 | min_ring_freq = mult_frac(min_ring_freq, 8, 3); | |
4323 | ||
4324 | /* | |
4325 | * For each potential GPU frequency, load a ring frequency we'd like | |
4326 | * to use for memory access. We do this by specifying the IA frequency | |
4327 | * the PCU should use as a reference to determine the ring frequency. | |
4328 | */ | |
4329 | for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq; | |
4330 | gpu_freq--) { | |
4331 | int diff = dev_priv->rps.max_freq - gpu_freq; | |
4332 | unsigned int ia_freq = 0, ring_freq = 0; | |
4333 | ||
4334 | if (INTEL_INFO(dev)->gen >= 8) { | |
4335 | /* max(2 * GT, DDR). NB: GT is 50MHz units */ | |
4336 | ring_freq = max(min_ring_freq, gpu_freq); | |
4337 | } else if (IS_HASWELL(dev)) { | |
4338 | ring_freq = mult_frac(gpu_freq, 5, 4); | |
4339 | ring_freq = max(min_ring_freq, ring_freq); | |
4340 | /* leave ia_freq as the default, chosen by cpufreq */ | |
4341 | } else { | |
4342 | /* On older processors, there is no separate ring | |
4343 | * clock domain, so in order to boost the bandwidth | |
4344 | * of the ring, we need to upclock the CPU (ia_freq). | |
4345 | * | |
4346 | * For GPU frequencies less than 750MHz, | |
4347 | * just use the lowest ring freq. | |
4348 | */ | |
4349 | if (gpu_freq < min_freq) | |
4350 | ia_freq = 800; | |
4351 | else | |
4352 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); | |
4353 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); | |
4354 | } | |
4355 | ||
4356 | sandybridge_pcode_write(dev_priv, | |
4357 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, | |
4358 | ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | | |
4359 | ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | | |
4360 | gpu_freq); | |
4361 | } | |
4362 | } | |
4363 | ||
4364 | void gen6_update_ring_freq(struct drm_device *dev) | |
4365 | { | |
4366 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4367 | ||
4368 | if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev)) | |
4369 | return; | |
4370 | ||
4371 | mutex_lock(&dev_priv->rps.hw_lock); | |
4372 | __gen6_update_ring_freq(dev); | |
4373 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4374 | } | |
4375 | ||
4376 | static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) | |
4377 | { | |
4378 | struct drm_device *dev = dev_priv->dev; | |
4379 | u32 val, rp0; | |
4380 | ||
4381 | if (dev->pdev->revision >= 0x20) { | |
4382 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); | |
4383 | ||
4384 | switch (INTEL_INFO(dev)->eu_total) { | |
4385 | case 8: | |
4386 | /* (2 * 4) config */ | |
4387 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT); | |
4388 | break; | |
4389 | case 12: | |
4390 | /* (2 * 6) config */ | |
4391 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT); | |
4392 | break; | |
4393 | case 16: | |
4394 | /* (2 * 8) config */ | |
4395 | default: | |
4396 | /* Setting (2 * 8) Min RP0 for any other combination */ | |
4397 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT); | |
4398 | break; | |
4399 | } | |
4400 | rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK); | |
4401 | } else { | |
4402 | /* For pre-production hardware */ | |
4403 | val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG); | |
4404 | rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & | |
4405 | PUNIT_GPU_STATUS_MAX_FREQ_MASK; | |
4406 | } | |
4407 | return rp0; | |
4408 | } | |
4409 | ||
4410 | static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
4411 | { | |
4412 | u32 val, rpe; | |
4413 | ||
4414 | val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); | |
4415 | rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; | |
4416 | ||
4417 | return rpe; | |
4418 | } | |
4419 | ||
4420 | static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) | |
4421 | { | |
4422 | struct drm_device *dev = dev_priv->dev; | |
4423 | u32 val, rp1; | |
4424 | ||
4425 | if (dev->pdev->revision >= 0x20) { | |
4426 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); | |
4427 | rp1 = (val & FB_GFX_FREQ_FUSE_MASK); | |
4428 | } else { | |
4429 | /* For pre-production hardware */ | |
4430 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
4431 | rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & | |
4432 | PUNIT_GPU_STATUS_MAX_FREQ_MASK); | |
4433 | } | |
4434 | return rp1; | |
4435 | } | |
4436 | ||
4437 | static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv) | |
4438 | { | |
4439 | struct drm_device *dev = dev_priv->dev; | |
4440 | u32 val, rpn; | |
4441 | ||
4442 | if (dev->pdev->revision >= 0x20) { | |
4443 | val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE); | |
4444 | rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) & | |
4445 | FB_GFX_FREQ_FUSE_MASK); | |
4446 | } else { /* For pre-production hardware */ | |
4447 | val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG); | |
4448 | rpn = ((val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & | |
4449 | PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK); | |
4450 | } | |
4451 | ||
4452 | return rpn; | |
4453 | } | |
4454 | ||
4455 | static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv) | |
4456 | { | |
4457 | u32 val, rp1; | |
4458 | ||
4459 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); | |
4460 | ||
4461 | rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; | |
4462 | ||
4463 | return rp1; | |
4464 | } | |
4465 | ||
4466 | static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) | |
4467 | { | |
4468 | u32 val, rp0; | |
4469 | ||
4470 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); | |
4471 | ||
4472 | rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; | |
4473 | /* Clamp to max */ | |
4474 | rp0 = min_t(u32, rp0, 0xea); | |
4475 | ||
4476 | return rp0; | |
4477 | } | |
4478 | ||
4479 | static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
4480 | { | |
4481 | u32 val, rpe; | |
4482 | ||
4483 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); | |
4484 | rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; | |
4485 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); | |
4486 | rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; | |
4487 | ||
4488 | return rpe; | |
4489 | } | |
4490 | ||
4491 | static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) | |
4492 | { | |
4493 | return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; | |
4494 | } | |
4495 | ||
4496 | /* Check that the pctx buffer wasn't move under us. */ | |
4497 | static void valleyview_check_pctx(struct drm_i915_private *dev_priv) | |
4498 | { | |
4499 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; | |
4500 | ||
4501 | WARN_ON(pctx_addr != dev_priv->mm.stolen_base + | |
4502 | dev_priv->vlv_pctx->stolen->start); | |
4503 | } | |
4504 | ||
4505 | ||
4506 | /* Check that the pcbr address is not empty. */ | |
4507 | static void cherryview_check_pctx(struct drm_i915_private *dev_priv) | |
4508 | { | |
4509 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; | |
4510 | ||
4511 | WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0); | |
4512 | } | |
4513 | ||
4514 | static void cherryview_setup_pctx(struct drm_device *dev) | |
4515 | { | |
4516 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4517 | unsigned long pctx_paddr, paddr; | |
4518 | struct i915_gtt *gtt = &dev_priv->gtt; | |
4519 | u32 pcbr; | |
4520 | int pctx_size = 32*1024; | |
4521 | ||
4522 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
4523 | ||
4524 | pcbr = I915_READ(VLV_PCBR); | |
4525 | if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { | |
4526 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); | |
4527 | paddr = (dev_priv->mm.stolen_base + | |
4528 | (gtt->stolen_size - pctx_size)); | |
4529 | ||
4530 | pctx_paddr = (paddr & (~4095)); | |
4531 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
4532 | } | |
4533 | ||
4534 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); | |
4535 | } | |
4536 | ||
4537 | static void valleyview_setup_pctx(struct drm_device *dev) | |
4538 | { | |
4539 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4540 | struct drm_i915_gem_object *pctx; | |
4541 | unsigned long pctx_paddr; | |
4542 | u32 pcbr; | |
4543 | int pctx_size = 24*1024; | |
4544 | ||
4545 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
4546 | ||
4547 | pcbr = I915_READ(VLV_PCBR); | |
4548 | if (pcbr) { | |
4549 | /* BIOS set it up already, grab the pre-alloc'd space */ | |
4550 | int pcbr_offset; | |
4551 | ||
4552 | pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; | |
4553 | pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev, | |
4554 | pcbr_offset, | |
4555 | I915_GTT_OFFSET_NONE, | |
4556 | pctx_size); | |
4557 | goto out; | |
4558 | } | |
4559 | ||
4560 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); | |
4561 | ||
4562 | /* | |
4563 | * From the Gunit register HAS: | |
4564 | * The Gfx driver is expected to program this register and ensure | |
4565 | * proper allocation within Gfx stolen memory. For example, this | |
4566 | * register should be programmed such than the PCBR range does not | |
4567 | * overlap with other ranges, such as the frame buffer, protected | |
4568 | * memory, or any other relevant ranges. | |
4569 | */ | |
4570 | pctx = i915_gem_object_create_stolen(dev, pctx_size); | |
4571 | if (!pctx) { | |
4572 | DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); | |
4573 | return; | |
4574 | } | |
4575 | ||
4576 | pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; | |
4577 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
4578 | ||
4579 | out: | |
4580 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); | |
4581 | dev_priv->vlv_pctx = pctx; | |
4582 | } | |
4583 | ||
4584 | static void valleyview_cleanup_pctx(struct drm_device *dev) | |
4585 | { | |
4586 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4587 | ||
4588 | if (WARN_ON(!dev_priv->vlv_pctx)) | |
4589 | return; | |
4590 | ||
4591 | drm_gem_object_unreference(&dev_priv->vlv_pctx->base); | |
4592 | dev_priv->vlv_pctx = NULL; | |
4593 | } | |
4594 | ||
4595 | static void valleyview_init_gt_powersave(struct drm_device *dev) | |
4596 | { | |
4597 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4598 | u32 val; | |
4599 | ||
4600 | valleyview_setup_pctx(dev); | |
4601 | ||
4602 | mutex_lock(&dev_priv->rps.hw_lock); | |
4603 | ||
4604 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
4605 | switch ((val >> 6) & 3) { | |
4606 | case 0: | |
4607 | case 1: | |
4608 | dev_priv->mem_freq = 800; | |
4609 | break; | |
4610 | case 2: | |
4611 | dev_priv->mem_freq = 1066; | |
4612 | break; | |
4613 | case 3: | |
4614 | dev_priv->mem_freq = 1333; | |
4615 | break; | |
4616 | } | |
4617 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); | |
4618 | ||
4619 | dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); | |
4620 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
4621 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", | |
4622 | vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq), | |
4623 | dev_priv->rps.max_freq); | |
4624 | ||
4625 | dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); | |
4626 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", | |
4627 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
4628 | dev_priv->rps.efficient_freq); | |
4629 | ||
4630 | dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); | |
4631 | DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n", | |
4632 | vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), | |
4633 | dev_priv->rps.rp1_freq); | |
4634 | ||
4635 | dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); | |
4636 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", | |
4637 | vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq), | |
4638 | dev_priv->rps.min_freq); | |
4639 | ||
4640 | /* Preserve min/max settings in case of re-init */ | |
4641 | if (dev_priv->rps.max_freq_softlimit == 0) | |
4642 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
4643 | ||
4644 | if (dev_priv->rps.min_freq_softlimit == 0) | |
4645 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; | |
4646 | ||
4647 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4648 | } | |
4649 | ||
4650 | static void cherryview_init_gt_powersave(struct drm_device *dev) | |
4651 | { | |
4652 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4653 | u32 val; | |
4654 | ||
4655 | cherryview_setup_pctx(dev); | |
4656 | ||
4657 | mutex_lock(&dev_priv->rps.hw_lock); | |
4658 | ||
4659 | mutex_lock(&dev_priv->dpio_lock); | |
4660 | val = vlv_cck_read(dev_priv, CCK_FUSE_REG); | |
4661 | mutex_unlock(&dev_priv->dpio_lock); | |
4662 | ||
4663 | switch ((val >> 2) & 0x7) { | |
4664 | case 0: | |
4665 | case 1: | |
4666 | dev_priv->rps.cz_freq = 200; | |
4667 | dev_priv->mem_freq = 1600; | |
4668 | break; | |
4669 | case 2: | |
4670 | dev_priv->rps.cz_freq = 267; | |
4671 | dev_priv->mem_freq = 1600; | |
4672 | break; | |
4673 | case 3: | |
4674 | dev_priv->rps.cz_freq = 333; | |
4675 | dev_priv->mem_freq = 2000; | |
4676 | break; | |
4677 | case 4: | |
4678 | dev_priv->rps.cz_freq = 320; | |
4679 | dev_priv->mem_freq = 1600; | |
4680 | break; | |
4681 | case 5: | |
4682 | dev_priv->rps.cz_freq = 400; | |
4683 | dev_priv->mem_freq = 1600; | |
4684 | break; | |
4685 | } | |
4686 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); | |
4687 | ||
4688 | dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); | |
4689 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
4690 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", | |
4691 | vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq), | |
4692 | dev_priv->rps.max_freq); | |
4693 | ||
4694 | dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); | |
4695 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", | |
4696 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
4697 | dev_priv->rps.efficient_freq); | |
4698 | ||
4699 | dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); | |
4700 | DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n", | |
4701 | vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), | |
4702 | dev_priv->rps.rp1_freq); | |
4703 | ||
4704 | dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv); | |
4705 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", | |
4706 | vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq), | |
4707 | dev_priv->rps.min_freq); | |
4708 | ||
4709 | WARN_ONCE((dev_priv->rps.max_freq | | |
4710 | dev_priv->rps.efficient_freq | | |
4711 | dev_priv->rps.rp1_freq | | |
4712 | dev_priv->rps.min_freq) & 1, | |
4713 | "Odd GPU freq values\n"); | |
4714 | ||
4715 | /* Preserve min/max settings in case of re-init */ | |
4716 | if (dev_priv->rps.max_freq_softlimit == 0) | |
4717 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
4718 | ||
4719 | if (dev_priv->rps.min_freq_softlimit == 0) | |
4720 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; | |
4721 | ||
4722 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4723 | } | |
4724 | ||
4725 | static void valleyview_cleanup_gt_powersave(struct drm_device *dev) | |
4726 | { | |
4727 | valleyview_cleanup_pctx(dev); | |
4728 | } | |
4729 | ||
4730 | static void cherryview_enable_rps(struct drm_device *dev) | |
4731 | { | |
4732 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4733 | struct intel_engine_cs *ring; | |
4734 | u32 gtfifodbg, val, rc6_mode = 0, pcbr; | |
4735 | int i; | |
4736 | ||
4737 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
4738 | ||
4739 | gtfifodbg = I915_READ(GTFIFODBG); | |
4740 | if (gtfifodbg) { | |
4741 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", | |
4742 | gtfifodbg); | |
4743 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
4744 | } | |
4745 | ||
4746 | cherryview_check_pctx(dev_priv); | |
4747 | ||
4748 | /* 1a & 1b: Get forcewake during program sequence. Although the driver | |
4749 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
4750 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4751 | ||
4752 | /* Disable RC states. */ | |
4753 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4754 | ||
4755 | /* 2a: Program RC6 thresholds.*/ | |
4756 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
4757 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
4758 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
4759 | ||
4760 | for_each_ring(ring, dev_priv, i) | |
4761 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
4762 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
4763 | ||
4764 | /* TO threshold set to 1750 us ( 0x557 * 1.28 us) */ | |
4765 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); | |
4766 | ||
4767 | /* allows RC6 residency counter to work */ | |
4768 | I915_WRITE(VLV_COUNTER_CONTROL, | |
4769 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | | |
4770 | VLV_MEDIA_RC6_COUNT_EN | | |
4771 | VLV_RENDER_RC6_COUNT_EN)); | |
4772 | ||
4773 | /* For now we assume BIOS is allocating and populating the PCBR */ | |
4774 | pcbr = I915_READ(VLV_PCBR); | |
4775 | ||
4776 | /* 3: Enable RC6 */ | |
4777 | if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) && | |
4778 | (pcbr >> VLV_PCBR_ADDR_SHIFT)) | |
4779 | rc6_mode = GEN7_RC_CTL_TO_MODE; | |
4780 | ||
4781 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); | |
4782 | ||
4783 | /* 4 Program defaults and thresholds for RPS*/ | |
4784 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); | |
4785 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); | |
4786 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
4787 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
4788 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
4789 | ||
4790 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
4791 | ||
4792 | /* 5: Enable RPS */ | |
4793 | I915_WRITE(GEN6_RP_CONTROL, | |
4794 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
4795 | GEN6_RP_MEDIA_IS_GFX | | |
4796 | GEN6_RP_ENABLE | | |
4797 | GEN6_RP_UP_BUSY_AVG | | |
4798 | GEN6_RP_DOWN_IDLE_AVG); | |
4799 | ||
4800 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
4801 | ||
4802 | /* RPS code assumes GPLL is used */ | |
4803 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); | |
4804 | ||
4805 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no"); | |
4806 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); | |
4807 | ||
4808 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; | |
4809 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", | |
4810 | vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq), | |
4811 | dev_priv->rps.cur_freq); | |
4812 | ||
4813 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", | |
4814 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
4815 | dev_priv->rps.efficient_freq); | |
4816 | ||
4817 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); | |
4818 | ||
4819 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
4820 | } | |
4821 | ||
4822 | static void valleyview_enable_rps(struct drm_device *dev) | |
4823 | { | |
4824 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4825 | struct intel_engine_cs *ring; | |
4826 | u32 gtfifodbg, val, rc6_mode = 0; | |
4827 | int i; | |
4828 | ||
4829 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
4830 | ||
4831 | valleyview_check_pctx(dev_priv); | |
4832 | ||
4833 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { | |
4834 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", | |
4835 | gtfifodbg); | |
4836 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
4837 | } | |
4838 | ||
4839 | /* If VLV, Forcewake all wells, else re-direct to regular path */ | |
4840 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4841 | ||
4842 | /* Disable RC states. */ | |
4843 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4844 | ||
4845 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); | |
4846 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); | |
4847 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
4848 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
4849 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
4850 | ||
4851 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
4852 | ||
4853 | I915_WRITE(GEN6_RP_CONTROL, | |
4854 | GEN6_RP_MEDIA_TURBO | | |
4855 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
4856 | GEN6_RP_MEDIA_IS_GFX | | |
4857 | GEN6_RP_ENABLE | | |
4858 | GEN6_RP_UP_BUSY_AVG | | |
4859 | GEN6_RP_DOWN_IDLE_CONT); | |
4860 | ||
4861 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); | |
4862 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
4863 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
4864 | ||
4865 | for_each_ring(ring, dev_priv, i) | |
4866 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
4867 | ||
4868 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); | |
4869 | ||
4870 | /* allows RC6 residency counter to work */ | |
4871 | I915_WRITE(VLV_COUNTER_CONTROL, | |
4872 | _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN | | |
4873 | VLV_RENDER_RC0_COUNT_EN | | |
4874 | VLV_MEDIA_RC6_COUNT_EN | | |
4875 | VLV_RENDER_RC6_COUNT_EN)); | |
4876 | ||
4877 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) | |
4878 | rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; | |
4879 | ||
4880 | intel_print_rc6_info(dev, rc6_mode); | |
4881 | ||
4882 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); | |
4883 | ||
4884 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
4885 | ||
4886 | /* RPS code assumes GPLL is used */ | |
4887 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); | |
4888 | ||
4889 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no"); | |
4890 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); | |
4891 | ||
4892 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; | |
4893 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", | |
4894 | vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq), | |
4895 | dev_priv->rps.cur_freq); | |
4896 | ||
4897 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", | |
4898 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
4899 | dev_priv->rps.efficient_freq); | |
4900 | ||
4901 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); | |
4902 | ||
4903 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
4904 | } | |
4905 | ||
4906 | void ironlake_teardown_rc6(struct drm_device *dev) | |
4907 | { | |
4908 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4909 | ||
4910 | if (dev_priv->ips.renderctx) { | |
4911 | i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx); | |
4912 | drm_gem_object_unreference(&dev_priv->ips.renderctx->base); | |
4913 | dev_priv->ips.renderctx = NULL; | |
4914 | } | |
4915 | ||
4916 | if (dev_priv->ips.pwrctx) { | |
4917 | i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx); | |
4918 | drm_gem_object_unreference(&dev_priv->ips.pwrctx->base); | |
4919 | dev_priv->ips.pwrctx = NULL; | |
4920 | } | |
4921 | } | |
4922 | ||
4923 | static void ironlake_disable_rc6(struct drm_device *dev) | |
4924 | { | |
4925 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4926 | ||
4927 | if (I915_READ(PWRCTXA)) { | |
4928 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ | |
4929 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); | |
4930 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), | |
4931 | 50); | |
4932 | ||
4933 | I915_WRITE(PWRCTXA, 0); | |
4934 | POSTING_READ(PWRCTXA); | |
4935 | ||
4936 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); | |
4937 | POSTING_READ(RSTDBYCTL); | |
4938 | } | |
4939 | } | |
4940 | ||
4941 | static int ironlake_setup_rc6(struct drm_device *dev) | |
4942 | { | |
4943 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4944 | ||
4945 | if (dev_priv->ips.renderctx == NULL) | |
4946 | dev_priv->ips.renderctx = intel_alloc_context_page(dev); | |
4947 | if (!dev_priv->ips.renderctx) | |
4948 | return -ENOMEM; | |
4949 | ||
4950 | if (dev_priv->ips.pwrctx == NULL) | |
4951 | dev_priv->ips.pwrctx = intel_alloc_context_page(dev); | |
4952 | if (!dev_priv->ips.pwrctx) { | |
4953 | ironlake_teardown_rc6(dev); | |
4954 | return -ENOMEM; | |
4955 | } | |
4956 | ||
4957 | return 0; | |
4958 | } | |
4959 | ||
4960 | static void ironlake_enable_rc6(struct drm_device *dev) | |
4961 | { | |
4962 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4963 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; | |
4964 | bool was_interruptible; | |
4965 | int ret; | |
4966 | ||
4967 | /* rc6 disabled by default due to repeated reports of hanging during | |
4968 | * boot and resume. | |
4969 | */ | |
4970 | if (!intel_enable_rc6(dev)) | |
4971 | return; | |
4972 | ||
4973 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
4974 | ||
4975 | ret = ironlake_setup_rc6(dev); | |
4976 | if (ret) | |
4977 | return; | |
4978 | ||
4979 | was_interruptible = dev_priv->mm.interruptible; | |
4980 | dev_priv->mm.interruptible = false; | |
4981 | ||
4982 | /* | |
4983 | * GPU can automatically power down the render unit if given a page | |
4984 | * to save state. | |
4985 | */ | |
4986 | ret = intel_ring_begin(ring, 6); | |
4987 | if (ret) { | |
4988 | ironlake_teardown_rc6(dev); | |
4989 | dev_priv->mm.interruptible = was_interruptible; | |
4990 | return; | |
4991 | } | |
4992 | ||
4993 | intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); | |
4994 | intel_ring_emit(ring, MI_SET_CONTEXT); | |
4995 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) | | |
4996 | MI_MM_SPACE_GTT | | |
4997 | MI_SAVE_EXT_STATE_EN | | |
4998 | MI_RESTORE_EXT_STATE_EN | | |
4999 | MI_RESTORE_INHIBIT); | |
5000 | intel_ring_emit(ring, MI_SUSPEND_FLUSH); | |
5001 | intel_ring_emit(ring, MI_NOOP); | |
5002 | intel_ring_emit(ring, MI_FLUSH); | |
5003 | intel_ring_advance(ring); | |
5004 | ||
5005 | /* | |
5006 | * Wait for the command parser to advance past MI_SET_CONTEXT. The HW | |
5007 | * does an implicit flush, combined with MI_FLUSH above, it should be | |
5008 | * safe to assume that renderctx is valid | |
5009 | */ | |
5010 | ret = intel_ring_idle(ring); | |
5011 | dev_priv->mm.interruptible = was_interruptible; | |
5012 | if (ret) { | |
5013 | DRM_ERROR("failed to enable ironlake power savings\n"); | |
5014 | ironlake_teardown_rc6(dev); | |
5015 | return; | |
5016 | } | |
5017 | ||
5018 | I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN); | |
5019 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); | |
5020 | ||
5021 | intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE); | |
5022 | } | |
5023 | ||
5024 | static unsigned long intel_pxfreq(u32 vidfreq) | |
5025 | { | |
5026 | unsigned long freq; | |
5027 | int div = (vidfreq & 0x3f0000) >> 16; | |
5028 | int post = (vidfreq & 0x3000) >> 12; | |
5029 | int pre = (vidfreq & 0x7); | |
5030 | ||
5031 | if (!pre) | |
5032 | return 0; | |
5033 | ||
5034 | freq = ((div * 133333) / ((1<<post) * pre)); | |
5035 | ||
5036 | return freq; | |
5037 | } | |
5038 | ||
5039 | static const struct cparams { | |
5040 | u16 i; | |
5041 | u16 t; | |
5042 | u16 m; | |
5043 | u16 c; | |
5044 | } cparams[] = { | |
5045 | { 1, 1333, 301, 28664 }, | |
5046 | { 1, 1066, 294, 24460 }, | |
5047 | { 1, 800, 294, 25192 }, | |
5048 | { 0, 1333, 276, 27605 }, | |
5049 | { 0, 1066, 276, 27605 }, | |
5050 | { 0, 800, 231, 23784 }, | |
5051 | }; | |
5052 | ||
5053 | static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) | |
5054 | { | |
5055 | u64 total_count, diff, ret; | |
5056 | u32 count1, count2, count3, m = 0, c = 0; | |
5057 | unsigned long now = jiffies_to_msecs(jiffies), diff1; | |
5058 | int i; | |
5059 | ||
5060 | assert_spin_locked(&mchdev_lock); | |
5061 | ||
5062 | diff1 = now - dev_priv->ips.last_time1; | |
5063 | ||
5064 | /* Prevent division-by-zero if we are asking too fast. | |
5065 | * Also, we don't get interesting results if we are polling | |
5066 | * faster than once in 10ms, so just return the saved value | |
5067 | * in such cases. | |
5068 | */ | |
5069 | if (diff1 <= 10) | |
5070 | return dev_priv->ips.chipset_power; | |
5071 | ||
5072 | count1 = I915_READ(DMIEC); | |
5073 | count2 = I915_READ(DDREC); | |
5074 | count3 = I915_READ(CSIEC); | |
5075 | ||
5076 | total_count = count1 + count2 + count3; | |
5077 | ||
5078 | /* FIXME: handle per-counter overflow */ | |
5079 | if (total_count < dev_priv->ips.last_count1) { | |
5080 | diff = ~0UL - dev_priv->ips.last_count1; | |
5081 | diff += total_count; | |
5082 | } else { | |
5083 | diff = total_count - dev_priv->ips.last_count1; | |
5084 | } | |
5085 | ||
5086 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { | |
5087 | if (cparams[i].i == dev_priv->ips.c_m && | |
5088 | cparams[i].t == dev_priv->ips.r_t) { | |
5089 | m = cparams[i].m; | |
5090 | c = cparams[i].c; | |
5091 | break; | |
5092 | } | |
5093 | } | |
5094 | ||
5095 | diff = div_u64(diff, diff1); | |
5096 | ret = ((m * diff) + c); | |
5097 | ret = div_u64(ret, 10); | |
5098 | ||
5099 | dev_priv->ips.last_count1 = total_count; | |
5100 | dev_priv->ips.last_time1 = now; | |
5101 | ||
5102 | dev_priv->ips.chipset_power = ret; | |
5103 | ||
5104 | return ret; | |
5105 | } | |
5106 | ||
5107 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) | |
5108 | { | |
5109 | struct drm_device *dev = dev_priv->dev; | |
5110 | unsigned long val; | |
5111 | ||
5112 | if (INTEL_INFO(dev)->gen != 5) | |
5113 | return 0; | |
5114 | ||
5115 | spin_lock_irq(&mchdev_lock); | |
5116 | ||
5117 | val = __i915_chipset_val(dev_priv); | |
5118 | ||
5119 | spin_unlock_irq(&mchdev_lock); | |
5120 | ||
5121 | return val; | |
5122 | } | |
5123 | ||
5124 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) | |
5125 | { | |
5126 | unsigned long m, x, b; | |
5127 | u32 tsfs; | |
5128 | ||
5129 | tsfs = I915_READ(TSFS); | |
5130 | ||
5131 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); | |
5132 | x = I915_READ8(TR1); | |
5133 | ||
5134 | b = tsfs & TSFS_INTR_MASK; | |
5135 | ||
5136 | return ((m * x) / 127) - b; | |
5137 | } | |
5138 | ||
5139 | static int _pxvid_to_vd(u8 pxvid) | |
5140 | { | |
5141 | if (pxvid == 0) | |
5142 | return 0; | |
5143 | ||
5144 | if (pxvid >= 8 && pxvid < 31) | |
5145 | pxvid = 31; | |
5146 | ||
5147 | return (pxvid + 2) * 125; | |
5148 | } | |
5149 | ||
5150 | static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) | |
5151 | { | |
5152 | struct drm_device *dev = dev_priv->dev; | |
5153 | const int vd = _pxvid_to_vd(pxvid); | |
5154 | const int vm = vd - 1125; | |
5155 | ||
5156 | if (INTEL_INFO(dev)->is_mobile) | |
5157 | return vm > 0 ? vm : 0; | |
5158 | ||
5159 | return vd; | |
5160 | } | |
5161 | ||
5162 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) | |
5163 | { | |
5164 | u64 now, diff, diffms; | |
5165 | u32 count; | |
5166 | ||
5167 | assert_spin_locked(&mchdev_lock); | |
5168 | ||
5169 | now = ktime_get_raw_ns(); | |
5170 | diffms = now - dev_priv->ips.last_time2; | |
5171 | do_div(diffms, NSEC_PER_MSEC); | |
5172 | ||
5173 | /* Don't divide by 0 */ | |
5174 | if (!diffms) | |
5175 | return; | |
5176 | ||
5177 | count = I915_READ(GFXEC); | |
5178 | ||
5179 | if (count < dev_priv->ips.last_count2) { | |
5180 | diff = ~0UL - dev_priv->ips.last_count2; | |
5181 | diff += count; | |
5182 | } else { | |
5183 | diff = count - dev_priv->ips.last_count2; | |
5184 | } | |
5185 | ||
5186 | dev_priv->ips.last_count2 = count; | |
5187 | dev_priv->ips.last_time2 = now; | |
5188 | ||
5189 | /* More magic constants... */ | |
5190 | diff = diff * 1181; | |
5191 | diff = div_u64(diff, diffms * 10); | |
5192 | dev_priv->ips.gfx_power = diff; | |
5193 | } | |
5194 | ||
5195 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) | |
5196 | { | |
5197 | struct drm_device *dev = dev_priv->dev; | |
5198 | ||
5199 | if (INTEL_INFO(dev)->gen != 5) | |
5200 | return; | |
5201 | ||
5202 | spin_lock_irq(&mchdev_lock); | |
5203 | ||
5204 | __i915_update_gfx_val(dev_priv); | |
5205 | ||
5206 | spin_unlock_irq(&mchdev_lock); | |
5207 | } | |
5208 | ||
5209 | static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) | |
5210 | { | |
5211 | unsigned long t, corr, state1, corr2, state2; | |
5212 | u32 pxvid, ext_v; | |
5213 | ||
5214 | assert_spin_locked(&mchdev_lock); | |
5215 | ||
5216 | pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4)); | |
5217 | pxvid = (pxvid >> 24) & 0x7f; | |
5218 | ext_v = pvid_to_extvid(dev_priv, pxvid); | |
5219 | ||
5220 | state1 = ext_v; | |
5221 | ||
5222 | t = i915_mch_val(dev_priv); | |
5223 | ||
5224 | /* Revel in the empirically derived constants */ | |
5225 | ||
5226 | /* Correction factor in 1/100000 units */ | |
5227 | if (t > 80) | |
5228 | corr = ((t * 2349) + 135940); | |
5229 | else if (t >= 50) | |
5230 | corr = ((t * 964) + 29317); | |
5231 | else /* < 50 */ | |
5232 | corr = ((t * 301) + 1004); | |
5233 | ||
5234 | corr = corr * ((150142 * state1) / 10000 - 78642); | |
5235 | corr /= 100000; | |
5236 | corr2 = (corr * dev_priv->ips.corr); | |
5237 | ||
5238 | state2 = (corr2 * state1) / 10000; | |
5239 | state2 /= 100; /* convert to mW */ | |
5240 | ||
5241 | __i915_update_gfx_val(dev_priv); | |
5242 | ||
5243 | return dev_priv->ips.gfx_power + state2; | |
5244 | } | |
5245 | ||
5246 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) | |
5247 | { | |
5248 | struct drm_device *dev = dev_priv->dev; | |
5249 | unsigned long val; | |
5250 | ||
5251 | if (INTEL_INFO(dev)->gen != 5) | |
5252 | return 0; | |
5253 | ||
5254 | spin_lock_irq(&mchdev_lock); | |
5255 | ||
5256 | val = __i915_gfx_val(dev_priv); | |
5257 | ||
5258 | spin_unlock_irq(&mchdev_lock); | |
5259 | ||
5260 | return val; | |
5261 | } | |
5262 | ||
5263 | /** | |
5264 | * i915_read_mch_val - return value for IPS use | |
5265 | * | |
5266 | * Calculate and return a value for the IPS driver to use when deciding whether | |
5267 | * we have thermal and power headroom to increase CPU or GPU power budget. | |
5268 | */ | |
5269 | unsigned long i915_read_mch_val(void) | |
5270 | { | |
5271 | struct drm_i915_private *dev_priv; | |
5272 | unsigned long chipset_val, graphics_val, ret = 0; | |
5273 | ||
5274 | spin_lock_irq(&mchdev_lock); | |
5275 | if (!i915_mch_dev) | |
5276 | goto out_unlock; | |
5277 | dev_priv = i915_mch_dev; | |
5278 | ||
5279 | chipset_val = __i915_chipset_val(dev_priv); | |
5280 | graphics_val = __i915_gfx_val(dev_priv); | |
5281 | ||
5282 | ret = chipset_val + graphics_val; | |
5283 | ||
5284 | out_unlock: | |
5285 | spin_unlock_irq(&mchdev_lock); | |
5286 | ||
5287 | return ret; | |
5288 | } | |
5289 | EXPORT_SYMBOL_GPL(i915_read_mch_val); | |
5290 | ||
5291 | /** | |
5292 | * i915_gpu_raise - raise GPU frequency limit | |
5293 | * | |
5294 | * Raise the limit; IPS indicates we have thermal headroom. | |
5295 | */ | |
5296 | bool i915_gpu_raise(void) | |
5297 | { | |
5298 | struct drm_i915_private *dev_priv; | |
5299 | bool ret = true; | |
5300 | ||
5301 | spin_lock_irq(&mchdev_lock); | |
5302 | if (!i915_mch_dev) { | |
5303 | ret = false; | |
5304 | goto out_unlock; | |
5305 | } | |
5306 | dev_priv = i915_mch_dev; | |
5307 | ||
5308 | if (dev_priv->ips.max_delay > dev_priv->ips.fmax) | |
5309 | dev_priv->ips.max_delay--; | |
5310 | ||
5311 | out_unlock: | |
5312 | spin_unlock_irq(&mchdev_lock); | |
5313 | ||
5314 | return ret; | |
5315 | } | |
5316 | EXPORT_SYMBOL_GPL(i915_gpu_raise); | |
5317 | ||
5318 | /** | |
5319 | * i915_gpu_lower - lower GPU frequency limit | |
5320 | * | |
5321 | * IPS indicates we're close to a thermal limit, so throttle back the GPU | |
5322 | * frequency maximum. | |
5323 | */ | |
5324 | bool i915_gpu_lower(void) | |
5325 | { | |
5326 | struct drm_i915_private *dev_priv; | |
5327 | bool ret = true; | |
5328 | ||
5329 | spin_lock_irq(&mchdev_lock); | |
5330 | if (!i915_mch_dev) { | |
5331 | ret = false; | |
5332 | goto out_unlock; | |
5333 | } | |
5334 | dev_priv = i915_mch_dev; | |
5335 | ||
5336 | if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) | |
5337 | dev_priv->ips.max_delay++; | |
5338 | ||
5339 | out_unlock: | |
5340 | spin_unlock_irq(&mchdev_lock); | |
5341 | ||
5342 | return ret; | |
5343 | } | |
5344 | EXPORT_SYMBOL_GPL(i915_gpu_lower); | |
5345 | ||
5346 | /** | |
5347 | * i915_gpu_busy - indicate GPU business to IPS | |
5348 | * | |
5349 | * Tell the IPS driver whether or not the GPU is busy. | |
5350 | */ | |
5351 | bool i915_gpu_busy(void) | |
5352 | { | |
5353 | struct drm_i915_private *dev_priv; | |
5354 | struct intel_engine_cs *ring; | |
5355 | bool ret = false; | |
5356 | int i; | |
5357 | ||
5358 | spin_lock_irq(&mchdev_lock); | |
5359 | if (!i915_mch_dev) | |
5360 | goto out_unlock; | |
5361 | dev_priv = i915_mch_dev; | |
5362 | ||
5363 | for_each_ring(ring, dev_priv, i) | |
5364 | ret |= !list_empty(&ring->request_list); | |
5365 | ||
5366 | out_unlock: | |
5367 | spin_unlock_irq(&mchdev_lock); | |
5368 | ||
5369 | return ret; | |
5370 | } | |
5371 | EXPORT_SYMBOL_GPL(i915_gpu_busy); | |
5372 | ||
5373 | /** | |
5374 | * i915_gpu_turbo_disable - disable graphics turbo | |
5375 | * | |
5376 | * Disable graphics turbo by resetting the max frequency and setting the | |
5377 | * current frequency to the default. | |
5378 | */ | |
5379 | bool i915_gpu_turbo_disable(void) | |
5380 | { | |
5381 | struct drm_i915_private *dev_priv; | |
5382 | bool ret = true; | |
5383 | ||
5384 | spin_lock_irq(&mchdev_lock); | |
5385 | if (!i915_mch_dev) { | |
5386 | ret = false; | |
5387 | goto out_unlock; | |
5388 | } | |
5389 | dev_priv = i915_mch_dev; | |
5390 | ||
5391 | dev_priv->ips.max_delay = dev_priv->ips.fstart; | |
5392 | ||
5393 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) | |
5394 | ret = false; | |
5395 | ||
5396 | out_unlock: | |
5397 | spin_unlock_irq(&mchdev_lock); | |
5398 | ||
5399 | return ret; | |
5400 | } | |
5401 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); | |
5402 | ||
5403 | /** | |
5404 | * Tells the intel_ips driver that the i915 driver is now loaded, if | |
5405 | * IPS got loaded first. | |
5406 | * | |
5407 | * This awkward dance is so that neither module has to depend on the | |
5408 | * other in order for IPS to do the appropriate communication of | |
5409 | * GPU turbo limits to i915. | |
5410 | */ | |
5411 | static void | |
5412 | ips_ping_for_i915_load(void) | |
5413 | { | |
5414 | void (*link)(void); | |
5415 | ||
5416 | link = symbol_get(ips_link_to_i915_driver); | |
5417 | if (link) { | |
5418 | link(); | |
5419 | symbol_put(ips_link_to_i915_driver); | |
5420 | } | |
5421 | } | |
5422 | ||
5423 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) | |
5424 | { | |
5425 | /* We only register the i915 ips part with intel-ips once everything is | |
5426 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ | |
5427 | spin_lock_irq(&mchdev_lock); | |
5428 | i915_mch_dev = dev_priv; | |
5429 | spin_unlock_irq(&mchdev_lock); | |
5430 | ||
5431 | ips_ping_for_i915_load(); | |
5432 | } | |
5433 | ||
5434 | void intel_gpu_ips_teardown(void) | |
5435 | { | |
5436 | spin_lock_irq(&mchdev_lock); | |
5437 | i915_mch_dev = NULL; | |
5438 | spin_unlock_irq(&mchdev_lock); | |
5439 | } | |
5440 | ||
5441 | static void intel_init_emon(struct drm_device *dev) | |
5442 | { | |
5443 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5444 | u32 lcfuse; | |
5445 | u8 pxw[16]; | |
5446 | int i; | |
5447 | ||
5448 | /* Disable to program */ | |
5449 | I915_WRITE(ECR, 0); | |
5450 | POSTING_READ(ECR); | |
5451 | ||
5452 | /* Program energy weights for various events */ | |
5453 | I915_WRITE(SDEW, 0x15040d00); | |
5454 | I915_WRITE(CSIEW0, 0x007f0000); | |
5455 | I915_WRITE(CSIEW1, 0x1e220004); | |
5456 | I915_WRITE(CSIEW2, 0x04000004); | |
5457 | ||
5458 | for (i = 0; i < 5; i++) | |
5459 | I915_WRITE(PEW + (i * 4), 0); | |
5460 | for (i = 0; i < 3; i++) | |
5461 | I915_WRITE(DEW + (i * 4), 0); | |
5462 | ||
5463 | /* Program P-state weights to account for frequency power adjustment */ | |
5464 | for (i = 0; i < 16; i++) { | |
5465 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); | |
5466 | unsigned long freq = intel_pxfreq(pxvidfreq); | |
5467 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
5468 | PXVFREQ_PX_SHIFT; | |
5469 | unsigned long val; | |
5470 | ||
5471 | val = vid * vid; | |
5472 | val *= (freq / 1000); | |
5473 | val *= 255; | |
5474 | val /= (127*127*900); | |
5475 | if (val > 0xff) | |
5476 | DRM_ERROR("bad pxval: %ld\n", val); | |
5477 | pxw[i] = val; | |
5478 | } | |
5479 | /* Render standby states get 0 weight */ | |
5480 | pxw[14] = 0; | |
5481 | pxw[15] = 0; | |
5482 | ||
5483 | for (i = 0; i < 4; i++) { | |
5484 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
5485 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
5486 | I915_WRITE(PXW + (i * 4), val); | |
5487 | } | |
5488 | ||
5489 | /* Adjust magic regs to magic values (more experimental results) */ | |
5490 | I915_WRITE(OGW0, 0); | |
5491 | I915_WRITE(OGW1, 0); | |
5492 | I915_WRITE(EG0, 0x00007f00); | |
5493 | I915_WRITE(EG1, 0x0000000e); | |
5494 | I915_WRITE(EG2, 0x000e0000); | |
5495 | I915_WRITE(EG3, 0x68000300); | |
5496 | I915_WRITE(EG4, 0x42000000); | |
5497 | I915_WRITE(EG5, 0x00140031); | |
5498 | I915_WRITE(EG6, 0); | |
5499 | I915_WRITE(EG7, 0); | |
5500 | ||
5501 | for (i = 0; i < 8; i++) | |
5502 | I915_WRITE(PXWL + (i * 4), 0); | |
5503 | ||
5504 | /* Enable PMON + select events */ | |
5505 | I915_WRITE(ECR, 0x80000019); | |
5506 | ||
5507 | lcfuse = I915_READ(LCFUSE02); | |
5508 | ||
5509 | dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); | |
5510 | } | |
5511 | ||
5512 | void intel_init_gt_powersave(struct drm_device *dev) | |
5513 | { | |
5514 | i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6); | |
5515 | ||
5516 | if (IS_CHERRYVIEW(dev)) | |
5517 | cherryview_init_gt_powersave(dev); | |
5518 | else if (IS_VALLEYVIEW(dev)) | |
5519 | valleyview_init_gt_powersave(dev); | |
5520 | } | |
5521 | ||
5522 | void intel_cleanup_gt_powersave(struct drm_device *dev) | |
5523 | { | |
5524 | if (IS_CHERRYVIEW(dev)) | |
5525 | return; | |
5526 | else if (IS_VALLEYVIEW(dev)) | |
5527 | valleyview_cleanup_gt_powersave(dev); | |
5528 | } | |
5529 | ||
5530 | static void gen6_suspend_rps(struct drm_device *dev) | |
5531 | { | |
5532 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5533 | ||
5534 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); | |
5535 | ||
5536 | /* | |
5537 | * TODO: disable RPS interrupts on GEN9+ too once RPS support | |
5538 | * is added for it. | |
5539 | */ | |
5540 | if (INTEL_INFO(dev)->gen < 9) | |
5541 | gen6_disable_rps_interrupts(dev); | |
5542 | } | |
5543 | ||
5544 | /** | |
5545 | * intel_suspend_gt_powersave - suspend PM work and helper threads | |
5546 | * @dev: drm device | |
5547 | * | |
5548 | * We don't want to disable RC6 or other features here, we just want | |
5549 | * to make sure any work we've queued has finished and won't bother | |
5550 | * us while we're suspended. | |
5551 | */ | |
5552 | void intel_suspend_gt_powersave(struct drm_device *dev) | |
5553 | { | |
5554 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5555 | ||
5556 | if (INTEL_INFO(dev)->gen < 6) | |
5557 | return; | |
5558 | ||
5559 | gen6_suspend_rps(dev); | |
5560 | ||
5561 | /* Force GPU to min freq during suspend */ | |
5562 | gen6_rps_idle(dev_priv); | |
5563 | } | |
5564 | ||
5565 | void intel_disable_gt_powersave(struct drm_device *dev) | |
5566 | { | |
5567 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5568 | ||
5569 | if (IS_IRONLAKE_M(dev)) { | |
5570 | ironlake_disable_drps(dev); | |
5571 | ironlake_disable_rc6(dev); | |
5572 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
5573 | intel_suspend_gt_powersave(dev); | |
5574 | ||
5575 | mutex_lock(&dev_priv->rps.hw_lock); | |
5576 | if (INTEL_INFO(dev)->gen >= 9) | |
5577 | gen9_disable_rps(dev); | |
5578 | else if (IS_CHERRYVIEW(dev)) | |
5579 | cherryview_disable_rps(dev); | |
5580 | else if (IS_VALLEYVIEW(dev)) | |
5581 | valleyview_disable_rps(dev); | |
5582 | else | |
5583 | gen6_disable_rps(dev); | |
5584 | ||
5585 | dev_priv->rps.enabled = false; | |
5586 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5587 | } | |
5588 | } | |
5589 | ||
5590 | static void intel_gen6_powersave_work(struct work_struct *work) | |
5591 | { | |
5592 | struct drm_i915_private *dev_priv = | |
5593 | container_of(work, struct drm_i915_private, | |
5594 | rps.delayed_resume_work.work); | |
5595 | struct drm_device *dev = dev_priv->dev; | |
5596 | ||
5597 | mutex_lock(&dev_priv->rps.hw_lock); | |
5598 | ||
5599 | /* | |
5600 | * TODO: reset/enable RPS interrupts on GEN9+ too, once RPS support is | |
5601 | * added for it. | |
5602 | */ | |
5603 | if (INTEL_INFO(dev)->gen < 9) | |
5604 | gen6_reset_rps_interrupts(dev); | |
5605 | ||
5606 | if (IS_CHERRYVIEW(dev)) { | |
5607 | cherryview_enable_rps(dev); | |
5608 | } else if (IS_VALLEYVIEW(dev)) { | |
5609 | valleyview_enable_rps(dev); | |
5610 | } else if (INTEL_INFO(dev)->gen >= 9) { | |
5611 | gen9_enable_rc6(dev); | |
5612 | gen9_enable_rps(dev); | |
5613 | __gen6_update_ring_freq(dev); | |
5614 | } else if (IS_BROADWELL(dev)) { | |
5615 | gen8_enable_rps(dev); | |
5616 | __gen6_update_ring_freq(dev); | |
5617 | } else { | |
5618 | gen6_enable_rps(dev); | |
5619 | __gen6_update_ring_freq(dev); | |
5620 | } | |
5621 | dev_priv->rps.enabled = true; | |
5622 | ||
5623 | if (INTEL_INFO(dev)->gen < 9) | |
5624 | gen6_enable_rps_interrupts(dev); | |
5625 | ||
5626 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5627 | ||
5628 | intel_runtime_pm_put(dev_priv); | |
5629 | } | |
5630 | ||
5631 | void intel_enable_gt_powersave(struct drm_device *dev) | |
5632 | { | |
5633 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5634 | ||
5635 | if (IS_IRONLAKE_M(dev)) { | |
5636 | mutex_lock(&dev->struct_mutex); | |
5637 | ironlake_enable_drps(dev); | |
5638 | ironlake_enable_rc6(dev); | |
5639 | intel_init_emon(dev); | |
5640 | mutex_unlock(&dev->struct_mutex); | |
5641 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
5642 | /* | |
5643 | * PCU communication is slow and this doesn't need to be | |
5644 | * done at any specific time, so do this out of our fast path | |
5645 | * to make resume and init faster. | |
5646 | * | |
5647 | * We depend on the HW RC6 power context save/restore | |
5648 | * mechanism when entering D3 through runtime PM suspend. So | |
5649 | * disable RPM until RPS/RC6 is properly setup. We can only | |
5650 | * get here via the driver load/system resume/runtime resume | |
5651 | * paths, so the _noresume version is enough (and in case of | |
5652 | * runtime resume it's necessary). | |
5653 | */ | |
5654 | if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work, | |
5655 | round_jiffies_up_relative(HZ))) | |
5656 | intel_runtime_pm_get_noresume(dev_priv); | |
5657 | } | |
5658 | } | |
5659 | ||
5660 | void intel_reset_gt_powersave(struct drm_device *dev) | |
5661 | { | |
5662 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5663 | ||
5664 | if (INTEL_INFO(dev)->gen < 6) | |
5665 | return; | |
5666 | ||
5667 | gen6_suspend_rps(dev); | |
5668 | dev_priv->rps.enabled = false; | |
5669 | } | |
5670 | ||
5671 | static void ibx_init_clock_gating(struct drm_device *dev) | |
5672 | { | |
5673 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5674 | ||
5675 | /* | |
5676 | * On Ibex Peak and Cougar Point, we need to disable clock | |
5677 | * gating for the panel power sequencer or it will fail to | |
5678 | * start up when no ports are active. | |
5679 | */ | |
5680 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
5681 | } | |
5682 | ||
5683 | static void g4x_disable_trickle_feed(struct drm_device *dev) | |
5684 | { | |
5685 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5686 | int pipe; | |
5687 | ||
5688 | for_each_pipe(dev_priv, pipe) { | |
5689 | I915_WRITE(DSPCNTR(pipe), | |
5690 | I915_READ(DSPCNTR(pipe)) | | |
5691 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
5692 | intel_flush_primary_plane(dev_priv, pipe); | |
5693 | } | |
5694 | } | |
5695 | ||
5696 | static void ilk_init_lp_watermarks(struct drm_device *dev) | |
5697 | { | |
5698 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5699 | ||
5700 | I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); | |
5701 | I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); | |
5702 | I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); | |
5703 | ||
5704 | /* | |
5705 | * Don't touch WM1S_LP_EN here. | |
5706 | * Doing so could cause underruns. | |
5707 | */ | |
5708 | } | |
5709 | ||
5710 | static void ironlake_init_clock_gating(struct drm_device *dev) | |
5711 | { | |
5712 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5713 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; | |
5714 | ||
5715 | /* | |
5716 | * Required for FBC | |
5717 | * WaFbcDisableDpfcClockGating:ilk | |
5718 | */ | |
5719 | dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | | |
5720 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | | |
5721 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE; | |
5722 | ||
5723 | I915_WRITE(PCH_3DCGDIS0, | |
5724 | MARIUNIT_CLOCK_GATE_DISABLE | | |
5725 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
5726 | I915_WRITE(PCH_3DCGDIS1, | |
5727 | VFMUNIT_CLOCK_GATE_DISABLE); | |
5728 | ||
5729 | /* | |
5730 | * According to the spec the following bits should be set in | |
5731 | * order to enable memory self-refresh | |
5732 | * The bit 22/21 of 0x42004 | |
5733 | * The bit 5 of 0x42020 | |
5734 | * The bit 15 of 0x45000 | |
5735 | */ | |
5736 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5737 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5738 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
5739 | dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; | |
5740 | I915_WRITE(DISP_ARB_CTL, | |
5741 | (I915_READ(DISP_ARB_CTL) | | |
5742 | DISP_FBC_WM_DIS)); | |
5743 | ||
5744 | ilk_init_lp_watermarks(dev); | |
5745 | ||
5746 | /* | |
5747 | * Based on the document from hardware guys the following bits | |
5748 | * should be set unconditionally in order to enable FBC. | |
5749 | * The bit 22 of 0x42000 | |
5750 | * The bit 22 of 0x42004 | |
5751 | * The bit 7,8,9 of 0x42020. | |
5752 | */ | |
5753 | if (IS_IRONLAKE_M(dev)) { | |
5754 | /* WaFbcAsynchFlipDisableFbcQueue:ilk */ | |
5755 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
5756 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
5757 | ILK_FBCQ_DIS); | |
5758 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5759 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5760 | ILK_DPARB_GATE); | |
5761 | } | |
5762 | ||
5763 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); | |
5764 | ||
5765 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5766 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5767 | ILK_ELPIN_409_SELECT); | |
5768 | I915_WRITE(_3D_CHICKEN2, | |
5769 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | | |
5770 | _3D_CHICKEN2_WM_READ_PIPELINED); | |
5771 | ||
5772 | /* WaDisableRenderCachePipelinedFlush:ilk */ | |
5773 | I915_WRITE(CACHE_MODE_0, | |
5774 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
5775 | ||
5776 | /* WaDisable_RenderCache_OperationalFlush:ilk */ | |
5777 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
5778 | ||
5779 | g4x_disable_trickle_feed(dev); | |
5780 | ||
5781 | ibx_init_clock_gating(dev); | |
5782 | } | |
5783 | ||
5784 | static void cpt_init_clock_gating(struct drm_device *dev) | |
5785 | { | |
5786 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5787 | int pipe; | |
5788 | uint32_t val; | |
5789 | ||
5790 | /* | |
5791 | * On Ibex Peak and Cougar Point, we need to disable clock | |
5792 | * gating for the panel power sequencer or it will fail to | |
5793 | * start up when no ports are active. | |
5794 | */ | |
5795 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | | |
5796 | PCH_DPLUNIT_CLOCK_GATE_DISABLE | | |
5797 | PCH_CPUNIT_CLOCK_GATE_DISABLE); | |
5798 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | | |
5799 | DPLS_EDP_PPS_FIX_DIS); | |
5800 | /* The below fixes the weird display corruption, a few pixels shifted | |
5801 | * downward, on (only) LVDS of some HP laptops with IVY. | |
5802 | */ | |
5803 | for_each_pipe(dev_priv, pipe) { | |
5804 | val = I915_READ(TRANS_CHICKEN2(pipe)); | |
5805 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
5806 | val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; | |
5807 | if (dev_priv->vbt.fdi_rx_polarity_inverted) | |
5808 | val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; | |
5809 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; | |
5810 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; | |
5811 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; | |
5812 | I915_WRITE(TRANS_CHICKEN2(pipe), val); | |
5813 | } | |
5814 | /* WADP0ClockGatingDisable */ | |
5815 | for_each_pipe(dev_priv, pipe) { | |
5816 | I915_WRITE(TRANS_CHICKEN1(pipe), | |
5817 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); | |
5818 | } | |
5819 | } | |
5820 | ||
5821 | static void gen6_check_mch_setup(struct drm_device *dev) | |
5822 | { | |
5823 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5824 | uint32_t tmp; | |
5825 | ||
5826 | tmp = I915_READ(MCH_SSKPD); | |
5827 | if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) | |
5828 | DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", | |
5829 | tmp); | |
5830 | } | |
5831 | ||
5832 | static void gen6_init_clock_gating(struct drm_device *dev) | |
5833 | { | |
5834 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5835 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; | |
5836 | ||
5837 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); | |
5838 | ||
5839 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5840 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5841 | ILK_ELPIN_409_SELECT); | |
5842 | ||
5843 | /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ | |
5844 | I915_WRITE(_3D_CHICKEN, | |
5845 | _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); | |
5846 | ||
5847 | /* WaDisable_RenderCache_OperationalFlush:snb */ | |
5848 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
5849 | ||
5850 | /* | |
5851 | * BSpec recoomends 8x4 when MSAA is used, | |
5852 | * however in practice 16x4 seems fastest. | |
5853 | * | |
5854 | * Note that PS/WM thread counts depend on the WIZ hashing | |
5855 | * disable bit, which we don't touch here, but it's good | |
5856 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
5857 | */ | |
5858 | I915_WRITE(GEN6_GT_MODE, | |
5859 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); | |
5860 | ||
5861 | ilk_init_lp_watermarks(dev); | |
5862 | ||
5863 | I915_WRITE(CACHE_MODE_0, | |
5864 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); | |
5865 | ||
5866 | I915_WRITE(GEN6_UCGCTL1, | |
5867 | I915_READ(GEN6_UCGCTL1) | | |
5868 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | | |
5869 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
5870 | ||
5871 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock | |
5872 | * gating disable must be set. Failure to set it results in | |
5873 | * flickering pixels due to Z write ordering failures after | |
5874 | * some amount of runtime in the Mesa "fire" demo, and Unigine | |
5875 | * Sanctuary and Tropics, and apparently anything else with | |
5876 | * alpha test or pixel discard. | |
5877 | * | |
5878 | * According to the spec, bit 11 (RCCUNIT) must also be set, | |
5879 | * but we didn't debug actual testcases to find it out. | |
5880 | * | |
5881 | * WaDisableRCCUnitClockGating:snb | |
5882 | * WaDisableRCPBUnitClockGating:snb | |
5883 | */ | |
5884 | I915_WRITE(GEN6_UCGCTL2, | |
5885 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | | |
5886 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); | |
5887 | ||
5888 | /* WaStripsFansDisableFastClipPerformanceFix:snb */ | |
5889 | I915_WRITE(_3D_CHICKEN3, | |
5890 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); | |
5891 | ||
5892 | /* | |
5893 | * Bspec says: | |
5894 | * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and | |
5895 | * 3DSTATE_SF number of SF output attributes is more than 16." | |
5896 | */ | |
5897 | I915_WRITE(_3D_CHICKEN3, | |
5898 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); | |
5899 | ||
5900 | /* | |
5901 | * According to the spec the following bits should be | |
5902 | * set in order to enable memory self-refresh and fbc: | |
5903 | * The bit21 and bit22 of 0x42000 | |
5904 | * The bit21 and bit22 of 0x42004 | |
5905 | * The bit5 and bit7 of 0x42020 | |
5906 | * The bit14 of 0x70180 | |
5907 | * The bit14 of 0x71180 | |
5908 | * | |
5909 | * WaFbcAsynchFlipDisableFbcQueue:snb | |
5910 | */ | |
5911 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
5912 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
5913 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); | |
5914 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5915 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5916 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); | |
5917 | I915_WRITE(ILK_DSPCLK_GATE_D, | |
5918 | I915_READ(ILK_DSPCLK_GATE_D) | | |
5919 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE | | |
5920 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); | |
5921 | ||
5922 | g4x_disable_trickle_feed(dev); | |
5923 | ||
5924 | cpt_init_clock_gating(dev); | |
5925 | ||
5926 | gen6_check_mch_setup(dev); | |
5927 | } | |
5928 | ||
5929 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) | |
5930 | { | |
5931 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); | |
5932 | ||
5933 | /* | |
5934 | * WaVSThreadDispatchOverride:ivb,vlv | |
5935 | * | |
5936 | * This actually overrides the dispatch | |
5937 | * mode for all thread types. | |
5938 | */ | |
5939 | reg &= ~GEN7_FF_SCHED_MASK; | |
5940 | reg |= GEN7_FF_TS_SCHED_HW; | |
5941 | reg |= GEN7_FF_VS_SCHED_HW; | |
5942 | reg |= GEN7_FF_DS_SCHED_HW; | |
5943 | ||
5944 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); | |
5945 | } | |
5946 | ||
5947 | static void lpt_init_clock_gating(struct drm_device *dev) | |
5948 | { | |
5949 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5950 | ||
5951 | /* | |
5952 | * TODO: this bit should only be enabled when really needed, then | |
5953 | * disabled when not needed anymore in order to save power. | |
5954 | */ | |
5955 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) | |
5956 | I915_WRITE(SOUTH_DSPCLK_GATE_D, | |
5957 | I915_READ(SOUTH_DSPCLK_GATE_D) | | |
5958 | PCH_LP_PARTITION_LEVEL_DISABLE); | |
5959 | ||
5960 | /* WADPOClockGatingDisable:hsw */ | |
5961 | I915_WRITE(_TRANSA_CHICKEN1, | |
5962 | I915_READ(_TRANSA_CHICKEN1) | | |
5963 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); | |
5964 | } | |
5965 | ||
5966 | static void lpt_suspend_hw(struct drm_device *dev) | |
5967 | { | |
5968 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5969 | ||
5970 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
5971 | uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
5972 | ||
5973 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
5974 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
5975 | } | |
5976 | } | |
5977 | ||
5978 | static void broadwell_init_clock_gating(struct drm_device *dev) | |
5979 | { | |
5980 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5981 | enum pipe pipe; | |
5982 | ||
5983 | I915_WRITE(WM3_LP_ILK, 0); | |
5984 | I915_WRITE(WM2_LP_ILK, 0); | |
5985 | I915_WRITE(WM1_LP_ILK, 0); | |
5986 | ||
5987 | /* WaSwitchSolVfFArbitrationPriority:bdw */ | |
5988 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); | |
5989 | ||
5990 | /* WaPsrDPAMaskVBlankInSRD:bdw */ | |
5991 | I915_WRITE(CHICKEN_PAR1_1, | |
5992 | I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); | |
5993 | ||
5994 | /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ | |
5995 | for_each_pipe(dev_priv, pipe) { | |
5996 | I915_WRITE(CHICKEN_PIPESL_1(pipe), | |
5997 | I915_READ(CHICKEN_PIPESL_1(pipe)) | | |
5998 | BDW_DPRS_MASK_VBLANK_SRD); | |
5999 | } | |
6000 | ||
6001 | /* WaVSRefCountFullforceMissDisable:bdw */ | |
6002 | /* WaDSRefCountFullforceMissDisable:bdw */ | |
6003 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
6004 | I915_READ(GEN7_FF_THREAD_MODE) & | |
6005 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
6006 | ||
6007 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, | |
6008 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
6009 | ||
6010 | /* WaDisableSDEUnitClockGating:bdw */ | |
6011 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
6012 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
6013 | ||
6014 | lpt_init_clock_gating(dev); | |
6015 | } | |
6016 | ||
6017 | static void haswell_init_clock_gating(struct drm_device *dev) | |
6018 | { | |
6019 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6020 | ||
6021 | ilk_init_lp_watermarks(dev); | |
6022 | ||
6023 | /* L3 caching of data atomics doesn't work -- disable it. */ | |
6024 | I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); | |
6025 | I915_WRITE(HSW_ROW_CHICKEN3, | |
6026 | _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); | |
6027 | ||
6028 | /* This is required by WaCatErrorRejectionIssue:hsw */ | |
6029 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, | |
6030 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
6031 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
6032 | ||
6033 | /* WaVSRefCountFullforceMissDisable:hsw */ | |
6034 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
6035 | I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); | |
6036 | ||
6037 | /* WaDisable_RenderCache_OperationalFlush:hsw */ | |
6038 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6039 | ||
6040 | /* enable HiZ Raw Stall Optimization */ | |
6041 | I915_WRITE(CACHE_MODE_0_GEN7, | |
6042 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
6043 | ||
6044 | /* WaDisable4x2SubspanOptimization:hsw */ | |
6045 | I915_WRITE(CACHE_MODE_1, | |
6046 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
6047 | ||
6048 | /* | |
6049 | * BSpec recommends 8x4 when MSAA is used, | |
6050 | * however in practice 16x4 seems fastest. | |
6051 | * | |
6052 | * Note that PS/WM thread counts depend on the WIZ hashing | |
6053 | * disable bit, which we don't touch here, but it's good | |
6054 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
6055 | */ | |
6056 | I915_WRITE(GEN7_GT_MODE, | |
6057 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); | |
6058 | ||
6059 | /* WaSampleCChickenBitEnable:hsw */ | |
6060 | I915_WRITE(HALF_SLICE_CHICKEN3, | |
6061 | _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE)); | |
6062 | ||
6063 | /* WaSwitchSolVfFArbitrationPriority:hsw */ | |
6064 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); | |
6065 | ||
6066 | /* WaRsPkgCStateDisplayPMReq:hsw */ | |
6067 | I915_WRITE(CHICKEN_PAR1_1, | |
6068 | I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); | |
6069 | ||
6070 | lpt_init_clock_gating(dev); | |
6071 | } | |
6072 | ||
6073 | static void ivybridge_init_clock_gating(struct drm_device *dev) | |
6074 | { | |
6075 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6076 | uint32_t snpcr; | |
6077 | ||
6078 | ilk_init_lp_watermarks(dev); | |
6079 | ||
6080 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); | |
6081 | ||
6082 | /* WaDisableEarlyCull:ivb */ | |
6083 | I915_WRITE(_3D_CHICKEN3, | |
6084 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
6085 | ||
6086 | /* WaDisableBackToBackFlipFix:ivb */ | |
6087 | I915_WRITE(IVB_CHICKEN3, | |
6088 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
6089 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
6090 | ||
6091 | /* WaDisablePSDDualDispatchEnable:ivb */ | |
6092 | if (IS_IVB_GT1(dev)) | |
6093 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, | |
6094 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
6095 | ||
6096 | /* WaDisable_RenderCache_OperationalFlush:ivb */ | |
6097 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6098 | ||
6099 | /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ | |
6100 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, | |
6101 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); | |
6102 | ||
6103 | /* WaApplyL3ControlAndL3ChickenMode:ivb */ | |
6104 | I915_WRITE(GEN7_L3CNTLREG1, | |
6105 | GEN7_WA_FOR_GEN7_L3_CONTROL); | |
6106 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, | |
6107 | GEN7_WA_L3_CHICKEN_MODE); | |
6108 | if (IS_IVB_GT1(dev)) | |
6109 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
6110 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
6111 | else { | |
6112 | /* must write both registers */ | |
6113 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
6114 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
6115 | I915_WRITE(GEN7_ROW_CHICKEN2_GT2, | |
6116 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
6117 | } | |
6118 | ||
6119 | /* WaForceL3Serialization:ivb */ | |
6120 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & | |
6121 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
6122 | ||
6123 | /* | |
6124 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. | |
6125 | * This implements the WaDisableRCZUnitClockGating:ivb workaround. | |
6126 | */ | |
6127 | I915_WRITE(GEN6_UCGCTL2, | |
6128 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); | |
6129 | ||
6130 | /* This is required by WaCatErrorRejectionIssue:ivb */ | |
6131 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, | |
6132 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
6133 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
6134 | ||
6135 | g4x_disable_trickle_feed(dev); | |
6136 | ||
6137 | gen7_setup_fixed_func_scheduler(dev_priv); | |
6138 | ||
6139 | if (0) { /* causes HiZ corruption on ivb:gt1 */ | |
6140 | /* enable HiZ Raw Stall Optimization */ | |
6141 | I915_WRITE(CACHE_MODE_0_GEN7, | |
6142 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
6143 | } | |
6144 | ||
6145 | /* WaDisable4x2SubspanOptimization:ivb */ | |
6146 | I915_WRITE(CACHE_MODE_1, | |
6147 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
6148 | ||
6149 | /* | |
6150 | * BSpec recommends 8x4 when MSAA is used, | |
6151 | * however in practice 16x4 seems fastest. | |
6152 | * | |
6153 | * Note that PS/WM thread counts depend on the WIZ hashing | |
6154 | * disable bit, which we don't touch here, but it's good | |
6155 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
6156 | */ | |
6157 | I915_WRITE(GEN7_GT_MODE, | |
6158 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); | |
6159 | ||
6160 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
6161 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
6162 | snpcr |= GEN6_MBC_SNPCR_MED; | |
6163 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
6164 | ||
6165 | if (!HAS_PCH_NOP(dev)) | |
6166 | cpt_init_clock_gating(dev); | |
6167 | ||
6168 | gen6_check_mch_setup(dev); | |
6169 | } | |
6170 | ||
6171 | static void valleyview_init_clock_gating(struct drm_device *dev) | |
6172 | { | |
6173 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6174 | ||
6175 | I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); | |
6176 | ||
6177 | /* WaDisableEarlyCull:vlv */ | |
6178 | I915_WRITE(_3D_CHICKEN3, | |
6179 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
6180 | ||
6181 | /* WaDisableBackToBackFlipFix:vlv */ | |
6182 | I915_WRITE(IVB_CHICKEN3, | |
6183 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
6184 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
6185 | ||
6186 | /* WaPsdDispatchEnable:vlv */ | |
6187 | /* WaDisablePSDDualDispatchEnable:vlv */ | |
6188 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, | |
6189 | _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | | |
6190 | GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
6191 | ||
6192 | /* WaDisable_RenderCache_OperationalFlush:vlv */ | |
6193 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6194 | ||
6195 | /* WaForceL3Serialization:vlv */ | |
6196 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & | |
6197 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
6198 | ||
6199 | /* WaDisableDopClockGating:vlv */ | |
6200 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
6201 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
6202 | ||
6203 | /* This is required by WaCatErrorRejectionIssue:vlv */ | |
6204 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, | |
6205 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
6206 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
6207 | ||
6208 | gen7_setup_fixed_func_scheduler(dev_priv); | |
6209 | ||
6210 | /* | |
6211 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. | |
6212 | * This implements the WaDisableRCZUnitClockGating:vlv workaround. | |
6213 | */ | |
6214 | I915_WRITE(GEN6_UCGCTL2, | |
6215 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); | |
6216 | ||
6217 | /* WaDisableL3Bank2xClockGate:vlv | |
6218 | * Disabling L3 clock gating- MMIO 940c[25] = 1 | |
6219 | * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ | |
6220 | I915_WRITE(GEN7_UCGCTL4, | |
6221 | I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); | |
6222 | ||
6223 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); | |
6224 | ||
6225 | /* | |
6226 | * BSpec says this must be set, even though | |
6227 | * WaDisable4x2SubspanOptimization isn't listed for VLV. | |
6228 | */ | |
6229 | I915_WRITE(CACHE_MODE_1, | |
6230 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
6231 | ||
6232 | /* | |
6233 | * BSpec recommends 8x4 when MSAA is used, | |
6234 | * however in practice 16x4 seems fastest. | |
6235 | * | |
6236 | * Note that PS/WM thread counts depend on the WIZ hashing | |
6237 | * disable bit, which we don't touch here, but it's good | |
6238 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
6239 | */ | |
6240 | I915_WRITE(GEN7_GT_MODE, | |
6241 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); | |
6242 | ||
6243 | /* | |
6244 | * WaIncreaseL3CreditsForVLVB0:vlv | |
6245 | * This is the hardware default actually. | |
6246 | */ | |
6247 | I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); | |
6248 | ||
6249 | /* | |
6250 | * WaDisableVLVClockGating_VBIIssue:vlv | |
6251 | * Disable clock gating on th GCFG unit to prevent a delay | |
6252 | * in the reporting of vblank events. | |
6253 | */ | |
6254 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); | |
6255 | } | |
6256 | ||
6257 | static void cherryview_init_clock_gating(struct drm_device *dev) | |
6258 | { | |
6259 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6260 | ||
6261 | I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); | |
6262 | ||
6263 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); | |
6264 | ||
6265 | /* WaVSRefCountFullforceMissDisable:chv */ | |
6266 | /* WaDSRefCountFullforceMissDisable:chv */ | |
6267 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
6268 | I915_READ(GEN7_FF_THREAD_MODE) & | |
6269 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
6270 | ||
6271 | /* WaDisableSemaphoreAndSyncFlipWait:chv */ | |
6272 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, | |
6273 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
6274 | ||
6275 | /* WaDisableCSUnitClockGating:chv */ | |
6276 | I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | | |
6277 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
6278 | ||
6279 | /* WaDisableSDEUnitClockGating:chv */ | |
6280 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
6281 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
6282 | } | |
6283 | ||
6284 | static void g4x_init_clock_gating(struct drm_device *dev) | |
6285 | { | |
6286 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6287 | uint32_t dspclk_gate; | |
6288 | ||
6289 | I915_WRITE(RENCLK_GATE_D1, 0); | |
6290 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
6291 | GS_UNIT_CLOCK_GATE_DISABLE | | |
6292 | CL_UNIT_CLOCK_GATE_DISABLE); | |
6293 | I915_WRITE(RAMCLK_GATE_D, 0); | |
6294 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
6295 | OVRUNIT_CLOCK_GATE_DISABLE | | |
6296 | OVCUNIT_CLOCK_GATE_DISABLE; | |
6297 | if (IS_GM45(dev)) | |
6298 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; | |
6299 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
6300 | ||
6301 | /* WaDisableRenderCachePipelinedFlush */ | |
6302 | I915_WRITE(CACHE_MODE_0, | |
6303 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
6304 | ||
6305 | /* WaDisable_RenderCache_OperationalFlush:g4x */ | |
6306 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6307 | ||
6308 | g4x_disable_trickle_feed(dev); | |
6309 | } | |
6310 | ||
6311 | static void crestline_init_clock_gating(struct drm_device *dev) | |
6312 | { | |
6313 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6314 | ||
6315 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); | |
6316 | I915_WRITE(RENCLK_GATE_D2, 0); | |
6317 | I915_WRITE(DSPCLK_GATE_D, 0); | |
6318 | I915_WRITE(RAMCLK_GATE_D, 0); | |
6319 | I915_WRITE16(DEUC, 0); | |
6320 | I915_WRITE(MI_ARB_STATE, | |
6321 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6322 | ||
6323 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ | |
6324 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6325 | } | |
6326 | ||
6327 | static void broadwater_init_clock_gating(struct drm_device *dev) | |
6328 | { | |
6329 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6330 | ||
6331 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | | |
6332 | I965_RCC_CLOCK_GATE_DISABLE | | |
6333 | I965_RCPB_CLOCK_GATE_DISABLE | | |
6334 | I965_ISC_CLOCK_GATE_DISABLE | | |
6335 | I965_FBC_CLOCK_GATE_DISABLE); | |
6336 | I915_WRITE(RENCLK_GATE_D2, 0); | |
6337 | I915_WRITE(MI_ARB_STATE, | |
6338 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6339 | ||
6340 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ | |
6341 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6342 | } | |
6343 | ||
6344 | static void gen3_init_clock_gating(struct drm_device *dev) | |
6345 | { | |
6346 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6347 | u32 dstate = I915_READ(D_STATE); | |
6348 | ||
6349 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
6350 | DSTATE_DOT_CLOCK_GATING; | |
6351 | I915_WRITE(D_STATE, dstate); | |
6352 | ||
6353 | if (IS_PINEVIEW(dev)) | |
6354 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); | |
6355 | ||
6356 | /* IIR "flip pending" means done if this bit is set */ | |
6357 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); | |
6358 | ||
6359 | /* interrupts should cause a wake up from C3 */ | |
6360 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); | |
6361 | ||
6362 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ | |
6363 | I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
6364 | ||
6365 | I915_WRITE(MI_ARB_STATE, | |
6366 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6367 | } | |
6368 | ||
6369 | static void i85x_init_clock_gating(struct drm_device *dev) | |
6370 | { | |
6371 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6372 | ||
6373 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); | |
6374 | ||
6375 | /* interrupts should cause a wake up from C3 */ | |
6376 | I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | | |
6377 | _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); | |
6378 | ||
6379 | I915_WRITE(MEM_MODE, | |
6380 | _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6381 | } | |
6382 | ||
6383 | static void i830_init_clock_gating(struct drm_device *dev) | |
6384 | { | |
6385 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6386 | ||
6387 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); | |
6388 | ||
6389 | I915_WRITE(MEM_MODE, | |
6390 | _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | | |
6391 | _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); | |
6392 | } | |
6393 | ||
6394 | void intel_init_clock_gating(struct drm_device *dev) | |
6395 | { | |
6396 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6397 | ||
6398 | dev_priv->display.init_clock_gating(dev); | |
6399 | } | |
6400 | ||
6401 | void intel_suspend_hw(struct drm_device *dev) | |
6402 | { | |
6403 | if (HAS_PCH_LPT(dev)) | |
6404 | lpt_suspend_hw(dev); | |
6405 | } | |
6406 | ||
6407 | /* Set up chip specific power management-related functions */ | |
6408 | void intel_init_pm(struct drm_device *dev) | |
6409 | { | |
6410 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6411 | ||
6412 | intel_fbc_init(dev_priv); | |
6413 | ||
6414 | /* For cxsr */ | |
6415 | if (IS_PINEVIEW(dev)) | |
6416 | i915_pineview_get_mem_freq(dev); | |
6417 | else if (IS_GEN5(dev)) | |
6418 | i915_ironlake_get_mem_freq(dev); | |
6419 | ||
6420 | /* For FIFO watermark updates */ | |
6421 | if (INTEL_INFO(dev)->gen >= 9) { | |
6422 | skl_setup_wm_latency(dev); | |
6423 | ||
6424 | dev_priv->display.init_clock_gating = gen9_init_clock_gating; | |
6425 | dev_priv->display.update_wm = skl_update_wm; | |
6426 | dev_priv->display.update_sprite_wm = skl_update_sprite_wm; | |
6427 | } else if (HAS_PCH_SPLIT(dev)) { | |
6428 | ilk_setup_wm_latency(dev); | |
6429 | ||
6430 | if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] && | |
6431 | dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || | |
6432 | (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && | |
6433 | dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { | |
6434 | dev_priv->display.update_wm = ilk_update_wm; | |
6435 | dev_priv->display.update_sprite_wm = ilk_update_sprite_wm; | |
6436 | } else { | |
6437 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
6438 | "Disable CxSR\n"); | |
6439 | } | |
6440 | ||
6441 | if (IS_GEN5(dev)) | |
6442 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; | |
6443 | else if (IS_GEN6(dev)) | |
6444 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; | |
6445 | else if (IS_IVYBRIDGE(dev)) | |
6446 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; | |
6447 | else if (IS_HASWELL(dev)) | |
6448 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; | |
6449 | else if (INTEL_INFO(dev)->gen == 8) | |
6450 | dev_priv->display.init_clock_gating = broadwell_init_clock_gating; | |
6451 | } else if (IS_CHERRYVIEW(dev)) { | |
6452 | dev_priv->display.update_wm = cherryview_update_wm; | |
6453 | dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm; | |
6454 | dev_priv->display.init_clock_gating = | |
6455 | cherryview_init_clock_gating; | |
6456 | } else if (IS_VALLEYVIEW(dev)) { | |
6457 | dev_priv->display.update_wm = valleyview_update_wm; | |
6458 | dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm; | |
6459 | dev_priv->display.init_clock_gating = | |
6460 | valleyview_init_clock_gating; | |
6461 | } else if (IS_PINEVIEW(dev)) { | |
6462 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), | |
6463 | dev_priv->is_ddr3, | |
6464 | dev_priv->fsb_freq, | |
6465 | dev_priv->mem_freq)) { | |
6466 | DRM_INFO("failed to find known CxSR latency " | |
6467 | "(found ddr%s fsb freq %d, mem freq %d), " | |
6468 | "disabling CxSR\n", | |
6469 | (dev_priv->is_ddr3 == 1) ? "3" : "2", | |
6470 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
6471 | /* Disable CxSR and never update its watermark again */ | |
6472 | intel_set_memory_cxsr(dev_priv, false); | |
6473 | dev_priv->display.update_wm = NULL; | |
6474 | } else | |
6475 | dev_priv->display.update_wm = pineview_update_wm; | |
6476 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; | |
6477 | } else if (IS_G4X(dev)) { | |
6478 | dev_priv->display.update_wm = g4x_update_wm; | |
6479 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; | |
6480 | } else if (IS_GEN4(dev)) { | |
6481 | dev_priv->display.update_wm = i965_update_wm; | |
6482 | if (IS_CRESTLINE(dev)) | |
6483 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; | |
6484 | else if (IS_BROADWATER(dev)) | |
6485 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; | |
6486 | } else if (IS_GEN3(dev)) { | |
6487 | dev_priv->display.update_wm = i9xx_update_wm; | |
6488 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
6489 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; | |
6490 | } else if (IS_GEN2(dev)) { | |
6491 | if (INTEL_INFO(dev)->num_pipes == 1) { | |
6492 | dev_priv->display.update_wm = i845_update_wm; | |
6493 | dev_priv->display.get_fifo_size = i845_get_fifo_size; | |
6494 | } else { | |
6495 | dev_priv->display.update_wm = i9xx_update_wm; | |
6496 | dev_priv->display.get_fifo_size = i830_get_fifo_size; | |
6497 | } | |
6498 | ||
6499 | if (IS_I85X(dev) || IS_I865G(dev)) | |
6500 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; | |
6501 | else | |
6502 | dev_priv->display.init_clock_gating = i830_init_clock_gating; | |
6503 | } else { | |
6504 | DRM_ERROR("unexpected fall-through in intel_init_pm\n"); | |
6505 | } | |
6506 | } | |
6507 | ||
6508 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val) | |
6509 | { | |
6510 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
6511 | ||
6512 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
6513 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); | |
6514 | return -EAGAIN; | |
6515 | } | |
6516 | ||
6517 | I915_WRITE(GEN6_PCODE_DATA, *val); | |
6518 | I915_WRITE(GEN6_PCODE_DATA1, 0); | |
6519 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); | |
6520 | ||
6521 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
6522 | 500)) { | |
6523 | DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); | |
6524 | return -ETIMEDOUT; | |
6525 | } | |
6526 | ||
6527 | *val = I915_READ(GEN6_PCODE_DATA); | |
6528 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
6529 | ||
6530 | return 0; | |
6531 | } | |
6532 | ||
6533 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val) | |
6534 | { | |
6535 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
6536 | ||
6537 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
6538 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); | |
6539 | return -EAGAIN; | |
6540 | } | |
6541 | ||
6542 | I915_WRITE(GEN6_PCODE_DATA, val); | |
6543 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); | |
6544 | ||
6545 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
6546 | 500)) { | |
6547 | DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); | |
6548 | return -ETIMEDOUT; | |
6549 | } | |
6550 | ||
6551 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
6552 | ||
6553 | return 0; | |
6554 | } | |
6555 | ||
6556 | static int vlv_gpu_freq_div(unsigned int czclk_freq) | |
6557 | { | |
6558 | switch (czclk_freq) { | |
6559 | case 200: | |
6560 | return 10; | |
6561 | case 267: | |
6562 | return 12; | |
6563 | case 320: | |
6564 | case 333: | |
6565 | return 16; | |
6566 | case 400: | |
6567 | return 20; | |
6568 | default: | |
6569 | return -1; | |
6570 | } | |
6571 | } | |
6572 | ||
6573 | static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) | |
6574 | { | |
6575 | int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4); | |
6576 | ||
6577 | div = vlv_gpu_freq_div(czclk_freq); | |
6578 | if (div < 0) | |
6579 | return div; | |
6580 | ||
6581 | return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div); | |
6582 | } | |
6583 | ||
6584 | static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) | |
6585 | { | |
6586 | int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4); | |
6587 | ||
6588 | mul = vlv_gpu_freq_div(czclk_freq); | |
6589 | if (mul < 0) | |
6590 | return mul; | |
6591 | ||
6592 | return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6; | |
6593 | } | |
6594 | ||
6595 | static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) | |
6596 | { | |
6597 | int div, czclk_freq = dev_priv->rps.cz_freq; | |
6598 | ||
6599 | div = vlv_gpu_freq_div(czclk_freq) / 2; | |
6600 | if (div < 0) | |
6601 | return div; | |
6602 | ||
6603 | return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; | |
6604 | } | |
6605 | ||
6606 | static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) | |
6607 | { | |
6608 | int mul, czclk_freq = dev_priv->rps.cz_freq; | |
6609 | ||
6610 | mul = vlv_gpu_freq_div(czclk_freq) / 2; | |
6611 | if (mul < 0) | |
6612 | return mul; | |
6613 | ||
6614 | /* CHV needs even values */ | |
6615 | return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2; | |
6616 | } | |
6617 | ||
6618 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) | |
6619 | { | |
6620 | if (IS_CHERRYVIEW(dev_priv->dev)) | |
6621 | return chv_gpu_freq(dev_priv, val); | |
6622 | else if (IS_VALLEYVIEW(dev_priv->dev)) | |
6623 | return byt_gpu_freq(dev_priv, val); | |
6624 | else | |
6625 | return val * GT_FREQUENCY_MULTIPLIER; | |
6626 | } | |
6627 | ||
6628 | int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val) | |
6629 | { | |
6630 | return intel_gpu_freq(dev_priv, val); | |
6631 | } | |
6632 | ||
6633 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) | |
6634 | { | |
6635 | if (IS_CHERRYVIEW(dev_priv->dev)) | |
6636 | return chv_freq_opcode(dev_priv, val); | |
6637 | else if (IS_VALLEYVIEW(dev_priv->dev)) | |
6638 | return byt_freq_opcode(dev_priv, val); | |
6639 | else | |
6640 | return val / GT_FREQUENCY_MULTIPLIER; | |
6641 | } | |
6642 | ||
6643 | int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val) | |
6644 | { | |
6645 | return intel_freq_opcode(dev_priv, val); | |
6646 | } | |
6647 | ||
6648 | void intel_pm_setup(struct drm_device *dev) | |
6649 | { | |
6650 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6651 | ||
6652 | mutex_init(&dev_priv->rps.hw_lock); | |
6653 | ||
6654 | INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, | |
6655 | intel_gen6_powersave_work); | |
6656 | ||
6657 | dev_priv->pm.suspended = false; | |
6658 | } |