]>
Commit | Line | Data |
---|---|---|
1 | /* | |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2007 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
23 | * DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | * Authors: | |
26 | * Eric Anholt <eric@anholt.net> | |
27 | */ | |
28 | #include <linux/i2c.h> | |
29 | #include <linux/slab.h> | |
30 | #include <linux/delay.h> | |
31 | #include "drmP.h" | |
32 | #include "drm.h" | |
33 | #include "drm_crtc.h" | |
34 | #include "drm_edid.h" | |
35 | #include "intel_drv.h" | |
36 | #include "i915_drm.h" | |
37 | #include "i915_drv.h" | |
38 | #include "intel_sdvo_regs.h" | |
39 | ||
40 | #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) | |
41 | #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) | |
42 | #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) | |
43 | #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0) | |
44 | ||
45 | #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ | |
46 | SDVO_TV_MASK) | |
47 | ||
48 | #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) | |
49 | #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) | |
50 | #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) | |
51 | ||
52 | ||
53 | static const char *tv_format_names[] = { | |
54 | "NTSC_M" , "NTSC_J" , "NTSC_443", | |
55 | "PAL_B" , "PAL_D" , "PAL_G" , | |
56 | "PAL_H" , "PAL_I" , "PAL_M" , | |
57 | "PAL_N" , "PAL_NC" , "PAL_60" , | |
58 | "SECAM_B" , "SECAM_D" , "SECAM_G" , | |
59 | "SECAM_K" , "SECAM_K1", "SECAM_L" , | |
60 | "SECAM_60" | |
61 | }; | |
62 | ||
63 | #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) | |
64 | ||
65 | struct intel_sdvo { | |
66 | struct intel_encoder base; | |
67 | ||
68 | u8 slave_addr; | |
69 | ||
70 | /* Register for the SDVO device: SDVOB or SDVOC */ | |
71 | int sdvo_reg; | |
72 | ||
73 | /* Active outputs controlled by this SDVO output */ | |
74 | uint16_t controlled_output; | |
75 | ||
76 | /* | |
77 | * Capabilities of the SDVO device returned by | |
78 | * i830_sdvo_get_capabilities() | |
79 | */ | |
80 | struct intel_sdvo_caps caps; | |
81 | ||
82 | /* Pixel clock limitations reported by the SDVO device, in kHz */ | |
83 | int pixel_clock_min, pixel_clock_max; | |
84 | ||
85 | /* | |
86 | * For multiple function SDVO device, | |
87 | * this is for current attached outputs. | |
88 | */ | |
89 | uint16_t attached_output; | |
90 | ||
91 | /** | |
92 | * This is set if we're going to treat the device as TV-out. | |
93 | * | |
94 | * While we have these nice friendly flags for output types that ought | |
95 | * to decide this for us, the S-Video output on our HDMI+S-Video card | |
96 | * shows up as RGB1 (VGA). | |
97 | */ | |
98 | bool is_tv; | |
99 | ||
100 | /* This is for current tv format name */ | |
101 | int tv_format_index; | |
102 | ||
103 | /** | |
104 | * This is set if we treat the device as HDMI, instead of DVI. | |
105 | */ | |
106 | bool is_hdmi; | |
107 | ||
108 | /** | |
109 | * This is set if we detect output of sdvo device as LVDS and | |
110 | * have a valid fixed mode to use with the panel. | |
111 | */ | |
112 | bool is_lvds; | |
113 | ||
114 | /** | |
115 | * This is sdvo fixed pannel mode pointer | |
116 | */ | |
117 | struct drm_display_mode *sdvo_lvds_fixed_mode; | |
118 | ||
119 | /* | |
120 | * supported encoding mode, used to determine whether HDMI is | |
121 | * supported | |
122 | */ | |
123 | struct intel_sdvo_encode encode; | |
124 | ||
125 | /* DDC bus used by this SDVO encoder */ | |
126 | uint8_t ddc_bus; | |
127 | ||
128 | /* Mac mini hack -- use the same DDC as the analog connector */ | |
129 | struct i2c_adapter *analog_ddc_bus; | |
130 | ||
131 | /* Input timings for adjusted_mode */ | |
132 | struct intel_sdvo_dtd input_dtd; | |
133 | }; | |
134 | ||
135 | struct intel_sdvo_connector { | |
136 | struct intel_connector base; | |
137 | ||
138 | /* Mark the type of connector */ | |
139 | uint16_t output_flag; | |
140 | ||
141 | /* This contains all current supported TV format */ | |
142 | u8 tv_format_supported[TV_FORMAT_NUM]; | |
143 | int format_supported_num; | |
144 | struct drm_property *tv_format; | |
145 | ||
146 | /* add the property for the SDVO-TV */ | |
147 | struct drm_property *left; | |
148 | struct drm_property *right; | |
149 | struct drm_property *top; | |
150 | struct drm_property *bottom; | |
151 | struct drm_property *hpos; | |
152 | struct drm_property *vpos; | |
153 | struct drm_property *contrast; | |
154 | struct drm_property *saturation; | |
155 | struct drm_property *hue; | |
156 | struct drm_property *sharpness; | |
157 | struct drm_property *flicker_filter; | |
158 | struct drm_property *flicker_filter_adaptive; | |
159 | struct drm_property *flicker_filter_2d; | |
160 | struct drm_property *tv_chroma_filter; | |
161 | struct drm_property *tv_luma_filter; | |
162 | struct drm_property *dot_crawl; | |
163 | ||
164 | /* add the property for the SDVO-TV/LVDS */ | |
165 | struct drm_property *brightness; | |
166 | ||
167 | /* Add variable to record current setting for the above property */ | |
168 | u32 left_margin, right_margin, top_margin, bottom_margin; | |
169 | ||
170 | /* this is to get the range of margin.*/ | |
171 | u32 max_hscan, max_vscan; | |
172 | u32 max_hpos, cur_hpos; | |
173 | u32 max_vpos, cur_vpos; | |
174 | u32 cur_brightness, max_brightness; | |
175 | u32 cur_contrast, max_contrast; | |
176 | u32 cur_saturation, max_saturation; | |
177 | u32 cur_hue, max_hue; | |
178 | u32 cur_sharpness, max_sharpness; | |
179 | u32 cur_flicker_filter, max_flicker_filter; | |
180 | u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; | |
181 | u32 cur_flicker_filter_2d, max_flicker_filter_2d; | |
182 | u32 cur_tv_chroma_filter, max_tv_chroma_filter; | |
183 | u32 cur_tv_luma_filter, max_tv_luma_filter; | |
184 | u32 cur_dot_crawl, max_dot_crawl; | |
185 | }; | |
186 | ||
187 | static struct intel_sdvo *enc_to_intel_sdvo(struct drm_encoder *encoder) | |
188 | { | |
189 | return container_of(enc_to_intel_encoder(encoder), struct intel_sdvo, base); | |
190 | } | |
191 | ||
192 | static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) | |
193 | { | |
194 | return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); | |
195 | } | |
196 | ||
197 | static bool | |
198 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); | |
199 | static bool | |
200 | intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, | |
201 | struct intel_sdvo_connector *intel_sdvo_connector, | |
202 | int type); | |
203 | static bool | |
204 | intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, | |
205 | struct intel_sdvo_connector *intel_sdvo_connector); | |
206 | ||
207 | /** | |
208 | * Writes the SDVOB or SDVOC with the given value, but always writes both | |
209 | * SDVOB and SDVOC to work around apparent hardware issues (according to | |
210 | * comments in the BIOS). | |
211 | */ | |
212 | static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) | |
213 | { | |
214 | struct drm_device *dev = intel_sdvo->base.enc.dev; | |
215 | struct drm_i915_private *dev_priv = dev->dev_private; | |
216 | u32 bval = val, cval = val; | |
217 | int i; | |
218 | ||
219 | if (intel_sdvo->sdvo_reg == PCH_SDVOB) { | |
220 | I915_WRITE(intel_sdvo->sdvo_reg, val); | |
221 | I915_READ(intel_sdvo->sdvo_reg); | |
222 | return; | |
223 | } | |
224 | ||
225 | if (intel_sdvo->sdvo_reg == SDVOB) { | |
226 | cval = I915_READ(SDVOC); | |
227 | } else { | |
228 | bval = I915_READ(SDVOB); | |
229 | } | |
230 | /* | |
231 | * Write the registers twice for luck. Sometimes, | |
232 | * writing them only once doesn't appear to 'stick'. | |
233 | * The BIOS does this too. Yay, magic | |
234 | */ | |
235 | for (i = 0; i < 2; i++) | |
236 | { | |
237 | I915_WRITE(SDVOB, bval); | |
238 | I915_READ(SDVOB); | |
239 | I915_WRITE(SDVOC, cval); | |
240 | I915_READ(SDVOC); | |
241 | } | |
242 | } | |
243 | ||
244 | static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) | |
245 | { | |
246 | u8 out_buf[2] = { addr, 0 }; | |
247 | u8 buf[2]; | |
248 | struct i2c_msg msgs[] = { | |
249 | { | |
250 | .addr = intel_sdvo->slave_addr >> 1, | |
251 | .flags = 0, | |
252 | .len = 1, | |
253 | .buf = out_buf, | |
254 | }, | |
255 | { | |
256 | .addr = intel_sdvo->slave_addr >> 1, | |
257 | .flags = I2C_M_RD, | |
258 | .len = 1, | |
259 | .buf = buf, | |
260 | } | |
261 | }; | |
262 | int ret; | |
263 | ||
264 | if ((ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 2)) == 2) | |
265 | { | |
266 | *ch = buf[0]; | |
267 | return true; | |
268 | } | |
269 | ||
270 | DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); | |
271 | return false; | |
272 | } | |
273 | ||
274 | static bool intel_sdvo_write_byte(struct intel_sdvo *intel_sdvo, int addr, u8 ch) | |
275 | { | |
276 | u8 out_buf[2] = { addr, ch }; | |
277 | struct i2c_msg msgs[] = { | |
278 | { | |
279 | .addr = intel_sdvo->slave_addr >> 1, | |
280 | .flags = 0, | |
281 | .len = 2, | |
282 | .buf = out_buf, | |
283 | } | |
284 | }; | |
285 | ||
286 | return i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 1) == 1; | |
287 | } | |
288 | ||
289 | #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} | |
290 | /** Mapping of command numbers to names, for debug output */ | |
291 | static const struct _sdvo_cmd_name { | |
292 | u8 cmd; | |
293 | const char *name; | |
294 | } sdvo_cmd_names[] = { | |
295 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), | |
296 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), | |
297 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), | |
298 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), | |
299 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), | |
300 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), | |
301 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), | |
302 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), | |
303 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), | |
304 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), | |
305 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), | |
306 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), | |
307 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), | |
308 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), | |
309 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), | |
310 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), | |
311 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), | |
312 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), | |
313 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), | |
314 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), | |
315 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), | |
316 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), | |
317 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), | |
318 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), | |
319 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), | |
320 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), | |
321 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), | |
322 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), | |
323 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), | |
324 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), | |
325 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), | |
326 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), | |
327 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), | |
328 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), | |
329 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), | |
330 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), | |
331 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), | |
332 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), | |
333 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), | |
334 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), | |
335 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), | |
336 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), | |
337 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), | |
338 | ||
339 | /* Add the op code for SDVO enhancements */ | |
340 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), | |
341 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), | |
342 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), | |
343 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), | |
344 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), | |
345 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), | |
346 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), | |
347 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), | |
348 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), | |
349 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), | |
350 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), | |
351 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), | |
352 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), | |
353 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), | |
354 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), | |
355 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), | |
356 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), | |
357 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), | |
358 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), | |
359 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), | |
360 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), | |
361 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), | |
362 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), | |
363 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), | |
364 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), | |
365 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), | |
366 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), | |
367 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), | |
368 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), | |
369 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), | |
370 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), | |
371 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), | |
372 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), | |
373 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), | |
374 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), | |
375 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), | |
376 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), | |
377 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), | |
378 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), | |
379 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), | |
380 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), | |
381 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), | |
382 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), | |
383 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), | |
384 | ||
385 | /* HDMI op code */ | |
386 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), | |
387 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), | |
388 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), | |
389 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), | |
390 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), | |
391 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), | |
392 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), | |
393 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), | |
394 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), | |
395 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), | |
396 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), | |
397 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), | |
398 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), | |
399 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), | |
400 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), | |
401 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), | |
402 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), | |
403 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), | |
404 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), | |
405 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), | |
406 | }; | |
407 | ||
408 | #define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB) | |
409 | #define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC") | |
410 | ||
411 | static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, | |
412 | const void *args, int args_len) | |
413 | { | |
414 | int i; | |
415 | ||
416 | DRM_DEBUG_KMS("%s: W: %02X ", | |
417 | SDVO_NAME(intel_sdvo), cmd); | |
418 | for (i = 0; i < args_len; i++) | |
419 | DRM_LOG_KMS("%02X ", ((u8 *)args)[i]); | |
420 | for (; i < 8; i++) | |
421 | DRM_LOG_KMS(" "); | |
422 | for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { | |
423 | if (cmd == sdvo_cmd_names[i].cmd) { | |
424 | DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name); | |
425 | break; | |
426 | } | |
427 | } | |
428 | if (i == ARRAY_SIZE(sdvo_cmd_names)) | |
429 | DRM_LOG_KMS("(%02X)", cmd); | |
430 | DRM_LOG_KMS("\n"); | |
431 | } | |
432 | ||
433 | static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, | |
434 | const void *args, int args_len) | |
435 | { | |
436 | int i; | |
437 | ||
438 | intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); | |
439 | ||
440 | for (i = 0; i < args_len; i++) { | |
441 | if (!intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0 - i, | |
442 | ((u8*)args)[i])) | |
443 | return false; | |
444 | } | |
445 | ||
446 | return intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_OPCODE, cmd); | |
447 | } | |
448 | ||
449 | static const char *cmd_status_names[] = { | |
450 | "Power on", | |
451 | "Success", | |
452 | "Not supported", | |
453 | "Invalid arg", | |
454 | "Pending", | |
455 | "Target not specified", | |
456 | "Scaling not supported" | |
457 | }; | |
458 | ||
459 | static void intel_sdvo_debug_response(struct intel_sdvo *intel_sdvo, | |
460 | void *response, int response_len, | |
461 | u8 status) | |
462 | { | |
463 | int i; | |
464 | ||
465 | DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo)); | |
466 | for (i = 0; i < response_len; i++) | |
467 | DRM_LOG_KMS("%02X ", ((u8 *)response)[i]); | |
468 | for (; i < 8; i++) | |
469 | DRM_LOG_KMS(" "); | |
470 | if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) | |
471 | DRM_LOG_KMS("(%s)", cmd_status_names[status]); | |
472 | else | |
473 | DRM_LOG_KMS("(??? %d)", status); | |
474 | DRM_LOG_KMS("\n"); | |
475 | } | |
476 | ||
477 | static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, | |
478 | void *response, int response_len) | |
479 | { | |
480 | int i; | |
481 | u8 status; | |
482 | u8 retry = 50; | |
483 | ||
484 | while (retry--) { | |
485 | /* Read the command response */ | |
486 | for (i = 0; i < response_len; i++) { | |
487 | if (!intel_sdvo_read_byte(intel_sdvo, | |
488 | SDVO_I2C_RETURN_0 + i, | |
489 | &((u8 *)response)[i])) | |
490 | return false; | |
491 | } | |
492 | ||
493 | /* read the return status */ | |
494 | if (!intel_sdvo_read_byte(intel_sdvo, SDVO_I2C_CMD_STATUS, | |
495 | &status)) | |
496 | return false; | |
497 | ||
498 | intel_sdvo_debug_response(intel_sdvo, response, response_len, | |
499 | status); | |
500 | if (status != SDVO_CMD_STATUS_PENDING) | |
501 | break; | |
502 | ||
503 | mdelay(50); | |
504 | } | |
505 | ||
506 | return status == SDVO_CMD_STATUS_SUCCESS; | |
507 | } | |
508 | ||
509 | static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) | |
510 | { | |
511 | if (mode->clock >= 100000) | |
512 | return 1; | |
513 | else if (mode->clock >= 50000) | |
514 | return 2; | |
515 | else | |
516 | return 4; | |
517 | } | |
518 | ||
519 | /** | |
520 | * Try to read the response after issuie the DDC switch command. But it | |
521 | * is noted that we must do the action of reading response and issuing DDC | |
522 | * switch command in one I2C transaction. Otherwise when we try to start | |
523 | * another I2C transaction after issuing the DDC bus switch, it will be | |
524 | * switched to the internal SDVO register. | |
525 | */ | |
526 | static void intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, | |
527 | u8 target) | |
528 | { | |
529 | u8 out_buf[2], cmd_buf[2], ret_value[2], ret; | |
530 | struct i2c_msg msgs[] = { | |
531 | { | |
532 | .addr = intel_sdvo->slave_addr >> 1, | |
533 | .flags = 0, | |
534 | .len = 2, | |
535 | .buf = out_buf, | |
536 | }, | |
537 | /* the following two are to read the response */ | |
538 | { | |
539 | .addr = intel_sdvo->slave_addr >> 1, | |
540 | .flags = 0, | |
541 | .len = 1, | |
542 | .buf = cmd_buf, | |
543 | }, | |
544 | { | |
545 | .addr = intel_sdvo->slave_addr >> 1, | |
546 | .flags = I2C_M_RD, | |
547 | .len = 1, | |
548 | .buf = ret_value, | |
549 | }, | |
550 | }; | |
551 | ||
552 | intel_sdvo_debug_write(intel_sdvo, SDVO_CMD_SET_CONTROL_BUS_SWITCH, | |
553 | &target, 1); | |
554 | /* write the DDC switch command argument */ | |
555 | intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0, target); | |
556 | ||
557 | out_buf[0] = SDVO_I2C_OPCODE; | |
558 | out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH; | |
559 | cmd_buf[0] = SDVO_I2C_CMD_STATUS; | |
560 | cmd_buf[1] = 0; | |
561 | ret_value[0] = 0; | |
562 | ret_value[1] = 0; | |
563 | ||
564 | ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 3); | |
565 | if (ret != 3) { | |
566 | /* failure in I2C transfer */ | |
567 | DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); | |
568 | return; | |
569 | } | |
570 | if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) { | |
571 | DRM_DEBUG_KMS("DDC switch command returns response %d\n", | |
572 | ret_value[0]); | |
573 | return; | |
574 | } | |
575 | return; | |
576 | } | |
577 | ||
578 | static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) | |
579 | { | |
580 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) | |
581 | return false; | |
582 | ||
583 | return intel_sdvo_read_response(intel_sdvo, NULL, 0); | |
584 | } | |
585 | ||
586 | static bool | |
587 | intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) | |
588 | { | |
589 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) | |
590 | return false; | |
591 | ||
592 | return intel_sdvo_read_response(intel_sdvo, value, len); | |
593 | } | |
594 | ||
595 | static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) | |
596 | { | |
597 | struct intel_sdvo_set_target_input_args targets = {0}; | |
598 | return intel_sdvo_set_value(intel_sdvo, | |
599 | SDVO_CMD_SET_TARGET_INPUT, | |
600 | &targets, sizeof(targets)); | |
601 | } | |
602 | ||
603 | /** | |
604 | * Return whether each input is trained. | |
605 | * | |
606 | * This function is making an assumption about the layout of the response, | |
607 | * which should be checked against the docs. | |
608 | */ | |
609 | static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) | |
610 | { | |
611 | struct intel_sdvo_get_trained_inputs_response response; | |
612 | ||
613 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, | |
614 | &response, sizeof(response))) | |
615 | return false; | |
616 | ||
617 | *input_1 = response.input0_trained; | |
618 | *input_2 = response.input1_trained; | |
619 | return true; | |
620 | } | |
621 | ||
622 | static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, | |
623 | u16 outputs) | |
624 | { | |
625 | return intel_sdvo_set_value(intel_sdvo, | |
626 | SDVO_CMD_SET_ACTIVE_OUTPUTS, | |
627 | &outputs, sizeof(outputs)); | |
628 | } | |
629 | ||
630 | static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, | |
631 | int mode) | |
632 | { | |
633 | u8 state = SDVO_ENCODER_STATE_ON; | |
634 | ||
635 | switch (mode) { | |
636 | case DRM_MODE_DPMS_ON: | |
637 | state = SDVO_ENCODER_STATE_ON; | |
638 | break; | |
639 | case DRM_MODE_DPMS_STANDBY: | |
640 | state = SDVO_ENCODER_STATE_STANDBY; | |
641 | break; | |
642 | case DRM_MODE_DPMS_SUSPEND: | |
643 | state = SDVO_ENCODER_STATE_SUSPEND; | |
644 | break; | |
645 | case DRM_MODE_DPMS_OFF: | |
646 | state = SDVO_ENCODER_STATE_OFF; | |
647 | break; | |
648 | } | |
649 | ||
650 | return intel_sdvo_set_value(intel_sdvo, | |
651 | SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); | |
652 | } | |
653 | ||
654 | static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, | |
655 | int *clock_min, | |
656 | int *clock_max) | |
657 | { | |
658 | struct intel_sdvo_pixel_clock_range clocks; | |
659 | ||
660 | if (!intel_sdvo_get_value(intel_sdvo, | |
661 | SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, | |
662 | &clocks, sizeof(clocks))) | |
663 | return false; | |
664 | ||
665 | /* Convert the values from units of 10 kHz to kHz. */ | |
666 | *clock_min = clocks.min * 10; | |
667 | *clock_max = clocks.max * 10; | |
668 | return true; | |
669 | } | |
670 | ||
671 | static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, | |
672 | u16 outputs) | |
673 | { | |
674 | return intel_sdvo_set_value(intel_sdvo, | |
675 | SDVO_CMD_SET_TARGET_OUTPUT, | |
676 | &outputs, sizeof(outputs)); | |
677 | } | |
678 | ||
679 | static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, | |
680 | struct intel_sdvo_dtd *dtd) | |
681 | { | |
682 | return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && | |
683 | intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); | |
684 | } | |
685 | ||
686 | static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, | |
687 | struct intel_sdvo_dtd *dtd) | |
688 | { | |
689 | return intel_sdvo_set_timing(intel_sdvo, | |
690 | SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); | |
691 | } | |
692 | ||
693 | static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, | |
694 | struct intel_sdvo_dtd *dtd) | |
695 | { | |
696 | return intel_sdvo_set_timing(intel_sdvo, | |
697 | SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); | |
698 | } | |
699 | ||
700 | static bool | |
701 | intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, | |
702 | uint16_t clock, | |
703 | uint16_t width, | |
704 | uint16_t height) | |
705 | { | |
706 | struct intel_sdvo_preferred_input_timing_args args; | |
707 | ||
708 | memset(&args, 0, sizeof(args)); | |
709 | args.clock = clock; | |
710 | args.width = width; | |
711 | args.height = height; | |
712 | args.interlace = 0; | |
713 | ||
714 | if (intel_sdvo->is_lvds && | |
715 | (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || | |
716 | intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) | |
717 | args.scaled = 1; | |
718 | ||
719 | return intel_sdvo_set_value(intel_sdvo, | |
720 | SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, | |
721 | &args, sizeof(args)); | |
722 | } | |
723 | ||
724 | static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, | |
725 | struct intel_sdvo_dtd *dtd) | |
726 | { | |
727 | return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, | |
728 | &dtd->part1, sizeof(dtd->part1)) && | |
729 | intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, | |
730 | &dtd->part2, sizeof(dtd->part2)); | |
731 | } | |
732 | ||
733 | static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) | |
734 | { | |
735 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); | |
736 | } | |
737 | ||
738 | static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, | |
739 | const struct drm_display_mode *mode) | |
740 | { | |
741 | uint16_t width, height; | |
742 | uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; | |
743 | uint16_t h_sync_offset, v_sync_offset; | |
744 | ||
745 | width = mode->crtc_hdisplay; | |
746 | height = mode->crtc_vdisplay; | |
747 | ||
748 | /* do some mode translations */ | |
749 | h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start; | |
750 | h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
751 | ||
752 | v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start; | |
753 | v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
754 | ||
755 | h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start; | |
756 | v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start; | |
757 | ||
758 | dtd->part1.clock = mode->clock / 10; | |
759 | dtd->part1.h_active = width & 0xff; | |
760 | dtd->part1.h_blank = h_blank_len & 0xff; | |
761 | dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | | |
762 | ((h_blank_len >> 8) & 0xf); | |
763 | dtd->part1.v_active = height & 0xff; | |
764 | dtd->part1.v_blank = v_blank_len & 0xff; | |
765 | dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | | |
766 | ((v_blank_len >> 8) & 0xf); | |
767 | ||
768 | dtd->part2.h_sync_off = h_sync_offset & 0xff; | |
769 | dtd->part2.h_sync_width = h_sync_len & 0xff; | |
770 | dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | | |
771 | (v_sync_len & 0xf); | |
772 | dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | | |
773 | ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | | |
774 | ((v_sync_len & 0x30) >> 4); | |
775 | ||
776 | dtd->part2.dtd_flags = 0x18; | |
777 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) | |
778 | dtd->part2.dtd_flags |= 0x2; | |
779 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) | |
780 | dtd->part2.dtd_flags |= 0x4; | |
781 | ||
782 | dtd->part2.sdvo_flags = 0; | |
783 | dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; | |
784 | dtd->part2.reserved = 0; | |
785 | } | |
786 | ||
787 | static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode, | |
788 | const struct intel_sdvo_dtd *dtd) | |
789 | { | |
790 | mode->hdisplay = dtd->part1.h_active; | |
791 | mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; | |
792 | mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off; | |
793 | mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; | |
794 | mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width; | |
795 | mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; | |
796 | mode->htotal = mode->hdisplay + dtd->part1.h_blank; | |
797 | mode->htotal += (dtd->part1.h_high & 0xf) << 8; | |
798 | ||
799 | mode->vdisplay = dtd->part1.v_active; | |
800 | mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; | |
801 | mode->vsync_start = mode->vdisplay; | |
802 | mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; | |
803 | mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; | |
804 | mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0; | |
805 | mode->vsync_end = mode->vsync_start + | |
806 | (dtd->part2.v_sync_off_width & 0xf); | |
807 | mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; | |
808 | mode->vtotal = mode->vdisplay + dtd->part1.v_blank; | |
809 | mode->vtotal += (dtd->part1.v_high & 0xf) << 8; | |
810 | ||
811 | mode->clock = dtd->part1.clock * 10; | |
812 | ||
813 | mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); | |
814 | if (dtd->part2.dtd_flags & 0x2) | |
815 | mode->flags |= DRM_MODE_FLAG_PHSYNC; | |
816 | if (dtd->part2.dtd_flags & 0x4) | |
817 | mode->flags |= DRM_MODE_FLAG_PVSYNC; | |
818 | } | |
819 | ||
820 | static bool intel_sdvo_get_supp_encode(struct intel_sdvo *intel_sdvo, | |
821 | struct intel_sdvo_encode *encode) | |
822 | { | |
823 | if (intel_sdvo_get_value(intel_sdvo, | |
824 | SDVO_CMD_GET_SUPP_ENCODE, | |
825 | encode, sizeof(*encode))) | |
826 | return true; | |
827 | ||
828 | /* non-support means DVI */ | |
829 | memset(encode, 0, sizeof(*encode)); | |
830 | return false; | |
831 | } | |
832 | ||
833 | static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, | |
834 | uint8_t mode) | |
835 | { | |
836 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); | |
837 | } | |
838 | ||
839 | static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, | |
840 | uint8_t mode) | |
841 | { | |
842 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); | |
843 | } | |
844 | ||
845 | #if 0 | |
846 | static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) | |
847 | { | |
848 | int i, j; | |
849 | uint8_t set_buf_index[2]; | |
850 | uint8_t av_split; | |
851 | uint8_t buf_size; | |
852 | uint8_t buf[48]; | |
853 | uint8_t *pos; | |
854 | ||
855 | intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); | |
856 | ||
857 | for (i = 0; i <= av_split; i++) { | |
858 | set_buf_index[0] = i; set_buf_index[1] = 0; | |
859 | intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, | |
860 | set_buf_index, 2); | |
861 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); | |
862 | intel_sdvo_read_response(encoder, &buf_size, 1); | |
863 | ||
864 | pos = buf; | |
865 | for (j = 0; j <= buf_size; j += 8) { | |
866 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, | |
867 | NULL, 0); | |
868 | intel_sdvo_read_response(encoder, pos, 8); | |
869 | pos += 8; | |
870 | } | |
871 | } | |
872 | } | |
873 | #endif | |
874 | ||
875 | static bool intel_sdvo_set_hdmi_buf(struct intel_sdvo *intel_sdvo, | |
876 | int index, | |
877 | uint8_t *data, int8_t size, uint8_t tx_rate) | |
878 | { | |
879 | uint8_t set_buf_index[2]; | |
880 | ||
881 | set_buf_index[0] = index; | |
882 | set_buf_index[1] = 0; | |
883 | ||
884 | if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_INDEX, | |
885 | set_buf_index, 2)) | |
886 | return false; | |
887 | ||
888 | for (; size > 0; size -= 8) { | |
889 | if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_DATA, data, 8)) | |
890 | return false; | |
891 | ||
892 | data += 8; | |
893 | } | |
894 | ||
895 | return intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1); | |
896 | } | |
897 | ||
898 | static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size) | |
899 | { | |
900 | uint8_t csum = 0; | |
901 | int i; | |
902 | ||
903 | for (i = 0; i < size; i++) | |
904 | csum += data[i]; | |
905 | ||
906 | return 0x100 - csum; | |
907 | } | |
908 | ||
909 | #define DIP_TYPE_AVI 0x82 | |
910 | #define DIP_VERSION_AVI 0x2 | |
911 | #define DIP_LEN_AVI 13 | |
912 | ||
913 | struct dip_infoframe { | |
914 | uint8_t type; | |
915 | uint8_t version; | |
916 | uint8_t len; | |
917 | uint8_t checksum; | |
918 | union { | |
919 | struct { | |
920 | /* Packet Byte #1 */ | |
921 | uint8_t S:2; | |
922 | uint8_t B:2; | |
923 | uint8_t A:1; | |
924 | uint8_t Y:2; | |
925 | uint8_t rsvd1:1; | |
926 | /* Packet Byte #2 */ | |
927 | uint8_t R:4; | |
928 | uint8_t M:2; | |
929 | uint8_t C:2; | |
930 | /* Packet Byte #3 */ | |
931 | uint8_t SC:2; | |
932 | uint8_t Q:2; | |
933 | uint8_t EC:3; | |
934 | uint8_t ITC:1; | |
935 | /* Packet Byte #4 */ | |
936 | uint8_t VIC:7; | |
937 | uint8_t rsvd2:1; | |
938 | /* Packet Byte #5 */ | |
939 | uint8_t PR:4; | |
940 | uint8_t rsvd3:4; | |
941 | /* Packet Byte #6~13 */ | |
942 | uint16_t top_bar_end; | |
943 | uint16_t bottom_bar_start; | |
944 | uint16_t left_bar_end; | |
945 | uint16_t right_bar_start; | |
946 | } avi; | |
947 | struct { | |
948 | /* Packet Byte #1 */ | |
949 | uint8_t channel_count:3; | |
950 | uint8_t rsvd1:1; | |
951 | uint8_t coding_type:4; | |
952 | /* Packet Byte #2 */ | |
953 | uint8_t sample_size:2; /* SS0, SS1 */ | |
954 | uint8_t sample_frequency:3; | |
955 | uint8_t rsvd2:3; | |
956 | /* Packet Byte #3 */ | |
957 | uint8_t coding_type_private:5; | |
958 | uint8_t rsvd3:3; | |
959 | /* Packet Byte #4 */ | |
960 | uint8_t channel_allocation; | |
961 | /* Packet Byte #5 */ | |
962 | uint8_t rsvd4:3; | |
963 | uint8_t level_shift:4; | |
964 | uint8_t downmix_inhibit:1; | |
965 | } audio; | |
966 | uint8_t payload[28]; | |
967 | } __attribute__ ((packed)) u; | |
968 | } __attribute__((packed)); | |
969 | ||
970 | static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, | |
971 | struct drm_display_mode * mode) | |
972 | { | |
973 | struct dip_infoframe avi_if = { | |
974 | .type = DIP_TYPE_AVI, | |
975 | .version = DIP_VERSION_AVI, | |
976 | .len = DIP_LEN_AVI, | |
977 | }; | |
978 | ||
979 | avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if, | |
980 | 4 + avi_if.len); | |
981 | return intel_sdvo_set_hdmi_buf(intel_sdvo, 1, (uint8_t *)&avi_if, | |
982 | 4 + avi_if.len, | |
983 | SDVO_HBUF_TX_VSYNC); | |
984 | } | |
985 | ||
986 | static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) | |
987 | { | |
988 | struct intel_sdvo_tv_format format; | |
989 | uint32_t format_map; | |
990 | ||
991 | format_map = 1 << intel_sdvo->tv_format_index; | |
992 | memset(&format, 0, sizeof(format)); | |
993 | memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); | |
994 | ||
995 | BUILD_BUG_ON(sizeof(format) != 6); | |
996 | return intel_sdvo_set_value(intel_sdvo, | |
997 | SDVO_CMD_SET_TV_FORMAT, | |
998 | &format, sizeof(format)); | |
999 | } | |
1000 | ||
1001 | static bool | |
1002 | intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, | |
1003 | struct drm_display_mode *mode) | |
1004 | { | |
1005 | struct intel_sdvo_dtd output_dtd; | |
1006 | ||
1007 | if (!intel_sdvo_set_target_output(intel_sdvo, | |
1008 | intel_sdvo->attached_output)) | |
1009 | return false; | |
1010 | ||
1011 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); | |
1012 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) | |
1013 | return false; | |
1014 | ||
1015 | return true; | |
1016 | } | |
1017 | ||
1018 | static bool | |
1019 | intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo, | |
1020 | struct drm_display_mode *mode, | |
1021 | struct drm_display_mode *adjusted_mode) | |
1022 | { | |
1023 | /* Reset the input timing to the screen. Assume always input 0. */ | |
1024 | if (!intel_sdvo_set_target_input(intel_sdvo)) | |
1025 | return false; | |
1026 | ||
1027 | if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, | |
1028 | mode->clock / 10, | |
1029 | mode->hdisplay, | |
1030 | mode->vdisplay)) | |
1031 | return false; | |
1032 | ||
1033 | if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, | |
1034 | &intel_sdvo->input_dtd)) | |
1035 | return false; | |
1036 | ||
1037 | intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd); | |
1038 | ||
1039 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
1040 | return true; | |
1041 | } | |
1042 | ||
1043 | static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder, | |
1044 | struct drm_display_mode *mode, | |
1045 | struct drm_display_mode *adjusted_mode) | |
1046 | { | |
1047 | struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); | |
1048 | int multiplier; | |
1049 | ||
1050 | /* We need to construct preferred input timings based on our | |
1051 | * output timings. To do that, we have to set the output | |
1052 | * timings, even though this isn't really the right place in | |
1053 | * the sequence to do it. Oh well. | |
1054 | */ | |
1055 | if (intel_sdvo->is_tv) { | |
1056 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) | |
1057 | return false; | |
1058 | ||
1059 | (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo, | |
1060 | mode, | |
1061 | adjusted_mode); | |
1062 | } else if (intel_sdvo->is_lvds) { | |
1063 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, | |
1064 | intel_sdvo->sdvo_lvds_fixed_mode)) | |
1065 | return false; | |
1066 | ||
1067 | (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo, | |
1068 | mode, | |
1069 | adjusted_mode); | |
1070 | } | |
1071 | ||
1072 | /* Make the CRTC code factor in the SDVO pixel multiplier. The | |
1073 | * SDVO device will factor out the multiplier during mode_set. | |
1074 | */ | |
1075 | multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode); | |
1076 | intel_mode_set_pixel_multiplier(adjusted_mode, multiplier); | |
1077 | ||
1078 | return true; | |
1079 | } | |
1080 | ||
1081 | static void intel_sdvo_mode_set(struct drm_encoder *encoder, | |
1082 | struct drm_display_mode *mode, | |
1083 | struct drm_display_mode *adjusted_mode) | |
1084 | { | |
1085 | struct drm_device *dev = encoder->dev; | |
1086 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1087 | struct drm_crtc *crtc = encoder->crtc; | |
1088 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1089 | struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); | |
1090 | u32 sdvox; | |
1091 | struct intel_sdvo_in_out_map in_out; | |
1092 | struct intel_sdvo_dtd input_dtd; | |
1093 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); | |
1094 | int rate; | |
1095 | ||
1096 | if (!mode) | |
1097 | return; | |
1098 | ||
1099 | /* First, set the input mapping for the first input to our controlled | |
1100 | * output. This is only correct if we're a single-input device, in | |
1101 | * which case the first input is the output from the appropriate SDVO | |
1102 | * channel on the motherboard. In a two-input device, the first input | |
1103 | * will be SDVOB and the second SDVOC. | |
1104 | */ | |
1105 | in_out.in0 = intel_sdvo->attached_output; | |
1106 | in_out.in1 = 0; | |
1107 | ||
1108 | intel_sdvo_set_value(intel_sdvo, | |
1109 | SDVO_CMD_SET_IN_OUT_MAP, | |
1110 | &in_out, sizeof(in_out)); | |
1111 | ||
1112 | /* Set the output timings to the screen */ | |
1113 | if (!intel_sdvo_set_target_output(intel_sdvo, | |
1114 | intel_sdvo->attached_output)) | |
1115 | return; | |
1116 | ||
1117 | /* We have tried to get input timing in mode_fixup, and filled into | |
1118 | * adjusted_mode. | |
1119 | */ | |
1120 | if (intel_sdvo->is_tv || intel_sdvo->is_lvds) { | |
1121 | input_dtd = intel_sdvo->input_dtd; | |
1122 | } else { | |
1123 | /* Set the output timing to the screen */ | |
1124 | if (!intel_sdvo_set_target_output(intel_sdvo, | |
1125 | intel_sdvo->attached_output)) | |
1126 | return; | |
1127 | ||
1128 | intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); | |
1129 | (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd); | |
1130 | } | |
1131 | ||
1132 | /* Set the input timing to the screen. Assume always input 0. */ | |
1133 | if (!intel_sdvo_set_target_input(intel_sdvo)) | |
1134 | return; | |
1135 | ||
1136 | if (intel_sdvo->is_hdmi && | |
1137 | !intel_sdvo_set_avi_infoframe(intel_sdvo, mode)) | |
1138 | return; | |
1139 | ||
1140 | if (intel_sdvo->is_tv && | |
1141 | !intel_sdvo_set_tv_format(intel_sdvo)) | |
1142 | return; | |
1143 | ||
1144 | (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd); | |
1145 | ||
1146 | switch (pixel_multiplier) { | |
1147 | default: | |
1148 | case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; | |
1149 | case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; | |
1150 | case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; | |
1151 | } | |
1152 | if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) | |
1153 | return; | |
1154 | ||
1155 | /* Set the SDVO control regs. */ | |
1156 | if (IS_I965G(dev)) { | |
1157 | sdvox = SDVO_BORDER_ENABLE; | |
1158 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1159 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; | |
1160 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
1161 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; | |
1162 | } else { | |
1163 | sdvox = I915_READ(intel_sdvo->sdvo_reg); | |
1164 | switch (intel_sdvo->sdvo_reg) { | |
1165 | case SDVOB: | |
1166 | sdvox &= SDVOB_PRESERVE_MASK; | |
1167 | break; | |
1168 | case SDVOC: | |
1169 | sdvox &= SDVOC_PRESERVE_MASK; | |
1170 | break; | |
1171 | } | |
1172 | sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; | |
1173 | } | |
1174 | if (intel_crtc->pipe == 1) | |
1175 | sdvox |= SDVO_PIPE_B_SELECT; | |
1176 | if (intel_sdvo->is_hdmi) | |
1177 | sdvox |= SDVO_AUDIO_ENABLE; | |
1178 | ||
1179 | if (IS_I965G(dev)) { | |
1180 | /* done in crtc_mode_set as the dpll_md reg must be written early */ | |
1181 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { | |
1182 | /* done in crtc_mode_set as it lives inside the dpll register */ | |
1183 | } else { | |
1184 | sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT; | |
1185 | } | |
1186 | ||
1187 | if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL) | |
1188 | sdvox |= SDVO_STALL_SELECT; | |
1189 | intel_sdvo_write_sdvox(intel_sdvo, sdvox); | |
1190 | } | |
1191 | ||
1192 | static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode) | |
1193 | { | |
1194 | struct drm_device *dev = encoder->dev; | |
1195 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1196 | struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); | |
1197 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
1198 | u32 temp; | |
1199 | ||
1200 | if (mode != DRM_MODE_DPMS_ON) { | |
1201 | intel_sdvo_set_active_outputs(intel_sdvo, 0); | |
1202 | if (0) | |
1203 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); | |
1204 | ||
1205 | if (mode == DRM_MODE_DPMS_OFF) { | |
1206 | temp = I915_READ(intel_sdvo->sdvo_reg); | |
1207 | if ((temp & SDVO_ENABLE) != 0) { | |
1208 | intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE); | |
1209 | } | |
1210 | } | |
1211 | } else { | |
1212 | bool input1, input2; | |
1213 | int i; | |
1214 | u8 status; | |
1215 | ||
1216 | temp = I915_READ(intel_sdvo->sdvo_reg); | |
1217 | if ((temp & SDVO_ENABLE) == 0) | |
1218 | intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE); | |
1219 | for (i = 0; i < 2; i++) | |
1220 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1221 | ||
1222 | status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); | |
1223 | /* Warn if the device reported failure to sync. | |
1224 | * A lot of SDVO devices fail to notify of sync, but it's | |
1225 | * a given it the status is a success, we succeeded. | |
1226 | */ | |
1227 | if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { | |
1228 | DRM_DEBUG_KMS("First %s output reported failure to " | |
1229 | "sync\n", SDVO_NAME(intel_sdvo)); | |
1230 | } | |
1231 | ||
1232 | if (0) | |
1233 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); | |
1234 | intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); | |
1235 | } | |
1236 | return; | |
1237 | } | |
1238 | ||
1239 | static int intel_sdvo_mode_valid(struct drm_connector *connector, | |
1240 | struct drm_display_mode *mode) | |
1241 | { | |
1242 | struct drm_encoder *encoder = intel_attached_encoder(connector); | |
1243 | struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); | |
1244 | ||
1245 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
1246 | return MODE_NO_DBLESCAN; | |
1247 | ||
1248 | if (intel_sdvo->pixel_clock_min > mode->clock) | |
1249 | return MODE_CLOCK_LOW; | |
1250 | ||
1251 | if (intel_sdvo->pixel_clock_max < mode->clock) | |
1252 | return MODE_CLOCK_HIGH; | |
1253 | ||
1254 | if (intel_sdvo->is_lvds) { | |
1255 | if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) | |
1256 | return MODE_PANEL; | |
1257 | ||
1258 | if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) | |
1259 | return MODE_PANEL; | |
1260 | } | |
1261 | ||
1262 | return MODE_OK; | |
1263 | } | |
1264 | ||
1265 | static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) | |
1266 | { | |
1267 | return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DEVICE_CAPS, caps, sizeof(*caps)); | |
1268 | } | |
1269 | ||
1270 | /* No use! */ | |
1271 | #if 0 | |
1272 | struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB) | |
1273 | { | |
1274 | struct drm_connector *connector = NULL; | |
1275 | struct intel_sdvo *iout = NULL; | |
1276 | struct intel_sdvo *sdvo; | |
1277 | ||
1278 | /* find the sdvo connector */ | |
1279 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1280 | iout = to_intel_sdvo(connector); | |
1281 | ||
1282 | if (iout->type != INTEL_OUTPUT_SDVO) | |
1283 | continue; | |
1284 | ||
1285 | sdvo = iout->dev_priv; | |
1286 | ||
1287 | if (sdvo->sdvo_reg == SDVOB && sdvoB) | |
1288 | return connector; | |
1289 | ||
1290 | if (sdvo->sdvo_reg == SDVOC && !sdvoB) | |
1291 | return connector; | |
1292 | ||
1293 | } | |
1294 | ||
1295 | return NULL; | |
1296 | } | |
1297 | ||
1298 | int intel_sdvo_supports_hotplug(struct drm_connector *connector) | |
1299 | { | |
1300 | u8 response[2]; | |
1301 | u8 status; | |
1302 | struct intel_sdvo *intel_sdvo; | |
1303 | DRM_DEBUG_KMS("\n"); | |
1304 | ||
1305 | if (!connector) | |
1306 | return 0; | |
1307 | ||
1308 | intel_sdvo = to_intel_sdvo(connector); | |
1309 | ||
1310 | return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, | |
1311 | &response, 2) && response[0]; | |
1312 | } | |
1313 | ||
1314 | void intel_sdvo_set_hotplug(struct drm_connector *connector, int on) | |
1315 | { | |
1316 | u8 response[2]; | |
1317 | u8 status; | |
1318 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(connector); | |
1319 | ||
1320 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0); | |
1321 | intel_sdvo_read_response(intel_sdvo, &response, 2); | |
1322 | ||
1323 | if (on) { | |
1324 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0); | |
1325 | status = intel_sdvo_read_response(intel_sdvo, &response, 2); | |
1326 | ||
1327 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2); | |
1328 | } else { | |
1329 | response[0] = 0; | |
1330 | response[1] = 0; | |
1331 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2); | |
1332 | } | |
1333 | ||
1334 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0); | |
1335 | intel_sdvo_read_response(intel_sdvo, &response, 2); | |
1336 | } | |
1337 | #endif | |
1338 | ||
1339 | static bool | |
1340 | intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) | |
1341 | { | |
1342 | int caps = 0; | |
1343 | ||
1344 | if (intel_sdvo->caps.output_flags & | |
1345 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) | |
1346 | caps++; | |
1347 | if (intel_sdvo->caps.output_flags & | |
1348 | (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)) | |
1349 | caps++; | |
1350 | if (intel_sdvo->caps.output_flags & | |
1351 | (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1)) | |
1352 | caps++; | |
1353 | if (intel_sdvo->caps.output_flags & | |
1354 | (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1)) | |
1355 | caps++; | |
1356 | if (intel_sdvo->caps.output_flags & | |
1357 | (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1)) | |
1358 | caps++; | |
1359 | ||
1360 | if (intel_sdvo->caps.output_flags & | |
1361 | (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1)) | |
1362 | caps++; | |
1363 | ||
1364 | if (intel_sdvo->caps.output_flags & | |
1365 | (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)) | |
1366 | caps++; | |
1367 | ||
1368 | return (caps > 1); | |
1369 | } | |
1370 | ||
1371 | static struct drm_connector * | |
1372 | intel_find_analog_connector(struct drm_device *dev) | |
1373 | { | |
1374 | struct drm_connector *connector; | |
1375 | struct drm_encoder *encoder; | |
1376 | struct intel_sdvo *intel_sdvo; | |
1377 | ||
1378 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1379 | intel_sdvo = enc_to_intel_sdvo(encoder); | |
1380 | if (intel_sdvo->base.type == INTEL_OUTPUT_ANALOG) { | |
1381 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1382 | if (encoder == intel_attached_encoder(connector)) | |
1383 | return connector; | |
1384 | } | |
1385 | } | |
1386 | } | |
1387 | return NULL; | |
1388 | } | |
1389 | ||
1390 | static int | |
1391 | intel_analog_is_connected(struct drm_device *dev) | |
1392 | { | |
1393 | struct drm_connector *analog_connector; | |
1394 | ||
1395 | analog_connector = intel_find_analog_connector(dev); | |
1396 | if (!analog_connector) | |
1397 | return false; | |
1398 | ||
1399 | if (analog_connector->funcs->detect(analog_connector) == | |
1400 | connector_status_disconnected) | |
1401 | return false; | |
1402 | ||
1403 | return true; | |
1404 | } | |
1405 | ||
1406 | enum drm_connector_status | |
1407 | intel_sdvo_hdmi_sink_detect(struct drm_connector *connector) | |
1408 | { | |
1409 | struct drm_encoder *encoder = intel_attached_encoder(connector); | |
1410 | struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); | |
1411 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); | |
1412 | enum drm_connector_status status = connector_status_connected; | |
1413 | struct edid *edid = NULL; | |
1414 | ||
1415 | edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus); | |
1416 | ||
1417 | /* This is only applied to SDVO cards with multiple outputs */ | |
1418 | if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { | |
1419 | uint8_t saved_ddc, temp_ddc; | |
1420 | saved_ddc = intel_sdvo->ddc_bus; | |
1421 | temp_ddc = intel_sdvo->ddc_bus >> 1; | |
1422 | /* | |
1423 | * Don't use the 1 as the argument of DDC bus switch to get | |
1424 | * the EDID. It is used for SDVO SPD ROM. | |
1425 | */ | |
1426 | while(temp_ddc > 1) { | |
1427 | intel_sdvo->ddc_bus = temp_ddc; | |
1428 | edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus); | |
1429 | if (edid) { | |
1430 | /* | |
1431 | * When we can get the EDID, maybe it is the | |
1432 | * correct DDC bus. Update it. | |
1433 | */ | |
1434 | intel_sdvo->ddc_bus = temp_ddc; | |
1435 | break; | |
1436 | } | |
1437 | temp_ddc >>= 1; | |
1438 | } | |
1439 | if (edid == NULL) | |
1440 | intel_sdvo->ddc_bus = saved_ddc; | |
1441 | } | |
1442 | /* when there is no edid and no monitor is connected with VGA | |
1443 | * port, try to use the CRT ddc to read the EDID for DVI-connector | |
1444 | */ | |
1445 | if (edid == NULL && intel_sdvo->analog_ddc_bus && | |
1446 | !intel_analog_is_connected(connector->dev)) | |
1447 | edid = drm_get_edid(connector, intel_sdvo->analog_ddc_bus); | |
1448 | ||
1449 | if (edid != NULL) { | |
1450 | bool is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); | |
1451 | bool need_digital = !!(intel_sdvo_connector->output_flag & SDVO_TMDS_MASK); | |
1452 | ||
1453 | /* DDC bus is shared, match EDID to connector type */ | |
1454 | if (is_digital && need_digital) | |
1455 | intel_sdvo->is_hdmi = drm_detect_hdmi_monitor(edid); | |
1456 | else if (is_digital != need_digital) | |
1457 | status = connector_status_disconnected; | |
1458 | ||
1459 | connector->display_info.raw_edid = NULL; | |
1460 | } else | |
1461 | status = connector_status_disconnected; | |
1462 | ||
1463 | kfree(edid); | |
1464 | ||
1465 | return status; | |
1466 | } | |
1467 | ||
1468 | static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector) | |
1469 | { | |
1470 | uint16_t response; | |
1471 | struct drm_encoder *encoder = intel_attached_encoder(connector); | |
1472 | struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); | |
1473 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); | |
1474 | enum drm_connector_status ret; | |
1475 | ||
1476 | if (!intel_sdvo_write_cmd(intel_sdvo, | |
1477 | SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0)) | |
1478 | return connector_status_unknown; | |
1479 | if (intel_sdvo->is_tv) { | |
1480 | /* add 30ms delay when the output type is SDVO-TV */ | |
1481 | mdelay(30); | |
1482 | } | |
1483 | if (!intel_sdvo_read_response(intel_sdvo, &response, 2)) | |
1484 | return connector_status_unknown; | |
1485 | ||
1486 | DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8); | |
1487 | ||
1488 | if (response == 0) | |
1489 | return connector_status_disconnected; | |
1490 | ||
1491 | intel_sdvo->attached_output = response; | |
1492 | ||
1493 | if ((intel_sdvo_connector->output_flag & response) == 0) | |
1494 | ret = connector_status_disconnected; | |
1495 | else if (response & SDVO_TMDS_MASK) | |
1496 | ret = intel_sdvo_hdmi_sink_detect(connector); | |
1497 | else | |
1498 | ret = connector_status_connected; | |
1499 | ||
1500 | /* May update encoder flag for like clock for SDVO TV, etc.*/ | |
1501 | if (ret == connector_status_connected) { | |
1502 | intel_sdvo->is_tv = false; | |
1503 | intel_sdvo->is_lvds = false; | |
1504 | intel_sdvo->base.needs_tv_clock = false; | |
1505 | ||
1506 | if (response & SDVO_TV_MASK) { | |
1507 | intel_sdvo->is_tv = true; | |
1508 | intel_sdvo->base.needs_tv_clock = true; | |
1509 | } | |
1510 | if (response & SDVO_LVDS_MASK) | |
1511 | intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; | |
1512 | } | |
1513 | ||
1514 | return ret; | |
1515 | } | |
1516 | ||
1517 | static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) | |
1518 | { | |
1519 | struct drm_encoder *encoder = intel_attached_encoder(connector); | |
1520 | struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); | |
1521 | int num_modes; | |
1522 | ||
1523 | /* set the bus switch and get the modes */ | |
1524 | num_modes = intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus); | |
1525 | ||
1526 | /* | |
1527 | * Mac mini hack. On this device, the DVI-I connector shares one DDC | |
1528 | * link between analog and digital outputs. So, if the regular SDVO | |
1529 | * DDC fails, check to see if the analog output is disconnected, in | |
1530 | * which case we'll look there for the digital DDC data. | |
1531 | */ | |
1532 | if (num_modes == 0 && | |
1533 | intel_sdvo->analog_ddc_bus && | |
1534 | !intel_analog_is_connected(connector->dev)) { | |
1535 | /* Switch to the analog ddc bus and try that | |
1536 | */ | |
1537 | (void) intel_ddc_get_modes(connector, intel_sdvo->analog_ddc_bus); | |
1538 | } | |
1539 | } | |
1540 | ||
1541 | /* | |
1542 | * Set of SDVO TV modes. | |
1543 | * Note! This is in reply order (see loop in get_tv_modes). | |
1544 | * XXX: all 60Hz refresh? | |
1545 | */ | |
1546 | struct drm_display_mode sdvo_tv_modes[] = { | |
1547 | { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, | |
1548 | 416, 0, 200, 201, 232, 233, 0, | |
1549 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
1550 | { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, | |
1551 | 416, 0, 240, 241, 272, 273, 0, | |
1552 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
1553 | { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, | |
1554 | 496, 0, 300, 301, 332, 333, 0, | |
1555 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
1556 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, | |
1557 | 736, 0, 350, 351, 382, 383, 0, | |
1558 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
1559 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, | |
1560 | 736, 0, 400, 401, 432, 433, 0, | |
1561 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
1562 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, | |
1563 | 736, 0, 480, 481, 512, 513, 0, | |
1564 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
1565 | { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, | |
1566 | 800, 0, 480, 481, 512, 513, 0, | |
1567 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
1568 | { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, | |
1569 | 800, 0, 576, 577, 608, 609, 0, | |
1570 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
1571 | { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, | |
1572 | 816, 0, 350, 351, 382, 383, 0, | |
1573 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
1574 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, | |
1575 | 816, 0, 400, 401, 432, 433, 0, | |
1576 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
1577 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, | |
1578 | 816, 0, 480, 481, 512, 513, 0, | |
1579 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
1580 | { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, | |
1581 | 816, 0, 540, 541, 572, 573, 0, | |
1582 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
1583 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, | |
1584 | 816, 0, 576, 577, 608, 609, 0, | |
1585 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
1586 | { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, | |
1587 | 864, 0, 576, 577, 608, 609, 0, | |
1588 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
1589 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, | |
1590 | 896, 0, 600, 601, 632, 633, 0, | |
1591 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
1592 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, | |
1593 | 928, 0, 624, 625, 656, 657, 0, | |
1594 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
1595 | { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, | |
1596 | 1016, 0, 766, 767, 798, 799, 0, | |
1597 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
1598 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, | |
1599 | 1120, 0, 768, 769, 800, 801, 0, | |
1600 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
1601 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, | |
1602 | 1376, 0, 1024, 1025, 1056, 1057, 0, | |
1603 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
1604 | }; | |
1605 | ||
1606 | static void intel_sdvo_get_tv_modes(struct drm_connector *connector) | |
1607 | { | |
1608 | struct drm_encoder *encoder = intel_attached_encoder(connector); | |
1609 | struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); | |
1610 | struct intel_sdvo_sdtv_resolution_request tv_res; | |
1611 | uint32_t reply = 0, format_map = 0; | |
1612 | int i; | |
1613 | ||
1614 | /* Read the list of supported input resolutions for the selected TV | |
1615 | * format. | |
1616 | */ | |
1617 | format_map = 1 << intel_sdvo->tv_format_index; | |
1618 | memcpy(&tv_res, &format_map, | |
1619 | min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); | |
1620 | ||
1621 | if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) | |
1622 | return; | |
1623 | ||
1624 | BUILD_BUG_ON(sizeof(tv_res) != 3); | |
1625 | if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, | |
1626 | &tv_res, sizeof(tv_res))) | |
1627 | return; | |
1628 | if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) | |
1629 | return; | |
1630 | ||
1631 | for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) | |
1632 | if (reply & (1 << i)) { | |
1633 | struct drm_display_mode *nmode; | |
1634 | nmode = drm_mode_duplicate(connector->dev, | |
1635 | &sdvo_tv_modes[i]); | |
1636 | if (nmode) | |
1637 | drm_mode_probed_add(connector, nmode); | |
1638 | } | |
1639 | } | |
1640 | ||
1641 | static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) | |
1642 | { | |
1643 | struct drm_encoder *encoder = intel_attached_encoder(connector); | |
1644 | struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); | |
1645 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
1646 | struct drm_display_mode *newmode; | |
1647 | ||
1648 | /* | |
1649 | * Attempt to get the mode list from DDC. | |
1650 | * Assume that the preferred modes are | |
1651 | * arranged in priority order. | |
1652 | */ | |
1653 | intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus); | |
1654 | if (list_empty(&connector->probed_modes) == false) | |
1655 | goto end; | |
1656 | ||
1657 | /* Fetch modes from VBT */ | |
1658 | if (dev_priv->sdvo_lvds_vbt_mode != NULL) { | |
1659 | newmode = drm_mode_duplicate(connector->dev, | |
1660 | dev_priv->sdvo_lvds_vbt_mode); | |
1661 | if (newmode != NULL) { | |
1662 | /* Guarantee the mode is preferred */ | |
1663 | newmode->type = (DRM_MODE_TYPE_PREFERRED | | |
1664 | DRM_MODE_TYPE_DRIVER); | |
1665 | drm_mode_probed_add(connector, newmode); | |
1666 | } | |
1667 | } | |
1668 | ||
1669 | end: | |
1670 | list_for_each_entry(newmode, &connector->probed_modes, head) { | |
1671 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { | |
1672 | intel_sdvo->sdvo_lvds_fixed_mode = | |
1673 | drm_mode_duplicate(connector->dev, newmode); | |
1674 | ||
1675 | drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode, | |
1676 | 0); | |
1677 | ||
1678 | intel_sdvo->is_lvds = true; | |
1679 | break; | |
1680 | } | |
1681 | } | |
1682 | ||
1683 | } | |
1684 | ||
1685 | static int intel_sdvo_get_modes(struct drm_connector *connector) | |
1686 | { | |
1687 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); | |
1688 | ||
1689 | if (IS_TV(intel_sdvo_connector)) | |
1690 | intel_sdvo_get_tv_modes(connector); | |
1691 | else if (IS_LVDS(intel_sdvo_connector)) | |
1692 | intel_sdvo_get_lvds_modes(connector); | |
1693 | else | |
1694 | intel_sdvo_get_ddc_modes(connector); | |
1695 | ||
1696 | return !list_empty(&connector->probed_modes); | |
1697 | } | |
1698 | ||
1699 | static void | |
1700 | intel_sdvo_destroy_enhance_property(struct drm_connector *connector) | |
1701 | { | |
1702 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); | |
1703 | struct drm_device *dev = connector->dev; | |
1704 | ||
1705 | if (intel_sdvo_connector->left) | |
1706 | drm_property_destroy(dev, intel_sdvo_connector->left); | |
1707 | if (intel_sdvo_connector->right) | |
1708 | drm_property_destroy(dev, intel_sdvo_connector->right); | |
1709 | if (intel_sdvo_connector->top) | |
1710 | drm_property_destroy(dev, intel_sdvo_connector->top); | |
1711 | if (intel_sdvo_connector->bottom) | |
1712 | drm_property_destroy(dev, intel_sdvo_connector->bottom); | |
1713 | if (intel_sdvo_connector->hpos) | |
1714 | drm_property_destroy(dev, intel_sdvo_connector->hpos); | |
1715 | if (intel_sdvo_connector->vpos) | |
1716 | drm_property_destroy(dev, intel_sdvo_connector->vpos); | |
1717 | if (intel_sdvo_connector->saturation) | |
1718 | drm_property_destroy(dev, intel_sdvo_connector->saturation); | |
1719 | if (intel_sdvo_connector->contrast) | |
1720 | drm_property_destroy(dev, intel_sdvo_connector->contrast); | |
1721 | if (intel_sdvo_connector->hue) | |
1722 | drm_property_destroy(dev, intel_sdvo_connector->hue); | |
1723 | if (intel_sdvo_connector->sharpness) | |
1724 | drm_property_destroy(dev, intel_sdvo_connector->sharpness); | |
1725 | if (intel_sdvo_connector->flicker_filter) | |
1726 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter); | |
1727 | if (intel_sdvo_connector->flicker_filter_2d) | |
1728 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d); | |
1729 | if (intel_sdvo_connector->flicker_filter_adaptive) | |
1730 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive); | |
1731 | if (intel_sdvo_connector->tv_luma_filter) | |
1732 | drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter); | |
1733 | if (intel_sdvo_connector->tv_chroma_filter) | |
1734 | drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter); | |
1735 | if (intel_sdvo_connector->dot_crawl) | |
1736 | drm_property_destroy(dev, intel_sdvo_connector->dot_crawl); | |
1737 | if (intel_sdvo_connector->brightness) | |
1738 | drm_property_destroy(dev, intel_sdvo_connector->brightness); | |
1739 | } | |
1740 | ||
1741 | static void intel_sdvo_destroy(struct drm_connector *connector) | |
1742 | { | |
1743 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); | |
1744 | ||
1745 | if (intel_sdvo_connector->tv_format) | |
1746 | drm_property_destroy(connector->dev, | |
1747 | intel_sdvo_connector->tv_format); | |
1748 | ||
1749 | intel_sdvo_destroy_enhance_property(connector); | |
1750 | drm_sysfs_connector_remove(connector); | |
1751 | drm_connector_cleanup(connector); | |
1752 | kfree(connector); | |
1753 | } | |
1754 | ||
1755 | static int | |
1756 | intel_sdvo_set_property(struct drm_connector *connector, | |
1757 | struct drm_property *property, | |
1758 | uint64_t val) | |
1759 | { | |
1760 | struct drm_encoder *encoder = intel_attached_encoder(connector); | |
1761 | struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); | |
1762 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); | |
1763 | uint16_t temp_value; | |
1764 | uint8_t cmd; | |
1765 | int ret; | |
1766 | ||
1767 | ret = drm_connector_property_set_value(connector, property, val); | |
1768 | if (ret) | |
1769 | return ret; | |
1770 | ||
1771 | #define CHECK_PROPERTY(name, NAME) \ | |
1772 | if (intel_sdvo_connector->name == property) { \ | |
1773 | if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ | |
1774 | if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ | |
1775 | cmd = SDVO_CMD_SET_##NAME; \ | |
1776 | intel_sdvo_connector->cur_##name = temp_value; \ | |
1777 | goto set_value; \ | |
1778 | } | |
1779 | ||
1780 | if (property == intel_sdvo_connector->tv_format) { | |
1781 | if (val >= TV_FORMAT_NUM) | |
1782 | return -EINVAL; | |
1783 | ||
1784 | if (intel_sdvo->tv_format_index == | |
1785 | intel_sdvo_connector->tv_format_supported[val]) | |
1786 | return 0; | |
1787 | ||
1788 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; | |
1789 | goto done; | |
1790 | } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { | |
1791 | temp_value = val; | |
1792 | if (intel_sdvo_connector->left == property) { | |
1793 | drm_connector_property_set_value(connector, | |
1794 | intel_sdvo_connector->right, val); | |
1795 | if (intel_sdvo_connector->left_margin == temp_value) | |
1796 | return 0; | |
1797 | ||
1798 | intel_sdvo_connector->left_margin = temp_value; | |
1799 | intel_sdvo_connector->right_margin = temp_value; | |
1800 | temp_value = intel_sdvo_connector->max_hscan - | |
1801 | intel_sdvo_connector->left_margin; | |
1802 | cmd = SDVO_CMD_SET_OVERSCAN_H; | |
1803 | goto set_value; | |
1804 | } else if (intel_sdvo_connector->right == property) { | |
1805 | drm_connector_property_set_value(connector, | |
1806 | intel_sdvo_connector->left, val); | |
1807 | if (intel_sdvo_connector->right_margin == temp_value) | |
1808 | return 0; | |
1809 | ||
1810 | intel_sdvo_connector->left_margin = temp_value; | |
1811 | intel_sdvo_connector->right_margin = temp_value; | |
1812 | temp_value = intel_sdvo_connector->max_hscan - | |
1813 | intel_sdvo_connector->left_margin; | |
1814 | cmd = SDVO_CMD_SET_OVERSCAN_H; | |
1815 | goto set_value; | |
1816 | } else if (intel_sdvo_connector->top == property) { | |
1817 | drm_connector_property_set_value(connector, | |
1818 | intel_sdvo_connector->bottom, val); | |
1819 | if (intel_sdvo_connector->top_margin == temp_value) | |
1820 | return 0; | |
1821 | ||
1822 | intel_sdvo_connector->top_margin = temp_value; | |
1823 | intel_sdvo_connector->bottom_margin = temp_value; | |
1824 | temp_value = intel_sdvo_connector->max_vscan - | |
1825 | intel_sdvo_connector->top_margin; | |
1826 | cmd = SDVO_CMD_SET_OVERSCAN_V; | |
1827 | goto set_value; | |
1828 | } else if (intel_sdvo_connector->bottom == property) { | |
1829 | drm_connector_property_set_value(connector, | |
1830 | intel_sdvo_connector->top, val); | |
1831 | if (intel_sdvo_connector->bottom_margin == temp_value) | |
1832 | return 0; | |
1833 | ||
1834 | intel_sdvo_connector->top_margin = temp_value; | |
1835 | intel_sdvo_connector->bottom_margin = temp_value; | |
1836 | temp_value = intel_sdvo_connector->max_vscan - | |
1837 | intel_sdvo_connector->top_margin; | |
1838 | cmd = SDVO_CMD_SET_OVERSCAN_V; | |
1839 | goto set_value; | |
1840 | } | |
1841 | CHECK_PROPERTY(hpos, HPOS) | |
1842 | CHECK_PROPERTY(vpos, VPOS) | |
1843 | CHECK_PROPERTY(saturation, SATURATION) | |
1844 | CHECK_PROPERTY(contrast, CONTRAST) | |
1845 | CHECK_PROPERTY(hue, HUE) | |
1846 | CHECK_PROPERTY(brightness, BRIGHTNESS) | |
1847 | CHECK_PROPERTY(sharpness, SHARPNESS) | |
1848 | CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) | |
1849 | CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) | |
1850 | CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) | |
1851 | CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) | |
1852 | CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) | |
1853 | CHECK_PROPERTY(dot_crawl, DOT_CRAWL) | |
1854 | } | |
1855 | ||
1856 | return -EINVAL; /* unknown property */ | |
1857 | ||
1858 | set_value: | |
1859 | if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) | |
1860 | return -EIO; | |
1861 | ||
1862 | ||
1863 | done: | |
1864 | if (encoder->crtc) { | |
1865 | struct drm_crtc *crtc = encoder->crtc; | |
1866 | ||
1867 | drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x, | |
1868 | crtc->y, crtc->fb); | |
1869 | } | |
1870 | ||
1871 | return 0; | |
1872 | #undef CHECK_PROPERTY | |
1873 | } | |
1874 | ||
1875 | static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = { | |
1876 | .dpms = intel_sdvo_dpms, | |
1877 | .mode_fixup = intel_sdvo_mode_fixup, | |
1878 | .prepare = intel_encoder_prepare, | |
1879 | .mode_set = intel_sdvo_mode_set, | |
1880 | .commit = intel_encoder_commit, | |
1881 | }; | |
1882 | ||
1883 | static const struct drm_connector_funcs intel_sdvo_connector_funcs = { | |
1884 | .dpms = drm_helper_connector_dpms, | |
1885 | .detect = intel_sdvo_detect, | |
1886 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1887 | .set_property = intel_sdvo_set_property, | |
1888 | .destroy = intel_sdvo_destroy, | |
1889 | }; | |
1890 | ||
1891 | static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { | |
1892 | .get_modes = intel_sdvo_get_modes, | |
1893 | .mode_valid = intel_sdvo_mode_valid, | |
1894 | .best_encoder = intel_attached_encoder, | |
1895 | }; | |
1896 | ||
1897 | static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) | |
1898 | { | |
1899 | struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); | |
1900 | ||
1901 | if (intel_sdvo->analog_ddc_bus) | |
1902 | intel_i2c_destroy(intel_sdvo->analog_ddc_bus); | |
1903 | ||
1904 | if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) | |
1905 | drm_mode_destroy(encoder->dev, | |
1906 | intel_sdvo->sdvo_lvds_fixed_mode); | |
1907 | ||
1908 | intel_encoder_destroy(encoder); | |
1909 | } | |
1910 | ||
1911 | static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { | |
1912 | .destroy = intel_sdvo_enc_destroy, | |
1913 | }; | |
1914 | ||
1915 | static void | |
1916 | intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) | |
1917 | { | |
1918 | uint16_t mask = 0; | |
1919 | unsigned int num_bits; | |
1920 | ||
1921 | /* Make a mask of outputs less than or equal to our own priority in the | |
1922 | * list. | |
1923 | */ | |
1924 | switch (sdvo->controlled_output) { | |
1925 | case SDVO_OUTPUT_LVDS1: | |
1926 | mask |= SDVO_OUTPUT_LVDS1; | |
1927 | case SDVO_OUTPUT_LVDS0: | |
1928 | mask |= SDVO_OUTPUT_LVDS0; | |
1929 | case SDVO_OUTPUT_TMDS1: | |
1930 | mask |= SDVO_OUTPUT_TMDS1; | |
1931 | case SDVO_OUTPUT_TMDS0: | |
1932 | mask |= SDVO_OUTPUT_TMDS0; | |
1933 | case SDVO_OUTPUT_RGB1: | |
1934 | mask |= SDVO_OUTPUT_RGB1; | |
1935 | case SDVO_OUTPUT_RGB0: | |
1936 | mask |= SDVO_OUTPUT_RGB0; | |
1937 | break; | |
1938 | } | |
1939 | ||
1940 | /* Count bits to find what number we are in the priority list. */ | |
1941 | mask &= sdvo->caps.output_flags; | |
1942 | num_bits = hweight16(mask); | |
1943 | /* If more than 3 outputs, default to DDC bus 3 for now. */ | |
1944 | if (num_bits > 3) | |
1945 | num_bits = 3; | |
1946 | ||
1947 | /* Corresponds to SDVO_CONTROL_BUS_DDCx */ | |
1948 | sdvo->ddc_bus = 1 << num_bits; | |
1949 | } | |
1950 | ||
1951 | /** | |
1952 | * Choose the appropriate DDC bus for control bus switch command for this | |
1953 | * SDVO output based on the controlled output. | |
1954 | * | |
1955 | * DDC bus number assignment is in a priority order of RGB outputs, then TMDS | |
1956 | * outputs, then LVDS outputs. | |
1957 | */ | |
1958 | static void | |
1959 | intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, | |
1960 | struct intel_sdvo *sdvo, u32 reg) | |
1961 | { | |
1962 | struct sdvo_device_mapping *mapping; | |
1963 | ||
1964 | if (IS_SDVOB(reg)) | |
1965 | mapping = &(dev_priv->sdvo_mappings[0]); | |
1966 | else | |
1967 | mapping = &(dev_priv->sdvo_mappings[1]); | |
1968 | ||
1969 | if (mapping->initialized) | |
1970 | sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); | |
1971 | else | |
1972 | intel_sdvo_guess_ddc_bus(sdvo); | |
1973 | } | |
1974 | ||
1975 | static bool | |
1976 | intel_sdvo_get_digital_encoding_mode(struct intel_sdvo *intel_sdvo, int device) | |
1977 | { | |
1978 | return intel_sdvo_set_target_output(intel_sdvo, | |
1979 | device == 0 ? SDVO_OUTPUT_TMDS0 : SDVO_OUTPUT_TMDS1) && | |
1980 | intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, | |
1981 | &intel_sdvo->is_hdmi, 1); | |
1982 | } | |
1983 | ||
1984 | static struct intel_sdvo * | |
1985 | intel_sdvo_chan_to_intel_sdvo(struct intel_i2c_chan *chan) | |
1986 | { | |
1987 | struct drm_device *dev = chan->drm_dev; | |
1988 | struct drm_encoder *encoder; | |
1989 | ||
1990 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1991 | struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); | |
1992 | if (intel_sdvo->base.ddc_bus == &chan->adapter) | |
1993 | return intel_sdvo; | |
1994 | } | |
1995 | ||
1996 | return NULL; | |
1997 | } | |
1998 | ||
1999 | static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap, | |
2000 | struct i2c_msg msgs[], int num) | |
2001 | { | |
2002 | struct intel_sdvo *intel_sdvo; | |
2003 | struct i2c_algo_bit_data *algo_data; | |
2004 | const struct i2c_algorithm *algo; | |
2005 | ||
2006 | algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data; | |
2007 | intel_sdvo = | |
2008 | intel_sdvo_chan_to_intel_sdvo((struct intel_i2c_chan *) | |
2009 | (algo_data->data)); | |
2010 | if (intel_sdvo == NULL) | |
2011 | return -EINVAL; | |
2012 | ||
2013 | algo = intel_sdvo->base.i2c_bus->algo; | |
2014 | ||
2015 | intel_sdvo_set_control_bus_switch(intel_sdvo, intel_sdvo->ddc_bus); | |
2016 | return algo->master_xfer(i2c_adap, msgs, num); | |
2017 | } | |
2018 | ||
2019 | static struct i2c_algorithm intel_sdvo_i2c_bit_algo = { | |
2020 | .master_xfer = intel_sdvo_master_xfer, | |
2021 | }; | |
2022 | ||
2023 | static u8 | |
2024 | intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg) | |
2025 | { | |
2026 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2027 | struct sdvo_device_mapping *my_mapping, *other_mapping; | |
2028 | ||
2029 | if (IS_SDVOB(sdvo_reg)) { | |
2030 | my_mapping = &dev_priv->sdvo_mappings[0]; | |
2031 | other_mapping = &dev_priv->sdvo_mappings[1]; | |
2032 | } else { | |
2033 | my_mapping = &dev_priv->sdvo_mappings[1]; | |
2034 | other_mapping = &dev_priv->sdvo_mappings[0]; | |
2035 | } | |
2036 | ||
2037 | /* If the BIOS described our SDVO device, take advantage of it. */ | |
2038 | if (my_mapping->slave_addr) | |
2039 | return my_mapping->slave_addr; | |
2040 | ||
2041 | /* If the BIOS only described a different SDVO device, use the | |
2042 | * address that it isn't using. | |
2043 | */ | |
2044 | if (other_mapping->slave_addr) { | |
2045 | if (other_mapping->slave_addr == 0x70) | |
2046 | return 0x72; | |
2047 | else | |
2048 | return 0x70; | |
2049 | } | |
2050 | ||
2051 | /* No SDVO device info is found for another DVO port, | |
2052 | * so use mapping assumption we had before BIOS parsing. | |
2053 | */ | |
2054 | if (IS_SDVOB(sdvo_reg)) | |
2055 | return 0x70; | |
2056 | else | |
2057 | return 0x72; | |
2058 | } | |
2059 | ||
2060 | static void | |
2061 | intel_sdvo_connector_init(struct drm_encoder *encoder, | |
2062 | struct drm_connector *connector) | |
2063 | { | |
2064 | drm_connector_init(encoder->dev, connector, &intel_sdvo_connector_funcs, | |
2065 | connector->connector_type); | |
2066 | ||
2067 | drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs); | |
2068 | ||
2069 | connector->interlace_allowed = 0; | |
2070 | connector->doublescan_allowed = 0; | |
2071 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
2072 | ||
2073 | drm_mode_connector_attach_encoder(connector, encoder); | |
2074 | drm_sysfs_connector_add(connector); | |
2075 | } | |
2076 | ||
2077 | static bool | |
2078 | intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) | |
2079 | { | |
2080 | struct drm_encoder *encoder = &intel_sdvo->base.enc; | |
2081 | struct drm_connector *connector; | |
2082 | struct intel_connector *intel_connector; | |
2083 | struct intel_sdvo_connector *intel_sdvo_connector; | |
2084 | ||
2085 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); | |
2086 | if (!intel_sdvo_connector) | |
2087 | return false; | |
2088 | ||
2089 | if (device == 0) { | |
2090 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; | |
2091 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; | |
2092 | } else if (device == 1) { | |
2093 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; | |
2094 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; | |
2095 | } | |
2096 | ||
2097 | intel_connector = &intel_sdvo_connector->base; | |
2098 | connector = &intel_connector->base; | |
2099 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; | |
2100 | encoder->encoder_type = DRM_MODE_ENCODER_TMDS; | |
2101 | connector->connector_type = DRM_MODE_CONNECTOR_DVID; | |
2102 | ||
2103 | if (intel_sdvo_get_supp_encode(intel_sdvo, &intel_sdvo->encode) | |
2104 | && intel_sdvo_get_digital_encoding_mode(intel_sdvo, device) | |
2105 | && intel_sdvo->is_hdmi) { | |
2106 | /* enable hdmi encoding mode if supported */ | |
2107 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); | |
2108 | intel_sdvo_set_colorimetry(intel_sdvo, | |
2109 | SDVO_COLORIMETRY_RGB256); | |
2110 | connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; | |
2111 | } | |
2112 | intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | | |
2113 | (1 << INTEL_ANALOG_CLONE_BIT)); | |
2114 | ||
2115 | intel_sdvo_connector_init(encoder, connector); | |
2116 | ||
2117 | return true; | |
2118 | } | |
2119 | ||
2120 | static bool | |
2121 | intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) | |
2122 | { | |
2123 | struct drm_encoder *encoder = &intel_sdvo->base.enc; | |
2124 | struct drm_connector *connector; | |
2125 | struct intel_connector *intel_connector; | |
2126 | struct intel_sdvo_connector *intel_sdvo_connector; | |
2127 | ||
2128 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); | |
2129 | if (!intel_sdvo_connector) | |
2130 | return false; | |
2131 | ||
2132 | intel_connector = &intel_sdvo_connector->base; | |
2133 | connector = &intel_connector->base; | |
2134 | encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; | |
2135 | connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; | |
2136 | ||
2137 | intel_sdvo->controlled_output |= type; | |
2138 | intel_sdvo_connector->output_flag = type; | |
2139 | ||
2140 | intel_sdvo->is_tv = true; | |
2141 | intel_sdvo->base.needs_tv_clock = true; | |
2142 | intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT; | |
2143 | ||
2144 | intel_sdvo_connector_init(encoder, connector); | |
2145 | ||
2146 | if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) | |
2147 | goto err; | |
2148 | ||
2149 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) | |
2150 | goto err; | |
2151 | ||
2152 | return true; | |
2153 | ||
2154 | err: | |
2155 | intel_sdvo_destroy_enhance_property(connector); | |
2156 | kfree(intel_sdvo_connector); | |
2157 | return false; | |
2158 | } | |
2159 | ||
2160 | static bool | |
2161 | intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) | |
2162 | { | |
2163 | struct drm_encoder *encoder = &intel_sdvo->base.enc; | |
2164 | struct drm_connector *connector; | |
2165 | struct intel_connector *intel_connector; | |
2166 | struct intel_sdvo_connector *intel_sdvo_connector; | |
2167 | ||
2168 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); | |
2169 | if (!intel_sdvo_connector) | |
2170 | return false; | |
2171 | ||
2172 | intel_connector = &intel_sdvo_connector->base; | |
2173 | connector = &intel_connector->base; | |
2174 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; | |
2175 | encoder->encoder_type = DRM_MODE_ENCODER_DAC; | |
2176 | connector->connector_type = DRM_MODE_CONNECTOR_VGA; | |
2177 | ||
2178 | if (device == 0) { | |
2179 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; | |
2180 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; | |
2181 | } else if (device == 1) { | |
2182 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; | |
2183 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; | |
2184 | } | |
2185 | ||
2186 | intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | | |
2187 | (1 << INTEL_ANALOG_CLONE_BIT)); | |
2188 | ||
2189 | intel_sdvo_connector_init(encoder, connector); | |
2190 | return true; | |
2191 | } | |
2192 | ||
2193 | static bool | |
2194 | intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) | |
2195 | { | |
2196 | struct drm_encoder *encoder = &intel_sdvo->base.enc; | |
2197 | struct drm_connector *connector; | |
2198 | struct intel_connector *intel_connector; | |
2199 | struct intel_sdvo_connector *intel_sdvo_connector; | |
2200 | ||
2201 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); | |
2202 | if (!intel_sdvo_connector) | |
2203 | return false; | |
2204 | ||
2205 | intel_connector = &intel_sdvo_connector->base; | |
2206 | connector = &intel_connector->base; | |
2207 | encoder->encoder_type = DRM_MODE_ENCODER_LVDS; | |
2208 | connector->connector_type = DRM_MODE_CONNECTOR_LVDS; | |
2209 | ||
2210 | if (device == 0) { | |
2211 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; | |
2212 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; | |
2213 | } else if (device == 1) { | |
2214 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; | |
2215 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; | |
2216 | } | |
2217 | ||
2218 | intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) | | |
2219 | (1 << INTEL_SDVO_LVDS_CLONE_BIT)); | |
2220 | ||
2221 | intel_sdvo_connector_init(encoder, connector); | |
2222 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) | |
2223 | goto err; | |
2224 | ||
2225 | return true; | |
2226 | ||
2227 | err: | |
2228 | intel_sdvo_destroy_enhance_property(connector); | |
2229 | kfree(intel_sdvo_connector); | |
2230 | return false; | |
2231 | } | |
2232 | ||
2233 | static bool | |
2234 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) | |
2235 | { | |
2236 | intel_sdvo->is_tv = false; | |
2237 | intel_sdvo->base.needs_tv_clock = false; | |
2238 | intel_sdvo->is_lvds = false; | |
2239 | ||
2240 | /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ | |
2241 | ||
2242 | if (flags & SDVO_OUTPUT_TMDS0) | |
2243 | if (!intel_sdvo_dvi_init(intel_sdvo, 0)) | |
2244 | return false; | |
2245 | ||
2246 | if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) | |
2247 | if (!intel_sdvo_dvi_init(intel_sdvo, 1)) | |
2248 | return false; | |
2249 | ||
2250 | /* TV has no XXX1 function block */ | |
2251 | if (flags & SDVO_OUTPUT_SVID0) | |
2252 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) | |
2253 | return false; | |
2254 | ||
2255 | if (flags & SDVO_OUTPUT_CVBS0) | |
2256 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) | |
2257 | return false; | |
2258 | ||
2259 | if (flags & SDVO_OUTPUT_RGB0) | |
2260 | if (!intel_sdvo_analog_init(intel_sdvo, 0)) | |
2261 | return false; | |
2262 | ||
2263 | if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) | |
2264 | if (!intel_sdvo_analog_init(intel_sdvo, 1)) | |
2265 | return false; | |
2266 | ||
2267 | if (flags & SDVO_OUTPUT_LVDS0) | |
2268 | if (!intel_sdvo_lvds_init(intel_sdvo, 0)) | |
2269 | return false; | |
2270 | ||
2271 | if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) | |
2272 | if (!intel_sdvo_lvds_init(intel_sdvo, 1)) | |
2273 | return false; | |
2274 | ||
2275 | if ((flags & SDVO_OUTPUT_MASK) == 0) { | |
2276 | unsigned char bytes[2]; | |
2277 | ||
2278 | intel_sdvo->controlled_output = 0; | |
2279 | memcpy(bytes, &intel_sdvo->caps.output_flags, 2); | |
2280 | DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", | |
2281 | SDVO_NAME(intel_sdvo), | |
2282 | bytes[0], bytes[1]); | |
2283 | return false; | |
2284 | } | |
2285 | intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1); | |
2286 | ||
2287 | return true; | |
2288 | } | |
2289 | ||
2290 | static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, | |
2291 | struct intel_sdvo_connector *intel_sdvo_connector, | |
2292 | int type) | |
2293 | { | |
2294 | struct drm_device *dev = intel_sdvo->base.enc.dev; | |
2295 | struct intel_sdvo_tv_format format; | |
2296 | uint32_t format_map, i; | |
2297 | ||
2298 | if (!intel_sdvo_set_target_output(intel_sdvo, type)) | |
2299 | return false; | |
2300 | ||
2301 | if (!intel_sdvo_get_value(intel_sdvo, | |
2302 | SDVO_CMD_GET_SUPPORTED_TV_FORMATS, | |
2303 | &format, sizeof(format))) | |
2304 | return false; | |
2305 | ||
2306 | memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); | |
2307 | ||
2308 | if (format_map == 0) | |
2309 | return false; | |
2310 | ||
2311 | intel_sdvo_connector->format_supported_num = 0; | |
2312 | for (i = 0 ; i < TV_FORMAT_NUM; i++) | |
2313 | if (format_map & (1 << i)) | |
2314 | intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; | |
2315 | ||
2316 | ||
2317 | intel_sdvo_connector->tv_format = | |
2318 | drm_property_create(dev, DRM_MODE_PROP_ENUM, | |
2319 | "mode", intel_sdvo_connector->format_supported_num); | |
2320 | if (!intel_sdvo_connector->tv_format) | |
2321 | return false; | |
2322 | ||
2323 | for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) | |
2324 | drm_property_add_enum( | |
2325 | intel_sdvo_connector->tv_format, i, | |
2326 | i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); | |
2327 | ||
2328 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; | |
2329 | drm_connector_attach_property(&intel_sdvo_connector->base.base, | |
2330 | intel_sdvo_connector->tv_format, 0); | |
2331 | return true; | |
2332 | ||
2333 | } | |
2334 | ||
2335 | #define ENHANCEMENT(name, NAME) do { \ | |
2336 | if (enhancements.name) { \ | |
2337 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ | |
2338 | !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ | |
2339 | return false; \ | |
2340 | intel_sdvo_connector->max_##name = data_value[0]; \ | |
2341 | intel_sdvo_connector->cur_##name = response; \ | |
2342 | intel_sdvo_connector->name = \ | |
2343 | drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \ | |
2344 | if (!intel_sdvo_connector->name) return false; \ | |
2345 | intel_sdvo_connector->name->values[0] = 0; \ | |
2346 | intel_sdvo_connector->name->values[1] = data_value[0]; \ | |
2347 | drm_connector_attach_property(connector, \ | |
2348 | intel_sdvo_connector->name, \ | |
2349 | intel_sdvo_connector->cur_##name); \ | |
2350 | DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ | |
2351 | data_value[0], data_value[1], response); \ | |
2352 | } \ | |
2353 | } while(0) | |
2354 | ||
2355 | static bool | |
2356 | intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, | |
2357 | struct intel_sdvo_connector *intel_sdvo_connector, | |
2358 | struct intel_sdvo_enhancements_reply enhancements) | |
2359 | { | |
2360 | struct drm_device *dev = intel_sdvo->base.enc.dev; | |
2361 | struct drm_connector *connector = &intel_sdvo_connector->base.base; | |
2362 | uint16_t response, data_value[2]; | |
2363 | ||
2364 | /* when horizontal overscan is supported, Add the left/right property */ | |
2365 | if (enhancements.overscan_h) { | |
2366 | if (!intel_sdvo_get_value(intel_sdvo, | |
2367 | SDVO_CMD_GET_MAX_OVERSCAN_H, | |
2368 | &data_value, 4)) | |
2369 | return false; | |
2370 | ||
2371 | if (!intel_sdvo_get_value(intel_sdvo, | |
2372 | SDVO_CMD_GET_OVERSCAN_H, | |
2373 | &response, 2)) | |
2374 | return false; | |
2375 | ||
2376 | intel_sdvo_connector->max_hscan = data_value[0]; | |
2377 | intel_sdvo_connector->left_margin = data_value[0] - response; | |
2378 | intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; | |
2379 | intel_sdvo_connector->left = | |
2380 | drm_property_create(dev, DRM_MODE_PROP_RANGE, | |
2381 | "left_margin", 2); | |
2382 | if (!intel_sdvo_connector->left) | |
2383 | return false; | |
2384 | ||
2385 | intel_sdvo_connector->left->values[0] = 0; | |
2386 | intel_sdvo_connector->left->values[1] = data_value[0]; | |
2387 | drm_connector_attach_property(connector, | |
2388 | intel_sdvo_connector->left, | |
2389 | intel_sdvo_connector->left_margin); | |
2390 | ||
2391 | intel_sdvo_connector->right = | |
2392 | drm_property_create(dev, DRM_MODE_PROP_RANGE, | |
2393 | "right_margin", 2); | |
2394 | if (!intel_sdvo_connector->right) | |
2395 | return false; | |
2396 | ||
2397 | intel_sdvo_connector->right->values[0] = 0; | |
2398 | intel_sdvo_connector->right->values[1] = data_value[0]; | |
2399 | drm_connector_attach_property(connector, | |
2400 | intel_sdvo_connector->right, | |
2401 | intel_sdvo_connector->right_margin); | |
2402 | DRM_DEBUG_KMS("h_overscan: max %d, " | |
2403 | "default %d, current %d\n", | |
2404 | data_value[0], data_value[1], response); | |
2405 | } | |
2406 | ||
2407 | if (enhancements.overscan_v) { | |
2408 | if (!intel_sdvo_get_value(intel_sdvo, | |
2409 | SDVO_CMD_GET_MAX_OVERSCAN_V, | |
2410 | &data_value, 4)) | |
2411 | return false; | |
2412 | ||
2413 | if (!intel_sdvo_get_value(intel_sdvo, | |
2414 | SDVO_CMD_GET_OVERSCAN_V, | |
2415 | &response, 2)) | |
2416 | return false; | |
2417 | ||
2418 | intel_sdvo_connector->max_vscan = data_value[0]; | |
2419 | intel_sdvo_connector->top_margin = data_value[0] - response; | |
2420 | intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; | |
2421 | intel_sdvo_connector->top = | |
2422 | drm_property_create(dev, DRM_MODE_PROP_RANGE, | |
2423 | "top_margin", 2); | |
2424 | if (!intel_sdvo_connector->top) | |
2425 | return false; | |
2426 | ||
2427 | intel_sdvo_connector->top->values[0] = 0; | |
2428 | intel_sdvo_connector->top->values[1] = data_value[0]; | |
2429 | drm_connector_attach_property(connector, | |
2430 | intel_sdvo_connector->top, | |
2431 | intel_sdvo_connector->top_margin); | |
2432 | ||
2433 | intel_sdvo_connector->bottom = | |
2434 | drm_property_create(dev, DRM_MODE_PROP_RANGE, | |
2435 | "bottom_margin", 2); | |
2436 | if (!intel_sdvo_connector->bottom) | |
2437 | return false; | |
2438 | ||
2439 | intel_sdvo_connector->bottom->values[0] = 0; | |
2440 | intel_sdvo_connector->bottom->values[1] = data_value[0]; | |
2441 | drm_connector_attach_property(connector, | |
2442 | intel_sdvo_connector->bottom, | |
2443 | intel_sdvo_connector->bottom_margin); | |
2444 | DRM_DEBUG_KMS("v_overscan: max %d, " | |
2445 | "default %d, current %d\n", | |
2446 | data_value[0], data_value[1], response); | |
2447 | } | |
2448 | ||
2449 | ENHANCEMENT(hpos, HPOS); | |
2450 | ENHANCEMENT(vpos, VPOS); | |
2451 | ENHANCEMENT(saturation, SATURATION); | |
2452 | ENHANCEMENT(contrast, CONTRAST); | |
2453 | ENHANCEMENT(hue, HUE); | |
2454 | ENHANCEMENT(sharpness, SHARPNESS); | |
2455 | ENHANCEMENT(brightness, BRIGHTNESS); | |
2456 | ENHANCEMENT(flicker_filter, FLICKER_FILTER); | |
2457 | ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); | |
2458 | ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); | |
2459 | ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); | |
2460 | ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); | |
2461 | ||
2462 | if (enhancements.dot_crawl) { | |
2463 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) | |
2464 | return false; | |
2465 | ||
2466 | intel_sdvo_connector->max_dot_crawl = 1; | |
2467 | intel_sdvo_connector->cur_dot_crawl = response & 0x1; | |
2468 | intel_sdvo_connector->dot_crawl = | |
2469 | drm_property_create(dev, DRM_MODE_PROP_RANGE, "dot_crawl", 2); | |
2470 | if (!intel_sdvo_connector->dot_crawl) | |
2471 | return false; | |
2472 | ||
2473 | intel_sdvo_connector->dot_crawl->values[0] = 0; | |
2474 | intel_sdvo_connector->dot_crawl->values[1] = 1; | |
2475 | drm_connector_attach_property(connector, | |
2476 | intel_sdvo_connector->dot_crawl, | |
2477 | intel_sdvo_connector->cur_dot_crawl); | |
2478 | DRM_DEBUG_KMS("dot crawl: current %d\n", response); | |
2479 | } | |
2480 | ||
2481 | return true; | |
2482 | } | |
2483 | ||
2484 | static bool | |
2485 | intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, | |
2486 | struct intel_sdvo_connector *intel_sdvo_connector, | |
2487 | struct intel_sdvo_enhancements_reply enhancements) | |
2488 | { | |
2489 | struct drm_device *dev = intel_sdvo->base.enc.dev; | |
2490 | struct drm_connector *connector = &intel_sdvo_connector->base.base; | |
2491 | uint16_t response, data_value[2]; | |
2492 | ||
2493 | ENHANCEMENT(brightness, BRIGHTNESS); | |
2494 | ||
2495 | return true; | |
2496 | } | |
2497 | #undef ENHANCEMENT | |
2498 | ||
2499 | static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, | |
2500 | struct intel_sdvo_connector *intel_sdvo_connector) | |
2501 | { | |
2502 | union { | |
2503 | struct intel_sdvo_enhancements_reply reply; | |
2504 | uint16_t response; | |
2505 | } enhancements; | |
2506 | ||
2507 | if (!intel_sdvo_get_value(intel_sdvo, | |
2508 | SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, | |
2509 | &enhancements, sizeof(enhancements))) | |
2510 | return false; | |
2511 | ||
2512 | if (enhancements.response == 0) { | |
2513 | DRM_DEBUG_KMS("No enhancement is supported\n"); | |
2514 | return true; | |
2515 | } | |
2516 | ||
2517 | if (IS_TV(intel_sdvo_connector)) | |
2518 | return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); | |
2519 | else if(IS_LVDS(intel_sdvo_connector)) | |
2520 | return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); | |
2521 | else | |
2522 | return true; | |
2523 | ||
2524 | } | |
2525 | ||
2526 | bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg) | |
2527 | { | |
2528 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2529 | struct intel_encoder *intel_encoder; | |
2530 | struct intel_sdvo *intel_sdvo; | |
2531 | u8 ch[0x40]; | |
2532 | int i; | |
2533 | u32 i2c_reg, ddc_reg, analog_ddc_reg; | |
2534 | ||
2535 | intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL); | |
2536 | if (!intel_sdvo) | |
2537 | return false; | |
2538 | ||
2539 | intel_sdvo->sdvo_reg = sdvo_reg; | |
2540 | ||
2541 | intel_encoder = &intel_sdvo->base; | |
2542 | intel_encoder->type = INTEL_OUTPUT_SDVO; | |
2543 | ||
2544 | if (HAS_PCH_SPLIT(dev)) { | |
2545 | i2c_reg = PCH_GPIOE; | |
2546 | ddc_reg = PCH_GPIOE; | |
2547 | analog_ddc_reg = PCH_GPIOA; | |
2548 | } else { | |
2549 | i2c_reg = GPIOE; | |
2550 | ddc_reg = GPIOE; | |
2551 | analog_ddc_reg = GPIOA; | |
2552 | } | |
2553 | ||
2554 | /* setup the DDC bus. */ | |
2555 | if (IS_SDVOB(sdvo_reg)) | |
2556 | intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOB"); | |
2557 | else | |
2558 | intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOC"); | |
2559 | ||
2560 | if (!intel_encoder->i2c_bus) | |
2561 | goto err_inteloutput; | |
2562 | ||
2563 | intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg); | |
2564 | ||
2565 | /* Save the bit-banging i2c functionality for use by the DDC wrapper */ | |
2566 | intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality; | |
2567 | ||
2568 | /* Read the regs to test if we can talk to the device */ | |
2569 | for (i = 0; i < 0x40; i++) { | |
2570 | if (!intel_sdvo_read_byte(intel_sdvo, i, &ch[i])) { | |
2571 | DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n", | |
2572 | IS_SDVOB(sdvo_reg) ? 'B' : 'C'); | |
2573 | goto err_i2c; | |
2574 | } | |
2575 | } | |
2576 | ||
2577 | /* setup the DDC bus. */ | |
2578 | if (IS_SDVOB(sdvo_reg)) { | |
2579 | intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOB DDC BUS"); | |
2580 | intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg, | |
2581 | "SDVOB/VGA DDC BUS"); | |
2582 | dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS; | |
2583 | } else { | |
2584 | intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOC DDC BUS"); | |
2585 | intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg, | |
2586 | "SDVOC/VGA DDC BUS"); | |
2587 | dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS; | |
2588 | } | |
2589 | if (intel_encoder->ddc_bus == NULL || intel_sdvo->analog_ddc_bus == NULL) | |
2590 | goto err_i2c; | |
2591 | ||
2592 | /* Wrap with our custom algo which switches to DDC mode */ | |
2593 | intel_encoder->ddc_bus->algo = &intel_sdvo_i2c_bit_algo; | |
2594 | ||
2595 | /* encoder type will be decided later */ | |
2596 | drm_encoder_init(dev, &intel_encoder->enc, &intel_sdvo_enc_funcs, 0); | |
2597 | drm_encoder_helper_add(&intel_encoder->enc, &intel_sdvo_helper_funcs); | |
2598 | ||
2599 | /* In default case sdvo lvds is false */ | |
2600 | if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) | |
2601 | goto err_enc; | |
2602 | ||
2603 | if (intel_sdvo_output_setup(intel_sdvo, | |
2604 | intel_sdvo->caps.output_flags) != true) { | |
2605 | DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n", | |
2606 | IS_SDVOB(sdvo_reg) ? 'B' : 'C'); | |
2607 | goto err_enc; | |
2608 | } | |
2609 | ||
2610 | intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg); | |
2611 | ||
2612 | /* Set the input timing to the screen. Assume always input 0. */ | |
2613 | if (!intel_sdvo_set_target_input(intel_sdvo)) | |
2614 | goto err_enc; | |
2615 | ||
2616 | if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, | |
2617 | &intel_sdvo->pixel_clock_min, | |
2618 | &intel_sdvo->pixel_clock_max)) | |
2619 | goto err_enc; | |
2620 | ||
2621 | DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " | |
2622 | "clock range %dMHz - %dMHz, " | |
2623 | "input 1: %c, input 2: %c, " | |
2624 | "output 1: %c, output 2: %c\n", | |
2625 | SDVO_NAME(intel_sdvo), | |
2626 | intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, | |
2627 | intel_sdvo->caps.device_rev_id, | |
2628 | intel_sdvo->pixel_clock_min / 1000, | |
2629 | intel_sdvo->pixel_clock_max / 1000, | |
2630 | (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', | |
2631 | (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', | |
2632 | /* check currently supported outputs */ | |
2633 | intel_sdvo->caps.output_flags & | |
2634 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', | |
2635 | intel_sdvo->caps.output_flags & | |
2636 | (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); | |
2637 | return true; | |
2638 | ||
2639 | err_enc: | |
2640 | drm_encoder_cleanup(&intel_encoder->enc); | |
2641 | err_i2c: | |
2642 | if (intel_sdvo->analog_ddc_bus != NULL) | |
2643 | intel_i2c_destroy(intel_sdvo->analog_ddc_bus); | |
2644 | if (intel_encoder->ddc_bus != NULL) | |
2645 | intel_i2c_destroy(intel_encoder->ddc_bus); | |
2646 | if (intel_encoder->i2c_bus != NULL) | |
2647 | intel_i2c_destroy(intel_encoder->i2c_bus); | |
2648 | err_inteloutput: | |
2649 | kfree(intel_sdvo); | |
2650 | ||
2651 | return false; | |
2652 | } |