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1 | /* | |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs <bskeggs@redhat.com> | |
23 | */ | |
24 | ||
25 | #include "drmP.h" | |
26 | #include "nouveau_drv.h" | |
27 | #include "nouveau_dma.h" | |
28 | #include "nouveau_ramht.h" | |
29 | #include "nouveau_fence.h" | |
30 | ||
31 | struct nv10_fence_chan { | |
32 | struct nouveau_fence_chan base; | |
33 | }; | |
34 | ||
35 | struct nv10_fence_priv { | |
36 | struct nouveau_fence_priv base; | |
37 | struct nouveau_bo *bo; | |
38 | spinlock_t lock; | |
39 | u32 sequence; | |
40 | }; | |
41 | ||
42 | static int | |
43 | nv10_fence_emit(struct nouveau_fence *fence) | |
44 | { | |
45 | struct nouveau_channel *chan = fence->channel; | |
46 | int ret = RING_SPACE(chan, 2); | |
47 | if (ret == 0) { | |
48 | BEGIN_NV04(chan, 0, NV10_SUBCHAN_REF_CNT, 1); | |
49 | OUT_RING (chan, fence->sequence); | |
50 | FIRE_RING (chan); | |
51 | } | |
52 | return ret; | |
53 | } | |
54 | ||
55 | static int | |
56 | nv10_fence_sync(struct nouveau_fence *fence, struct nouveau_channel *chan) | |
57 | { | |
58 | return -ENODEV; | |
59 | } | |
60 | ||
61 | static int | |
62 | nv17_fence_sync(struct nouveau_fence *fence, struct nouveau_channel *chan) | |
63 | { | |
64 | struct nv10_fence_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_FENCE); | |
65 | struct nouveau_channel *prev = fence->channel; | |
66 | u32 value; | |
67 | int ret; | |
68 | ||
69 | if (!mutex_trylock(&prev->mutex)) | |
70 | return -EBUSY; | |
71 | ||
72 | spin_lock(&priv->lock); | |
73 | value = priv->sequence; | |
74 | priv->sequence += 2; | |
75 | spin_unlock(&priv->lock); | |
76 | ||
77 | ret = RING_SPACE(prev, 5); | |
78 | if (!ret) { | |
79 | BEGIN_NV04(prev, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4); | |
80 | OUT_RING (prev, NvSema); | |
81 | OUT_RING (prev, 0); | |
82 | OUT_RING (prev, value + 0); | |
83 | OUT_RING (prev, value + 1); | |
84 | FIRE_RING (prev); | |
85 | } | |
86 | ||
87 | if (!ret && !(ret = RING_SPACE(chan, 5))) { | |
88 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4); | |
89 | OUT_RING (chan, NvSema); | |
90 | OUT_RING (chan, 0); | |
91 | OUT_RING (chan, value + 1); | |
92 | OUT_RING (chan, value + 2); | |
93 | FIRE_RING (chan); | |
94 | } | |
95 | ||
96 | mutex_unlock(&prev->mutex); | |
97 | return 0; | |
98 | } | |
99 | ||
100 | static u32 | |
101 | nv10_fence_read(struct nouveau_channel *chan) | |
102 | { | |
103 | return nvchan_rd32(chan, 0x0048); | |
104 | } | |
105 | ||
106 | static void | |
107 | nv10_fence_context_del(struct nouveau_channel *chan, int engine) | |
108 | { | |
109 | struct nv10_fence_chan *fctx = chan->engctx[engine]; | |
110 | nouveau_fence_context_del(&fctx->base); | |
111 | chan->engctx[engine] = NULL; | |
112 | kfree(fctx); | |
113 | } | |
114 | ||
115 | static int | |
116 | nv10_fence_context_new(struct nouveau_channel *chan, int engine) | |
117 | { | |
118 | struct nv10_fence_priv *priv = nv_engine(chan->dev, engine); | |
119 | struct nv10_fence_chan *fctx; | |
120 | struct nouveau_gpuobj *obj; | |
121 | int ret = 0; | |
122 | ||
123 | fctx = chan->engctx[engine] = kzalloc(sizeof(*fctx), GFP_KERNEL); | |
124 | if (!fctx) | |
125 | return -ENOMEM; | |
126 | ||
127 | nouveau_fence_context_new(&fctx->base); | |
128 | ||
129 | if (priv->bo) { | |
130 | struct ttm_mem_reg *mem = &priv->bo->bo.mem; | |
131 | ||
132 | ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_FROM_MEMORY, | |
133 | mem->start * PAGE_SIZE, mem->size, | |
134 | NV_MEM_ACCESS_RW, | |
135 | NV_MEM_TARGET_VRAM, &obj); | |
136 | if (!ret) { | |
137 | ret = nouveau_ramht_insert(chan, NvSema, obj); | |
138 | nouveau_gpuobj_ref(NULL, &obj); | |
139 | } | |
140 | } | |
141 | ||
142 | if (ret) | |
143 | nv10_fence_context_del(chan, engine); | |
144 | return ret; | |
145 | } | |
146 | ||
147 | static int | |
148 | nv10_fence_fini(struct drm_device *dev, int engine, bool suspend) | |
149 | { | |
150 | return 0; | |
151 | } | |
152 | ||
153 | static int | |
154 | nv10_fence_init(struct drm_device *dev, int engine) | |
155 | { | |
156 | return 0; | |
157 | } | |
158 | ||
159 | static void | |
160 | nv10_fence_destroy(struct drm_device *dev, int engine) | |
161 | { | |
162 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
163 | struct nv10_fence_priv *priv = nv_engine(dev, engine); | |
164 | ||
165 | nouveau_bo_ref(NULL, &priv->bo); | |
166 | dev_priv->eng[engine] = NULL; | |
167 | kfree(priv); | |
168 | } | |
169 | ||
170 | int | |
171 | nv10_fence_create(struct drm_device *dev) | |
172 | { | |
173 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
174 | struct nv10_fence_priv *priv; | |
175 | int ret = 0; | |
176 | ||
177 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
178 | if (!priv) | |
179 | return -ENOMEM; | |
180 | ||
181 | priv->base.engine.destroy = nv10_fence_destroy; | |
182 | priv->base.engine.init = nv10_fence_init; | |
183 | priv->base.engine.fini = nv10_fence_fini; | |
184 | priv->base.engine.context_new = nv10_fence_context_new; | |
185 | priv->base.engine.context_del = nv10_fence_context_del; | |
186 | priv->base.emit = nv10_fence_emit; | |
187 | priv->base.read = nv10_fence_read; | |
188 | priv->base.sync = nv10_fence_sync; | |
189 | dev_priv->eng[NVOBJ_ENGINE_FENCE] = &priv->base.engine; | |
190 | spin_lock_init(&priv->lock); | |
191 | ||
192 | if (dev_priv->chipset >= 0x17) { | |
193 | ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM, | |
194 | 0, 0x0000, NULL, &priv->bo); | |
195 | if (!ret) { | |
196 | ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM); | |
197 | if (!ret) | |
198 | ret = nouveau_bo_map(priv->bo); | |
199 | if (ret) | |
200 | nouveau_bo_ref(NULL, &priv->bo); | |
201 | } | |
202 | ||
203 | if (ret == 0) { | |
204 | nouveau_bo_wr32(priv->bo, 0x000, 0x00000000); | |
205 | priv->base.sync = nv17_fence_sync; | |
206 | } | |
207 | } | |
208 | ||
209 | if (ret) | |
210 | nv10_fence_destroy(dev, NVOBJ_ENGINE_FENCE); | |
211 | return ret; | |
212 | } |